From: Ingo Molnar Date: Tue, 23 Dec 2008 15:27:23 +0000 (+0100) Subject: Merge branches 'x86/apic', 'x86/cleanups', 'x86/cpufeature', 'x86/crashdump', 'x86... X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=fa623d1b0222adbe8f822e53c08003b9679a410c;hp=7a9787e1eba95a166265e6a260cf30af04ef0a99;p=deliverable%2Flinux.git Merge branches 'x86/apic', 'x86/cleanups', 'x86/cpufeature', 'x86/crashdump', 'x86/debug', 'x86/defconfig', 'x86/detect-hyper', 'x86/doc', 'x86/dumpstack', 'x86/early-printk', 'x86/fpu', 'x86/idle', 'x86/io', 'x86/memory-corruption-check', 'x86/microcode', 'x86/mm', 'x86/mtrr', 'x86/nmi-watchdog', 'x86/pat2', 'x86/pci-ioapic-boot-irq-quirks', 'x86/ptrace', 'x86/quirks', 'x86/reboot', 'x86/setup-memory', 'x86/signal', 'x86/sparse-fixes', 'x86/time', 'x86/uv' and 'x86/xen' into x86/core --- diff --git a/.mailmap b/.mailmap index eba9bf953ef5..97f7b4fb6139 100644 --- a/.mailmap +++ b/.mailmap @@ -80,6 +80,8 @@ Nguyen Anh Quynh Paolo 'Blaisorblade' Giarrusso Patrick Mochel Peter A Jonsson +Peter Oruba +Peter Oruba Praveen BP Rajesh Shah Ralf Baechle diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index 7286ad090db7..2a39aeba1464 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -42,14 +42,8 @@ IRQ.txt - description of what an IRQ is. ManagementStyle - how to (attempt to) manage kernel hackers. -MSI-HOWTO.txt - - the Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ. RCU/ - directory with info on RCU (read-copy update). -README.DAC960 - - info on Mylex DAC960/DAC1100 PCI RAID Controller Driver for Linux. -README.cycladesZ - - info on Cyclades-Z firmware loading. SAK.txt - info on Secure Attention Keys. SM501.txt @@ -86,20 +80,16 @@ blackfin/ - directory with documentation for the Blackfin arch. block/ - info on the Block I/O (BIO) layer. +blockdev/ + - info on block devices & drivers cachetlb.txt - describes the cache/TLB flushing interfaces Linux uses. -cciss.txt - - info, major/minor #'s for Compaq's SMART Array Controllers. cdrom/ - directory with information on the CD-ROM drivers that Linux has. -computone.txt - - info on Computone Intelliport II/Plus Multiport Serial Driver. connector/ - docs on the netlink based userspace<->kernel space communication mod. console/ - documentation on Linux console drivers. -cpqarray.txt - - info on using Compaq's SMART2 Intelligent Disk Array Controllers. cpu-freq/ - info on CPU frequency and voltage scaling. cpu-hotplug.txt @@ -126,8 +116,6 @@ device-mapper/ - directory with info on Device Mapper. devices.txt - plain ASCII listing of all the nodes in /dev/ with major minor #'s. -digiepca.txt - - info on Digi Intl. {PC,PCI,EISA}Xx and Xem series cards. dontdiff - file containing a list of files that should never be diff'ed. driver-model/ @@ -152,14 +140,10 @@ filesystems/ - info on the vfs and the various filesystems that Linux supports. firmware_class/ - request_firmware() hotplug interface info. -floppy.txt - - notes and driver options for the floppy disk driver. frv/ - Fujitsu FR-V Linux documentation. gpio.txt - overview of GPIO (General Purpose Input/Output) access conventions. -hayes-esp.txt - - info on using the Hayes ESP serial driver. highuid.txt - notes on the change from 16 bit to 32 bit user/group IDs. timers/ @@ -172,7 +156,7 @@ i2c/ - directory with info about the I2C bus/protocol (2 wire, kHz speed). i2o/ - directory with info about the Linux I2O subsystem. -i386/ +x86/i386/ - directory with info about Linux on Intel 32 bit architecture. ia64/ - directory with info about Linux on Intel 64 bit architecture. @@ -186,8 +170,6 @@ io_ordering.txt - info on ordering I/O writes to memory-mapped addresses. ioctl/ - directory with documents describing various IOCTL calls. -ioctl-number.txt - - how to implement and register device/driver ioctl calls. iostats.txt - info on I/O statistics Linux kernel provides. irqflags-tracing.txt @@ -250,14 +232,10 @@ mips/ - directory with info about Linux on MIPS architecture. mono.txt - how to execute Mono-based .NET binaries with the help of BINFMT_MISC. -moxa-smartio - - file with info on installing/using Moxa multiport serial driver. mutex-design.txt - info on the generic mutex subsystem. namespaces/ - directory with various information about namespaces -nbd.txt - - info on a TCP implementation of a network block device. netlabel/ - directory with information on the NetLabel subsystem. networking/ @@ -270,8 +248,6 @@ numastat.txt - info on how to read Numa policy hit/miss statistics in sysfs. oops-tracing.txt - how to decode those nasty internal kernel error dump messages. -paride.txt - - information about the parallel port IDE subsystem. parisc/ - directory with info on using Linux on PA-RISC architecture. parport.txt @@ -290,20 +266,16 @@ powerpc/ - directory with info on using Linux with the PowerPC. preempt-locking.txt - info on locking under a preemptive kernel. +printk-formats.txt + - how to get printk format specifiers right prio_tree.txt - info on radix-priority-search-tree use for indexing vmas. -ramdisk.txt - - short guide on how to set up and use the RAM disk. rbtree.txt - info on what red-black trees are and what they are for. -riscom8.txt - - notes on using the RISCom/8 multi-port serial driver. robust-futex-ABI.txt - documentation of the robust futex ABI. robust-futexes.txt - a description of what robust futexes are. -rocket.txt - - info on the Comtrol RocketPort multiport serial driver. rt-mutex-design.txt - description of the RealTime mutex implementation design. rt-mutex.txt @@ -332,8 +304,6 @@ sparc/ - directory with info on using Linux on Sparc architecture. sparse.txt - info on how to obtain and use the sparse tool for typechecking. -specialix.txt - - info on hardware/driver for specialix IO8+ multiport serial card. spi/ - overview of Linux kernel Serial Peripheral Interface (SPI) support. spinlocks.txt @@ -342,14 +312,10 @@ stable_api_nonsense.txt - info on why the kernel does not have a stable in-kernel api or abi. stable_kernel_rules.txt - rules and procedures for the -stable kernel releases. -stallion.txt - - info on using the Stallion multiport serial driver. svga.txt - short guide on selecting video modes at boot via VGA BIOS. sysfs-rules.txt - How not to use sysfs. -sx.txt - - info on the Specialix SX/SI multiport serial driver. sysctl/ - directory with info on the /proc/sys/* files. sysrq.txt @@ -358,8 +324,6 @@ telephony/ - directory with info on telephony (e.g. voice over IP) support. time_interpolators.txt - info on time interpolators. -tty.txt - - guide to the locking policies of the tty layer. uml/ - directory with information about User Mode Linux. unicode.txt @@ -382,7 +346,7 @@ w1/ - directory with documents regarding the 1-wire (w1) subsystem. watchdog/ - how to auto-reboot Linux if it has "fallen and can't get up". ;-) -x86_64/ +x86/x86_64/ - directory with info on Linux support for AMD x86-64 (Hammer) machines. zorro.txt - info on writing drivers for Zorro bus devices found on Amigas. diff --git a/Documentation/ABI/testing/sysfs-c2port b/Documentation/ABI/testing/sysfs-c2port new file mode 100644 index 000000000000..716cffc457e9 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-c2port @@ -0,0 +1,88 @@ +What: /sys/class/c2port/ +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/ directory will contain files and + directories that will provide a unified interface to + the C2 port interface. + +What: /sys/class/c2port/c2portX +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/ directory is related to X-th + C2 port into the system. Each directory will contain files to + manage and control its C2 port. + +What: /sys/class/c2port/c2portX/access +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/access file enable the access + to the C2 port from the system. No commands can be sent + till this entry is set to 0. + +What: /sys/class/c2port/c2portX/dev_id +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/dev_id file show the device ID + of the connected micro. + +What: /sys/class/c2port/c2portX/flash_access +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/flash_access file enable the + access to the on-board flash of the connected micro. + No commands can be sent till this entry is set to 0. + +What: /sys/class/c2port/c2portX/flash_block_size +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/flash_block_size file show + the on-board flash block size of the connected micro. + +What: /sys/class/c2port/c2portX/flash_blocks_num +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/flash_blocks_num file show + the on-board flash blocks number of the connected micro. + +What: /sys/class/c2port/c2portX/flash_data +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/flash_data file export + the content of the on-board flash of the connected micro. + +What: /sys/class/c2port/c2portX/flash_erase +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/flash_erase file execute + the "erase" command on the on-board flash of the connected + micro. + +What: /sys/class/c2port/c2portX/flash_erase +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/flash_erase file show the + on-board flash size of the connected micro. + +What: /sys/class/c2port/c2portX/reset +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/reset file execute a "reset" + command on the connected micro. + +What: /sys/class/c2port/c2portX/rev_id +Date: October 2008 +Contact: Rodolfo Giometti +Description: + The /sys/class/c2port/c2portX/rev_id file show the revision ID + of the connected micro. diff --git a/Documentation/ABI/testing/sysfs-firmware-acpi b/Documentation/ABI/testing/sysfs-firmware-acpi index f27be7d1a49f..e8ffc70ffe12 100644 --- a/Documentation/ABI/testing/sysfs-firmware-acpi +++ b/Documentation/ABI/testing/sysfs-firmware-acpi @@ -89,7 +89,7 @@ Description: error - an interrupt that can't be accounted for above. - invalid: it's either a wakeup GPE or a GPE/Fixed Event that + invalid: it's either a GPE or a Fixed Event that doesn't have an event handler. disable: the GPE/Fixed Event is valid but disabled. @@ -117,30 +117,30 @@ Description: and other user space applications so that the machine won't shutdown when pressing the power button. # cat ff_pwr_btn - 0 + 0 enabled # press the power button for 3 times; # cat ff_pwr_btn - 3 + 3 enabled # echo disable > ff_pwr_btn # cat ff_pwr_btn - disable + 3 disabled # press the power button for 3 times; # cat ff_pwr_btn - disable + 3 disabled # echo enable > ff_pwr_btn # cat ff_pwr_btn - 4 + 4 enabled /* * this is because the status bit is set even if the enable bit is cleared, * and it triggers an ACPI fixed event when the enable bit is set again */ # press the power button for 3 times; # cat ff_pwr_btn - 7 + 7 enabled # echo disable > ff_pwr_btn # press the power button for 3 times; # echo clear > ff_pwr_btn /* clear the status bit */ # echo disable > ff_pwr_btn # cat ff_pwr_btn - 7 + 7 enabled diff --git a/Documentation/DMA-API.txt b/Documentation/DMA-API.txt index b8e86460046e..b462bb149543 100644 --- a/Documentation/DMA-API.txt +++ b/Documentation/DMA-API.txt @@ -316,12 +316,10 @@ reduce current DMA mapping usage or delay and try again later). pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) -Maps a scatter gather list from the block layer. - Returns: the number of physical segments mapped (this may be shorter -than passed in if the block layer determines that some -elements of the scatter/gather list are physically adjacent and thus -may be mapped with a single entry). +than passed in if some elements of the scatter/gather list are +physically or virtually adjacent and an IOMMU maps them with a single +entry). Please note that the sg cannot be mapped again if it has been mapped once. The mapping process is allowed to destroy information in the sg. diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile index fabc06466b93..9b1f6ca100d1 100644 --- a/Documentation/DocBook/Makefile +++ b/Documentation/DocBook/Makefile @@ -136,7 +136,7 @@ quiet_cmd_db2ps = PS $@ %.ps : %.xml $(call cmd,db2ps) -quiet_cmd_db2pdf = PDF $@ +quiet_cmd_db2pdf = PDF $@ cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template)) %.pdf : %.xml $(call cmd,db2pdf) @@ -148,7 +148,7 @@ build_main_index = rm -rf $(main_idx) && \ echo '

Kernel Version: $(KERNELVERSION)

' >> $(main_idx) && \ cat $(HTML) >> $(main_idx) -quiet_cmd_db2html = HTML $@ +quiet_cmd_db2html = HTML $@ cmd_db2html = xmlto xhtml $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \ echo ' \ $(patsubst %.html,%,$(notdir $@))

' > $@ diff --git a/Documentation/DocBook/deviceiobook.tmpl b/Documentation/DocBook/deviceiobook.tmpl index 9ee6f3cbb414..3ed88126ab8f 100644 --- a/Documentation/DocBook/deviceiobook.tmpl +++ b/Documentation/DocBook/deviceiobook.tmpl @@ -24,7 +24,7 @@ Cox

- alan@redhat.com + alan@lxorguk.ukuu.org.uk
@@ -316,7 +316,7 @@ CPU B: spin_unlock_irqrestore(&dev_lock, flags) Public Functions Provided -!Iinclude/asm-x86/io_32.h +!Iarch/x86/include/asm/io_32.h !Elib/iomap.c diff --git a/Documentation/DocBook/kernel-api.tmpl b/Documentation/DocBook/kernel-api.tmpl index 9d0058e788e5..5818ff75786a 100644 --- a/Documentation/DocBook/kernel-api.tmpl +++ b/Documentation/DocBook/kernel-api.tmpl @@ -45,8 +45,8 @@ Atomic and pointer manipulation -!Iinclude/asm-x86/atomic_32.h -!Iinclude/asm-x86/unaligned.h +!Iarch/x86/include/asm/atomic_32.h +!Iarch/x86/include/asm/unaligned.h Delaying, scheduling, and timer routines @@ -119,7 +119,7 @@ X!Ilib/string.c !Elib/string.c Bit Operations -!Iinclude/asm-x86/bitops.h +!Iarch/x86/include/asm/bitops.h @@ -155,7 +155,7 @@ X!Ilib/string.c !Emm/slab.c User Space Memory Access -!Iinclude/asm-x86/uaccess_32.h +!Iarch/x86/include/asm/uaccess_32.h !Earch/x86/lib/usercopy_32.c More Memory Management Functions @@ -265,7 +265,7 @@ X!Earch/x86/kernel/mca_32.c --> MCA Bus DMA -!Iinclude/asm-x86/mca_dma.h +!Iarch/x86/include/asm/mca_dma.h diff --git a/Documentation/DocBook/kernel-hacking.tmpl b/Documentation/DocBook/kernel-hacking.tmpl index ae15d55350ec..a50d6cd58573 100644 --- a/Documentation/DocBook/kernel-hacking.tmpl +++ b/Documentation/DocBook/kernel-hacking.tmpl @@ -1239,7 +1239,7 @@ static struct block_device_operations opt_fops = { - include/asm-x86/delay_32.h: + arch/x86/include/asm/delay.h: #define ndelay(n) (__builtin_constant_p(n) ? \ @@ -1265,7 +1265,7 @@ static struct block_device_operations opt_fops = { - include/asm-x86/uaccess_32.h: + arch/x86/include/asm/uaccess_32.h: diff --git a/Documentation/DocBook/mcabook.tmpl b/Documentation/DocBook/mcabook.tmpl index 529a53dc1389..467ccac6ec50 100644 --- a/Documentation/DocBook/mcabook.tmpl +++ b/Documentation/DocBook/mcabook.tmpl @@ -12,7 +12,7 @@ Cox
- alan@redhat.com + alan@lxorguk.ukuu.org.uk
@@ -101,7 +101,7 @@ DMA Functions Provided -!Iinclude/asm-x86/mca_dma.h +!Iarch/x86/include/asm/mca_dma.h diff --git a/Documentation/DocBook/wanbook.tmpl b/Documentation/DocBook/wanbook.tmpl index 9eebcc304de4..8c93db122f04 100644 --- a/Documentation/DocBook/wanbook.tmpl +++ b/Documentation/DocBook/wanbook.tmpl @@ -12,7 +12,7 @@ Cox
- alan@redhat.com + alan@lxorguk.ukuu.org.uk
diff --git a/Documentation/DocBook/z8530book.tmpl b/Documentation/DocBook/z8530book.tmpl index a42a8a4c7689..6f3883be877e 100644 --- a/Documentation/DocBook/z8530book.tmpl +++ b/Documentation/DocBook/z8530book.tmpl @@ -12,7 +12,7 @@ Cox
- alan@redhat.com + alan@lxorguk.ukuu.org.uk
diff --git a/Documentation/MSI-HOWTO.txt b/Documentation/MSI-HOWTO.txt deleted file mode 100644 index 256defd7e174..000000000000 --- a/Documentation/MSI-HOWTO.txt +++ /dev/null @@ -1,509 +0,0 @@ - The MSI Driver Guide HOWTO - Tom L Nguyen tom.l.nguyen@intel.com - 10/03/2003 - Revised Feb 12, 2004 by Martine Silbermann - email: Martine.Silbermann@hp.com - Revised Jun 25, 2004 by Tom L Nguyen - -1. About this guide - -This guide describes the basics of Message Signaled Interrupts (MSI), -the advantages of using MSI over traditional interrupt mechanisms, -and how to enable your driver to use MSI or MSI-X. Also included is -a Frequently Asked Questions (FAQ) section. - -1.1 Terminology - -PCI devices can be single-function or multi-function. In either case, -when this text talks about enabling or disabling MSI on a "device -function," it is referring to one specific PCI device and function and -not to all functions on a PCI device (unless the PCI device has only -one function). - -2. Copyright 2003 Intel Corporation - -3. What is MSI/MSI-X? - -Message Signaled Interrupt (MSI), as described in the PCI Local Bus -Specification Revision 2.3 or later, is an optional feature, and a -required feature for PCI Express devices. MSI enables a device function -to request service by sending an Inbound Memory Write on its PCI bus to -the FSB as a Message Signal Interrupt transaction. Because MSI is -generated in the form of a Memory Write, all transaction conditions, -such as a Retry, Master-Abort, Target-Abort or normal completion, are -supported. - -A PCI device that supports MSI must also support pin IRQ assertion -interrupt mechanism to provide backward compatibility for systems that -do not support MSI. In systems which support MSI, the bus driver is -responsible for initializing the message address and message data of -the device function's MSI/MSI-X capability structure during device -initial configuration. - -An MSI capable device function indicates MSI support by implementing -the MSI/MSI-X capability structure in its PCI capability list. The -device function may implement both the MSI capability structure and -the MSI-X capability structure; however, the bus driver should not -enable both. - -The MSI capability structure contains Message Control register, -Message Address register and Message Data register. These registers -provide the bus driver control over MSI. The Message Control register -indicates the MSI capability supported by the device. The Message -Address register specifies the target address and the Message Data -register specifies the characteristics of the message. To request -service, the device function writes the content of the Message Data -register to the target address. The device and its software driver -are prohibited from writing to these registers. - -The MSI-X capability structure is an optional extension to MSI. It -uses an independent and separate capability structure. There are -some key advantages to implementing the MSI-X capability structure -over the MSI capability structure as described below. - - - Support a larger maximum number of vectors per function. - - - Provide the ability for system software to configure - each vector with an independent message address and message - data, specified by a table that resides in Memory Space. - - - MSI and MSI-X both support per-vector masking. Per-vector - masking is an optional extension of MSI but a required - feature for MSI-X. Per-vector masking provides the kernel the - ability to mask/unmask a single MSI while running its - interrupt service routine. If per-vector masking is - not supported, then the device driver should provide the - hardware/software synchronization to ensure that the device - generates MSI when the driver wants it to do so. - -4. Why use MSI? - -As a benefit to the simplification of board design, MSI allows board -designers to remove out-of-band interrupt routing. MSI is another -step towards a legacy-free environment. - -Due to increasing pressure on chipset and processor packages to -reduce pin count, the need for interrupt pins is expected to -diminish over time. Devices, due to pin constraints, may implement -messages to increase performance. - -PCI Express endpoints uses INTx emulation (in-band messages) instead -of IRQ pin assertion. Using INTx emulation requires interrupt -sharing among devices connected to the same node (PCI bridge) while -MSI is unique (non-shared) and does not require BIOS configuration -support. As a result, the PCI Express technology requires MSI -support for better interrupt performance. - -Using MSI enables the device functions to support two or more -vectors, which can be configured to target different CPUs to -increase scalability. - -5. Configuring a driver to use MSI/MSI-X - -By default, the kernel will not enable MSI/MSI-X on all devices that -support this capability. The CONFIG_PCI_MSI kernel option -must be selected to enable MSI/MSI-X support. - -5.1 Including MSI/MSI-X support into the kernel - -To allow MSI/MSI-X capable device drivers to selectively enable -MSI/MSI-X (using pci_enable_msi()/pci_enable_msix() as described -below), the VECTOR based scheme needs to be enabled by setting -CONFIG_PCI_MSI during kernel config. - -Since the target of the inbound message is the local APIC, providing -CONFIG_X86_LOCAL_APIC must be enabled as well as CONFIG_PCI_MSI. - -5.2 Configuring for MSI support - -Due to the non-contiguous fashion in vector assignment of the -existing Linux kernel, this version does not support multiple -messages regardless of a device function is capable of supporting -more than one vector. To enable MSI on a device function's MSI -capability structure requires a device driver to call the function -pci_enable_msi() explicitly. - -5.2.1 API pci_enable_msi - -int pci_enable_msi(struct pci_dev *dev) - -With this new API, a device driver that wants to have MSI -enabled on its device function must call this API to enable MSI. -A successful call will initialize the MSI capability structure -with ONE vector, regardless of whether a device function is -capable of supporting multiple messages. This vector replaces the -pre-assigned dev->irq with a new MSI vector. To avoid a conflict -of the new assigned vector with existing pre-assigned vector requires -a device driver to call this API before calling request_irq(). - -5.2.2 API pci_disable_msi - -void pci_disable_msi(struct pci_dev *dev) - -This API should always be used to undo the effect of pci_enable_msi() -when a device driver is unloading. This API restores dev->irq with -the pre-assigned IOAPIC vector and switches a device's interrupt -mode to PCI pin-irq assertion/INTx emulation mode. - -Note that a device driver should always call free_irq() on the MSI vector -that it has done request_irq() on before calling this API. Failure to do -so results in a BUG_ON() and a device will be left with MSI enabled and -leaks its vector. - -5.2.3 MSI mode vs. legacy mode diagram - -The below diagram shows the events which switch the interrupt -mode on the MSI-capable device function between MSI mode and -PIN-IRQ assertion mode. - - ------------ pci_enable_msi ------------------------ - | | <=============== | | - | MSI MODE | | PIN-IRQ ASSERTION MODE | - | | ===============> | | - ------------ pci_disable_msi ------------------------ - - -Figure 1. MSI Mode vs. Legacy Mode - -In Figure 1, a device operates by default in legacy mode. Legacy -in this context means PCI pin-irq assertion or PCI-Express INTx -emulation. A successful MSI request (using pci_enable_msi()) switches -a device's interrupt mode to MSI mode. A pre-assigned IOAPIC vector -stored in dev->irq will be saved by the PCI subsystem and a new -assigned MSI vector will replace dev->irq. - -To return back to its default mode, a device driver should always call -pci_disable_msi() to undo the effect of pci_enable_msi(). Note that a -device driver should always call free_irq() on the MSI vector it has -done request_irq() on before calling pci_disable_msi(). Failure to do -so results in a BUG_ON() and a device will be left with MSI enabled and -leaks its vector. Otherwise, the PCI subsystem restores a device's -dev->irq with a pre-assigned IOAPIC vector and marks the released -MSI vector as unused. - -Once being marked as unused, there is no guarantee that the PCI -subsystem will reserve this MSI vector for a device. Depending on -the availability of current PCI vector resources and the number of -MSI/MSI-X requests from other drivers, this MSI may be re-assigned. - -For the case where the PCI subsystem re-assigns this MSI vector to -another driver, a request to switch back to MSI mode may result -in being assigned a different MSI vector or a failure if no more -vectors are available. - -5.3 Configuring for MSI-X support - -Due to the ability of the system software to configure each vector of -the MSI-X capability structure with an independent message address -and message data, the non-contiguous fashion in vector assignment of -the existing Linux kernel has no impact on supporting multiple -messages on an MSI-X capable device functions. To enable MSI-X on -a device function's MSI-X capability structure requires its device -driver to call the function pci_enable_msix() explicitly. - -The function pci_enable_msix(), once invoked, enables either -all or nothing, depending on the current availability of PCI vector -resources. If the PCI vector resources are available for the number -of vectors requested by a device driver, this function will configure -the MSI-X table of the MSI-X capability structure of a device with -requested messages. To emphasize this reason, for example, a device -may be capable for supporting the maximum of 32 vectors while its -software driver usually may request 4 vectors. It is recommended -that the device driver should call this function once during the -initialization phase of the device driver. - -Unlike the function pci_enable_msi(), the function pci_enable_msix() -does not replace the pre-assigned IOAPIC dev->irq with a new MSI -vector because the PCI subsystem writes the 1:1 vector-to-entry mapping -into the field vector of each element contained in a second argument. -Note that the pre-assigned IOAPIC dev->irq is valid only if the device -operates in PIN-IRQ assertion mode. In MSI-X mode, any attempt at -using dev->irq by the device driver to request for interrupt service -may result in unpredictable behavior. - -For each MSI-X vector granted, a device driver is responsible for calling -other functions like request_irq(), enable_irq(), etc. to enable -this vector with its corresponding interrupt service handler. It is -a device driver's choice to assign all vectors with the same -interrupt service handler or each vector with a unique interrupt -service handler. - -5.3.1 Handling MMIO address space of MSI-X Table - -The PCI 3.0 specification has implementation notes that MMIO address -space for a device's MSI-X structure should be isolated so that the -software system can set different pages for controlling accesses to the -MSI-X structure. The implementation of MSI support requires the PCI -subsystem, not a device driver, to maintain full control of the MSI-X -table/MSI-X PBA (Pending Bit Array) and MMIO address space of the MSI-X -table/MSI-X PBA. A device driver should not access the MMIO address -space of the MSI-X table/MSI-X PBA. - -5.3.2 API pci_enable_msix - -int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) - -This API enables a device driver to request the PCI subsystem -to enable MSI-X messages on its hardware device. Depending on -the availability of PCI vectors resources, the PCI subsystem enables -either all or none of the requested vectors. - -Argument 'dev' points to the device (pci_dev) structure. - -Argument 'entries' is a pointer to an array of msix_entry structs. -The number of entries is indicated in argument 'nvec'. -struct msix_entry is defined in /driver/pci/msi.h: - -struct msix_entry { - u16 vector; /* kernel uses to write alloc vector */ - u16 entry; /* driver uses to specify entry */ -}; - -A device driver is responsible for initializing the field 'entry' of -each element with a unique entry supported by MSI-X table. Otherwise, --EINVAL will be returned as a result. A successful return of zero -indicates the PCI subsystem completed initializing each of the requested -entries of the MSI-X table with message address and message data. -Last but not least, the PCI subsystem will write the 1:1 -vector-to-entry mapping into the field 'vector' of each element. A -device driver is responsible for keeping track of allocated MSI-X -vectors in its internal data structure. - -A return of zero indicates that the number of MSI-X vectors was -successfully allocated. A return of greater than zero indicates -MSI-X vector shortage. Or a return of less than zero indicates -a failure. This failure may be a result of duplicate entries -specified in second argument, or a result of no available vector, -or a result of failing to initialize MSI-X table entries. - -5.3.3 API pci_disable_msix - -void pci_disable_msix(struct pci_dev *dev) - -This API should always be used to undo the effect of pci_enable_msix() -when a device driver is unloading. Note that a device driver should -always call free_irq() on all MSI-X vectors it has done request_irq() -on before calling this API. Failure to do so results in a BUG_ON() and -a device will be left with MSI-X enabled and leaks its vectors. - -5.3.4 MSI-X mode vs. legacy mode diagram - -The below diagram shows the events which switch the interrupt -mode on the MSI-X capable device function between MSI-X mode and -PIN-IRQ assertion mode (legacy). - - ------------ pci_enable_msix(,,n) ------------------------ - | | <=============== | | - | MSI-X MODE | | PIN-IRQ ASSERTION MODE | - | | ===============> | | - ------------ pci_disable_msix ------------------------ - -Figure 2. MSI-X Mode vs. Legacy Mode - -In Figure 2, a device operates by default in legacy mode. A -successful MSI-X request (using pci_enable_msix()) switches a -device's interrupt mode to MSI-X mode. A pre-assigned IOAPIC vector -stored in dev->irq will be saved by the PCI subsystem; however, -unlike MSI mode, the PCI subsystem will not replace dev->irq with -assigned MSI-X vector because the PCI subsystem already writes the 1:1 -vector-to-entry mapping into the field 'vector' of each element -specified in second argument. - -To return back to its default mode, a device driver should always call -pci_disable_msix() to undo the effect of pci_enable_msix(). Note that -a device driver should always call free_irq() on all MSI-X vectors it -has done request_irq() on before calling pci_disable_msix(). Failure -to do so results in a BUG_ON() and a device will be left with MSI-X -enabled and leaks its vectors. Otherwise, the PCI subsystem switches a -device function's interrupt mode from MSI-X mode to legacy mode and -marks all allocated MSI-X vectors as unused. - -Once being marked as unused, there is no guarantee that the PCI -subsystem will reserve these MSI-X vectors for a device. Depending on -the availability of current PCI vector resources and the number of -MSI/MSI-X requests from other drivers, these MSI-X vectors may be -re-assigned. - -For the case where the PCI subsystem re-assigned these MSI-X vectors -to other drivers, a request to switch back to MSI-X mode may result -being assigned with another set of MSI-X vectors or a failure if no -more vectors are available. - -5.4 Handling function implementing both MSI and MSI-X capabilities - -For the case where a function implements both MSI and MSI-X -capabilities, the PCI subsystem enables a device to run either in MSI -mode or MSI-X mode but not both. A device driver determines whether it -wants MSI or MSI-X enabled on its hardware device. Once a device -driver requests for MSI, for example, it is prohibited from requesting -MSI-X; in other words, a device driver is not permitted to ping-pong -between MSI mod MSI-X mode during a run-time. - -5.5 Hardware requirements for MSI/MSI-X support - -MSI/MSI-X support requires support from both system hardware and -individual hardware device functions. - -5.5.1 Required x86 hardware support - -Since the target of MSI address is the local APIC CPU, enabling -MSI/MSI-X support in the Linux kernel is dependent on whether existing -system hardware supports local APIC. Users should verify that their -system supports local APIC operation by testing that it runs when -CONFIG_X86_LOCAL_APIC=y. - -In SMP environment, CONFIG_X86_LOCAL_APIC is automatically set; -however, in UP environment, users must manually set -CONFIG_X86_LOCAL_APIC. Once CONFIG_X86_LOCAL_APIC=y, setting -CONFIG_PCI_MSI enables the VECTOR based scheme and the option for -MSI-capable device drivers to selectively enable MSI/MSI-X. - -Note that CONFIG_X86_IO_APIC setting is irrelevant because MSI/MSI-X -vector is allocated new during runtime and MSI/MSI-X support does not -depend on BIOS support. This key independency enables MSI/MSI-X -support on future IOxAPIC free platforms. - -5.5.2 Device hardware support - -The hardware device function supports MSI by indicating the -MSI/MSI-X capability structure on its PCI capability list. By -default, this capability structure will not be initialized by -the kernel to enable MSI during the system boot. In other words, -the device function is running on its default pin assertion mode. -Note that in many cases the hardware supporting MSI have bugs, -which may result in system hangs. The software driver of specific -MSI-capable hardware is responsible for deciding whether to call -pci_enable_msi or not. A return of zero indicates the kernel -successfully initialized the MSI/MSI-X capability structure of the -device function. The device function is now running on MSI/MSI-X mode. - -5.6 How to tell whether MSI/MSI-X is enabled on device function - -At the driver level, a return of zero from the function call of -pci_enable_msi()/pci_enable_msix() indicates to a device driver that -its device function is initialized successfully and ready to run in -MSI/MSI-X mode. - -At the user level, users can use the command 'cat /proc/interrupts' -to display the vectors allocated for devices and their interrupt -MSI/MSI-X modes ("PCI-MSI"/"PCI-MSI-X"). Below shows MSI mode is -enabled on a SCSI Adaptec 39320D Ultra320 controller. - - CPU0 CPU1 - 0: 324639 0 IO-APIC-edge timer - 1: 1186 0 IO-APIC-edge i8042 - 2: 0 0 XT-PIC cascade - 12: 2797 0 IO-APIC-edge i8042 - 14: 6543 0 IO-APIC-edge ide0 - 15: 1 0 IO-APIC-edge ide1 -169: 0 0 IO-APIC-level uhci-hcd -185: 0 0 IO-APIC-level uhci-hcd -193: 138 10 PCI-MSI aic79xx -201: 30 0 PCI-MSI aic79xx -225: 30 0 IO-APIC-level aic7xxx -233: 30 0 IO-APIC-level aic7xxx -NMI: 0 0 -LOC: 324553 325068 -ERR: 0 -MIS: 0 - -6. MSI quirks - -Several PCI chipsets or devices are known to not support MSI. -The PCI stack provides 3 possible levels of MSI disabling: -* on a single device -* on all devices behind a specific bridge -* globally - -6.1. Disabling MSI on a single device - -Under some circumstances it might be required to disable MSI on a -single device. This may be achieved by either not calling pci_enable_msi() -or all, or setting the pci_dev->no_msi flag before (most of the time -in a quirk). - -6.2. Disabling MSI below a bridge - -The vast majority of MSI quirks are required by PCI bridges not -being able to route MSI between busses. In this case, MSI have to be -disabled on all devices behind this bridge. It is achieves by setting -the PCI_BUS_FLAGS_NO_MSI flag in the pci_bus->bus_flags of the bridge -subordinate bus. There is no need to set the same flag on bridges that -are below the broken bridge. When pci_enable_msi() is called to enable -MSI on a device, pci_msi_supported() takes care of checking the NO_MSI -flag in all parent busses of the device. - -Some bridges actually support dynamic MSI support enabling/disabling -by changing some bits in their PCI configuration space (especially -the Hypertransport chipsets such as the nVidia nForce and Serverworks -HT2000). It may then be required to update the NO_MSI flag on the -corresponding devices in the sysfs hierarchy. To enable MSI support -on device "0000:00:0e", do: - - echo 1 > /sys/bus/pci/devices/0000:00:0e/msi_bus - -To disable MSI support, echo 0 instead of 1. Note that it should be -used with caution since changing this value might break interrupts. - -6.3. Disabling MSI globally - -Some extreme cases may require to disable MSI globally on the system. -For now, the only known case is a Serverworks PCI-X chipsets (MSI are -not supported on several busses that are not all connected to the -chipset in the Linux PCI hierarchy). In the vast majority of other -cases, disabling only behind a specific bridge is enough. - -For debugging purpose, the user may also pass pci=nomsi on the kernel -command-line to explicitly disable MSI globally. But, once the appro- -priate quirks are added to the kernel, this option should not be -required anymore. - -6.4. Finding why MSI cannot be enabled on a device - -Assuming that MSI are not enabled on a device, you should look at -dmesg to find messages that quirks may output when disabling MSI -on some devices, some bridges or even globally. -Then, lspci -t gives the list of bridges above a device. Reading -/sys/bus/pci/devices/0000:00:0e/msi_bus will tell you whether MSI -are enabled (1) or disabled (0). In 0 is found in a single bridge -msi_bus file above the device, MSI cannot be enabled. - -7. FAQ - -Q1. Are there any limitations on using the MSI? - -A1. If the PCI device supports MSI and conforms to the -specification and the platform supports the APIC local bus, -then using MSI should work. - -Q2. Will it work on all the Pentium processors (P3, P4, Xeon, -AMD processors)? In P3 IPI's are transmitted on the APIC local -bus and in P4 and Xeon they are transmitted on the system -bus. Are there any implications with this? - -A2. MSI support enables a PCI device sending an inbound -memory write (0xfeexxxxx as target address) on its PCI bus -directly to the FSB. Since the message address has a -redirection hint bit cleared, it should work. - -Q3. The target address 0xfeexxxxx will be translated by the -Host Bridge into an interrupt message. Are there any -limitations on the chipsets such as Intel 8xx, Intel e7xxx, -or VIA? - -A3. If these chipsets support an inbound memory write with -target address set as 0xfeexxxxx, as conformed to PCI -specification 2.3 or latest, then it should work. - -Q4. From the driver point of view, if the MSI is lost because -of errors occurring during inbound memory write, then it may -wait forever. Is there a mechanism for it to recover? - -A4. Since the target of the transaction is an inbound memory -write, all transaction termination conditions (Retry, -Master-Abort, Target-Abort, or normal completion) are -supported. A device sending an MSI must abide by all the PCI -rules and conditions regarding that inbound memory write. So, -if a retry is signaled it must retry, etc... We believe that -the recommendation for Abort is also a retry (refer to PCI -specification 2.3 or latest). diff --git a/Documentation/ManagementStyle b/Documentation/ManagementStyle index 49a8efa5afeb..a5f0ea58c788 100644 --- a/Documentation/ManagementStyle +++ b/Documentation/ManagementStyle @@ -17,7 +17,7 @@ companies. If you sign purchase orders or you have any clue about the budget of your group, you're almost certainly not a kernel manager. These suggestions may or may not apply to you. -First off, I'd suggest buying "Seven Habits of Highly Successful +First off, I'd suggest buying "Seven Habits of Highly Effective People", and NOT read it. Burn it, it's a great symbolic gesture. (*) This document does so not so much by answering the question, but by diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX index 49f43946c6b6..812b17fe3ed0 100644 --- a/Documentation/PCI/00-INDEX +++ b/Documentation/PCI/00-INDEX @@ -1,5 +1,7 @@ 00-INDEX - this file +MSI-HOWTO.txt + - the Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ. PCI-DMA-mapping.txt - info for PCI drivers using DMA portably across all platforms PCIEBUS-HOWTO.txt diff --git a/Documentation/PCI/MSI-HOWTO.txt b/Documentation/PCI/MSI-HOWTO.txt new file mode 100644 index 000000000000..256defd7e174 --- /dev/null +++ b/Documentation/PCI/MSI-HOWTO.txt @@ -0,0 +1,509 @@ + The MSI Driver Guide HOWTO + Tom L Nguyen tom.l.nguyen@intel.com + 10/03/2003 + Revised Feb 12, 2004 by Martine Silbermann + email: Martine.Silbermann@hp.com + Revised Jun 25, 2004 by Tom L Nguyen + +1. About this guide + +This guide describes the basics of Message Signaled Interrupts (MSI), +the advantages of using MSI over traditional interrupt mechanisms, +and how to enable your driver to use MSI or MSI-X. Also included is +a Frequently Asked Questions (FAQ) section. + +1.1 Terminology + +PCI devices can be single-function or multi-function. In either case, +when this text talks about enabling or disabling MSI on a "device +function," it is referring to one specific PCI device and function and +not to all functions on a PCI device (unless the PCI device has only +one function). + +2. Copyright 2003 Intel Corporation + +3. What is MSI/MSI-X? + +Message Signaled Interrupt (MSI), as described in the PCI Local Bus +Specification Revision 2.3 or later, is an optional feature, and a +required feature for PCI Express devices. MSI enables a device function +to request service by sending an Inbound Memory Write on its PCI bus to +the FSB as a Message Signal Interrupt transaction. Because MSI is +generated in the form of a Memory Write, all transaction conditions, +such as a Retry, Master-Abort, Target-Abort or normal completion, are +supported. + +A PCI device that supports MSI must also support pin IRQ assertion +interrupt mechanism to provide backward compatibility for systems that +do not support MSI. In systems which support MSI, the bus driver is +responsible for initializing the message address and message data of +the device function's MSI/MSI-X capability structure during device +initial configuration. + +An MSI capable device function indicates MSI support by implementing +the MSI/MSI-X capability structure in its PCI capability list. The +device function may implement both the MSI capability structure and +the MSI-X capability structure; however, the bus driver should not +enable both. + +The MSI capability structure contains Message Control register, +Message Address register and Message Data register. These registers +provide the bus driver control over MSI. The Message Control register +indicates the MSI capability supported by the device. The Message +Address register specifies the target address and the Message Data +register specifies the characteristics of the message. To request +service, the device function writes the content of the Message Data +register to the target address. The device and its software driver +are prohibited from writing to these registers. + +The MSI-X capability structure is an optional extension to MSI. It +uses an independent and separate capability structure. There are +some key advantages to implementing the MSI-X capability structure +over the MSI capability structure as described below. + + - Support a larger maximum number of vectors per function. + + - Provide the ability for system software to configure + each vector with an independent message address and message + data, specified by a table that resides in Memory Space. + + - MSI and MSI-X both support per-vector masking. Per-vector + masking is an optional extension of MSI but a required + feature for MSI-X. Per-vector masking provides the kernel the + ability to mask/unmask a single MSI while running its + interrupt service routine. If per-vector masking is + not supported, then the device driver should provide the + hardware/software synchronization to ensure that the device + generates MSI when the driver wants it to do so. + +4. Why use MSI? + +As a benefit to the simplification of board design, MSI allows board +designers to remove out-of-band interrupt routing. MSI is another +step towards a legacy-free environment. + +Due to increasing pressure on chipset and processor packages to +reduce pin count, the need for interrupt pins is expected to +diminish over time. Devices, due to pin constraints, may implement +messages to increase performance. + +PCI Express endpoints uses INTx emulation (in-band messages) instead +of IRQ pin assertion. Using INTx emulation requires interrupt +sharing among devices connected to the same node (PCI bridge) while +MSI is unique (non-shared) and does not require BIOS configuration +support. As a result, the PCI Express technology requires MSI +support for better interrupt performance. + +Using MSI enables the device functions to support two or more +vectors, which can be configured to target different CPUs to +increase scalability. + +5. Configuring a driver to use MSI/MSI-X + +By default, the kernel will not enable MSI/MSI-X on all devices that +support this capability. The CONFIG_PCI_MSI kernel option +must be selected to enable MSI/MSI-X support. + +5.1 Including MSI/MSI-X support into the kernel + +To allow MSI/MSI-X capable device drivers to selectively enable +MSI/MSI-X (using pci_enable_msi()/pci_enable_msix() as described +below), the VECTOR based scheme needs to be enabled by setting +CONFIG_PCI_MSI during kernel config. + +Since the target of the inbound message is the local APIC, providing +CONFIG_X86_LOCAL_APIC must be enabled as well as CONFIG_PCI_MSI. + +5.2 Configuring for MSI support + +Due to the non-contiguous fashion in vector assignment of the +existing Linux kernel, this version does not support multiple +messages regardless of a device function is capable of supporting +more than one vector. To enable MSI on a device function's MSI +capability structure requires a device driver to call the function +pci_enable_msi() explicitly. + +5.2.1 API pci_enable_msi + +int pci_enable_msi(struct pci_dev *dev) + +With this new API, a device driver that wants to have MSI +enabled on its device function must call this API to enable MSI. +A successful call will initialize the MSI capability structure +with ONE vector, regardless of whether a device function is +capable of supporting multiple messages. This vector replaces the +pre-assigned dev->irq with a new MSI vector. To avoid a conflict +of the new assigned vector with existing pre-assigned vector requires +a device driver to call this API before calling request_irq(). + +5.2.2 API pci_disable_msi + +void pci_disable_msi(struct pci_dev *dev) + +This API should always be used to undo the effect of pci_enable_msi() +when a device driver is unloading. This API restores dev->irq with +the pre-assigned IOAPIC vector and switches a device's interrupt +mode to PCI pin-irq assertion/INTx emulation mode. + +Note that a device driver should always call free_irq() on the MSI vector +that it has done request_irq() on before calling this API. Failure to do +so results in a BUG_ON() and a device will be left with MSI enabled and +leaks its vector. + +5.2.3 MSI mode vs. legacy mode diagram + +The below diagram shows the events which switch the interrupt +mode on the MSI-capable device function between MSI mode and +PIN-IRQ assertion mode. + + ------------ pci_enable_msi ------------------------ + | | <=============== | | + | MSI MODE | | PIN-IRQ ASSERTION MODE | + | | ===============> | | + ------------ pci_disable_msi ------------------------ + + +Figure 1. MSI Mode vs. Legacy Mode + +In Figure 1, a device operates by default in legacy mode. Legacy +in this context means PCI pin-irq assertion or PCI-Express INTx +emulation. A successful MSI request (using pci_enable_msi()) switches +a device's interrupt mode to MSI mode. A pre-assigned IOAPIC vector +stored in dev->irq will be saved by the PCI subsystem and a new +assigned MSI vector will replace dev->irq. + +To return back to its default mode, a device driver should always call +pci_disable_msi() to undo the effect of pci_enable_msi(). Note that a +device driver should always call free_irq() on the MSI vector it has +done request_irq() on before calling pci_disable_msi(). Failure to do +so results in a BUG_ON() and a device will be left with MSI enabled and +leaks its vector. Otherwise, the PCI subsystem restores a device's +dev->irq with a pre-assigned IOAPIC vector and marks the released +MSI vector as unused. + +Once being marked as unused, there is no guarantee that the PCI +subsystem will reserve this MSI vector for a device. Depending on +the availability of current PCI vector resources and the number of +MSI/MSI-X requests from other drivers, this MSI may be re-assigned. + +For the case where the PCI subsystem re-assigns this MSI vector to +another driver, a request to switch back to MSI mode may result +in being assigned a different MSI vector or a failure if no more +vectors are available. + +5.3 Configuring for MSI-X support + +Due to the ability of the system software to configure each vector of +the MSI-X capability structure with an independent message address +and message data, the non-contiguous fashion in vector assignment of +the existing Linux kernel has no impact on supporting multiple +messages on an MSI-X capable device functions. To enable MSI-X on +a device function's MSI-X capability structure requires its device +driver to call the function pci_enable_msix() explicitly. + +The function pci_enable_msix(), once invoked, enables either +all or nothing, depending on the current availability of PCI vector +resources. If the PCI vector resources are available for the number +of vectors requested by a device driver, this function will configure +the MSI-X table of the MSI-X capability structure of a device with +requested messages. To emphasize this reason, for example, a device +may be capable for supporting the maximum of 32 vectors while its +software driver usually may request 4 vectors. It is recommended +that the device driver should call this function once during the +initialization phase of the device driver. + +Unlike the function pci_enable_msi(), the function pci_enable_msix() +does not replace the pre-assigned IOAPIC dev->irq with a new MSI +vector because the PCI subsystem writes the 1:1 vector-to-entry mapping +into the field vector of each element contained in a second argument. +Note that the pre-assigned IOAPIC dev->irq is valid only if the device +operates in PIN-IRQ assertion mode. In MSI-X mode, any attempt at +using dev->irq by the device driver to request for interrupt service +may result in unpredictable behavior. + +For each MSI-X vector granted, a device driver is responsible for calling +other functions like request_irq(), enable_irq(), etc. to enable +this vector with its corresponding interrupt service handler. It is +a device driver's choice to assign all vectors with the same +interrupt service handler or each vector with a unique interrupt +service handler. + +5.3.1 Handling MMIO address space of MSI-X Table + +The PCI 3.0 specification has implementation notes that MMIO address +space for a device's MSI-X structure should be isolated so that the +software system can set different pages for controlling accesses to the +MSI-X structure. The implementation of MSI support requires the PCI +subsystem, not a device driver, to maintain full control of the MSI-X +table/MSI-X PBA (Pending Bit Array) and MMIO address space of the MSI-X +table/MSI-X PBA. A device driver should not access the MMIO address +space of the MSI-X table/MSI-X PBA. + +5.3.2 API pci_enable_msix + +int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) + +This API enables a device driver to request the PCI subsystem +to enable MSI-X messages on its hardware device. Depending on +the availability of PCI vectors resources, the PCI subsystem enables +either all or none of the requested vectors. + +Argument 'dev' points to the device (pci_dev) structure. + +Argument 'entries' is a pointer to an array of msix_entry structs. +The number of entries is indicated in argument 'nvec'. +struct msix_entry is defined in /driver/pci/msi.h: + +struct msix_entry { + u16 vector; /* kernel uses to write alloc vector */ + u16 entry; /* driver uses to specify entry */ +}; + +A device driver is responsible for initializing the field 'entry' of +each element with a unique entry supported by MSI-X table. Otherwise, +-EINVAL will be returned as a result. A successful return of zero +indicates the PCI subsystem completed initializing each of the requested +entries of the MSI-X table with message address and message data. +Last but not least, the PCI subsystem will write the 1:1 +vector-to-entry mapping into the field 'vector' of each element. A +device driver is responsible for keeping track of allocated MSI-X +vectors in its internal data structure. + +A return of zero indicates that the number of MSI-X vectors was +successfully allocated. A return of greater than zero indicates +MSI-X vector shortage. Or a return of less than zero indicates +a failure. This failure may be a result of duplicate entries +specified in second argument, or a result of no available vector, +or a result of failing to initialize MSI-X table entries. + +5.3.3 API pci_disable_msix + +void pci_disable_msix(struct pci_dev *dev) + +This API should always be used to undo the effect of pci_enable_msix() +when a device driver is unloading. Note that a device driver should +always call free_irq() on all MSI-X vectors it has done request_irq() +on before calling this API. Failure to do so results in a BUG_ON() and +a device will be left with MSI-X enabled and leaks its vectors. + +5.3.4 MSI-X mode vs. legacy mode diagram + +The below diagram shows the events which switch the interrupt +mode on the MSI-X capable device function between MSI-X mode and +PIN-IRQ assertion mode (legacy). + + ------------ pci_enable_msix(,,n) ------------------------ + | | <=============== | | + | MSI-X MODE | | PIN-IRQ ASSERTION MODE | + | | ===============> | | + ------------ pci_disable_msix ------------------------ + +Figure 2. MSI-X Mode vs. Legacy Mode + +In Figure 2, a device operates by default in legacy mode. A +successful MSI-X request (using pci_enable_msix()) switches a +device's interrupt mode to MSI-X mode. A pre-assigned IOAPIC vector +stored in dev->irq will be saved by the PCI subsystem; however, +unlike MSI mode, the PCI subsystem will not replace dev->irq with +assigned MSI-X vector because the PCI subsystem already writes the 1:1 +vector-to-entry mapping into the field 'vector' of each element +specified in second argument. + +To return back to its default mode, a device driver should always call +pci_disable_msix() to undo the effect of pci_enable_msix(). Note that +a device driver should always call free_irq() on all MSI-X vectors it +has done request_irq() on before calling pci_disable_msix(). Failure +to do so results in a BUG_ON() and a device will be left with MSI-X +enabled and leaks its vectors. Otherwise, the PCI subsystem switches a +device function's interrupt mode from MSI-X mode to legacy mode and +marks all allocated MSI-X vectors as unused. + +Once being marked as unused, there is no guarantee that the PCI +subsystem will reserve these MSI-X vectors for a device. Depending on +the availability of current PCI vector resources and the number of +MSI/MSI-X requests from other drivers, these MSI-X vectors may be +re-assigned. + +For the case where the PCI subsystem re-assigned these MSI-X vectors +to other drivers, a request to switch back to MSI-X mode may result +being assigned with another set of MSI-X vectors or a failure if no +more vectors are available. + +5.4 Handling function implementing both MSI and MSI-X capabilities + +For the case where a function implements both MSI and MSI-X +capabilities, the PCI subsystem enables a device to run either in MSI +mode or MSI-X mode but not both. A device driver determines whether it +wants MSI or MSI-X enabled on its hardware device. Once a device +driver requests for MSI, for example, it is prohibited from requesting +MSI-X; in other words, a device driver is not permitted to ping-pong +between MSI mod MSI-X mode during a run-time. + +5.5 Hardware requirements for MSI/MSI-X support + +MSI/MSI-X support requires support from both system hardware and +individual hardware device functions. + +5.5.1 Required x86 hardware support + +Since the target of MSI address is the local APIC CPU, enabling +MSI/MSI-X support in the Linux kernel is dependent on whether existing +system hardware supports local APIC. Users should verify that their +system supports local APIC operation by testing that it runs when +CONFIG_X86_LOCAL_APIC=y. + +In SMP environment, CONFIG_X86_LOCAL_APIC is automatically set; +however, in UP environment, users must manually set +CONFIG_X86_LOCAL_APIC. Once CONFIG_X86_LOCAL_APIC=y, setting +CONFIG_PCI_MSI enables the VECTOR based scheme and the option for +MSI-capable device drivers to selectively enable MSI/MSI-X. + +Note that CONFIG_X86_IO_APIC setting is irrelevant because MSI/MSI-X +vector is allocated new during runtime and MSI/MSI-X support does not +depend on BIOS support. This key independency enables MSI/MSI-X +support on future IOxAPIC free platforms. + +5.5.2 Device hardware support + +The hardware device function supports MSI by indicating the +MSI/MSI-X capability structure on its PCI capability list. By +default, this capability structure will not be initialized by +the kernel to enable MSI during the system boot. In other words, +the device function is running on its default pin assertion mode. +Note that in many cases the hardware supporting MSI have bugs, +which may result in system hangs. The software driver of specific +MSI-capable hardware is responsible for deciding whether to call +pci_enable_msi or not. A return of zero indicates the kernel +successfully initialized the MSI/MSI-X capability structure of the +device function. The device function is now running on MSI/MSI-X mode. + +5.6 How to tell whether MSI/MSI-X is enabled on device function + +At the driver level, a return of zero from the function call of +pci_enable_msi()/pci_enable_msix() indicates to a device driver that +its device function is initialized successfully and ready to run in +MSI/MSI-X mode. + +At the user level, users can use the command 'cat /proc/interrupts' +to display the vectors allocated for devices and their interrupt +MSI/MSI-X modes ("PCI-MSI"/"PCI-MSI-X"). Below shows MSI mode is +enabled on a SCSI Adaptec 39320D Ultra320 controller. + + CPU0 CPU1 + 0: 324639 0 IO-APIC-edge timer + 1: 1186 0 IO-APIC-edge i8042 + 2: 0 0 XT-PIC cascade + 12: 2797 0 IO-APIC-edge i8042 + 14: 6543 0 IO-APIC-edge ide0 + 15: 1 0 IO-APIC-edge ide1 +169: 0 0 IO-APIC-level uhci-hcd +185: 0 0 IO-APIC-level uhci-hcd +193: 138 10 PCI-MSI aic79xx +201: 30 0 PCI-MSI aic79xx +225: 30 0 IO-APIC-level aic7xxx +233: 30 0 IO-APIC-level aic7xxx +NMI: 0 0 +LOC: 324553 325068 +ERR: 0 +MIS: 0 + +6. MSI quirks + +Several PCI chipsets or devices are known to not support MSI. +The PCI stack provides 3 possible levels of MSI disabling: +* on a single device +* on all devices behind a specific bridge +* globally + +6.1. Disabling MSI on a single device + +Under some circumstances it might be required to disable MSI on a +single device. This may be achieved by either not calling pci_enable_msi() +or all, or setting the pci_dev->no_msi flag before (most of the time +in a quirk). + +6.2. Disabling MSI below a bridge + +The vast majority of MSI quirks are required by PCI bridges not +being able to route MSI between busses. In this case, MSI have to be +disabled on all devices behind this bridge. It is achieves by setting +the PCI_BUS_FLAGS_NO_MSI flag in the pci_bus->bus_flags of the bridge +subordinate bus. There is no need to set the same flag on bridges that +are below the broken bridge. When pci_enable_msi() is called to enable +MSI on a device, pci_msi_supported() takes care of checking the NO_MSI +flag in all parent busses of the device. + +Some bridges actually support dynamic MSI support enabling/disabling +by changing some bits in their PCI configuration space (especially +the Hypertransport chipsets such as the nVidia nForce and Serverworks +HT2000). It may then be required to update the NO_MSI flag on the +corresponding devices in the sysfs hierarchy. To enable MSI support +on device "0000:00:0e", do: + + echo 1 > /sys/bus/pci/devices/0000:00:0e/msi_bus + +To disable MSI support, echo 0 instead of 1. Note that it should be +used with caution since changing this value might break interrupts. + +6.3. Disabling MSI globally + +Some extreme cases may require to disable MSI globally on the system. +For now, the only known case is a Serverworks PCI-X chipsets (MSI are +not supported on several busses that are not all connected to the +chipset in the Linux PCI hierarchy). In the vast majority of other +cases, disabling only behind a specific bridge is enough. + +For debugging purpose, the user may also pass pci=nomsi on the kernel +command-line to explicitly disable MSI globally. But, once the appro- +priate quirks are added to the kernel, this option should not be +required anymore. + +6.4. Finding why MSI cannot be enabled on a device + +Assuming that MSI are not enabled on a device, you should look at +dmesg to find messages that quirks may output when disabling MSI +on some devices, some bridges or even globally. +Then, lspci -t gives the list of bridges above a device. Reading +/sys/bus/pci/devices/0000:00:0e/msi_bus will tell you whether MSI +are enabled (1) or disabled (0). In 0 is found in a single bridge +msi_bus file above the device, MSI cannot be enabled. + +7. FAQ + +Q1. Are there any limitations on using the MSI? + +A1. If the PCI device supports MSI and conforms to the +specification and the platform supports the APIC local bus, +then using MSI should work. + +Q2. Will it work on all the Pentium processors (P3, P4, Xeon, +AMD processors)? In P3 IPI's are transmitted on the APIC local +bus and in P4 and Xeon they are transmitted on the system +bus. Are there any implications with this? + +A2. MSI support enables a PCI device sending an inbound +memory write (0xfeexxxxx as target address) on its PCI bus +directly to the FSB. Since the message address has a +redirection hint bit cleared, it should work. + +Q3. The target address 0xfeexxxxx will be translated by the +Host Bridge into an interrupt message. Are there any +limitations on the chipsets such as Intel 8xx, Intel e7xxx, +or VIA? + +A3. If these chipsets support an inbound memory write with +target address set as 0xfeexxxxx, as conformed to PCI +specification 2.3 or latest, then it should work. + +Q4. From the driver point of view, if the MSI is lost because +of errors occurring during inbound memory write, then it may +wait forever. Is there a mechanism for it to recover? + +A4. Since the target of the transaction is an inbound memory +write, all transaction termination conditions (Retry, +Master-Abort, Target-Abort, or normal completion) are +supported. A device sending an MSI must abide by all the PCI +rules and conditions regarding that inbound memory write. So, +if a retry is signaled it must retry, etc... We believe that +the recommendation for Abort is also a retry (refer to PCI +specification 2.3 or latest). diff --git a/Documentation/README.DAC960 b/Documentation/README.DAC960 deleted file mode 100644 index 0e8f618ab534..000000000000 --- a/Documentation/README.DAC960 +++ /dev/null @@ -1,756 +0,0 @@ - Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers - - Version 2.2.11 for Linux 2.2.19 - Version 2.4.11 for Linux 2.4.12 - - PRODUCTION RELEASE - - 11 October 2001 - - Leonard N. Zubkoff - Dandelion Digital - lnz@dandelion.com - - Copyright 1998-2001 by Leonard N. Zubkoff - - - INTRODUCTION - -Mylex, Inc. designs and manufactures a variety of high performance PCI RAID -controllers. Mylex Corporation is located at 34551 Ardenwood Blvd., Fremont, -California 94555, USA and can be reached at 510.796.6100 or on the World Wide -Web at http://www.mylex.com. Mylex Technical Support can be reached by -electronic mail at mylexsup@us.ibm.com, by voice at 510.608.2400, or by FAX at -510.745.7715. Contact information for offices in Europe and Japan is available -on their Web site. - -The latest information on Linux support for DAC960 PCI RAID Controllers, as -well as the most recent release of this driver, will always be available from -my Linux Home Page at URL "http://www.dandelion.com/Linux/". The Linux DAC960 -driver supports all current Mylex PCI RAID controllers including the new -eXtremeRAID 2000/3000 and AcceleRAID 352/170/160 models which have an entirely -new firmware interface from the older eXtremeRAID 1100, AcceleRAID 150/200/250, -and DAC960PJ/PG/PU/PD/PL. See below for a complete controller list as well as -minimum firmware version requirements. For simplicity, in most places this -documentation refers to DAC960 generically rather than explicitly listing all -the supported models. - -Driver bug reports should be sent via electronic mail to "lnz@dandelion.com". -Please include with the bug report the complete configuration messages reported -by the driver at startup, along with any subsequent system messages relevant to -the controller's operation, and a detailed description of your system's -hardware configuration. Driver bugs are actually quite rare; if you encounter -problems with disks being marked offline, for example, please contact Mylex -Technical Support as the problem is related to the hardware configuration -rather than the Linux driver. - -Please consult the RAID controller documentation for detailed information -regarding installation and configuration of the controllers. This document -primarily provides information specific to the Linux support. - - - DRIVER FEATURES - -The DAC960 RAID controllers are supported solely as high performance RAID -controllers, not as interfaces to arbitrary SCSI devices. The Linux DAC960 -driver operates at the block device level, the same level as the SCSI and IDE -drivers. Unlike other RAID controllers currently supported on Linux, the -DAC960 driver is not dependent on the SCSI subsystem, and hence avoids all the -complexity and unnecessary code that would be associated with an implementation -as a SCSI driver. The DAC960 driver is designed for as high a performance as -possible with no compromises or extra code for compatibility with lower -performance devices. The DAC960 driver includes extensive error logging and -online configuration management capabilities. Except for initial configuration -of the controller and adding new disk drives, most everything can be handled -from Linux while the system is operational. - -The DAC960 driver is architected to support up to 8 controllers per system. -Each DAC960 parallel SCSI controller can support up to 15 disk drives per -channel, for a maximum of 60 drives on a four channel controller; the fibre -channel eXtremeRAID 3000 controller supports up to 125 disk drives per loop for -a total of 250 drives. The drives installed on a controller are divided into -one or more "Drive Groups", and then each Drive Group is subdivided further -into 1 to 32 "Logical Drives". Each Logical Drive has a specific RAID Level -and caching policy associated with it, and it appears to Linux as a single -block device. Logical Drives are further subdivided into up to 7 partitions -through the normal Linux and PC disk partitioning schemes. Logical Drives are -also known as "System Drives", and Drive Groups are also called "Packs". Both -terms are in use in the Mylex documentation; I have chosen to standardize on -the more generic "Logical Drive" and "Drive Group". - -DAC960 RAID disk devices are named in the style of the obsolete Device File -System (DEVFS). The device corresponding to Logical Drive D on Controller C -is referred to as /dev/rd/cCdD, and the partitions are called /dev/rd/cCdDp1 -through /dev/rd/cCdDp7. For example, partition 3 of Logical Drive 5 on -Controller 2 is referred to as /dev/rd/c2d5p3. Note that unlike with SCSI -disks the device names will not change in the event of a disk drive failure. -The DAC960 driver is assigned major numbers 48 - 55 with one major number per -controller. The 8 bits of minor number are divided into 5 bits for the Logical -Drive and 3 bits for the partition. - - - SUPPORTED DAC960/AcceleRAID/eXtremeRAID PCI RAID CONTROLLERS - -The following list comprises the supported DAC960, AcceleRAID, and eXtremeRAID -PCI RAID Controllers as of the date of this document. It is recommended that -anyone purchasing a Mylex PCI RAID Controller not in the following table -contact the author beforehand to verify that it is or will be supported. - -eXtremeRAID 3000 - 1 Wide Ultra-2/LVD SCSI channel - 2 External Fibre FC-AL channels - 233MHz StrongARM SA 110 Processor - 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) - 32MB/64MB ECC SDRAM Memory - -eXtremeRAID 2000 - 4 Wide Ultra-160 LVD SCSI channels - 233MHz StrongARM SA 110 Processor - 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) - 32MB/64MB ECC SDRAM Memory - -AcceleRAID 352 - 2 Wide Ultra-160 LVD SCSI channels - 100MHz Intel i960RN RISC Processor - 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) - 32MB/64MB ECC SDRAM Memory - -AcceleRAID 170 - 1 Wide Ultra-160 LVD SCSI channel - 100MHz Intel i960RM RISC Processor - 16MB/32MB/64MB ECC SDRAM Memory - -AcceleRAID 160 (AcceleRAID 170LP) - 1 Wide Ultra-160 LVD SCSI channel - 100MHz Intel i960RS RISC Processor - Built in 16M ECC SDRAM Memory - PCI Low Profile Form Factor - fit for 2U height - -eXtremeRAID 1100 (DAC1164P) - 3 Wide Ultra-2/LVD SCSI channels - 233MHz StrongARM SA 110 Processor - 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) - 16MB/32MB/64MB Parity SDRAM Memory with Battery Backup - -AcceleRAID 250 (DAC960PTL1) - Uses onboard Symbios SCSI chips on certain motherboards - Also includes one onboard Wide Ultra-2/LVD SCSI Channel - 66MHz Intel i960RD RISC Processor - 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory - -AcceleRAID 200 (DAC960PTL0) - Uses onboard Symbios SCSI chips on certain motherboards - Includes no onboard SCSI Channels - 66MHz Intel i960RD RISC Processor - 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory - -AcceleRAID 150 (DAC960PRL) - Uses onboard Symbios SCSI chips on certain motherboards - Also includes one onboard Wide Ultra-2/LVD SCSI Channel - 33MHz Intel i960RP RISC Processor - 4MB Parity EDO Memory - -DAC960PJ 1/2/3 Wide Ultra SCSI-3 Channels - 66MHz Intel i960RD RISC Processor - 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory - -DAC960PG 1/2/3 Wide Ultra SCSI-3 Channels - 33MHz Intel i960RP RISC Processor - 4MB/8MB ECC EDO Memory - -DAC960PU 1/2/3 Wide Ultra SCSI-3 Channels - Intel i960CF RISC Processor - 4MB/8MB EDRAM or 2MB/4MB/8MB/16MB/32MB DRAM Memory - -DAC960PD 1/2/3 Wide Fast SCSI-2 Channels - Intel i960CF RISC Processor - 4MB/8MB EDRAM or 2MB/4MB/8MB/16MB/32MB DRAM Memory - -DAC960PL 1/2/3 Wide Fast SCSI-2 Channels - Intel i960 RISC Processor - 2MB/4MB/8MB/16MB/32MB DRAM Memory - -DAC960P 1/2/3 Wide Fast SCSI-2 Channels - Intel i960 RISC Processor - 2MB/4MB/8MB/16MB/32MB DRAM Memory - -For the eXtremeRAID 2000/3000 and AcceleRAID 352/170/160, firmware version -6.00-01 or above is required. - -For the eXtremeRAID 1100, firmware version 5.06-0-52 or above is required. - -For the AcceleRAID 250, 200, and 150, firmware version 4.06-0-57 or above is -required. - -For the DAC960PJ and DAC960PG, firmware version 4.06-0-00 or above is required. - -For the DAC960PU, DAC960PD, DAC960PL, and DAC960P, either firmware version -3.51-0-04 or above is required (for dual Flash ROM controllers), or firmware -version 2.73-0-00 or above is required (for single Flash ROM controllers) - -Please note that not all SCSI disk drives are suitable for use with DAC960 -controllers, and only particular firmware versions of any given model may -actually function correctly. Similarly, not all motherboards have a BIOS that -properly initializes the AcceleRAID 250, AcceleRAID 200, AcceleRAID 150, -DAC960PJ, and DAC960PG because the Intel i960RD/RP is a multi-function device. -If in doubt, contact Mylex RAID Technical Support (mylexsup@us.ibm.com) to -verify compatibility. Mylex makes available a hard disk compatibility list at -http://www.mylex.com/support/hdcomp/hd-lists.html. - - - DRIVER INSTALLATION - -This distribution was prepared for Linux kernel version 2.2.19 or 2.4.12. - -To install the DAC960 RAID driver, you may use the following commands, -replacing "/usr/src" with wherever you keep your Linux kernel source tree: - - cd /usr/src - tar -xvzf DAC960-2.2.11.tar.gz (or DAC960-2.4.11.tar.gz) - mv README.DAC960 linux/Documentation - mv DAC960.[ch] linux/drivers/block - patch -p0 < DAC960.patch (if DAC960.patch is included) - cd linux - make config - make bzImage (or zImage) - -Then install "arch/i386/boot/bzImage" or "arch/i386/boot/zImage" as your -standard kernel, run lilo if appropriate, and reboot. - -To create the necessary devices in /dev, the "make_rd" script included in -"DAC960-Utilities.tar.gz" from http://www.dandelion.com/Linux/ may be used. -LILO 21 and FDISK v2.9 include DAC960 support; also included in this archive -are patches to LILO 20 and FDISK v2.8 that add DAC960 support, along with -statically linked executables of LILO and FDISK. This modified version of LILO -will allow booting from a DAC960 controller and/or mounting the root file -system from a DAC960. - -Red Hat Linux 6.0 and SuSE Linux 6.1 include support for Mylex PCI RAID -controllers. Installing directly onto a DAC960 may be problematic from other -Linux distributions until their installation utilities are updated. - - - INSTALLATION NOTES - -Before installing Linux or adding DAC960 logical drives to an existing Linux -system, the controller must first be configured to provide one or more logical -drives using the BIOS Configuration Utility or DACCF. Please note that since -there are only at most 6 usable partitions on each logical drive, systems -requiring more partitions should subdivide a drive group into multiple logical -drives, each of which can have up to 6 usable partitions. Also, note that with -large disk arrays it is advisable to enable the 8GB BIOS Geometry (255/63) -rather than accepting the default 2GB BIOS Geometry (128/32); failing to so do -will cause the logical drive geometry to have more than 65535 cylinders which -will make it impossible for FDISK to be used properly. The 8GB BIOS Geometry -can be enabled by configuring the DAC960 BIOS, which is accessible via Alt-M -during the BIOS initialization sequence. - -For maximum performance and the most efficient E2FSCK performance, it is -recommended that EXT2 file systems be built with a 4KB block size and 16 block -stride to match the DAC960 controller's 64KB default stripe size. The command -"mke2fs -b 4096 -R stride=16 " is appropriate. Unless there will be a -large number of small files on the file systems, it is also beneficial to add -the "-i 16384" option to increase the bytes per inode parameter thereby -reducing the file system metadata. Finally, on systems that will only be run -with Linux 2.2 or later kernels it is beneficial to enable sparse superblocks -with the "-s 1" option. - - - DAC960 ANNOUNCEMENTS MAILING LIST - -The DAC960 Announcements Mailing List provides a forum for informing Linux -users of new driver releases and other announcements regarding Linux support -for DAC960 PCI RAID Controllers. To join the mailing list, send a message to -"dac960-announce-request@dandelion.com" with the line "subscribe" in the -message body. - - - CONTROLLER CONFIGURATION AND STATUS MONITORING - -The DAC960 RAID controllers running firmware 4.06 or above include a Background -Initialization facility so that system downtime is minimized both for initial -installation and subsequent configuration of additional storage. The BIOS -Configuration Utility (accessible via Alt-R during the BIOS initialization -sequence) is used to quickly configure the controller, and then the logical -drives that have been created are available for immediate use even while they -are still being initialized by the controller. The primary need for online -configuration and status monitoring is then to avoid system downtime when disk -drives fail and must be replaced. Mylex's online monitoring and configuration -utilities are being ported to Linux and will become available at some point in -the future. Note that with a SAF-TE (SCSI Accessed Fault-Tolerant Enclosure) -enclosure, the controller is able to rebuild failed drives automatically as -soon as a drive replacement is made available. - -The primary interfaces for controller configuration and status monitoring are -special files created in the /proc/rd/... hierarchy along with the normal -system console logging mechanism. Whenever the system is operating, the DAC960 -driver queries each controller for status information every 10 seconds, and -checks for additional conditions every 60 seconds. The initial status of each -controller is always available for controller N in /proc/rd/cN/initial_status, -and the current status as of the last status monitoring query is available in -/proc/rd/cN/current_status. In addition, status changes are also logged by the -driver to the system console and will appear in the log files maintained by -syslog. The progress of asynchronous rebuild or consistency check operations -is also available in /proc/rd/cN/current_status, and progress messages are -logged to the system console at most every 60 seconds. - -Starting with the 2.2.3/2.0.3 versions of the driver, the status information -available in /proc/rd/cN/initial_status and /proc/rd/cN/current_status has been -augmented to include the vendor, model, revision, and serial number (if -available) for each physical device found connected to the controller: - -***** DAC960 RAID Driver Version 2.2.3 of 19 August 1999 ***** -Copyright 1998-1999 by Leonard N. Zubkoff -Configuring Mylex DAC960PRL PCI RAID Controller - Firmware Version: 4.07-0-07, Channels: 1, Memory Size: 16MB - PCI Bus: 1, Device: 4, Function: 1, I/O Address: Unassigned - PCI Address: 0xFE300000 mapped at 0xA0800000, IRQ Channel: 21 - Controller Queue Depth: 128, Maximum Blocks per Command: 128 - Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 - Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 - SAF-TE Enclosure Management Enabled - Physical Devices: - 0:0 Vendor: IBM Model: DRVS09D Revision: 0270 - Serial Number: 68016775HA - Disk Status: Online, 17928192 blocks - 0:1 Vendor: IBM Model: DRVS09D Revision: 0270 - Serial Number: 68004E53HA - Disk Status: Online, 17928192 blocks - 0:2 Vendor: IBM Model: DRVS09D Revision: 0270 - Serial Number: 13013935HA - Disk Status: Online, 17928192 blocks - 0:3 Vendor: IBM Model: DRVS09D Revision: 0270 - Serial Number: 13016897HA - Disk Status: Online, 17928192 blocks - 0:4 Vendor: IBM Model: DRVS09D Revision: 0270 - Serial Number: 68019905HA - Disk Status: Online, 17928192 blocks - 0:5 Vendor: IBM Model: DRVS09D Revision: 0270 - Serial Number: 68012753HA - Disk Status: Online, 17928192 blocks - 0:6 Vendor: ESG-SHV Model: SCA HSBP M6 Revision: 0.61 - Logical Drives: - /dev/rd/c0d0: RAID-5, Online, 89640960 blocks, Write Thru - No Rebuild or Consistency Check in Progress - -To simplify the monitoring process for custom software, the special file -/proc/rd/status returns "OK" when all DAC960 controllers in the system are -operating normally and no failures have occurred, or "ALERT" if any logical -drives are offline or critical or any non-standby physical drives are dead. - -Configuration commands for controller N are available via the special file -/proc/rd/cN/user_command. A human readable command can be written to this -special file to initiate a configuration operation, and the results of the -operation can then be read back from the special file in addition to being -logged to the system console. The shell command sequence - - echo "" > /proc/rd/c0/user_command - cat /proc/rd/c0/user_command - -is typically used to execute configuration commands. The configuration -commands are: - - flush-cache - - The "flush-cache" command flushes the controller's cache. The system - automatically flushes the cache at shutdown or if the driver module is - unloaded, so this command is only needed to be certain a write back cache - is flushed to disk before the system is powered off by a command to a UPS. - Note that the flush-cache command also stops an asynchronous rebuild or - consistency check, so it should not be used except when the system is being - halted. - - kill : - - The "kill" command marks the physical drive : as DEAD. - This command is provided primarily for testing, and should not be used - during normal system operation. - - make-online : - - The "make-online" command changes the physical drive : - from status DEAD to status ONLINE. In cases where multiple physical drives - have been killed simultaneously, this command may be used to bring all but - one of them back online, after which a rebuild to the final drive is - necessary. - - Warning: make-online should only be used on a dead physical drive that is - an active part of a drive group, never on a standby drive. The command - should never be used on a dead drive that is part of a critical logical - drive; rebuild should be used if only a single drive is dead. - - make-standby : - - The "make-standby" command changes physical drive : - from status DEAD to status STANDBY. It should only be used in cases where - a dead drive was replaced after an automatic rebuild was performed onto a - standby drive. It cannot be used to add a standby drive to the controller - configuration if one was not created initially; the BIOS Configuration - Utility must be used for that currently. - - rebuild : - - The "rebuild" command initiates an asynchronous rebuild onto physical drive - :. It should only be used when a dead drive has been - replaced. - - check-consistency - - The "check-consistency" command initiates an asynchronous consistency check - of with automatic restoration. It can be used - whenever it is desired to verify the consistency of the redundancy - information. - - cancel-rebuild - cancel-consistency-check - - The "cancel-rebuild" and "cancel-consistency-check" commands cancel any - rebuild or consistency check operations previously initiated. - - - EXAMPLE I - DRIVE FAILURE WITHOUT A STANDBY DRIVE - -The following annotated logs demonstrate the controller configuration and and -online status monitoring capabilities of the Linux DAC960 Driver. The test -configuration comprises 6 1GB Quantum Atlas I disk drives on two channels of a -DAC960PJ controller. The physical drives are configured into a single drive -group without a standby drive, and the drive group has been configured into two -logical drives, one RAID-5 and one RAID-6. Note that these logs are from an -earlier version of the driver and the messages have changed somewhat with newer -releases, but the functionality remains similar. First, here is the current -status of the RAID configuration: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status -***** DAC960 RAID Driver Version 2.0.0 of 23 March 1999 ***** -Copyright 1998-1999 by Leonard N. Zubkoff -Configuring Mylex DAC960PJ PCI RAID Controller - Firmware Version: 4.06-0-08, Channels: 3, Memory Size: 8MB - PCI Bus: 0, Device: 19, Function: 1, I/O Address: Unassigned - PCI Address: 0xFD4FC000 mapped at 0x8807000, IRQ Channel: 9 - Controller Queue Depth: 128, Maximum Blocks per Command: 128 - Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 - Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Online, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Online, 5498880 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Online, 3305472 blocks, Write Thru - No Rebuild or Consistency Check in Progress - -gwynedd:/u/lnz# cat /proc/rd/status -OK - -The above messages indicate that everything is healthy, and /proc/rd/status -returns "OK" indicating that there are no problems with any DAC960 controller -in the system. For demonstration purposes, while I/O is active Physical Drive -1:1 is now disconnected, simulating a drive failure. The failure is noted by -the driver within 10 seconds of the controller's having detected it, and the -driver logs the following console status messages indicating that Logical -Drives 0 and 1 are now CRITICAL as a result of Physical Drive 1:1 being DEAD: - -DAC960#0: Physical Drive 1:2 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 -DAC960#0: Physical Drive 1:3 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 -DAC960#0: Physical Drive 1:1 killed because of timeout on SCSI command -DAC960#0: Physical Drive 1:1 is now DEAD -DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now CRITICAL -DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now CRITICAL - -The Sense Keys logged here are just Check Condition / Unit Attention conditions -arising from a SCSI bus reset that is forced by the controller during its error -recovery procedures. Concurrently with the above, the driver status available -from /proc/rd also reflects the drive failure. The status message in -/proc/rd/status has changed from "OK" to "ALERT": - -gwynedd:/u/lnz# cat /proc/rd/status -ALERT - -and /proc/rd/c0/current_status has been updated: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Dead, 2201600 blocks - 1:2 - Disk: Online, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Critical, 5498880 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Critical, 3305472 blocks, Write Thru - No Rebuild or Consistency Check in Progress - -Since there are no standby drives configured, the system can continue to access -the logical drives in a performance degraded mode until the failed drive is -replaced and a rebuild operation completed to restore the redundancy of the -logical drives. Once Physical Drive 1:1 is replaced with a properly -functioning drive, or if the physical drive was killed without having failed -(e.g., due to electrical problems on the SCSI bus), the user can instruct the -controller to initiate a rebuild operation onto the newly replaced drive: - -gwynedd:/u/lnz# echo "rebuild 1:1" > /proc/rd/c0/user_command -gwynedd:/u/lnz# cat /proc/rd/c0/user_command -Rebuild of Physical Drive 1:1 Initiated - -The echo command instructs the controller to initiate an asynchronous rebuild -operation onto Physical Drive 1:1, and the status message that results from the -operation is then available for reading from /proc/rd/c0/user_command, as well -as being logged to the console by the driver. - -Within 10 seconds of this command the driver logs the initiation of the -asynchronous rebuild operation: - -DAC960#0: Rebuild of Physical Drive 1:1 Initiated -DAC960#0: Physical Drive 1:1 Error Log: Sense Key = 6, ASC = 29, ASCQ = 01 -DAC960#0: Physical Drive 1:1 is now WRITE-ONLY -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 1% completed - -and /proc/rd/c0/current_status is updated: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Write-Only, 2201600 blocks - 1:2 - Disk: Online, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Critical, 5498880 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Critical, 3305472 blocks, Write Thru - Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 6% completed - -As the rebuild progresses, the current status in /proc/rd/c0/current_status is -updated every 10 seconds: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Write-Only, 2201600 blocks - 1:2 - Disk: Online, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Critical, 5498880 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Critical, 3305472 blocks, Write Thru - Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 15% completed - -and every minute a progress message is logged to the console by the driver: - -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 32% completed -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 63% completed -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 94% completed -DAC960#0: Rebuild in Progress: Logical Drive 1 (/dev/rd/c0d1) 94% completed - -Finally, the rebuild completes successfully. The driver logs the status of the -logical and physical drives and the rebuild completion: - -DAC960#0: Rebuild Completed Successfully -DAC960#0: Physical Drive 1:1 is now ONLINE -DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now ONLINE -DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now ONLINE - -/proc/rd/c0/current_status is updated: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Online, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Online, 5498880 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Online, 3305472 blocks, Write Thru - Rebuild Completed Successfully - -and /proc/rd/status indicates that everything is healthy once again: - -gwynedd:/u/lnz# cat /proc/rd/status -OK - - - EXAMPLE II - DRIVE FAILURE WITH A STANDBY DRIVE - -The following annotated logs demonstrate the controller configuration and and -online status monitoring capabilities of the Linux DAC960 Driver. The test -configuration comprises 6 1GB Quantum Atlas I disk drives on two channels of a -DAC960PJ controller. The physical drives are configured into a single drive -group with a standby drive, and the drive group has been configured into two -logical drives, one RAID-5 and one RAID-6. Note that these logs are from an -earlier version of the driver and the messages have changed somewhat with newer -releases, but the functionality remains similar. First, here is the current -status of the RAID configuration: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status -***** DAC960 RAID Driver Version 2.0.0 of 23 March 1999 ***** -Copyright 1998-1999 by Leonard N. Zubkoff -Configuring Mylex DAC960PJ PCI RAID Controller - Firmware Version: 4.06-0-08, Channels: 3, Memory Size: 8MB - PCI Bus: 0, Device: 19, Function: 1, I/O Address: Unassigned - PCI Address: 0xFD4FC000 mapped at 0x8807000, IRQ Channel: 9 - Controller Queue Depth: 128, Maximum Blocks per Command: 128 - Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 - Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Online, 2201600 blocks - 1:3 - Disk: Standby, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Online, 4399104 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Online, 2754560 blocks, Write Thru - No Rebuild or Consistency Check in Progress - -gwynedd:/u/lnz# cat /proc/rd/status -OK - -The above messages indicate that everything is healthy, and /proc/rd/status -returns "OK" indicating that there are no problems with any DAC960 controller -in the system. For demonstration purposes, while I/O is active Physical Drive -1:2 is now disconnected, simulating a drive failure. The failure is noted by -the driver within 10 seconds of the controller's having detected it, and the -driver logs the following console status messages: - -DAC960#0: Physical Drive 1:1 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 -DAC960#0: Physical Drive 1:3 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 -DAC960#0: Physical Drive 1:2 killed because of timeout on SCSI command -DAC960#0: Physical Drive 1:2 is now DEAD -DAC960#0: Physical Drive 1:2 killed because it was removed -DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now CRITICAL -DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now CRITICAL - -Since a standby drive is configured, the controller automatically begins -rebuilding onto the standby drive: - -DAC960#0: Physical Drive 1:3 is now WRITE-ONLY -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 4% completed - -Concurrently with the above, the driver status available from /proc/rd also -reflects the drive failure and automatic rebuild. The status message in -/proc/rd/status has changed from "OK" to "ALERT": - -gwynedd:/u/lnz# cat /proc/rd/status -ALERT - -and /proc/rd/c0/current_status has been updated: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Dead, 2201600 blocks - 1:3 - Disk: Write-Only, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Critical, 4399104 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Critical, 2754560 blocks, Write Thru - Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 4% completed - -As the rebuild progresses, the current status in /proc/rd/c0/current_status is -updated every 10 seconds: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Dead, 2201600 blocks - 1:3 - Disk: Write-Only, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Critical, 4399104 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Critical, 2754560 blocks, Write Thru - Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 40% completed - -and every minute a progress message is logged on the console by the driver: - -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 40% completed -DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 76% completed -DAC960#0: Rebuild in Progress: Logical Drive 1 (/dev/rd/c0d1) 66% completed -DAC960#0: Rebuild in Progress: Logical Drive 1 (/dev/rd/c0d1) 84% completed - -Finally, the rebuild completes successfully. The driver logs the status of the -logical and physical drives and the rebuild completion: - -DAC960#0: Rebuild Completed Successfully -DAC960#0: Physical Drive 1:3 is now ONLINE -DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now ONLINE -DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now ONLINE - -/proc/rd/c0/current_status is updated: - -***** DAC960 RAID Driver Version 2.0.0 of 23 March 1999 ***** -Copyright 1998-1999 by Leonard N. Zubkoff -Configuring Mylex DAC960PJ PCI RAID Controller - Firmware Version: 4.06-0-08, Channels: 3, Memory Size: 8MB - PCI Bus: 0, Device: 19, Function: 1, I/O Address: Unassigned - PCI Address: 0xFD4FC000 mapped at 0x8807000, IRQ Channel: 9 - Controller Queue Depth: 128, Maximum Blocks per Command: 128 - Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 - Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Dead, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Online, 4399104 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Online, 2754560 blocks, Write Thru - Rebuild Completed Successfully - -and /proc/rd/status indicates that everything is healthy once again: - -gwynedd:/u/lnz# cat /proc/rd/status -OK - -Note that the absence of a viable standby drive does not create an "ALERT" -status. Once dead Physical Drive 1:2 has been replaced, the controller must be -told that this has occurred and that the newly replaced drive should become the -new standby drive: - -gwynedd:/u/lnz# echo "make-standby 1:2" > /proc/rd/c0/user_command -gwynedd:/u/lnz# cat /proc/rd/c0/user_command -Make Standby of Physical Drive 1:2 Succeeded - -The echo command instructs the controller to make Physical Drive 1:2 into a -standby drive, and the status message that results from the operation is then -available for reading from /proc/rd/c0/user_command, as well as being logged to -the console by the driver. Within 60 seconds of this command the driver logs: - -DAC960#0: Physical Drive 1:2 Error Log: Sense Key = 6, ASC = 29, ASCQ = 01 -DAC960#0: Physical Drive 1:2 is now STANDBY -DAC960#0: Make Standby of Physical Drive 1:2 Succeeded - -and /proc/rd/c0/current_status is updated: - -gwynedd:/u/lnz# cat /proc/rd/c0/current_status - ... - Physical Devices: - 0:1 - Disk: Online, 2201600 blocks - 0:2 - Disk: Online, 2201600 blocks - 0:3 - Disk: Online, 2201600 blocks - 1:1 - Disk: Online, 2201600 blocks - 1:2 - Disk: Standby, 2201600 blocks - 1:3 - Disk: Online, 2201600 blocks - Logical Drives: - /dev/rd/c0d0: RAID-5, Online, 4399104 blocks, Write Thru - /dev/rd/c0d1: RAID-6, Online, 2754560 blocks, Write Thru - Rebuild Completed Successfully diff --git a/Documentation/README.cycladesZ b/Documentation/README.cycladesZ deleted file mode 100644 index 024a69443cc2..000000000000 --- a/Documentation/README.cycladesZ +++ /dev/null @@ -1,8 +0,0 @@ - -The Cyclades-Z must have firmware loaded onto the card before it will -operate. This operation should be performed during system startup, - -The firmware, loader program and the latest device driver code are -available from Cyclades at - ftp://ftp.cyclades.com/pub/cyclades/cyclades-z/linux/ - diff --git a/Documentation/accounting/.gitignore b/Documentation/accounting/.gitignore new file mode 100644 index 000000000000..86485203c4ae --- /dev/null +++ b/Documentation/accounting/.gitignore @@ -0,0 +1 @@ +getdelays diff --git a/Documentation/acpi/debug.txt b/Documentation/acpi/debug.txt new file mode 100644 index 000000000000..65bf47c46b6d --- /dev/null +++ b/Documentation/acpi/debug.txt @@ -0,0 +1,148 @@ + ACPI Debug Output + + +The ACPI CA, the Linux ACPI core, and some ACPI drivers can generate debug +output. This document describes how to use this facility. + +Compile-time configuration +-------------------------- + +ACPI debug output is globally enabled by CONFIG_ACPI_DEBUG. If this config +option is turned off, the debug messages are not even built into the +kernel. + +Boot- and run-time configuration +-------------------------------- + +When CONFIG_ACPI_DEBUG=y, you can select the component and level of messages +you're interested in. At boot-time, use the acpi.debug_layer and +acpi.debug_level kernel command line options. After boot, you can use the +debug_layer and debug_level files in /sys/module/acpi/parameters/ to control +the debug messages. + +debug_layer (component) +----------------------- + +The "debug_layer" is a mask that selects components of interest, e.g., a +specific driver or part of the ACPI interpreter. To build the debug_layer +bitmask, look for the "#define _COMPONENT" in an ACPI source file. + +You can set the debug_layer mask at boot-time using the acpi.debug_layer +command line argument, and you can change it after boot by writing values +to /sys/module/acpi/parameters/debug_layer. + +The possible components are defined in include/acpi/acoutput.h and +include/acpi/acpi_drivers.h. Reading /sys/module/acpi/parameters/debug_layer +shows the supported mask values, currently these: + + ACPI_UTILITIES 0x00000001 + ACPI_HARDWARE 0x00000002 + ACPI_EVENTS 0x00000004 + ACPI_TABLES 0x00000008 + ACPI_NAMESPACE 0x00000010 + ACPI_PARSER 0x00000020 + ACPI_DISPATCHER 0x00000040 + ACPI_EXECUTER 0x00000080 + ACPI_RESOURCES 0x00000100 + ACPI_CA_DEBUGGER 0x00000200 + ACPI_OS_SERVICES 0x00000400 + ACPI_CA_DISASSEMBLER 0x00000800 + ACPI_COMPILER 0x00001000 + ACPI_TOOLS 0x00002000 + ACPI_BUS_COMPONENT 0x00010000 + ACPI_AC_COMPONENT 0x00020000 + ACPI_BATTERY_COMPONENT 0x00040000 + ACPI_BUTTON_COMPONENT 0x00080000 + ACPI_SBS_COMPONENT 0x00100000 + ACPI_FAN_COMPONENT 0x00200000 + ACPI_PCI_COMPONENT 0x00400000 + ACPI_POWER_COMPONENT 0x00800000 + ACPI_CONTAINER_COMPONENT 0x01000000 + ACPI_SYSTEM_COMPONENT 0x02000000 + ACPI_THERMAL_COMPONENT 0x04000000 + ACPI_MEMORY_DEVICE_COMPONENT 0x08000000 + ACPI_VIDEO_COMPONENT 0x10000000 + ACPI_PROCESSOR_COMPONENT 0x20000000 + +debug_level +----------- + +The "debug_level" is a mask that selects different types of messages, e.g., +those related to initialization, method execution, informational messages, etc. +To build debug_level, look at the level specified in an ACPI_DEBUG_PRINT() +statement. + +The ACPI interpreter uses several different levels, but the Linux +ACPI core and ACPI drivers generally only use ACPI_LV_INFO. + +You can set the debug_level mask at boot-time using the acpi.debug_level +command line argument, and you can change it after boot by writing values +to /sys/module/acpi/parameters/debug_level. + +The possible levels are defined in include/acpi/acoutput.h. Reading +/sys/module/acpi/parameters/debug_level shows the supported mask values, +currently these: + + ACPI_LV_INIT 0x00000001 + ACPI_LV_DEBUG_OBJECT 0x00000002 + ACPI_LV_INFO 0x00000004 + ACPI_LV_INIT_NAMES 0x00000020 + ACPI_LV_PARSE 0x00000040 + ACPI_LV_LOAD 0x00000080 + ACPI_LV_DISPATCH 0x00000100 + ACPI_LV_EXEC 0x00000200 + ACPI_LV_NAMES 0x00000400 + ACPI_LV_OPREGION 0x00000800 + ACPI_LV_BFIELD 0x00001000 + ACPI_LV_TABLES 0x00002000 + ACPI_LV_VALUES 0x00004000 + ACPI_LV_OBJECTS 0x00008000 + ACPI_LV_RESOURCES 0x00010000 + ACPI_LV_USER_REQUESTS 0x00020000 + ACPI_LV_PACKAGE 0x00040000 + ACPI_LV_ALLOCATIONS 0x00100000 + ACPI_LV_FUNCTIONS 0x00200000 + ACPI_LV_OPTIMIZATIONS 0x00400000 + ACPI_LV_MUTEX 0x01000000 + ACPI_LV_THREADS 0x02000000 + ACPI_LV_IO 0x04000000 + ACPI_LV_INTERRUPTS 0x08000000 + ACPI_LV_AML_DISASSEMBLE 0x10000000 + ACPI_LV_VERBOSE_INFO 0x20000000 + ACPI_LV_FULL_TABLES 0x40000000 + ACPI_LV_EVENTS 0x80000000 + +Examples +-------- + +For example, drivers/acpi/bus.c contains this: + + #define _COMPONENT ACPI_BUS_COMPONENT + ... + ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device insertion detected\n")); + +To turn on this message, set the ACPI_BUS_COMPONENT bit in acpi.debug_layer +and the ACPI_LV_INFO bit in acpi.debug_level. (The ACPI_DEBUG_PRINT +statement uses ACPI_DB_INFO, which is macro based on the ACPI_LV_INFO +definition.) + +Enable all AML "Debug" output (stores to the Debug object while interpreting +AML) during boot: + + acpi.debug_layer=0xffffffff acpi.debug_level=0x2 + +Enable PCI and PCI interrupt routing debug messages: + + acpi.debug_layer=0x400000 acpi.debug_level=0x4 + +Enable all ACPI hardware-related messages: + + acpi.debug_layer=0x2 acpi.debug_level=0xffffffff + +Enable all ACPI_DB_INFO messages after boot: + + # echo 0x4 > /sys/module/acpi/parameters/debug_level + +Show all valid component values: + + # cat /sys/module/acpi/parameters/debug_layer diff --git a/Documentation/arm/empeg/README b/Documentation/arm/empeg/README deleted file mode 100644 index 09cc8d03ae58..000000000000 --- a/Documentation/arm/empeg/README +++ /dev/null @@ -1,13 +0,0 @@ -Empeg, Ltd's Empeg MP3 Car Audio Player - -The initial design is to go in your car, but you can use it at home, on a -boat... almost anywhere. The principle is to store CD-quality music using -MPEG technology onto a hard disk in the unit, and use the power of the -embedded computer to serve up the music you want. - -For more details, see: - - http://www.empeg.com - - - diff --git a/Documentation/arm/empeg/ir.txt b/Documentation/arm/empeg/ir.txt deleted file mode 100644 index 10a297450164..000000000000 --- a/Documentation/arm/empeg/ir.txt +++ /dev/null @@ -1,49 +0,0 @@ -Infra-red driver documentation. - -Mike Crowe -(C) Empeg Ltd 1999 - -Not a lot here yet :-) - -The Kenwood KCA-R6A remote control generates a sequence like the following: - -Go low for approx 16T (Around 9000us) -Go high for approx 8T (Around 4000us) -Go low for less than 2T (Around 750us) - -For each of the 32 bits - Go high for more than 2T (Around 1500us) == 1 - Go high for less than T (Around 400us) == 0 - Go low for less than 2T (Around 750us) - -Rather than repeat a signal when the button is held down certain buttons -generate the following code to indicate repetition. - -Go low for approx 16T -Go high for approx 4T -Go low for less than 2T - -(By removing the <2T from the start of the sequence and placing at the end - it can be considered a stop bit but I found it easier to deal with it at - the start). - -The 32 bits are encoded as XxYy where x and y are the actual data values -while X and Y are the logical inverses of the associated data values. Using -LSB first yields sensible codes for the numbers. - -All codes are of the form b9xx - -The numeric keys generate the code 0x where x is the number pressed. - -Tuner 1c -Tape 1d -CD 1e -CD-MD-CH 1f -Track- 0a -Track+ 0b -Rewind 0c -FF 0d -DNPP 5e -Play/Pause 0e -Vol+ 14 -Vol- 15 diff --git a/Documentation/arm/empeg/mkdevs b/Documentation/arm/empeg/mkdevs deleted file mode 100644 index 7a85e28d14f3..000000000000 --- a/Documentation/arm/empeg/mkdevs +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh -mknod /dev/display c 244 0 -mknod /dev/ir c 242 0 -mknod /dev/usb0 c 243 0 -mknod /dev/audio c 245 4 -mknod /dev/dsp c 245 3 -mknod /dev/mixer c 245 0 -mknod /dev/empeg_state c 246 0 -mknod /dev/radio0 c 81 64 -ln -sf radio0 radio -ln -sf usb0 usb diff --git a/Documentation/arm/mem_alignment b/Documentation/arm/mem_alignment index d145ccca169a..c7c7a114c78c 100644 --- a/Documentation/arm/mem_alignment +++ b/Documentation/arm/mem_alignment @@ -24,7 +24,7 @@ real bad - it changes the behaviour of all unaligned instructions in user space, and might cause programs to fail unexpectedly. To change the alignment trap behavior, simply echo a number into -/proc/sys/debug/alignment. The number is made up from various bits: +/proc/cpu/alignment. The number is made up from various bits: bit behavior when set --- ----------------- diff --git a/Documentation/auxdisplay/.gitignore b/Documentation/auxdisplay/.gitignore new file mode 100644 index 000000000000..7af222860a96 --- /dev/null +++ b/Documentation/auxdisplay/.gitignore @@ -0,0 +1 @@ +cfag12864b-example diff --git a/Documentation/blockdev/00-INDEX b/Documentation/blockdev/00-INDEX new file mode 100644 index 000000000000..86f054c47013 --- /dev/null +++ b/Documentation/blockdev/00-INDEX @@ -0,0 +1,16 @@ +00-INDEX + - this file +README.DAC960 + - info on Mylex DAC960/DAC1100 PCI RAID Controller Driver for Linux. +cciss.txt + - info, major/minor #'s for Compaq's SMART Array Controllers. +cpqarray.txt + - info on using Compaq's SMART2 Intelligent Disk Array Controllers. +floppy.txt + - notes and driver options for the floppy disk driver. +nbd.txt + - info on a TCP implementation of a network block device. +paride.txt + - information about the parallel port IDE subsystem. +ramdisk.txt + - short guide on how to set up and use the RAM disk. diff --git a/Documentation/blockdev/README.DAC960 b/Documentation/blockdev/README.DAC960 new file mode 100644 index 000000000000..0e8f618ab534 --- /dev/null +++ b/Documentation/blockdev/README.DAC960 @@ -0,0 +1,756 @@ + Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers + + Version 2.2.11 for Linux 2.2.19 + Version 2.4.11 for Linux 2.4.12 + + PRODUCTION RELEASE + + 11 October 2001 + + Leonard N. Zubkoff + Dandelion Digital + lnz@dandelion.com + + Copyright 1998-2001 by Leonard N. Zubkoff + + + INTRODUCTION + +Mylex, Inc. designs and manufactures a variety of high performance PCI RAID +controllers. Mylex Corporation is located at 34551 Ardenwood Blvd., Fremont, +California 94555, USA and can be reached at 510.796.6100 or on the World Wide +Web at http://www.mylex.com. Mylex Technical Support can be reached by +electronic mail at mylexsup@us.ibm.com, by voice at 510.608.2400, or by FAX at +510.745.7715. Contact information for offices in Europe and Japan is available +on their Web site. + +The latest information on Linux support for DAC960 PCI RAID Controllers, as +well as the most recent release of this driver, will always be available from +my Linux Home Page at URL "http://www.dandelion.com/Linux/". The Linux DAC960 +driver supports all current Mylex PCI RAID controllers including the new +eXtremeRAID 2000/3000 and AcceleRAID 352/170/160 models which have an entirely +new firmware interface from the older eXtremeRAID 1100, AcceleRAID 150/200/250, +and DAC960PJ/PG/PU/PD/PL. See below for a complete controller list as well as +minimum firmware version requirements. For simplicity, in most places this +documentation refers to DAC960 generically rather than explicitly listing all +the supported models. + +Driver bug reports should be sent via electronic mail to "lnz@dandelion.com". +Please include with the bug report the complete configuration messages reported +by the driver at startup, along with any subsequent system messages relevant to +the controller's operation, and a detailed description of your system's +hardware configuration. Driver bugs are actually quite rare; if you encounter +problems with disks being marked offline, for example, please contact Mylex +Technical Support as the problem is related to the hardware configuration +rather than the Linux driver. + +Please consult the RAID controller documentation for detailed information +regarding installation and configuration of the controllers. This document +primarily provides information specific to the Linux support. + + + DRIVER FEATURES + +The DAC960 RAID controllers are supported solely as high performance RAID +controllers, not as interfaces to arbitrary SCSI devices. The Linux DAC960 +driver operates at the block device level, the same level as the SCSI and IDE +drivers. Unlike other RAID controllers currently supported on Linux, the +DAC960 driver is not dependent on the SCSI subsystem, and hence avoids all the +complexity and unnecessary code that would be associated with an implementation +as a SCSI driver. The DAC960 driver is designed for as high a performance as +possible with no compromises or extra code for compatibility with lower +performance devices. The DAC960 driver includes extensive error logging and +online configuration management capabilities. Except for initial configuration +of the controller and adding new disk drives, most everything can be handled +from Linux while the system is operational. + +The DAC960 driver is architected to support up to 8 controllers per system. +Each DAC960 parallel SCSI controller can support up to 15 disk drives per +channel, for a maximum of 60 drives on a four channel controller; the fibre +channel eXtremeRAID 3000 controller supports up to 125 disk drives per loop for +a total of 250 drives. The drives installed on a controller are divided into +one or more "Drive Groups", and then each Drive Group is subdivided further +into 1 to 32 "Logical Drives". Each Logical Drive has a specific RAID Level +and caching policy associated with it, and it appears to Linux as a single +block device. Logical Drives are further subdivided into up to 7 partitions +through the normal Linux and PC disk partitioning schemes. Logical Drives are +also known as "System Drives", and Drive Groups are also called "Packs". Both +terms are in use in the Mylex documentation; I have chosen to standardize on +the more generic "Logical Drive" and "Drive Group". + +DAC960 RAID disk devices are named in the style of the obsolete Device File +System (DEVFS). The device corresponding to Logical Drive D on Controller C +is referred to as /dev/rd/cCdD, and the partitions are called /dev/rd/cCdDp1 +through /dev/rd/cCdDp7. For example, partition 3 of Logical Drive 5 on +Controller 2 is referred to as /dev/rd/c2d5p3. Note that unlike with SCSI +disks the device names will not change in the event of a disk drive failure. +The DAC960 driver is assigned major numbers 48 - 55 with one major number per +controller. The 8 bits of minor number are divided into 5 bits for the Logical +Drive and 3 bits for the partition. + + + SUPPORTED DAC960/AcceleRAID/eXtremeRAID PCI RAID CONTROLLERS + +The following list comprises the supported DAC960, AcceleRAID, and eXtremeRAID +PCI RAID Controllers as of the date of this document. It is recommended that +anyone purchasing a Mylex PCI RAID Controller not in the following table +contact the author beforehand to verify that it is or will be supported. + +eXtremeRAID 3000 + 1 Wide Ultra-2/LVD SCSI channel + 2 External Fibre FC-AL channels + 233MHz StrongARM SA 110 Processor + 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) + 32MB/64MB ECC SDRAM Memory + +eXtremeRAID 2000 + 4 Wide Ultra-160 LVD SCSI channels + 233MHz StrongARM SA 110 Processor + 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) + 32MB/64MB ECC SDRAM Memory + +AcceleRAID 352 + 2 Wide Ultra-160 LVD SCSI channels + 100MHz Intel i960RN RISC Processor + 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) + 32MB/64MB ECC SDRAM Memory + +AcceleRAID 170 + 1 Wide Ultra-160 LVD SCSI channel + 100MHz Intel i960RM RISC Processor + 16MB/32MB/64MB ECC SDRAM Memory + +AcceleRAID 160 (AcceleRAID 170LP) + 1 Wide Ultra-160 LVD SCSI channel + 100MHz Intel i960RS RISC Processor + Built in 16M ECC SDRAM Memory + PCI Low Profile Form Factor - fit for 2U height + +eXtremeRAID 1100 (DAC1164P) + 3 Wide Ultra-2/LVD SCSI channels + 233MHz StrongARM SA 110 Processor + 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots) + 16MB/32MB/64MB Parity SDRAM Memory with Battery Backup + +AcceleRAID 250 (DAC960PTL1) + Uses onboard Symbios SCSI chips on certain motherboards + Also includes one onboard Wide Ultra-2/LVD SCSI Channel + 66MHz Intel i960RD RISC Processor + 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory + +AcceleRAID 200 (DAC960PTL0) + Uses onboard Symbios SCSI chips on certain motherboards + Includes no onboard SCSI Channels + 66MHz Intel i960RD RISC Processor + 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory + +AcceleRAID 150 (DAC960PRL) + Uses onboard Symbios SCSI chips on certain motherboards + Also includes one onboard Wide Ultra-2/LVD SCSI Channel + 33MHz Intel i960RP RISC Processor + 4MB Parity EDO Memory + +DAC960PJ 1/2/3 Wide Ultra SCSI-3 Channels + 66MHz Intel i960RD RISC Processor + 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory + +DAC960PG 1/2/3 Wide Ultra SCSI-3 Channels + 33MHz Intel i960RP RISC Processor + 4MB/8MB ECC EDO Memory + +DAC960PU 1/2/3 Wide Ultra SCSI-3 Channels + Intel i960CF RISC Processor + 4MB/8MB EDRAM or 2MB/4MB/8MB/16MB/32MB DRAM Memory + +DAC960PD 1/2/3 Wide Fast SCSI-2 Channels + Intel i960CF RISC Processor + 4MB/8MB EDRAM or 2MB/4MB/8MB/16MB/32MB DRAM Memory + +DAC960PL 1/2/3 Wide Fast SCSI-2 Channels + Intel i960 RISC Processor + 2MB/4MB/8MB/16MB/32MB DRAM Memory + +DAC960P 1/2/3 Wide Fast SCSI-2 Channels + Intel i960 RISC Processor + 2MB/4MB/8MB/16MB/32MB DRAM Memory + +For the eXtremeRAID 2000/3000 and AcceleRAID 352/170/160, firmware version +6.00-01 or above is required. + +For the eXtremeRAID 1100, firmware version 5.06-0-52 or above is required. + +For the AcceleRAID 250, 200, and 150, firmware version 4.06-0-57 or above is +required. + +For the DAC960PJ and DAC960PG, firmware version 4.06-0-00 or above is required. + +For the DAC960PU, DAC960PD, DAC960PL, and DAC960P, either firmware version +3.51-0-04 or above is required (for dual Flash ROM controllers), or firmware +version 2.73-0-00 or above is required (for single Flash ROM controllers) + +Please note that not all SCSI disk drives are suitable for use with DAC960 +controllers, and only particular firmware versions of any given model may +actually function correctly. Similarly, not all motherboards have a BIOS that +properly initializes the AcceleRAID 250, AcceleRAID 200, AcceleRAID 150, +DAC960PJ, and DAC960PG because the Intel i960RD/RP is a multi-function device. +If in doubt, contact Mylex RAID Technical Support (mylexsup@us.ibm.com) to +verify compatibility. Mylex makes available a hard disk compatibility list at +http://www.mylex.com/support/hdcomp/hd-lists.html. + + + DRIVER INSTALLATION + +This distribution was prepared for Linux kernel version 2.2.19 or 2.4.12. + +To install the DAC960 RAID driver, you may use the following commands, +replacing "/usr/src" with wherever you keep your Linux kernel source tree: + + cd /usr/src + tar -xvzf DAC960-2.2.11.tar.gz (or DAC960-2.4.11.tar.gz) + mv README.DAC960 linux/Documentation + mv DAC960.[ch] linux/drivers/block + patch -p0 < DAC960.patch (if DAC960.patch is included) + cd linux + make config + make bzImage (or zImage) + +Then install "arch/i386/boot/bzImage" or "arch/i386/boot/zImage" as your +standard kernel, run lilo if appropriate, and reboot. + +To create the necessary devices in /dev, the "make_rd" script included in +"DAC960-Utilities.tar.gz" from http://www.dandelion.com/Linux/ may be used. +LILO 21 and FDISK v2.9 include DAC960 support; also included in this archive +are patches to LILO 20 and FDISK v2.8 that add DAC960 support, along with +statically linked executables of LILO and FDISK. This modified version of LILO +will allow booting from a DAC960 controller and/or mounting the root file +system from a DAC960. + +Red Hat Linux 6.0 and SuSE Linux 6.1 include support for Mylex PCI RAID +controllers. Installing directly onto a DAC960 may be problematic from other +Linux distributions until their installation utilities are updated. + + + INSTALLATION NOTES + +Before installing Linux or adding DAC960 logical drives to an existing Linux +system, the controller must first be configured to provide one or more logical +drives using the BIOS Configuration Utility or DACCF. Please note that since +there are only at most 6 usable partitions on each logical drive, systems +requiring more partitions should subdivide a drive group into multiple logical +drives, each of which can have up to 6 usable partitions. Also, note that with +large disk arrays it is advisable to enable the 8GB BIOS Geometry (255/63) +rather than accepting the default 2GB BIOS Geometry (128/32); failing to so do +will cause the logical drive geometry to have more than 65535 cylinders which +will make it impossible for FDISK to be used properly. The 8GB BIOS Geometry +can be enabled by configuring the DAC960 BIOS, which is accessible via Alt-M +during the BIOS initialization sequence. + +For maximum performance and the most efficient E2FSCK performance, it is +recommended that EXT2 file systems be built with a 4KB block size and 16 block +stride to match the DAC960 controller's 64KB default stripe size. The command +"mke2fs -b 4096 -R stride=16 " is appropriate. Unless there will be a +large number of small files on the file systems, it is also beneficial to add +the "-i 16384" option to increase the bytes per inode parameter thereby +reducing the file system metadata. Finally, on systems that will only be run +with Linux 2.2 or later kernels it is beneficial to enable sparse superblocks +with the "-s 1" option. + + + DAC960 ANNOUNCEMENTS MAILING LIST + +The DAC960 Announcements Mailing List provides a forum for informing Linux +users of new driver releases and other announcements regarding Linux support +for DAC960 PCI RAID Controllers. To join the mailing list, send a message to +"dac960-announce-request@dandelion.com" with the line "subscribe" in the +message body. + + + CONTROLLER CONFIGURATION AND STATUS MONITORING + +The DAC960 RAID controllers running firmware 4.06 or above include a Background +Initialization facility so that system downtime is minimized both for initial +installation and subsequent configuration of additional storage. The BIOS +Configuration Utility (accessible via Alt-R during the BIOS initialization +sequence) is used to quickly configure the controller, and then the logical +drives that have been created are available for immediate use even while they +are still being initialized by the controller. The primary need for online +configuration and status monitoring is then to avoid system downtime when disk +drives fail and must be replaced. Mylex's online monitoring and configuration +utilities are being ported to Linux and will become available at some point in +the future. Note that with a SAF-TE (SCSI Accessed Fault-Tolerant Enclosure) +enclosure, the controller is able to rebuild failed drives automatically as +soon as a drive replacement is made available. + +The primary interfaces for controller configuration and status monitoring are +special files created in the /proc/rd/... hierarchy along with the normal +system console logging mechanism. Whenever the system is operating, the DAC960 +driver queries each controller for status information every 10 seconds, and +checks for additional conditions every 60 seconds. The initial status of each +controller is always available for controller N in /proc/rd/cN/initial_status, +and the current status as of the last status monitoring query is available in +/proc/rd/cN/current_status. In addition, status changes are also logged by the +driver to the system console and will appear in the log files maintained by +syslog. The progress of asynchronous rebuild or consistency check operations +is also available in /proc/rd/cN/current_status, and progress messages are +logged to the system console at most every 60 seconds. + +Starting with the 2.2.3/2.0.3 versions of the driver, the status information +available in /proc/rd/cN/initial_status and /proc/rd/cN/current_status has been +augmented to include the vendor, model, revision, and serial number (if +available) for each physical device found connected to the controller: + +***** DAC960 RAID Driver Version 2.2.3 of 19 August 1999 ***** +Copyright 1998-1999 by Leonard N. Zubkoff +Configuring Mylex DAC960PRL PCI RAID Controller + Firmware Version: 4.07-0-07, Channels: 1, Memory Size: 16MB + PCI Bus: 1, Device: 4, Function: 1, I/O Address: Unassigned + PCI Address: 0xFE300000 mapped at 0xA0800000, IRQ Channel: 21 + Controller Queue Depth: 128, Maximum Blocks per Command: 128 + Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 + Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 + SAF-TE Enclosure Management Enabled + Physical Devices: + 0:0 Vendor: IBM Model: DRVS09D Revision: 0270 + Serial Number: 68016775HA + Disk Status: Online, 17928192 blocks + 0:1 Vendor: IBM Model: DRVS09D Revision: 0270 + Serial Number: 68004E53HA + Disk Status: Online, 17928192 blocks + 0:2 Vendor: IBM Model: DRVS09D Revision: 0270 + Serial Number: 13013935HA + Disk Status: Online, 17928192 blocks + 0:3 Vendor: IBM Model: DRVS09D Revision: 0270 + Serial Number: 13016897HA + Disk Status: Online, 17928192 blocks + 0:4 Vendor: IBM Model: DRVS09D Revision: 0270 + Serial Number: 68019905HA + Disk Status: Online, 17928192 blocks + 0:5 Vendor: IBM Model: DRVS09D Revision: 0270 + Serial Number: 68012753HA + Disk Status: Online, 17928192 blocks + 0:6 Vendor: ESG-SHV Model: SCA HSBP M6 Revision: 0.61 + Logical Drives: + /dev/rd/c0d0: RAID-5, Online, 89640960 blocks, Write Thru + No Rebuild or Consistency Check in Progress + +To simplify the monitoring process for custom software, the special file +/proc/rd/status returns "OK" when all DAC960 controllers in the system are +operating normally and no failures have occurred, or "ALERT" if any logical +drives are offline or critical or any non-standby physical drives are dead. + +Configuration commands for controller N are available via the special file +/proc/rd/cN/user_command. A human readable command can be written to this +special file to initiate a configuration operation, and the results of the +operation can then be read back from the special file in addition to being +logged to the system console. The shell command sequence + + echo "" > /proc/rd/c0/user_command + cat /proc/rd/c0/user_command + +is typically used to execute configuration commands. The configuration +commands are: + + flush-cache + + The "flush-cache" command flushes the controller's cache. The system + automatically flushes the cache at shutdown or if the driver module is + unloaded, so this command is only needed to be certain a write back cache + is flushed to disk before the system is powered off by a command to a UPS. + Note that the flush-cache command also stops an asynchronous rebuild or + consistency check, so it should not be used except when the system is being + halted. + + kill : + + The "kill" command marks the physical drive : as DEAD. + This command is provided primarily for testing, and should not be used + during normal system operation. + + make-online : + + The "make-online" command changes the physical drive : + from status DEAD to status ONLINE. In cases where multiple physical drives + have been killed simultaneously, this command may be used to bring all but + one of them back online, after which a rebuild to the final drive is + necessary. + + Warning: make-online should only be used on a dead physical drive that is + an active part of a drive group, never on a standby drive. The command + should never be used on a dead drive that is part of a critical logical + drive; rebuild should be used if only a single drive is dead. + + make-standby : + + The "make-standby" command changes physical drive : + from status DEAD to status STANDBY. It should only be used in cases where + a dead drive was replaced after an automatic rebuild was performed onto a + standby drive. It cannot be used to add a standby drive to the controller + configuration if one was not created initially; the BIOS Configuration + Utility must be used for that currently. + + rebuild : + + The "rebuild" command initiates an asynchronous rebuild onto physical drive + :. It should only be used when a dead drive has been + replaced. + + check-consistency + + The "check-consistency" command initiates an asynchronous consistency check + of with automatic restoration. It can be used + whenever it is desired to verify the consistency of the redundancy + information. + + cancel-rebuild + cancel-consistency-check + + The "cancel-rebuild" and "cancel-consistency-check" commands cancel any + rebuild or consistency check operations previously initiated. + + + EXAMPLE I - DRIVE FAILURE WITHOUT A STANDBY DRIVE + +The following annotated logs demonstrate the controller configuration and and +online status monitoring capabilities of the Linux DAC960 Driver. The test +configuration comprises 6 1GB Quantum Atlas I disk drives on two channels of a +DAC960PJ controller. The physical drives are configured into a single drive +group without a standby drive, and the drive group has been configured into two +logical drives, one RAID-5 and one RAID-6. Note that these logs are from an +earlier version of the driver and the messages have changed somewhat with newer +releases, but the functionality remains similar. First, here is the current +status of the RAID configuration: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status +***** DAC960 RAID Driver Version 2.0.0 of 23 March 1999 ***** +Copyright 1998-1999 by Leonard N. Zubkoff +Configuring Mylex DAC960PJ PCI RAID Controller + Firmware Version: 4.06-0-08, Channels: 3, Memory Size: 8MB + PCI Bus: 0, Device: 19, Function: 1, I/O Address: Unassigned + PCI Address: 0xFD4FC000 mapped at 0x8807000, IRQ Channel: 9 + Controller Queue Depth: 128, Maximum Blocks per Command: 128 + Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 + Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Online, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Online, 5498880 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Online, 3305472 blocks, Write Thru + No Rebuild or Consistency Check in Progress + +gwynedd:/u/lnz# cat /proc/rd/status +OK + +The above messages indicate that everything is healthy, and /proc/rd/status +returns "OK" indicating that there are no problems with any DAC960 controller +in the system. For demonstration purposes, while I/O is active Physical Drive +1:1 is now disconnected, simulating a drive failure. The failure is noted by +the driver within 10 seconds of the controller's having detected it, and the +driver logs the following console status messages indicating that Logical +Drives 0 and 1 are now CRITICAL as a result of Physical Drive 1:1 being DEAD: + +DAC960#0: Physical Drive 1:2 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 +DAC960#0: Physical Drive 1:3 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 +DAC960#0: Physical Drive 1:1 killed because of timeout on SCSI command +DAC960#0: Physical Drive 1:1 is now DEAD +DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now CRITICAL +DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now CRITICAL + +The Sense Keys logged here are just Check Condition / Unit Attention conditions +arising from a SCSI bus reset that is forced by the controller during its error +recovery procedures. Concurrently with the above, the driver status available +from /proc/rd also reflects the drive failure. The status message in +/proc/rd/status has changed from "OK" to "ALERT": + +gwynedd:/u/lnz# cat /proc/rd/status +ALERT + +and /proc/rd/c0/current_status has been updated: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Dead, 2201600 blocks + 1:2 - Disk: Online, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Critical, 5498880 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Critical, 3305472 blocks, Write Thru + No Rebuild or Consistency Check in Progress + +Since there are no standby drives configured, the system can continue to access +the logical drives in a performance degraded mode until the failed drive is +replaced and a rebuild operation completed to restore the redundancy of the +logical drives. Once Physical Drive 1:1 is replaced with a properly +functioning drive, or if the physical drive was killed without having failed +(e.g., due to electrical problems on the SCSI bus), the user can instruct the +controller to initiate a rebuild operation onto the newly replaced drive: + +gwynedd:/u/lnz# echo "rebuild 1:1" > /proc/rd/c0/user_command +gwynedd:/u/lnz# cat /proc/rd/c0/user_command +Rebuild of Physical Drive 1:1 Initiated + +The echo command instructs the controller to initiate an asynchronous rebuild +operation onto Physical Drive 1:1, and the status message that results from the +operation is then available for reading from /proc/rd/c0/user_command, as well +as being logged to the console by the driver. + +Within 10 seconds of this command the driver logs the initiation of the +asynchronous rebuild operation: + +DAC960#0: Rebuild of Physical Drive 1:1 Initiated +DAC960#0: Physical Drive 1:1 Error Log: Sense Key = 6, ASC = 29, ASCQ = 01 +DAC960#0: Physical Drive 1:1 is now WRITE-ONLY +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 1% completed + +and /proc/rd/c0/current_status is updated: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Write-Only, 2201600 blocks + 1:2 - Disk: Online, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Critical, 5498880 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Critical, 3305472 blocks, Write Thru + Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 6% completed + +As the rebuild progresses, the current status in /proc/rd/c0/current_status is +updated every 10 seconds: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Write-Only, 2201600 blocks + 1:2 - Disk: Online, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Critical, 5498880 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Critical, 3305472 blocks, Write Thru + Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 15% completed + +and every minute a progress message is logged to the console by the driver: + +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 32% completed +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 63% completed +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 94% completed +DAC960#0: Rebuild in Progress: Logical Drive 1 (/dev/rd/c0d1) 94% completed + +Finally, the rebuild completes successfully. The driver logs the status of the +logical and physical drives and the rebuild completion: + +DAC960#0: Rebuild Completed Successfully +DAC960#0: Physical Drive 1:1 is now ONLINE +DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now ONLINE +DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now ONLINE + +/proc/rd/c0/current_status is updated: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Online, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Online, 5498880 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Online, 3305472 blocks, Write Thru + Rebuild Completed Successfully + +and /proc/rd/status indicates that everything is healthy once again: + +gwynedd:/u/lnz# cat /proc/rd/status +OK + + + EXAMPLE II - DRIVE FAILURE WITH A STANDBY DRIVE + +The following annotated logs demonstrate the controller configuration and and +online status monitoring capabilities of the Linux DAC960 Driver. The test +configuration comprises 6 1GB Quantum Atlas I disk drives on two channels of a +DAC960PJ controller. The physical drives are configured into a single drive +group with a standby drive, and the drive group has been configured into two +logical drives, one RAID-5 and one RAID-6. Note that these logs are from an +earlier version of the driver and the messages have changed somewhat with newer +releases, but the functionality remains similar. First, here is the current +status of the RAID configuration: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status +***** DAC960 RAID Driver Version 2.0.0 of 23 March 1999 ***** +Copyright 1998-1999 by Leonard N. Zubkoff +Configuring Mylex DAC960PJ PCI RAID Controller + Firmware Version: 4.06-0-08, Channels: 3, Memory Size: 8MB + PCI Bus: 0, Device: 19, Function: 1, I/O Address: Unassigned + PCI Address: 0xFD4FC000 mapped at 0x8807000, IRQ Channel: 9 + Controller Queue Depth: 128, Maximum Blocks per Command: 128 + Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 + Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Online, 2201600 blocks + 1:3 - Disk: Standby, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Online, 4399104 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Online, 2754560 blocks, Write Thru + No Rebuild or Consistency Check in Progress + +gwynedd:/u/lnz# cat /proc/rd/status +OK + +The above messages indicate that everything is healthy, and /proc/rd/status +returns "OK" indicating that there are no problems with any DAC960 controller +in the system. For demonstration purposes, while I/O is active Physical Drive +1:2 is now disconnected, simulating a drive failure. The failure is noted by +the driver within 10 seconds of the controller's having detected it, and the +driver logs the following console status messages: + +DAC960#0: Physical Drive 1:1 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 +DAC960#0: Physical Drive 1:3 Error Log: Sense Key = 6, ASC = 29, ASCQ = 02 +DAC960#0: Physical Drive 1:2 killed because of timeout on SCSI command +DAC960#0: Physical Drive 1:2 is now DEAD +DAC960#0: Physical Drive 1:2 killed because it was removed +DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now CRITICAL +DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now CRITICAL + +Since a standby drive is configured, the controller automatically begins +rebuilding onto the standby drive: + +DAC960#0: Physical Drive 1:3 is now WRITE-ONLY +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 4% completed + +Concurrently with the above, the driver status available from /proc/rd also +reflects the drive failure and automatic rebuild. The status message in +/proc/rd/status has changed from "OK" to "ALERT": + +gwynedd:/u/lnz# cat /proc/rd/status +ALERT + +and /proc/rd/c0/current_status has been updated: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Dead, 2201600 blocks + 1:3 - Disk: Write-Only, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Critical, 4399104 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Critical, 2754560 blocks, Write Thru + Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 4% completed + +As the rebuild progresses, the current status in /proc/rd/c0/current_status is +updated every 10 seconds: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Dead, 2201600 blocks + 1:3 - Disk: Write-Only, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Critical, 4399104 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Critical, 2754560 blocks, Write Thru + Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 40% completed + +and every minute a progress message is logged on the console by the driver: + +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 40% completed +DAC960#0: Rebuild in Progress: Logical Drive 0 (/dev/rd/c0d0) 76% completed +DAC960#0: Rebuild in Progress: Logical Drive 1 (/dev/rd/c0d1) 66% completed +DAC960#0: Rebuild in Progress: Logical Drive 1 (/dev/rd/c0d1) 84% completed + +Finally, the rebuild completes successfully. The driver logs the status of the +logical and physical drives and the rebuild completion: + +DAC960#0: Rebuild Completed Successfully +DAC960#0: Physical Drive 1:3 is now ONLINE +DAC960#0: Logical Drive 0 (/dev/rd/c0d0) is now ONLINE +DAC960#0: Logical Drive 1 (/dev/rd/c0d1) is now ONLINE + +/proc/rd/c0/current_status is updated: + +***** DAC960 RAID Driver Version 2.0.0 of 23 March 1999 ***** +Copyright 1998-1999 by Leonard N. Zubkoff +Configuring Mylex DAC960PJ PCI RAID Controller + Firmware Version: 4.06-0-08, Channels: 3, Memory Size: 8MB + PCI Bus: 0, Device: 19, Function: 1, I/O Address: Unassigned + PCI Address: 0xFD4FC000 mapped at 0x8807000, IRQ Channel: 9 + Controller Queue Depth: 128, Maximum Blocks per Command: 128 + Driver Queue Depth: 127, Maximum Scatter/Gather Segments: 33 + Stripe Size: 64KB, Segment Size: 8KB, BIOS Geometry: 255/63 + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Dead, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Online, 4399104 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Online, 2754560 blocks, Write Thru + Rebuild Completed Successfully + +and /proc/rd/status indicates that everything is healthy once again: + +gwynedd:/u/lnz# cat /proc/rd/status +OK + +Note that the absence of a viable standby drive does not create an "ALERT" +status. Once dead Physical Drive 1:2 has been replaced, the controller must be +told that this has occurred and that the newly replaced drive should become the +new standby drive: + +gwynedd:/u/lnz# echo "make-standby 1:2" > /proc/rd/c0/user_command +gwynedd:/u/lnz# cat /proc/rd/c0/user_command +Make Standby of Physical Drive 1:2 Succeeded + +The echo command instructs the controller to make Physical Drive 1:2 into a +standby drive, and the status message that results from the operation is then +available for reading from /proc/rd/c0/user_command, as well as being logged to +the console by the driver. Within 60 seconds of this command the driver logs: + +DAC960#0: Physical Drive 1:2 Error Log: Sense Key = 6, ASC = 29, ASCQ = 01 +DAC960#0: Physical Drive 1:2 is now STANDBY +DAC960#0: Make Standby of Physical Drive 1:2 Succeeded + +and /proc/rd/c0/current_status is updated: + +gwynedd:/u/lnz# cat /proc/rd/c0/current_status + ... + Physical Devices: + 0:1 - Disk: Online, 2201600 blocks + 0:2 - Disk: Online, 2201600 blocks + 0:3 - Disk: Online, 2201600 blocks + 1:1 - Disk: Online, 2201600 blocks + 1:2 - Disk: Standby, 2201600 blocks + 1:3 - Disk: Online, 2201600 blocks + Logical Drives: + /dev/rd/c0d0: RAID-5, Online, 4399104 blocks, Write Thru + /dev/rd/c0d1: RAID-6, Online, 2754560 blocks, Write Thru + Rebuild Completed Successfully diff --git a/Documentation/blockdev/cciss.txt b/Documentation/blockdev/cciss.txt new file mode 100644 index 000000000000..89698e8df7d4 --- /dev/null +++ b/Documentation/blockdev/cciss.txt @@ -0,0 +1,171 @@ +This driver is for Compaq's SMART Array Controllers. + +Supported Cards: +---------------- + +This driver is known to work with the following cards: + + * SA 5300 + * SA 5i + * SA 532 + * SA 5312 + * SA 641 + * SA 642 + * SA 6400 + * SA 6400 U320 Expansion Module + * SA 6i + * SA P600 + * SA P800 + * SA E400 + * SA P400i + * SA E200 + * SA E200i + * SA E500 + * SA P700m + * SA P212 + * SA P410 + * SA P410i + * SA P411 + * SA P812 + * SA P712m + * SA P711m + +Detecting drive failures: +------------------------- + +To get the status of logical volumes and to detect physical drive +failures, you can use the cciss_vol_status program found here: +http://cciss.sourceforge.net/#cciss_utils + +Device Naming: +-------------- + +If nodes are not already created in the /dev/cciss directory, run as root: + +# cd /dev +# ./MAKEDEV cciss + +You need some entries in /dev for the cciss device. The MAKEDEV script +can make device nodes for you automatically. Currently the device setup +is as follows: + +Major numbers: + 104 cciss0 + 105 cciss1 + 106 cciss2 + 105 cciss3 + 108 cciss4 + 109 cciss5 + 110 cciss6 + 111 cciss7 + +Minor numbers: + b7 b6 b5 b4 b3 b2 b1 b0 + |----+----| |----+----| + | | + | +-------- Partition ID (0=wholedev, 1-15 partition) + | + +-------------------- Logical Volume number + +The device naming scheme is: +/dev/cciss/c0d0 Controller 0, disk 0, whole device +/dev/cciss/c0d0p1 Controller 0, disk 0, partition 1 +/dev/cciss/c0d0p2 Controller 0, disk 0, partition 2 +/dev/cciss/c0d0p3 Controller 0, disk 0, partition 3 + +/dev/cciss/c1d1 Controller 1, disk 1, whole device +/dev/cciss/c1d1p1 Controller 1, disk 1, partition 1 +/dev/cciss/c1d1p2 Controller 1, disk 1, partition 2 +/dev/cciss/c1d1p3 Controller 1, disk 1, partition 3 + +SCSI tape drive and medium changer support +------------------------------------------ + +SCSI sequential access devices and medium changer devices are supported and +appropriate device nodes are automatically created. (e.g. +/dev/st0, /dev/st1, etc. See the "st" man page for more details.) +You must enable "SCSI tape drive support for Smart Array 5xxx" and +"SCSI support" in your kernel configuration to be able to use SCSI +tape drives with your Smart Array 5xxx controller. + +Additionally, note that the driver will not engage the SCSI core at init +time. The driver must be directed to dynamically engage the SCSI core via +the /proc filesystem entry which the "block" side of the driver creates as +/proc/driver/cciss/cciss* at runtime. This is because at driver init time, +the SCSI core may not yet be initialized (because the driver is a block +driver) and attempting to register it with the SCSI core in such a case +would cause a hang. This is best done via an initialization script +(typically in /etc/init.d, but could vary depending on distribution). +For example: + + for x in /proc/driver/cciss/cciss[0-9]* + do + echo "engage scsi" > $x + done + +Once the SCSI core is engaged by the driver, it cannot be disengaged +(except by unloading the driver, if it happens to be linked as a module.) + +Note also that if no sequential access devices or medium changers are +detected, the SCSI core will not be engaged by the action of the above +script. + +Hot plug support for SCSI tape drives +------------------------------------- + +Hot plugging of SCSI tape drives is supported, with some caveats. +The cciss driver must be informed that changes to the SCSI bus +have been made. This may be done via the /proc filesystem. +For example: + + echo "rescan" > /proc/scsi/cciss0/1 + +This causes the driver to query the adapter about changes to the +physical SCSI buses and/or fibre channel arbitrated loop and the +driver to make note of any new or removed sequential access devices +or medium changers. The driver will output messages indicating what +devices have been added or removed and the controller, bus, target and +lun used to address the device. It then notifies the SCSI mid layer +of these changes. + +Note that the naming convention of the /proc filesystem entries +contains a number in addition to the driver name. (E.g. "cciss0" +instead of just "cciss" which you might expect.) + +Note: ONLY sequential access devices and medium changers are presented +as SCSI devices to the SCSI mid layer by the cciss driver. Specifically, +physical SCSI disk drives are NOT presented to the SCSI mid layer. The +physical SCSI disk drives are controlled directly by the array controller +hardware and it is important to prevent the kernel from attempting to directly +access these devices too, as if the array controller were merely a SCSI +controller in the same way that we are allowing it to access SCSI tape drives. + +SCSI error handling for tape drives and medium changers +------------------------------------------------------- + +The linux SCSI mid layer provides an error handling protocol which +kicks into gear whenever a SCSI command fails to complete within a +certain amount of time (which can vary depending on the command). +The cciss driver participates in this protocol to some extent. The +normal protocol is a four step process. First the device is told +to abort the command. If that doesn't work, the device is reset. +If that doesn't work, the SCSI bus is reset. If that doesn't work +the host bus adapter is reset. Because the cciss driver is a block +driver as well as a SCSI driver and only the tape drives and medium +changers are presented to the SCSI mid layer, and unlike more +straightforward SCSI drivers, disk i/o continues through the block +side during the SCSI error recovery process, the cciss driver only +implements the first two of these actions, aborting the command, and +resetting the device. Additionally, most tape drives will not oblige +in aborting commands, and sometimes it appears they will not even +obey a reset command, though in most circumstances they will. In +the case that the command cannot be aborted and the device cannot be +reset, the device will be set offline. + +In the event the error handling code is triggered and a tape drive is +successfully reset or the tardy command is successfully aborted, the +tape drive may still not allow i/o to continue until some command +is issued which positions the tape to a known position. Typically you +must rewind the tape (by issuing "mt -f /dev/st0 rewind" for example) +before i/o can proceed again to a tape drive which was reset. + diff --git a/Documentation/blockdev/cpqarray.txt b/Documentation/blockdev/cpqarray.txt new file mode 100644 index 000000000000..c7154e20ef5e --- /dev/null +++ b/Documentation/blockdev/cpqarray.txt @@ -0,0 +1,93 @@ +This driver is for Compaq's SMART2 Intelligent Disk Array Controllers. + +Supported Cards: +---------------- + +This driver is known to work with the following cards: + + * SMART (EISA) + * SMART-2/E (EISA) + * SMART-2/P + * SMART-2DH + * SMART-2SL + * SMART-221 + * SMART-3100ES + * SMART-3200 + * Integrated Smart Array Controller + * SA 4200 + * SA 4250ES + * SA 431 + * RAID LC2 Controller + +It should also work with some really old Disk array adapters, but I am +unable to test against these cards: + + * IDA + * IDA-2 + * IAES + + +EISA Controllers: +----------------- + +If you want to use an EISA controller you'll have to supply some +modprobe/lilo parameters. If the driver is compiled into the kernel, must +give it the controller's IO port address at boot time (it is not +necessary to specify the IRQ). For example, if you had two SMART-2/E +controllers, in EISA slots 1 and 2 you'd give it a boot argument like +this: + + smart2=0x1000,0x2000 + +If you were loading the driver as a module, you'd give load it like this: + + modprobe cpqarray eisa=0x1000,0x2000 + +You can use EISA and PCI adapters at the same time. + + +Device Naming: +-------------- + +You need some entries in /dev for the ida device. MAKEDEV in the /dev +directory can make device nodes for you automatically. The device setup is +as follows: + +Major numbers: + 72 ida0 + 73 ida1 + 74 ida2 + 75 ida3 + 76 ida4 + 77 ida5 + 78 ida6 + 79 ida7 + +Minor numbers: + b7 b6 b5 b4 b3 b2 b1 b0 + |----+----| |----+----| + | | + | +-------- Partition ID (0=wholedev, 1-15 partition) + | + +-------------------- Logical Volume number + +The device naming scheme is: +/dev/ida/c0d0 Controller 0, disk 0, whole device +/dev/ida/c0d0p1 Controller 0, disk 0, partition 1 +/dev/ida/c0d0p2 Controller 0, disk 0, partition 2 +/dev/ida/c0d0p3 Controller 0, disk 0, partition 3 + +/dev/ida/c1d1 Controller 1, disk 1, whole device +/dev/ida/c1d1p1 Controller 1, disk 1, partition 1 +/dev/ida/c1d1p2 Controller 1, disk 1, partition 2 +/dev/ida/c1d1p3 Controller 1, disk 1, partition 3 + + +Changelog: +========== + +10-28-2004 : General cleanup, syntax fixes for in-kernel driver version. + James Nelson + + +1999 : Original Document diff --git a/Documentation/blockdev/floppy.txt b/Documentation/blockdev/floppy.txt new file mode 100644 index 000000000000..6ccab88705cb --- /dev/null +++ b/Documentation/blockdev/floppy.txt @@ -0,0 +1,245 @@ +This file describes the floppy driver. + +FAQ list: +========= + + A FAQ list may be found in the fdutils package (see below), and also +at . + + +LILO configuration options (Thinkpad users, read this) +====================================================== + + The floppy driver is configured using the 'floppy=' option in +lilo. This option can be typed at the boot prompt, or entered in the +lilo configuration file. + + Example: If your kernel is called linux-2.6.9, type the following line +at the lilo boot prompt (if you have a thinkpad): + + linux-2.6.9 floppy=thinkpad + +You may also enter the following line in /etc/lilo.conf, in the description +of linux-2.6.9: + + append = "floppy=thinkpad" + + Several floppy related options may be given, example: + + linux-2.6.9 floppy=daring floppy=two_fdc + append = "floppy=daring floppy=two_fdc" + + If you give options both in the lilo config file and on the boot +prompt, the option strings of both places are concatenated, the boot +prompt options coming last. That's why there are also options to +restore the default behavior. + + +Module configuration options +============================ + + If you use the floppy driver as a module, use the following syntax: +modprobe floppy + +Example: + modprobe floppy omnibook messages + + If you need certain options enabled every time you load the floppy driver, +you can put: + + options floppy omnibook messages + +in /etc/modprobe.conf. + + + The floppy driver related options are: + + floppy=asus_pci + Sets the bit mask to allow only units 0 and 1. (default) + + floppy=daring + Tells the floppy driver that you have a well behaved floppy controller. + This allows more efficient and smoother operation, but may fail on + certain controllers. This may speed up certain operations. + + floppy=0,daring + Tells the floppy driver that your floppy controller should be used + with caution. + + floppy=one_fdc + Tells the floppy driver that you have only one floppy controller. + (default) + + floppy=two_fdc + floppy=
,two_fdc + Tells the floppy driver that you have two floppy controllers. + The second floppy controller is assumed to be at
. + This option is not needed if the second controller is at address + 0x370, and if you use the 'cmos' option. + + floppy=thinkpad + Tells the floppy driver that you have a Thinkpad. Thinkpads use an + inverted convention for the disk change line. + + floppy=0,thinkpad + Tells the floppy driver that you don't have a Thinkpad. + + floppy=omnibook + floppy=nodma + Tells the floppy driver not to use Dma for data transfers. + This is needed on HP Omnibooks, which don't have a workable + DMA channel for the floppy driver. This option is also useful + if you frequently get "Unable to allocate DMA memory" messages. + Indeed, dma memory needs to be continuous in physical memory, + and is thus harder to find, whereas non-dma buffers may be + allocated in virtual memory. However, I advise against this if + you have an FDC without a FIFO (8272A or 82072). 82072A and + later are OK. You also need at least a 486 to use nodma. + If you use nodma mode, I suggest you also set the FIFO + threshold to 10 or lower, in order to limit the number of data + transfer interrupts. + + If you have a FIFO-able FDC, the floppy driver automatically + falls back on non DMA mode if no DMA-able memory can be found. + If you want to avoid this, explicitly ask for 'yesdma'. + + floppy=yesdma + Tells the floppy driver that a workable DMA channel is available. + (default) + + floppy=nofifo + Disables the FIFO entirely. This is needed if you get "Bus + master arbitration error" messages from your Ethernet card (or + from other devices) while accessing the floppy. + + floppy=usefifo + Enables the FIFO. (default) + + floppy=,fifo_depth + Sets the FIFO threshold. This is mostly relevant in DMA + mode. If this is higher, the floppy driver tolerates more + interrupt latency, but it triggers more interrupts (i.e. it + imposes more load on the rest of the system). If this is + lower, the interrupt latency should be lower too (faster + processor). The benefit of a lower threshold is less + interrupts. + + To tune the fifo threshold, switch on over/underrun messages + using 'floppycontrol --messages'. Then access a floppy + disk. If you get a huge amount of "Over/Underrun - retrying" + messages, then the fifo threshold is too low. Try with a + higher value, until you only get an occasional Over/Underrun. + It is a good idea to compile the floppy driver as a module + when doing this tuning. Indeed, it allows to try different + fifo values without rebooting the machine for each test. Note + that you need to do 'floppycontrol --messages' every time you + re-insert the module. + + Usually, tuning the fifo threshold should not be needed, as + the default (0xa) is reasonable. + + floppy=,,cmos + Sets the CMOS type of to . This is mandatory if + you have more than two floppy drives (only two can be + described in the physical CMOS), or if your BIOS uses + non-standard CMOS types. The CMOS types are: + + 0 - Use the value of the physical CMOS + 1 - 5 1/4 DD + 2 - 5 1/4 HD + 3 - 3 1/2 DD + 4 - 3 1/2 HD + 5 - 3 1/2 ED + 6 - 3 1/2 ED + 16 - unknown or not installed + + (Note: there are two valid types for ED drives. This is because 5 was + initially chosen to represent floppy *tapes*, and 6 for ED drives. + AMI ignored this, and used 5 for ED drives. That's why the floppy + driver handles both.) + + floppy=unexpected_interrupts + Print a warning message when an unexpected interrupt is received. + (default) + + floppy=no_unexpected_interrupts + floppy=L40SX + Don't print a message when an unexpected interrupt is received. This + is needed on IBM L40SX laptops in certain video modes. (There seems + to be an interaction between video and floppy. The unexpected + interrupts affect only performance, and can be safely ignored.) + + floppy=broken_dcl + Don't use the disk change line, but assume that the disk was + changed whenever the device node is reopened. Needed on some + boxes where the disk change line is broken or unsupported. + This should be regarded as a stopgap measure, indeed it makes + floppy operation less efficient due to unneeded cache + flushings, and slightly more unreliable. Please verify your + cable, connection and jumper settings if you have any DCL + problems. However, some older drives, and also some laptops + are known not to have a DCL. + + floppy=debug + Print debugging messages. + + floppy=messages + Print informational messages for some operations (disk change + notifications, warnings about over and underruns, and about + autodetection). + + floppy=silent_dcl_clear + Uses a less noisy way to clear the disk change line (which + doesn't involve seeks). Implied by 'daring' option. + + floppy=,irq + Sets the floppy IRQ to instead of 6. + + floppy=,dma + Sets the floppy DMA channel to instead of 2. + + floppy=slow + Use PS/2 stepping rate: + " PS/2 floppies have much slower step rates than regular floppies. + It's been recommended that take about 1/4 of the default speed + in some more extreme cases." + + +Supporting utilities and additional documentation: +================================================== + + Additional parameters of the floppy driver can be configured at +runtime. Utilities which do this can be found in the fdutils package. +This package also contains a new version of mtools which allows to +access high capacity disks (up to 1992K on a high density 3 1/2 disk!). +It also contains additional documentation about the floppy driver. + +The latest version can be found at fdutils homepage: + http://fdutils.linux.lu + +The fdutils releases can be found at: + http://fdutils.linux.lu/download.html + http://www.tux.org/pub/knaff/fdutils/ + ftp://metalab.unc.edu/pub/Linux/utils/disk-management/ + +Reporting problems about the floppy driver +========================================== + + If you have a question or a bug report about the floppy driver, mail +me at Alain.Knaff@poboxes.com . If you post to Usenet, preferably use +comp.os.linux.hardware. As the volume in these groups is rather high, +be sure to include the word "floppy" (or "FLOPPY") in the subject +line. If the reported problem happens when mounting floppy disks, be +sure to mention also the type of the filesystem in the subject line. + + Be sure to read the FAQ before mailing/posting any bug reports! + + Alain + +Changelog +========= + +10-30-2004 : Cleanup, updating, add reference to module configuration. + James Nelson + +6-3-2000 : Original Document diff --git a/Documentation/blockdev/nbd.txt b/Documentation/blockdev/nbd.txt new file mode 100644 index 000000000000..aeb93ffe6416 --- /dev/null +++ b/Documentation/blockdev/nbd.txt @@ -0,0 +1,47 @@ + Network Block Device (TCP version) + + What is it: With this compiled in the kernel (or as a module), Linux + can use a remote server as one of its block devices. So every time + the client computer wants to read, e.g., /dev/nb0, it sends a + request over TCP to the server, which will reply with the data read. + This can be used for stations with low disk space (or even diskless - + if you boot from floppy) to borrow disk space from another computer. + Unlike NFS, it is possible to put any filesystem on it, etc. It should + even be possible to use NBD as a root filesystem (I've never tried), + but it requires a user-level program to be in the initrd to start. + It also allows you to run block-device in user land (making server + and client physically the same computer, communicating using loopback). + + Current state: It currently works. Network block device is stable. + I originally thought that it was impossible to swap over TCP. It + turned out not to be true - swapping over TCP now works and seems + to be deadlock-free, but it requires heavy patches into Linux's + network layer. + + For more information, or to download the nbd-client and nbd-server + tools, go to http://nbd.sf.net/. + + Howto: To setup nbd, you can simply do the following: + + First, serve a device or file from a remote server: + + nbd-server + + e.g., + root@server1 # nbd-server 1234 /dev/sdb1 + + (serves sdb1 partition on TCP port 1234) + + Then, on the local (client) system: + + nbd-client /dev/nb[0-n] + + e.g., + root@client1 # nbd-client server1 1234 /dev/nb0 + + (creates the nb0 device on client1) + + The nbd kernel module need only be installed on the client + system, as the nbd-server is completely in userspace. In fact, + the nbd-server has been successfully ported to other operating + systems, including Windows. diff --git a/Documentation/blockdev/paride.txt b/Documentation/blockdev/paride.txt new file mode 100644 index 000000000000..e4312676bdda --- /dev/null +++ b/Documentation/blockdev/paride.txt @@ -0,0 +1,417 @@ + + Linux and parallel port IDE devices + +PARIDE v1.03 (c) 1997-8 Grant Guenther + +1. Introduction + +Owing to the simplicity and near universality of the parallel port interface +to personal computers, many external devices such as portable hard-disk, +CD-ROM, LS-120 and tape drives use the parallel port to connect to their +host computer. While some devices (notably scanners) use ad-hoc methods +to pass commands and data through the parallel port interface, most +external devices are actually identical to an internal model, but with +a parallel-port adapter chip added in. Some of the original parallel port +adapters were little more than mechanisms for multiplexing a SCSI bus. +(The Iomega PPA-3 adapter used in the ZIP drives is an example of this +approach). Most current designs, however, take a different approach. +The adapter chip reproduces a small ISA or IDE bus in the external device +and the communication protocol provides operations for reading and writing +device registers, as well as data block transfer functions. Sometimes, +the device being addressed via the parallel cable is a standard SCSI +controller like an NCR 5380. The "ditto" family of external tape +drives use the ISA replicator to interface a floppy disk controller, +which is then connected to a floppy-tape mechanism. The vast majority +of external parallel port devices, however, are now based on standard +IDE type devices, which require no intermediate controller. If one +were to open up a parallel port CD-ROM drive, for instance, one would +find a standard ATAPI CD-ROM drive, a power supply, and a single adapter +that interconnected a standard PC parallel port cable and a standard +IDE cable. It is usually possible to exchange the CD-ROM device with +any other device using the IDE interface. + +The document describes the support in Linux for parallel port IDE +devices. It does not cover parallel port SCSI devices, "ditto" tape +drives or scanners. Many different devices are supported by the +parallel port IDE subsystem, including: + + MicroSolutions backpack CD-ROM + MicroSolutions backpack PD/CD + MicroSolutions backpack hard-drives + MicroSolutions backpack 8000t tape drive + SyQuest EZ-135, EZ-230 & SparQ drives + Avatar Shark + Imation Superdisk LS-120 + Maxell Superdisk LS-120 + FreeCom Power CD + Hewlett-Packard 5GB and 8GB tape drives + Hewlett-Packard 7100 and 7200 CD-RW drives + +as well as most of the clone and no-name products on the market. + +To support such a wide range of devices, PARIDE, the parallel port IDE +subsystem, is actually structured in three parts. There is a base +paride module which provides a registry and some common methods for +accessing the parallel ports. The second component is a set of +high-level drivers for each of the different types of supported devices: + + pd IDE disk + pcd ATAPI CD-ROM + pf ATAPI disk + pt ATAPI tape + pg ATAPI generic + +(Currently, the pg driver is only used with CD-R drives). + +The high-level drivers function according to the relevant standards. +The third component of PARIDE is a set of low-level protocol drivers +for each of the parallel port IDE adapter chips. Thanks to the interest +and encouragement of Linux users from many parts of the world, +support is available for almost all known adapter protocols: + + aten ATEN EH-100 (HK) + bpck Microsolutions backpack (US) + comm DataStor (old-type) "commuter" adapter (TW) + dstr DataStor EP-2000 (TW) + epat Shuttle EPAT (UK) + epia Shuttle EPIA (UK) + fit2 FIT TD-2000 (US) + fit3 FIT TD-3000 (US) + friq Freecom IQ cable (DE) + frpw Freecom Power (DE) + kbic KingByte KBIC-951A and KBIC-971A (TW) + ktti KT Technology PHd adapter (SG) + on20 OnSpec 90c20 (US) + on26 OnSpec 90c26 (US) + + +2. Using the PARIDE subsystem + +While configuring the Linux kernel, you may choose either to build +the PARIDE drivers into your kernel, or to build them as modules. + +In either case, you will need to select "Parallel port IDE device support" +as well as at least one of the high-level drivers and at least one +of the parallel port communication protocols. If you do not know +what kind of parallel port adapter is used in your drive, you could +begin by checking the file names and any text files on your DOS +installation floppy. Alternatively, you can look at the markings on +the adapter chip itself. That's usually sufficient to identify the +correct device. + +You can actually select all the protocol modules, and allow the PARIDE +subsystem to try them all for you. + +For the "brand-name" products listed above, here are the protocol +and high-level drivers that you would use: + + Manufacturer Model Driver Protocol + + MicroSolutions CD-ROM pcd bpck + MicroSolutions PD drive pf bpck + MicroSolutions hard-drive pd bpck + MicroSolutions 8000t tape pt bpck + SyQuest EZ, SparQ pd epat + Imation Superdisk pf epat + Maxell Superdisk pf friq + Avatar Shark pd epat + FreeCom CD-ROM pcd frpw + Hewlett-Packard 5GB Tape pt epat + Hewlett-Packard 7200e (CD) pcd epat + Hewlett-Packard 7200e (CD-R) pg epat + +2.1 Configuring built-in drivers + +We recommend that you get to know how the drivers work and how to +configure them as loadable modules, before attempting to compile a +kernel with the drivers built-in. + +If you built all of your PARIDE support directly into your kernel, +and you have just a single parallel port IDE device, your kernel should +locate it automatically for you. If you have more than one device, +you may need to give some command line options to your bootloader +(eg: LILO), how to do that is beyond the scope of this document. + +The high-level drivers accept a number of command line parameters, all +of which are documented in the source files in linux/drivers/block/paride. +By default, each driver will automatically try all parallel ports it +can find, and all protocol types that have been installed, until it finds +a parallel port IDE adapter. Once it finds one, the probe stops. So, +if you have more than one device, you will need to tell the drivers +how to identify them. This requires specifying the port address, the +protocol identification number and, for some devices, the drive's +chain ID. While your system is booting, a number of messages are +displayed on the console. Like all such messages, they can be +reviewed with the 'dmesg' command. Among those messages will be +some lines like: + + paride: bpck registered as protocol 0 + paride: epat registered as protocol 1 + +The numbers will always be the same until you build a new kernel with +different protocol selections. You should note these numbers as you +will need them to identify the devices. + +If you happen to be using a MicroSolutions backpack device, you will +also need to know the unit ID number for each drive. This is usually +the last two digits of the drive's serial number (but read MicroSolutions' +documentation about this). + +As an example, let's assume that you have a MicroSolutions PD/CD drive +with unit ID number 36 connected to the parallel port at 0x378, a SyQuest +EZ-135 connected to the chained port on the PD/CD drive and also an +Imation Superdisk connected to port 0x278. You could give the following +options on your boot command: + + pd.drive0=0x378,1 pf.drive0=0x278,1 pf.drive1=0x378,0,36 + +In the last option, pf.drive1 configures device /dev/pf1, the 0x378 +is the parallel port base address, the 0 is the protocol registration +number and 36 is the chain ID. + +Please note: while PARIDE will work both with and without the +PARPORT parallel port sharing system that is included by the +"Parallel port support" option, PARPORT must be included and enabled +if you want to use chains of devices on the same parallel port. + +2.2 Loading and configuring PARIDE as modules + +It is much faster and simpler to get to understand the PARIDE drivers +if you use them as loadable kernel modules. + +Note 1: using these drivers with the "kerneld" automatic module loading +system is not recommended for beginners, and is not documented here. + +Note 2: if you build PARPORT support as a loadable module, PARIDE must +also be built as loadable modules, and PARPORT must be loaded before the +PARIDE modules. + +To use PARIDE, you must begin by + + insmod paride + +this loads a base module which provides a registry for the protocols, +among other tasks. + +Then, load as many of the protocol modules as you think you might need. +As you load each module, it will register the protocols that it supports, +and print a log message to your kernel log file and your console. For +example: + + # insmod epat + paride: epat registered as protocol 0 + # insmod kbic + paride: k951 registered as protocol 1 + paride: k971 registered as protocol 2 + +Finally, you can load high-level drivers for each kind of device that +you have connected. By default, each driver will autoprobe for a single +device, but you can support up to four similar devices by giving their +individual co-ordinates when you load the driver. + +For example, if you had two no-name CD-ROM drives both using the +KingByte KBIC-951A adapter, one on port 0x378 and the other on 0x3bc +you could give the following command: + + # insmod pcd drive0=0x378,1 drive1=0x3bc,1 + +For most adapters, giving a port address and protocol number is sufficient, +but check the source files in linux/drivers/block/paride for more +information. (Hopefully someone will write some man pages one day !). + +As another example, here's what happens when PARPORT is installed, and +a SyQuest EZ-135 is attached to port 0x378: + + # insmod paride + paride: version 1.0 installed + # insmod epat + paride: epat registered as protocol 0 + # insmod pd + pd: pd version 1.0, major 45, cluster 64, nice 0 + pda: Sharing parport1 at 0x378 + pda: epat 1.0, Shuttle EPAT chip c3 at 0x378, mode 5 (EPP-32), delay 1 + pda: SyQuest EZ135A, 262144 blocks [128M], (512/16/32), removable media + pda: pda1 + +Note that the last line is the output from the generic partition table +scanner - in this case it reports that it has found a disk with one partition. + +2.3 Using a PARIDE device + +Once the drivers have been loaded, you can access PARIDE devices in the +same way as their traditional counterparts. You will probably need to +create the device "special files". Here is a simple script that you can +cut to a file and execute: + +#!/bin/bash +# +# mkd -- a script to create the device special files for the PARIDE subsystem +# +function mkdev { + mknod $1 $2 $3 $4 ; chmod 0660 $1 ; chown root:disk $1 +} +# +function pd { + D=$( printf \\$( printf "x%03x" $[ $1 + 97 ] ) ) + mkdev pd$D b 45 $[ $1 * 16 ] + for P in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + do mkdev pd$D$P b 45 $[ $1 * 16 + $P ] + done +} +# +cd /dev +# +for u in 0 1 2 3 ; do pd $u ; done +for u in 0 1 2 3 ; do mkdev pcd$u b 46 $u ; done +for u in 0 1 2 3 ; do mkdev pf$u b 47 $u ; done +for u in 0 1 2 3 ; do mkdev pt$u c 96 $u ; done +for u in 0 1 2 3 ; do mkdev npt$u c 96 $[ $u + 128 ] ; done +for u in 0 1 2 3 ; do mkdev pg$u c 97 $u ; done +# +# end of mkd + +With the device files and drivers in place, you can access PARIDE devices +like any other Linux device. For example, to mount a CD-ROM in pcd0, use: + + mount /dev/pcd0 /cdrom + +If you have a fresh Avatar Shark cartridge, and the drive is pda, you +might do something like: + + fdisk /dev/pda -- make a new partition table with + partition 1 of type 83 + + mke2fs /dev/pda1 -- to build the file system + + mkdir /shark -- make a place to mount the disk + + mount /dev/pda1 /shark + +Devices like the Imation superdisk work in the same way, except that +they do not have a partition table. For example to make a 120MB +floppy that you could share with a DOS system: + + mkdosfs /dev/pf0 + mount /dev/pf0 /mnt + + +2.4 The pf driver + +The pf driver is intended for use with parallel port ATAPI disk +devices. The most common devices in this category are PD drives +and LS-120 drives. Traditionally, media for these devices are not +partitioned. Consequently, the pf driver does not support partitioned +media. This may be changed in a future version of the driver. + +2.5 Using the pt driver + +The pt driver for parallel port ATAPI tape drives is a minimal driver. +It does not yet support many of the standard tape ioctl operations. +For best performance, a block size of 32KB should be used. You will +probably want to set the parallel port delay to 0, if you can. + +2.6 Using the pg driver + +The pg driver can be used in conjunction with the cdrecord program +to create CD-ROMs. Please get cdrecord version 1.6.1 or later +from ftp://ftp.fokus.gmd.de/pub/unix/cdrecord/ . To record CD-R media +your parallel port should ideally be set to EPP mode, and the "port delay" +should be set to 0. With those settings it is possible to record at 2x +speed without any buffer underruns. If you cannot get the driver to work +in EPP mode, try to use "bidirectional" or "PS/2" mode and 1x speeds only. + + +3. Troubleshooting + +3.1 Use EPP mode if you can + +The most common problems that people report with the PARIDE drivers +concern the parallel port CMOS settings. At this time, none of the +PARIDE protocol modules support ECP mode, or any ECP combination modes. +If you are able to do so, please set your parallel port into EPP mode +using your CMOS setup procedure. + +3.2 Check the port delay + +Some parallel ports cannot reliably transfer data at full speed. To +offset the errors, the PARIDE protocol modules introduce a "port +delay" between each access to the i/o ports. Each protocol sets +a default value for this delay. In most cases, the user can override +the default and set it to 0 - resulting in somewhat higher transfer +rates. In some rare cases (especially with older 486 systems) the +default delays are not long enough. if you experience corrupt data +transfers, or unexpected failures, you may wish to increase the +port delay. The delay can be programmed using the "driveN" parameters +to each of the high-level drivers. Please see the notes above, or +read the comments at the beginning of the driver source files in +linux/drivers/block/paride. + +3.3 Some drives need a printer reset + +There appear to be a number of "noname" external drives on the market +that do not always power up correctly. We have noticed this with some +drives based on OnSpec and older Freecom adapters. In these rare cases, +the adapter can often be reinitialised by issuing a "printer reset" on +the parallel port. As the reset operation is potentially disruptive in +multiple device environments, the PARIDE drivers will not do it +automatically. You can however, force a printer reset by doing: + + insmod lp reset=1 + rmmod lp + +If you have one of these marginal cases, you should probably build +your paride drivers as modules, and arrange to do the printer reset +before loading the PARIDE drivers. + +3.4 Use the verbose option and dmesg if you need help + +While a lot of testing has gone into these drivers to make them work +as smoothly as possible, problems will arise. If you do have problems, +please check all the obvious things first: does the drive work in +DOS with the manufacturer's drivers ? If that doesn't yield any useful +clues, then please make sure that only one drive is hooked to your system, +and that either (a) PARPORT is enabled or (b) no other device driver +is using your parallel port (check in /proc/ioports). Then, load the +appropriate drivers (you can load several protocol modules if you want) +as in: + + # insmod paride + # insmod epat + # insmod bpck + # insmod kbic + ... + # insmod pd verbose=1 + +(using the correct driver for the type of device you have, of course). +The verbose=1 parameter will cause the drivers to log a trace of their +activity as they attempt to locate your drive. + +Use 'dmesg' to capture a log of all the PARIDE messages (any messages +beginning with paride:, a protocol module's name or a driver's name) and +include that with your bug report. You can submit a bug report in one +of two ways. Either send it directly to the author of the PARIDE suite, +by e-mail to grant@torque.net, or join the linux-parport mailing list +and post your report there. + +3.5 For more information or help + +You can join the linux-parport mailing list by sending a mail message +to + linux-parport-request@torque.net + +with the single word + + subscribe + +in the body of the mail message (not in the subject line). Please be +sure that your mail program is correctly set up when you do this, as +the list manager is a robot that will subscribe you using the reply +address in your mail headers. REMOVE any anti-spam gimmicks you may +have in your mail headers, when sending mail to the list server. + +You might also find some useful information on the linux-parport +web pages (although they are not always up to date) at + + http://www.torque.net/parport/ + + diff --git a/Documentation/blockdev/ramdisk.txt b/Documentation/blockdev/ramdisk.txt new file mode 100644 index 000000000000..6c820baa19a6 --- /dev/null +++ b/Documentation/blockdev/ramdisk.txt @@ -0,0 +1,165 @@ +Using the RAM disk block device with Linux +------------------------------------------ + +Contents: + + 1) Overview + 2) Kernel Command Line Parameters + 3) Using "rdev -r" + 4) An Example of Creating a Compressed RAM Disk + + +1) Overview +----------- + +The RAM disk driver is a way to use main system memory as a block device. It +is required for initrd, an initial filesystem used if you need to load modules +in order to access the root filesystem (see Documentation/initrd.txt). It can +also be used for a temporary filesystem for crypto work, since the contents +are erased on reboot. + +The RAM disk dynamically grows as more space is required. It does this by using +RAM from the buffer cache. The driver marks the buffers it is using as dirty +so that the VM subsystem does not try to reclaim them later. + +The RAM disk supports up to 16 RAM disks by default, and can be reconfigured +to support an unlimited number of RAM disks (at your own risk). Just change +the configuration symbol BLK_DEV_RAM_COUNT in the Block drivers config menu +and (re)build the kernel. + +To use RAM disk support with your system, run './MAKEDEV ram' from the /dev +directory. RAM disks are all major number 1, and start with minor number 0 +for /dev/ram0, etc. If used, modern kernels use /dev/ram0 for an initrd. + +The new RAM disk also has the ability to load compressed RAM disk images, +allowing one to squeeze more programs onto an average installation or +rescue floppy disk. + + +2) Kernel Command Line Parameters +--------------------------------- + + ramdisk_size=N + ============== + +This parameter tells the RAM disk driver to set up RAM disks of N k size. The +default is 4096 (4 MB) (8192 (8 MB) on S390). + + ramdisk_blocksize=N + =================== + +This parameter tells the RAM disk driver how many bytes to use per block. The +default is 1024 (BLOCK_SIZE). + + +3) Using "rdev -r" +------------------ + +The usage of the word (two bytes) that "rdev -r" sets in the kernel image is +as follows. The low 11 bits (0 -> 10) specify an offset (in 1 k blocks) of up +to 2 MB (2^11) of where to find the RAM disk (this used to be the size). Bit +14 indicates that a RAM disk is to be loaded, and bit 15 indicates whether a +prompt/wait sequence is to be given before trying to read the RAM disk. Since +the RAM disk dynamically grows as data is being written into it, a size field +is not required. Bits 11 to 13 are not currently used and may as well be zero. +These numbers are no magical secrets, as seen below: + +./arch/i386/kernel/setup.c:#define RAMDISK_IMAGE_START_MASK 0x07FF +./arch/i386/kernel/setup.c:#define RAMDISK_PROMPT_FLAG 0x8000 +./arch/i386/kernel/setup.c:#define RAMDISK_LOAD_FLAG 0x4000 + +Consider a typical two floppy disk setup, where you will have the +kernel on disk one, and have already put a RAM disk image onto disk #2. + +Hence you want to set bits 0 to 13 as 0, meaning that your RAM disk +starts at an offset of 0 kB from the beginning of the floppy. +The command line equivalent is: "ramdisk_start=0" + +You want bit 14 as one, indicating that a RAM disk is to be loaded. +The command line equivalent is: "load_ramdisk=1" + +You want bit 15 as one, indicating that you want a prompt/keypress +sequence so that you have a chance to switch floppy disks. +The command line equivalent is: "prompt_ramdisk=1" + +Putting that together gives 2^15 + 2^14 + 0 = 49152 for an rdev word. +So to create disk one of the set, you would do: + + /usr/src/linux# cat arch/i386/boot/zImage > /dev/fd0 + /usr/src/linux# rdev /dev/fd0 /dev/fd0 + /usr/src/linux# rdev -r /dev/fd0 49152 + +If you make a boot disk that has LILO, then for the above, you would use: + append = "ramdisk_start=0 load_ramdisk=1 prompt_ramdisk=1" +Since the default start = 0 and the default prompt = 1, you could use: + append = "load_ramdisk=1" + + +4) An Example of Creating a Compressed RAM Disk +---------------------------------------------- + +To create a RAM disk image, you will need a spare block device to +construct it on. This can be the RAM disk device itself, or an +unused disk partition (such as an unmounted swap partition). For this +example, we will use the RAM disk device, "/dev/ram0". + +Note: This technique should not be done on a machine with less than 8 MB +of RAM. If using a spare disk partition instead of /dev/ram0, then this +restriction does not apply. + +a) Decide on the RAM disk size that you want. Say 2 MB for this example. + Create it by writing to the RAM disk device. (This step is not currently + required, but may be in the future.) It is wise to zero out the + area (esp. for disks) so that maximal compression is achieved for + the unused blocks of the image that you are about to create. + + dd if=/dev/zero of=/dev/ram0 bs=1k count=2048 + +b) Make a filesystem on it. Say ext2fs for this example. + + mke2fs -vm0 /dev/ram0 2048 + +c) Mount it, copy the files you want to it (eg: /etc/* /dev/* ...) + and unmount it again. + +d) Compress the contents of the RAM disk. The level of compression + will be approximately 50% of the space used by the files. Unused + space on the RAM disk will compress to almost nothing. + + dd if=/dev/ram0 bs=1k count=2048 | gzip -v9 > /tmp/ram_image.gz + +e) Put the kernel onto the floppy + + dd if=zImage of=/dev/fd0 bs=1k + +f) Put the RAM disk image onto the floppy, after the kernel. Use an offset + that is slightly larger than the kernel, so that you can put another + (possibly larger) kernel onto the same floppy later without overlapping + the RAM disk image. An offset of 400 kB for kernels about 350 kB in + size would be reasonable. Make sure offset+size of ram_image.gz is + not larger than the total space on your floppy (usually 1440 kB). + + dd if=/tmp/ram_image.gz of=/dev/fd0 bs=1k seek=400 + +g) Use "rdev" to set the boot device, RAM disk offset, prompt flag, etc. + For prompt_ramdisk=1, load_ramdisk=1, ramdisk_start=400, one would + have 2^15 + 2^14 + 400 = 49552. + + rdev /dev/fd0 /dev/fd0 + rdev -r /dev/fd0 49552 + +That is it. You now have your boot/root compressed RAM disk floppy. Some +users may wish to combine steps (d) and (f) by using a pipe. + +-------------------------------------------------------------------------- + Paul Gortmaker 12/95 + +Changelog: +---------- + +10-22-04 : Updated to reflect changes in command line options, remove + obsolete references, general cleanup. + James Nelson (james4765@gmail.com) + + +12-95 : Original Document diff --git a/Documentation/c2port.txt b/Documentation/c2port.txt new file mode 100644 index 000000000000..d9bf93ea4398 --- /dev/null +++ b/Documentation/c2port.txt @@ -0,0 +1,90 @@ + C2 port support + --------------- + +(C) Copyright 2007 Rodolfo Giometti + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + + +Overview +-------- + +This driver implements the support for Linux of Silicon Labs (Silabs) +C2 Interface used for in-system programming of micro controllers. + +By using this driver you can reprogram the in-system flash without EC2 +or EC3 debug adapter. This solution is also useful in those systems +where the micro controller is connected via special GPIOs pins. + +References +---------- + +The C2 Interface main references are at (http://www.silabs.com) +Silicon Laboratories site], see: + +- AN127: FLASH Programming via the C2 Interface at +http://www.silabs.com/public/documents/tpub_doc/anote/Microcontrollers/Small_Form_Factor/en/an127.pdf, and + +- C2 Specification at +http://www.silabs.com/public/documents/tpub_doc/spec/Microcontrollers/en/C2spec.pdf, + +however it implements a two wire serial communication protocol (bit +banging) designed to enable in-system programming, debugging, and +boundary-scan testing on low pin-count Silicon Labs devices. Currently +this code supports only flash programming but extensions are easy to +add. + +Using the driver +---------------- + +Once the driver is loaded you can use sysfs support to get C2port's +info or read/write in-system flash. + +# ls /sys/class/c2port/c2port0/ +access flash_block_size flash_erase rev_id +dev_id flash_blocks_num flash_size subsystem/ +flash_access flash_data reset uevent + +Initially the C2port access is disabled since you hardware may have +such lines multiplexed with other devices so, to get access to the +C2port, you need the command: + +# echo 1 > /sys/class/c2port/c2port0/access + +after that you should read the device ID and revision ID of the +connected micro controller: + +# cat /sys/class/c2port/c2port0/dev_id +8 +# cat /sys/class/c2port/c2port0/rev_id +1 + +However, for security reasons, the in-system flash access in not +enabled yet, to do so you need the command: + +# echo 1 > /sys/class/c2port/c2port0/flash_access + +After that you can read the whole flash: + +# cat /sys/class/c2port/c2port0/flash_data > image + +erase it: + +# echo 1 > /sys/class/c2port/c2port0/flash_erase + +and write it: + +# cat image > /sys/class/c2port/c2port0/flash_data + +after writing you have to reset the device to execute the new code: + +# echo 1 > /sys/class/c2port/c2port0/reset diff --git a/Documentation/cciss.txt b/Documentation/cciss.txt deleted file mode 100644 index 8244c6442faa..000000000000 --- a/Documentation/cciss.txt +++ /dev/null @@ -1,168 +0,0 @@ -This driver is for Compaq's SMART Array Controllers. - -Supported Cards: ----------------- - -This driver is known to work with the following cards: - - * SA 5300 - * SA 5i - * SA 532 - * SA 5312 - * SA 641 - * SA 642 - * SA 6400 - * SA 6400 U320 Expansion Module - * SA 6i - * SA P600 - * SA P800 - * SA E400 - * SA P400i - * SA E200 - * SA E200i - * SA E500 - * SA P212 - * SA P410 - * SA P410i - * SA P411 - * SA P812 - -Detecting drive failures: -------------------------- - -To get the status of logical volumes and to detect physical drive -failures, you can use the cciss_vol_status program found here: -http://cciss.sourceforge.net/#cciss_utils - -Device Naming: --------------- - -If nodes are not already created in the /dev/cciss directory, run as root: - -# cd /dev -# ./MAKEDEV cciss - -You need some entries in /dev for the cciss device. The MAKEDEV script -can make device nodes for you automatically. Currently the device setup -is as follows: - -Major numbers: - 104 cciss0 - 105 cciss1 - 106 cciss2 - 105 cciss3 - 108 cciss4 - 109 cciss5 - 110 cciss6 - 111 cciss7 - -Minor numbers: - b7 b6 b5 b4 b3 b2 b1 b0 - |----+----| |----+----| - | | - | +-------- Partition ID (0=wholedev, 1-15 partition) - | - +-------------------- Logical Volume number - -The device naming scheme is: -/dev/cciss/c0d0 Controller 0, disk 0, whole device -/dev/cciss/c0d0p1 Controller 0, disk 0, partition 1 -/dev/cciss/c0d0p2 Controller 0, disk 0, partition 2 -/dev/cciss/c0d0p3 Controller 0, disk 0, partition 3 - -/dev/cciss/c1d1 Controller 1, disk 1, whole device -/dev/cciss/c1d1p1 Controller 1, disk 1, partition 1 -/dev/cciss/c1d1p2 Controller 1, disk 1, partition 2 -/dev/cciss/c1d1p3 Controller 1, disk 1, partition 3 - -SCSI tape drive and medium changer support ------------------------------------------- - -SCSI sequential access devices and medium changer devices are supported and -appropriate device nodes are automatically created. (e.g. -/dev/st0, /dev/st1, etc. See the "st" man page for more details.) -You must enable "SCSI tape drive support for Smart Array 5xxx" and -"SCSI support" in your kernel configuration to be able to use SCSI -tape drives with your Smart Array 5xxx controller. - -Additionally, note that the driver will not engage the SCSI core at init -time. The driver must be directed to dynamically engage the SCSI core via -the /proc filesystem entry which the "block" side of the driver creates as -/proc/driver/cciss/cciss* at runtime. This is because at driver init time, -the SCSI core may not yet be initialized (because the driver is a block -driver) and attempting to register it with the SCSI core in such a case -would cause a hang. This is best done via an initialization script -(typically in /etc/init.d, but could vary depending on distribution). -For example: - - for x in /proc/driver/cciss/cciss[0-9]* - do - echo "engage scsi" > $x - done - -Once the SCSI core is engaged by the driver, it cannot be disengaged -(except by unloading the driver, if it happens to be linked as a module.) - -Note also that if no sequential access devices or medium changers are -detected, the SCSI core will not be engaged by the action of the above -script. - -Hot plug support for SCSI tape drives -------------------------------------- - -Hot plugging of SCSI tape drives is supported, with some caveats. -The cciss driver must be informed that changes to the SCSI bus -have been made. This may be done via the /proc filesystem. -For example: - - echo "rescan" > /proc/scsi/cciss0/1 - -This causes the driver to query the adapter about changes to the -physical SCSI buses and/or fibre channel arbitrated loop and the -driver to make note of any new or removed sequential access devices -or medium changers. The driver will output messages indicating what -devices have been added or removed and the controller, bus, target and -lun used to address the device. It then notifies the SCSI mid layer -of these changes. - -Note that the naming convention of the /proc filesystem entries -contains a number in addition to the driver name. (E.g. "cciss0" -instead of just "cciss" which you might expect.) - -Note: ONLY sequential access devices and medium changers are presented -as SCSI devices to the SCSI mid layer by the cciss driver. Specifically, -physical SCSI disk drives are NOT presented to the SCSI mid layer. The -physical SCSI disk drives are controlled directly by the array controller -hardware and it is important to prevent the kernel from attempting to directly -access these devices too, as if the array controller were merely a SCSI -controller in the same way that we are allowing it to access SCSI tape drives. - -SCSI error handling for tape drives and medium changers -------------------------------------------------------- - -The linux SCSI mid layer provides an error handling protocol which -kicks into gear whenever a SCSI command fails to complete within a -certain amount of time (which can vary depending on the command). -The cciss driver participates in this protocol to some extent. The -normal protocol is a four step process. First the device is told -to abort the command. If that doesn't work, the device is reset. -If that doesn't work, the SCSI bus is reset. If that doesn't work -the host bus adapter is reset. Because the cciss driver is a block -driver as well as a SCSI driver and only the tape drives and medium -changers are presented to the SCSI mid layer, and unlike more -straightforward SCSI drivers, disk i/o continues through the block -side during the SCSI error recovery process, the cciss driver only -implements the first two of these actions, aborting the command, and -resetting the device. Additionally, most tape drives will not oblige -in aborting commands, and sometimes it appears they will not even -obey a reset command, though in most circumstances they will. In -the case that the command cannot be aborted and the device cannot be -reset, the device will be set offline. - -In the event the error handling code is triggered and a tape drive is -successfully reset or the tardy command is successfully aborted, the -tape drive may still not allow i/o to continue until some command -is issued which positions the tape to a known position. Typically you -must rewind the tape (by issuing "mt -f /dev/st0 rewind" for example) -before i/o can proceed again to a tape drive which was reset. - diff --git a/Documentation/cgroups/freezer-subsystem.txt b/Documentation/cgroups/freezer-subsystem.txt index c50ab58b72eb..41f37fea1276 100644 --- a/Documentation/cgroups/freezer-subsystem.txt +++ b/Documentation/cgroups/freezer-subsystem.txt @@ -1,4 +1,4 @@ - The cgroup freezer is useful to batch job management system which start +The cgroup freezer is useful to batch job management system which start and stop sets of tasks in order to schedule the resources of a machine according to the desires of a system administrator. This sort of program is often used on HPC clusters to schedule access to the cluster as a @@ -6,7 +6,7 @@ whole. The cgroup freezer uses cgroups to describe the set of tasks to be started/stopped by the batch job management system. It also provides a means to start and stop the tasks composing the job. - The cgroup freezer will also be useful for checkpointing running groups +The cgroup freezer will also be useful for checkpointing running groups of tasks. The freezer allows the checkpoint code to obtain a consistent image of the tasks by attempting to force the tasks in a cgroup into a quiescent state. Once the tasks are quiescent another task can @@ -16,7 +16,7 @@ recoverable error occur. This also allows the checkpointed tasks to be migrated between nodes in a cluster by copying the gathered information to another node and restarting the tasks there. - Sequences of SIGSTOP and SIGCONT are not always sufficient for stopping +Sequences of SIGSTOP and SIGCONT are not always sufficient for stopping and resuming tasks in userspace. Both of these signals are observable from within the tasks we wish to freeze. While SIGSTOP cannot be caught, blocked, or ignored it can be seen by waiting or ptracing parent tasks. @@ -37,26 +37,29 @@ demonstrate this problem using nested bash shells: - This happens because bash can observe both signals and choose how it +This happens because bash can observe both signals and choose how it responds to them. - Another example of a program which catches and responds to these +Another example of a program which catches and responds to these signals is gdb. In fact any program designed to use ptrace is likely to have a problem with this method of stopping and resuming tasks. - In contrast, the cgroup freezer uses the kernel freezer code to +In contrast, the cgroup freezer uses the kernel freezer code to prevent the freeze/unfreeze cycle from becoming visible to the tasks being frozen. This allows the bash example above and gdb to run as expected. - The freezer subsystem in the container filesystem defines a file named +The freezer subsystem in the container filesystem defines a file named freezer.state. Writing "FROZEN" to the state file will freeze all tasks in the cgroup. Subsequently writing "THAWED" will unfreeze the tasks in the cgroup. Reading will return the current state. +Note freezer.state doesn't exist in root cgroup, which means root cgroup +is non-freezable. + * Examples of usage : - # mkdir /containers/freezer + # mkdir /containers # mount -t cgroup -ofreezer freezer /containers # mkdir /containers/0 # echo $some_pid > /containers/0/tasks @@ -94,6 +97,6 @@ things happens: the freezer.state file 2) Userspace retries the freezing operation by writing "FROZEN" to the freezer.state file (writing "FREEZING" is not legal - and returns EIO) + and returns EINVAL) 3) The tasks that blocked the cgroup from entering the "FROZEN" state disappear from the cgroup's set of tasks. diff --git a/Documentation/computone.txt b/Documentation/computone.txt deleted file mode 100644 index 5e2a0c76bfa0..000000000000 --- a/Documentation/computone.txt +++ /dev/null @@ -1,522 +0,0 @@ -NOTE: This is an unmaintained driver. It is not guaranteed to work due to -changes made in the tty layer in 2.6. If you wish to take over maintenance of -this driver, contact Michael Warfield . - -Changelog: ----------- -11-01-2001: Original Document - -10-29-2004: Minor misspelling & format fix, update status of driver. - James Nelson - -Computone Intelliport II/Plus Multiport Serial Driver ------------------------------------------------------ - -Release Notes For Linux Kernel 2.2 and higher. -These notes are for the drivers which have already been integrated into the -kernel and have been tested on Linux kernels 2.0, 2.2, 2.3, and 2.4. - -Version: 1.2.14 -Date: 11/01/2001 -Historical Author: Andrew Manison -Primary Author: Doug McNash -Support: support@computone.com -Fixes and Updates: Mike Warfield - -This file assumes that you are using the Computone drivers which are -integrated into the kernel sources. For updating the drivers or installing -drivers into kernels which do not already have Computone drivers, please -refer to the instructions in the README.computone file in the driver patch. - - -1. INTRODUCTION - -This driver supports the entire family of Intelliport II/Plus controllers -with the exception of the MicroChannel controllers. It does not support -products previous to the Intelliport II. - -This driver was developed on the v2.0.x Linux tree and has been tested up -to v2.4.14; it will probably not work with earlier v1.X kernels,. - - -2. QUICK INSTALLATION - -Hardware - If you have an ISA card, find a free interrupt and io port. - List those in use with `cat /proc/interrupts` and - `cat /proc/ioports`. Set the card dip switches to a free - address. You may need to configure your BIOS to reserve an - irq for an ISA card. PCI and EISA parameters are set - automagically. Insert card into computer with the power off - before or after drivers installation. - - Note the hardware address from the Computone ISA cards installed into - the system. These are required for editing ip2.c or editing - /etc/modprobe.conf, or for specification on the modprobe - command line. - - Note that the /etc/modules.conf should be used for older (pre-2.6) - kernels. - -Software - - -Module installation: - -a) Determine free irq/address to use if any (configure BIOS if need be) -b) Run "make config" or "make menuconfig" or "make xconfig" - Select (m) module for CONFIG_COMPUTONE under character - devices. CONFIG_PCI and CONFIG_MODULES also may need to be set. -c) Set address on ISA cards then: - edit /usr/src/linux/drivers/char/ip2.c if needed - or - edit /etc/modprobe.conf if needed (module). - or both to match this setting. -d) Run "make modules" -e) Run "make modules_install" -f) Run "/sbin/depmod -a" -g) install driver using `modprobe ip2 ` (options listed below) -h) run ip2mkdev (either the script below or the binary version) - - -Kernel installation: - -a) Determine free irq/address to use if any (configure BIOS if need be) -b) Run "make config" or "make menuconfig" or "make xconfig" - Select (y) kernel for CONFIG_COMPUTONE under character - devices. CONFIG_PCI may need to be set if you have PCI bus. -c) Set address on ISA cards then: - edit /usr/src/linux/drivers/char/ip2.c - (Optional - may be specified on kernel command line now) -d) Run "make zImage" or whatever target you prefer. -e) mv /usr/src/linux/arch/i386/boot/zImage to /boot. -f) Add new config for this kernel into /etc/lilo.conf, run "lilo" - or copy to a floppy disk and boot from that floppy disk. -g) Reboot using this kernel -h) run ip2mkdev (either the script below or the binary version) - -Kernel command line options: - -When compiling the driver into the kernel, io and irq may be -compiled into the driver by editing ip2.c and setting the values for -io and irq in the appropriate array. An alternative is to specify -a command line parameter to the kernel at boot up. - - ip2=io0,irq0,io1,irq1,io2,irq2,io3,irq3 - -Note that this order is very different from the specifications for the -modload parameters which have separate IRQ and IO specifiers. - -The io port also selects PCI (1) and EISA (2) boards. - - io=0 No board - io=1 PCI board - io=2 EISA board - else ISA board io address - -You only need to specify the boards which are present. - - Examples: - - 2 PCI boards: - - ip2=1,0,1,0 - - 1 ISA board at 0x310 irq 5: - - ip2=0x310,5 - -This can be added to and "append" option in lilo.conf similar to this: - - append="ip2=1,0,1,0" - - -3. INSTALLATION - -Previously, the driver sources were packaged with a set of patch files -to update the character drivers' makefile and configuration file, and other -kernel source files. A build script (ip2build) was included which applies -the patches if needed, and build any utilities needed. -What you receive may be a single patch file in conventional kernel -patch format build script. That form can also be applied by -running patch -p1 < ThePatchFile. Otherwise run ip2build. - -The driver can be installed as a module (recommended) or built into the -kernel. This is selected as for other drivers through the `make config` -command from the root of the Linux source tree. If the driver is built -into the kernel you will need to edit the file ip2.c to match the boards -you are installing. See that file for instructions. If the driver is -installed as a module the configuration can also be specified on the -modprobe command line as follows: - - modprobe ip2 irq=irq1,irq2,irq3,irq4 io=addr1,addr2,addr3,addr4 - -where irqnum is one of the valid Intelliport II interrupts (3,4,5,7,10,11, -12,15) and addr1-4 are the base addresses for up to four controllers. If -the irqs are not specified the driver uses the default in ip2.c (which -selects polled mode). If no base addresses are specified the defaults in -ip2.c are used. If you are autoloading the driver module with kerneld or -kmod the base addresses and interrupt number must also be set in ip2.c -and recompile or just insert and options line in /etc/modprobe.conf or both. -The options line is equivalent to the command line and takes precedence over -what is in ip2.c. - -/etc/modprobe.conf sample: - options ip2 io=1,0x328 irq=1,10 - alias char-major-71 ip2 - alias char-major-72 ip2 - alias char-major-73 ip2 - -The equivalent in ip2.c: - -static int io[IP2_MAX_BOARDS]= { 1, 0x328, 0, 0 }; -static int irq[IP2_MAX_BOARDS] = { 1, 10, -1, -1 }; - -The equivalent for the kernel command line (in lilo.conf): - - append="ip2=1,1,0x328,10" - - -Note: Both io and irq should be updated to reflect YOUR system. An "io" - address of 1 or 2 indicates a PCI or EISA card in the board table. - The PCI or EISA irq will be assigned automatically. - -Specifying an invalid or in-use irq will default the driver into -running in polled mode for that card. If all irq entries are 0 then -all cards will operate in polled mode. - -If you select the driver as part of the kernel run : - - make zlilo (or whatever you do to create a bootable kernel) - -If you selected a module run : - - make modules && make modules_install - -The utility ip2mkdev (see 5 and 7 below) creates all the device nodes -required by the driver. For a device to be created it must be configured -in the driver and the board must be installed. Only devices corresponding -to real IntelliPort II ports are created. With multiple boards and expansion -boxes this will leave gaps in the sequence of device names. ip2mkdev uses -Linux tty naming conventions: ttyF0 - ttyF255 for normal devices, and -cuf0 - cuf255 for callout devices. - - -4. USING THE DRIVERS - -As noted above, the driver implements the ports in accordance with Linux -conventions, and the devices should be interchangeable with the standard -serial devices. (This is a key point for problem reporting: please make -sure that what you are trying do works on the ttySx/cuax ports first; then -tell us what went wrong with the ip2 ports!) - -Higher speeds can be obtained using the setserial utility which remaps -38,400 bps (extb) to 57,600 bps, 115,200 bps, or a custom speed. -Intelliport II installations using the PowerPort expansion module can -use the custom speed setting to select the highest speeds: 153,600 bps, -230,400 bps, 307,200 bps, 460,800bps and 921,600 bps. The base for -custom baud rate configuration is fixed at 921,600 for cards/expansion -modules with ST654's and 115200 for those with Cirrus CD1400's. This -corresponds to the maximum bit rates those chips are capable. -For example if the baud base is 921600 and the baud divisor is 18 then -the custom rate is 921600/18 = 51200 bps. See the setserial man page for -complete details. Of course if stty accepts the higher rates now you can -use that as well as the standard ioctls(). - - -5. ip2mkdev and assorted utilities... - -Several utilities, including the source for a binary ip2mkdev utility are -available under .../drivers/char/ip2. These can be build by changing to -that directory and typing "make" after the kernel has be built. If you do -not wish to compile the binary utilities, the shell script below can be -cut out and run as "ip2mkdev" to create the necessary device files. To -use the ip2mkdev script, you must have procfs enabled and the proc file -system mounted on /proc. - - -6. NOTES - -This is a release version of the driver, but it is impossible to test it -in all configurations of Linux. If there is any anomalous behaviour that -does not match the standard serial port's behaviour please let us know. - - -7. ip2mkdev shell script - -Previously, this script was simply attached here. It is now attached as a -shar archive to make it easier to extract the script from the documentation. -To create the ip2mkdev shell script change to a convenient directory (/tmp -works just fine) and run the following command: - - unshar Documentation/computone.txt - (This file) - -You should now have a file ip2mkdev in your current working directory with -permissions set to execute. Running that script with then create the -necessary devices for the Computone boards, interfaces, and ports which -are present on you system at the time it is run. - - -#!/bin/sh -# This is a shell archive (produced by GNU sharutils 4.2.1). -# To extract the files from this archive, save it to some FILE, remove -# everything before the `!/bin/sh' line above, then type `sh FILE'. -# -# Made on 2001-10-29 10:32 EST by . -# Source directory was `/home2/src/tmp'. -# -# Existing files will *not* be overwritten unless `-c' is specified. -# -# This shar contains: -# length mode name -# ------ ---------- ------------------------------------------ -# 4251 -rwxr-xr-x ip2mkdev -# -save_IFS="${IFS}" -IFS="${IFS}:" -gettext_dir=FAILED -locale_dir=FAILED -first_param="$1" -for dir in $PATH -do - if test "$gettext_dir" = FAILED && test -f $dir/gettext \ - && ($dir/gettext --version >/dev/null 2>&1) - then - set `$dir/gettext --version 2>&1` - if test "$3" = GNU - then - gettext_dir=$dir - fi - fi - if test "$locale_dir" = FAILED && test -f $dir/shar \ - && ($dir/shar --print-text-domain-dir >/dev/null 2>&1) - then - locale_dir=`$dir/shar --print-text-domain-dir` - fi -done -IFS="$save_IFS" -if test "$locale_dir" = FAILED || test "$gettext_dir" = FAILED -then - echo=echo -else - TEXTDOMAINDIR=$locale_dir - export TEXTDOMAINDIR - TEXTDOMAIN=sharutils - export TEXTDOMAIN - echo="$gettext_dir/gettext -s" -fi -if touch -am -t 200112312359.59 $$.touch >/dev/null 2>&1 && test ! -f 200112312359.59 -a -f $$.touch; then - shar_touch='touch -am -t $1$2$3$4$5$6.$7 "$8"' -elif touch -am 123123592001.59 $$.touch >/dev/null 2>&1 && test ! -f 123123592001.59 -a ! -f 123123592001.5 -a -f $$.touch; then - shar_touch='touch -am $3$4$5$6$1$2.$7 "$8"' -elif touch -am 1231235901 $$.touch >/dev/null 2>&1 && test ! -f 1231235901 -a -f $$.touch; then - shar_touch='touch -am $3$4$5$6$2 "$8"' -else - shar_touch=: - echo - $echo 'WARNING: not restoring timestamps. Consider getting and' - $echo "installing GNU \`touch', distributed in GNU File Utilities..." - echo -fi -rm -f 200112312359.59 123123592001.59 123123592001.5 1231235901 $$.touch -# -if mkdir _sh17581; then - $echo 'x -' 'creating lock directory' -else - $echo 'failed to create lock directory' - exit 1 -fi -# ============= ip2mkdev ============== -if test -f 'ip2mkdev' && test "$first_param" != -c; then - $echo 'x -' SKIPPING 'ip2mkdev' '(file already exists)' -else - $echo 'x -' extracting 'ip2mkdev' '(text)' - sed 's/^X//' << 'SHAR_EOF' > 'ip2mkdev' && -#!/bin/sh - -# -# ip2mkdev -# -# Make or remove devices as needed for Computone Intelliport drivers -# -# First rule! If the dev file exists and you need it, don't mess -# with it. That prevents us from screwing up open ttys, ownership -# and permissions on a running system! -# -# This script will NOT remove devices that no longer exist if their -# board or interface box has been removed. If you want to get rid -# of them, you can manually do an "rm -f /dev/ttyF* /dev/cuaf*" -# before running this script. Running this script will then recreate -# all the valid devices. -# -# Michael H. Warfield -# /\/\|=mhw=|\/\/ -# mhw@wittsend.com -# -# Updated 10/29/2000 for version 1.2.13 naming convention -# under devfs. /\/\|=mhw=|\/\/ -# -# Updated 03/09/2000 for devfs support in ip2 drivers. /\/\|=mhw=|\/\/ -# -X -if test -d /dev/ip2 ; then -# This is devfs mode... We don't do anything except create symlinks -# from the real devices to the old names! -X cd /dev -X echo "Creating symbolic links to devfs devices" -X for i in `ls ip2` ; do -X if test ! -L ip2$i ; then -X # Remove it incase it wasn't a symlink (old device) -X rm -f ip2$i -X ln -s ip2/$i ip2$i -X fi -X done -X for i in `( cd tts ; ls F* )` ; do -X if test ! -L tty$i ; then -X # Remove it incase it wasn't a symlink (old device) -X rm -f tty$i -X ln -s tts/$i tty$i -X fi -X done -X for i in `( cd cua ; ls F* )` ; do -X DEVNUMBER=`expr $i : 'F\(.*\)'` -X if test ! -L cuf$DEVNUMBER ; then -X # Remove it incase it wasn't a symlink (old device) -X rm -f cuf$DEVNUMBER -X ln -s cua/$i cuf$DEVNUMBER -X fi -X done -X exit 0 -fi -X -if test ! -f /proc/tty/drivers -then -X echo "\ -Unable to check driver status. -Make sure proc file system is mounted." -X -X exit 255 -fi -X -if test ! -f /proc/tty/driver/ip2 -then -X echo "\ -Unable to locate ip2 proc file. -Attempting to load driver" -X -X if /sbin/insmod ip2 -X then -X if test ! -f /proc/tty/driver/ip2 -X then -X echo "\ -Unable to locate ip2 proc file after loading driver. -Driver initialization failure or driver version error. -" -X exit 255 -X fi -X else -X echo "Unable to load ip2 driver." -X exit 255 -X fi -fi -X -# Ok... So we got the driver loaded and we can locate the procfs files. -# Next we need our major numbers. -X -TTYMAJOR=`sed -e '/^ip2/!d' -e '/\/dev\/tt/!d' -e 's/.*tt[^ ]*[ ]*\([0-9]*\)[ ]*.*/\1/' < /proc/tty/drivers` -CUAMAJOR=`sed -e '/^ip2/!d' -e '/\/dev\/cu/!d' -e 's/.*cu[^ ]*[ ]*\([0-9]*\)[ ]*.*/\1/' < /proc/tty/drivers` -BRDMAJOR=`sed -e '/^Driver: /!d' -e 's/.*IMajor=\([0-9]*\)[ ]*.*/\1/' < /proc/tty/driver/ip2` -X -echo "\ -TTYMAJOR = $TTYMAJOR -CUAMAJOR = $CUAMAJOR -BRDMAJOR = $BRDMAJOR -" -X -# Ok... Now we should know our major numbers, if appropriate... -# Now we need our boards and start the device loops. -X -grep '^Board [0-9]:' /proc/tty/driver/ip2 | while read token number type alltherest -do -X # The test for blank "type" will catch the stats lead-in lines -X # if they exist in the file -X if test "$type" = "vacant" -o "$type" = "Vacant" -o "$type" = "" -X then -X continue -X fi -X -X BOARDNO=`expr "$number" : '\([0-9]\):'` -X PORTS=`expr "$alltherest" : '.*ports=\([0-9]*\)' | tr ',' ' '` -X MINORS=`expr "$alltherest" : '.*minors=\([0-9,]*\)' | tr ',' ' '` -X -X if test "$BOARDNO" = "" -o "$PORTS" = "" -X then -# This may be a bug. We should at least get this much information -X echo "Unable to process board line" -X continue -X fi -X -X if test "$MINORS" = "" -X then -# Silently skip this one. This board seems to have no boxes -X continue -X fi -X -X echo "board $BOARDNO: $type ports = $PORTS; port numbers = $MINORS" -X -X if test "$BRDMAJOR" != "" -X then -X BRDMINOR=`expr $BOARDNO \* 4` -X STSMINOR=`expr $BRDMINOR + 1` -X if test ! -c /dev/ip2ipl$BOARDNO ; then -X mknod /dev/ip2ipl$BOARDNO c $BRDMAJOR $BRDMINOR -X fi -X if test ! -c /dev/ip2stat$BOARDNO ; then -X mknod /dev/ip2stat$BOARDNO c $BRDMAJOR $STSMINOR -X fi -X fi -X -X if test "$TTYMAJOR" != "" -X then -X PORTNO=$BOARDBASE -X -X for PORTNO in $MINORS -X do -X if test ! -c /dev/ttyF$PORTNO ; then -X # We got the hardware but no device - make it -X mknod /dev/ttyF$PORTNO c $TTYMAJOR $PORTNO -X fi -X done -X fi -X -X if test "$CUAMAJOR" != "" -X then -X PORTNO=$BOARDBASE -X -X for PORTNO in $MINORS -X do -X if test ! -c /dev/cuf$PORTNO ; then -X # We got the hardware but no device - make it -X mknod /dev/cuf$PORTNO c $CUAMAJOR $PORTNO -X fi -X done -X fi -done -X -Xexit 0 -SHAR_EOF - (set 20 01 10 29 10 32 01 'ip2mkdev'; eval "$shar_touch") && - chmod 0755 'ip2mkdev' || - $echo 'restore of' 'ip2mkdev' 'failed' - if ( md5sum --help 2>&1 | grep 'sage: md5sum \[' ) >/dev/null 2>&1 \ - && ( md5sum --version 2>&1 | grep -v 'textutils 1.12' ) >/dev/null; then - md5sum -c << SHAR_EOF >/dev/null 2>&1 \ - || $echo 'ip2mkdev:' 'MD5 check failed' -cb5717134509f38bad9fde6b1f79b4a4 ip2mkdev -SHAR_EOF - else - shar_count="`LC_ALL= LC_CTYPE= LANG= wc -c < 'ip2mkdev'`" - test 4251 -eq "$shar_count" || - $echo 'ip2mkdev:' 'original size' '4251,' 'current size' "$shar_count!" - fi -fi -rm -fr _sh17581 -exit 0 diff --git a/Documentation/connector/.gitignore b/Documentation/connector/.gitignore new file mode 100644 index 000000000000..d2b9c32accd4 --- /dev/null +++ b/Documentation/connector/.gitignore @@ -0,0 +1 @@ +ucon diff --git a/Documentation/cpqarray.txt b/Documentation/cpqarray.txt deleted file mode 100644 index c7154e20ef5e..000000000000 --- a/Documentation/cpqarray.txt +++ /dev/null @@ -1,93 +0,0 @@ -This driver is for Compaq's SMART2 Intelligent Disk Array Controllers. - -Supported Cards: ----------------- - -This driver is known to work with the following cards: - - * SMART (EISA) - * SMART-2/E (EISA) - * SMART-2/P - * SMART-2DH - * SMART-2SL - * SMART-221 - * SMART-3100ES - * SMART-3200 - * Integrated Smart Array Controller - * SA 4200 - * SA 4250ES - * SA 431 - * RAID LC2 Controller - -It should also work with some really old Disk array adapters, but I am -unable to test against these cards: - - * IDA - * IDA-2 - * IAES - - -EISA Controllers: ------------------ - -If you want to use an EISA controller you'll have to supply some -modprobe/lilo parameters. If the driver is compiled into the kernel, must -give it the controller's IO port address at boot time (it is not -necessary to specify the IRQ). For example, if you had two SMART-2/E -controllers, in EISA slots 1 and 2 you'd give it a boot argument like -this: - - smart2=0x1000,0x2000 - -If you were loading the driver as a module, you'd give load it like this: - - modprobe cpqarray eisa=0x1000,0x2000 - -You can use EISA and PCI adapters at the same time. - - -Device Naming: --------------- - -You need some entries in /dev for the ida device. MAKEDEV in the /dev -directory can make device nodes for you automatically. The device setup is -as follows: - -Major numbers: - 72 ida0 - 73 ida1 - 74 ida2 - 75 ida3 - 76 ida4 - 77 ida5 - 78 ida6 - 79 ida7 - -Minor numbers: - b7 b6 b5 b4 b3 b2 b1 b0 - |----+----| |----+----| - | | - | +-------- Partition ID (0=wholedev, 1-15 partition) - | - +-------------------- Logical Volume number - -The device naming scheme is: -/dev/ida/c0d0 Controller 0, disk 0, whole device -/dev/ida/c0d0p1 Controller 0, disk 0, partition 1 -/dev/ida/c0d0p2 Controller 0, disk 0, partition 2 -/dev/ida/c0d0p3 Controller 0, disk 0, partition 3 - -/dev/ida/c1d1 Controller 1, disk 1, whole device -/dev/ida/c1d1p1 Controller 1, disk 1, partition 1 -/dev/ida/c1d1p2 Controller 1, disk 1, partition 2 -/dev/ida/c1d1p3 Controller 1, disk 1, partition 3 - - -Changelog: -========== - -10-28-2004 : General cleanup, syntax fixes for in-kernel driver version. - James Nelson - - -1999 : Original Document diff --git a/Documentation/cpu-freq/user-guide.txt b/Documentation/cpu-freq/user-guide.txt index 6c442d8426b5..4f3f3840320e 100644 --- a/Documentation/cpu-freq/user-guide.txt +++ b/Documentation/cpu-freq/user-guide.txt @@ -23,6 +23,7 @@ Contents: 1.3 sparc64 1.4 ppc 1.5 SuperH +1.6 Blackfin 2. "Policy" / "Governor"? 2.1 Policy @@ -97,6 +98,17 @@ The following SuperH processors are supported by cpufreq: SH-3 SH-4 +1.6 Blackfin +------------ + +The following Blackfin processors are supported by cpufreq: + +BF522, BF523, BF524, BF525, BF526, BF527, Rev 0.1 or higher +BF531, BF532, BF533, Rev 0.3 or higher +BF534, BF536, BF537, Rev 0.2 or higher +BF561, Rev 0.3 or higher +BF542, BF544, BF547, BF548, BF549, Rev 0.1 or higher + 2. "Policy" / "Governor" ? ========================== diff --git a/Documentation/digiepca.txt b/Documentation/digiepca.txt deleted file mode 100644 index f2560e22f2c9..000000000000 --- a/Documentation/digiepca.txt +++ /dev/null @@ -1,98 +0,0 @@ -NOTE: This driver is obsolete. Digi provides a 2.6 driver (dgdm) at -http://www.digi.com for PCI cards. They no longer maintain this driver, -and have no 2.6 driver for ISA cards. - -This driver requires a number of user-space tools. They can be acquired from -http://www.digi.com, but only works with 2.4 kernels. - - -The Digi Intl. epca driver. ----------------------------- -The Digi Intl. epca driver for Linux supports the following boards: - -Digi PC/Xem, PC/Xr, PC/Xe, PC/Xi, PC/Xeve -Digi EISA/Xem, PCI/Xem, PCI/Xr - -Limitations: ------------- -Currently the driver only autoprobes for supported PCI boards. - -The Linux MAKEDEV command does not support generating the Digiboard -Devices. Users executing digiConfig to setup EISA and PC series cards -will have their device nodes automatically constructed (cud?? for ~CLOCAL, -and ttyD?? for CLOCAL). Users wishing to boot their board from the LILO -prompt, or those users booting PCI cards may use buildDIGI to construct -the necessary nodes. - -Notes: ------- -This driver may be configured via LILO. For users who have already configured -their driver using digiConfig, configuring from LILO will override previous -settings. Multiple boards may be configured by issuing multiple LILO command -lines. For examples see the bottom of this document. - -Device names start at 0 and continue up. Beware of this as previous Digi -drivers started device names with 1. - -PCI boards are auto-detected and configured by the driver. PCI boards will -be allocated device numbers (internally) beginning with the lowest PCI slot -first. In other words a PCI card in slot 3 will always have higher device -nodes than a PCI card in slot 1. - -LILO config examples: ---------------------- -Using LILO's APPEND command, a string of comma separated identifiers or -integers can be used to configure supported boards. The six values in order -are: - - Enable/Disable this card or Override, - Type of card: PC/Xe (AccelePort) (0), PC/Xeve (1), PC/Xem or PC/Xr (2), - EISA/Xem (3), PC/64Xe (4), PC/Xi (5), - Enable/Disable alternate pin arrangement, - Number of ports on this card, - I/O Port where card is configured (in HEX if using string identifiers), - Base of memory window (in HEX if using string identifiers), - -NOTE : PCI boards are auto-detected and configured. Do not attempt to -configure PCI boards with the LILO append command. If you wish to override -previous configuration data (As set by digiConfig), but you do not wish to -configure any specific card (Example if there are PCI cards in the system) -the following override command will accomplish this: --> append="digi=2" - -Samples: - append="digiepca=E,PC/Xe,D,16,200,D0000" - or - append="digi=1,0,0,16,512,851968" - -Supporting Tools: ------------------ -Supporting tools include digiDload, digiConfig, buildPCI, and ditty. See -drivers/char/README.epca for more details. Note, -this driver REQUIRES that digiDload be executed prior to it being used. -Failure to do this will result in an ENODEV error. - -Documentation: --------------- -Complete documentation for this product may be found in the tool package. - -Sources of information and support: ------------------------------------ -Digi Intl. support site for this product: - --> http://www.digi.com - -Acknowledgments: ----------------- -Much of this work (And even text) was derived from a similar document -supporting the original public domain DigiBoard driver Copyright (C) -1994,1995 Troy De Jongh. Many thanks to Christoph Lameter -(christoph@lameter.com) and Mike McLagan (mike.mclagan@linux.org) who authored -and contributed to the original document. - -Changelog: ----------- -10-29-04: Update status of driver, remove dead links in document - James Nelson - -2000 (?) Original Document diff --git a/Documentation/email-clients.txt b/Documentation/email-clients.txt index 2ebb94d6ed8e..a618efab7b15 100644 --- a/Documentation/email-clients.txt +++ b/Documentation/email-clients.txt @@ -213,4 +213,29 @@ TkRat (GUI) Works. Use "Insert file..." or external editor. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Gmail (Web GUI) + +If you just have to use Gmail to send patches, it CAN be made to work. It +requires a bit of external help, though. + +The first problem is that Gmail converts tabs to spaces. This will +totally break your patches. To prevent this, you have to use a different +editor. There is a firefox extension called "ViewSourceWith" +(https://addons.mozilla.org/en-US/firefox/addon/394) which allows you to +edit any text box in the editor of your choice. Configure it to launch +your favorite editor. When you want to send a patch, use this technique. +Once you have crafted your messsage + patch, save and exit the editor, +which should reload the Gmail edit box. GMAIL WILL PRESERVE THE TABS. +Hoorah. Apparently you can cut-n-paste literal tabs, but Gmail will +convert those to spaces upon sending! + +The second problem is that Gmail converts tabs to spaces on replies. If +you reply to a patch, don't expect to be able to apply it as a patch. + +The last problem is that Gmail will base64-encode any message that has a +non-ASCII character. That includes things like European names. Be aware. + +Gmail is not convenient for lkml patches, but CAN be made to work. + ### diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 05d71b4b9430..1a8af7354e79 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -56,30 +56,6 @@ Who: Mauro Carvalho Chehab --------------------------- -What: old tuner-3036 i2c driver -When: 2.6.28 -Why: This driver is for VERY old i2c-over-parallel port teletext receiver - boxes. Rather then spending effort on converting this driver to V4L2, - and since it is extremely unlikely that anyone still uses one of these - devices, it was decided to drop it. -Who: Hans Verkuil - Mauro Carvalho Chehab - - --------------------------- - -What: V4L2 dpc7146 driver -When: 2.6.28 -Why: Old driver for the dpc7146 demonstration board that is no longer - relevant. The last time this was tested on actual hardware was - probably around 2002. Since this is a driver for a demonstration - board the decision was made to remove it rather than spending a - lot of effort continually updating this driver to stay in sync - with the latest internal V4L2 or I2C API. -Who: Hans Verkuil - Mauro Carvalho Chehab - ---------------------------- - What: PCMCIA control ioctl (needed for pcmcia-cs [cardmgr, cardctl]) When: November 2005 Files: drivers/pcmcia/: pcmcia_ioctl.c @@ -268,18 +244,6 @@ Who: Michael Buesch --------------------------- -What: init_mm export -When: 2.6.26 -Why: Not used in-tree. The current out-of-tree users used it to - work around problems in the CPA code which should be resolved - by now. One usecase was described to provide verification code - of the CPA operation. That's a good idea in general, but such - code / infrastructure should be in the kernel and not in some - out-of-tree driver. -Who: Thomas Gleixner - ----------------------------- - What: usedac i386 kernel parameter When: 2.6.27 Why: replaced by allowdac and no dac combination diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 8362860e21a7..23d2f4460deb 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -161,8 +161,12 @@ prototypes: int (*set_page_dirty)(struct page *page); int (*readpages)(struct file *filp, struct address_space *mapping, struct list_head *pages, unsigned nr_pages); - int (*prepare_write)(struct file *, struct page *, unsigned, unsigned); - int (*commit_write)(struct file *, struct page *, unsigned, unsigned); + int (*write_begin)(struct file *, struct address_space *mapping, + loff_t pos, unsigned len, unsigned flags, + struct page **pagep, void **fsdata); + int (*write_end)(struct file *, struct address_space *mapping, + loff_t pos, unsigned len, unsigned copied, + struct page *page, void *fsdata); sector_t (*bmap)(struct address_space *, sector_t); int (*invalidatepage) (struct page *, unsigned long); int (*releasepage) (struct page *, int); @@ -180,8 +184,6 @@ sync_page: no maybe writepages: no set_page_dirty no no readpages: no -prepare_write: no yes yes -commit_write: no yes yes write_begin: no locks the page yes write_end: no yes, unlocks yes perform_write: no n/a yes @@ -191,7 +193,7 @@ releasepage: no yes direct_IO: no launder_page: no yes - ->prepare_write(), ->commit_write(), ->sync_page() and ->readpage() + ->write_begin(), ->write_end(), ->sync_page() and ->readpage() may be called from the request handler (/dev/loop). ->readpage() unlocks the page, either synchronously or via I/O diff --git a/Documentation/filesystems/ocfs2.txt b/Documentation/filesystems/ocfs2.txt index 4340cc825796..67310fbbb7df 100644 --- a/Documentation/filesystems/ocfs2.txt +++ b/Documentation/filesystems/ocfs2.txt @@ -28,10 +28,7 @@ Manish Singh Caveats ======= Features which OCFS2 does not support yet: - - extended attributes - quotas - - cluster aware flock - - cluster aware lockf - Directory change notification (F_NOTIFY) - Distributed Caching (F_SETLEASE/F_GETLEASE/break_lease) - POSIX ACLs diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index bcceb99b81dd..71df353e367c 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -44,6 +44,7 @@ Table of Contents 2.14 /proc//io - Display the IO accounting fields 2.15 /proc//coredump_filter - Core dump filtering settings 2.16 /proc//mountinfo - Information about mounts + 2.17 /proc/sys/fs/epoll - Configuration options for the epoll interface ------------------------------------------------------------------------------ Preface @@ -1338,10 +1339,13 @@ nmi_watchdog Enables/Disables the NMI watchdog on x86 systems. When the value is non-zero the NMI watchdog is enabled and will continuously test all online cpus to -determine whether or not they are still functioning properly. +determine whether or not they are still functioning properly. Currently, +passing "nmi_watchdog=" parameter at boot time is required for this function +to work. -Because the NMI watchdog shares registers with oprofile, by disabling the NMI -watchdog, oprofile may have more registers to utilize. +If LAPIC NMI watchdog method is in use (nmi_watchdog=2 kernel parameter), the +NMI watchdog shares registers with oprofile. By disabling the NMI watchdog, +oprofile may have more registers to utilize. msgmni ------ @@ -2483,4 +2487,30 @@ For more information on mount propagation see: Documentation/filesystems/sharedsubtree.txt +2.17 /proc/sys/fs/epoll - Configuration options for the epoll interface +-------------------------------------------------------- + +This directory contains configuration options for the epoll(7) interface. + +max_user_instances +------------------ + +This is the maximum number of epoll file descriptors that a single user can +have open at a given time. The default value is 128, and should be enough +for normal users. + +max_user_watches +---------------- + +Every epoll file descriptor can store a number of files to be monitored +for event readiness. Each one of these monitored files constitutes a "watch". +This configuration option sets the maximum number of "watches" that are +allowed for each user. +Each "watch" costs roughly 90 bytes on a 32bit kernel, and roughly 160 bytes +on a 64bit one. +The current default value for max_user_watches is the 1/32 of the available +low memory, divided for the "watch" cost in bytes. + + ------------------------------------------------------------------------------ + diff --git a/Documentation/filesystems/ramfs-rootfs-initramfs.txt b/Documentation/filesystems/ramfs-rootfs-initramfs.txt index 62fe9b1e0890..a8273d5fad20 100644 --- a/Documentation/filesystems/ramfs-rootfs-initramfs.txt +++ b/Documentation/filesystems/ramfs-rootfs-initramfs.txt @@ -130,12 +130,12 @@ The 2.6 kernel build process always creates a gzipped cpio format initramfs archive and links it into the resulting kernel binary. By default, this archive is empty (consuming 134 bytes on x86). -The config option CONFIG_INITRAMFS_SOURCE (for some reason buried under -devices->block devices in menuconfig, and living in usr/Kconfig) can be used -to specify a source for the initramfs archive, which will automatically be -incorporated into the resulting binary. This option can point to an existing -gzipped cpio archive, a directory containing files to be archived, or a text -file specification such as the following example: +The config option CONFIG_INITRAMFS_SOURCE (in General Setup in menuconfig, +and living in usr/Kconfig) can be used to specify a source for the +initramfs archive, which will automatically be incorporated into the +resulting binary. This option can point to an existing gzipped cpio +archive, a directory containing files to be archived, or a text file +specification such as the following example: dir /dev 755 0 0 nod /dev/console 644 0 0 c 5 1 diff --git a/Documentation/filesystems/vfat.txt b/Documentation/filesystems/vfat.txt index bbac4f1d9056..3a5ddc96901a 100644 --- a/Documentation/filesystems/vfat.txt +++ b/Documentation/filesystems/vfat.txt @@ -8,6 +8,12 @@ if you want to format from within Linux. VFAT MOUNT OPTIONS ---------------------------------------------------------------------- +uid=### -- Set the owner of all files on this filesystem. + The default is the uid of current process. + +gid=### -- Set the group of all files on this filesystem. + The default is the gid of current process. + umask=### -- The permission mask (for files and directories, see umask(1)). The default is the umask of current process. @@ -36,7 +42,7 @@ codepage=### -- Sets the codepage number for converting to shortname characters on FAT filesystem. By default, FAT_DEFAULT_CODEPAGE setting is used. -iocharset=name -- Character set to use for converting between the +iocharset= -- Character set to use for converting between the encoding is used for user visible filename and 16 bit Unicode characters. Long filenames are stored on disk in Unicode format, but Unix for the most part doesn't @@ -86,6 +92,8 @@ check=s|r|n -- Case sensitivity checking setting. r: relaxed, case insensitive n: normal, default setting, currently case insensitive +nocase -- This was deprecated for vfat. Use shortname=win95 instead. + shortname=lower|win95|winnt|mixed -- Shortname display/create setting. lower: convert to lowercase for display, @@ -99,11 +107,31 @@ shortname=lower|win95|winnt|mixed tz=UTC -- Interpret timestamps as UTC rather than local time. This option disables the conversion of timestamps between local time (as used by Windows on FAT) and UTC - (which Linux uses internally). This is particuluarly + (which Linux uses internally). This is particularly useful when mounting devices (like digital cameras) that are set to UTC in order to avoid the pitfalls of local time. +showexec -- If set, the execute permission bits of the file will be + allowed only if the extension part of the name is .EXE, + .COM, or .BAT. Not set by default. + +debug -- Can be set, but unused by the current implementation. + +sys_immutable -- If set, ATTR_SYS attribute on FAT is handled as + IMMUTABLE flag on Linux. Not set by default. + +flush -- If set, the filesystem will try to flush to disk more + early than normal. Not set by default. + +rodir -- FAT has the ATTR_RO (read-only) attribute. But on Windows, + the ATTR_RO of the directory will be just ignored actually, + and is used by only applications as flag. E.g. it's setted + for the customized folder. + + If you want to use ATTR_RO as read-only flag even for + the directory, set this option. + : 0,1,yes,no,true,false TODO diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index c4d348dabe94..5579bda58a6d 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -492,7 +492,7 @@ written-back to storage typically in whole pages, however the address_space has finer control of write sizes. The read process essentially only requires 'readpage'. The write -process is more complicated and uses prepare_write/commit_write or +process is more complicated and uses write_begin/write_end or set_page_dirty to write data into the address_space, and writepage, sync_page, and writepages to writeback data to storage. @@ -521,8 +521,6 @@ struct address_space_operations { int (*set_page_dirty)(struct page *page); int (*readpages)(struct file *filp, struct address_space *mapping, struct list_head *pages, unsigned nr_pages); - int (*prepare_write)(struct file *, struct page *, unsigned, unsigned); - int (*commit_write)(struct file *, struct page *, unsigned, unsigned); int (*write_begin)(struct file *, struct address_space *mapping, loff_t pos, unsigned len, unsigned flags, struct page **pagep, void **fsdata); @@ -598,37 +596,7 @@ struct address_space_operations { readpages is only used for read-ahead, so read errors are ignored. If anything goes wrong, feel free to give up. - prepare_write: called by the generic write path in VM to set up a write - request for a page. This indicates to the address space that - the given range of bytes is about to be written. The - address_space should check that the write will be able to - complete, by allocating space if necessary and doing any other - internal housekeeping. If the write will update parts of - any basic-blocks on storage, then those blocks should be - pre-read (if they haven't been read already) so that the - updated blocks can be written out properly. - The page will be locked. - - Note: the page _must not_ be marked uptodate in this function - (or anywhere else) unless it actually is uptodate right now. As - soon as a page is marked uptodate, it is possible for a concurrent - read(2) to copy it to userspace. - - commit_write: If prepare_write succeeds, new data will be copied - into the page and then commit_write will be called. It will - typically update the size of the file (if appropriate) and - mark the inode as dirty, and do any other related housekeeping - operations. It should avoid returning an error if possible - - errors should have been handled by prepare_write. - - write_begin: This is intended as a replacement for prepare_write. The - key differences being that: - - it returns a locked page (in *pagep) rather than being - given a pre locked page; - - it must be able to cope with short writes (where the - length passed to write_begin is greater than the number - of bytes copied into the page). - + write_begin: Called by the generic buffered write code to ask the filesystem to prepare to write len bytes at the given offset in the file. The address_space should check that the write will be able to complete, @@ -640,6 +608,9 @@ struct address_space_operations { The filesystem must return the locked pagecache page for the specified offset, in *pagep, for the caller to write into. + It must be able to cope with short writes (where the length passed to + write_begin is greater than the number of bytes copied into the page). + flags is a field for AOP_FLAG_xxx flags, described in include/linux/fs.h. diff --git a/Documentation/filesystems/xip.txt b/Documentation/filesystems/xip.txt index 3cc4010521a0..0466ee569278 100644 --- a/Documentation/filesystems/xip.txt +++ b/Documentation/filesystems/xip.txt @@ -39,10 +39,11 @@ The block device operation is optional, these block devices support it as of today: - dcssblk: s390 dcss block device driver -An address space operation named get_xip_page is used to retrieve reference -to a struct page. To address the target page, a reference to an address_space, -and a sector number is provided. A 3rd argument indicates whether the -function should allocate blocks if needed. +An address space operation named get_xip_mem is used to retrieve references +to a page frame number and a kernel address. To obtain these values a reference +to an address_space is provided. This function assigns values to the kmem and +pfn parameters. The third argument indicates whether the function should allocate +blocks if needed. This address space operation is mutually exclusive with readpage&writepage that do page cache read/write operations. diff --git a/Documentation/floppy.txt b/Documentation/floppy.txt deleted file mode 100644 index 6ccab88705cb..000000000000 --- a/Documentation/floppy.txt +++ /dev/null @@ -1,245 +0,0 @@ -This file describes the floppy driver. - -FAQ list: -========= - - A FAQ list may be found in the fdutils package (see below), and also -at . - - -LILO configuration options (Thinkpad users, read this) -====================================================== - - The floppy driver is configured using the 'floppy=' option in -lilo. This option can be typed at the boot prompt, or entered in the -lilo configuration file. - - Example: If your kernel is called linux-2.6.9, type the following line -at the lilo boot prompt (if you have a thinkpad): - - linux-2.6.9 floppy=thinkpad - -You may also enter the following line in /etc/lilo.conf, in the description -of linux-2.6.9: - - append = "floppy=thinkpad" - - Several floppy related options may be given, example: - - linux-2.6.9 floppy=daring floppy=two_fdc - append = "floppy=daring floppy=two_fdc" - - If you give options both in the lilo config file and on the boot -prompt, the option strings of both places are concatenated, the boot -prompt options coming last. That's why there are also options to -restore the default behavior. - - -Module configuration options -============================ - - If you use the floppy driver as a module, use the following syntax: -modprobe floppy - -Example: - modprobe floppy omnibook messages - - If you need certain options enabled every time you load the floppy driver, -you can put: - - options floppy omnibook messages - -in /etc/modprobe.conf. - - - The floppy driver related options are: - - floppy=asus_pci - Sets the bit mask to allow only units 0 and 1. (default) - - floppy=daring - Tells the floppy driver that you have a well behaved floppy controller. - This allows more efficient and smoother operation, but may fail on - certain controllers. This may speed up certain operations. - - floppy=0,daring - Tells the floppy driver that your floppy controller should be used - with caution. - - floppy=one_fdc - Tells the floppy driver that you have only one floppy controller. - (default) - - floppy=two_fdc - floppy=
,two_fdc - Tells the floppy driver that you have two floppy controllers. - The second floppy controller is assumed to be at
. - This option is not needed if the second controller is at address - 0x370, and if you use the 'cmos' option. - - floppy=thinkpad - Tells the floppy driver that you have a Thinkpad. Thinkpads use an - inverted convention for the disk change line. - - floppy=0,thinkpad - Tells the floppy driver that you don't have a Thinkpad. - - floppy=omnibook - floppy=nodma - Tells the floppy driver not to use Dma for data transfers. - This is needed on HP Omnibooks, which don't have a workable - DMA channel for the floppy driver. This option is also useful - if you frequently get "Unable to allocate DMA memory" messages. - Indeed, dma memory needs to be continuous in physical memory, - and is thus harder to find, whereas non-dma buffers may be - allocated in virtual memory. However, I advise against this if - you have an FDC without a FIFO (8272A or 82072). 82072A and - later are OK. You also need at least a 486 to use nodma. - If you use nodma mode, I suggest you also set the FIFO - threshold to 10 or lower, in order to limit the number of data - transfer interrupts. - - If you have a FIFO-able FDC, the floppy driver automatically - falls back on non DMA mode if no DMA-able memory can be found. - If you want to avoid this, explicitly ask for 'yesdma'. - - floppy=yesdma - Tells the floppy driver that a workable DMA channel is available. - (default) - - floppy=nofifo - Disables the FIFO entirely. This is needed if you get "Bus - master arbitration error" messages from your Ethernet card (or - from other devices) while accessing the floppy. - - floppy=usefifo - Enables the FIFO. (default) - - floppy=,fifo_depth - Sets the FIFO threshold. This is mostly relevant in DMA - mode. If this is higher, the floppy driver tolerates more - interrupt latency, but it triggers more interrupts (i.e. it - imposes more load on the rest of the system). If this is - lower, the interrupt latency should be lower too (faster - processor). The benefit of a lower threshold is less - interrupts. - - To tune the fifo threshold, switch on over/underrun messages - using 'floppycontrol --messages'. Then access a floppy - disk. If you get a huge amount of "Over/Underrun - retrying" - messages, then the fifo threshold is too low. Try with a - higher value, until you only get an occasional Over/Underrun. - It is a good idea to compile the floppy driver as a module - when doing this tuning. Indeed, it allows to try different - fifo values without rebooting the machine for each test. Note - that you need to do 'floppycontrol --messages' every time you - re-insert the module. - - Usually, tuning the fifo threshold should not be needed, as - the default (0xa) is reasonable. - - floppy=,,cmos - Sets the CMOS type of to . This is mandatory if - you have more than two floppy drives (only two can be - described in the physical CMOS), or if your BIOS uses - non-standard CMOS types. The CMOS types are: - - 0 - Use the value of the physical CMOS - 1 - 5 1/4 DD - 2 - 5 1/4 HD - 3 - 3 1/2 DD - 4 - 3 1/2 HD - 5 - 3 1/2 ED - 6 - 3 1/2 ED - 16 - unknown or not installed - - (Note: there are two valid types for ED drives. This is because 5 was - initially chosen to represent floppy *tapes*, and 6 for ED drives. - AMI ignored this, and used 5 for ED drives. That's why the floppy - driver handles both.) - - floppy=unexpected_interrupts - Print a warning message when an unexpected interrupt is received. - (default) - - floppy=no_unexpected_interrupts - floppy=L40SX - Don't print a message when an unexpected interrupt is received. This - is needed on IBM L40SX laptops in certain video modes. (There seems - to be an interaction between video and floppy. The unexpected - interrupts affect only performance, and can be safely ignored.) - - floppy=broken_dcl - Don't use the disk change line, but assume that the disk was - changed whenever the device node is reopened. Needed on some - boxes where the disk change line is broken or unsupported. - This should be regarded as a stopgap measure, indeed it makes - floppy operation less efficient due to unneeded cache - flushings, and slightly more unreliable. Please verify your - cable, connection and jumper settings if you have any DCL - problems. However, some older drives, and also some laptops - are known not to have a DCL. - - floppy=debug - Print debugging messages. - - floppy=messages - Print informational messages for some operations (disk change - notifications, warnings about over and underruns, and about - autodetection). - - floppy=silent_dcl_clear - Uses a less noisy way to clear the disk change line (which - doesn't involve seeks). Implied by 'daring' option. - - floppy=,irq - Sets the floppy IRQ to instead of 6. - - floppy=,dma - Sets the floppy DMA channel to instead of 2. - - floppy=slow - Use PS/2 stepping rate: - " PS/2 floppies have much slower step rates than regular floppies. - It's been recommended that take about 1/4 of the default speed - in some more extreme cases." - - -Supporting utilities and additional documentation: -================================================== - - Additional parameters of the floppy driver can be configured at -runtime. Utilities which do this can be found in the fdutils package. -This package also contains a new version of mtools which allows to -access high capacity disks (up to 1992K on a high density 3 1/2 disk!). -It also contains additional documentation about the floppy driver. - -The latest version can be found at fdutils homepage: - http://fdutils.linux.lu - -The fdutils releases can be found at: - http://fdutils.linux.lu/download.html - http://www.tux.org/pub/knaff/fdutils/ - ftp://metalab.unc.edu/pub/Linux/utils/disk-management/ - -Reporting problems about the floppy driver -========================================== - - If you have a question or a bug report about the floppy driver, mail -me at Alain.Knaff@poboxes.com . If you post to Usenet, preferably use -comp.os.linux.hardware. As the volume in these groups is rather high, -be sure to include the word "floppy" (or "FLOPPY") in the subject -line. If the reported problem happens when mounting floppy disks, be -sure to mention also the type of the filesystem in the subject line. - - Be sure to read the FAQ before mailing/posting any bug reports! - - Alain - -Changelog -========= - -10-30-2004 : Cleanup, updating, add reference to module configuration. - James Nelson - -6-3-2000 : Original Document diff --git a/Documentation/ftrace.txt b/Documentation/ftrace.txt index d330fe3103da..9cc4d685dde5 100644 --- a/Documentation/ftrace.txt +++ b/Documentation/ftrace.txt @@ -8,7 +8,7 @@ Copyright 2008 Red Hat Inc. Reviewers: Elias Oltmanns, Randy Dunlap, Andrew Morton, John Kacur, and David Teigland. -Written for: 2.6.27-rc1 +Written for: 2.6.28-rc2 Introduction ------------ @@ -50,26 +50,26 @@ of ftrace. Here is a list of some of the key files: Note: all time values are in microseconds. - current_tracer : This is used to set or display the current tracer + current_tracer: This is used to set or display the current tracer that is configured. - available_tracers : This holds the different types of tracers that + available_tracers: This holds the different types of tracers that have been compiled into the kernel. The tracers listed here can be configured by echoing their name into current_tracer. - tracing_enabled : This sets or displays whether the current_tracer + tracing_enabled: This sets or displays whether the current_tracer is activated and tracing or not. Echo 0 into this file to disable the tracer or 1 to enable it. - trace : This file holds the output of the trace in a human readable + trace: This file holds the output of the trace in a human readable format (described below). - latency_trace : This file shows the same trace but the information + latency_trace: This file shows the same trace but the information is organized more to display possible latencies in the system (described below). - trace_pipe : The output is the same as the "trace" file but this + trace_pipe: The output is the same as the "trace" file but this file is meant to be streamed with live tracing. Reads from this file will block until new data is retrieved. Unlike the "trace" and "latency_trace" @@ -82,11 +82,11 @@ of ftrace. Here is a list of some of the key files: tracer is not adding more data, they will display the same information every time they are read. - iter_ctrl : This file lets the user control the amount of data + iter_ctrl: This file lets the user control the amount of data that is displayed in one of the above output files. - trace_max_latency : Some of the tracers record the max latency. + trace_max_latency: Some of the tracers record the max latency. For example, the time interrupts are disabled. This time is saved in this file. The max trace will also be stored, and displayed by either @@ -94,29 +94,26 @@ of ftrace. Here is a list of some of the key files: only be recorded if the latency is greater than the value in this file. (in microseconds) - trace_entries : This sets or displays the number of trace - entries each CPU buffer can hold. The tracer buffers - are the same size for each CPU. The displayed number - is the size of the CPU buffer and not total size. The + trace_entries: This sets or displays the number of bytes each CPU + buffer can hold. The tracer buffers are the same size + for each CPU. The displayed number is the size of the + CPU buffer and not total size of all buffers. The trace buffers are allocated in pages (blocks of memory that the kernel uses for allocation, usually 4 KB in size). - Since each entry is smaller than a page, if the last - allocated page has room for more entries than were - requested, the rest of the page is used to allocate - entries. + If the last page allocated has room for more bytes + than requested, the rest of the page will be used, + making the actual allocation bigger than requested. + (Note, the size may not be a multiple of the page size due + to buffer managment overhead.) This can only be updated when the current_tracer - is set to "none". + is set to "nop". - NOTE: It is planned on changing the allocated buffers - from being the number of possible CPUS to - the number of online CPUS. - - tracing_cpumask : This is a mask that lets the user only trace + tracing_cpumask: This is a mask that lets the user only trace on specified CPUS. The format is a hex string representing the CPUS. - set_ftrace_filter : When dynamic ftrace is configured in (see the + set_ftrace_filter: When dynamic ftrace is configured in (see the section below "dynamic ftrace"), the code is dynamically modified (code text rewrite) to disable calling of the function profiler (mcount). This lets tracing be configured @@ -130,14 +127,11 @@ of ftrace. Here is a list of some of the key files: be traced. If a function exists in both set_ftrace_filter and set_ftrace_notrace, the function will _not_ be traced. - available_filter_functions : When a function is encountered the first - time by the dynamic tracer, it is recorded and - later the call is converted into a nop. This file - lists the functions that have been recorded - by the dynamic tracer and these functions can - be used to set the ftrace filter by the above - "set_ftrace_filter" file. (See the section "dynamic ftrace" - below for more details). + available_filter_functions: This lists the functions that ftrace + has processed and can trace. These are the function + names that you can pass to "set_ftrace_filter" or + "set_ftrace_notrace". (See the section "dynamic ftrace" + below for more details.) The Tracers @@ -145,7 +139,7 @@ The Tracers Here is the list of current tracers that may be configured. - ftrace - function tracer that uses mcount to trace all functions. + function - function tracer that uses mcount to trace all functions. sched_switch - traces the context switches between tasks. @@ -166,8 +160,8 @@ Here is the list of current tracers that may be configured. the highest priority task to get scheduled after it has been woken up. - none - This is not a tracer. To remove all tracers from tracing - simply echo "none" into current_tracer. + nop - This is not a tracer. To remove all tracers from tracing + simply echo "nop" into current_tracer. Examples of using the tracer @@ -182,7 +176,7 @@ Output format: Here is an example of the output format of the file "trace" -------- -# tracer: ftrace +# tracer: function # # TASK-PID CPU# TIMESTAMP FUNCTION # | | | | | @@ -192,7 +186,7 @@ Here is an example of the output format of the file "trace" -------- A header is printed with the tracer name that is represented by the trace. -In this case the tracer is "ftrace". Then a header showing the format. Task +In this case the tracer is "function". Then a header showing the format. Task name "bash", the task PID "4251", the CPU that it was running on "01", the timestamp in . format, the function name that was traced "path_put" and the parent function that called this function @@ -291,6 +285,9 @@ explains which is which. CPU#: The CPU which the process was running on. irqs-off: 'd' interrupts are disabled. '.' otherwise. + Note: If the architecture does not support a way to + read the irq flags variable, an 'X' will always + be printed here. need-resched: 'N' task need_resched is set, '.' otherwise. @@ -1000,22 +997,20 @@ is the stack for the hard interrupt. This hides the fact that NEED_RESCHED has been set. We do not see the 'N' until we switch back to the task's assigned stack. -ftrace ------- +function +-------- -ftrace is not only the name of the tracing infrastructure, but it -is also a name of one of the tracers. The tracer is the function -tracer. Enabling the function tracer can be done from the -debug file system. Make sure the ftrace_enabled is set otherwise -this tracer is a nop. +This tracer is the function tracer. Enabling the function tracer +can be done from the debug file system. Make sure the ftrace_enabled is +set; otherwise this tracer is a nop. # sysctl kernel.ftrace_enabled=1 - # echo ftrace > /debug/tracing/current_tracer + # echo function > /debug/tracing/current_tracer # echo 1 > /debug/tracing/tracing_enabled # usleep 1 # echo 0 > /debug/tracing/tracing_enabled # cat /debug/tracing/trace -# tracer: ftrace +# tracer: function # # TASK-PID CPU# TIMESTAMP FUNCTION # | | | | | @@ -1037,10 +1032,10 @@ this tracer is a nop. [...] -Note: ftrace uses ring buffers to store the above entries. The newest data -may overwrite the oldest data. Sometimes using echo to stop the trace -is not sufficient because the tracing could have overwritten the data -that you wanted to record. For this reason, it is sometimes better to +Note: function tracer uses ring buffers to store the above entries. +The newest data may overwrite the oldest data. Sometimes using echo to +stop the trace is not sufficient because the tracing could have overwritten +the data that you wanted to record. For this reason, it is sometimes better to disable tracing directly from a program. This allows you to stop the tracing at the point that you hit the part that you are interested in. To disable the tracing directly from a C program, something like following @@ -1074,18 +1069,31 @@ every kernel function, produced by the -pg switch in gcc), starts of pointing to a simple return. (Enabling FTRACE will include the -pg switch in the compiling of the kernel.) -When dynamic ftrace is initialized, it calls kstop_machine to make -the machine act like a uniprocessor so that it can freely modify code -without worrying about other processors executing that same code. At -initialization, the mcount calls are changed to call a "record_ip" -function. After this, the first time a kernel function is called, -it has the calling address saved in a hash table. - -Later on the ftraced kernel thread is awoken and will again call -kstop_machine if new functions have been recorded. The ftraced thread -will change all calls to mcount to "nop". Just calling mcount -and having mcount return has shown a 10% overhead. By converting -it to a nop, there is no measurable overhead to the system. +At compile time every C file object is run through the +recordmcount.pl script (located in the scripts directory). This +script will process the C object using objdump to find all the +locations in the .text section that call mcount. (Note, only +the .text section is processed, since processing other sections +like .init.text may cause races due to those sections being freed). + +A new section called "__mcount_loc" is created that holds references +to all the mcount call sites in the .text section. This section is +compiled back into the original object. The final linker will add +all these references into a single table. + +On boot up, before SMP is initialized, the dynamic ftrace code +scans this table and updates all the locations into nops. It also +records the locations, which are added to the available_filter_functions +list. Modules are processed as they are loaded and before they are +executed. When a module is unloaded, it also removes its functions from +the ftrace function list. This is automatic in the module unload +code, and the module author does not need to worry about it. + +When tracing is enabled, kstop_machine is called to prevent races +with the CPUS executing code being modified (which can cause the +CPU to do undesireable things), and the nops are patched back +to calls. But this time, they do not call mcount (which is just +a function stub). They now call into the ftrace infrastructure. One special side-effect to the recording of the functions being traced is that we can now selectively choose which functions we @@ -1248,36 +1256,6 @@ Produces: We can see that there's no more lock or preempt tracing. -ftraced -------- - -As mentioned above, when dynamic ftrace is configured in, a kernel -thread wakes up once a second and checks to see if there are mcount -calls that need to be converted into nops. If there are not any, then -it simply goes back to sleep. But if there are some, it will call -kstop_machine to convert the calls to nops. - -There may be a case in which you do not want this added latency. -Perhaps you are doing some audio recording and this activity might -cause skips in the playback. There is an interface to disable -and enable the "ftraced" kernel thread. - - # echo 0 > /debug/tracing/ftraced_enabled - -This will disable the calling of kstop_machine to update the -mcount calls to nops. Remember that there is a large overhead -to calling mcount. Without this kernel thread, that overhead will -exist. - -If there are recorded calls to mcount, any write to the ftraced_enabled -file will cause the kstop_machine to run. This means that a -user can manually perform the updates when they want to by simply -echoing a '0' into the ftraced_enabled file. - -The updates are also done at the beginning of enabling a tracer -that uses ftrace function recording. - - trace_pipe ---------- @@ -1286,14 +1264,14 @@ on the tracing is different. Every read from trace_pipe is consumed. This means that subsequent reads will be different. The trace is live. - # echo ftrace > /debug/tracing/current_tracer + # echo function > /debug/tracing/current_tracer # cat /debug/tracing/trace_pipe > /tmp/trace.out & [1] 4153 # echo 1 > /debug/tracing/tracing_enabled # usleep 1 # echo 0 > /debug/tracing/tracing_enabled # cat /debug/tracing/trace -# tracer: ftrace +# tracer: function # # TASK-PID CPU# TIMESTAMP FUNCTION # | | | | | @@ -1314,7 +1292,7 @@ is live. Note, reading the trace_pipe file will block until more input is added. By changing the tracer, trace_pipe will issue an EOF. We needed -to set the ftrace tracer _before_ cating the trace_pipe file. +to set the function tracer _before_ we "cat" the trace_pipe file. trace entries @@ -1331,10 +1309,10 @@ number of entries. 65620 Note, to modify this, you must have tracing completely disabled. To do that, -echo "none" into the current_tracer. If the current_tracer is not set -to "none", an EINVAL error will be returned. +echo "nop" into the current_tracer. If the current_tracer is not set +to "nop", an EINVAL error will be returned. - # echo none > /debug/tracing/current_tracer + # echo nop > /debug/tracing/current_tracer # echo 100000 > /debug/tracing/trace_entries # cat /debug/tracing/trace_entries 100045 diff --git a/Documentation/hayes-esp.txt b/Documentation/hayes-esp.txt deleted file mode 100644 index 09b5d5856758..000000000000 --- a/Documentation/hayes-esp.txt +++ /dev/null @@ -1,154 +0,0 @@ -HAYES ESP DRIVER VERSION 2.1 - -A big thanks to the people at Hayes, especially Alan Adamson. Their support -has enabled me to provide enhancements to the driver. - -Please report your experiences with this driver to me (arobinso@nyx.net). I -am looking for both positive and negative feedback. - -*** IMPORTANT CHANGES FOR 2.1 *** -Support for PIO mode. Five situations will cause PIO mode to be used: -1) A multiport card is detected. PIO mode will always be used. (8 port cards -do not support DMA). -2) The DMA channel is set to an invalid value (anything other than 1 or 3). -3) The DMA buffer/channel could not be allocated. The port will revert to PIO -mode until it is reopened. -4) Less than a specified number of bytes need to be transferred to/from the -FIFOs. PIO mode will be used for that transfer only. -5) A port needs to do a DMA transfer and another port is already using the -DMA channel. PIO mode will be used for that transfer only. - -Since the Hayes ESP seems to conflict with other cards (notably sound cards) -when using DMA, DMA is turned off by default. To use DMA, it must be turned -on explicitly, either with the "dma=" option described below or with -setserial. A multiport card can be forced into DMA mode by using setserial; -however, most multiport cards don't support DMA. - -The latest version of setserial allows the enhanced configuration of the ESP -card to be viewed and modified. -*** - -This package contains the files needed to compile a module to support the Hayes -ESP card. The drivers are basically a modified version of the serial drivers. - -Features: - -- Uses the enhanced mode of the ESP card, allowing a wider range of - interrupts and features than compatibility mode -- Uses DMA and 16 bit PIO mode to transfer data to and from the ESP's FIFOs, - reducing CPU load -- Supports primary and secondary ports - - -If the driver is compiled as a module, the IRQs to use can be specified by -using the irq= option. The format is: - -irq=[0x100],[0x140],[0x180],[0x200],[0x240],[0x280],[0x300],[0x380] - -The address in brackets is the base address of the card. The IRQ of -nonexistent cards can be set to 0. If an IRQ of a card that does exist is set -to 0, the driver will attempt to guess at the correct IRQ. For example, to set -the IRQ of the card at address 0x300 to 12, the insmod command would be: - -insmod esp irq=0,0,0,0,0,0,12,0 - -The custom divisor can be set by using the divisor= option. The format is the -same as for the irq= option. Each divisor value is a series of hex digits, -with each digit representing the divisor to use for a corresponding port. The -divisor value is constructed RIGHT TO LEFT. Specifying a nonzero divisor value -will automatically set the spd_cust flag. To calculate the divisor to use for -a certain baud rate, divide the port's base baud (generally 921600) by the -desired rate. For example, to set the divisor of the primary port at 0x300 to -4 and the divisor of the secondary port at 0x308 to 8, the insmod command would -be: - -insmod esp divisor=0,0,0,0,0,0,0x84,0 - -The dma= option can be used to set the DMA channel. The channel can be either -1 or 3. Specifying any other value will force the driver to use PIO mode. -For example, to set the DMA channel to 3, the insmod command would be: - -insmod esp dma=3 - -The rx_trigger= and tx_trigger= options can be used to set the FIFO trigger -levels. They specify when the ESP card should send an interrupt. Larger -values will decrease the number of interrupts; however, a value too high may -result in data loss. Valid values are 1 through 1023, with 768 being the -default. For example, to set the receive trigger level to 512 bytes and the -transmit trigger level to 700 bytes, the insmod command would be: - -insmod esp rx_trigger=512 tx_trigger=700 - -The flow_off= and flow_on= options can be used to set the hardware flow off/ -flow on levels. The flow on level must be lower than the flow off level, and -the flow off level should be higher than rx_trigger. Valid values are 1 -through 1023, with 1016 being the default flow off level and 944 being the -default flow on level. For example, to set the flow off level to 1000 bytes -and the flow on level to 935 bytes, the insmod command would be: - -insmod esp flow_off=1000 flow_on=935 - -The rx_timeout= option can be used to set the receive timeout value. This -value indicates how long after receiving the last character that the ESP card -should wait before signalling an interrupt. Valid values are 0 though 255, -with 128 being the default. A value too high will increase latency, and a -value too low will cause unnecessary interrupts. For example, to set the -receive timeout to 255, the insmod command would be: - -insmod esp rx_timeout=255 - -The pio_threshold= option sets the threshold (in number of characters) for -using PIO mode instead of DMA mode. For example, if this value is 32, -transfers of 32 bytes or less will always use PIO mode. - -insmod esp pio_threshold=32 - -Multiple options can be listed on the insmod command line by separating each -option with a space. For example: - -insmod esp dma=3 trigger=512 - -The esp module can be automatically loaded when needed. To cause this to -happen, add the following lines to /etc/modprobe.conf (replacing the last line -with options for your configuration): - -alias char-major-57 esp -alias char-major-58 esp -options esp irq=0,0,0,0,0,0,3,0 divisor=0,0,0,0,0,0,0x4,0 - -You may also need to run 'depmod -a'. - -Devices must be created manually. To create the devices, note the output from -the module after it is inserted. The output will appear in the location where -kernel messages usually appear (usually /var/adm/messages). Create two devices -for each 'tty' mentioned, one with major of 57 and the other with major of 58. -The minor number should be the same as the tty number reported. The commands -would be (replace ? with the tty number): - -mknod /dev/ttyP? c 57 ? -mknod /dev/cup? c 58 ? - -For example, if the following line appears: - -Oct 24 18:17:23 techno kernel: ttyP8 at 0x0140 (irq = 3) is an ESP primary port - -...two devices should be created: - -mknod /dev/ttyP8 c 57 8 -mknod /dev/cup8 c 58 8 - -You may need to set the permissions on the devices: - -chmod 666 /dev/ttyP* -chmod 666 /dev/cup* - -The ESP module and the serial module should not conflict (they can be used at -the same time). After the ESP module has been loaded the ports on the ESP card -will no longer be accessible by the serial driver. - -If I/O errors are experienced when accessing the port, check for IRQ and DMA -conflicts ('cat /proc/interrupts' and 'cat /proc/dma' for a list of IRQs and -DMAs currently in use). - -Enjoy! -Andrew J. Robinson diff --git a/Documentation/hwmon/adt7462 b/Documentation/hwmon/adt7462 new file mode 100644 index 000000000000..ec660b328275 --- /dev/null +++ b/Documentation/hwmon/adt7462 @@ -0,0 +1,67 @@ +Kernel driver adt7462 +====================== + +Supported chips: + * Analog Devices ADT7462 + Prefix: 'adt7462' + Addresses scanned: I2C 0x58, 0x5C + Datasheet: Publicly available at the Analog Devices website + +Author: Darrick J. Wong + +Description +----------- + +This driver implements support for the Analog Devices ADT7462 chip family. + +This chip is a bit of a beast. It has 8 counters for measuring fan speed. It +can also measure 13 voltages or 4 temperatures, or various combinations of the +two. See the chip documentation for more details about the exact set of +configurations. This driver does not allow one to configure the chip; that is +left to the system designer. + +A sophisticated control system for the PWM outputs is designed into the ADT7462 +that allows fan speed to be adjusted automatically based on any of the three +temperature sensors. Each PWM output is individually adjustable and +programmable. Once configured, the ADT7462 will adjust the PWM outputs in +response to the measured temperatures without further host intervention. This +feature can also be disabled for manual control of the PWM's. + +Each of the measured inputs (voltage, temperature, fan speed) has +corresponding high/low limit values. The ADT7462 will signal an ALARM if +any measured value exceeds either limit. + +The ADT7462 samples all inputs continuously. The driver will not read +the registers more often than once every other second. Further, +configuration data is only read once per minute. + +Special Features +---------------- + +The ADT7462 have a 10-bit ADC and can therefore measure temperatures +with 0.25 degC resolution. + +The Analog Devices datasheet is very detailed and describes a procedure for +determining an optimal configuration for the automatic PWM control. + +The driver will report sensor labels when it is able to determine that +information from the configuration registers. + +Configuration Notes +------------------- + +Besides standard interfaces driver adds the following: + +* PWM Control + +* pwm#_auto_point1_pwm and temp#_auto_point1_temp and +* pwm#_auto_point2_pwm and temp#_auto_point2_temp - + +point1: Set the pwm speed at a lower temperature bound. +point2: Set the pwm speed at a higher temperature bound. + +The ADT7462 will scale the pwm between the lower and higher pwm speed when +the temperature is between the two temperature boundaries. PWM values range +from 0 (off) to 255 (full speed). Fan speed will be set to maximum when the +temperature sensor associated with the PWM control exceeds temp#_max. + diff --git a/Documentation/hwmon/lis3lv02d b/Documentation/hwmon/lis3lv02d new file mode 100644 index 000000000000..65dfb0c0fd67 --- /dev/null +++ b/Documentation/hwmon/lis3lv02d @@ -0,0 +1,49 @@ +Kernel driver lis3lv02d +================== + +Supported chips: + + * STMicroelectronics LIS3LV02DL and LIS3LV02DQ + +Author: + Yan Burman + Eric Piel + + +Description +----------- + +This driver provides support for the accelerometer found in various HP laptops +sporting the feature officially called "HP Mobile Data Protection System 3D" or +"HP 3D DriveGuard". It detect automatically laptops with this sensor. Known models +(for now the HP 2133, nc6420, nc2510, nc8510, nc84x0, nw9440 and nx9420) will +have their axis automatically oriented on standard way (eg: you can directly +play neverball). The accelerometer data is readable via +/sys/devices/platform/lis3lv02d. + +Sysfs attributes under /sys/devices/platform/lis3lv02d/: +position - 3D position that the accelerometer reports. Format: "(x,y,z)" +calibrate - read: values (x, y, z) that are used as the base for input class device operation. + write: forces the base to be recalibrated with the current position. +rate - reports the sampling rate of the accelerometer device in HZ + +This driver also provides an absolute input class device, allowing +the laptop to act as a pinball machine-esque joystick. + +Axes orientation +---------------- + +For better compatibility between the various laptops. The values reported by +the accelerometer are converted into a "standard" organisation of the axes +(aka "can play neverball out of the box"): + * When the laptop is horizontal the position reported is about 0 for X and Y +and a positive value for Z + * If the left side is elevated, X increases (becomes positive) + * If the front side (where the touchpad is) is elevated, Y decreases (becomes negative) + * If the laptop is put upside-down, Z becomes negative + +If your laptop model is not recognized (cf "dmesg"), you can send an email to the +authors to add it to the database. When reporting a new laptop, please include +the output of "dmidecode" plus the value of /sys/devices/platform/lis3lv02d/position +in these four cases. + diff --git a/Documentation/i2c/busses/i2c-sis96x b/Documentation/i2c/busses/i2c-sis96x index 266481fd26e2..70e6a0cc1e15 100644 --- a/Documentation/i2c/busses/i2c-sis96x +++ b/Documentation/i2c/busses/i2c-sis96x @@ -42,7 +42,7 @@ I suspect that this driver could be made to work for the following SiS chipsets as well: 635, and 635T. If anyone owns a board with those chips AND is willing to risk crashing & burning an otherwise well-behaved kernel in the name of progress... please contact me at or -via the project's mailing list: . Please send bug +via the linux-i2c mailing list: . Please send bug reports and/or success stories as well. diff --git a/Documentation/ia64/.gitignore b/Documentation/ia64/.gitignore new file mode 100644 index 000000000000..ab806edc8732 --- /dev/null +++ b/Documentation/ia64/.gitignore @@ -0,0 +1 @@ +aliasing-test diff --git a/Documentation/ics932s401 b/Documentation/ics932s401 new file mode 100644 index 000000000000..07a739f406d8 --- /dev/null +++ b/Documentation/ics932s401 @@ -0,0 +1,31 @@ +Kernel driver ics932s401 +====================== + +Supported chips: + * IDT ICS932S401 + Prefix: 'ics932s401' + Addresses scanned: I2C 0x69 + Datasheet: Publically available at the IDT website + +Author: Darrick J. Wong + +Description +----------- + +This driver implements support for the IDT ICS932S401 chip family. + +This chip has 4 clock outputs--a base clock for the CPU (which is likely +multiplied to get the real CPU clock), a system clock, a PCI clock, a USB +clock, and a reference clock. The driver reports selected and actual +frequency. If spread spectrum mode is enabled, the driver also reports by what +percent the clock signal is being spread, which should be between 0 and -0.5%. +All frequencies are reported in KHz. + +The ICS932S401 monitors all inputs continuously. The driver will not read +the registers more often than once every other second. + +Special Features +---------------- + +The clocks could be reprogrammed to increase system speed. I will not help you +do this, as you risk damaging your system! diff --git a/Documentation/input/elantech.txt b/Documentation/input/elantech.txt new file mode 100644 index 000000000000..a10c3b6ba7c4 --- /dev/null +++ b/Documentation/input/elantech.txt @@ -0,0 +1,405 @@ +Elantech Touchpad Driver +======================== + + Copyright (C) 2007-2008 Arjan Opmeer + + Extra information for hardware version 1 found and + provided by Steve Havelka + + Version 2 (EeePC) hardware support based on patches + received from Woody at Xandros and forwarded to me + by user StewieGriffin at the eeeuser.com forum + + +Contents +~~~~~~~~ + + 1. Introduction + 2. Extra knobs + 3. Hardware version 1 + 3.1 Registers + 3.2 Native relative mode 4 byte packet format + 3.3 Native absolute mode 4 byte packet format + 4. Hardware version 2 + 4.1 Registers + 4.2 Native absolute mode 6 byte packet format + 4.2.1 One finger touch + 4.2.2 Two finger touch + + + +1. Introduction + ~~~~~~~~~~~~ + +Currently the Linux Elantech touchpad driver is aware of two different +hardware versions unimaginatively called version 1 and version 2. Version 1 +is found in "older" laptops and uses 4 bytes per packet. Version 2 seems to +be introduced with the EeePC and uses 6 bytes per packet. + +The driver tries to support both hardware versions and should be compatible +with the Xorg Synaptics touchpad driver and its graphical configuration +utilities. + +Additionally the operation of the touchpad can be altered by adjusting the +contents of some of its internal registers. These registers are represented +by the driver as sysfs entries under /sys/bus/serio/drivers/psmouse/serio? +that can be read from and written to. + +Currently only the registers for hardware version 1 are somewhat understood. +Hardware version 2 seems to use some of the same registers but it is not +known whether the bits in the registers represent the same thing or might +have changed their meaning. + +On top of that, some register settings have effect only when the touchpad is +in relative mode and not in absolute mode. As the Linux Elantech touchpad +driver always puts the hardware into absolute mode not all information +mentioned below can be used immediately. But because there is no freely +available Elantech documentation the information is provided here anyway for +completeness sake. + + +///////////////////////////////////////////////////////////////////////////// + + +2. Extra knobs + ~~~~~~~~~~~ + +Currently the Linux Elantech touchpad driver provides two extra knobs under +/sys/bus/serio/drivers/psmouse/serio? for the user. + +* debug + + Turn different levels of debugging ON or OFF. + + By echoing "0" to this file all debugging will be turned OFF. + + Currently a value of "1" will turn on some basic debugging and a value of + "2" will turn on packet debugging. For hardware version 1 the default is + OFF. For version 2 the default is "1". + + Turning packet debugging on will make the driver dump every packet + received to the syslog before processing it. Be warned that this can + generate quite a lot of data! + +* paritycheck + + Turns parity checking ON or OFF. + + By echoing "0" to this file parity checking will be turned OFF. Any + non-zero value will turn it ON. For hardware version 1 the default is ON. + For version 2 the default it is OFF. + + Hardware version 1 provides basic data integrity verification by + calculating a parity bit for the last 3 bytes of each packet. The driver + can check these bits and reject any packet that appears corrupted. Using + this knob you can bypass that check. + + It is not known yet whether hardware version 2 provides the same parity + bits. Hence checking is disabled by default. Currently even turning it on + will do nothing. + + +///////////////////////////////////////////////////////////////////////////// + + +3. Hardware version 1 + ================== + +3.1 Registers + ~~~~~~~~~ + +By echoing a hexadecimal value to a register it contents can be altered. + +For example: + + echo -n 0x16 > reg_10 + +* reg_10 + + bit 7 6 5 4 3 2 1 0 + B C T D L A S E + + E: 1 = enable smart edges unconditionally + S: 1 = enable smart edges only when dragging + A: 1 = absolute mode (needs 4 byte packets, see reg_11) + L: 1 = enable drag lock (see reg_22) + D: 1 = disable dynamic resolution + T: 1 = disable tapping + C: 1 = enable corner tap + B: 1 = swap left and right button + +* reg_11 + + bit 7 6 5 4 3 2 1 0 + 1 0 0 H V 1 F P + + P: 1 = enable parity checking for relative mode + F: 1 = enable native 4 byte packet mode + V: 1 = enable vertical scroll area + H: 1 = enable horizontal scroll area + +* reg_20 + + single finger width? + +* reg_21 + + scroll area width (small: 0x40 ... wide: 0xff) + +* reg_22 + + drag lock time out (short: 0x14 ... long: 0xfe; + 0xff = tap again to release) + +* reg_23 + + tap make timeout? + +* reg_24 + + tap release timeout? + +* reg_25 + + smart edge cursor speed (0x02 = slow, 0x03 = medium, 0x04 = fast) + +* reg_26 + + smart edge activation area width? + + +3.2 Native relative mode 4 byte packet format + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +byte 0: + bit 7 6 5 4 3 2 1 0 + c c p2 p1 1 M R L + + L, R, M = 1 when Left, Right, Middle mouse button pressed + some models have M as byte 3 odd parity bit + when parity checking is enabled (reg_11, P = 1): + p1..p2 = byte 1 and 2 odd parity bit + c = 1 when corner tap detected + +byte 1: + bit 7 6 5 4 3 2 1 0 + dx7 dx6 dx5 dx4 dx3 dx2 dx1 dx0 + + dx7..dx0 = x movement; positive = right, negative = left + byte 1 = 0xf0 when corner tap detected + +byte 2: + bit 7 6 5 4 3 2 1 0 + dy7 dy6 dy5 dy4 dy3 dy2 dy1 dy0 + + dy7..dy0 = y movement; positive = up, negative = down + +byte 3: + parity checking enabled (reg_11, P = 1): + + bit 7 6 5 4 3 2 1 0 + w h n1 n0 ds3 ds2 ds1 ds0 + + normally: + ds3..ds0 = scroll wheel amount and direction + positive = down or left + negative = up or right + when corner tap detected: + ds0 = 1 when top right corner tapped + ds1 = 1 when bottom right corner tapped + ds2 = 1 when bottom left corner tapped + ds3 = 1 when top left corner tapped + n1..n0 = number of fingers on touchpad + only models with firmware 2.x report this, models with + firmware 1.x seem to map one, two and three finger taps + directly to L, M and R mouse buttons + h = 1 when horizontal scroll action + w = 1 when wide finger touch? + + otherwise (reg_11, P = 0): + + bit 7 6 5 4 3 2 1 0 + ds7 ds6 ds5 ds4 ds3 ds2 ds1 ds0 + + ds7..ds0 = vertical scroll amount and direction + negative = up + positive = down + + +3.3 Native absolute mode 4 byte packet format + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +byte 0: + firmware version 1.x: + + bit 7 6 5 4 3 2 1 0 + D U p1 p2 1 p3 R L + + L, R = 1 when Left, Right mouse button pressed + p1..p3 = byte 1..3 odd parity bit + D, U = 1 when rocker switch pressed Up, Down + + firmware version 2.x: + + bit 7 6 5 4 3 2 1 0 + n1 n0 p2 p1 1 p3 R L + + L, R = 1 when Left, Right mouse button pressed + p1..p3 = byte 1..3 odd parity bit + n1..n0 = number of fingers on touchpad + +byte 1: + firmware version 1.x: + + bit 7 6 5 4 3 2 1 0 + f 0 th tw x9 x8 y9 y8 + + tw = 1 when two finger touch + th = 1 when three finger touch + f = 1 when finger touch + + firmware version 2.x: + + bit 7 6 5 4 3 2 1 0 + . . . . x9 x8 y9 y8 + +byte 2: + bit 7 6 5 4 3 2 1 0 + x7 x6 x5 x4 x3 x2 x1 x0 + + x9..x0 = absolute x value (horizontal) + +byte 3: + bit 7 6 5 4 3 2 1 0 + y7 y6 y5 y4 y3 y2 y1 y0 + + y9..y0 = absolute y value (vertical) + + +///////////////////////////////////////////////////////////////////////////// + + +4. Hardware version 2 + ================== + + +4.1 Registers + ~~~~~~~~~ + +By echoing a hexadecimal value to a register it contents can be altered. + +For example: + + echo -n 0x56 > reg_10 + +* reg_10 + + bit 7 6 5 4 3 2 1 0 + 0 1 0 1 0 1 D 0 + + D: 1 = enable drag and drop + +* reg_11 + + bit 7 6 5 4 3 2 1 0 + 1 0 0 0 S 0 1 0 + + S: 1 = enable vertical scroll + +* reg_21 + + unknown (0x00) + +* reg_22 + + drag and drop release time out (short: 0x70 ... long 0x7e; + 0x7f = never i.e. tap again to release) + + +4.2 Native absolute mode 6 byte packet format + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +4.2.1 One finger touch + ~~~~~~~~~~~~~~~~ + +byte 0: + + bit 7 6 5 4 3 2 1 0 + n1 n0 . . . . R L + + L, R = 1 when Left, Right mouse button pressed + n1..n0 = numbers of fingers on touchpad + +byte 1: + + bit 7 6 5 4 3 2 1 0 + x15 x14 x13 x12 x11 x10 x9 x8 + +byte 2: + + bit 7 6 5 4 3 2 1 0 + x7 x6 x5 x4 x4 x2 x1 x0 + + x15..x0 = absolute x value (horizontal) + +byte 3: + + bit 7 6 5 4 3 2 1 0 + . . . . . . . . + +byte 4: + + bit 7 6 5 4 3 2 1 0 + y15 y14 y13 y12 y11 y10 y8 y8 + +byte 5: + + bit 7 6 5 4 3 2 1 0 + y7 y6 y5 y4 y3 y2 y1 y0 + + y15..y0 = absolute y value (vertical) + + +4.2.2 Two finger touch + ~~~~~~~~~~~~~~~~ + +byte 0: + + bit 7 6 5 4 3 2 1 0 + n1 n0 ay8 ax8 . . R L + + L, R = 1 when Left, Right mouse button pressed + n1..n0 = numbers of fingers on touchpad + +byte 1: + + bit 7 6 5 4 3 2 1 0 + ax7 ax6 ax5 ax4 ax3 ax2 ax1 ax0 + + ax8..ax0 = first finger absolute x value + +byte 2: + + bit 7 6 5 4 3 2 1 0 + ay7 ay6 ay5 ay4 ay3 ay2 ay1 ay0 + + ay8..ay0 = first finger absolute y value + +byte 3: + + bit 7 6 5 4 3 2 1 0 + . . by8 bx8 . . . . + +byte 4: + + bit 7 6 5 4 3 2 1 0 + bx7 bx6 bx5 bx4 bx3 bx2 bx1 bx0 + + bx8..bx0 = second finger absolute x value + +byte 5: + + bit 7 6 5 4 3 2 1 0 + by7 by8 by5 by4 by3 by2 by1 by0 + + by8..by0 = second finger absolute y value diff --git a/Documentation/input/input-programming.txt b/Documentation/input/input-programming.txt index 81905e81585e..7f8b9d97bc47 100644 --- a/Documentation/input/input-programming.txt +++ b/Documentation/input/input-programming.txt @@ -20,10 +20,11 @@ pressed or released a BUTTON_IRQ happens. The driver could look like: static struct input_dev *button_dev; -static void button_interrupt(int irq, void *dummy, struct pt_regs *fp) +static irqreturn_t button_interrupt(int irq, void *dummy) { input_report_key(button_dev, BTN_0, inb(BUTTON_PORT) & 1); input_sync(button_dev); + return IRQ_HANDLED; } static int __init button_init(void) diff --git a/Documentation/io-mapping.txt b/Documentation/io-mapping.txt new file mode 100644 index 000000000000..473e43b2d588 --- /dev/null +++ b/Documentation/io-mapping.txt @@ -0,0 +1,82 @@ +The io_mapping functions in linux/io-mapping.h provide an abstraction for +efficiently mapping small regions of an I/O device to the CPU. The initial +usage is to support the large graphics aperture on 32-bit processors where +ioremap_wc cannot be used to statically map the entire aperture to the CPU +as it would consume too much of the kernel address space. + +A mapping object is created during driver initialization using + + struct io_mapping *io_mapping_create_wc(unsigned long base, + unsigned long size) + + 'base' is the bus address of the region to be made + mappable, while 'size' indicates how large a mapping region to + enable. Both are in bytes. + + This _wc variant provides a mapping which may only be used + with the io_mapping_map_atomic_wc or io_mapping_map_wc. + +With this mapping object, individual pages can be mapped either atomically +or not, depending on the necessary scheduling environment. Of course, atomic +maps are more efficient: + + void *io_mapping_map_atomic_wc(struct io_mapping *mapping, + unsigned long offset) + + 'offset' is the offset within the defined mapping region. + Accessing addresses beyond the region specified in the + creation function yields undefined results. Using an offset + which is not page aligned yields an undefined result. The + return value points to a single page in CPU address space. + + This _wc variant returns a write-combining map to the + page and may only be used with mappings created by + io_mapping_create_wc + + Note that the task may not sleep while holding this page + mapped. + + void io_mapping_unmap_atomic(void *vaddr) + + 'vaddr' must be the the value returned by the last + io_mapping_map_atomic_wc call. This unmaps the specified + page and allows the task to sleep once again. + +If you need to sleep while holding the lock, you can use the non-atomic +variant, although they may be significantly slower. + + void *io_mapping_map_wc(struct io_mapping *mapping, + unsigned long offset) + + This works like io_mapping_map_atomic_wc except it allows + the task to sleep while holding the page mapped. + + void io_mapping_unmap(void *vaddr) + + This works like io_mapping_unmap_atomic, except it is used + for pages mapped with io_mapping_map_wc. + +At driver close time, the io_mapping object must be freed: + + void io_mapping_free(struct io_mapping *mapping) + +Current Implementation: + +The initial implementation of these functions uses existing mapping +mechanisms and so provides only an abstraction layer and no new +functionality. + +On 64-bit processors, io_mapping_create_wc calls ioremap_wc for the whole +range, creating a permanent kernel-visible mapping to the resource. The +map_atomic and map functions add the requested offset to the base of the +virtual address returned by ioremap_wc. + +On 32-bit processors with HIGHMEM defined, io_mapping_map_atomic_wc uses +kmap_atomic_pfn to map the specified page in an atomic fashion; +kmap_atomic_pfn isn't really supposed to be used with device pages, but it +provides an efficient mapping for this usage. + +On 32-bit processors without HIGHMEM defined, io_mapping_map_atomic_wc and +io_mapping_map_wc both use ioremap_wc, a terribly inefficient function which +performs an IPI to inform all processors about the new mapping. This results +in a significant performance penalty. diff --git a/Documentation/ioctl-number.txt b/Documentation/ioctl-number.txt deleted file mode 100644 index b880ce5dbd33..000000000000 --- a/Documentation/ioctl-number.txt +++ /dev/null @@ -1,201 +0,0 @@ -Ioctl Numbers -19 October 1999 -Michael Elizabeth Chastain - - -If you are adding new ioctl's to the kernel, you should use the _IO -macros defined in : - - _IO an ioctl with no parameters - _IOW an ioctl with write parameters (copy_from_user) - _IOR an ioctl with read parameters (copy_to_user) - _IOWR an ioctl with both write and read parameters. - -'Write' and 'read' are from the user's point of view, just like the -system calls 'write' and 'read'. For example, a SET_FOO ioctl would -be _IOW, although the kernel would actually read data from user space; -a GET_FOO ioctl would be _IOR, although the kernel would actually write -data to user space. - -The first argument to _IO, _IOW, _IOR, or _IOWR is an identifying letter -or number from the table below. Because of the large number of drivers, -many drivers share a partial letter with other drivers. - -If you are writing a driver for a new device and need a letter, pick an -unused block with enough room for expansion: 32 to 256 ioctl commands. -You can register the block by patching this file and submitting the -patch to Linus Torvalds. Or you can e-mail me at and -I'll register one for you. - -The second argument to _IO, _IOW, _IOR, or _IOWR is a sequence number -to distinguish ioctls from each other. The third argument to _IOW, -_IOR, or _IOWR is the type of the data going into the kernel or coming -out of the kernel (e.g. 'int' or 'struct foo'). NOTE! Do NOT use -sizeof(arg) as the third argument as this results in your ioctl thinking -it passes an argument of type size_t. - -Some devices use their major number as the identifier; this is OK, as -long as it is unique. Some devices are irregular and don't follow any -convention at all. - -Following this convention is good because: - -(1) Keeping the ioctl's globally unique helps error checking: - if a program calls an ioctl on the wrong device, it will get an - error rather than some unexpected behaviour. - -(2) The 'strace' build procedure automatically finds ioctl numbers - defined with _IO, _IOW, _IOR, or _IOWR. - -(3) 'strace' can decode numbers back into useful names when the - numbers are unique. - -(4) People looking for ioctls can grep for them more easily when - this convention is used to define the ioctl numbers. - -(5) When following the convention, the driver code can use generic - code to copy the parameters between user and kernel space. - -This table lists ioctls visible from user land for Linux/i386. It contains -most drivers up to 2.3.14, but I know I am missing some. - -Code Seq# Include File Comments -======================================================== -0x00 00-1F linux/fs.h conflict! -0x00 00-1F scsi/scsi_ioctl.h conflict! -0x00 00-1F linux/fb.h conflict! -0x00 00-1F linux/wavefront.h conflict! -0x02 all linux/fd.h -0x03 all linux/hdreg.h -0x04 D2-DC linux/umsdos_fs.h Dead since 2.6.11, but don't reuse these. -0x06 all linux/lp.h -0x09 all linux/md.h -0x12 all linux/fs.h - linux/blkpg.h -0x1b all InfiniBand Subsystem -0x20 all drivers/cdrom/cm206.h -0x22 all scsi/sg.h -'#' 00-3F IEEE 1394 Subsystem Block for the entire subsystem -'1' 00-1F PPS kit from Ulrich Windl - -'8' all SNP8023 advanced NIC card - -'A' 00-1F linux/apm_bios.h -'B' C0-FF advanced bbus - -'C' all linux/soundcard.h -'D' all asm-s390/dasd.h -'E' all linux/input.h -'F' all linux/fb.h -'H' all linux/hiddev.h -'I' all linux/isdn.h -'J' 00-1F drivers/scsi/gdth_ioctl.h -'K' all linux/kd.h -'L' 00-1F linux/loop.h -'L' 20-2F driver/usb/misc/vstusb.h -'L' E0-FF linux/ppdd.h encrypted disk device driver - -'M' all linux/soundcard.h -'N' 00-1F drivers/usb/scanner.h -'P' all linux/soundcard.h -'Q' all linux/soundcard.h -'R' 00-1F linux/random.h -'S' all linux/cdrom.h conflict! -'S' 80-81 scsi/scsi_ioctl.h conflict! -'S' 82-FF scsi/scsi.h conflict! -'T' all linux/soundcard.h conflict! -'T' all asm-i386/ioctls.h conflict! -'U' 00-EF linux/drivers/usb/usb.h -'V' all linux/vt.h -'W' 00-1F linux/watchdog.h conflict! -'W' 00-1F linux/wanrouter.h conflict! -'X' all linux/xfs_fs.h -'Y' all linux/cyclades.h -'[' 00-07 linux/usb/usbtmc.h USB Test and Measurement Devices - -'a' all ATM on linux - -'b' 00-FF bit3 vme host bridge - -'c' 00-7F linux/comstats.h conflict! -'c' 00-7F linux/coda.h conflict! -'c' 80-9F asm-s390/chsc.h -'d' 00-FF linux/char/drm/drm/h conflict! -'d' 00-DF linux/video_decoder.h conflict! -'d' F0-FF linux/digi1.h -'e' all linux/digi1.h conflict! -'e' 00-1F linux/video_encoder.h conflict! -'e' 00-1F net/irda/irtty.h conflict! -'f' 00-1F linux/ext2_fs.h -'h' 00-7F Charon filesystem - -'i' 00-3F linux/i2o.h -'j' 00-3F linux/joystick.h -'l' 00-3F linux/tcfs_fs.h transparent cryptographic file system - -'l' 40-7F linux/udf_fs_i.h in development: - -'m' all linux/mtio.h conflict! -'m' all linux/soundcard.h conflict! -'m' all linux/synclink.h conflict! -'m' 00-1F net/irda/irmod.h conflict! -'n' 00-7F linux/ncp_fs.h -'n' E0-FF video/matrox.h matroxfb -'o' 00-1F fs/ocfs2/ocfs2_fs.h OCFS2 -'p' 00-0F linux/phantom.h conflict! (OpenHaptics needs this) -'p' 00-3F linux/mc146818rtc.h conflict! -'p' 40-7F linux/nvram.h -'p' 80-9F user-space parport - -'q' 00-1F linux/serio.h -'q' 80-FF Internet PhoneJACK, Internet LineJACK - -'r' 00-1F linux/msdos_fs.h -'s' all linux/cdk.h -'t' 00-7F linux/if_ppp.h -'t' 80-8F linux/isdn_ppp.h -'u' 00-1F linux/smb_fs.h -'v' 00-1F linux/ext2_fs.h conflict! -'v' all linux/videodev.h conflict! -'w' all CERN SCI driver -'y' 00-1F packet based user level communications - -'z' 00-3F CAN bus card - -'z' 40-7F CAN bus card - -0x80 00-1F linux/fb.h -0x81 00-1F linux/videotext.h -0x89 00-06 asm-i386/sockios.h -0x89 0B-DF linux/sockios.h -0x89 E0-EF linux/sockios.h SIOCPROTOPRIVATE range -0x89 F0-FF linux/sockios.h SIOCDEVPRIVATE range -0x8B all linux/wireless.h -0x8C 00-3F WiNRADiO driver - -0x90 00 drivers/cdrom/sbpcd.h -0x93 60-7F linux/auto_fs.h -0x99 00-0F 537-Addinboard driver - -0xA0 all linux/sdp/sdp.h Industrial Device Project - -0xA3 80-8F Port ACL in development: - -0xA3 90-9F linux/dtlk.h -0xAB 00-1F linux/nbd.h -0xAC 00-1F linux/raw.h -0xAD 00 Netfilter device in development: - -0xAE all linux/kvm.h Kernel-based Virtual Machine - -0xB0 all RATIO devices in development: - -0xB1 00-1F PPPoX -0xCB 00-1F CBM serial IEC bus in development: - -0xDD 00-3F ZFCP device driver see drivers/s390/scsi/ - -0xF3 00-3F video/sisfb.h sisfb (in development) - -0xF4 00-1F video/mbxfb.h mbxfb - diff --git a/Documentation/ioctl/00-INDEX b/Documentation/ioctl/00-INDEX new file mode 100644 index 000000000000..d2fe4d4729ef --- /dev/null +++ b/Documentation/ioctl/00-INDEX @@ -0,0 +1,10 @@ +00-INDEX + - this file +cdrom.txt + - summary of CDROM ioctl calls +hdio.txt + - summary of HDIO_ ioctl calls +ioctl-decoding.txt + - how to decode the bits of an IOCTL code +ioctl-number.txt + - how to implement and register device/driver ioctl calls diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt new file mode 100644 index 000000000000..b880ce5dbd33 --- /dev/null +++ b/Documentation/ioctl/ioctl-number.txt @@ -0,0 +1,201 @@ +Ioctl Numbers +19 October 1999 +Michael Elizabeth Chastain + + +If you are adding new ioctl's to the kernel, you should use the _IO +macros defined in : + + _IO an ioctl with no parameters + _IOW an ioctl with write parameters (copy_from_user) + _IOR an ioctl with read parameters (copy_to_user) + _IOWR an ioctl with both write and read parameters. + +'Write' and 'read' are from the user's point of view, just like the +system calls 'write' and 'read'. For example, a SET_FOO ioctl would +be _IOW, although the kernel would actually read data from user space; +a GET_FOO ioctl would be _IOR, although the kernel would actually write +data to user space. + +The first argument to _IO, _IOW, _IOR, or _IOWR is an identifying letter +or number from the table below. Because of the large number of drivers, +many drivers share a partial letter with other drivers. + +If you are writing a driver for a new device and need a letter, pick an +unused block with enough room for expansion: 32 to 256 ioctl commands. +You can register the block by patching this file and submitting the +patch to Linus Torvalds. Or you can e-mail me at and +I'll register one for you. + +The second argument to _IO, _IOW, _IOR, or _IOWR is a sequence number +to distinguish ioctls from each other. The third argument to _IOW, +_IOR, or _IOWR is the type of the data going into the kernel or coming +out of the kernel (e.g. 'int' or 'struct foo'). NOTE! Do NOT use +sizeof(arg) as the third argument as this results in your ioctl thinking +it passes an argument of type size_t. + +Some devices use their major number as the identifier; this is OK, as +long as it is unique. Some devices are irregular and don't follow any +convention at all. + +Following this convention is good because: + +(1) Keeping the ioctl's globally unique helps error checking: + if a program calls an ioctl on the wrong device, it will get an + error rather than some unexpected behaviour. + +(2) The 'strace' build procedure automatically finds ioctl numbers + defined with _IO, _IOW, _IOR, or _IOWR. + +(3) 'strace' can decode numbers back into useful names when the + numbers are unique. + +(4) People looking for ioctls can grep for them more easily when + this convention is used to define the ioctl numbers. + +(5) When following the convention, the driver code can use generic + code to copy the parameters between user and kernel space. + +This table lists ioctls visible from user land for Linux/i386. It contains +most drivers up to 2.3.14, but I know I am missing some. + +Code Seq# Include File Comments +======================================================== +0x00 00-1F linux/fs.h conflict! +0x00 00-1F scsi/scsi_ioctl.h conflict! +0x00 00-1F linux/fb.h conflict! +0x00 00-1F linux/wavefront.h conflict! +0x02 all linux/fd.h +0x03 all linux/hdreg.h +0x04 D2-DC linux/umsdos_fs.h Dead since 2.6.11, but don't reuse these. +0x06 all linux/lp.h +0x09 all linux/md.h +0x12 all linux/fs.h + linux/blkpg.h +0x1b all InfiniBand Subsystem +0x20 all drivers/cdrom/cm206.h +0x22 all scsi/sg.h +'#' 00-3F IEEE 1394 Subsystem Block for the entire subsystem +'1' 00-1F PPS kit from Ulrich Windl + +'8' all SNP8023 advanced NIC card + +'A' 00-1F linux/apm_bios.h +'B' C0-FF advanced bbus + +'C' all linux/soundcard.h +'D' all asm-s390/dasd.h +'E' all linux/input.h +'F' all linux/fb.h +'H' all linux/hiddev.h +'I' all linux/isdn.h +'J' 00-1F drivers/scsi/gdth_ioctl.h +'K' all linux/kd.h +'L' 00-1F linux/loop.h +'L' 20-2F driver/usb/misc/vstusb.h +'L' E0-FF linux/ppdd.h encrypted disk device driver + +'M' all linux/soundcard.h +'N' 00-1F drivers/usb/scanner.h +'P' all linux/soundcard.h +'Q' all linux/soundcard.h +'R' 00-1F linux/random.h +'S' all linux/cdrom.h conflict! +'S' 80-81 scsi/scsi_ioctl.h conflict! +'S' 82-FF scsi/scsi.h conflict! +'T' all linux/soundcard.h conflict! +'T' all asm-i386/ioctls.h conflict! +'U' 00-EF linux/drivers/usb/usb.h +'V' all linux/vt.h +'W' 00-1F linux/watchdog.h conflict! +'W' 00-1F linux/wanrouter.h conflict! +'X' all linux/xfs_fs.h +'Y' all linux/cyclades.h +'[' 00-07 linux/usb/usbtmc.h USB Test and Measurement Devices + +'a' all ATM on linux + +'b' 00-FF bit3 vme host bridge + +'c' 00-7F linux/comstats.h conflict! +'c' 00-7F linux/coda.h conflict! +'c' 80-9F asm-s390/chsc.h +'d' 00-FF linux/char/drm/drm/h conflict! +'d' 00-DF linux/video_decoder.h conflict! +'d' F0-FF linux/digi1.h +'e' all linux/digi1.h conflict! +'e' 00-1F linux/video_encoder.h conflict! +'e' 00-1F net/irda/irtty.h conflict! +'f' 00-1F linux/ext2_fs.h +'h' 00-7F Charon filesystem + +'i' 00-3F linux/i2o.h +'j' 00-3F linux/joystick.h +'l' 00-3F linux/tcfs_fs.h transparent cryptographic file system + +'l' 40-7F linux/udf_fs_i.h in development: + +'m' all linux/mtio.h conflict! +'m' all linux/soundcard.h conflict! +'m' all linux/synclink.h conflict! +'m' 00-1F net/irda/irmod.h conflict! +'n' 00-7F linux/ncp_fs.h +'n' E0-FF video/matrox.h matroxfb +'o' 00-1F fs/ocfs2/ocfs2_fs.h OCFS2 +'p' 00-0F linux/phantom.h conflict! (OpenHaptics needs this) +'p' 00-3F linux/mc146818rtc.h conflict! +'p' 40-7F linux/nvram.h +'p' 80-9F user-space parport + +'q' 00-1F linux/serio.h +'q' 80-FF Internet PhoneJACK, Internet LineJACK + +'r' 00-1F linux/msdos_fs.h +'s' all linux/cdk.h +'t' 00-7F linux/if_ppp.h +'t' 80-8F linux/isdn_ppp.h +'u' 00-1F linux/smb_fs.h +'v' 00-1F linux/ext2_fs.h conflict! +'v' all linux/videodev.h conflict! +'w' all CERN SCI driver +'y' 00-1F packet based user level communications + +'z' 00-3F CAN bus card + +'z' 40-7F CAN bus card + +0x80 00-1F linux/fb.h +0x81 00-1F linux/videotext.h +0x89 00-06 asm-i386/sockios.h +0x89 0B-DF linux/sockios.h +0x89 E0-EF linux/sockios.h SIOCPROTOPRIVATE range +0x89 F0-FF linux/sockios.h SIOCDEVPRIVATE range +0x8B all linux/wireless.h +0x8C 00-3F WiNRADiO driver + +0x90 00 drivers/cdrom/sbpcd.h +0x93 60-7F linux/auto_fs.h +0x99 00-0F 537-Addinboard driver + +0xA0 all linux/sdp/sdp.h Industrial Device Project + +0xA3 80-8F Port ACL in development: + +0xA3 90-9F linux/dtlk.h +0xAB 00-1F linux/nbd.h +0xAC 00-1F linux/raw.h +0xAD 00 Netfilter device in development: + +0xAE all linux/kvm.h Kernel-based Virtual Machine + +0xB0 all RATIO devices in development: + +0xB1 00-1F PPPoX +0xCB 00-1F CBM serial IEC bus in development: + +0xDD 00-3F ZFCP device driver see drivers/s390/scsi/ + +0xF3 00-3F video/sisfb.h sisfb (in development) + +0xF4 00-1F video/mbxfb.h mbxfb + diff --git a/Documentation/isdn/CREDITS b/Documentation/isdn/CREDITS index 8cac6c2f23ee..c1679e913fca 100644 --- a/Documentation/isdn/CREDITS +++ b/Documentation/isdn/CREDITS @@ -5,7 +5,7 @@ I want to thank all who contributed to this project and especially to: Thomas Bogendörfer (tsbogend@bigbug.franken.de) Tester, lots of bugfixes and hints. -Alan Cox (alan@redhat.com) +Alan Cox (alan@lxorguk.ukuu.org.uk) For help getting into standard-kernel. Henner Eisen (eis@baty.hanse.de) diff --git a/Documentation/ja_JP/HOWTO b/Documentation/ja_JP/HOWTO index 0775cf4798b2..55476982b5ca 100644 --- a/Documentation/ja_JP/HOWTO +++ b/Documentation/ja_JP/HOWTO @@ -11,14 +11,14 @@ for non English (read: Japanese) speakers and is not intended as a fork. So if you have any comments or updates for this file, please try to update the original English file first. -Last Updated: 2008/08/21 +Last Updated: 2008/10/24 ================================== これは、 -linux-2.6.27/Documentation/HOWTO +linux-2.6.28/Documentation/HOWTO の和訳です。 翻訳団体： JF プロジェクト < http://www.linux.or.jp/JF/ > -翻訳日： 2008/8/5 +翻訳日： 2008/10/24 翻訳者： Tsugikazu Shibata 校正者： 松倉さん 小林 雅典さん (Masanori Kobayasi) @@ -110,8 +110,8 @@ Linux カーネルソースツリーは幅広い範囲のドキュメントを 新しいドキュメントファイルも追加することを勧めます。 カーネルの変更が、カーネルがユーザ空間に公開しているインターフェイスの 変更を引き起こす場合、その変更を説明するマニュアルページのパッチや情報 -をマニュアルページのメンテナ mtk.manpages@gmail.com に送ることを勧めま -す。 +をマニュアルページのメンテナ mtk.manpages@gmail.com に送り、CC を +linux-api@ver.kernel.org に送ることを勧めます。 以下はカーネルソースツリーに含まれている読んでおくべきファイルの一覧で す- @@ -149,7 +149,7 @@ Linux カーネルソースツリーは幅広い範囲のドキュメントを この他にパッチを作る方法についてのよくできた記述は- "The Perfect Patch" - http://www.zip.com.au/~akpm/linux/patches/stuff/tpp.txt + http://userweb.kernel.org/~akpm/stuff/tpp.txt "Linux kernel patch submission format" http://linux.yyz.us/patch-format.html @@ -664,7 +664,7 @@ Linux カーネルコミュニティは、一度に大量のコードの塊を これについて全てがどのようにあるべきかについての詳細は、以下のドキュメ ントの ChangeLog セクションを見てください- "The Perfect Patch" - http://www.zip.com.au/~akpm/linux/patches/stuff/tpp.txt + http://userweb.kernel.org/~akpm/stuff/tpp.txt これらのどれもが、時にはとても困難です。これらの慣例を完璧に実施するに は数年かかるかもしれません。これは継続的な改善のプロセスであり、そのた diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 63bac584f9cb..d5418d528910 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -100,7 +100,7 @@ parameter is applicable: X86-32 X86-32, aka i386 architecture is enabled. X86-64 X86-64 architecture is enabled. More X86-64 boot options can be found in - Documentation/x86_64/boot-options.txt . + Documentation/x86/x86_64/boot-options.txt . X86 Either 32bit or 64bit x86 (same as X86-32+X86-64) In addition, the following text indicates that the option: @@ -112,10 +112,10 @@ In addition, the following text indicates that the option: Parameters denoted with BOOT are actually interpreted by the boot loader, and have no meaning to the kernel directly. Do not modify the syntax of boot loader parameters without extreme -need or coordination with . +need or coordination with . There are also arch-specific kernel-parameters not documented here. -See for example . +See for example . Note that ALL kernel parameters listed below are CASE SENSITIVE, and that a trailing = on the name of any parameter states that that parameter will @@ -198,59 +198,42 @@ and is between 256 and 4096 characters. It is defined in the file that require a timer override, but don't have HPET - acpi.debug_layer= [HW,ACPI] - Format: - Each bit of the indicates an ACPI debug layer, - 1: enable, 0: disable. It is useful for boot time - debugging. After system has booted up, it can be set - via /sys/module/acpi/parameters/debug_layer. - CONFIG_ACPI_DEBUG must be enabled for this to produce any output. - Available bits (add the numbers together) to enable debug output - for specific parts of the ACPI subsystem: - 0x01 utilities 0x02 hardware 0x04 events 0x08 tables - 0x10 namespace 0x20 parser 0x40 dispatcher - 0x80 executer 0x100 resources 0x200 acpica debugger - 0x400 os services 0x800 acpica disassembler. - The number can be in decimal or prefixed with 0x in hex. - Warning: Many of these options can produce a lot of - output and make your system unusable. Be very careful. - - acpi.debug_level= [HW,ACPI] + acpi_backlight= [HW,ACPI] + acpi_backlight=vendor + acpi_backlight=video + If set to vendor, prefer vendor specific driver + (e.g. thinkpad_acpi, sony_acpi, etc.) instead + of the ACPI video.ko driver. + + acpi_display_output= [HW,ACPI] + acpi_display_output=vendor + acpi_display_output=video + See above. + + acpi.debug_layer= [HW,ACPI,ACPI_DEBUG] + acpi.debug_level= [HW,ACPI,ACPI_DEBUG] Format: - Each bit of the indicates an ACPI debug level, - which corresponds to the level in an ACPI_DEBUG_PRINT - statement. After system has booted up, this mask - can be set via /sys/module/acpi/parameters/debug_level. - - CONFIG_ACPI_DEBUG must be enabled for this to produce - any output. The number can be in decimal or prefixed - with 0x in hex. Some of these options produce so much - output that the system is unusable. - - The following global components are defined by the - ACPI CA: - 0x01 error - 0x02 warn - 0x04 init - 0x08 debug object - 0x10 info - 0x20 init names - 0x40 parse - 0x80 load - 0x100 dispatch - 0x200 execute - 0x400 names - 0x800 operation region - 0x1000 bfield - 0x2000 tables - 0x4000 values - 0x8000 objects - 0x10000 resources - 0x20000 user requests - 0x40000 package - The number can be in decimal or prefixed with 0x in hex. - Warning: Many of these options can produce a lot of - output and make your system unusable. Be very careful. + CONFIG_ACPI_DEBUG must be enabled to produce any ACPI + debug output. Bits in debug_layer correspond to a + _COMPONENT in an ACPI source file, e.g., + #define _COMPONENT ACPI_PCI_COMPONENT + Bits in debug_level correspond to a level in + ACPI_DEBUG_PRINT statements, e.g., + ACPI_DEBUG_PRINT((ACPI_DB_INFO, ... + See Documentation/acpi/debug.txt for more information + about debug layers and levels. + + Enable AML "Debug" output, i.e., stores to the Debug + object while interpreting AML: + acpi.debug_layer=0xffffffff acpi.debug_level=0x2 + Enable PCI/PCI interrupt routing info messages: + acpi.debug_layer=0x400000 acpi.debug_level=0x4 + Enable all messages related to ACPI hardware: + acpi.debug_layer=0x2 acpi.debug_level=0xffffffff + + Some values produce so much output that the system is + unusable. The "log_buf_len" parameter may be useful + if you need to capture more output. acpi.power_nocheck= [HW,ACPI] Format: 1/0 enable/disable the check of power state. @@ -311,7 +294,9 @@ and is between 256 and 4096 characters. It is defined in the file Possible values are: isolate - enable device isolation (each device, as far as possible, will get its own protection - domain) + domain) [default] + share - put every device behind one IOMMU into the + same protection domain fullflush - enable flushing of IO/TLB entries when they are unmapped. Otherwise they are flushed before they will be reused, which @@ -646,7 +631,7 @@ and is between 256 and 4096 characters. It is defined in the file digiepca= [HW,SERIAL] See drivers/char/README.epca and - Documentation/digiepca.txt. + Documentation/serial/digiepca.txt. disable_mtrr_cleanup [X86] enable_mtrr_cleanup [X86] @@ -757,7 +742,7 @@ and is between 256 and 4096 characters. It is defined in the file See header of drivers/scsi/fdomain.c. floppy= [HW] - See Documentation/floppy.txt. + See Documentation/blockdev/floppy.txt. force_pal_cache_flush [IA-64] Avoid check_sal_cache_flush which may hang on @@ -995,13 +980,15 @@ and is between 256 and 4096 characters. It is defined in the file Format: ,..., or - - (must be a positive range in ascending order) + - + (must be a positive range in ascending order) or a mixture ,...,- + This option can be used to specify one or more CPUs to isolate from the general SMP balancing and scheduling - algorithms. The only way to move a process onto or off - an "isolated" CPU is via the CPU affinity syscalls. + algorithms. You can move a process onto or off an + "isolated" CPU via the CPU affinity syscalls or cpuset. begins at 0 and the maximum value is "number of CPUs in system - 1". @@ -1116,7 +1103,7 @@ and is between 256 and 4096 characters. It is defined in the file the same attribute, the last one is used. load_ramdisk= [RAM] List of ramdisks to load from floppy - See Documentation/ramdisk.txt. + See Documentation/blockdev/ramdisk.txt. lockd.nlm_grace_period=P [NFS] Assign grace period. Format: @@ -1208,8 +1195,8 @@ and is between 256 and 4096 characters. It is defined in the file it is equivalent to "nosmp", which also disables the IO APIC. - max_addr=[KMG] [KNL,BOOT,ia64] All physical memory greater than or - equal to this physical address is ignored. + max_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory greater than + or equal to this physical address is ignored. max_luns= [SCSI] Maximum number of LUNs to probe. Should be between 1 and 2^32-1. @@ -1222,7 +1209,7 @@ and is between 256 and 4096 characters. It is defined in the file mce [X86-32] Machine Check Exception - mce=option [X86-64] See Documentation/x86_64/boot-options.txt + mce=option [X86-64] See Documentation/x86/x86_64/boot-options.txt md= [HW] RAID subsystems devices and level See Documentation/md.txt. @@ -1309,6 +1296,9 @@ and is between 256 and 4096 characters. It is defined in the file mga= [HW,DRM] + min_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory below this + physical address is ignored. + mminit_loglevel= [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this parameter allows control of the logging verbosity for @@ -1403,7 +1393,20 @@ and is between 256 and 4096 characters. It is defined in the file when a NMI is triggered. Format: [state][,regs][,debounce][,die] - nmi_watchdog= [KNL,BUGS=X86-32] Debugging features for SMP kernels + nmi_watchdog= [KNL,BUGS=X86-32,X86-64] Debugging features for SMP kernels + Format: [panic,][num] + Valid num: 0,1,2 + 0 - turn nmi_watchdog off + 1 - use the IO-APIC timer for the NMI watchdog + 2 - use the local APIC for the NMI watchdog using + a performance counter. Note: This will use one performance + counter and the local APIC's performance vector. + When panic is specified panic when an NMI watchdog timeout occurs. + This is useful when you use a panic=... timeout and need the box + quickly up again. + Instead of 1 and 2 it is possible to use the following + symbolic names: lapic and ioapic + Example: nmi_watchdog=2 or nmi_watchdog=panic,lapic no387 [BUGS=X86-32] Tells the kernel to use the 387 maths emulation library even if a 387 maths coprocessor @@ -1470,8 +1473,6 @@ and is between 256 and 4096 characters. It is defined in the file Valid arguments: on, off Default: on - noirqbalance [X86-32,SMP,KNL] Disable kernel irq balancing - noirqdebug [X86-32] Disables the code which attempts to detect and disable unhandled interrupt sources. @@ -1613,7 +1614,7 @@ and is between 256 and 4096 characters. It is defined in the file pcd. [PARIDE] See header of drivers/block/paride/pcd.c. - See also Documentation/paride.txt. + See also Documentation/blockdev/paride.txt. pci=option[,option...] [PCI] various PCI subsystem options: off [X86] don't probe for the PCI bus @@ -1725,7 +1726,7 @@ and is between 256 and 4096 characters. It is defined in the file pcmv= [HW,PCMCIA] BadgePAD 4 pd. [PARIDE] - See Documentation/paride.txt. + See Documentation/blockdev/paride.txt. pdcchassis= [PARISC,HW] Disable/Enable PDC Chassis Status codes at boot time. @@ -1733,13 +1734,13 @@ and is between 256 and 4096 characters. It is defined in the file See arch/parisc/kernel/pdc_chassis.c pf. [PARIDE] - See Documentation/paride.txt. + See Documentation/blockdev/paride.txt. pg. [PARIDE] - See Documentation/paride.txt. + See Documentation/blockdev/paride.txt. pirq= [SMP,APIC] Manual mp-table setup - See Documentation/i386/IO-APIC.txt. + See Documentation/x86/i386/IO-APIC.txt. plip= [PPT,NET] Parallel port network link Format: { parport | timid | 0 } @@ -1806,7 +1807,7 @@ and is between 256 and 4096 characters. It is defined in the file prompt_ramdisk= [RAM] List of RAM disks to prompt for floppy disk before loading. - See Documentation/ramdisk.txt. + See Documentation/blockdev/ramdisk.txt. psmouse.proto= [HW,MOUSE] Highest PS2 mouse protocol extension to probe for; one of (bare|imps|exps|lifebook|any). @@ -1826,7 +1827,7 @@ and is between 256 and 4096 characters. It is defined in the file ,,,,, pt. [PARIDE] - See Documentation/paride.txt. + See Documentation/blockdev/paride.txt. pty.legacy_count= [KNL] Number of legacy pty's. Overwrites compiled-in @@ -1840,10 +1841,10 @@ and is between 256 and 4096 characters. It is defined in the file See Documentation/md.txt. ramdisk_blocksize= [RAM] - See Documentation/ramdisk.txt. + See Documentation/blockdev/ramdisk.txt. ramdisk_size= [RAM] Sizes of RAM disks in kilobytes - See Documentation/ramdisk.txt. + See Documentation/blockdev/ramdisk.txt. rcupdate.blimit= [KNL,BOOT] Set maximum number of finished RCU callbacks to process @@ -2175,7 +2176,7 @@ and is between 256 and 4096 characters. It is defined in the file See Documentation/sonypi.txt specialix= [HW,SERIAL] Specialix multi-serial port adapter - See Documentation/specialix.txt. + See Documentation/serial/specialix.txt. spia_io_base= [HW,MTD] spia_fio_base= @@ -2278,6 +2279,13 @@ and is between 256 and 4096 characters. It is defined in the file Format: ,,,,,,,, + tsc= Disable clocksource-must-verify flag for TSC. + Format: + [x86] reliable: mark tsc clocksource as reliable, this + disables clocksource verification at runtime. + Used to enable high-resolution timer mode on older + hardware, and in virtualized environment. + turbografx.map[2|3]= [HW,JOY] TurboGraFX parallel port interface Format: @@ -2354,7 +2362,7 @@ and is between 256 and 4096 characters. It is defined in the file See Documentation/fb/modedb.txt. vga= [BOOT,X86-32] Select a particular video mode - See Documentation/i386/boot.txt and + See Documentation/x86/i386/boot.txt and Documentation/svga.txt. Use vga=ask for menu. This is actually a boot loader parameter; the value is diff --git a/Documentation/lguest/Makefile b/Documentation/lguest/Makefile index bac037eb1cda..725eef81cd48 100644 --- a/Documentation/lguest/Makefile +++ b/Documentation/lguest/Makefile @@ -1,5 +1,5 @@ # This creates the demonstration utility "lguest" which runs a Linux guest. -CFLAGS:=-Wall -Wmissing-declarations -Wmissing-prototypes -O3 -I../../include +CFLAGS:=-Wall -Wmissing-declarations -Wmissing-prototypes -O3 -I../../include -I../../arch/x86/include LDLIBS:=-lz all: lguest diff --git a/Documentation/lguest/lguest.c b/Documentation/lguest/lguest.c index 7228369d1014..804520633fcf 100644 --- a/Documentation/lguest/lguest.c +++ b/Documentation/lguest/lguest.c @@ -44,7 +44,7 @@ #include "linux/virtio_console.h" #include "linux/virtio_rng.h" #include "linux/virtio_ring.h" -#include "asm-x86/bootparam.h" +#include "asm/bootparam.h" /*L:110 We can ignore the 39 include files we need for this program, but I do * want to draw attention to the use of kernel-style types. * @@ -402,7 +402,7 @@ static unsigned long load_bzimage(int fd) void *p = from_guest_phys(0x100000); /* Go back to the start of the file and read the header. It should be - * a Linux boot header (see Documentation/i386/boot.txt) */ + * a Linux boot header (see Documentation/x86/i386/boot.txt) */ lseek(fd, 0, SEEK_SET); read(fd, &boot, sizeof(boot)); diff --git a/Documentation/local_ops.txt b/Documentation/local_ops.txt index f4f8b1c6c8ba..23045b8b50f0 100644 --- a/Documentation/local_ops.txt +++ b/Documentation/local_ops.txt @@ -149,7 +149,7 @@ static void do_test_timer(unsigned long data) int cpu; /* Increment the counters */ - on_each_cpu(test_each, NULL, 0, 1); + on_each_cpu(test_each, NULL, 1); /* Read all the counters */ printk("Counters read from CPU %d\n", smp_processor_id()); for_each_online_cpu(cpu) { diff --git a/Documentation/moxa-smartio b/Documentation/moxa-smartio deleted file mode 100644 index 5337e80a5b96..000000000000 --- a/Documentation/moxa-smartio +++ /dev/null @@ -1,523 +0,0 @@ -============================================================================= - MOXA Smartio/Industio Family Device Driver Installation Guide - for Linux Kernel 2.4.x, 2.6.x - Copyright (C) 2008, Moxa Inc. -============================================================================= -Date: 01/21/2008 - -Content - -1. Introduction -2. System Requirement -3. Installation - 3.1 Hardware installation - 3.2 Driver files - 3.3 Device naming convention - 3.4 Module driver configuration - 3.5 Static driver configuration for Linux kernel 2.4.x and 2.6.x. - 3.6 Custom configuration - 3.7 Verify driver installation -4. Utilities -5. Setserial -6. Troubleshooting - ------------------------------------------------------------------------------ -1. Introduction - - The Smartio/Industio/UPCI family Linux driver supports following multiport - boards. - - - 2 ports multiport board - CP-102U, CP-102UL, CP-102UF - CP-132U-I, CP-132UL, - CP-132, CP-132I, CP132S, CP-132IS, - CI-132, CI-132I, CI-132IS, - (C102H, C102HI, C102HIS, C102P, CP-102, CP-102S) - - - 4 ports multiport board - CP-104EL, - CP-104UL, CP-104JU, - CP-134U, CP-134U-I, - C104H/PCI, C104HS/PCI, - CP-114, CP-114I, CP-114S, CP-114IS, CP-114UL, - C104H, C104HS, - CI-104J, CI-104JS, - CI-134, CI-134I, CI-134IS, - (C114HI, CT-114I, C104P) - POS-104UL, - CB-114, - CB-134I - - - 8 ports multiport board - CP-118EL, CP-168EL, - CP-118U, CP-168U, - C168H/PCI, - C168H, C168HS, - (C168P), - CB-108 - - This driver and installation procedure have been developed upon Linux Kernel - 2.4.x and 2.6.x. This driver supports Intel x86 hardware platform. In order - to maintain compatibility, this version has also been properly tested with - RedHat, Mandrake, Fedora and S.u.S.E Linux. However, if compatibility problem - occurs, please contact Moxa at support@moxa.com.tw. - - In addition to device driver, useful utilities are also provided in this - version. They are - - msdiag Diagnostic program for displaying installed Moxa - Smartio/Industio boards. - - msmon Monitor program to observe data count and line status signals. - - msterm A simple terminal program which is useful in testing serial - ports. - - io-irq.exe Configuration program to setup ISA boards. Please note that - this program can only be executed under DOS. - - All the drivers and utilities are published in form of source code under - GNU General Public License in this version. Please refer to GNU General - Public License announcement in each source code file for more detail. - - In Moxa's Web sites, you may always find latest driver at http://web.moxa.com. - - This version of driver can be installed as Loadable Module (Module driver) - or built-in into kernel (Static driver). You may refer to following - installation procedure for suitable one. Before you install the driver, - please refer to hardware installation procedure in the User's Manual. - - We assume the user should be familiar with following documents. - - Serial-HOWTO - - Kernel-HOWTO - ------------------------------------------------------------------------------ -2. System Requirement - - Hardware platform: Intel x86 machine - - Kernel version: 2.4.x or 2.6.x - - gcc version 2.72 or later - - Maximum 4 boards can be installed in combination - ------------------------------------------------------------------------------ -3. Installation - - 3.1 Hardware installation - 3.2 Driver files - 3.3 Device naming convention - 3.4 Module driver configuration - 3.5 Static driver configuration for Linux kernel 2.4.x, 2.6.x. - 3.6 Custom configuration - 3.7 Verify driver installation - - - 3.1 Hardware installation - - There are two types of buses, ISA and PCI, for Smartio/Industio - family multiport board. - - ISA board - --------- - You'll have to configure CAP address, I/O address, Interrupt Vector - as well as IRQ before installing this driver. Please refer to hardware - installation procedure in User's Manual before proceed any further. - Please make sure the JP1 is open after the ISA board is set properly. - - PCI/UPCI board - -------------- - You may need to adjust IRQ usage in BIOS to avoid from IRQ conflict - with other ISA devices. Please refer to hardware installation - procedure in User's Manual in advance. - - PCI IRQ Sharing - ----------- - Each port within the same multiport board shares the same IRQ. Up to - 4 Moxa Smartio/Industio PCI Family multiport boards can be installed - together on one system and they can share the same IRQ. - - - 3.2 Driver files - - The driver file may be obtained from ftp, CD-ROM or floppy disk. The - first step, anyway, is to copy driver file "mxser.tgz" into specified - directory. e.g. /moxa. The execute commands as below. - - # cd / - # mkdir moxa - # cd /moxa - # tar xvf /dev/fd0 - - or - - # cd / - # mkdir moxa - # cd /moxa - # cp /mnt/cdrom//mxser.tgz . - # tar xvfz mxser.tgz - - - 3.3 Device naming convention - - You may find all the driver and utilities files in /moxa/mxser. - Following installation procedure depends on the model you'd like to - run the driver. If you prefer module driver, please refer to 3.4. - If static driver is required, please refer to 3.5. - - Dialin and callout port - ----------------------- - This driver remains traditional serial device properties. There are - two special file name for each serial port. One is dial-in port - which is named "ttyMxx". For callout port, the naming convention - is "cumxx". - - Device naming when more than 2 boards installed - ----------------------------------------------- - Naming convention for each Smartio/Industio multiport board is - pre-defined as below. - - Board Num. Dial-in Port Callout port - 1st board ttyM0 - ttyM7 cum0 - cum7 - 2nd board ttyM8 - ttyM15 cum8 - cum15 - 3rd board ttyM16 - ttyM23 cum16 - cum23 - 4th board ttyM24 - ttym31 cum24 - cum31 - - - !!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - Under Kernel 2.6 the cum Device is Obsolete. So use ttyM* - device instead. - !!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - - Board sequence - -------------- - This driver will activate ISA boards according to the parameter set - in the driver. After all specified ISA board activated, PCI board - will be installed in the system automatically driven. - Therefore the board number is sorted by the CAP address of ISA boards. - For PCI boards, their sequence will be after ISA boards and C168H/PCI - has higher priority than C104H/PCI boards. - - 3.4 Module driver configuration - Module driver is easiest way to install. If you prefer static driver - installation, please skip this paragraph. - - - ------------- Prepare to use the MOXA driver-------------------- - 3.4.1 Create tty device with correct major number - Before using MOXA driver, your system must have the tty devices - which are created with driver's major number. We offer one shell - script "msmknod" to simplify the procedure. - This step is only needed to be executed once. But you still - need to do this procedure when: - a. You change the driver's major number. Please refer the "3.7" - section. - b. Your total installed MOXA boards number is changed. Maybe you - add/delete one MOXA board. - c. You want to change the tty name. This needs to modify the - shell script "msmknod" - - The procedure is: - # cd /moxa/mxser/driver - # ./msmknod - - This shell script will require the major number for dial-in - device and callout device to create tty device. You also need - to specify the total installed MOXA board number. Default major - numbers for dial-in device and callout device are 30, 35. If - you need to change to other number, please refer section "3.7" - for more detailed procedure. - Msmknod will delete any special files occupying the same device - naming. - - 3.4.2 Build the MOXA driver and utilities - Before using the MOXA driver and utilities, you need compile the - all the source code. This step is only need to be executed once. - But you still re-compile the source code if you modify the source - code. For example, if you change the driver's major number (see - "3.7" section), then you need to do this step again. - - Find "Makefile" in /moxa/mxser, then run - - # make clean; make install - - !!!!!!!!!! NOTE !!!!!!!!!!!!!!!!! - For Red Hat 9, Red Hat Enterprise Linux AS3/ES3/WS3 & Fedora Core1: - # make clean; make installsp1 - - For Red Hat Enterprise Linux AS4/ES4/WS4: - # make clean; make installsp2 - !!!!!!!!!! NOTE !!!!!!!!!!!!!!!!! - - The driver files "mxser.o" and utilities will be properly compiled - and copied to system directories respectively. - - ------------- Load MOXA driver-------------------- - 3.4.3 Load the MOXA driver - - # modprobe mxser - - will activate the module driver. You may run "lsmod" to check - if "mxser" is activated. If the MOXA board is ISA board, the - is needed. Please refer to section "3.4.5" for more - information. - - - ------------- Load MOXA driver on boot -------------------- - 3.4.4 For the above description, you may manually execute - "modprobe mxser" to activate this driver and run - "rmmod mxser" to remove it. - However, it's better to have a boot time configuration to - eliminate manual operation. Boot time configuration can be - achieved by rc file. We offer one "rc.mxser" file to simplify - the procedure under "moxa/mxser/driver". - - But if you use ISA board, please modify the "modprobe ..." command - to add the argument (see "3.4.5" section). After modifying the - rc.mxser, please try to execute "/moxa/mxser/driver/rc.mxser" - manually to make sure the modification is ok. If any error - encountered, please try to modify again. If the modification is - completed, follow the below step. - - Run following command for setting rc files. - - # cd /moxa/mxser/driver - # cp ./rc.mxser /etc/rc.d - # cd /etc/rc.d - - Check "rc.serial" is existed or not. If "rc.serial" doesn't exist, - create it by vi, run "chmod 755 rc.serial" to change the permission. - Add "/etc/rc.d/rc.mxser" in last line, - - Reboot and check if moxa.o activated by "lsmod" command. - - 3.4.5. If you'd like to drive Smartio/Industio ISA boards in the system, - you'll have to add parameter to specify CAP address of given - board while activating "mxser.o". The format for parameters are - as follows. - - modprobe mxser ioaddr=0x???,0x???,0x???,0x??? - | | | | - | | | +- 4th ISA board - | | +------ 3rd ISA board - | +------------ 2nd ISA board - +------------------- 1st ISA board - - 3.5 Static driver configuration for Linux kernel 2.4.x and 2.6.x - - Note: To use static driver, you must install the linux kernel - source package. - - 3.5.1 Backup the built-in driver in the kernel. - # cd /usr/src/linux/drivers/char - # mv mxser.c mxser.c.old - - For Red Hat 7.x user, you need to create link: - # cd /usr/src - # ln -s linux-2.4 linux - - 3.5.2 Create link - # cd /usr/src/linux/drivers/char - # ln -s /moxa/mxser/driver/mxser.c mxser.c - - 3.5.3 Add CAP address list for ISA boards. For PCI boards user, - please skip this step. - - In module mode, the CAP address for ISA board is given by - parameter. In static driver configuration, you'll have to - assign it within driver's source code. If you will not - install any ISA boards, you may skip to next portion. - The instructions to modify driver source code are as - below. - a. # cd /moxa/mxser/driver - # vi mxser.c - b. Find the array mxserBoardCAP[] as below. - - static int mxserBoardCAP[] - = {0x00, 0x00, 0x00, 0x00}; - - c. Change the address within this array using vi. For - example, to driver 2 ISA boards with CAP address - 0x280 and 0x180 as 1st and 2nd board. Just to change - the source code as follows. - - static int mxserBoardCAP[] - = {0x280, 0x180, 0x00, 0x00}; - - 3.5.4 Setup kernel configuration - - Configure the kernel: - - # cd /usr/src/linux - # make menuconfig - - You will go into a menu-driven system. Please select [Character - devices][Non-standard serial port support], enable the [Moxa - SmartIO support] driver with "[*]" for built-in (not "[M]"), then - select [Exit] to exit this program. - - 3.5.5 Rebuild kernel - The following are for Linux kernel rebuilding, for your - reference only. - For appropriate details, please refer to the Linux document. - - a. cd /usr/src/linux - b. make clean /* take a few minutes */ - c. make dep /* take a few minutes */ - d. make bzImage /* take probably 10-20 minutes */ - e. make install /* copy boot image to correct position */ - f. Please make sure the boot kernel (vmlinuz) is in the - correct position. - g. If you use 'lilo' utility, you should check /etc/lilo.conf - 'image' item specified the path which is the 'vmlinuz' path, - or you will load wrong (or old) boot kernel image (vmlinuz). - After checking /etc/lilo.conf, please run "lilo". - - Note that if the result of "make bzImage" is ERROR, then you have to - go back to Linux configuration Setup. Type "make menuconfig" in - directory /usr/src/linux. - - - 3.5.6 Make tty device and special file - # cd /moxa/mxser/driver - # ./msmknod - - 3.5.7 Make utility - # cd /moxa/mxser/utility - # make clean; make install - - 3.5.8 Reboot - - - - 3.6 Custom configuration - Although this driver already provides you default configuration, you - still can change the device name and major number. The instruction to - change these parameters are shown as below. - - Change Device name - ------------------ - If you'd like to use other device names instead of default naming - convention, all you have to do is to modify the internal code - within the shell script "msmknod". First, you have to open "msmknod" - by vi. Locate each line contains "ttyM" and "cum" and change them - to the device name you desired. "msmknod" creates the device names - you need next time executed. - - Change Major number - ------------------- - If major number 30 and 35 had been occupied, you may have to select - 2 free major numbers for this driver. There are 3 steps to change - major numbers. - - 3.6.1 Find free major numbers - In /proc/devices, you may find all the major numbers occupied - in the system. Please select 2 major numbers that are available. - e.g. 40, 45. - 3.6.2 Create special files - Run /moxa/mxser/driver/msmknod to create special files with - specified major numbers. - 3.6.3 Modify driver with new major number - Run vi to open /moxa/mxser/driver/mxser.c. Locate the line - contains "MXSERMAJOR". Change the content as below. - #define MXSERMAJOR 40 - #define MXSERCUMAJOR 45 - 3.6.4 Run "make clean; make install" in /moxa/mxser/driver. - - 3.7 Verify driver installation - You may refer to /var/log/messages to check the latest status - log reported by this driver whenever it's activated. - ------------------------------------------------------------------------------ -4. Utilities - There are 3 utilities contained in this driver. They are msdiag, msmon and - msterm. These 3 utilities are released in form of source code. They should - be compiled into executable file and copied into /usr/bin. - - Before using these utilities, please load driver (refer 3.4 & 3.5) and - make sure you had run the "msmknod" utility. - - msdiag - Diagnostic - -------------------- - This utility provides the function to display what Moxa Smartio/Industio - board found by driver in the system. - - msmon - Port Monitoring - ----------------------- - This utility gives the user a quick view about all the MOXA ports' - activities. One can easily learn each port's total received/transmitted - (Rx/Tx) character count since the time when the monitoring is started. - Rx/Tx throughputs per second are also reported in interval basis (e.g. - the last 5 seconds) and in average basis (since the time the monitoring - is started). You can reset all ports' count by key. <+> <-> - (plus/minus) keys to change the displaying time interval. Press - on the port, that cursor stay, to view the port's communication - parameters, signal status, and input/output queue. - - msterm - Terminal Emulation - --------------------------- - This utility provides data sending and receiving ability of all tty ports, - especially for MOXA ports. It is quite useful for testing simple - application, for example, sending AT command to a modem connected to the - port or used as a terminal for login purpose. Note that this is only a - dumb terminal emulation without handling full screen operation. - ------------------------------------------------------------------------------ -5. Setserial - - Supported Setserial parameters are listed as below. - - uart set UART type(16450-->disable FIFO, 16550A-->enable FIFO) - close_delay set the amount of time(in 1/100 of a second) that DTR - should be kept low while being closed. - closing_wait set the amount of time(in 1/100 of a second) that the - serial port should wait for data to be drained while - being closed, before the receiver is disable. - spd_hi Use 57.6kb when the application requests 38.4kb. - spd_vhi Use 115.2kb when the application requests 38.4kb. - spd_shi Use 230.4kb when the application requests 38.4kb. - spd_warp Use 460.8kb when the application requests 38.4kb. - spd_normal Use 38.4kb when the application requests 38.4kb. - spd_cust Use the custom divisor to set the speed when the - application requests 38.4kb. - divisor This option set the custom divison. - baud_base This option set the base baud rate. - ------------------------------------------------------------------------------ -6. Troubleshooting - - The boot time error messages and solutions are stated as clearly as - possible. If all the possible solutions fail, please contact our technical - support team to get more help. - - - Error msg: More than 4 Moxa Smartio/Industio family boards found. Fifth board - and after are ignored. - Solution: - To avoid this problem, please unplug fifth and after board, because Moxa - driver supports up to 4 boards. - - Error msg: Request_irq fail, IRQ(?) may be conflict with another device. - Solution: - Other PCI or ISA devices occupy the assigned IRQ. If you are not sure - which device causes the situation, please check /proc/interrupts to find - free IRQ and simply change another free IRQ for Moxa board. - - Error msg: Board #: C1xx Series(CAP=xxx) interrupt number invalid. - Solution: - Each port within the same multiport board shares the same IRQ. Please set - one IRQ (IRQ doesn't equal to zero) for one Moxa board. - - Error msg: No interrupt vector be set for Moxa ISA board(CAP=xxx). - Solution: - Moxa ISA board needs an interrupt vector.Please refer to user's manual - "Hardware Installation" chapter to set interrupt vector. - - Error msg: Couldn't install MOXA Smartio/Industio family driver! - Solution: - Load Moxa driver fail, the major number may conflict with other devices. - Please refer to previous section 3.7 to change a free major number for - Moxa driver. - - Error msg: Couldn't install MOXA Smartio/Industio family callout driver! - Solution: - Load Moxa callout driver fail, the callout device major number may - conflict with other devices. Please refer to previous section 3.7 to - change a free callout device major number for Moxa driver. - - ------------------------------------------------------------------------------ - diff --git a/Documentation/nbd.txt b/Documentation/nbd.txt deleted file mode 100644 index aeb93ffe6416..000000000000 --- a/Documentation/nbd.txt +++ /dev/null @@ -1,47 +0,0 @@ - Network Block Device (TCP version) - - What is it: With this compiled in the kernel (or as a module), Linux - can use a remote server as one of its block devices. So every time - the client computer wants to read, e.g., /dev/nb0, it sends a - request over TCP to the server, which will reply with the data read. - This can be used for stations with low disk space (or even diskless - - if you boot from floppy) to borrow disk space from another computer. - Unlike NFS, it is possible to put any filesystem on it, etc. It should - even be possible to use NBD as a root filesystem (I've never tried), - but it requires a user-level program to be in the initrd to start. - It also allows you to run block-device in user land (making server - and client physically the same computer, communicating using loopback). - - Current state: It currently works. Network block device is stable. - I originally thought that it was impossible to swap over TCP. It - turned out not to be true - swapping over TCP now works and seems - to be deadlock-free, but it requires heavy patches into Linux's - network layer. - - For more information, or to download the nbd-client and nbd-server - tools, go to http://nbd.sf.net/. - - Howto: To setup nbd, you can simply do the following: - - First, serve a device or file from a remote server: - - nbd-server - - e.g., - root@server1 # nbd-server 1234 /dev/sdb1 - - (serves sdb1 partition on TCP port 1234) - - Then, on the local (client) system: - - nbd-client /dev/nb[0-n] - - e.g., - root@client1 # nbd-client server1 1234 /dev/nb0 - - (creates the nb0 device on client1) - - The nbd kernel module need only be installed on the client - system, as the nbd-server is completely in userspace. In fact, - the nbd-server has been successfully ported to other operating - systems, including Windows. diff --git a/Documentation/networking/.gitignore b/Documentation/networking/.gitignore new file mode 100644 index 000000000000..286a5680f490 --- /dev/null +++ b/Documentation/networking/.gitignore @@ -0,0 +1 @@ +ifenslave diff --git a/Documentation/networking/dmfe.txt b/Documentation/networking/dmfe.txt index b1b7499dd9d3..8006c227fda2 100644 --- a/Documentation/networking/dmfe.txt +++ b/Documentation/networking/dmfe.txt @@ -60,6 +60,6 @@ Tobias Ringstrom : Current Maintainer Contributors: Marcelo Tosatti -Alan Cox +Alan Cox Jeff Garzik Vojtech Pavlik diff --git a/Documentation/networking/phy.txt b/Documentation/networking/phy.txt index 8df6a7b0e66c..88bb71b46da4 100644 --- a/Documentation/networking/phy.txt +++ b/Documentation/networking/phy.txt @@ -96,7 +96,7 @@ Letting the PHY Abstraction Layer do Everything static void adjust_link(struct net_device *dev); Next, you need to know the device name of the PHY connected to this device. - The name will look something like, "phy0:0", where the first number is the + The name will look something like, "0:00", where the first number is the bus id, and the second is the PHY's address on that bus. Typically, the bus is responsible for making its ID unique. diff --git a/Documentation/nmi_watchdog.txt b/Documentation/nmi_watchdog.txt index 90aa4531cb67..bf9f80a98282 100644 --- a/Documentation/nmi_watchdog.txt +++ b/Documentation/nmi_watchdog.txt @@ -69,6 +69,11 @@ to the overall system performance. On x86 nmi_watchdog is disabled by default so you have to enable it with a boot time parameter. +It's possible to disable the NMI watchdog in run-time by writing "0" to +/proc/sys/kernel/nmi_watchdog. Writing "1" to the same file will re-enable +the NMI watchdog. Notice that you still need to use "nmi_watchdog=" parameter +at boot time. + NOTE: In kernels prior to 2.4.2-ac18 the NMI-oopser is enabled unconditionally on x86 SMP boxes. diff --git a/Documentation/paride.txt b/Documentation/paride.txt deleted file mode 100644 index e4312676bdda..000000000000 --- a/Documentation/paride.txt +++ /dev/null @@ -1,417 +0,0 @@ - - Linux and parallel port IDE devices - -PARIDE v1.03 (c) 1997-8 Grant Guenther - -1. Introduction - -Owing to the simplicity and near universality of the parallel port interface -to personal computers, many external devices such as portable hard-disk, -CD-ROM, LS-120 and tape drives use the parallel port to connect to their -host computer. While some devices (notably scanners) use ad-hoc methods -to pass commands and data through the parallel port interface, most -external devices are actually identical to an internal model, but with -a parallel-port adapter chip added in. Some of the original parallel port -adapters were little more than mechanisms for multiplexing a SCSI bus. -(The Iomega PPA-3 adapter used in the ZIP drives is an example of this -approach). Most current designs, however, take a different approach. -The adapter chip reproduces a small ISA or IDE bus in the external device -and the communication protocol provides operations for reading and writing -device registers, as well as data block transfer functions. Sometimes, -the device being addressed via the parallel cable is a standard SCSI -controller like an NCR 5380. The "ditto" family of external tape -drives use the ISA replicator to interface a floppy disk controller, -which is then connected to a floppy-tape mechanism. The vast majority -of external parallel port devices, however, are now based on standard -IDE type devices, which require no intermediate controller. If one -were to open up a parallel port CD-ROM drive, for instance, one would -find a standard ATAPI CD-ROM drive, a power supply, and a single adapter -that interconnected a standard PC parallel port cable and a standard -IDE cable. It is usually possible to exchange the CD-ROM device with -any other device using the IDE interface. - -The document describes the support in Linux for parallel port IDE -devices. It does not cover parallel port SCSI devices, "ditto" tape -drives or scanners. Many different devices are supported by the -parallel port IDE subsystem, including: - - MicroSolutions backpack CD-ROM - MicroSolutions backpack PD/CD - MicroSolutions backpack hard-drives - MicroSolutions backpack 8000t tape drive - SyQuest EZ-135, EZ-230 & SparQ drives - Avatar Shark - Imation Superdisk LS-120 - Maxell Superdisk LS-120 - FreeCom Power CD - Hewlett-Packard 5GB and 8GB tape drives - Hewlett-Packard 7100 and 7200 CD-RW drives - -as well as most of the clone and no-name products on the market. - -To support such a wide range of devices, PARIDE, the parallel port IDE -subsystem, is actually structured in three parts. There is a base -paride module which provides a registry and some common methods for -accessing the parallel ports. The second component is a set of -high-level drivers for each of the different types of supported devices: - - pd IDE disk - pcd ATAPI CD-ROM - pf ATAPI disk - pt ATAPI tape - pg ATAPI generic - -(Currently, the pg driver is only used with CD-R drives). - -The high-level drivers function according to the relevant standards. -The third component of PARIDE is a set of low-level protocol drivers -for each of the parallel port IDE adapter chips. Thanks to the interest -and encouragement of Linux users from many parts of the world, -support is available for almost all known adapter protocols: - - aten ATEN EH-100 (HK) - bpck Microsolutions backpack (US) - comm DataStor (old-type) "commuter" adapter (TW) - dstr DataStor EP-2000 (TW) - epat Shuttle EPAT (UK) - epia Shuttle EPIA (UK) - fit2 FIT TD-2000 (US) - fit3 FIT TD-3000 (US) - friq Freecom IQ cable (DE) - frpw Freecom Power (DE) - kbic KingByte KBIC-951A and KBIC-971A (TW) - ktti KT Technology PHd adapter (SG) - on20 OnSpec 90c20 (US) - on26 OnSpec 90c26 (US) - - -2. Using the PARIDE subsystem - -While configuring the Linux kernel, you may choose either to build -the PARIDE drivers into your kernel, or to build them as modules. - -In either case, you will need to select "Parallel port IDE device support" -as well as at least one of the high-level drivers and at least one -of the parallel port communication protocols. If you do not know -what kind of parallel port adapter is used in your drive, you could -begin by checking the file names and any text files on your DOS -installation floppy. Alternatively, you can look at the markings on -the adapter chip itself. That's usually sufficient to identify the -correct device. - -You can actually select all the protocol modules, and allow the PARIDE -subsystem to try them all for you. - -For the "brand-name" products listed above, here are the protocol -and high-level drivers that you would use: - - Manufacturer Model Driver Protocol - - MicroSolutions CD-ROM pcd bpck - MicroSolutions PD drive pf bpck - MicroSolutions hard-drive pd bpck - MicroSolutions 8000t tape pt bpck - SyQuest EZ, SparQ pd epat - Imation Superdisk pf epat - Maxell Superdisk pf friq - Avatar Shark pd epat - FreeCom CD-ROM pcd frpw - Hewlett-Packard 5GB Tape pt epat - Hewlett-Packard 7200e (CD) pcd epat - Hewlett-Packard 7200e (CD-R) pg epat - -2.1 Configuring built-in drivers - -We recommend that you get to know how the drivers work and how to -configure them as loadable modules, before attempting to compile a -kernel with the drivers built-in. - -If you built all of your PARIDE support directly into your kernel, -and you have just a single parallel port IDE device, your kernel should -locate it automatically for you. If you have more than one device, -you may need to give some command line options to your bootloader -(eg: LILO), how to do that is beyond the scope of this document. - -The high-level drivers accept a number of command line parameters, all -of which are documented in the source files in linux/drivers/block/paride. -By default, each driver will automatically try all parallel ports it -can find, and all protocol types that have been installed, until it finds -a parallel port IDE adapter. Once it finds one, the probe stops. So, -if you have more than one device, you will need to tell the drivers -how to identify them. This requires specifying the port address, the -protocol identification number and, for some devices, the drive's -chain ID. While your system is booting, a number of messages are -displayed on the console. Like all such messages, they can be -reviewed with the 'dmesg' command. Among those messages will be -some lines like: - - paride: bpck registered as protocol 0 - paride: epat registered as protocol 1 - -The numbers will always be the same until you build a new kernel with -different protocol selections. You should note these numbers as you -will need them to identify the devices. - -If you happen to be using a MicroSolutions backpack device, you will -also need to know the unit ID number for each drive. This is usually -the last two digits of the drive's serial number (but read MicroSolutions' -documentation about this). - -As an example, let's assume that you have a MicroSolutions PD/CD drive -with unit ID number 36 connected to the parallel port at 0x378, a SyQuest -EZ-135 connected to the chained port on the PD/CD drive and also an -Imation Superdisk connected to port 0x278. You could give the following -options on your boot command: - - pd.drive0=0x378,1 pf.drive0=0x278,1 pf.drive1=0x378,0,36 - -In the last option, pf.drive1 configures device /dev/pf1, the 0x378 -is the parallel port base address, the 0 is the protocol registration -number and 36 is the chain ID. - -Please note: while PARIDE will work both with and without the -PARPORT parallel port sharing system that is included by the -"Parallel port support" option, PARPORT must be included and enabled -if you want to use chains of devices on the same parallel port. - -2.2 Loading and configuring PARIDE as modules - -It is much faster and simpler to get to understand the PARIDE drivers -if you use them as loadable kernel modules. - -Note 1: using these drivers with the "kerneld" automatic module loading -system is not recommended for beginners, and is not documented here. - -Note 2: if you build PARPORT support as a loadable module, PARIDE must -also be built as loadable modules, and PARPORT must be loaded before the -PARIDE modules. - -To use PARIDE, you must begin by - - insmod paride - -this loads a base module which provides a registry for the protocols, -among other tasks. - -Then, load as many of the protocol modules as you think you might need. -As you load each module, it will register the protocols that it supports, -and print a log message to your kernel log file and your console. For -example: - - # insmod epat - paride: epat registered as protocol 0 - # insmod kbic - paride: k951 registered as protocol 1 - paride: k971 registered as protocol 2 - -Finally, you can load high-level drivers for each kind of device that -you have connected. By default, each driver will autoprobe for a single -device, but you can support up to four similar devices by giving their -individual co-ordinates when you load the driver. - -For example, if you had two no-name CD-ROM drives both using the -KingByte KBIC-951A adapter, one on port 0x378 and the other on 0x3bc -you could give the following command: - - # insmod pcd drive0=0x378,1 drive1=0x3bc,1 - -For most adapters, giving a port address and protocol number is sufficient, -but check the source files in linux/drivers/block/paride for more -information. (Hopefully someone will write some man pages one day !). - -As another example, here's what happens when PARPORT is installed, and -a SyQuest EZ-135 is attached to port 0x378: - - # insmod paride - paride: version 1.0 installed - # insmod epat - paride: epat registered as protocol 0 - # insmod pd - pd: pd version 1.0, major 45, cluster 64, nice 0 - pda: Sharing parport1 at 0x378 - pda: epat 1.0, Shuttle EPAT chip c3 at 0x378, mode 5 (EPP-32), delay 1 - pda: SyQuest EZ135A, 262144 blocks [128M], (512/16/32), removable media - pda: pda1 - -Note that the last line is the output from the generic partition table -scanner - in this case it reports that it has found a disk with one partition. - -2.3 Using a PARIDE device - -Once the drivers have been loaded, you can access PARIDE devices in the -same way as their traditional counterparts. You will probably need to -create the device "special files". Here is a simple script that you can -cut to a file and execute: - -#!/bin/bash -# -# mkd -- a script to create the device special files for the PARIDE subsystem -# -function mkdev { - mknod $1 $2 $3 $4 ; chmod 0660 $1 ; chown root:disk $1 -} -# -function pd { - D=$( printf \\$( printf "x%03x" $[ $1 + 97 ] ) ) - mkdev pd$D b 45 $[ $1 * 16 ] - for P in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - do mkdev pd$D$P b 45 $[ $1 * 16 + $P ] - done -} -# -cd /dev -# -for u in 0 1 2 3 ; do pd $u ; done -for u in 0 1 2 3 ; do mkdev pcd$u b 46 $u ; done -for u in 0 1 2 3 ; do mkdev pf$u b 47 $u ; done -for u in 0 1 2 3 ; do mkdev pt$u c 96 $u ; done -for u in 0 1 2 3 ; do mkdev npt$u c 96 $[ $u + 128 ] ; done -for u in 0 1 2 3 ; do mkdev pg$u c 97 $u ; done -# -# end of mkd - -With the device files and drivers in place, you can access PARIDE devices -like any other Linux device. For example, to mount a CD-ROM in pcd0, use: - - mount /dev/pcd0 /cdrom - -If you have a fresh Avatar Shark cartridge, and the drive is pda, you -might do something like: - - fdisk /dev/pda -- make a new partition table with - partition 1 of type 83 - - mke2fs /dev/pda1 -- to build the file system - - mkdir /shark -- make a place to mount the disk - - mount /dev/pda1 /shark - -Devices like the Imation superdisk work in the same way, except that -they do not have a partition table. For example to make a 120MB -floppy that you could share with a DOS system: - - mkdosfs /dev/pf0 - mount /dev/pf0 /mnt - - -2.4 The pf driver - -The pf driver is intended for use with parallel port ATAPI disk -devices. The most common devices in this category are PD drives -and LS-120 drives. Traditionally, media for these devices are not -partitioned. Consequently, the pf driver does not support partitioned -media. This may be changed in a future version of the driver. - -2.5 Using the pt driver - -The pt driver for parallel port ATAPI tape drives is a minimal driver. -It does not yet support many of the standard tape ioctl operations. -For best performance, a block size of 32KB should be used. You will -probably want to set the parallel port delay to 0, if you can. - -2.6 Using the pg driver - -The pg driver can be used in conjunction with the cdrecord program -to create CD-ROMs. Please get cdrecord version 1.6.1 or later -from ftp://ftp.fokus.gmd.de/pub/unix/cdrecord/ . To record CD-R media -your parallel port should ideally be set to EPP mode, and the "port delay" -should be set to 0. With those settings it is possible to record at 2x -speed without any buffer underruns. If you cannot get the driver to work -in EPP mode, try to use "bidirectional" or "PS/2" mode and 1x speeds only. - - -3. Troubleshooting - -3.1 Use EPP mode if you can - -The most common problems that people report with the PARIDE drivers -concern the parallel port CMOS settings. At this time, none of the -PARIDE protocol modules support ECP mode, or any ECP combination modes. -If you are able to do so, please set your parallel port into EPP mode -using your CMOS setup procedure. - -3.2 Check the port delay - -Some parallel ports cannot reliably transfer data at full speed. To -offset the errors, the PARIDE protocol modules introduce a "port -delay" between each access to the i/o ports. Each protocol sets -a default value for this delay. In most cases, the user can override -the default and set it to 0 - resulting in somewhat higher transfer -rates. In some rare cases (especially with older 486 systems) the -default delays are not long enough. if you experience corrupt data -transfers, or unexpected failures, you may wish to increase the -port delay. The delay can be programmed using the "driveN" parameters -to each of the high-level drivers. Please see the notes above, or -read the comments at the beginning of the driver source files in -linux/drivers/block/paride. - -3.3 Some drives need a printer reset - -There appear to be a number of "noname" external drives on the market -that do not always power up correctly. We have noticed this with some -drives based on OnSpec and older Freecom adapters. In these rare cases, -the adapter can often be reinitialised by issuing a "printer reset" on -the parallel port. As the reset operation is potentially disruptive in -multiple device environments, the PARIDE drivers will not do it -automatically. You can however, force a printer reset by doing: - - insmod lp reset=1 - rmmod lp - -If you have one of these marginal cases, you should probably build -your paride drivers as modules, and arrange to do the printer reset -before loading the PARIDE drivers. - -3.4 Use the verbose option and dmesg if you need help - -While a lot of testing has gone into these drivers to make them work -as smoothly as possible, problems will arise. If you do have problems, -please check all the obvious things first: does the drive work in -DOS with the manufacturer's drivers ? If that doesn't yield any useful -clues, then please make sure that only one drive is hooked to your system, -and that either (a) PARPORT is enabled or (b) no other device driver -is using your parallel port (check in /proc/ioports). Then, load the -appropriate drivers (you can load several protocol modules if you want) -as in: - - # insmod paride - # insmod epat - # insmod bpck - # insmod kbic - ... - # insmod pd verbose=1 - -(using the correct driver for the type of device you have, of course). -The verbose=1 parameter will cause the drivers to log a trace of their -activity as they attempt to locate your drive. - -Use 'dmesg' to capture a log of all the PARIDE messages (any messages -beginning with paride:, a protocol module's name or a driver's name) and -include that with your bug report. You can submit a bug report in one -of two ways. Either send it directly to the author of the PARIDE suite, -by e-mail to grant@torque.net, or join the linux-parport mailing list -and post your report there. - -3.5 For more information or help - -You can join the linux-parport mailing list by sending a mail message -to - linux-parport-request@torque.net - -with the single word - - subscribe - -in the body of the mail message (not in the subject line). Please be -sure that your mail program is correctly set up when you do this, as -the list manager is a robot that will subscribe you using the reply -address in your mail headers. REMOVE any anti-spam gimmicks you may -have in your mail headers, when sending mail to the list server. - -You might also find some useful information on the linux-parport -web pages (although they are not always up to date) at - - http://www.torque.net/parport/ - - diff --git a/Documentation/pcmcia/.gitignore b/Documentation/pcmcia/.gitignore new file mode 100644 index 000000000000..53d081336757 --- /dev/null +++ b/Documentation/pcmcia/.gitignore @@ -0,0 +1 @@ +crc32hash diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index 02ea9a971b8e..0ab0230cbcb0 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -41,25 +41,14 @@ Table of Contents VI - System-on-a-chip devices and nodes 1) Defining child nodes of an SOC 2) Representing devices without a current OF specification - a) MDIO IO device - b) Gianfar-compatible ethernet nodes - c) PHY nodes - d) Interrupt controllers - e) I2C - f) Freescale SOC USB controllers - g) Freescale SOC SEC Security Engines - h) Board Control and Status (BCSR) - i) Freescale QUICC Engine module (QE) - j) CFI or JEDEC memory-mapped NOR flash - k) Global Utilities Block - l) Freescale Communications Processor Module - m) Chipselect/Local Bus - n) 4xx/Axon EMAC ethernet nodes - o) Xilinx IP cores - p) Freescale Synchronous Serial Interface - q) USB EHCI controllers - r) MDIO on GPIOs - s) SPI busses + a) PHY nodes + b) Interrupt controllers + c) CFI or JEDEC memory-mapped NOR flash + d) 4xx/Axon EMAC ethernet nodes + e) Xilinx IP cores + f) USB EHCI controllers + g) MDIO on GPIOs + h) SPI busses VII - Marvell Discovery mv64[345]6x System Controller chips 1) The /system-controller node @@ -1830,41 +1819,7 @@ platforms are moved over to use the flattened-device-tree model. big-endian; }; - r) Freescale Display Interface Unit - - The Freescale DIU is a LCD controller, with proper hardware, it can also - drive DVI monitors. - - Required properties: - - compatible : should be "fsl-diu". - - reg : should contain at least address and length of the DIU register - set. - - Interrupts : one DIU interrupt should be describe here. - - Example (MPC8610HPCD) - display@2c000 { - compatible = "fsl,diu"; - reg = <0x2c000 100>; - interrupts = <72 2>; - interrupt-parent = <&mpic>; - }; - - s) Freescale on board FPGA - - This is the memory-mapped registers for on board FPGA. - - Required properities: - - compatible : should be "fsl,fpga-pixis". - - reg : should contain the address and the lenght of the FPPGA register - set. - - Example (MPC8610HPCD) - board-control@e8000000 { - compatible = "fsl,fpga-pixis"; - reg = <0xe8000000 32>; - }; - - r) MDIO on GPIOs + g) MDIO on GPIOs Currently defined compatibles: - virtual,gpio-mdio @@ -1884,7 +1839,7 @@ platforms are moved over to use the flattened-device-tree model. &qe_pio_c 6>; }; - s) SPI (Serial Peripheral Interface) busses + h) SPI (Serial Peripheral Interface) busses SPI busses can be described with a node for the SPI master device and a set of child nodes for each SPI slave on the bus. For this diff --git a/Documentation/printk-formats.txt b/Documentation/printk-formats.txt new file mode 100644 index 000000000000..1b5a5ddbc3ef --- /dev/null +++ b/Documentation/printk-formats.txt @@ -0,0 +1,35 @@ +If variable is of Type, use printk format specifier: +--------------------------------------------------------- + int %d or %x + unsigned int %u or %x + long %ld or %lx + unsigned long %lu or %lx + long long %lld or %llx + unsigned long long %llu or %llx + size_t %zu or %zx + ssize_t %zd or %zx + +Raw pointer value SHOULD be printed with %p. + +u64 SHOULD be printed with %llu/%llx, (unsigned long long): + + printk("%llu", (unsigned long long)u64_var); + +s64 SHOULD be printed with %lld/%llx, (long long): + + printk("%lld", (long long)s64_var); + +If is dependent on a config option for its size (e.g., sector_t, +blkcnt_t, phys_addr_t, resource_size_t) or is architecture-dependent +for its size (e.g., tcflag_t), use a format specifier of its largest +possible type and explicitly cast to it. Example: + + printk("test: sector number/total blocks: %llu/%llu\n", + (unsigned long long)sector, (unsigned long long)blockcount); + +Reminder: sizeof() result is of type size_t. + +Thank you for your cooperation and attention. + + +By Randy Dunlap diff --git a/Documentation/ramdisk.txt b/Documentation/ramdisk.txt deleted file mode 100644 index 6c820baa19a6..000000000000 --- a/Documentation/ramdisk.txt +++ /dev/null @@ -1,165 +0,0 @@ -Using the RAM disk block device with Linux ------------------------------------------- - -Contents: - - 1) Overview - 2) Kernel Command Line Parameters - 3) Using "rdev -r" - 4) An Example of Creating a Compressed RAM Disk - - -1) Overview ------------ - -The RAM disk driver is a way to use main system memory as a block device. It -is required for initrd, an initial filesystem used if you need to load modules -in order to access the root filesystem (see Documentation/initrd.txt). It can -also be used for a temporary filesystem for crypto work, since the contents -are erased on reboot. - -The RAM disk dynamically grows as more space is required. It does this by using -RAM from the buffer cache. The driver marks the buffers it is using as dirty -so that the VM subsystem does not try to reclaim them later. - -The RAM disk supports up to 16 RAM disks by default, and can be reconfigured -to support an unlimited number of RAM disks (at your own risk). Just change -the configuration symbol BLK_DEV_RAM_COUNT in the Block drivers config menu -and (re)build the kernel. - -To use RAM disk support with your system, run './MAKEDEV ram' from the /dev -directory. RAM disks are all major number 1, and start with minor number 0 -for /dev/ram0, etc. If used, modern kernels use /dev/ram0 for an initrd. - -The new RAM disk also has the ability to load compressed RAM disk images, -allowing one to squeeze more programs onto an average installation or -rescue floppy disk. - - -2) Kernel Command Line Parameters ---------------------------------- - - ramdisk_size=N - ============== - -This parameter tells the RAM disk driver to set up RAM disks of N k size. The -default is 4096 (4 MB) (8192 (8 MB) on S390). - - ramdisk_blocksize=N - =================== - -This parameter tells the RAM disk driver how many bytes to use per block. The -default is 1024 (BLOCK_SIZE). - - -3) Using "rdev -r" ------------------- - -The usage of the word (two bytes) that "rdev -r" sets in the kernel image is -as follows. The low 11 bits (0 -> 10) specify an offset (in 1 k blocks) of up -to 2 MB (2^11) of where to find the RAM disk (this used to be the size). Bit -14 indicates that a RAM disk is to be loaded, and bit 15 indicates whether a -prompt/wait sequence is to be given before trying to read the RAM disk. Since -the RAM disk dynamically grows as data is being written into it, a size field -is not required. Bits 11 to 13 are not currently used and may as well be zero. -These numbers are no magical secrets, as seen below: - -./arch/i386/kernel/setup.c:#define RAMDISK_IMAGE_START_MASK 0x07FF -./arch/i386/kernel/setup.c:#define RAMDISK_PROMPT_FLAG 0x8000 -./arch/i386/kernel/setup.c:#define RAMDISK_LOAD_FLAG 0x4000 - -Consider a typical two floppy disk setup, where you will have the -kernel on disk one, and have already put a RAM disk image onto disk #2. - -Hence you want to set bits 0 to 13 as 0, meaning that your RAM disk -starts at an offset of 0 kB from the beginning of the floppy. -The command line equivalent is: "ramdisk_start=0" - -You want bit 14 as one, indicating that a RAM disk is to be loaded. -The command line equivalent is: "load_ramdisk=1" - -You want bit 15 as one, indicating that you want a prompt/keypress -sequence so that you have a chance to switch floppy disks. -The command line equivalent is: "prompt_ramdisk=1" - -Putting that together gives 2^15 + 2^14 + 0 = 49152 for an rdev word. -So to create disk one of the set, you would do: - - /usr/src/linux# cat arch/i386/boot/zImage > /dev/fd0 - /usr/src/linux# rdev /dev/fd0 /dev/fd0 - /usr/src/linux# rdev -r /dev/fd0 49152 - -If you make a boot disk that has LILO, then for the above, you would use: - append = "ramdisk_start=0 load_ramdisk=1 prompt_ramdisk=1" -Since the default start = 0 and the default prompt = 1, you could use: - append = "load_ramdisk=1" - - -4) An Example of Creating a Compressed RAM Disk ----------------------------------------------- - -To create a RAM disk image, you will need a spare block device to -construct it on. This can be the RAM disk device itself, or an -unused disk partition (such as an unmounted swap partition). For this -example, we will use the RAM disk device, "/dev/ram0". - -Note: This technique should not be done on a machine with less than 8 MB -of RAM. If using a spare disk partition instead of /dev/ram0, then this -restriction does not apply. - -a) Decide on the RAM disk size that you want. Say 2 MB for this example. - Create it by writing to the RAM disk device. (This step is not currently - required, but may be in the future.) It is wise to zero out the - area (esp. for disks) so that maximal compression is achieved for - the unused blocks of the image that you are about to create. - - dd if=/dev/zero of=/dev/ram0 bs=1k count=2048 - -b) Make a filesystem on it. Say ext2fs for this example. - - mke2fs -vm0 /dev/ram0 2048 - -c) Mount it, copy the files you want to it (eg: /etc/* /dev/* ...) - and unmount it again. - -d) Compress the contents of the RAM disk. The level of compression - will be approximately 50% of the space used by the files. Unused - space on the RAM disk will compress to almost nothing. - - dd if=/dev/ram0 bs=1k count=2048 | gzip -v9 > /tmp/ram_image.gz - -e) Put the kernel onto the floppy - - dd if=zImage of=/dev/fd0 bs=1k - -f) Put the RAM disk image onto the floppy, after the kernel. Use an offset - that is slightly larger than the kernel, so that you can put another - (possibly larger) kernel onto the same floppy later without overlapping - the RAM disk image. An offset of 400 kB for kernels about 350 kB in - size would be reasonable. Make sure offset+size of ram_image.gz is - not larger than the total space on your floppy (usually 1440 kB). - - dd if=/tmp/ram_image.gz of=/dev/fd0 bs=1k seek=400 - -g) Use "rdev" to set the boot device, RAM disk offset, prompt flag, etc. - For prompt_ramdisk=1, load_ramdisk=1, ramdisk_start=400, one would - have 2^15 + 2^14 + 400 = 49552. - - rdev /dev/fd0 /dev/fd0 - rdev -r /dev/fd0 49552 - -That is it. You now have your boot/root compressed RAM disk floppy. Some -users may wish to combine steps (d) and (f) by using a pipe. - --------------------------------------------------------------------------- - Paul Gortmaker 12/95 - -Changelog: ----------- - -10-22-04 : Updated to reflect changes in command line options, remove - obsolete references, general cleanup. - James Nelson (james4765@gmail.com) - - -12-95 : Original Document diff --git a/Documentation/riscom8.txt b/Documentation/riscom8.txt deleted file mode 100644 index 14f61fdad7ca..000000000000 --- a/Documentation/riscom8.txt +++ /dev/null @@ -1,36 +0,0 @@ -* NOTE - this is an unmaintained driver. The original author cannot be located. - -SDL Communications is now SBS Technologies, and does not have any -information on these ancient ISA cards on their website. - -James Nelson - 12-12-2004 - - This is the README for RISCom/8 multi-port serial driver - (C) 1994-1996 D.Gorodchanin - See file LICENSE for terms and conditions. - -NOTE: English is not my native language. - I'm sorry for any mistakes in this text. - -Misc. notes for RISCom/8 serial driver, in no particular order :) - -1) This driver can support up to 4 boards at time. - Use string "riscom8=0xXXX,0xXXX,0xXXX,0xXXX" at LILO prompt, for - setting I/O base addresses for boards. If you compile driver - as module use modprobe options "iobase=0xXXX iobase1=0xXXX iobase2=..." - -2) The driver partially supports famous 'setserial' program, you can use almost - any of its options, excluding port & irq settings. - -3) There are some misc. defines at the beginning of riscom8.c, please read the - comments and try to change some of them in case of problems. - -4) I consider the current state of the driver as BETA. - -5) SDL Communications WWW page is http://www.sdlcomm.com. - -6) You can use the MAKEDEV program to create RISCom/8 /dev/ttyL* entries. - -7) Minor numbers for first board are 0-7, for second 8-15, etc. - -22 Apr 1996. diff --git a/Documentation/rocket.txt b/Documentation/rocket.txt deleted file mode 100644 index 1d8582990435..000000000000 --- a/Documentation/rocket.txt +++ /dev/null @@ -1,189 +0,0 @@ -Comtrol(tm) RocketPort(R)/RocketModem(TM) Series -Device Driver for the Linux Operating System - -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- - -PRODUCT OVERVIEW ----------------- - -This driver provides a loadable kernel driver for the Comtrol RocketPort -and RocketModem PCI boards. These boards provide, 2, 4, 8, 16, or 32 -high-speed serial ports or modems. This driver supports up to a combination -of four RocketPort or RocketModems boards in one machine simultaneously. -This file assumes that you are using the RocketPort driver which is -integrated into the kernel sources. - -The driver can also be installed as an external module using the usual -"make;make install" routine. This external module driver, obtainable -from the Comtrol website listed below, is useful for updating the driver -or installing it into kernels which do not have the driver configured -into them. Installations instructions for the external module -are in the included README and HW_INSTALL files. - -RocketPort ISA and RocketModem II PCI boards currently are only supported by -this driver in module form. - -The RocketPort ISA board requires I/O ports to be configured by the DIP -switches on the board. See the section "ISA Rocketport Boards" below for -information on how to set the DIP switches. - -You pass the I/O port to the driver using the following module parameters: - -board1 : I/O port for the first ISA board -board2 : I/O port for the second ISA board -board3 : I/O port for the third ISA board -board4 : I/O port for the fourth ISA board - -There is a set of utilities and scripts provided with the external driver -( downloadable from http://www.comtrol.com ) that ease the configuration and -setup of the ISA cards. - -The RocketModem II PCI boards require firmware to be loaded into the card -before it will function. The driver has only been tested as a module for this -board. - -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- - -INSTALLATION PROCEDURES ------------------------ - -RocketPort/RocketModem PCI cards require no driver configuration, they are -automatically detected and configured. - -The RocketPort driver can be installed as a module (recommended) or built -into the kernel. This is selected, as for other drivers, through the `make config` -command from the root of the Linux source tree during the kernel build process. - -The RocketPort/RocketModem serial ports installed by this driver are assigned -device major number 46, and will be named /dev/ttyRx, where x is the port number -starting at zero (ex. /dev/ttyR0, /devttyR1, ...). If you have multiple cards -installed in the system, the mapping of port names to serial ports is displayed -in the system log at /var/log/messages. - -If installed as a module, the module must be loaded. This can be done -manually by entering "modprobe rocket". To have the module loaded automatically -upon system boot, edit the /etc/modprobe.conf file and add the line -"alias char-major-46 rocket". - -In order to use the ports, their device names (nodes) must be created with mknod. -This is only required once, the system will retain the names once created. To -create the RocketPort/RocketModem device names, use the command -"mknod /dev/ttyRx c 46 x" where x is the port number starting at zero. For example: - ->mknod /dev/ttyR0 c 46 0 ->mknod /dev/ttyR1 c 46 1 ->mknod /dev/ttyR2 c 46 2 - -The Linux script MAKEDEV will create the first 16 ttyRx device names (nodes) -for you: - ->/dev/MAKEDEV ttyR - -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- - -ISA Rocketport Boards ---------------------- - -You must assign and configure the I/O addresses used by the ISA Rocketport -card before installing and using it. This is done by setting a set of DIP -switches on the Rocketport board. - - -SETTING THE I/O ADDRESS ------------------------ - -Before installing RocketPort(R) or RocketPort RA boards, you must find -a range of I/O addresses for it to use. The first RocketPort card -requires a 68-byte contiguous block of I/O addresses, starting at one -of the following: 0x100h, 0x140h, 0x180h, 0x200h, 0x240h, 0x280h, -0x300h, 0x340h, 0x380h. This I/O address must be reflected in the DIP -switches of *all* of the Rocketport cards. - -The second, third, and fourth RocketPort cards require a 64-byte -contiguous block of I/O addresses, starting at one of the following -I/O addresses: 0x100h, 0x140h, 0x180h, 0x1C0h, 0x200h, 0x240h, 0x280h, -0x2C0h, 0x300h, 0x340h, 0x380h, 0x3C0h. The I/O address used by the -second, third, and fourth Rocketport cards (if present) are set via -software control. The DIP switch settings for the I/O address must be -set to the value of the first Rocketport cards. - -In order to distinguish each of the card from the others, each card -must have a unique board ID set on the dip switches. The first -Rocketport board must be set with the DIP switches corresponding to -the first board, the second board must be set with the DIP switches -corresponding to the second board, etc. IMPORTANT: The board ID is -the only place where the DIP switch settings should differ between the -various Rocketport boards in a system. - -The I/O address range used by any of the RocketPort cards must not -conflict with any other cards in the system, including other -RocketPort cards. Below, you will find a list of commonly used I/O -address ranges which may be in use by other devices in your system. -On a Linux system, "cat /proc/ioports" will also be helpful in -identifying what I/O addresses are being used by devices on your -system. - -Remember, the FIRST RocketPort uses 68 I/O addresses. So, if you set it -for 0x100, it will occupy 0x100 to 0x143. This would mean that you -CAN NOT set the second, third or fourth board for address 0x140 since -the first 4 bytes of that range are used by the first board. You would -need to set the second, third, or fourth board to one of the next available -blocks such as 0x180. - -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- - -RocketPort and RocketPort RA SW1 Settings: - - +-------------------------------+ - | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | - +-------+-------+---------------+ - | Unused| Card | I/O Port Block| - +-------------------------------+ - -DIP Switches DIP Switches -7 8 6 5 -=================== =================== -On On UNUSED, MUST BE ON. On On First Card <==== Default - On Off Second Card - Off On Third Card - Off Off Fourth Card - -DIP Switches I/O Address Range -4 3 2 1 Used by the First Card -===================================== -On Off On Off 100-143 -On Off Off On 140-183 -On Off Off Off 180-1C3 <==== Default -Off On On Off 200-243 -Off On Off On 240-283 -Off On Off Off 280-2C3 -Off Off On Off 300-343 -Off Off Off On 340-383 -Off Off Off Off 380-3C3 - -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- - -REPORTING BUGS --------------- - -For technical support, please provide the following -information: Driver version, kernel release, distribution of -kernel, and type of board you are using. Error messages and log -printouts port configuration details are especially helpful. - -USA - Phone: (612) 494-4100 - FAX: (612) 494-4199 - email: support@comtrol.com - -Comtrol Europe - Phone: +44 (0) 1 869 323-220 - FAX: +44 (0) 1 869 323-211 - email: support@comtrol.co.uk - -Web: http://www.comtrol.com -FTP: ftp.comtrol.com - -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- - - diff --git a/Documentation/scheduler/00-INDEX b/Documentation/scheduler/00-INDEX index fc234d093fbf..aabcc3a089ba 100644 --- a/Documentation/scheduler/00-INDEX +++ b/Documentation/scheduler/00-INDEX @@ -4,8 +4,6 @@ sched-arch.txt - CPU Scheduler implementation hints for architecture specific code. sched-coding.txt - reference for various scheduler-related methods in the O(1) scheduler. -sched-design.txt - - goals, design and implementation of the Linux O(1) scheduler. sched-design-CFS.txt - goals, design and implementation of the Complete Fair Scheduler. sched-domains.txt diff --git a/Documentation/scheduler/sched-design-CFS.txt b/Documentation/scheduler/sched-design-CFS.txt index 9d8eb553884c..eb471c7a905e 100644 --- a/Documentation/scheduler/sched-design-CFS.txt +++ b/Documentation/scheduler/sched-design-CFS.txt @@ -92,7 +92,7 @@ other HZ detail. Thus the CFS scheduler has no notion of "timeslices" in the way the previous scheduler had, and has no heuristics whatsoever. There is only one central tunable (you have to switch on CONFIG_SCHED_DEBUG): - /proc/sys/kernel/sched_granularity_ns + /proc/sys/kernel/sched_min_granularity_ns which can be used to tune the scheduler from "desktop" (i.e., low latencies) to "server" (i.e., good batching) workloads. It defaults to a setting suitable diff --git a/Documentation/scsi/aacraid.txt b/Documentation/scsi/aacraid.txt index 709ca991a451..ddace3afc83b 100644 --- a/Documentation/scsi/aacraid.txt +++ b/Documentation/scsi/aacraid.txt @@ -128,7 +128,7 @@ Supported Cards/Chipsets People ------------------------- -Alan Cox +Alan Cox Christoph Hellwig (updates for new-style PCI probing and SCSI host registration, small cleanups/fixes) Matt Domsch (revision ioctl, adapter messages) diff --git a/Documentation/serial/00-INDEX b/Documentation/serial/00-INDEX new file mode 100644 index 000000000000..07dcdb0d2a36 --- /dev/null +++ b/Documentation/serial/00-INDEX @@ -0,0 +1,24 @@ +00-INDEX + - this file. +README.cycladesZ + - info on Cyclades-Z firmware loading. +computone.txt + - info on Computone Intelliport II/Plus Multiport Serial Driver. +digiepca.txt + - info on Digi Intl. {PC,PCI,EISA}Xx and Xem series cards. +hayes-esp.txt + - info on using the Hayes ESP serial driver. +moxa-smartio + - file with info on installing/using Moxa multiport serial driver. +riscom8.txt + - notes on using the RISCom/8 multi-port serial driver. +rocket.txt + - info on the Comtrol RocketPort multiport serial driver. +specialix.txt + - info on hardware/driver for specialix IO8+ multiport serial card. +stallion.txt + - info on using the Stallion multiport serial driver. +sx.txt + - info on the Specialix SX/SI multiport serial driver. +tty.txt + - guide to the locking policies of the tty layer. diff --git a/Documentation/serial/README.cycladesZ b/Documentation/serial/README.cycladesZ new file mode 100644 index 000000000000..024a69443cc2 --- /dev/null +++ b/Documentation/serial/README.cycladesZ @@ -0,0 +1,8 @@ + +The Cyclades-Z must have firmware loaded onto the card before it will +operate. This operation should be performed during system startup, + +The firmware, loader program and the latest device driver code are +available from Cyclades at + ftp://ftp.cyclades.com/pub/cyclades/cyclades-z/linux/ + diff --git a/Documentation/serial/computone.txt b/Documentation/serial/computone.txt new file mode 100644 index 000000000000..c57ea4781e5d --- /dev/null +++ b/Documentation/serial/computone.txt @@ -0,0 +1,522 @@ +NOTE: This is an unmaintained driver. It is not guaranteed to work due to +changes made in the tty layer in 2.6. If you wish to take over maintenance of +this driver, contact Michael Warfield . + +Changelog: +---------- +11-01-2001: Original Document + +10-29-2004: Minor misspelling & format fix, update status of driver. + James Nelson + +Computone Intelliport II/Plus Multiport Serial Driver +----------------------------------------------------- + +Release Notes For Linux Kernel 2.2 and higher. +These notes are for the drivers which have already been integrated into the +kernel and have been tested on Linux kernels 2.0, 2.2, 2.3, and 2.4. + +Version: 1.2.14 +Date: 11/01/2001 +Historical Author: Andrew Manison +Primary Author: Doug McNash +Support: support@computone.com +Fixes and Updates: Mike Warfield + +This file assumes that you are using the Computone drivers which are +integrated into the kernel sources. For updating the drivers or installing +drivers into kernels which do not already have Computone drivers, please +refer to the instructions in the README.computone file in the driver patch. + + +1. INTRODUCTION + +This driver supports the entire family of Intelliport II/Plus controllers +with the exception of the MicroChannel controllers. It does not support +products previous to the Intelliport II. + +This driver was developed on the v2.0.x Linux tree and has been tested up +to v2.4.14; it will probably not work with earlier v1.X kernels,. + + +2. QUICK INSTALLATION + +Hardware - If you have an ISA card, find a free interrupt and io port. + List those in use with `cat /proc/interrupts` and + `cat /proc/ioports`. Set the card dip switches to a free + address. You may need to configure your BIOS to reserve an + irq for an ISA card. PCI and EISA parameters are set + automagically. Insert card into computer with the power off + before or after drivers installation. + + Note the hardware address from the Computone ISA cards installed into + the system. These are required for editing ip2.c or editing + /etc/modprobe.conf, or for specification on the modprobe + command line. + + Note that the /etc/modules.conf should be used for older (pre-2.6) + kernels. + +Software - + +Module installation: + +a) Determine free irq/address to use if any (configure BIOS if need be) +b) Run "make config" or "make menuconfig" or "make xconfig" + Select (m) module for CONFIG_COMPUTONE under character + devices. CONFIG_PCI and CONFIG_MODULES also may need to be set. +c) Set address on ISA cards then: + edit /usr/src/linux/drivers/char/ip2.c if needed + or + edit /etc/modprobe.conf if needed (module). + or both to match this setting. +d) Run "make modules" +e) Run "make modules_install" +f) Run "/sbin/depmod -a" +g) install driver using `modprobe ip2 ` (options listed below) +h) run ip2mkdev (either the script below or the binary version) + + +Kernel installation: + +a) Determine free irq/address to use if any (configure BIOS if need be) +b) Run "make config" or "make menuconfig" or "make xconfig" + Select (y) kernel for CONFIG_COMPUTONE under character + devices. CONFIG_PCI may need to be set if you have PCI bus. +c) Set address on ISA cards then: + edit /usr/src/linux/drivers/char/ip2.c + (Optional - may be specified on kernel command line now) +d) Run "make zImage" or whatever target you prefer. +e) mv /usr/src/linux/arch/i386/boot/zImage to /boot. +f) Add new config for this kernel into /etc/lilo.conf, run "lilo" + or copy to a floppy disk and boot from that floppy disk. +g) Reboot using this kernel +h) run ip2mkdev (either the script below or the binary version) + +Kernel command line options: + +When compiling the driver into the kernel, io and irq may be +compiled into the driver by editing ip2.c and setting the values for +io and irq in the appropriate array. An alternative is to specify +a command line parameter to the kernel at boot up. + + ip2=io0,irq0,io1,irq1,io2,irq2,io3,irq3 + +Note that this order is very different from the specifications for the +modload parameters which have separate IRQ and IO specifiers. + +The io port also selects PCI (1) and EISA (2) boards. + + io=0 No board + io=1 PCI board + io=2 EISA board + else ISA board io address + +You only need to specify the boards which are present. + + Examples: + + 2 PCI boards: + + ip2=1,0,1,0 + + 1 ISA board at 0x310 irq 5: + + ip2=0x310,5 + +This can be added to and "append" option in lilo.conf similar to this: + + append="ip2=1,0,1,0" + + +3. INSTALLATION + +Previously, the driver sources were packaged with a set of patch files +to update the character drivers' makefile and configuration file, and other +kernel source files. A build script (ip2build) was included which applies +the patches if needed, and build any utilities needed. +What you receive may be a single patch file in conventional kernel +patch format build script. That form can also be applied by +running patch -p1 < ThePatchFile. Otherwise run ip2build. + +The driver can be installed as a module (recommended) or built into the +kernel. This is selected as for other drivers through the `make config` +command from the root of the Linux source tree. If the driver is built +into the kernel you will need to edit the file ip2.c to match the boards +you are installing. See that file for instructions. If the driver is +installed as a module the configuration can also be specified on the +modprobe command line as follows: + + modprobe ip2 irq=irq1,irq2,irq3,irq4 io=addr1,addr2,addr3,addr4 + +where irqnum is one of the valid Intelliport II interrupts (3,4,5,7,10,11, +12,15) and addr1-4 are the base addresses for up to four controllers. If +the irqs are not specified the driver uses the default in ip2.c (which +selects polled mode). If no base addresses are specified the defaults in +ip2.c are used. If you are autoloading the driver module with kerneld or +kmod the base addresses and interrupt number must also be set in ip2.c +and recompile or just insert and options line in /etc/modprobe.conf or both. +The options line is equivalent to the command line and takes precedence over +what is in ip2.c. + +/etc/modprobe.conf sample: + options ip2 io=1,0x328 irq=1,10 + alias char-major-71 ip2 + alias char-major-72 ip2 + alias char-major-73 ip2 + +The equivalent in ip2.c: + +static int io[IP2_MAX_BOARDS]= { 1, 0x328, 0, 0 }; +static int irq[IP2_MAX_BOARDS] = { 1, 10, -1, -1 }; + +The equivalent for the kernel command line (in lilo.conf): + + append="ip2=1,1,0x328,10" + + +Note: Both io and irq should be updated to reflect YOUR system. An "io" + address of 1 or 2 indicates a PCI or EISA card in the board table. + The PCI or EISA irq will be assigned automatically. + +Specifying an invalid or in-use irq will default the driver into +running in polled mode for that card. If all irq entries are 0 then +all cards will operate in polled mode. + +If you select the driver as part of the kernel run : + + make zlilo (or whatever you do to create a bootable kernel) + +If you selected a module run : + + make modules && make modules_install + +The utility ip2mkdev (see 5 and 7 below) creates all the device nodes +required by the driver. For a device to be created it must be configured +in the driver and the board must be installed. Only devices corresponding +to real IntelliPort II ports are created. With multiple boards and expansion +boxes this will leave gaps in the sequence of device names. ip2mkdev uses +Linux tty naming conventions: ttyF0 - ttyF255 for normal devices, and +cuf0 - cuf255 for callout devices. + + +4. USING THE DRIVERS + +As noted above, the driver implements the ports in accordance with Linux +conventions, and the devices should be interchangeable with the standard +serial devices. (This is a key point for problem reporting: please make +sure that what you are trying do works on the ttySx/cuax ports first; then +tell us what went wrong with the ip2 ports!) + +Higher speeds can be obtained using the setserial utility which remaps +38,400 bps (extb) to 57,600 bps, 115,200 bps, or a custom speed. +Intelliport II installations using the PowerPort expansion module can +use the custom speed setting to select the highest speeds: 153,600 bps, +230,400 bps, 307,200 bps, 460,800bps and 921,600 bps. The base for +custom baud rate configuration is fixed at 921,600 for cards/expansion +modules with ST654's and 115200 for those with Cirrus CD1400's. This +corresponds to the maximum bit rates those chips are capable. +For example if the baud base is 921600 and the baud divisor is 18 then +the custom rate is 921600/18 = 51200 bps. See the setserial man page for +complete details. Of course if stty accepts the higher rates now you can +use that as well as the standard ioctls(). + + +5. ip2mkdev and assorted utilities... + +Several utilities, including the source for a binary ip2mkdev utility are +available under .../drivers/char/ip2. These can be build by changing to +that directory and typing "make" after the kernel has be built. If you do +not wish to compile the binary utilities, the shell script below can be +cut out and run as "ip2mkdev" to create the necessary device files. To +use the ip2mkdev script, you must have procfs enabled and the proc file +system mounted on /proc. + + +6. NOTES + +This is a release version of the driver, but it is impossible to test it +in all configurations of Linux. If there is any anomalous behaviour that +does not match the standard serial port's behaviour please let us know. + + +7. ip2mkdev shell script + +Previously, this script was simply attached here. It is now attached as a +shar archive to make it easier to extract the script from the documentation. +To create the ip2mkdev shell script change to a convenient directory (/tmp +works just fine) and run the following command: + + unshar Documentation/serial/computone.txt + (This file) + +You should now have a file ip2mkdev in your current working directory with +permissions set to execute. Running that script with then create the +necessary devices for the Computone boards, interfaces, and ports which +are present on you system at the time it is run. + + +#!/bin/sh +# This is a shell archive (produced by GNU sharutils 4.2.1). +# To extract the files from this archive, save it to some FILE, remove +# everything before the `!/bin/sh' line above, then type `sh FILE'. +# +# Made on 2001-10-29 10:32 EST by . +# Source directory was `/home2/src/tmp'. +# +# Existing files will *not* be overwritten unless `-c' is specified. +# +# This shar contains: +# length mode name +# ------ ---------- ------------------------------------------ +# 4251 -rwxr-xr-x ip2mkdev +# +save_IFS="${IFS}" +IFS="${IFS}:" +gettext_dir=FAILED +locale_dir=FAILED +first_param="$1" +for dir in $PATH +do + if test "$gettext_dir" = FAILED && test -f $dir/gettext \ + && ($dir/gettext --version >/dev/null 2>&1) + then + set `$dir/gettext --version 2>&1` + if test "$3" = GNU + then + gettext_dir=$dir + fi + fi + if test "$locale_dir" = FAILED && test -f $dir/shar \ + && ($dir/shar --print-text-domain-dir >/dev/null 2>&1) + then + locale_dir=`$dir/shar --print-text-domain-dir` + fi +done +IFS="$save_IFS" +if test "$locale_dir" = FAILED || test "$gettext_dir" = FAILED +then + echo=echo +else + TEXTDOMAINDIR=$locale_dir + export TEXTDOMAINDIR + TEXTDOMAIN=sharutils + export TEXTDOMAIN + echo="$gettext_dir/gettext -s" +fi +if touch -am -t 200112312359.59 $$.touch >/dev/null 2>&1 && test ! -f 200112312359.59 -a -f $$.touch; then + shar_touch='touch -am -t $1$2$3$4$5$6.$7 "$8"' +elif touch -am 123123592001.59 $$.touch >/dev/null 2>&1 && test ! -f 123123592001.59 -a ! -f 123123592001.5 -a -f $$.touch; then + shar_touch='touch -am $3$4$5$6$1$2.$7 "$8"' +elif touch -am 1231235901 $$.touch >/dev/null 2>&1 && test ! -f 1231235901 -a -f $$.touch; then + shar_touch='touch -am $3$4$5$6$2 "$8"' +else + shar_touch=: + echo + $echo 'WARNING: not restoring timestamps. Consider getting and' + $echo "installing GNU \`touch', distributed in GNU File Utilities..." + echo +fi +rm -f 200112312359.59 123123592001.59 123123592001.5 1231235901 $$.touch +# +if mkdir _sh17581; then + $echo 'x -' 'creating lock directory' +else + $echo 'failed to create lock directory' + exit 1 +fi +# ============= ip2mkdev ============== +if test -f 'ip2mkdev' && test "$first_param" != -c; then + $echo 'x -' SKIPPING 'ip2mkdev' '(file already exists)' +else + $echo 'x -' extracting 'ip2mkdev' '(text)' + sed 's/^X//' << 'SHAR_EOF' > 'ip2mkdev' && +#!/bin/sh - +# +# ip2mkdev +# +# Make or remove devices as needed for Computone Intelliport drivers +# +# First rule! If the dev file exists and you need it, don't mess +# with it. That prevents us from screwing up open ttys, ownership +# and permissions on a running system! +# +# This script will NOT remove devices that no longer exist if their +# board or interface box has been removed. If you want to get rid +# of them, you can manually do an "rm -f /dev/ttyF* /dev/cuaf*" +# before running this script. Running this script will then recreate +# all the valid devices. +# +# Michael H. Warfield +# /\/\|=mhw=|\/\/ +# mhw@wittsend.com +# +# Updated 10/29/2000 for version 1.2.13 naming convention +# under devfs. /\/\|=mhw=|\/\/ +# +# Updated 03/09/2000 for devfs support in ip2 drivers. /\/\|=mhw=|\/\/ +# +X +if test -d /dev/ip2 ; then +# This is devfs mode... We don't do anything except create symlinks +# from the real devices to the old names! +X cd /dev +X echo "Creating symbolic links to devfs devices" +X for i in `ls ip2` ; do +X if test ! -L ip2$i ; then +X # Remove it incase it wasn't a symlink (old device) +X rm -f ip2$i +X ln -s ip2/$i ip2$i +X fi +X done +X for i in `( cd tts ; ls F* )` ; do +X if test ! -L tty$i ; then +X # Remove it incase it wasn't a symlink (old device) +X rm -f tty$i +X ln -s tts/$i tty$i +X fi +X done +X for i in `( cd cua ; ls F* )` ; do +X DEVNUMBER=`expr $i : 'F\(.*\)'` +X if test ! -L cuf$DEVNUMBER ; then +X # Remove it incase it wasn't a symlink (old device) +X rm -f cuf$DEVNUMBER +X ln -s cua/$i cuf$DEVNUMBER +X fi +X done +X exit 0 +fi +X +if test ! -f /proc/tty/drivers +then +X echo "\ +Unable to check driver status. +Make sure proc file system is mounted." +X +X exit 255 +fi +X +if test ! -f /proc/tty/driver/ip2 +then +X echo "\ +Unable to locate ip2 proc file. +Attempting to load driver" +X +X if /sbin/insmod ip2 +X then +X if test ! -f /proc/tty/driver/ip2 +X then +X echo "\ +Unable to locate ip2 proc file after loading driver. +Driver initialization failure or driver version error. +" +X exit 255 +X fi +X else +X echo "Unable to load ip2 driver." +X exit 255 +X fi +fi +X +# Ok... So we got the driver loaded and we can locate the procfs files. +# Next we need our major numbers. +X +TTYMAJOR=`sed -e '/^ip2/!d' -e '/\/dev\/tt/!d' -e 's/.*tt[^ ]*[ ]*\([0-9]*\)[ ]*.*/\1/' < /proc/tty/drivers` +CUAMAJOR=`sed -e '/^ip2/!d' -e '/\/dev\/cu/!d' -e 's/.*cu[^ ]*[ ]*\([0-9]*\)[ ]*.*/\1/' < /proc/tty/drivers` +BRDMAJOR=`sed -e '/^Driver: /!d' -e 's/.*IMajor=\([0-9]*\)[ ]*.*/\1/' < /proc/tty/driver/ip2` +X +echo "\ +TTYMAJOR = $TTYMAJOR +CUAMAJOR = $CUAMAJOR +BRDMAJOR = $BRDMAJOR +" +X +# Ok... Now we should know our major numbers, if appropriate... +# Now we need our boards and start the device loops. +X +grep '^Board [0-9]:' /proc/tty/driver/ip2 | while read token number type alltherest +do +X # The test for blank "type" will catch the stats lead-in lines +X # if they exist in the file +X if test "$type" = "vacant" -o "$type" = "Vacant" -o "$type" = "" +X then +X continue +X fi +X +X BOARDNO=`expr "$number" : '\([0-9]\):'` +X PORTS=`expr "$alltherest" : '.*ports=\([0-9]*\)' | tr ',' ' '` +X MINORS=`expr "$alltherest" : '.*minors=\([0-9,]*\)' | tr ',' ' '` +X +X if test "$BOARDNO" = "" -o "$PORTS" = "" +X then +# This may be a bug. We should at least get this much information +X echo "Unable to process board line" +X continue +X fi +X +X if test "$MINORS" = "" +X then +# Silently skip this one. This board seems to have no boxes +X continue +X fi +X +X echo "board $BOARDNO: $type ports = $PORTS; port numbers = $MINORS" +X +X if test "$BRDMAJOR" != "" +X then +X BRDMINOR=`expr $BOARDNO \* 4` +X STSMINOR=`expr $BRDMINOR + 1` +X if test ! -c /dev/ip2ipl$BOARDNO ; then +X mknod /dev/ip2ipl$BOARDNO c $BRDMAJOR $BRDMINOR +X fi +X if test ! -c /dev/ip2stat$BOARDNO ; then +X mknod /dev/ip2stat$BOARDNO c $BRDMAJOR $STSMINOR +X fi +X fi +X +X if test "$TTYMAJOR" != "" +X then +X PORTNO=$BOARDBASE +X +X for PORTNO in $MINORS +X do +X if test ! -c /dev/ttyF$PORTNO ; then +X # We got the hardware but no device - make it +X mknod /dev/ttyF$PORTNO c $TTYMAJOR $PORTNO +X fi +X done +X fi +X +X if test "$CUAMAJOR" != "" +X then +X PORTNO=$BOARDBASE +X +X for PORTNO in $MINORS +X do +X if test ! -c /dev/cuf$PORTNO ; then +X # We got the hardware but no device - make it +X mknod /dev/cuf$PORTNO c $CUAMAJOR $PORTNO +X fi +X done +X fi +done +X +Xexit 0 +SHAR_EOF + (set 20 01 10 29 10 32 01 'ip2mkdev'; eval "$shar_touch") && + chmod 0755 'ip2mkdev' || + $echo 'restore of' 'ip2mkdev' 'failed' + if ( md5sum --help 2>&1 | grep 'sage: md5sum \[' ) >/dev/null 2>&1 \ + && ( md5sum --version 2>&1 | grep -v 'textutils 1.12' ) >/dev/null; then + md5sum -c << SHAR_EOF >/dev/null 2>&1 \ + || $echo 'ip2mkdev:' 'MD5 check failed' +cb5717134509f38bad9fde6b1f79b4a4 ip2mkdev +SHAR_EOF + else + shar_count="`LC_ALL= LC_CTYPE= LANG= wc -c < 'ip2mkdev'`" + test 4251 -eq "$shar_count" || + $echo 'ip2mkdev:' 'original size' '4251,' 'current size' "$shar_count!" + fi +fi +rm -fr _sh17581 +exit 0 diff --git a/Documentation/serial/digiepca.txt b/Documentation/serial/digiepca.txt new file mode 100644 index 000000000000..f2560e22f2c9 --- /dev/null +++ b/Documentation/serial/digiepca.txt @@ -0,0 +1,98 @@ +NOTE: This driver is obsolete. Digi provides a 2.6 driver (dgdm) at +http://www.digi.com for PCI cards. They no longer maintain this driver, +and have no 2.6 driver for ISA cards. + +This driver requires a number of user-space tools. They can be acquired from +http://www.digi.com, but only works with 2.4 kernels. + + +The Digi Intl. epca driver. +---------------------------- +The Digi Intl. epca driver for Linux supports the following boards: + +Digi PC/Xem, PC/Xr, PC/Xe, PC/Xi, PC/Xeve +Digi EISA/Xem, PCI/Xem, PCI/Xr + +Limitations: +------------ +Currently the driver only autoprobes for supported PCI boards. + +The Linux MAKEDEV command does not support generating the Digiboard +Devices. Users executing digiConfig to setup EISA and PC series cards +will have their device nodes automatically constructed (cud?? for ~CLOCAL, +and ttyD?? for CLOCAL). Users wishing to boot their board from the LILO +prompt, or those users booting PCI cards may use buildDIGI to construct +the necessary nodes. + +Notes: +------ +This driver may be configured via LILO. For users who have already configured +their driver using digiConfig, configuring from LILO will override previous +settings. Multiple boards may be configured by issuing multiple LILO command +lines. For examples see the bottom of this document. + +Device names start at 0 and continue up. Beware of this as previous Digi +drivers started device names with 1. + +PCI boards are auto-detected and configured by the driver. PCI boards will +be allocated device numbers (internally) beginning with the lowest PCI slot +first. In other words a PCI card in slot 3 will always have higher device +nodes than a PCI card in slot 1. + +LILO config examples: +--------------------- +Using LILO's APPEND command, a string of comma separated identifiers or +integers can be used to configure supported boards. The six values in order +are: + + Enable/Disable this card or Override, + Type of card: PC/Xe (AccelePort) (0), PC/Xeve (1), PC/Xem or PC/Xr (2), + EISA/Xem (3), PC/64Xe (4), PC/Xi (5), + Enable/Disable alternate pin arrangement, + Number of ports on this card, + I/O Port where card is configured (in HEX if using string identifiers), + Base of memory window (in HEX if using string identifiers), + +NOTE : PCI boards are auto-detected and configured. Do not attempt to +configure PCI boards with the LILO append command. If you wish to override +previous configuration data (As set by digiConfig), but you do not wish to +configure any specific card (Example if there are PCI cards in the system) +the following override command will accomplish this: +-> append="digi=2" + +Samples: + append="digiepca=E,PC/Xe,D,16,200,D0000" + or + append="digi=1,0,0,16,512,851968" + +Supporting Tools: +----------------- +Supporting tools include digiDload, digiConfig, buildPCI, and ditty. See +drivers/char/README.epca for more details. Note, +this driver REQUIRES that digiDload be executed prior to it being used. +Failure to do this will result in an ENODEV error. + +Documentation: +-------------- +Complete documentation for this product may be found in the tool package. + +Sources of information and support: +----------------------------------- +Digi Intl. support site for this product: + +-> http://www.digi.com + +Acknowledgments: +---------------- +Much of this work (And even text) was derived from a similar document +supporting the original public domain DigiBoard driver Copyright (C) +1994,1995 Troy De Jongh. Many thanks to Christoph Lameter +(christoph@lameter.com) and Mike McLagan (mike.mclagan@linux.org) who authored +and contributed to the original document. + +Changelog: +---------- +10-29-04: Update status of driver, remove dead links in document + James Nelson + +2000 (?) Original Document diff --git a/Documentation/serial/hayes-esp.txt b/Documentation/serial/hayes-esp.txt new file mode 100644 index 000000000000..09b5d5856758 --- /dev/null +++ b/Documentation/serial/hayes-esp.txt @@ -0,0 +1,154 @@ +HAYES ESP DRIVER VERSION 2.1 + +A big thanks to the people at Hayes, especially Alan Adamson. Their support +has enabled me to provide enhancements to the driver. + +Please report your experiences with this driver to me (arobinso@nyx.net). I +am looking for both positive and negative feedback. + +*** IMPORTANT CHANGES FOR 2.1 *** +Support for PIO mode. Five situations will cause PIO mode to be used: +1) A multiport card is detected. PIO mode will always be used. (8 port cards +do not support DMA). +2) The DMA channel is set to an invalid value (anything other than 1 or 3). +3) The DMA buffer/channel could not be allocated. The port will revert to PIO +mode until it is reopened. +4) Less than a specified number of bytes need to be transferred to/from the +FIFOs. PIO mode will be used for that transfer only. +5) A port needs to do a DMA transfer and another port is already using the +DMA channel. PIO mode will be used for that transfer only. + +Since the Hayes ESP seems to conflict with other cards (notably sound cards) +when using DMA, DMA is turned off by default. To use DMA, it must be turned +on explicitly, either with the "dma=" option described below or with +setserial. A multiport card can be forced into DMA mode by using setserial; +however, most multiport cards don't support DMA. + +The latest version of setserial allows the enhanced configuration of the ESP +card to be viewed and modified. +*** + +This package contains the files needed to compile a module to support the Hayes +ESP card. The drivers are basically a modified version of the serial drivers. + +Features: + +- Uses the enhanced mode of the ESP card, allowing a wider range of + interrupts and features than compatibility mode +- Uses DMA and 16 bit PIO mode to transfer data to and from the ESP's FIFOs, + reducing CPU load +- Supports primary and secondary ports + + +If the driver is compiled as a module, the IRQs to use can be specified by +using the irq= option. The format is: + +irq=[0x100],[0x140],[0x180],[0x200],[0x240],[0x280],[0x300],[0x380] + +The address in brackets is the base address of the card. The IRQ of +nonexistent cards can be set to 0. If an IRQ of a card that does exist is set +to 0, the driver will attempt to guess at the correct IRQ. For example, to set +the IRQ of the card at address 0x300 to 12, the insmod command would be: + +insmod esp irq=0,0,0,0,0,0,12,0 + +The custom divisor can be set by using the divisor= option. The format is the +same as for the irq= option. Each divisor value is a series of hex digits, +with each digit representing the divisor to use for a corresponding port. The +divisor value is constructed RIGHT TO LEFT. Specifying a nonzero divisor value +will automatically set the spd_cust flag. To calculate the divisor to use for +a certain baud rate, divide the port's base baud (generally 921600) by the +desired rate. For example, to set the divisor of the primary port at 0x300 to +4 and the divisor of the secondary port at 0x308 to 8, the insmod command would +be: + +insmod esp divisor=0,0,0,0,0,0,0x84,0 + +The dma= option can be used to set the DMA channel. The channel can be either +1 or 3. Specifying any other value will force the driver to use PIO mode. +For example, to set the DMA channel to 3, the insmod command would be: + +insmod esp dma=3 + +The rx_trigger= and tx_trigger= options can be used to set the FIFO trigger +levels. They specify when the ESP card should send an interrupt. Larger +values will decrease the number of interrupts; however, a value too high may +result in data loss. Valid values are 1 through 1023, with 768 being the +default. For example, to set the receive trigger level to 512 bytes and the +transmit trigger level to 700 bytes, the insmod command would be: + +insmod esp rx_trigger=512 tx_trigger=700 + +The flow_off= and flow_on= options can be used to set the hardware flow off/ +flow on levels. The flow on level must be lower than the flow off level, and +the flow off level should be higher than rx_trigger. Valid values are 1 +through 1023, with 1016 being the default flow off level and 944 being the +default flow on level. For example, to set the flow off level to 1000 bytes +and the flow on level to 935 bytes, the insmod command would be: + +insmod esp flow_off=1000 flow_on=935 + +The rx_timeout= option can be used to set the receive timeout value. This +value indicates how long after receiving the last character that the ESP card +should wait before signalling an interrupt. Valid values are 0 though 255, +with 128 being the default. A value too high will increase latency, and a +value too low will cause unnecessary interrupts. For example, to set the +receive timeout to 255, the insmod command would be: + +insmod esp rx_timeout=255 + +The pio_threshold= option sets the threshold (in number of characters) for +using PIO mode instead of DMA mode. For example, if this value is 32, +transfers of 32 bytes or less will always use PIO mode. + +insmod esp pio_threshold=32 + +Multiple options can be listed on the insmod command line by separating each +option with a space. For example: + +insmod esp dma=3 trigger=512 + +The esp module can be automatically loaded when needed. To cause this to +happen, add the following lines to /etc/modprobe.conf (replacing the last line +with options for your configuration): + +alias char-major-57 esp +alias char-major-58 esp +options esp irq=0,0,0,0,0,0,3,0 divisor=0,0,0,0,0,0,0x4,0 + +You may also need to run 'depmod -a'. + +Devices must be created manually. To create the devices, note the output from +the module after it is inserted. The output will appear in the location where +kernel messages usually appear (usually /var/adm/messages). Create two devices +for each 'tty' mentioned, one with major of 57 and the other with major of 58. +The minor number should be the same as the tty number reported. The commands +would be (replace ? with the tty number): + +mknod /dev/ttyP? c 57 ? +mknod /dev/cup? c 58 ? + +For example, if the following line appears: + +Oct 24 18:17:23 techno kernel: ttyP8 at 0x0140 (irq = 3) is an ESP primary port + +...two devices should be created: + +mknod /dev/ttyP8 c 57 8 +mknod /dev/cup8 c 58 8 + +You may need to set the permissions on the devices: + +chmod 666 /dev/ttyP* +chmod 666 /dev/cup* + +The ESP module and the serial module should not conflict (they can be used at +the same time). After the ESP module has been loaded the ports on the ESP card +will no longer be accessible by the serial driver. + +If I/O errors are experienced when accessing the port, check for IRQ and DMA +conflicts ('cat /proc/interrupts' and 'cat /proc/dma' for a list of IRQs and +DMAs currently in use). + +Enjoy! +Andrew J. Robinson diff --git a/Documentation/serial/moxa-smartio b/Documentation/serial/moxa-smartio new file mode 100644 index 000000000000..5337e80a5b96 --- /dev/null +++ b/Documentation/serial/moxa-smartio @@ -0,0 +1,523 @@ +============================================================================= + MOXA Smartio/Industio Family Device Driver Installation Guide + for Linux Kernel 2.4.x, 2.6.x + Copyright (C) 2008, Moxa Inc. +============================================================================= +Date: 01/21/2008 + +Content + +1. Introduction +2. System Requirement +3. Installation + 3.1 Hardware installation + 3.2 Driver files + 3.3 Device naming convention + 3.4 Module driver configuration + 3.5 Static driver configuration for Linux kernel 2.4.x and 2.6.x. + 3.6 Custom configuration + 3.7 Verify driver installation +4. Utilities +5. Setserial +6. Troubleshooting + +----------------------------------------------------------------------------- +1. Introduction + + The Smartio/Industio/UPCI family Linux driver supports following multiport + boards. + + - 2 ports multiport board + CP-102U, CP-102UL, CP-102UF + CP-132U-I, CP-132UL, + CP-132, CP-132I, CP132S, CP-132IS, + CI-132, CI-132I, CI-132IS, + (C102H, C102HI, C102HIS, C102P, CP-102, CP-102S) + + - 4 ports multiport board + CP-104EL, + CP-104UL, CP-104JU, + CP-134U, CP-134U-I, + C104H/PCI, C104HS/PCI, + CP-114, CP-114I, CP-114S, CP-114IS, CP-114UL, + C104H, C104HS, + CI-104J, CI-104JS, + CI-134, CI-134I, CI-134IS, + (C114HI, CT-114I, C104P) + POS-104UL, + CB-114, + CB-134I + + - 8 ports multiport board + CP-118EL, CP-168EL, + CP-118U, CP-168U, + C168H/PCI, + C168H, C168HS, + (C168P), + CB-108 + + This driver and installation procedure have been developed upon Linux Kernel + 2.4.x and 2.6.x. This driver supports Intel x86 hardware platform. In order + to maintain compatibility, this version has also been properly tested with + RedHat, Mandrake, Fedora and S.u.S.E Linux. However, if compatibility problem + occurs, please contact Moxa at support@moxa.com.tw. + + In addition to device driver, useful utilities are also provided in this + version. They are + - msdiag Diagnostic program for displaying installed Moxa + Smartio/Industio boards. + - msmon Monitor program to observe data count and line status signals. + - msterm A simple terminal program which is useful in testing serial + ports. + - io-irq.exe Configuration program to setup ISA boards. Please note that + this program can only be executed under DOS. + + All the drivers and utilities are published in form of source code under + GNU General Public License in this version. Please refer to GNU General + Public License announcement in each source code file for more detail. + + In Moxa's Web sites, you may always find latest driver at http://web.moxa.com. + + This version of driver can be installed as Loadable Module (Module driver) + or built-in into kernel (Static driver). You may refer to following + installation procedure for suitable one. Before you install the driver, + please refer to hardware installation procedure in the User's Manual. + + We assume the user should be familiar with following documents. + - Serial-HOWTO + - Kernel-HOWTO + +----------------------------------------------------------------------------- +2. System Requirement + - Hardware platform: Intel x86 machine + - Kernel version: 2.4.x or 2.6.x + - gcc version 2.72 or later + - Maximum 4 boards can be installed in combination + +----------------------------------------------------------------------------- +3. Installation + + 3.1 Hardware installation + 3.2 Driver files + 3.3 Device naming convention + 3.4 Module driver configuration + 3.5 Static driver configuration for Linux kernel 2.4.x, 2.6.x. + 3.6 Custom configuration + 3.7 Verify driver installation + + + 3.1 Hardware installation + + There are two types of buses, ISA and PCI, for Smartio/Industio + family multiport board. + + ISA board + --------- + You'll have to configure CAP address, I/O address, Interrupt Vector + as well as IRQ before installing this driver. Please refer to hardware + installation procedure in User's Manual before proceed any further. + Please make sure the JP1 is open after the ISA board is set properly. + + PCI/UPCI board + -------------- + You may need to adjust IRQ usage in BIOS to avoid from IRQ conflict + with other ISA devices. Please refer to hardware installation + procedure in User's Manual in advance. + + PCI IRQ Sharing + ----------- + Each port within the same multiport board shares the same IRQ. Up to + 4 Moxa Smartio/Industio PCI Family multiport boards can be installed + together on one system and they can share the same IRQ. + + + 3.2 Driver files + + The driver file may be obtained from ftp, CD-ROM or floppy disk. The + first step, anyway, is to copy driver file "mxser.tgz" into specified + directory. e.g. /moxa. The execute commands as below. + + # cd / + # mkdir moxa + # cd /moxa + # tar xvf /dev/fd0 + + or + + # cd / + # mkdir moxa + # cd /moxa + # cp /mnt/cdrom//mxser.tgz . + # tar xvfz mxser.tgz + + + 3.3 Device naming convention + + You may find all the driver and utilities files in /moxa/mxser. + Following installation procedure depends on the model you'd like to + run the driver. If you prefer module driver, please refer to 3.4. + If static driver is required, please refer to 3.5. + + Dialin and callout port + ----------------------- + This driver remains traditional serial device properties. There are + two special file name for each serial port. One is dial-in port + which is named "ttyMxx". For callout port, the naming convention + is "cumxx". + + Device naming when more than 2 boards installed + ----------------------------------------------- + Naming convention for each Smartio/Industio multiport board is + pre-defined as below. + + Board Num. Dial-in Port Callout port + 1st board ttyM0 - ttyM7 cum0 - cum7 + 2nd board ttyM8 - ttyM15 cum8 - cum15 + 3rd board ttyM16 - ttyM23 cum16 - cum23 + 4th board ttyM24 - ttym31 cum24 - cum31 + + + !!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + Under Kernel 2.6 the cum Device is Obsolete. So use ttyM* + device instead. + !!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + + Board sequence + -------------- + This driver will activate ISA boards according to the parameter set + in the driver. After all specified ISA board activated, PCI board + will be installed in the system automatically driven. + Therefore the board number is sorted by the CAP address of ISA boards. + For PCI boards, their sequence will be after ISA boards and C168H/PCI + has higher priority than C104H/PCI boards. + + 3.4 Module driver configuration + Module driver is easiest way to install. If you prefer static driver + installation, please skip this paragraph. + + + ------------- Prepare to use the MOXA driver-------------------- + 3.4.1 Create tty device with correct major number + Before using MOXA driver, your system must have the tty devices + which are created with driver's major number. We offer one shell + script "msmknod" to simplify the procedure. + This step is only needed to be executed once. But you still + need to do this procedure when: + a. You change the driver's major number. Please refer the "3.7" + section. + b. Your total installed MOXA boards number is changed. Maybe you + add/delete one MOXA board. + c. You want to change the tty name. This needs to modify the + shell script "msmknod" + + The procedure is: + # cd /moxa/mxser/driver + # ./msmknod + + This shell script will require the major number for dial-in + device and callout device to create tty device. You also need + to specify the total installed MOXA board number. Default major + numbers for dial-in device and callout device are 30, 35. If + you need to change to other number, please refer section "3.7" + for more detailed procedure. + Msmknod will delete any special files occupying the same device + naming. + + 3.4.2 Build the MOXA driver and utilities + Before using the MOXA driver and utilities, you need compile the + all the source code. This step is only need to be executed once. + But you still re-compile the source code if you modify the source + code. For example, if you change the driver's major number (see + "3.7" section), then you need to do this step again. + + Find "Makefile" in /moxa/mxser, then run + + # make clean; make install + + !!!!!!!!!! NOTE !!!!!!!!!!!!!!!!! + For Red Hat 9, Red Hat Enterprise Linux AS3/ES3/WS3 & Fedora Core1: + # make clean; make installsp1 + + For Red Hat Enterprise Linux AS4/ES4/WS4: + # make clean; make installsp2 + !!!!!!!!!! NOTE !!!!!!!!!!!!!!!!! + + The driver files "mxser.o" and utilities will be properly compiled + and copied to system directories respectively. + + ------------- Load MOXA driver-------------------- + 3.4.3 Load the MOXA driver + + # modprobe mxser + + will activate the module driver. You may run "lsmod" to check + if "mxser" is activated. If the MOXA board is ISA board, the + is needed. Please refer to section "3.4.5" for more + information. + + + ------------- Load MOXA driver on boot -------------------- + 3.4.4 For the above description, you may manually execute + "modprobe mxser" to activate this driver and run + "rmmod mxser" to remove it. + However, it's better to have a boot time configuration to + eliminate manual operation. Boot time configuration can be + achieved by rc file. We offer one "rc.mxser" file to simplify + the procedure under "moxa/mxser/driver". + + But if you use ISA board, please modify the "modprobe ..." command + to add the argument (see "3.4.5" section). After modifying the + rc.mxser, please try to execute "/moxa/mxser/driver/rc.mxser" + manually to make sure the modification is ok. If any error + encountered, please try to modify again. If the modification is + completed, follow the below step. + + Run following command for setting rc files. + + # cd /moxa/mxser/driver + # cp ./rc.mxser /etc/rc.d + # cd /etc/rc.d + + Check "rc.serial" is existed or not. If "rc.serial" doesn't exist, + create it by vi, run "chmod 755 rc.serial" to change the permission. + Add "/etc/rc.d/rc.mxser" in last line, + + Reboot and check if moxa.o activated by "lsmod" command. + + 3.4.5. If you'd like to drive Smartio/Industio ISA boards in the system, + you'll have to add parameter to specify CAP address of given + board while activating "mxser.o". The format for parameters are + as follows. + + modprobe mxser ioaddr=0x???,0x???,0x???,0x??? + | | | | + | | | +- 4th ISA board + | | +------ 3rd ISA board + | +------------ 2nd ISA board + +------------------- 1st ISA board + + 3.5 Static driver configuration for Linux kernel 2.4.x and 2.6.x + + Note: To use static driver, you must install the linux kernel + source package. + + 3.5.1 Backup the built-in driver in the kernel. + # cd /usr/src/linux/drivers/char + # mv mxser.c mxser.c.old + + For Red Hat 7.x user, you need to create link: + # cd /usr/src + # ln -s linux-2.4 linux + + 3.5.2 Create link + # cd /usr/src/linux/drivers/char + # ln -s /moxa/mxser/driver/mxser.c mxser.c + + 3.5.3 Add CAP address list for ISA boards. For PCI boards user, + please skip this step. + + In module mode, the CAP address for ISA board is given by + parameter. In static driver configuration, you'll have to + assign it within driver's source code. If you will not + install any ISA boards, you may skip to next portion. + The instructions to modify driver source code are as + below. + a. # cd /moxa/mxser/driver + # vi mxser.c + b. Find the array mxserBoardCAP[] as below. + + static int mxserBoardCAP[] + = {0x00, 0x00, 0x00, 0x00}; + + c. Change the address within this array using vi. For + example, to driver 2 ISA boards with CAP address + 0x280 and 0x180 as 1st and 2nd board. Just to change + the source code as follows. + + static int mxserBoardCAP[] + = {0x280, 0x180, 0x00, 0x00}; + + 3.5.4 Setup kernel configuration + + Configure the kernel: + + # cd /usr/src/linux + # make menuconfig + + You will go into a menu-driven system. Please select [Character + devices][Non-standard serial port support], enable the [Moxa + SmartIO support] driver with "[*]" for built-in (not "[M]"), then + select [Exit] to exit this program. + + 3.5.5 Rebuild kernel + The following are for Linux kernel rebuilding, for your + reference only. + For appropriate details, please refer to the Linux document. + + a. cd /usr/src/linux + b. make clean /* take a few minutes */ + c. make dep /* take a few minutes */ + d. make bzImage /* take probably 10-20 minutes */ + e. make install /* copy boot image to correct position */ + f. Please make sure the boot kernel (vmlinuz) is in the + correct position. + g. If you use 'lilo' utility, you should check /etc/lilo.conf + 'image' item specified the path which is the 'vmlinuz' path, + or you will load wrong (or old) boot kernel image (vmlinuz). + After checking /etc/lilo.conf, please run "lilo". + + Note that if the result of "make bzImage" is ERROR, then you have to + go back to Linux configuration Setup. Type "make menuconfig" in + directory /usr/src/linux. + + + 3.5.6 Make tty device and special file + # cd /moxa/mxser/driver + # ./msmknod + + 3.5.7 Make utility + # cd /moxa/mxser/utility + # make clean; make install + + 3.5.8 Reboot + + + + 3.6 Custom configuration + Although this driver already provides you default configuration, you + still can change the device name and major number. The instruction to + change these parameters are shown as below. + + Change Device name + ------------------ + If you'd like to use other device names instead of default naming + convention, all you have to do is to modify the internal code + within the shell script "msmknod". First, you have to open "msmknod" + by vi. Locate each line contains "ttyM" and "cum" and change them + to the device name you desired. "msmknod" creates the device names + you need next time executed. + + Change Major number + ------------------- + If major number 30 and 35 had been occupied, you may have to select + 2 free major numbers for this driver. There are 3 steps to change + major numbers. + + 3.6.1 Find free major numbers + In /proc/devices, you may find all the major numbers occupied + in the system. Please select 2 major numbers that are available. + e.g. 40, 45. + 3.6.2 Create special files + Run /moxa/mxser/driver/msmknod to create special files with + specified major numbers. + 3.6.3 Modify driver with new major number + Run vi to open /moxa/mxser/driver/mxser.c. Locate the line + contains "MXSERMAJOR". Change the content as below. + #define MXSERMAJOR 40 + #define MXSERCUMAJOR 45 + 3.6.4 Run "make clean; make install" in /moxa/mxser/driver. + + 3.7 Verify driver installation + You may refer to /var/log/messages to check the latest status + log reported by this driver whenever it's activated. + +----------------------------------------------------------------------------- +4. Utilities + There are 3 utilities contained in this driver. They are msdiag, msmon and + msterm. These 3 utilities are released in form of source code. They should + be compiled into executable file and copied into /usr/bin. + + Before using these utilities, please load driver (refer 3.4 & 3.5) and + make sure you had run the "msmknod" utility. + + msdiag - Diagnostic + -------------------- + This utility provides the function to display what Moxa Smartio/Industio + board found by driver in the system. + + msmon - Port Monitoring + ----------------------- + This utility gives the user a quick view about all the MOXA ports' + activities. One can easily learn each port's total received/transmitted + (Rx/Tx) character count since the time when the monitoring is started. + Rx/Tx throughputs per second are also reported in interval basis (e.g. + the last 5 seconds) and in average basis (since the time the monitoring + is started). You can reset all ports' count by key. <+> <-> + (plus/minus) keys to change the displaying time interval. Press + on the port, that cursor stay, to view the port's communication + parameters, signal status, and input/output queue. + + msterm - Terminal Emulation + --------------------------- + This utility provides data sending and receiving ability of all tty ports, + especially for MOXA ports. It is quite useful for testing simple + application, for example, sending AT command to a modem connected to the + port or used as a terminal for login purpose. Note that this is only a + dumb terminal emulation without handling full screen operation. + +----------------------------------------------------------------------------- +5. Setserial + + Supported Setserial parameters are listed as below. + + uart set UART type(16450-->disable FIFO, 16550A-->enable FIFO) + close_delay set the amount of time(in 1/100 of a second) that DTR + should be kept low while being closed. + closing_wait set the amount of time(in 1/100 of a second) that the + serial port should wait for data to be drained while + being closed, before the receiver is disable. + spd_hi Use 57.6kb when the application requests 38.4kb. + spd_vhi Use 115.2kb when the application requests 38.4kb. + spd_shi Use 230.4kb when the application requests 38.4kb. + spd_warp Use 460.8kb when the application requests 38.4kb. + spd_normal Use 38.4kb when the application requests 38.4kb. + spd_cust Use the custom divisor to set the speed when the + application requests 38.4kb. + divisor This option set the custom divison. + baud_base This option set the base baud rate. + +----------------------------------------------------------------------------- +6. Troubleshooting + + The boot time error messages and solutions are stated as clearly as + possible. If all the possible solutions fail, please contact our technical + support team to get more help. + + + Error msg: More than 4 Moxa Smartio/Industio family boards found. Fifth board + and after are ignored. + Solution: + To avoid this problem, please unplug fifth and after board, because Moxa + driver supports up to 4 boards. + + Error msg: Request_irq fail, IRQ(?) may be conflict with another device. + Solution: + Other PCI or ISA devices occupy the assigned IRQ. If you are not sure + which device causes the situation, please check /proc/interrupts to find + free IRQ and simply change another free IRQ for Moxa board. + + Error msg: Board #: C1xx Series(CAP=xxx) interrupt number invalid. + Solution: + Each port within the same multiport board shares the same IRQ. Please set + one IRQ (IRQ doesn't equal to zero) for one Moxa board. + + Error msg: No interrupt vector be set for Moxa ISA board(CAP=xxx). + Solution: + Moxa ISA board needs an interrupt vector.Please refer to user's manual + "Hardware Installation" chapter to set interrupt vector. + + Error msg: Couldn't install MOXA Smartio/Industio family driver! + Solution: + Load Moxa driver fail, the major number may conflict with other devices. + Please refer to previous section 3.7 to change a free major number for + Moxa driver. + + Error msg: Couldn't install MOXA Smartio/Industio family callout driver! + Solution: + Load Moxa callout driver fail, the callout device major number may + conflict with other devices. Please refer to previous section 3.7 to + change a free callout device major number for Moxa driver. + + +----------------------------------------------------------------------------- + diff --git a/Documentation/serial/riscom8.txt b/Documentation/serial/riscom8.txt new file mode 100644 index 000000000000..14f61fdad7ca --- /dev/null +++ b/Documentation/serial/riscom8.txt @@ -0,0 +1,36 @@ +* NOTE - this is an unmaintained driver. The original author cannot be located. + +SDL Communications is now SBS Technologies, and does not have any +information on these ancient ISA cards on their website. + +James Nelson - 12-12-2004 + + This is the README for RISCom/8 multi-port serial driver + (C) 1994-1996 D.Gorodchanin + See file LICENSE for terms and conditions. + +NOTE: English is not my native language. + I'm sorry for any mistakes in this text. + +Misc. notes for RISCom/8 serial driver, in no particular order :) + +1) This driver can support up to 4 boards at time. + Use string "riscom8=0xXXX,0xXXX,0xXXX,0xXXX" at LILO prompt, for + setting I/O base addresses for boards. If you compile driver + as module use modprobe options "iobase=0xXXX iobase1=0xXXX iobase2=..." + +2) The driver partially supports famous 'setserial' program, you can use almost + any of its options, excluding port & irq settings. + +3) There are some misc. defines at the beginning of riscom8.c, please read the + comments and try to change some of them in case of problems. + +4) I consider the current state of the driver as BETA. + +5) SDL Communications WWW page is http://www.sdlcomm.com. + +6) You can use the MAKEDEV program to create RISCom/8 /dev/ttyL* entries. + +7) Minor numbers for first board are 0-7, for second 8-15, etc. + +22 Apr 1996. diff --git a/Documentation/serial/rocket.txt b/Documentation/serial/rocket.txt new file mode 100644 index 000000000000..1d8582990435 --- /dev/null +++ b/Documentation/serial/rocket.txt @@ -0,0 +1,189 @@ +Comtrol(tm) RocketPort(R)/RocketModem(TM) Series +Device Driver for the Linux Operating System + +=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- + +PRODUCT OVERVIEW +---------------- + +This driver provides a loadable kernel driver for the Comtrol RocketPort +and RocketModem PCI boards. These boards provide, 2, 4, 8, 16, or 32 +high-speed serial ports or modems. This driver supports up to a combination +of four RocketPort or RocketModems boards in one machine simultaneously. +This file assumes that you are using the RocketPort driver which is +integrated into the kernel sources. + +The driver can also be installed as an external module using the usual +"make;make install" routine. This external module driver, obtainable +from the Comtrol website listed below, is useful for updating the driver +or installing it into kernels which do not have the driver configured +into them. Installations instructions for the external module +are in the included README and HW_INSTALL files. + +RocketPort ISA and RocketModem II PCI boards currently are only supported by +this driver in module form. + +The RocketPort ISA board requires I/O ports to be configured by the DIP +switches on the board. See the section "ISA Rocketport Boards" below for +information on how to set the DIP switches. + +You pass the I/O port to the driver using the following module parameters: + +board1 : I/O port for the first ISA board +board2 : I/O port for the second ISA board +board3 : I/O port for the third ISA board +board4 : I/O port for the fourth ISA board + +There is a set of utilities and scripts provided with the external driver +( downloadable from http://www.comtrol.com ) that ease the configuration and +setup of the ISA cards. + +The RocketModem II PCI boards require firmware to be loaded into the card +before it will function. The driver has only been tested as a module for this +board. + +=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- + +INSTALLATION PROCEDURES +----------------------- + +RocketPort/RocketModem PCI cards require no driver configuration, they are +automatically detected and configured. + +The RocketPort driver can be installed as a module (recommended) or built +into the kernel. This is selected, as for other drivers, through the `make config` +command from the root of the Linux source tree during the kernel build process. + +The RocketPort/RocketModem serial ports installed by this driver are assigned +device major number 46, and will be named /dev/ttyRx, where x is the port number +starting at zero (ex. /dev/ttyR0, /devttyR1, ...). If you have multiple cards +installed in the system, the mapping of port names to serial ports is displayed +in the system log at /var/log/messages. + +If installed as a module, the module must be loaded. This can be done +manually by entering "modprobe rocket". To have the module loaded automatically +upon system boot, edit the /etc/modprobe.conf file and add the line +"alias char-major-46 rocket". + +In order to use the ports, their device names (nodes) must be created with mknod. +This is only required once, the system will retain the names once created. To +create the RocketPort/RocketModem device names, use the command +"mknod /dev/ttyRx c 46 x" where x is the port number starting at zero. For example: + +>mknod /dev/ttyR0 c 46 0 +>mknod /dev/ttyR1 c 46 1 +>mknod /dev/ttyR2 c 46 2 + +The Linux script MAKEDEV will create the first 16 ttyRx device names (nodes) +for you: + +>/dev/MAKEDEV ttyR + +=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- + +ISA Rocketport Boards +--------------------- + +You must assign and configure the I/O addresses used by the ISA Rocketport +card before installing and using it. This is done by setting a set of DIP +switches on the Rocketport board. + + +SETTING THE I/O ADDRESS +----------------------- + +Before installing RocketPort(R) or RocketPort RA boards, you must find +a range of I/O addresses for it to use. The first RocketPort card +requires a 68-byte contiguous block of I/O addresses, starting at one +of the following: 0x100h, 0x140h, 0x180h, 0x200h, 0x240h, 0x280h, +0x300h, 0x340h, 0x380h. This I/O address must be reflected in the DIP +switches of *all* of the Rocketport cards. + +The second, third, and fourth RocketPort cards require a 64-byte +contiguous block of I/O addresses, starting at one of the following +I/O addresses: 0x100h, 0x140h, 0x180h, 0x1C0h, 0x200h, 0x240h, 0x280h, +0x2C0h, 0x300h, 0x340h, 0x380h, 0x3C0h. The I/O address used by the +second, third, and fourth Rocketport cards (if present) are set via +software control. The DIP switch settings for the I/O address must be +set to the value of the first Rocketport cards. + +In order to distinguish each of the card from the others, each card +must have a unique board ID set on the dip switches. The first +Rocketport board must be set with the DIP switches corresponding to +the first board, the second board must be set with the DIP switches +corresponding to the second board, etc. IMPORTANT: The board ID is +the only place where the DIP switch settings should differ between the +various Rocketport boards in a system. + +The I/O address range used by any of the RocketPort cards must not +conflict with any other cards in the system, including other +RocketPort cards. Below, you will find a list of commonly used I/O +address ranges which may be in use by other devices in your system. +On a Linux system, "cat /proc/ioports" will also be helpful in +identifying what I/O addresses are being used by devices on your +system. + +Remember, the FIRST RocketPort uses 68 I/O addresses. So, if you set it +for 0x100, it will occupy 0x100 to 0x143. This would mean that you +CAN NOT set the second, third or fourth board for address 0x140 since +the first 4 bytes of that range are used by the first board. You would +need to set the second, third, or fourth board to one of the next available +blocks such as 0x180. + +=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- + +RocketPort and RocketPort RA SW1 Settings: + + +-------------------------------+ + | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | + +-------+-------+---------------+ + | Unused| Card | I/O Port Block| + +-------------------------------+ + +DIP Switches DIP Switches +7 8 6 5 +=================== =================== +On On UNUSED, MUST BE ON. On On First Card <==== Default + On Off Second Card + Off On Third Card + Off Off Fourth Card + +DIP Switches I/O Address Range +4 3 2 1 Used by the First Card +===================================== +On Off On Off 100-143 +On Off Off On 140-183 +On Off Off Off 180-1C3 <==== Default +Off On On Off 200-243 +Off On Off On 240-283 +Off On Off Off 280-2C3 +Off Off On Off 300-343 +Off Off Off On 340-383 +Off Off Off Off 380-3C3 + +=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- + +REPORTING BUGS +-------------- + +For technical support, please provide the following +information: Driver version, kernel release, distribution of +kernel, and type of board you are using. Error messages and log +printouts port configuration details are especially helpful. + +USA + Phone: (612) 494-4100 + FAX: (612) 494-4199 + email: support@comtrol.com + +Comtrol Europe + Phone: +44 (0) 1 869 323-220 + FAX: +44 (0) 1 869 323-211 + email: support@comtrol.co.uk + +Web: http://www.comtrol.com +FTP: ftp.comtrol.com + +=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- + + diff --git a/Documentation/serial/specialix.txt b/Documentation/serial/specialix.txt new file mode 100644 index 000000000000..6eb6f3a3331c --- /dev/null +++ b/Documentation/serial/specialix.txt @@ -0,0 +1,383 @@ + + specialix.txt -- specialix IO8+ multiport serial driver readme. + + + + Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl) + + Specialix pays for the development and support of this driver. + Please DO contact io8-linux@specialix.co.uk if you require + support. + + This driver was developed in the BitWizard linux device + driver service. If you require a linux device driver for your + product, please contact devices@BitWizard.nl for a quote. + + This code is firmly based on the riscom/8 serial driver, + written by Dmitry Gorodchanin. The specialix IO8+ card + programming information was obtained from the CL-CD1865 Data + Book, and Specialix document number 6200059: IO8+ Hardware + Functional Specification, augmented by document number 6200088: + Merak Hardware Functional Specification. (IO8+/PCI is also + called Merak) + + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of + the License, or (at your option) any later version. + + This program is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, + USA. + + +Intro +===== + + +This file contains some random information, that I like to have online +instead of in a manual that can get lost. Ever misplace your Linux +kernel sources? And the manual of one of the boards in your computer? + + +Addresses and interrupts +======================== + +Address dip switch settings: +The dip switch sets bits 2-9 of the IO address. + + 9 8 7 6 5 4 3 2 + +-----------------+ + 0 | X X X X X X X | + | | = IoBase = 0x100 + 1 | X | + +-----------------+ ------ RS232 connectors ----> + + | | | + edge connector + | | | + V V V + +Base address 0x100 caused a conflict in one of my computers once. I +haven't the foggiest why. My Specialix card is now at 0x180. My +other computer runs just fine with the Specialix card at 0x100.... +The card occupies 4 addresses, but actually only two are really used. + +The PCI version doesn't have any dip switches. The BIOS assigns +an IO address. + +The driver now still autoprobes at 0x100, 0x180, 0x250 and 0x260. If +that causes trouble for you, please report that. I'll remove +autoprobing then. + +The driver will tell the card what IRQ to use, so you don't have to +change any jumpers to change the IRQ. Just use a command line +argument (irq=xx) to the insmod program to set the interrupt. + +The BIOS assigns the IRQ on the PCI version. You have no say in what +IRQ to use in that case. + +If your specialix cards are not at the default locations, you can use +the kernel command line argument "specialix=io0,irq0,io1,irq1...". +Here "io0" is the io address for the first card, and "irq0" is the +irq line that the first card should use. And so on. + +Examples. + +You use the driver as a module and have three cards at 0x100, 0x250 +and 0x180. And some way or another you want them detected in that +order. Moreover irq 12 is taken (e.g. by your PS/2 mouse). + + insmod specialix.o iobase=0x100,0x250,0x180 irq=9,11,15 + +The same three cards, but now in the kernel would require you to +add + + specialix=0x100,9,0x250,11,0x180,15 + +to the command line. This would become + + append="specialix=0x100,9,0x250,11,0x180,15" + +in your /etc/lilo.conf file if you use lilo. + +The Specialix driver is slightly odd: It allows you to have the second +or third card detected without having a first card. This has +advantages and disadvantages. A slot that isn't filled by an ISA card, +might be filled if a PCI card is detected. Thus if you have an ISA +card at 0x250 and a PCI card, you would get: + +sx0: specialix IO8+ Board at 0x100 not found. +sx1: specialix IO8+ Board at 0x180 not found. +sx2: specialix IO8+ board detected at 0x250, IRQ 12, CD1865 Rev. B. +sx3: specialix IO8+ Board at 0x260 not found. +sx0: specialix IO8+ board detected at 0xd800, IRQ 9, CD1865 Rev. B. + +This would happen if you don't give any probe hints to the driver. +If you would specify: + + specialix=0x250,11 + +you'd get the following messages: + +sx0: specialix IO8+ board detected at 0x250, IRQ 11, CD1865 Rev. B. +sx1: specialix IO8+ board detected at 0xd800, IRQ 9, CD1865 Rev. B. + +ISA probing is aborted after the IO address you gave is exhausted, and +the PCI card is now detected as the second card. The ISA card is now +also forced to IRQ11.... + + +Baud rates +========== + +The rev 1.2 and below boards use a CL-CD1864. These chips can only +do 64kbit. The rev 1.3 and newer boards use a CL-CD1865. These chips +are officially capable of 115k2. + +The Specialix card uses a 25MHz crystal (in times two mode, which in +fact is a divided by two mode). This is not enough to reach the rated +115k2 on all ports at the same time. With this clock rate you can only +do 37% of this rate. This means that at 115k2 on all ports you are +going to lose characters (The chip cannot handle that many incoming +bits at this clock rate.) (Yes, you read that correctly: there is a +limit to the number of -=bits=- per second that the chip can handle.) + +If you near the "limit" you will first start to see a graceful +degradation in that the chip cannot keep the transmitter busy at all +times. However with a central clock this slow, you can also get it to +miss incoming characters. The driver will print a warning message when +you are outside the official specs. The messages usually show up in +the file /var/log/messages . + +The specialix card cannot reliably do 115k2. If you use it, you have +to do "extensive testing" (*) to verify if it actually works. + +When "mgetty" communicates with my modem at 115k2 it reports: +got: +++[0d]ATQ0V1H0[0d][0d][8a]O[cb][0d][8a] + ^^^^ ^^^^ ^^^^ + +The three characters that have the "^^^" under them have suffered a +bit error in the highest bit. In conclusion: I've tested it, and found +that it simply DOESN'T work for me. I also suspect that this is also +caused by the baud rate being just a little bit out of tune. + +I upgraded the crystal to 66Mhz on one of my Specialix cards. Works +great! Contact me for details. (Voids warranty, requires a steady hand +and more such restrictions....) + + +(*) Cirrus logic CD1864 databook, page 40. + + +Cables for the Specialix IO8+ +============================= + +The pinout of the connectors on the IO8+ is: + + pin short direction long name + name + Pin 1 DCD input Data Carrier Detect + Pin 2 RXD input Receive + Pin 3 DTR/RTS output Data Terminal Ready/Ready To Send + Pin 4 GND - Ground + Pin 5 TXD output Transmit + Pin 6 CTS input Clear To Send + + + -- 6 5 4 3 2 1 -- + | | + | | + | | + | | + +----- -----+ + |__________| + clip + + Front view of an RJ12 connector. Cable moves "into" the paper. + (the plug is ready to plug into your mouth this way...) + + + NULL cable. I don't know who is going to use these except for + testing purposes, but I tested the cards with this cable. (It + took quite a while to figure out, so I'm not going to delete + it. So there! :-) + + + This end goes This end needs + straight into the some twists in + RJ12 plug. the wiring. + IO8+ RJ12 IO8+ RJ12 + 1 DCD white - + - - 1 DCD + 2 RXD black 5 TXD + 3 DTR/RTS red 6 CTS + 4 GND green 4 GND + 5 TXD yellow 2 RXD + 6 CTS blue 3 DTR/RTS + + + Same NULL cable, but now sorted on the second column. + + 1 DCD white - + - - 1 DCD + 5 TXD yellow 2 RXD + 6 CTS blue 3 DTR/RTS + 4 GND green 4 GND + 2 RXD black 5 TXD + 3 DTR/RTS red 6 CTS + + + + This is a modem cable usable for hardware handshaking: + RJ12 DB25 DB9 + 1 DCD white 8 DCD 1 DCD + 2 RXD black 3 RXD 2 RXD + 3 DTR/RTS red 4 RTS 7 RTS + 4 GND green 7 GND 5 GND + 5 TXD yellow 2 TXD 3 TXD + 6 CTS blue 5 CTS 8 CTS + +---- 6 DSR 6 DSR + +---- 20 DTR 4 DTR + + This is a modem cable usable for software handshaking: + It allows you to reset the modem using the DTR ioctls. + I (REW) have never tested this, "but xxxxxxxxxxxxx + says that it works." If you test this, please + tell me and I'll fill in your name on the xxx's. + + RJ12 DB25 DB9 + 1 DCD white 8 DCD 1 DCD + 2 RXD black 3 RXD 2 RXD + 3 DTR/RTS red 20 DTR 4 DTR + 4 GND green 7 GND 5 GND + 5 TXD yellow 2 TXD 3 TXD + 6 CTS blue 5 CTS 8 CTS + +---- 6 DSR 6 DSR + +---- 4 RTS 7 RTS + + I bought a 6 wire flat cable. It was colored as indicated. + Check that yours is the same before you trust me on this. + + +Hardware handshaking issues. +============================ + +The driver can be told to operate in two different ways. The default +behaviour is specialix.sx_rtscts = 0 where the pin behaves as DTR when +hardware handshaking is off. It behaves as the RTS hardware +handshaking signal when hardware handshaking is selected. + +When you use this, you have to use the appropriate cable. The +cable will either be compatible with hardware handshaking or with +software handshaking. So switching on the fly is not really an +option. + +I actually prefer to use the "specialix.sx_rtscts=1" option. +This makes the DTR/RTS pin always an RTS pin, and ioctls to +change DTR are always ignored. I have a cable that is configured +for this. + + +Ports and devices +================= + +Port 0 is the one furthest from the card-edge connector. + +Devices: + +You should make the devices as follows: + +bash +cd /dev +for i in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 \ + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +do + echo -n "$i " + mknod /dev/ttyW$i c 75 $i + mknod /dev/cuw$i c 76 $i +done +echo "" + +If your system doesn't come with these devices preinstalled, bug your +linux-vendor about this. They have had ample time to get this +implemented by now. + +You cannot have more than 4 boards in one computer. The card only +supports 4 different interrupts. If you really want this, contact me +about this and I'll give you a few tips (requires soldering iron).... + +If you have enough PCI slots, you can probably use more than 4 PCI +versions of the card though.... + +The PCI version of the card cannot adhere to the mechanical part of +the PCI spec because the 8 serial connectors are simply too large. If +it doesn't fit in your computer, bring back the card. + + +------------------------------------------------------------------------ + + + Fixed bugs and restrictions: + - During initialization, interrupts are blindly turned on. + Having a shadow variable would cause an extra memory + access on every IO instruction. + - The interrupt (on the card) should be disabled when we + don't allocate the Linux end of the interrupt. This allows + a different driver/card to use it while all ports are not in + use..... (a la standard serial port) + == An extra _off variant of the sx_in and sx_out macros are + now available. They don't set the interrupt enable bit. + These are used during initialization. Normal operation uses + the old variant which enables the interrupt line. + - RTS/DTR issue needs to be implemented according to + specialix' spec. + I kind of like the "determinism" of the current + implementation. Compile time flag? + == Ok. Compile time flag! Default is how Specialix likes it. + == Now a config time flag! Gets saved in your config file. Neat! + - Can you set the IO address from the lilo command line? + If you need this, bug me about it, I'll make it. + == Hah! No bugging needed. Fixed! :-) + - Cirrus logic hasn't gotten back to me yet why the CD1865 can + and the CD1864 can't do 115k2. I suspect that this is + because the CD1864 is not rated for 33MHz operation. + Therefore the CD1864 versions of the card can't do 115k2 on + all ports just like the CD1865 versions. The driver does + not block 115k2 on CD1864 cards. + == I called the Cirrus Logic representative here in Holland. + The CD1864 databook is identical to the CD1865 databook, + except for an extra warning at the end. Similar Bit errors + have been observed in testing at 115k2 on both an 1865 and + a 1864 chip. I see no reason why I would prohibit 115k2 on + 1864 chips and not do it on 1865 chips. Actually there is + reason to prohibit it on BOTH chips. I print a warning. + If you use 115k2, you're on your own. + - A spiky CD may send spurious HUPs. Also in CLOCAL??? + -- A fix for this turned out to be counter productive. + Different fix? Current behaviour is acceptable? + -- Maybe the current implementation is correct. If anybody + gets bitten by this, please report, and it will get fixed. + + -- Testing revealed that when in CLOCAL, the problem doesn't + occur. As warned for in the CD1865 manual, the chip may + send modem intr's on a spike. We could filter those out, + but that would be a cludge anyway (You'd still risk getting + a spurious HUP when two spikes occur.)..... + + + + Bugs & restrictions: + - This is a difficult card to autoprobe. + You have to WRITE to the address register to even + read-probe a CD186x register. Disable autodetection? + -- Specialix: any suggestions? + + diff --git a/Documentation/serial/stallion.txt b/Documentation/serial/stallion.txt new file mode 100644 index 000000000000..5c4902d9a5be --- /dev/null +++ b/Documentation/serial/stallion.txt @@ -0,0 +1,392 @@ +* NOTE - This is an unmaintained driver. Lantronix, which bought Stallion +technologies, is not active in driver maintenance, and they have no information +on when or if they will have a 2.6 driver. + +James Nelson - 12-12-2004 + +Stallion Multiport Serial Driver Readme +--------------------------------------- + +Copyright (C) 1994-1999, Stallion Technologies. + +Version: 5.5.1 +Date: 28MAR99 + + + +1. INTRODUCTION + +There are two drivers that work with the different families of Stallion +multiport serial boards. One is for the Stallion smart boards - that is +EasyIO, EasyConnection 8/32 and EasyConnection 8/64-PCI, the other for +the true Stallion intelligent multiport boards - EasyConnection 8/64 +(ISA, EISA, MCA), EasyConnection/RA-PCI, ONboard and Brumby. + +If you are using any of the Stallion intelligent multiport boards (Brumby, +ONboard, EasyConnection 8/64 (ISA, EISA, MCA), EasyConnection/RA-PCI) with +Linux you will need to get the driver utility package. This contains a +firmware loader and the firmware images necessary to make the devices operate. + +The Stallion Technologies ftp site, ftp.stallion.com, will always have +the latest version of the driver utility package. + +ftp://ftp.stallion.com/drivers/ata5/Linux/ata-linux-550.tar.gz + +As of the printing of this document the latest version of the driver +utility package is 5.5.0. If a later version is now available then you +should use the latest version. + +If you are using the EasyIO, EasyConnection 8/32 or EasyConnection 8/64-PCI +boards then you don't need this package, although it does have a serial stats +display program. + +If you require DIP switch settings, EISA or MCA configuration files, or any +other information related to Stallion boards then have a look at Stallion's +web pages at http://www.stallion.com. + + + +2. INSTALLATION + +The drivers can be used as loadable modules or compiled into the kernel. +You can choose which when doing a "config" on the kernel. + +All ISA, EISA and MCA boards that you want to use need to be configured into +the driver(s). All PCI boards will be automatically detected when you load +the driver - so they do not need to be entered into the driver(s) +configuration structure. Note that kernel PCI support is required to use PCI +boards. + +There are two methods of configuring ISA, EISA and MCA boards into the drivers. +If using the driver as a loadable module then the simplest method is to pass +the driver configuration as module arguments. The other method is to modify +the driver source to add configuration lines for each board in use. + +If you have pre-built Stallion driver modules then the module argument +configuration method should be used. A lot of Linux distributions come with +pre-built driver modules in /lib/modules/X.Y.Z/misc for the kernel in use. +That makes things pretty simple to get going. + + +2.1 MODULE DRIVER CONFIGURATION: + +The simplest configuration for modules is to use the module load arguments +to configure any ISA, EISA or MCA boards. PCI boards are automatically +detected, so do not need any additional configuration at all. + +If using EasyIO, EasyConnection 8/32 ISA or MCA, or EasyConnection 8/63-PCI +boards then use the "stallion" driver module, Otherwise if you are using +an EasyConnection 8/64 ISA, EISA or MCA, EasyConnection/RA-PCI, ONboard, +Brumby or original Stallion board then use the "istallion" driver module. + +Typically to load up the smart board driver use: + + modprobe stallion + +This will load the EasyIO and EasyConnection 8/32 driver. It will output a +message to say that it loaded and print the driver version number. It will +also print out whether it found the configured boards or not. These messages +may not appear on the console, but typically are always logged to +/var/adm/messages or /var/log/syslog files - depending on how the klogd and +syslogd daemons are setup on your system. + +To load the intelligent board driver use: + + modprobe istallion + +It will output similar messages to the smart board driver. + +If not using an auto-detectable board type (that is a PCI board) then you +will also need to supply command line arguments to the modprobe command +when loading the driver. The general form of the configuration argument is + + board?=[,[,][,]] + +where: + + board? -- specifies the arbitrary board number of this board, + can be in the range 0 to 3. + + name -- textual name of this board. The board name is the common + board name, or any "shortened" version of that. The board + type number may also be used here. + + ioaddr -- specifies the I/O address of this board. This argument is + optional, but should generally be specified. + + addr -- optional second address argument. Some board types require + a second I/O address, some require a memory address. The + exact meaning of this argument depends on the board type. + + irq -- optional IRQ line used by this board. + +Up to 4 board configuration arguments can be specified on the load line. +Here is some examples: + + modprobe stallion board0=easyio,0x2a0,5 + +This configures an EasyIO board as board 0 at I/O address 0x2a0 and IRQ 5. + + modprobe istallion board3=ec8/64,0x2c0,0xcc000 + +This configures an EasyConnection 8/64 ISA as board 3 at I/O address 0x2c0 at +memory address 0xcc000. + + modprobe stallion board1=ec8/32-at,0x2a0,0x280,10 + +This configures an EasyConnection 8/32 ISA board at primary I/O address 0x2a0, +secondary address 0x280 and IRQ 10. + +You will probably want to enter this module load and configuration information +into your system startup scripts so that the drivers are loaded and configured +on each system boot. Typically the start up script would be something like +/etc/modprobe.conf. + + +2.2 STATIC DRIVER CONFIGURATION: + +For static driver configuration you need to modify the driver source code. +Entering ISA, EISA and MCA boards into the driver(s) configuration structure +involves editing the driver(s) source file. It's pretty easy if you follow +the instructions below. Both drivers can support up to 4 boards. The smart +card driver (the stallion.c driver) supports any combination of EasyIO and +EasyConnection 8/32 boards (up to a total of 4). The intelligent driver +supports any combination of ONboards, Brumbys, Stallions and EasyConnection +8/64 (ISA and EISA) boards (up to a total of 4). + +To set up the driver(s) for the boards that you want to use you need to +edit the appropriate driver file and add configuration entries. + +If using EasyIO or EasyConnection 8/32 ISA or MCA boards, + In drivers/char/stallion.c: + - find the definition of the stl_brdconf array (of structures) + near the top of the file + - modify this to match the boards you are going to install + (the comments before this structure should help) + - save and exit + +If using ONboard, Brumby, Stallion or EasyConnection 8/64 (ISA or EISA) +boards, + In drivers/char/istallion.c: + - find the definition of the stli_brdconf array (of structures) + near the top of the file + - modify this to match the boards you are going to install + (the comments before this structure should help) + - save and exit + +Once you have set up the board configurations then you are ready to build +the kernel or modules. + +When the new kernel is booted, or the loadable module loaded then the +driver will emit some kernel trace messages about whether the configured +boards were detected or not. Depending on how your system logger is set +up these may come out on the console, or just be logged to +/var/adm/messages or /var/log/syslog. You should check the messages to +confirm that all is well. + + +2.3 SHARING INTERRUPTS + +It is possible to share interrupts between multiple EasyIO and +EasyConnection 8/32 boards in an EISA system. To do this you must be using +static driver configuration, modifying the driver source code to add driver +configuration. Then a couple of extra things are required: + +1. When entering the board resources into the stallion.c file you need to + mark the boards as using level triggered interrupts. Do this by replacing + the "0" entry at field position 6 (the last field) in the board + configuration structure with a "1". (This is the structure that defines + the board type, I/O locations, etc. for each board). All boards that are + sharing an interrupt must be set this way, and each board should have the + same interrupt number specified here as well. Now build the module or + kernel as you would normally. + +2. When physically installing the boards into the system you must enter + the system EISA configuration utility. You will need to install the EISA + configuration files for *all* the EasyIO and EasyConnection 8/32 boards + that are sharing interrupts. The Stallion EasyIO and EasyConnection 8/32 + EISA configuration files required are supplied by Stallion Technologies + on the EASY Utilities floppy diskette (usually supplied in the box with + the board when purchased. If not, you can pick it up from Stallion's FTP + site, ftp.stallion.com). You will need to edit the board resources to + choose level triggered interrupts, and make sure to set each board's + interrupt to the same IRQ number. + +You must complete both the above steps for this to work. When you reboot +or load the driver your EasyIO and EasyConnection 8/32 boards will be +sharing interrupts. + + +2.4 USING HIGH SHARED MEMORY + +The EasyConnection 8/64-EI, ONboard and Stallion boards are capable of +using shared memory addresses above the usual 640K - 1Mb range. The ONboard +ISA and the Stallion boards can be programmed to use memory addresses up to +16Mb (the ISA bus addressing limit), and the EasyConnection 8/64-EI and +ONboard/E can be programmed for memory addresses up to 4Gb (the EISA bus +addressing limit). + +The higher than 1Mb memory addresses are fully supported by this driver. +Just enter the address as you normally would for a lower than 1Mb address +(in the driver's board configuration structure). + + + +2.5 TROUBLE SHOOTING + +If a board is not found by the driver but is actually in the system then the +most likely problem is that the I/O address is wrong. Change the module load +argument for the loadable module form. Or change it in the driver stallion.c +or istallion.c configuration structure and rebuild the kernel or modules, or +change it on the board. + +On EasyIO and EasyConnection 8/32 boards the IRQ is software programmable, so +if there is a conflict you may need to change the IRQ used for a board. There +are no interrupts to worry about for ONboard, Brumby or EasyConnection 8/64 +(ISA, EISA and MCA) boards. The memory region on EasyConnection 8/64 and +ONboard boards is software programmable, but not on the Brumby boards. + + + +3. USING THE DRIVERS + +3.1 INTELLIGENT DRIVER OPERATION + +The intelligent boards also need to have their "firmware" code downloaded +to them. This is done via a user level application supplied in the driver +utility package called "stlload". Compile this program wherever you dropped +the package files, by typing "make". In its simplest form you can then type + + ./stlload -i cdk.sys + +in this directory and that will download board 0 (assuming board 0 is an +EasyConnection 8/64 or EasyConnection/RA board). To download to an +ONboard, Brumby or Stallion do: + + ./stlload -i 2681.sys + +Normally you would want all boards to be downloaded as part of the standard +system startup. To achieve this, add one of the lines above into the +/etc/rc.d/rc.S or /etc/rc.d/rc.serial file. To download each board just add +the "-b " option to the line. You will need to download code for +every board. You should probably move the stlload program into a system +directory, such as /usr/sbin. Also, the default location of the cdk.sys image +file in the stlload down-loader is /usr/lib/stallion. Create that directory +and put the cdk.sys and 2681.sys files in it. (It's a convenient place to put +them anyway). As an example your /etc/rc.d/rc.S file might have the +following lines added to it (if you had 3 boards): + + /usr/sbin/stlload -b 0 -i /usr/lib/stallion/cdk.sys + /usr/sbin/stlload -b 1 -i /usr/lib/stallion/2681.sys + /usr/sbin/stlload -b 2 -i /usr/lib/stallion/2681.sys + +The image files cdk.sys and 2681.sys are specific to the board types. The +cdk.sys will only function correctly on an EasyConnection 8/64 board. Similarly +the 2681.sys image fill only operate on ONboard, Brumby and Stallion boards. +If you load the wrong image file into a board it will fail to start up, and +of course the ports will not be operational! + +If you are using the modularized version of the driver you might want to put +the modprobe calls in the startup script as well (before the download lines +obviously). + + +3.2 USING THE SERIAL PORTS + +Once the driver is installed you will need to setup some device nodes to +access the serial ports. The simplest method is to use the /dev/MAKEDEV program. +It will automatically create device entries for Stallion boards. This will +create the normal serial port devices as /dev/ttyE# where# is the port number +starting from 0. A bank of 64 minor device numbers is allocated to each board, +so the first port on the second board is port 64,etc. A set of callout type +devices may also be created. They are created as the devices /dev/cue# where # +is the same as for the ttyE devices. + +For the most part the Stallion driver tries to emulate the standard PC system +COM ports and the standard Linux serial driver. The idea is that you should +be able to use Stallion board ports and COM ports interchangeably without +modifying anything but the device name. Anything that doesn't work like that +should be considered a bug in this driver! + +If you look at the driver code you will notice that it is fairly closely +based on the Linux serial driver (linux/drivers/char/serial.c). This is +intentional, obviously this is the easiest way to emulate its behavior! + +Since this driver tries to emulate the standard serial ports as much as +possible, most system utilities should work as they do for the standard +COM ports. Most importantly "stty" works as expected and "setserial" can +also be used (excepting the ability to auto-configure the I/O and IRQ +addresses of boards). Higher baud rates are supported in the usual fashion +through setserial or using the CBAUDEX extensions. Note that the EasyIO and +EasyConnection (all types) support at least 57600 and 115200 baud. The newer +EasyConnection XP modules and new EasyIO boards support 230400 and 460800 +baud as well. The older boards including ONboard and Brumby support a +maximum baud rate of 38400. + +If you are unfamiliar with how to use serial ports, then get the Serial-HOWTO +by Greg Hankins. It will explain everything you need to know! + + + +4. NOTES + +You can use both drivers at once if you have a mix of board types installed +in a system. However to do this you will need to change the major numbers +used by one of the drivers. Currently both drivers use major numbers 24, 25 +and 28 for their devices. Change one driver to use some other major numbers, +and then modify the mkdevnods script to make device nodes based on those new +major numbers. For example, you could change the istallion.c driver to use +major numbers 60, 61 and 62. You will also need to create device nodes with +different names for the ports, for example ttyF# and cuf#. + +The original Stallion board is no longer supported by Stallion Technologies. +Although it is known to work with the istallion driver. + +Finding a free physical memory address range can be a problem. The older +boards like the Stallion and ONboard need large areas (64K or even 128K), so +they can be very difficult to get into a system. If you have 16 Mb of RAM +then you have no choice but to put them somewhere in the 640K -> 1Mb range. +ONboards require 64K, so typically 0xd0000 is good, or 0xe0000 on some +systems. If you have an original Stallion board, "V4.0" or Rev.O, then you +need a 64K memory address space, so again 0xd0000 and 0xe0000 are good. +Older Stallion boards are a much bigger problem. They need 128K of address +space and must be on a 128K boundary. If you don't have a VGA card then +0xc0000 might be usable - there is really no other place you can put them +below 1Mb. + +Both the ONboard and old Stallion boards can use higher memory addresses as +well, but you must have less than 16Mb of RAM to be able to use them. Usual +high memory addresses used include 0xec0000 and 0xf00000. + +The Brumby boards only require 16Kb of address space, so you can usually +squeeze them in somewhere. Common addresses are 0xc8000, 0xcc000, or in +the 0xd0000 range. EasyConnection 8/64 boards are even better, they only +require 4Kb of address space, again usually 0xc8000, 0xcc000 or 0xd0000 +are good. + +If you are using an EasyConnection 8/64-EI or ONboard/E then usually the +0xd0000 or 0xe0000 ranges are the best options below 1Mb. If neither of +them can be used then the high memory support to use the really high address +ranges is the best option. Typically the 2Gb range is convenient for them, +and gets them well out of the way. + +The ports of the EasyIO-8M board do not have DCD or DTR signals. So these +ports cannot be used as real modem devices. Generally, when using these +ports you should only use the cueX devices. + +The driver utility package contains a couple of very useful programs. One +is a serial port statistics collection and display program - very handy +for solving serial port problems. The other is an extended option setting +program that works with the intelligent boards. + + + +5. DISCLAIMER + +The information contained in this document is believed to be accurate and +reliable. However, no responsibility is assumed by Stallion Technologies +Pty. Ltd. for its use, nor any infringements of patents or other rights +of third parties resulting from its use. Stallion Technologies reserves +the right to modify the design of its products and will endeavour to change +the information in manuals and accompanying documentation accordingly. + diff --git a/Documentation/serial/sx.txt b/Documentation/serial/sx.txt new file mode 100644 index 000000000000..cb4efa0fb5cc --- /dev/null +++ b/Documentation/serial/sx.txt @@ -0,0 +1,294 @@ + + sx.txt -- specialix SX/SI multiport serial driver readme. + + + + Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl) + + Specialix pays for the development and support of this driver. + Please DO contact support@specialix.co.uk if you require + support. + + This driver was developed in the BitWizard linux device + driver service. If you require a linux device driver for your + product, please contact devices@BitWizard.nl for a quote. + + (History) + There used to be an SI driver by Simon Allan. This is a complete + rewrite from scratch. Just a few lines-of-code have been snatched. + + (Sources) + Specialix document number 6210028: SX Host Card and Download Code + Software Functional Specification. + + (Copying) + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of + the License, or (at your option) any later version. + + This program is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, + USA. + + (Addendum) + I'd appreciate it that if you have fixes, that you send them + to me first. + + +Introduction +============ + +This file contains some random information, that I like to have online +instead of in a manual that can get lost. Ever misplace your Linux +kernel sources? And the manual of one of the boards in your computer? + + +Theory of operation +=================== + +An important thing to know is that the driver itself doesn't have the +firmware for the card. This means that you need the separate package +"sx_firmware". For now you can get the source at + + ftp://ftp.bitwizard.nl/specialix/sx_firmware_.tgz + +The firmware load needs a "misc" device, so you'll need to enable the +"Support for user misc device modules" in your kernel configuration. +The misc device needs to be called "/dev/specialix_sxctl". It needs +misc major 10, and minor number 167 (assigned by HPA). The section +on creating device files below also creates this device. + +After loading the sx.o module into your kernel, the driver will report +the number of cards detected, but because it doesn't have any +firmware, it will not be able to determine the number of ports. Only +when you then run "sx_firmware" will the firmware be downloaded and +the rest of the driver initialized. At that time the sx_firmware +program will report the number of ports installed. + +In contrast with many other multi port serial cards, some of the data +structures are only allocated when the card knows the number of ports +that are connected. This means we won't waste memory for 120 port +descriptor structures when you only have 8 ports. If you experience +problems due to this, please report them: I haven't seen any. + + +Interrupts +========== + +A multi port serial card, would generate a horrendous amount of +interrupts if it would interrupt the CPU for every received +character. Even more than 10 years ago, the trick not to use +interrupts but to poll the serial cards was invented. + +The SX card allow us to do this two ways. First the card limits its +own interrupt rate to a rate that won't overwhelm the CPU. Secondly, +we could forget about the cards interrupt completely and use the +internal timer for this purpose. + +Polling the card can take up to a few percent of your CPU. Using the +interrupts would be better if you have most of the ports idle. Using +timer-based polling is better if your card almost always has work to +do. You save the separate interrupt in that case. + +In any case, it doesn't really matter all that much. + +The most common problem with interrupts is that for ISA cards in a PCI +system the BIOS has to be told to configure that interrupt as "legacy +ISA". Otherwise the card can pull on the interrupt line all it wants +but the CPU won't see this. + +If you can't get the interrupt to work, remember that polling mode is +more efficient (provided you actually use the card intensively). + + +Allowed Configurations +====================== + +Some configurations are disallowed. Even though at a glance they might +seem to work, they are known to lockup the bus between the host card +and the device concentrators. You should respect the drivers decision +not to support certain configurations. It's there for a reason. + +Warning: Seriously technical stuff ahead. Executive summary: Don't use +SX cards except configured at a 64k boundary. Skip the next paragraph. + +The SX cards can theoretically be placed at a 32k boundary. So for +instance you can put an SX card at 0xc8000-0xd7fff. This is not a +"recommended configuration". ISA cards have to tell the bus controller +how they like their timing. Due to timing issues they have to do this +based on which 64k window the address falls into. This means that the +32k window below and above the SX card have to use exactly the same +timing as the SX card. That reportedly works for other SX cards. But +you're still left with two useless 32k windows that should not be used +by anybody else. + + +Configuring the driver +====================== + +PCI cards are always detected. The driver auto-probes for ISA cards at +some sensible addresses. Please report if the auto-probe causes trouble +in your system, or when a card isn't detected. + +I'm afraid I haven't implemented "kernel command line parameters" yet. +This means that if the default doesn't work for you, you shouldn't use +the compiled-into-the-kernel version of the driver. Use a module +instead. If you convince me that you need this, I'll make it for +you. Deal? + +I'm afraid that the module parameters are a bit clumsy. If you have a +better idea, please tell me. + +You can specify several parameters: + + sx_poll: number of jiffies between timer-based polls. + + Set this to "0" to disable timer based polls. + Initialization of cards without a working interrupt + will fail. + + Set this to "1" if you want a polling driver. + (on Intel: 100 polls per second). If you don't use + fast baud rates, you might consider a value like "5". + (If you don't know how to do the math, use 1). + + sx_slowpoll: Number of jiffies between timer-based polls. + Set this to "100" to poll once a second. + This should get the card out of a stall if the driver + ever misses an interrupt. I've never seen this happen, + and if it does, that's a bug. Tell me. + + sx_maxints: Number of interrupts to request from the card. + The card normally limits interrupts to about 100 per + second to offload the host CPU. You can increase this + number to reduce latency on the card a little. + Note that if you give a very high number you can overload + your CPU as well as the CPU on the host card. This setting + is inaccurate and not recommended for SI cards (But it + works). + + sx_irqmask: The mask of allowable IRQs to use. I suggest you set + this to 0 (disable IRQs all together) and use polling if + the assignment of IRQs becomes problematic. This is defined + as the sum of (1 << irq) 's that you want to allow. So + sx_irqmask of 8 (1 << 3) specifies that only irq 3 may + be used by the SX driver. If you want to specify to the + driver: "Either irq 11 or 12 is ok for you to use", then + specify (1 << 11) | (1 << 12) = 0x1800 . + + sx_debug: You can enable different sorts of debug traces with this. + At "-1" all debugging traces are active. You'll get several + times more debugging output than you'll get characters + transmitted. + + +Baud rates +========== + +Theoretically new SXDCs should be capable of more than 460k +baud. However the line drivers usually give up before that. Also the +CPU on the card may not be able to handle 8 channels going at full +blast at that speed. Moreover, the buffers are not large enough to +allow operation with 100 interrupts per second. You'll have to realize +that the card has a 256 byte buffer, so you'll have to increase the +number of interrupts per second if you have more than 256*100 bytes +per second to transmit. If you do any performance testing in this +area, I'd be glad to hear from you... + +(Psst Linux users..... I think the Linux driver is more efficient than +the driver for other OSes. If you can and want to benchmark them +against each other, be my guest, and report your findings...... :-) + + +Ports and devices +================= + +Port 0 is the top connector on the module closest to the host +card. Oh, the ports on the SXDCs and TAs are labelled from 1 to 8 +instead of from 0 to 7, as they are numbered by linux. I'm stubborn in +this: I know for sure that I wouldn't be able to calculate which port +is which anymore if I would change that.... + + +Devices: + +You should make the device files as follows: + +#!/bin/sh +# (I recommend that you cut-and-paste this into a file and run that) +cd /dev +t=0 +mknod specialix_sxctl c 10 167 +while [ $t -lt 64 ] + do + echo -n "$t " + mknod ttyX$t c 32 $t + mknod cux$t c 33 $t + t=`expr $t + 1` +done +echo "" +rm /etc/psdevtab +ps > /dev/null + + +This creates 64 devices. If you have more, increase the constant on +the line with "while". The devices start at 0, as is customary on +Linux. Specialix seems to like starting the numbering at 1. + +If your system doesn't come with these devices pre-installed, bug your +linux-vendor about this. They should have these devices +"pre-installed" before the new millennium. The "ps" stuff at the end +is to "tell" ps that the new devices exist. + +Officially the maximum number of cards per computer is 4. This driver +however supports as many cards in one machine as you want. You'll run +out of interrupts after a few, but you can switch to polled operation +then. At about 256 ports (More than 8 cards), we run out of minor +device numbers. Sorry. I suggest you buy a second computer.... (Or +switch to RIO). + +------------------------------------------------------------------------ + + + Fixed bugs and restrictions: + - Hangup processing. + -- Done. + + - the write path in generic_serial (lockup / oops). + -- Done (Ugly: not the way I want it. Copied from serial.c). + + - write buffer isn't flushed at close. + -- Done. I still seem to lose a few chars at close. + Sorry. I think that this is a firmware issue. (-> Specialix) + + - drain hardware before changing termios + - Change debug on the fly. + - ISA free irq -1. (no firmware loaded). + - adding c8000 as a probe address. Added warning. + - Add a RAMtest for the RAM on the card.c + - Crash when opening a port "way" of the number of allowed ports. + (for example opening port 60 when there are only 24 ports attached) + - Sometimes the use-count strays a bit. After a few hours of + testing the use count is sometimes "3". If you are not like + me and can remember what you did to get it that way, I'd + appreciate an Email. Possibly fixed. Tell me if anyone still + sees this. + - TAs don't work right if you don't connect all the modem control + signals. SXDCs do. T225 firmware problem -> Specialix. + (Mostly fixed now, I think. Tell me if you encounter this!) + + Bugs & restrictions: + + - Arbitrary baud rates. Requires firmware update. (-> Specialix) + + - Low latency (mostly firmware, -> Specialix) + + + diff --git a/Documentation/serial/tty.txt b/Documentation/serial/tty.txt new file mode 100644 index 000000000000..8e65c4498c52 --- /dev/null +++ b/Documentation/serial/tty.txt @@ -0,0 +1,292 @@ + + The Lockronomicon + +Your guide to the ancient and twisted locking policies of the tty layer and +the warped logic behind them. Beware all ye who read on. + +FIXME: still need to work out the full set of BKL assumptions and document +them so they can eventually be killed off. + + +Line Discipline +--------------- + +Line disciplines are registered with tty_register_ldisc() passing the +discipline number and the ldisc structure. At the point of registration the +discipline must be ready to use and it is possible it will get used before +the call returns success. If the call returns an error then it won't get +called. Do not re-use ldisc numbers as they are part of the userspace ABI +and writing over an existing ldisc will cause demons to eat your computer. +After the return the ldisc data has been copied so you may free your own +copy of the structure. You must not re-register over the top of the line +discipline even with the same data or your computer again will be eaten by +demons. + +In order to remove a line discipline call tty_unregister_ldisc(). +In ancient times this always worked. In modern times the function will +return -EBUSY if the ldisc is currently in use. Since the ldisc referencing +code manages the module counts this should not usually be a concern. + +Heed this warning: the reference count field of the registered copies of the +tty_ldisc structure in the ldisc table counts the number of lines using this +discipline. The reference count of the tty_ldisc structure within a tty +counts the number of active users of the ldisc at this instant. In effect it +counts the number of threads of execution within an ldisc method (plus those +about to enter and exit although this detail matters not). + +Line Discipline Methods +----------------------- + +TTY side interfaces: + +open() - Called when the line discipline is attached to + the terminal. No other call into the line + discipline for this tty will occur until it + completes successfully. Can sleep. + +close() - This is called on a terminal when the line + discipline is being unplugged. At the point of + execution no further users will enter the + ldisc code for this tty. Can sleep. + +hangup() - Called when the tty line is hung up. + The line discipline should cease I/O to the tty. + No further calls into the ldisc code will occur. + Can sleep. + +write() - A process is writing data through the line + discipline. Multiple write calls are serialized + by the tty layer for the ldisc. May sleep. + +flush_buffer() - (optional) May be called at any point between + open and close, and instructs the line discipline + to empty its input buffer. + +chars_in_buffer() - (optional) Report the number of bytes in the input + buffer. + +set_termios() - (optional) Called on termios structure changes. + The caller passes the old termios data and the + current data is in the tty. Called under the + termios semaphore so allowed to sleep. Serialized + against itself only. + +read() - Move data from the line discipline to the user. + Multiple read calls may occur in parallel and the + ldisc must deal with serialization issues. May + sleep. + +poll() - Check the status for the poll/select calls. Multiple + poll calls may occur in parallel. May sleep. + +ioctl() - Called when an ioctl is handed to the tty layer + that might be for the ldisc. Multiple ioctl calls + may occur in parallel. May sleep. + +Driver Side Interfaces: + +receive_buf() - Hand buffers of bytes from the driver to the ldisc + for processing. Semantics currently rather + mysterious 8( + +write_wakeup() - May be called at any point between open and close. + The TTY_DO_WRITE_WAKEUP flag indicates if a call + is needed but always races versus calls. Thus the + ldisc must be careful about setting order and to + handle unexpected calls. Must not sleep. + + The driver is forbidden from calling this directly + from the ->write call from the ldisc as the ldisc + is permitted to call the driver write method from + this function. In such a situation defer it. + + +Driver Access + +Line discipline methods can call the following methods of the underlying +hardware driver through the function pointers within the tty->driver +structure: + +write() Write a block of characters to the tty device. + Returns the number of characters accepted. The + character buffer passed to this method is already + in kernel space. + +put_char() Queues a character for writing to the tty device. + If there is no room in the queue, the character is + ignored. + +flush_chars() (Optional) If defined, must be called after + queueing characters with put_char() in order to + start transmission. + +write_room() Returns the numbers of characters the tty driver + will accept for queueing to be written. + +ioctl() Invoke device specific ioctl. + Expects data pointers to refer to userspace. + Returns ENOIOCTLCMD for unrecognized ioctl numbers. + +set_termios() Notify the tty driver that the device's termios + settings have changed. New settings are in + tty->termios. Previous settings should be passed in + the "old" argument. + + The API is defined such that the driver should return + the actual modes selected. This means that the + driver function is responsible for modifying any + bits in the request it cannot fulfill to indicate + the actual modes being used. A device with no + hardware capability for change (eg a USB dongle or + virtual port) can provide NULL for this method. + +throttle() Notify the tty driver that input buffers for the + line discipline are close to full, and it should + somehow signal that no more characters should be + sent to the tty. + +unthrottle() Notify the tty driver that characters can now be + sent to the tty without fear of overrunning the + input buffers of the line disciplines. + +stop() Ask the tty driver to stop outputting characters + to the tty device. + +start() Ask the tty driver to resume sending characters + to the tty device. + +hangup() Ask the tty driver to hang up the tty device. + +break_ctl() (Optional) Ask the tty driver to turn on or off + BREAK status on the RS-232 port. If state is -1, + then the BREAK status should be turned on; if + state is 0, then BREAK should be turned off. + If this routine is not implemented, use ioctls + TIOCSBRK / TIOCCBRK instead. + +wait_until_sent() Waits until the device has written out all of the + characters in its transmitter FIFO. + +send_xchar() Send a high-priority XON/XOFF character to the device. + + +Flags + +Line discipline methods have access to tty->flags field containing the +following interesting flags: + +TTY_THROTTLED Driver input is throttled. The ldisc should call + tty->driver->unthrottle() in order to resume + reception when it is ready to process more data. + +TTY_DO_WRITE_WAKEUP If set, causes the driver to call the ldisc's + write_wakeup() method in order to resume + transmission when it can accept more data + to transmit. + +TTY_IO_ERROR If set, causes all subsequent userspace read/write + calls on the tty to fail, returning -EIO. + +TTY_OTHER_CLOSED Device is a pty and the other side has closed. + +TTY_NO_WRITE_SPLIT Prevent driver from splitting up writes into + smaller chunks. + + +Locking + +Callers to the line discipline functions from the tty layer are required to +take line discipline locks. The same is true of calls from the driver side +but not yet enforced. + +Three calls are now provided + + ldisc = tty_ldisc_ref(tty); + +takes a handle to the line discipline in the tty and returns it. If no ldisc +is currently attached or the ldisc is being closed and re-opened at this +point then NULL is returned. While this handle is held the ldisc will not +change or go away. + + tty_ldisc_deref(ldisc) + +Returns the ldisc reference and allows the ldisc to be closed. Returning the +reference takes away your right to call the ldisc functions until you take +a new reference. + + ldisc = tty_ldisc_ref_wait(tty); + +Performs the same function as tty_ldisc_ref except that it will wait for an +ldisc change to complete and then return a reference to the new ldisc. + +While these functions are slightly slower than the old code they should have +minimal impact as most receive logic uses the flip buffers and they only +need to take a reference when they push bits up through the driver. + +A caution: The ldisc->open(), ldisc->close() and driver->set_ldisc +functions are called with the ldisc unavailable. Thus tty_ldisc_ref will +fail in this situation if used within these functions. Ldisc and driver +code calling its own functions must be careful in this case. + + +Driver Interface +---------------- + +open() - Called when a device is opened. May sleep + +close() - Called when a device is closed. At the point of + return from this call the driver must make no + further ldisc calls of any kind. May sleep + +write() - Called to write bytes to the device. May not + sleep. May occur in parallel in special cases. + Because this includes panic paths drivers generally + shouldn't try and do clever locking here. + +put_char() - Stuff a single character onto the queue. The + driver is guaranteed following up calls to + flush_chars. + +flush_chars() - Ask the kernel to write put_char queue + +write_room() - Return the number of characters tht can be stuffed + into the port buffers without overflow (or less). + The ldisc is responsible for being intelligent + about multi-threading of write_room/write calls + +ioctl() - Called when an ioctl may be for the driver + +set_termios() - Called on termios change, serialized against + itself by a semaphore. May sleep. + +set_ldisc() - Notifier for discipline change. At the point this + is done the discipline is not yet usable. Can now + sleep (I think) + +throttle() - Called by the ldisc to ask the driver to do flow + control. Serialization including with unthrottle + is the job of the ldisc layer. + +unthrottle() - Called by the ldisc to ask the driver to stop flow + control. + +stop() - Ldisc notifier to the driver to stop output. As with + throttle the serializations with start() are down + to the ldisc layer. + +start() - Ldisc notifier to the driver to start output. + +hangup() - Ask the tty driver to cause a hangup initiated + from the host side. [Can sleep ??] + +break_ctl() - Send RS232 break. Can sleep. Can get called in + parallel, driver must serialize (for now), and + with write calls. + +wait_until_sent() - Wait for characters to exit the hardware queue + of the driver. Can sleep + +send_xchar() - Send XON/XOFF and if possible jump the queue with + it in order to get fast flow control responses. + Cannot sleep ?? + diff --git a/Documentation/sh/new-machine.txt b/Documentation/sh/new-machine.txt index 5482bf5d005b..f0354164cb0e 100644 --- a/Documentation/sh/new-machine.txt +++ b/Documentation/sh/new-machine.txt @@ -47,9 +47,7 @@ Next, for companion chips: `-- sh `-- cchips `-- hd6446x - |-- hd64461 - | `-- cchip-specific files - `-- hd64465 + `-- hd64461 `-- cchip-specific files ... and so on. Headers for the companion chips are treated the same way as diff --git a/Documentation/sound/alsa/ALSA-Configuration.txt b/Documentation/sound/alsa/ALSA-Configuration.txt index e0e54a27fc10..394d7d378dc7 100644 --- a/Documentation/sound/alsa/ALSA-Configuration.txt +++ b/Documentation/sound/alsa/ALSA-Configuration.txt @@ -1063,6 +1063,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. STAC9227/9228/9229/927x ref Reference board + ref-no-jd Reference board without HP/Mic jack detection 3stack D965 3stack 5stack D965 5stack + SPDIF dell-3stack Dell Dimension E520 @@ -1072,10 +1073,14 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. ref Reference board dell-m4-1 Dell desktops dell-m4-2 Dell desktops + dell-m4-3 Dell desktops STAC92HD73* ref Reference board - dell-m6 Dell desktops + no-jd BIOS setup but without jack-detection + dell-m6-amic Dell desktops/laptops with analog mics + dell-m6-dmic Dell desktops/laptops with digital mics + dell-m6 Dell desktops/laptops with both type of mics STAC9872 vaio Setup for VAIO FE550G/SZ110 diff --git a/Documentation/specialix.txt b/Documentation/specialix.txt deleted file mode 100644 index 6eb6f3a3331c..000000000000 --- a/Documentation/specialix.txt +++ /dev/null @@ -1,383 +0,0 @@ - - specialix.txt -- specialix IO8+ multiport serial driver readme. - - - - Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl) - - Specialix pays for the development and support of this driver. - Please DO contact io8-linux@specialix.co.uk if you require - support. - - This driver was developed in the BitWizard linux device - driver service. If you require a linux device driver for your - product, please contact devices@BitWizard.nl for a quote. - - This code is firmly based on the riscom/8 serial driver, - written by Dmitry Gorodchanin. The specialix IO8+ card - programming information was obtained from the CL-CD1865 Data - Book, and Specialix document number 6200059: IO8+ Hardware - Functional Specification, augmented by document number 6200088: - Merak Hardware Functional Specification. (IO8+/PCI is also - called Merak) - - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of - the License, or (at your option) any later version. - - This program is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU General Public License for more details. - - You should have received a copy of the GNU General Public - License along with this program; if not, write to the Free - Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, - USA. - - -Intro -===== - - -This file contains some random information, that I like to have online -instead of in a manual that can get lost. Ever misplace your Linux -kernel sources? And the manual of one of the boards in your computer? - - -Addresses and interrupts -======================== - -Address dip switch settings: -The dip switch sets bits 2-9 of the IO address. - - 9 8 7 6 5 4 3 2 - +-----------------+ - 0 | X X X X X X X | - | | = IoBase = 0x100 - 1 | X | - +-----------------+ ------ RS232 connectors ----> - - | | | - edge connector - | | | - V V V - -Base address 0x100 caused a conflict in one of my computers once. I -haven't the foggiest why. My Specialix card is now at 0x180. My -other computer runs just fine with the Specialix card at 0x100.... -The card occupies 4 addresses, but actually only two are really used. - -The PCI version doesn't have any dip switches. The BIOS assigns -an IO address. - -The driver now still autoprobes at 0x100, 0x180, 0x250 and 0x260. If -that causes trouble for you, please report that. I'll remove -autoprobing then. - -The driver will tell the card what IRQ to use, so you don't have to -change any jumpers to change the IRQ. Just use a command line -argument (irq=xx) to the insmod program to set the interrupt. - -The BIOS assigns the IRQ on the PCI version. You have no say in what -IRQ to use in that case. - -If your specialix cards are not at the default locations, you can use -the kernel command line argument "specialix=io0,irq0,io1,irq1...". -Here "io0" is the io address for the first card, and "irq0" is the -irq line that the first card should use. And so on. - -Examples. - -You use the driver as a module and have three cards at 0x100, 0x250 -and 0x180. And some way or another you want them detected in that -order. Moreover irq 12 is taken (e.g. by your PS/2 mouse). - - insmod specialix.o iobase=0x100,0x250,0x180 irq=9,11,15 - -The same three cards, but now in the kernel would require you to -add - - specialix=0x100,9,0x250,11,0x180,15 - -to the command line. This would become - - append="specialix=0x100,9,0x250,11,0x180,15" - -in your /etc/lilo.conf file if you use lilo. - -The Specialix driver is slightly odd: It allows you to have the second -or third card detected without having a first card. This has -advantages and disadvantages. A slot that isn't filled by an ISA card, -might be filled if a PCI card is detected. Thus if you have an ISA -card at 0x250 and a PCI card, you would get: - -sx0: specialix IO8+ Board at 0x100 not found. -sx1: specialix IO8+ Board at 0x180 not found. -sx2: specialix IO8+ board detected at 0x250, IRQ 12, CD1865 Rev. B. -sx3: specialix IO8+ Board at 0x260 not found. -sx0: specialix IO8+ board detected at 0xd800, IRQ 9, CD1865 Rev. B. - -This would happen if you don't give any probe hints to the driver. -If you would specify: - - specialix=0x250,11 - -you'd get the following messages: - -sx0: specialix IO8+ board detected at 0x250, IRQ 11, CD1865 Rev. B. -sx1: specialix IO8+ board detected at 0xd800, IRQ 9, CD1865 Rev. B. - -ISA probing is aborted after the IO address you gave is exhausted, and -the PCI card is now detected as the second card. The ISA card is now -also forced to IRQ11.... - - -Baud rates -========== - -The rev 1.2 and below boards use a CL-CD1864. These chips can only -do 64kbit. The rev 1.3 and newer boards use a CL-CD1865. These chips -are officially capable of 115k2. - -The Specialix card uses a 25MHz crystal (in times two mode, which in -fact is a divided by two mode). This is not enough to reach the rated -115k2 on all ports at the same time. With this clock rate you can only -do 37% of this rate. This means that at 115k2 on all ports you are -going to lose characters (The chip cannot handle that many incoming -bits at this clock rate.) (Yes, you read that correctly: there is a -limit to the number of -=bits=- per second that the chip can handle.) - -If you near the "limit" you will first start to see a graceful -degradation in that the chip cannot keep the transmitter busy at all -times. However with a central clock this slow, you can also get it to -miss incoming characters. The driver will print a warning message when -you are outside the official specs. The messages usually show up in -the file /var/log/messages . - -The specialix card cannot reliably do 115k2. If you use it, you have -to do "extensive testing" (*) to verify if it actually works. - -When "mgetty" communicates with my modem at 115k2 it reports: -got: +++[0d]ATQ0V1H0[0d][0d][8a]O[cb][0d][8a] - ^^^^ ^^^^ ^^^^ - -The three characters that have the "^^^" under them have suffered a -bit error in the highest bit. In conclusion: I've tested it, and found -that it simply DOESN'T work for me. I also suspect that this is also -caused by the baud rate being just a little bit out of tune. - -I upgraded the crystal to 66Mhz on one of my Specialix cards. Works -great! Contact me for details. (Voids warranty, requires a steady hand -and more such restrictions....) - - -(*) Cirrus logic CD1864 databook, page 40. - - -Cables for the Specialix IO8+ -============================= - -The pinout of the connectors on the IO8+ is: - - pin short direction long name - name - Pin 1 DCD input Data Carrier Detect - Pin 2 RXD input Receive - Pin 3 DTR/RTS output Data Terminal Ready/Ready To Send - Pin 4 GND - Ground - Pin 5 TXD output Transmit - Pin 6 CTS input Clear To Send - - - -- 6 5 4 3 2 1 -- - | | - | | - | | - | | - +----- -----+ - |__________| - clip - - Front view of an RJ12 connector. Cable moves "into" the paper. - (the plug is ready to plug into your mouth this way...) - - - NULL cable. I don't know who is going to use these except for - testing purposes, but I tested the cards with this cable. (It - took quite a while to figure out, so I'm not going to delete - it. So there! :-) - - - This end goes This end needs - straight into the some twists in - RJ12 plug. the wiring. - IO8+ RJ12 IO8+ RJ12 - 1 DCD white - - - - 1 DCD - 2 RXD black 5 TXD - 3 DTR/RTS red 6 CTS - 4 GND green 4 GND - 5 TXD yellow 2 RXD - 6 CTS blue 3 DTR/RTS - - - Same NULL cable, but now sorted on the second column. - - 1 DCD white - - - - 1 DCD - 5 TXD yellow 2 RXD - 6 CTS blue 3 DTR/RTS - 4 GND green 4 GND - 2 RXD black 5 TXD - 3 DTR/RTS red 6 CTS - - - - This is a modem cable usable for hardware handshaking: - RJ12 DB25 DB9 - 1 DCD white 8 DCD 1 DCD - 2 RXD black 3 RXD 2 RXD - 3 DTR/RTS red 4 RTS 7 RTS - 4 GND green 7 GND 5 GND - 5 TXD yellow 2 TXD 3 TXD - 6 CTS blue 5 CTS 8 CTS - +---- 6 DSR 6 DSR - +---- 20 DTR 4 DTR - - This is a modem cable usable for software handshaking: - It allows you to reset the modem using the DTR ioctls. - I (REW) have never tested this, "but xxxxxxxxxxxxx - says that it works." If you test this, please - tell me and I'll fill in your name on the xxx's. - - RJ12 DB25 DB9 - 1 DCD white 8 DCD 1 DCD - 2 RXD black 3 RXD 2 RXD - 3 DTR/RTS red 20 DTR 4 DTR - 4 GND green 7 GND 5 GND - 5 TXD yellow 2 TXD 3 TXD - 6 CTS blue 5 CTS 8 CTS - +---- 6 DSR 6 DSR - +---- 4 RTS 7 RTS - - I bought a 6 wire flat cable. It was colored as indicated. - Check that yours is the same before you trust me on this. - - -Hardware handshaking issues. -============================ - -The driver can be told to operate in two different ways. The default -behaviour is specialix.sx_rtscts = 0 where the pin behaves as DTR when -hardware handshaking is off. It behaves as the RTS hardware -handshaking signal when hardware handshaking is selected. - -When you use this, you have to use the appropriate cable. The -cable will either be compatible with hardware handshaking or with -software handshaking. So switching on the fly is not really an -option. - -I actually prefer to use the "specialix.sx_rtscts=1" option. -This makes the DTR/RTS pin always an RTS pin, and ioctls to -change DTR are always ignored. I have a cable that is configured -for this. - - -Ports and devices -================= - -Port 0 is the one furthest from the card-edge connector. - -Devices: - -You should make the devices as follows: - -bash -cd /dev -for i in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 \ - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -do - echo -n "$i " - mknod /dev/ttyW$i c 75 $i - mknod /dev/cuw$i c 76 $i -done -echo "" - -If your system doesn't come with these devices preinstalled, bug your -linux-vendor about this. They have had ample time to get this -implemented by now. - -You cannot have more than 4 boards in one computer. The card only -supports 4 different interrupts. If you really want this, contact me -about this and I'll give you a few tips (requires soldering iron).... - -If you have enough PCI slots, you can probably use more than 4 PCI -versions of the card though.... - -The PCI version of the card cannot adhere to the mechanical part of -the PCI spec because the 8 serial connectors are simply too large. If -it doesn't fit in your computer, bring back the card. - - ------------------------------------------------------------------------- - - - Fixed bugs and restrictions: - - During initialization, interrupts are blindly turned on. - Having a shadow variable would cause an extra memory - access on every IO instruction. - - The interrupt (on the card) should be disabled when we - don't allocate the Linux end of the interrupt. This allows - a different driver/card to use it while all ports are not in - use..... (a la standard serial port) - == An extra _off variant of the sx_in and sx_out macros are - now available. They don't set the interrupt enable bit. - These are used during initialization. Normal operation uses - the old variant which enables the interrupt line. - - RTS/DTR issue needs to be implemented according to - specialix' spec. - I kind of like the "determinism" of the current - implementation. Compile time flag? - == Ok. Compile time flag! Default is how Specialix likes it. - == Now a config time flag! Gets saved in your config file. Neat! - - Can you set the IO address from the lilo command line? - If you need this, bug me about it, I'll make it. - == Hah! No bugging needed. Fixed! :-) - - Cirrus logic hasn't gotten back to me yet why the CD1865 can - and the CD1864 can't do 115k2. I suspect that this is - because the CD1864 is not rated for 33MHz operation. - Therefore the CD1864 versions of the card can't do 115k2 on - all ports just like the CD1865 versions. The driver does - not block 115k2 on CD1864 cards. - == I called the Cirrus Logic representative here in Holland. - The CD1864 databook is identical to the CD1865 databook, - except for an extra warning at the end. Similar Bit errors - have been observed in testing at 115k2 on both an 1865 and - a 1864 chip. I see no reason why I would prohibit 115k2 on - 1864 chips and not do it on 1865 chips. Actually there is - reason to prohibit it on BOTH chips. I print a warning. - If you use 115k2, you're on your own. - - A spiky CD may send spurious HUPs. Also in CLOCAL??? - -- A fix for this turned out to be counter productive. - Different fix? Current behaviour is acceptable? - -- Maybe the current implementation is correct. If anybody - gets bitten by this, please report, and it will get fixed. - - -- Testing revealed that when in CLOCAL, the problem doesn't - occur. As warned for in the CD1865 manual, the chip may - send modem intr's on a spike. We could filter those out, - but that would be a cludge anyway (You'd still risk getting - a spurious HUP when two spikes occur.)..... - - - - Bugs & restrictions: - - This is a difficult card to autoprobe. - You have to WRITE to the address register to even - read-probe a CD186x register. Disable autodetection? - -- Specialix: any suggestions? - - diff --git a/Documentation/spi/.gitignore b/Documentation/spi/.gitignore new file mode 100644 index 000000000000..4280576397e8 --- /dev/null +++ b/Documentation/spi/.gitignore @@ -0,0 +1,2 @@ +spidev_fdx +spidev_test diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary index 8bae2f018d34..0f5122eb282b 100644 --- a/Documentation/spi/spi-summary +++ b/Documentation/spi/spi-summary @@ -215,7 +215,7 @@ So for example arch/.../mach-*/board-*.c files might have code like: /* if your mach-* infrastructure doesn't support kernels that can * run on multiple boards, pdata wouldn't benefit from "__init". */ - static struct mysoc_spi_data __init pdata = { ... }; + static struct mysoc_spi_data __initdata pdata = { ... }; static __init board_init(void) { diff --git a/Documentation/stable_kernel_rules.txt b/Documentation/stable_kernel_rules.txt index 4cfc78835bc1..a452227361b1 100644 --- a/Documentation/stable_kernel_rules.txt +++ b/Documentation/stable_kernel_rules.txt @@ -12,6 +12,7 @@ Rules on what kind of patches are accepted, and which ones are not, into the marked CONFIG_BROKEN), an oops, a hang, data corruption, a real security issue, or some "oh, that's not good" issue. In short, something critical. + - New device IDs and quirks are also accepted. - No "theoretical race condition" issues, unless an explanation of how the race can be exploited is also provided. - It cannot contain any "trivial" fixes in it (spelling changes, diff --git a/Documentation/stallion.txt b/Documentation/stallion.txt deleted file mode 100644 index 5c4902d9a5be..000000000000 --- a/Documentation/stallion.txt +++ /dev/null @@ -1,392 +0,0 @@ -* NOTE - This is an unmaintained driver. Lantronix, which bought Stallion -technologies, is not active in driver maintenance, and they have no information -on when or if they will have a 2.6 driver. - -James Nelson - 12-12-2004 - -Stallion Multiport Serial Driver Readme ---------------------------------------- - -Copyright (C) 1994-1999, Stallion Technologies. - -Version: 5.5.1 -Date: 28MAR99 - - - -1. INTRODUCTION - -There are two drivers that work with the different families of Stallion -multiport serial boards. One is for the Stallion smart boards - that is -EasyIO, EasyConnection 8/32 and EasyConnection 8/64-PCI, the other for -the true Stallion intelligent multiport boards - EasyConnection 8/64 -(ISA, EISA, MCA), EasyConnection/RA-PCI, ONboard and Brumby. - -If you are using any of the Stallion intelligent multiport boards (Brumby, -ONboard, EasyConnection 8/64 (ISA, EISA, MCA), EasyConnection/RA-PCI) with -Linux you will need to get the driver utility package. This contains a -firmware loader and the firmware images necessary to make the devices operate. - -The Stallion Technologies ftp site, ftp.stallion.com, will always have -the latest version of the driver utility package. - -ftp://ftp.stallion.com/drivers/ata5/Linux/ata-linux-550.tar.gz - -As of the printing of this document the latest version of the driver -utility package is 5.5.0. If a later version is now available then you -should use the latest version. - -If you are using the EasyIO, EasyConnection 8/32 or EasyConnection 8/64-PCI -boards then you don't need this package, although it does have a serial stats -display program. - -If you require DIP switch settings, EISA or MCA configuration files, or any -other information related to Stallion boards then have a look at Stallion's -web pages at http://www.stallion.com. - - - -2. INSTALLATION - -The drivers can be used as loadable modules or compiled into the kernel. -You can choose which when doing a "config" on the kernel. - -All ISA, EISA and MCA boards that you want to use need to be configured into -the driver(s). All PCI boards will be automatically detected when you load -the driver - so they do not need to be entered into the driver(s) -configuration structure. Note that kernel PCI support is required to use PCI -boards. - -There are two methods of configuring ISA, EISA and MCA boards into the drivers. -If using the driver as a loadable module then the simplest method is to pass -the driver configuration as module arguments. The other method is to modify -the driver source to add configuration lines for each board in use. - -If you have pre-built Stallion driver modules then the module argument -configuration method should be used. A lot of Linux distributions come with -pre-built driver modules in /lib/modules/X.Y.Z/misc for the kernel in use. -That makes things pretty simple to get going. - - -2.1 MODULE DRIVER CONFIGURATION: - -The simplest configuration for modules is to use the module load arguments -to configure any ISA, EISA or MCA boards. PCI boards are automatically -detected, so do not need any additional configuration at all. - -If using EasyIO, EasyConnection 8/32 ISA or MCA, or EasyConnection 8/63-PCI -boards then use the "stallion" driver module, Otherwise if you are using -an EasyConnection 8/64 ISA, EISA or MCA, EasyConnection/RA-PCI, ONboard, -Brumby or original Stallion board then use the "istallion" driver module. - -Typically to load up the smart board driver use: - - modprobe stallion - -This will load the EasyIO and EasyConnection 8/32 driver. It will output a -message to say that it loaded and print the driver version number. It will -also print out whether it found the configured boards or not. These messages -may not appear on the console, but typically are always logged to -/var/adm/messages or /var/log/syslog files - depending on how the klogd and -syslogd daemons are setup on your system. - -To load the intelligent board driver use: - - modprobe istallion - -It will output similar messages to the smart board driver. - -If not using an auto-detectable board type (that is a PCI board) then you -will also need to supply command line arguments to the modprobe command -when loading the driver. The general form of the configuration argument is - - board?=[,[,][,]] - -where: - - board? -- specifies the arbitrary board number of this board, - can be in the range 0 to 3. - - name -- textual name of this board. The board name is the common - board name, or any "shortened" version of that. The board - type number may also be used here. - - ioaddr -- specifies the I/O address of this board. This argument is - optional, but should generally be specified. - - addr -- optional second address argument. Some board types require - a second I/O address, some require a memory address. The - exact meaning of this argument depends on the board type. - - irq -- optional IRQ line used by this board. - -Up to 4 board configuration arguments can be specified on the load line. -Here is some examples: - - modprobe stallion board0=easyio,0x2a0,5 - -This configures an EasyIO board as board 0 at I/O address 0x2a0 and IRQ 5. - - modprobe istallion board3=ec8/64,0x2c0,0xcc000 - -This configures an EasyConnection 8/64 ISA as board 3 at I/O address 0x2c0 at -memory address 0xcc000. - - modprobe stallion board1=ec8/32-at,0x2a0,0x280,10 - -This configures an EasyConnection 8/32 ISA board at primary I/O address 0x2a0, -secondary address 0x280 and IRQ 10. - -You will probably want to enter this module load and configuration information -into your system startup scripts so that the drivers are loaded and configured -on each system boot. Typically the start up script would be something like -/etc/modprobe.conf. - - -2.2 STATIC DRIVER CONFIGURATION: - -For static driver configuration you need to modify the driver source code. -Entering ISA, EISA and MCA boards into the driver(s) configuration structure -involves editing the driver(s) source file. It's pretty easy if you follow -the instructions below. Both drivers can support up to 4 boards. The smart -card driver (the stallion.c driver) supports any combination of EasyIO and -EasyConnection 8/32 boards (up to a total of 4). The intelligent driver -supports any combination of ONboards, Brumbys, Stallions and EasyConnection -8/64 (ISA and EISA) boards (up to a total of 4). - -To set up the driver(s) for the boards that you want to use you need to -edit the appropriate driver file and add configuration entries. - -If using EasyIO or EasyConnection 8/32 ISA or MCA boards, - In drivers/char/stallion.c: - - find the definition of the stl_brdconf array (of structures) - near the top of the file - - modify this to match the boards you are going to install - (the comments before this structure should help) - - save and exit - -If using ONboard, Brumby, Stallion or EasyConnection 8/64 (ISA or EISA) -boards, - In drivers/char/istallion.c: - - find the definition of the stli_brdconf array (of structures) - near the top of the file - - modify this to match the boards you are going to install - (the comments before this structure should help) - - save and exit - -Once you have set up the board configurations then you are ready to build -the kernel or modules. - -When the new kernel is booted, or the loadable module loaded then the -driver will emit some kernel trace messages about whether the configured -boards were detected or not. Depending on how your system logger is set -up these may come out on the console, or just be logged to -/var/adm/messages or /var/log/syslog. You should check the messages to -confirm that all is well. - - -2.3 SHARING INTERRUPTS - -It is possible to share interrupts between multiple EasyIO and -EasyConnection 8/32 boards in an EISA system. To do this you must be using -static driver configuration, modifying the driver source code to add driver -configuration. Then a couple of extra things are required: - -1. When entering the board resources into the stallion.c file you need to - mark the boards as using level triggered interrupts. Do this by replacing - the "0" entry at field position 6 (the last field) in the board - configuration structure with a "1". (This is the structure that defines - the board type, I/O locations, etc. for each board). All boards that are - sharing an interrupt must be set this way, and each board should have the - same interrupt number specified here as well. Now build the module or - kernel as you would normally. - -2. When physically installing the boards into the system you must enter - the system EISA configuration utility. You will need to install the EISA - configuration files for *all* the EasyIO and EasyConnection 8/32 boards - that are sharing interrupts. The Stallion EasyIO and EasyConnection 8/32 - EISA configuration files required are supplied by Stallion Technologies - on the EASY Utilities floppy diskette (usually supplied in the box with - the board when purchased. If not, you can pick it up from Stallion's FTP - site, ftp.stallion.com). You will need to edit the board resources to - choose level triggered interrupts, and make sure to set each board's - interrupt to the same IRQ number. - -You must complete both the above steps for this to work. When you reboot -or load the driver your EasyIO and EasyConnection 8/32 boards will be -sharing interrupts. - - -2.4 USING HIGH SHARED MEMORY - -The EasyConnection 8/64-EI, ONboard and Stallion boards are capable of -using shared memory addresses above the usual 640K - 1Mb range. The ONboard -ISA and the Stallion boards can be programmed to use memory addresses up to -16Mb (the ISA bus addressing limit), and the EasyConnection 8/64-EI and -ONboard/E can be programmed for memory addresses up to 4Gb (the EISA bus -addressing limit). - -The higher than 1Mb memory addresses are fully supported by this driver. -Just enter the address as you normally would for a lower than 1Mb address -(in the driver's board configuration structure). - - - -2.5 TROUBLE SHOOTING - -If a board is not found by the driver but is actually in the system then the -most likely problem is that the I/O address is wrong. Change the module load -argument for the loadable module form. Or change it in the driver stallion.c -or istallion.c configuration structure and rebuild the kernel or modules, or -change it on the board. - -On EasyIO and EasyConnection 8/32 boards the IRQ is software programmable, so -if there is a conflict you may need to change the IRQ used for a board. There -are no interrupts to worry about for ONboard, Brumby or EasyConnection 8/64 -(ISA, EISA and MCA) boards. The memory region on EasyConnection 8/64 and -ONboard boards is software programmable, but not on the Brumby boards. - - - -3. USING THE DRIVERS - -3.1 INTELLIGENT DRIVER OPERATION - -The intelligent boards also need to have their "firmware" code downloaded -to them. This is done via a user level application supplied in the driver -utility package called "stlload". Compile this program wherever you dropped -the package files, by typing "make". In its simplest form you can then type - - ./stlload -i cdk.sys - -in this directory and that will download board 0 (assuming board 0 is an -EasyConnection 8/64 or EasyConnection/RA board). To download to an -ONboard, Brumby or Stallion do: - - ./stlload -i 2681.sys - -Normally you would want all boards to be downloaded as part of the standard -system startup. To achieve this, add one of the lines above into the -/etc/rc.d/rc.S or /etc/rc.d/rc.serial file. To download each board just add -the "-b " option to the line. You will need to download code for -every board. You should probably move the stlload program into a system -directory, such as /usr/sbin. Also, the default location of the cdk.sys image -file in the stlload down-loader is /usr/lib/stallion. Create that directory -and put the cdk.sys and 2681.sys files in it. (It's a convenient place to put -them anyway). As an example your /etc/rc.d/rc.S file might have the -following lines added to it (if you had 3 boards): - - /usr/sbin/stlload -b 0 -i /usr/lib/stallion/cdk.sys - /usr/sbin/stlload -b 1 -i /usr/lib/stallion/2681.sys - /usr/sbin/stlload -b 2 -i /usr/lib/stallion/2681.sys - -The image files cdk.sys and 2681.sys are specific to the board types. The -cdk.sys will only function correctly on an EasyConnection 8/64 board. Similarly -the 2681.sys image fill only operate on ONboard, Brumby and Stallion boards. -If you load the wrong image file into a board it will fail to start up, and -of course the ports will not be operational! - -If you are using the modularized version of the driver you might want to put -the modprobe calls in the startup script as well (before the download lines -obviously). - - -3.2 USING THE SERIAL PORTS - -Once the driver is installed you will need to setup some device nodes to -access the serial ports. The simplest method is to use the /dev/MAKEDEV program. -It will automatically create device entries for Stallion boards. This will -create the normal serial port devices as /dev/ttyE# where# is the port number -starting from 0. A bank of 64 minor device numbers is allocated to each board, -so the first port on the second board is port 64,etc. A set of callout type -devices may also be created. They are created as the devices /dev/cue# where # -is the same as for the ttyE devices. - -For the most part the Stallion driver tries to emulate the standard PC system -COM ports and the standard Linux serial driver. The idea is that you should -be able to use Stallion board ports and COM ports interchangeably without -modifying anything but the device name. Anything that doesn't work like that -should be considered a bug in this driver! - -If you look at the driver code you will notice that it is fairly closely -based on the Linux serial driver (linux/drivers/char/serial.c). This is -intentional, obviously this is the easiest way to emulate its behavior! - -Since this driver tries to emulate the standard serial ports as much as -possible, most system utilities should work as they do for the standard -COM ports. Most importantly "stty" works as expected and "setserial" can -also be used (excepting the ability to auto-configure the I/O and IRQ -addresses of boards). Higher baud rates are supported in the usual fashion -through setserial or using the CBAUDEX extensions. Note that the EasyIO and -EasyConnection (all types) support at least 57600 and 115200 baud. The newer -EasyConnection XP modules and new EasyIO boards support 230400 and 460800 -baud as well. The older boards including ONboard and Brumby support a -maximum baud rate of 38400. - -If you are unfamiliar with how to use serial ports, then get the Serial-HOWTO -by Greg Hankins. It will explain everything you need to know! - - - -4. NOTES - -You can use both drivers at once if you have a mix of board types installed -in a system. However to do this you will need to change the major numbers -used by one of the drivers. Currently both drivers use major numbers 24, 25 -and 28 for their devices. Change one driver to use some other major numbers, -and then modify the mkdevnods script to make device nodes based on those new -major numbers. For example, you could change the istallion.c driver to use -major numbers 60, 61 and 62. You will also need to create device nodes with -different names for the ports, for example ttyF# and cuf#. - -The original Stallion board is no longer supported by Stallion Technologies. -Although it is known to work with the istallion driver. - -Finding a free physical memory address range can be a problem. The older -boards like the Stallion and ONboard need large areas (64K or even 128K), so -they can be very difficult to get into a system. If you have 16 Mb of RAM -then you have no choice but to put them somewhere in the 640K -> 1Mb range. -ONboards require 64K, so typically 0xd0000 is good, or 0xe0000 on some -systems. If you have an original Stallion board, "V4.0" or Rev.O, then you -need a 64K memory address space, so again 0xd0000 and 0xe0000 are good. -Older Stallion boards are a much bigger problem. They need 128K of address -space and must be on a 128K boundary. If you don't have a VGA card then -0xc0000 might be usable - there is really no other place you can put them -below 1Mb. - -Both the ONboard and old Stallion boards can use higher memory addresses as -well, but you must have less than 16Mb of RAM to be able to use them. Usual -high memory addresses used include 0xec0000 and 0xf00000. - -The Brumby boards only require 16Kb of address space, so you can usually -squeeze them in somewhere. Common addresses are 0xc8000, 0xcc000, or in -the 0xd0000 range. EasyConnection 8/64 boards are even better, they only -require 4Kb of address space, again usually 0xc8000, 0xcc000 or 0xd0000 -are good. - -If you are using an EasyConnection 8/64-EI or ONboard/E then usually the -0xd0000 or 0xe0000 ranges are the best options below 1Mb. If neither of -them can be used then the high memory support to use the really high address -ranges is the best option. Typically the 2Gb range is convenient for them, -and gets them well out of the way. - -The ports of the EasyIO-8M board do not have DCD or DTR signals. So these -ports cannot be used as real modem devices. Generally, when using these -ports you should only use the cueX devices. - -The driver utility package contains a couple of very useful programs. One -is a serial port statistics collection and display program - very handy -for solving serial port problems. The other is an extended option setting -program that works with the intelligent boards. - - - -5. DISCLAIMER - -The information contained in this document is believed to be accurate and -reliable. However, no responsibility is assumed by Stallion Technologies -Pty. Ltd. for its use, nor any infringements of patents or other rights -of third parties resulting from its use. Stallion Technologies reserves -the right to modify the design of its products and will endeavour to change -the information in manuals and accompanying documentation accordingly. - diff --git a/Documentation/sx.txt b/Documentation/sx.txt deleted file mode 100644 index cb4efa0fb5cc..000000000000 --- a/Documentation/sx.txt +++ /dev/null @@ -1,294 +0,0 @@ - - sx.txt -- specialix SX/SI multiport serial driver readme. - - - - Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl) - - Specialix pays for the development and support of this driver. - Please DO contact support@specialix.co.uk if you require - support. - - This driver was developed in the BitWizard linux device - driver service. If you require a linux device driver for your - product, please contact devices@BitWizard.nl for a quote. - - (History) - There used to be an SI driver by Simon Allan. This is a complete - rewrite from scratch. Just a few lines-of-code have been snatched. - - (Sources) - Specialix document number 6210028: SX Host Card and Download Code - Software Functional Specification. - - (Copying) - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of - the License, or (at your option) any later version. - - This program is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU General Public License for more details. - - You should have received a copy of the GNU General Public - License along with this program; if not, write to the Free - Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, - USA. - - (Addendum) - I'd appreciate it that if you have fixes, that you send them - to me first. - - -Introduction -============ - -This file contains some random information, that I like to have online -instead of in a manual that can get lost. Ever misplace your Linux -kernel sources? And the manual of one of the boards in your computer? - - -Theory of operation -=================== - -An important thing to know is that the driver itself doesn't have the -firmware for the card. This means that you need the separate package -"sx_firmware". For now you can get the source at - - ftp://ftp.bitwizard.nl/specialix/sx_firmware_.tgz - -The firmware load needs a "misc" device, so you'll need to enable the -"Support for user misc device modules" in your kernel configuration. -The misc device needs to be called "/dev/specialix_sxctl". It needs -misc major 10, and minor number 167 (assigned by HPA). The section -on creating device files below also creates this device. - -After loading the sx.o module into your kernel, the driver will report -the number of cards detected, but because it doesn't have any -firmware, it will not be able to determine the number of ports. Only -when you then run "sx_firmware" will the firmware be downloaded and -the rest of the driver initialized. At that time the sx_firmware -program will report the number of ports installed. - -In contrast with many other multi port serial cards, some of the data -structures are only allocated when the card knows the number of ports -that are connected. This means we won't waste memory for 120 port -descriptor structures when you only have 8 ports. If you experience -problems due to this, please report them: I haven't seen any. - - -Interrupts -========== - -A multi port serial card, would generate a horrendous amount of -interrupts if it would interrupt the CPU for every received -character. Even more than 10 years ago, the trick not to use -interrupts but to poll the serial cards was invented. - -The SX card allow us to do this two ways. First the card limits its -own interrupt rate to a rate that won't overwhelm the CPU. Secondly, -we could forget about the cards interrupt completely and use the -internal timer for this purpose. - -Polling the card can take up to a few percent of your CPU. Using the -interrupts would be better if you have most of the ports idle. Using -timer-based polling is better if your card almost always has work to -do. You save the separate interrupt in that case. - -In any case, it doesn't really matter all that much. - -The most common problem with interrupts is that for ISA cards in a PCI -system the BIOS has to be told to configure that interrupt as "legacy -ISA". Otherwise the card can pull on the interrupt line all it wants -but the CPU won't see this. - -If you can't get the interrupt to work, remember that polling mode is -more efficient (provided you actually use the card intensively). - - -Allowed Configurations -====================== - -Some configurations are disallowed. Even though at a glance they might -seem to work, they are known to lockup the bus between the host card -and the device concentrators. You should respect the drivers decision -not to support certain configurations. It's there for a reason. - -Warning: Seriously technical stuff ahead. Executive summary: Don't use -SX cards except configured at a 64k boundary. Skip the next paragraph. - -The SX cards can theoretically be placed at a 32k boundary. So for -instance you can put an SX card at 0xc8000-0xd7fff. This is not a -"recommended configuration". ISA cards have to tell the bus controller -how they like their timing. Due to timing issues they have to do this -based on which 64k window the address falls into. This means that the -32k window below and above the SX card have to use exactly the same -timing as the SX card. That reportedly works for other SX cards. But -you're still left with two useless 32k windows that should not be used -by anybody else. - - -Configuring the driver -====================== - -PCI cards are always detected. The driver auto-probes for ISA cards at -some sensible addresses. Please report if the auto-probe causes trouble -in your system, or when a card isn't detected. - -I'm afraid I haven't implemented "kernel command line parameters" yet. -This means that if the default doesn't work for you, you shouldn't use -the compiled-into-the-kernel version of the driver. Use a module -instead. If you convince me that you need this, I'll make it for -you. Deal? - -I'm afraid that the module parameters are a bit clumsy. If you have a -better idea, please tell me. - -You can specify several parameters: - - sx_poll: number of jiffies between timer-based polls. - - Set this to "0" to disable timer based polls. - Initialization of cards without a working interrupt - will fail. - - Set this to "1" if you want a polling driver. - (on Intel: 100 polls per second). If you don't use - fast baud rates, you might consider a value like "5". - (If you don't know how to do the math, use 1). - - sx_slowpoll: Number of jiffies between timer-based polls. - Set this to "100" to poll once a second. - This should get the card out of a stall if the driver - ever misses an interrupt. I've never seen this happen, - and if it does, that's a bug. Tell me. - - sx_maxints: Number of interrupts to request from the card. - The card normally limits interrupts to about 100 per - second to offload the host CPU. You can increase this - number to reduce latency on the card a little. - Note that if you give a very high number you can overload - your CPU as well as the CPU on the host card. This setting - is inaccurate and not recommended for SI cards (But it - works). - - sx_irqmask: The mask of allowable IRQs to use. I suggest you set - this to 0 (disable IRQs all together) and use polling if - the assignment of IRQs becomes problematic. This is defined - as the sum of (1 << irq) 's that you want to allow. So - sx_irqmask of 8 (1 << 3) specifies that only irq 3 may - be used by the SX driver. If you want to specify to the - driver: "Either irq 11 or 12 is ok for you to use", then - specify (1 << 11) | (1 << 12) = 0x1800 . - - sx_debug: You can enable different sorts of debug traces with this. - At "-1" all debugging traces are active. You'll get several - times more debugging output than you'll get characters - transmitted. - - -Baud rates -========== - -Theoretically new SXDCs should be capable of more than 460k -baud. However the line drivers usually give up before that. Also the -CPU on the card may not be able to handle 8 channels going at full -blast at that speed. Moreover, the buffers are not large enough to -allow operation with 100 interrupts per second. You'll have to realize -that the card has a 256 byte buffer, so you'll have to increase the -number of interrupts per second if you have more than 256*100 bytes -per second to transmit. If you do any performance testing in this -area, I'd be glad to hear from you... - -(Psst Linux users..... I think the Linux driver is more efficient than -the driver for other OSes. If you can and want to benchmark them -against each other, be my guest, and report your findings...... :-) - - -Ports and devices -================= - -Port 0 is the top connector on the module closest to the host -card. Oh, the ports on the SXDCs and TAs are labelled from 1 to 8 -instead of from 0 to 7, as they are numbered by linux. I'm stubborn in -this: I know for sure that I wouldn't be able to calculate which port -is which anymore if I would change that.... - - -Devices: - -You should make the device files as follows: - -#!/bin/sh -# (I recommend that you cut-and-paste this into a file and run that) -cd /dev -t=0 -mknod specialix_sxctl c 10 167 -while [ $t -lt 64 ] - do - echo -n "$t " - mknod ttyX$t c 32 $t - mknod cux$t c 33 $t - t=`expr $t + 1` -done -echo "" -rm /etc/psdevtab -ps > /dev/null - - -This creates 64 devices. If you have more, increase the constant on -the line with "while". The devices start at 0, as is customary on -Linux. Specialix seems to like starting the numbering at 1. - -If your system doesn't come with these devices pre-installed, bug your -linux-vendor about this. They should have these devices -"pre-installed" before the new millennium. The "ps" stuff at the end -is to "tell" ps that the new devices exist. - -Officially the maximum number of cards per computer is 4. This driver -however supports as many cards in one machine as you want. You'll run -out of interrupts after a few, but you can switch to polled operation -then. At about 256 ports (More than 8 cards), we run out of minor -device numbers. Sorry. I suggest you buy a second computer.... (Or -switch to RIO). - ------------------------------------------------------------------------- - - - Fixed bugs and restrictions: - - Hangup processing. - -- Done. - - - the write path in generic_serial (lockup / oops). - -- Done (Ugly: not the way I want it. Copied from serial.c). - - - write buffer isn't flushed at close. - -- Done. I still seem to lose a few chars at close. - Sorry. I think that this is a firmware issue. (-> Specialix) - - - drain hardware before changing termios - - Change debug on the fly. - - ISA free irq -1. (no firmware loaded). - - adding c8000 as a probe address. Added warning. - - Add a RAMtest for the RAM on the card.c - - Crash when opening a port "way" of the number of allowed ports. - (for example opening port 60 when there are only 24 ports attached) - - Sometimes the use-count strays a bit. After a few hours of - testing the use count is sometimes "3". If you are not like - me and can remember what you did to get it that way, I'd - appreciate an Email. Possibly fixed. Tell me if anyone still - sees this. - - TAs don't work right if you don't connect all the modem control - signals. SXDCs do. T225 firmware problem -> Specialix. - (Mostly fixed now, I think. Tell me if you encounter this!) - - Bugs & restrictions: - - - Arbitrary baud rates. Requires firmware update. (-> Specialix) - - - Low latency (mostly firmware, -> Specialix) - - - diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt index bde799e06598..a4ccdd1981cf 100644 --- a/Documentation/sysctl/kernel.txt +++ b/Documentation/sysctl/kernel.txt @@ -363,11 +363,21 @@ tainted: Non-zero if the kernel has been tainted. Numeric values, which can be ORed together: - 1 - A module with a non-GPL license has been loaded, this - includes modules with no license. - Set by modutils >= 2.4.9 and module-init-tools. - 2 - A module was force loaded by insmod -f. - Set by modutils >= 2.4.9 and module-init-tools. - 4 - Unsafe SMP processors: SMP with CPUs not designed for SMP. - 64 - A module from drivers/staging was loaded. + 1 - A module with a non-GPL license has been loaded, this + includes modules with no license. + Set by modutils >= 2.4.9 and module-init-tools. + 2 - A module was force loaded by insmod -f. + Set by modutils >= 2.4.9 and module-init-tools. + 4 - Unsafe SMP processors: SMP with CPUs not designed for SMP. + 8 - A module was forcibly unloaded from the system by rmmod -f. + 16 - A hardware machine check error occurred on the system. + 32 - A bad page was discovered on the system. + 64 - The user has asked that the system be marked "tainted". This + could be because they are running software that directly modifies + the hardware, or for other reasons. + 128 - The system has died. + 256 - The ACPI DSDT has been overridden with one supplied by the user + instead of using the one provided by the hardware. + 512 - A kernel warning has occurred. +1024 - A module from drivers/staging was loaded. diff --git a/Documentation/tracers/mmiotrace.txt b/Documentation/tracers/mmiotrace.txt index 5bbbe2096223..cde23b4a12a1 100644 --- a/Documentation/tracers/mmiotrace.txt +++ b/Documentation/tracers/mmiotrace.txt @@ -37,7 +37,7 @@ $ echo mmiotrace > /debug/tracing/current_tracer $ cat /debug/tracing/trace_pipe > mydump.txt & Start X or whatever. $ echo "X is up" > /debug/tracing/trace_marker -$ echo none > /debug/tracing/current_tracer +$ echo nop > /debug/tracing/current_tracer Check for lost events. @@ -66,7 +66,7 @@ which action. It is recommended to place descriptive markers about what you do. Shut down mmiotrace (requires root privileges): -$ echo none > /debug/tracing/current_tracer +$ echo nop > /debug/tracing/current_tracer The 'cat' process exits. If it does not, kill it by issuing 'fg' command and pressing ctrl+c. @@ -81,7 +81,9 @@ are: $ cat /debug/tracing/trace_entries gives you a number. Approximately double this number and write it back, for instance: +$ echo 0 > /debug/tracing/tracing_enabled $ echo 128000 > /debug/tracing/trace_entries +$ echo 1 > /debug/tracing/tracing_enabled Then start again from the top. If you are doing a trace for a driver project, e.g. Nouveau, you should also diff --git a/Documentation/tty.txt b/Documentation/tty.txt deleted file mode 100644 index 8e65c4498c52..000000000000 --- a/Documentation/tty.txt +++ /dev/null @@ -1,292 +0,0 @@ - - The Lockronomicon - -Your guide to the ancient and twisted locking policies of the tty layer and -the warped logic behind them. Beware all ye who read on. - -FIXME: still need to work out the full set of BKL assumptions and document -them so they can eventually be killed off. - - -Line Discipline ---------------- - -Line disciplines are registered with tty_register_ldisc() passing the -discipline number and the ldisc structure. At the point of registration the -discipline must be ready to use and it is possible it will get used before -the call returns success. If the call returns an error then it won't get -called. Do not re-use ldisc numbers as they are part of the userspace ABI -and writing over an existing ldisc will cause demons to eat your computer. -After the return the ldisc data has been copied so you may free your own -copy of the structure. You must not re-register over the top of the line -discipline even with the same data or your computer again will be eaten by -demons. - -In order to remove a line discipline call tty_unregister_ldisc(). -In ancient times this always worked. In modern times the function will -return -EBUSY if the ldisc is currently in use. Since the ldisc referencing -code manages the module counts this should not usually be a concern. - -Heed this warning: the reference count field of the registered copies of the -tty_ldisc structure in the ldisc table counts the number of lines using this -discipline. The reference count of the tty_ldisc structure within a tty -counts the number of active users of the ldisc at this instant. In effect it -counts the number of threads of execution within an ldisc method (plus those -about to enter and exit although this detail matters not). - -Line Discipline Methods ------------------------ - -TTY side interfaces: - -open() - Called when the line discipline is attached to - the terminal. No other call into the line - discipline for this tty will occur until it - completes successfully. Can sleep. - -close() - This is called on a terminal when the line - discipline is being unplugged. At the point of - execution no further users will enter the - ldisc code for this tty. Can sleep. - -hangup() - Called when the tty line is hung up. - The line discipline should cease I/O to the tty. - No further calls into the ldisc code will occur. - Can sleep. - -write() - A process is writing data through the line - discipline. Multiple write calls are serialized - by the tty layer for the ldisc. May sleep. - -flush_buffer() - (optional) May be called at any point between - open and close, and instructs the line discipline - to empty its input buffer. - -chars_in_buffer() - (optional) Report the number of bytes in the input - buffer. - -set_termios() - (optional) Called on termios structure changes. - The caller passes the old termios data and the - current data is in the tty. Called under the - termios semaphore so allowed to sleep. Serialized - against itself only. - -read() - Move data from the line discipline to the user. - Multiple read calls may occur in parallel and the - ldisc must deal with serialization issues. May - sleep. - -poll() - Check the status for the poll/select calls. Multiple - poll calls may occur in parallel. May sleep. - -ioctl() - Called when an ioctl is handed to the tty layer - that might be for the ldisc. Multiple ioctl calls - may occur in parallel. May sleep. - -Driver Side Interfaces: - -receive_buf() - Hand buffers of bytes from the driver to the ldisc - for processing. Semantics currently rather - mysterious 8( - -write_wakeup() - May be called at any point between open and close. - The TTY_DO_WRITE_WAKEUP flag indicates if a call - is needed but always races versus calls. Thus the - ldisc must be careful about setting order and to - handle unexpected calls. Must not sleep. - - The driver is forbidden from calling this directly - from the ->write call from the ldisc as the ldisc - is permitted to call the driver write method from - this function. In such a situation defer it. - - -Driver Access - -Line discipline methods can call the following methods of the underlying -hardware driver through the function pointers within the tty->driver -structure: - -write() Write a block of characters to the tty device. - Returns the number of characters accepted. The - character buffer passed to this method is already - in kernel space. - -put_char() Queues a character for writing to the tty device. - If there is no room in the queue, the character is - ignored. - -flush_chars() (Optional) If defined, must be called after - queueing characters with put_char() in order to - start transmission. - -write_room() Returns the numbers of characters the tty driver - will accept for queueing to be written. - -ioctl() Invoke device specific ioctl. - Expects data pointers to refer to userspace. - Returns ENOIOCTLCMD for unrecognized ioctl numbers. - -set_termios() Notify the tty driver that the device's termios - settings have changed. New settings are in - tty->termios. Previous settings should be passed in - the "old" argument. - - The API is defined such that the driver should return - the actual modes selected. This means that the - driver function is responsible for modifying any - bits in the request it cannot fulfill to indicate - the actual modes being used. A device with no - hardware capability for change (eg a USB dongle or - virtual port) can provide NULL for this method. - -throttle() Notify the tty driver that input buffers for the - line discipline are close to full, and it should - somehow signal that no more characters should be - sent to the tty. - -unthrottle() Notify the tty driver that characters can now be - sent to the tty without fear of overrunning the - input buffers of the line disciplines. - -stop() Ask the tty driver to stop outputting characters - to the tty device. - -start() Ask the tty driver to resume sending characters - to the tty device. - -hangup() Ask the tty driver to hang up the tty device. - -break_ctl() (Optional) Ask the tty driver to turn on or off - BREAK status on the RS-232 port. If state is -1, - then the BREAK status should be turned on; if - state is 0, then BREAK should be turned off. - If this routine is not implemented, use ioctls - TIOCSBRK / TIOCCBRK instead. - -wait_until_sent() Waits until the device has written out all of the - characters in its transmitter FIFO. - -send_xchar() Send a high-priority XON/XOFF character to the device. - - -Flags - -Line discipline methods have access to tty->flags field containing the -following interesting flags: - -TTY_THROTTLED Driver input is throttled. The ldisc should call - tty->driver->unthrottle() in order to resume - reception when it is ready to process more data. - -TTY_DO_WRITE_WAKEUP If set, causes the driver to call the ldisc's - write_wakeup() method in order to resume - transmission when it can accept more data - to transmit. - -TTY_IO_ERROR If set, causes all subsequent userspace read/write - calls on the tty to fail, returning -EIO. - -TTY_OTHER_CLOSED Device is a pty and the other side has closed. - -TTY_NO_WRITE_SPLIT Prevent driver from splitting up writes into - smaller chunks. - - -Locking - -Callers to the line discipline functions from the tty layer are required to -take line discipline locks. The same is true of calls from the driver side -but not yet enforced. - -Three calls are now provided - - ldisc = tty_ldisc_ref(tty); - -takes a handle to the line discipline in the tty and returns it. If no ldisc -is currently attached or the ldisc is being closed and re-opened at this -point then NULL is returned. While this handle is held the ldisc will not -change or go away. - - tty_ldisc_deref(ldisc) - -Returns the ldisc reference and allows the ldisc to be closed. Returning the -reference takes away your right to call the ldisc functions until you take -a new reference. - - ldisc = tty_ldisc_ref_wait(tty); - -Performs the same function as tty_ldisc_ref except that it will wait for an -ldisc change to complete and then return a reference to the new ldisc. - -While these functions are slightly slower than the old code they should have -minimal impact as most receive logic uses the flip buffers and they only -need to take a reference when they push bits up through the driver. - -A caution: The ldisc->open(), ldisc->close() and driver->set_ldisc -functions are called with the ldisc unavailable. Thus tty_ldisc_ref will -fail in this situation if used within these functions. Ldisc and driver -code calling its own functions must be careful in this case. - - -Driver Interface ----------------- - -open() - Called when a device is opened. May sleep - -close() - Called when a device is closed. At the point of - return from this call the driver must make no - further ldisc calls of any kind. May sleep - -write() - Called to write bytes to the device. May not - sleep. May occur in parallel in special cases. - Because this includes panic paths drivers generally - shouldn't try and do clever locking here. - -put_char() - Stuff a single character onto the queue. The - driver is guaranteed following up calls to - flush_chars. - -flush_chars() - Ask the kernel to write put_char queue - -write_room() - Return the number of characters tht can be stuffed - into the port buffers without overflow (or less). - The ldisc is responsible for being intelligent - about multi-threading of write_room/write calls - -ioctl() - Called when an ioctl may be for the driver - -set_termios() - Called on termios change, serialized against - itself by a semaphore. May sleep. - -set_ldisc() - Notifier for discipline change. At the point this - is done the discipline is not yet usable. Can now - sleep (I think) - -throttle() - Called by the ldisc to ask the driver to do flow - control. Serialization including with unthrottle - is the job of the ldisc layer. - -unthrottle() - Called by the ldisc to ask the driver to stop flow - control. - -stop() - Ldisc notifier to the driver to stop output. As with - throttle the serializations with start() are down - to the ldisc layer. - -start() - Ldisc notifier to the driver to start output. - -hangup() - Ask the tty driver to cause a hangup initiated - from the host side. [Can sleep ??] - -break_ctl() - Send RS232 break. Can sleep. Can get called in - parallel, driver must serialize (for now), and - with write calls. - -wait_until_sent() - Wait for characters to exit the hardware queue - of the driver. Can sleep - -send_xchar() - Send XON/XOFF and if possible jump the queue with - it in order to get fast flow control responses. - Cannot sleep ?? - diff --git a/Documentation/usb/gadget_serial.txt b/Documentation/usb/gadget_serial.txt index 9b22bd14c348..eac7df94d8e3 100644 --- a/Documentation/usb/gadget_serial.txt +++ b/Documentation/usb/gadget_serial.txt @@ -114,11 +114,11 @@ modules. Then you must load the gadget serial driver. To load it as an ACM device (recommended for interoperability), do this: - modprobe g_serial use_acm=1 + modprobe g_serial To load it as a vendor specific bulk in/out device, do this: - modprobe g_serial + modprobe g_serial use_acm=0 This will also automatically load the underlying gadget peripheral controller driver. This must be done each time you reboot the gadget diff --git a/Documentation/usb/proc_usb_info.txt b/Documentation/usb/proc_usb_info.txt index 077e9032d0cd..fafcd4723260 100644 --- a/Documentation/usb/proc_usb_info.txt +++ b/Documentation/usb/proc_usb_info.txt @@ -49,8 +49,10 @@ it and 002/048 sometime later. These files can be read as binary data. The binary data consists of first the device descriptor, then the descriptors for each -configuration of the device. That information is also shown in -text form by the /proc/bus/usb/devices file, described later. +configuration of the device. Multi-byte fields in the device and +configuration descriptors, but not other descriptors, are converted +to host endianness by the kernel. This information is also shown +in text form by the /proc/bus/usb/devices file, described later. These files may also be used to write user-level drivers for the USB devices. You would open the /proc/bus/usb/BBB/DDD file read/write, diff --git a/Documentation/usb/usbmon.txt b/Documentation/usb/usbmon.txt index 2917ce4ffdc4..270481906dc8 100644 --- a/Documentation/usb/usbmon.txt +++ b/Documentation/usb/usbmon.txt @@ -34,11 +34,12 @@ if usbmon is built into the kernel. Verify that bus sockets are present. # ls /sys/kernel/debug/usbmon -0s 0t 0u 1s 1t 1u 2s 2t 2u 3s 3t 3u 4s 4t 4u +0s 0u 1s 1t 1u 2s 2t 2u 3s 3t 3u 4s 4t 4u # -Now you can choose to either use the sockets numbered '0' (to capture packets on -all buses), and skip to step #3, or find the bus used by your device with step #2. +Now you can choose to either use the socket '0u' (to capture packets on all +buses), and skip to step #3, or find the bus used by your device with step #2. +This allows to filter away annoying devices that talk continuously. 2. Find which bus connects to the desired device @@ -99,8 +100,9 @@ on the event type, but there is a set of words, common for all types. Here is the list of words, from left to right: -- URB Tag. This is used to identify URBs is normally a kernel mode address - of the URB structure in hexadecimal. +- URB Tag. This is used to identify URBs, and is normally an in-kernel address + of the URB structure in hexadecimal, but can be a sequence number or any + other unique string, within reason. - Timestamp in microseconds, a decimal number. The timestamp's resolution depends on available clock, and so it can be much worse than a microsecond diff --git a/Documentation/video4linux/.gitignore b/Documentation/video4linux/.gitignore new file mode 100644 index 000000000000..952703943e8e --- /dev/null +++ b/Documentation/video4linux/.gitignore @@ -0,0 +1 @@ +v4lgrab diff --git a/Documentation/video4linux/README.cx88 b/Documentation/video4linux/README.cx88 index 06a33a4f52fd..166d5960b1a9 100644 --- a/Documentation/video4linux/README.cx88 +++ b/Documentation/video4linux/README.cx88 @@ -27,8 +27,8 @@ audio sound card) should be possible, but there is no code yet ... vbi - - some code present. Doesn't crash any more, but also doesn't - work yet ... + - Code present. Works for NTSC closed caption. PAL and other + TV norms may or may not work. how to add support for new cards diff --git a/Documentation/video4linux/bttv/CONTRIBUTORS b/Documentation/video4linux/bttv/CONTRIBUTORS index 8aad6dd93d6b..eb41b2650860 100644 --- a/Documentation/video4linux/bttv/CONTRIBUTORS +++ b/Documentation/video4linux/bttv/CONTRIBUTORS @@ -3,7 +3,7 @@ Contributors to bttv: Michael Chu AverMedia fix and more flexible card recognition -Alan Cox +Alan Cox Video4Linux interface and 2.1.x kernel adaptation Chris Kleitsch diff --git a/Documentation/video4linux/si470x.txt b/Documentation/video4linux/si470x.txt new file mode 100644 index 000000000000..11c5fd22a332 --- /dev/null +++ b/Documentation/video4linux/si470x.txt @@ -0,0 +1,118 @@ +Driver for USB radios for the Silicon Labs Si470x FM Radio Receivers + +Copyright (c) 2008 Tobias Lorenz + + +Information from Silicon Labs +============================= +Silicon Laboratories is the manufacturer of the radio ICs, that nowadays are the +most often used radio receivers in cell phones. Usually they are connected with +I2C. But SiLabs also provides a reference design, which integrates this IC, +together with a small microcontroller C8051F321, to form a USB radio. +Part of this reference design is also a radio application in binary and source +code. The software also contains an automatic firmware upgrade to the most +current version. Information on these can be downloaded here: +http://www.silabs.com/usbradio + + +Supported ICs +============= +The following ICs have a very similar register set, so that they are or will be +supported somewhen by the driver: +- Si4700: FM radio receiver +- Si4701: FM radio receiver, RDS Support +- Si4702: FM radio receiver +- Si4703: FM radio receiver, RDS Support +- Si4704: FM radio receiver, no external antenna required +- Si4705: FM radio receiver, no external antenna required, RDS support, Dig I/O +- Si4706: Enhanced FM RDS/TMC radio receiver, no external antenna required, RDS + Support +- Si4707: Dedicated weather band radio receiver with SAME decoder, RDS Support +- Si4708: Smallest FM receivers +- Si4709: Smallest FM receivers, RDS Support +More information on these can be downloaded here: +http://www.silabs.com/products/mcu/Pages/USBFMRadioRD.aspx + + +Supported USB devices +===================== +Currently the following USB radios (vendor:product) with the Silicon Labs si470x +chips are known to work: +- 10c4:818a: Silicon Labs USB FM Radio Reference Design +- 06e1:a155: ADS/Tech FM Radio Receiver (formerly Instant FM Music) (RDX-155-EF) +- 1b80:d700: KWorld USB FM Radio SnapMusic Mobile 700 (FM700) + + +Software +======== +Testing is usually done with most application under Debian/testing: +- fmtools - Utility for managing FM tuner cards +- gnomeradio - FM-radio tuner for the GNOME desktop +- gradio - GTK FM radio tuner +- kradio - Comfortable Radio Application for KDE +- radio - ncurses-based radio application + +There is also a library libv4l, which can be used. It's going to have a function +for frequency seeking, either by using hardware functionality as in radio-si470x +or by implementing a function as we currently have in every of the mentioned +programs. Somewhen the radio programs should make use of libv4l. + +For processing RDS information, there is a project ongoing at: +http://rdsd.berlios.de/ + +There is currently no project for making TMC sentences human readable. + + +Audio Listing +============= +USB Audio is provided by the ALSA snd_usb_audio module. It is recommended to +also select SND_USB_AUDIO, as this is required to get sound from the radio. For +listing you have to redirect the sound, for example using one of the following +commands. + +If you just want to test audio (very poor quality): +cat /dev/dsp1 > /dev/dsp + +If you use OSS try: +sox -2 --endian little -r 96000 -t oss /dev/dsp1 -t oss /dev/dsp + +If you use arts try: +arecord -D hw:1,0 -r96000 -c2 -f S16_LE | artsdsp aplay -B - + + +Module Parameters +================= +After loading the module, you still have access to some of them in the sysfs +mount under /sys/module/radio_si470x/parameters. The contents of read-only files +(0444) are not updated, even if space, band and de are changed using private +video controls. The others are runtime changeable. + + +Errors +====== +Increase tune_timeout, if you often get -EIO errors. + +When timed out or band limit is reached, hw_freq_seek returns -EAGAIN. + +If you get any errors from snd_usb_audio, please report them to the ALSA people. + + +Open Issues +=========== +V4L minor device allocation and parameter setting is not perfect. A solution is +currently under discussion. + +There is an USB interface for downloading/uploading new firmware images. Support +for it can be implemented using the request_firmware interface. + +There is a RDS interrupt mode. The driver is already using the same interface +for polling RDS information, but is currently not using the interrupt mode. + +There is a LED interface, which can be used to override the LED control +programmed in the firmware. This can be made available using the LED support +functions in the kernel. + + +Other useful information and links +================================== +http://www.silabs.com/usbradio diff --git a/Documentation/vm/.gitignore b/Documentation/vm/.gitignore new file mode 100644 index 000000000000..33e8a023df02 --- /dev/null +++ b/Documentation/vm/.gitignore @@ -0,0 +1 @@ +slabinfo diff --git a/Documentation/w1/masters/omap-hdq b/Documentation/w1/masters/omap-hdq new file mode 100644 index 000000000000..ca722e09b6a1 --- /dev/null +++ b/Documentation/w1/masters/omap-hdq @@ -0,0 +1,46 @@ +Kernel driver for omap HDQ/1-wire module. +======================================== + +Supported chips: +================ + HDQ/1-wire controller on the TI OMAP 2430/3430 platforms. + +A useful link about HDQ basics: +=============================== +http://focus.ti.com/lit/an/slua408/slua408.pdf + +Description: +============ +The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware +protocol of the master functions of the Benchmark HDQ and the Dallas +Semiconductor 1-Wire protocols. These protocols use a single wire for +communication between the master (HDQ/1-Wire controller) and the slave +(HDQ/1-Wire external compliant device). + +A typical application of the HDQ/1-Wire module is the communication with battery +monitor (gas gauge) integrated circuits. + +The controller supports operation in both HDQ and 1-wire mode. The essential +difference between the HDQ and 1-wire mode is how the slave device responds to +initialization pulse.In HDQ mode, the firmware does not require the host to +create an initialization pulse to the slave.However, the slave can be reset by +using an initialization pulse (also referred to as a break pulse).The slave +does not respond with a presence pulse as it does in the 1-Wire protocol. + +Remarks: +======== +The driver (drivers/w1/masters/omap_hdq.c) supports the HDQ mode of the +controller. In this mode, as we can not read the ID which obeys the W1 +spec(family:id:crc), a module parameter can be passed to the driver which will +be used to calculate the CRC and pass back an appropriate slave ID to the W1 +core. + +By default the master driver and the BQ slave i/f +driver(drivers/w1/slaves/w1_bq27000.c) sets the ID to 1. +Please note to load both the modules with a different ID if required, but note +that the ID used should be same for both master and slave driver loading. + +e.g: +insmod omap_hdq.ko W1_ID=2 +inamod w1_bq27000.ko F_ID=2 + diff --git a/Documentation/watchdog/src/.gitignore b/Documentation/watchdog/src/.gitignore new file mode 100644 index 000000000000..ac90997dba93 --- /dev/null +++ b/Documentation/watchdog/src/.gitignore @@ -0,0 +1,2 @@ +watchdog-simple +watchdog-test diff --git a/Documentation/x86/boot.txt b/Documentation/x86/boot.txt index 83c0033ee9e0..fcdc62b3c3d8 100644 --- a/Documentation/x86/boot.txt +++ b/Documentation/x86/boot.txt @@ -349,7 +349,7 @@ Protocol: 2.00+ 3 SYSLINUX 4 EtherBoot 5 ELILO - 7 GRuB + 7 GRUB 8 U-BOOT 9 Xen A Gujin @@ -537,8 +537,8 @@ Type: read Offset/size: 0x248/4 Protocol: 2.08+ - If non-zero then this field contains the offset from the end of the - real-mode code to the payload. + If non-zero then this field contains the offset from the beginning + of the protected-mode code to the payload. The payload may be compressed. The format of both the compressed and uncompressed data should be determined using the standard magic diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt index c93ff5f4c0dd..cf08c9fff3cd 100644 --- a/Documentation/x86/pat.txt +++ b/Documentation/x86/pat.txt @@ -80,6 +80,30 @@ pci proc | -- | -- | WC | | | | | ------------------------------------------------------------------- +Advanced APIs for drivers +------------------------- +A. Exporting pages to users with remap_pfn_range, io_remap_pfn_range, +vm_insert_pfn + +Drivers wanting to export some pages to userspace do it by using mmap +interface and a combination of +1) pgprot_noncached() +2) io_remap_pfn_range() or remap_pfn_range() or vm_insert_pfn() + +With PAT support, a new API pgprot_writecombine is being added. So, drivers can +continue to use the above sequence, with either pgprot_noncached() or +pgprot_writecombine() in step 1, followed by step 2. + +In addition, step 2 internally tracks the region as UC or WC in memtype +list in order to ensure no conflicting mapping. + +Note that this set of APIs only works with IO (non RAM) regions. If driver +wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc() +as step 0 above and also track the usage of those pages and use set_memory_wb() +before the page is freed to free pool. + + + Notes: -- in the above table mean "Not suggested usage for the API". Some of the --'s diff --git a/Documentation/x86/x86_64/boot-options.txt b/Documentation/x86/x86_64/boot-options.txt index 72ffb5373ec7..34c13040a718 100644 --- a/Documentation/x86/x86_64/boot-options.txt +++ b/Documentation/x86/x86_64/boot-options.txt @@ -35,7 +35,7 @@ APICs nolapic Don't use the local APIC (alias for i386 compatibility) - pirq=... See Documentation/i386/IO-APIC.txt + pirq=... See Documentation/x86/i386/IO-APIC.txt noapictimer Don't set up the APIC timer @@ -79,17 +79,6 @@ Timing Report when timer interrupts are lost because some code turned off interrupts for too long. - nmi_watchdog=NUMBER[,panic] - NUMBER can be: - 0 don't use an NMI watchdog - 1 use the IO-APIC timer for the NMI watchdog - 2 use the local APIC for the NMI watchdog using a performance counter. Note - This will use one performance counter and the local APIC's performance - vector. - When panic is specified panic when an NMI watchdog timeout occurs. - This is useful when you use a panic=... timeout and need the box - quickly up again. - nohpet Don't use the HPET timer. @@ -139,7 +128,7 @@ Non Executable Mappings SMP additional_cpus=NUM Allow NUM more CPUs for hotplug - (defaults are specified by the BIOS, see Documentation/x86_64/cpu-hotplug-spec) + (defaults are specified by the BIOS, see Documentation/x86/x86_64/cpu-hotplug-spec) NUMA diff --git a/Documentation/x86/x86_64/fake-numa-for-cpusets b/Documentation/x86/x86_64/fake-numa-for-cpusets index d1a985c5b00a..33bb56655991 100644 --- a/Documentation/x86/x86_64/fake-numa-for-cpusets +++ b/Documentation/x86/x86_64/fake-numa-for-cpusets @@ -10,7 +10,7 @@ amount of system memory that are available to a certain class of tasks. For more information on the features of cpusets, see Documentation/cpusets.txt. There are a number of different configurations you can use for your needs. For more information on the numa=fake command line option and its various ways of -configuring fake nodes, see Documentation/x86_64/boot-options.txt. +configuring fake nodes, see Documentation/x86/x86_64/boot-options.txt. For the purposes of this introduction, we'll assume a very primitive NUMA emulation setup of "numa=fake=4*512,". This will split our system memory into diff --git a/Documentation/x86/x86_64/mm.txt b/Documentation/x86/x86_64/mm.txt index efce75097369..29b52b14d0b4 100644 --- a/Documentation/x86/x86_64/mm.txt +++ b/Documentation/x86/x86_64/mm.txt @@ -6,7 +6,7 @@ Virtual memory map with 4 level page tables: 0000000000000000 - 00007fffffffffff (=47 bits) user space, different per mm hole caused by [48:63] sign extension ffff800000000000 - ffff80ffffffffff (=40 bits) guard hole -ffff810000000000 - ffffc0ffffffffff (=46 bits) direct mapping of all phys. memory +ffff880000000000 - ffffc0ffffffffff (=57 TB) direct mapping of all phys. memory ffffc10000000000 - ffffc1ffffffffff (=40 bits) hole ffffc20000000000 - ffffe1ffffffffff (=45 bits) vmalloc/ioremap space ffffe20000000000 - ffffe2ffffffffff (=40 bits) virtual memory map (1TB) diff --git a/MAINTAINERS b/MAINTAINERS index 16202c8ac68f..c42a567e010c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -347,7 +347,7 @@ S: Maintained ALI1563 I2C DRIVER P: Rudolf Marek M: r.marek@assembler.cz -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained ALPHA PORT @@ -610,6 +610,11 @@ P: Philipp Zabel M: philipp.zabel@gmail.com S: Maintained +ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT +P: Michael Petchkovsky +M: mkpetch@internode.on.net +S: Maintained + ARM/TOSA MACHINE SUPPORT P: Dmitry Baryshkov M: dbaryshkov@gmail.com @@ -716,7 +721,7 @@ W: http://sourceforge.net/projects/acpi4asus W: http://xf.iksaif.net/acpi4asus S: Maintained -ASYNCHRONOUS TRANSFERS/TRANSFORMS API +ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API P: Dan Williams M: dan.j.williams@intel.com P: Maciej Sosnowski @@ -738,6 +743,8 @@ P: Nick Kossifidis M: mickflemm@gmail.com P: Luis R. Rodriguez M: mcgrof@gmail.com +P: Bob Copeland +M: me@bobcopeland.com L: linux-wireless@vger.kernel.org L: ath5k-devel@lists.ath5k.org S: Maintained @@ -772,6 +779,7 @@ ATM P: Chas Williams M: chas@cmf.nrl.navy.mil L: linux-atm-general@lists.sourceforge.net (subscribers-only) +L: netdev@vger.kernel.org W: http://linux-atm.sourceforge.net S: Maintained @@ -1519,10 +1527,10 @@ W: http://ebtables.sourceforge.net/ S: Maintained ECRYPT FILE SYSTEM -P: Mike Halcrow, Phillip Hellewell -M: mhalcrow@us.ibm.com, phillip@hellewell.homeip.net -L: ecryptfs-devel@lists.sourceforge.net -W: http://ecryptfs.sourceforge.net/ +P: Tyler Hicks, Dustin Kirkland +M: tyhicks@linux.vnet.ibm.com, kirkland@canonical.com +L: ecryptfs-devel@lists.launchpad.net +W: https://launchpad.net/ecryptfs S: Supported EDAC-CORE @@ -1749,7 +1757,7 @@ FREESCALE I2C CPM DRIVER P: Jochen Friedrich M: jochen@scram.de L: linuxppc-dev@ozlabs.org -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained FREESCALE SOC FS_ENET DRIVER @@ -1802,7 +1810,7 @@ S: Maintained FTRACE P: Steven Rostedt -M: srostedt@redhat.com +M: rostedt@goodmis.org S: Maintained FUJITSU FR-V (FRV) PORT @@ -1872,6 +1880,37 @@ M: linux-kernel@vger.kernel.org W: http://www.kernel.org/pub/linux/kernel/people/rml/hdaps/ S: Maintained +GSPCA FINEPIX SUBDRIVER +P: Frank Zago +M: frank@zago.net +L: video4linux-list@redhat.com +S: Maintained + +GSPCA M5602 SUBDRIVER +P: Erik Andren +M: erik.andren@gmail.com +L: video4linux-list@redhat.com +S: Maintained + +GSPCA PAC207 SONIXB SUBDRIVER +P: Hans de Goede +M: hdegoede@redhat.com +L: video4linux-list@redhat.com +S: Maintained + +GSPCA T613 SUBDRIVER +P: Leandro Costantino +M: lcostantino@gmail.com +L: video4linux-list@redhat.com +S: Maintained + +GSPCA USB WEBCAM DRIVER +P: Jean-Francois Moine +M: moinejf@free.fr +W: http://moinejf.free.fr +L: video4linux-list@redhat.com +S: Maintained + HARDWARE MONITORING L: lm-sensors@lm-sensors.org W: http://www.lm-sensors.org/ @@ -2022,7 +2061,7 @@ S: Maintained I2C/SMBUS STUB DRIVER P: Mark M. Hoffman M: mhoffman@lightlink.com -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained I2C SUBSYSTEM @@ -2030,14 +2069,14 @@ P: Jean Delvare (PC drivers, core) M: khali@linux-fr.org P: Ben Dooks (embedded platforms) M: ben-linux@fluff.org -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org T: quilt http://khali.linux-fr.org/devel/linux-2.6/jdelvare-i2c/ S: Maintained I2C-TINY-USB DRIVER P: Till Harbaum M: till@harbaum.org -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org T: http://www.harbaum.org/till/i2c_tiny_usb S: Maintained @@ -2152,9 +2191,9 @@ S: Supported INOTIFY P: John McCutchan -M: ttb@tentacle.dhs.org +M: john@johnmccutchan.com P: Robert Love -M: rml@novell.com +M: rlove@rlove.org L: linux-kernel@vger.kernel.org S: Maintained @@ -2178,6 +2217,13 @@ M: adaplas@gmail.com L: linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers) S: Maintained +INTEL MENLOW THERMAL DRIVER +P: Sujith Thomas +M: sujith.thomas@intel.com +L: linux-acpi@vger.kernel.org +W: http://www.lesswatts.org/projects/acpi/ +S: Supported + INTEL IA32 MICROCODE UPDATE SUPPORT P: Tigran Aivazian M: tigran@aivazian.fsnet.co.uk @@ -2658,6 +2704,11 @@ P: Arnaldo Carvalho de Melo M: acme@ghostprotocols.net S: Maintained +LIS3LV02D ACCELEROMETER DRIVER +P: Eric Piel +M: eric.piel@tremplin-utc.net +S: Maintained + LM83 HARDWARE MONITOR DRIVER P: Jean Delvare M: khali@linux-fr.org @@ -2701,6 +2752,16 @@ M: matthew@wil.cx L: linux-scsi@vger.kernel.org S: Maintained +LTP (Linux Test Project) +P: Subrata Modak +M: subrata@linux.vnet.ibm.com +P: Mike Frysinger +M: vapier@gentoo.org +L: ltp-list@lists.sourceforge.net (subscribers-only) +W: http://ltp.sourceforge.net/ +T: git kernel.org/pub/scm/linux/kernel/git/galak/ltp.git +S: Maintained + M32R ARCHITECTURE P: Hirokazu Takata M: takata@linux-m32r.org @@ -3143,7 +3204,7 @@ S: Maintained OPENCORES I2C BUS DRIVER P: Peter Korsgaard M: jacmet@sunsite.dk -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained OPROFILE @@ -3190,7 +3251,7 @@ S: Maintained PA SEMI SMBUS DRIVER P: Olof Johansson M: olof@lixom.net -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained PANASONIC LAPTOP ACPI EXTRAS DRIVER @@ -3329,13 +3390,15 @@ S: Maintained PNP SUPPORT P: Adam Belay -M: ambx1@neo.rr.com +M: abelay@mit.edu +P: Bjorn Helgaas +M: bjorn.helgaas@hp.com S: Maintained PNXxxxx I2C DRIVER P: Vitaly Wool M: vitalywool@gmail.com -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained PPP PROTOCOL DRIVERS AND COMPRESSORS @@ -3696,6 +3759,15 @@ M: drzeus-sdhci@drzeus.cx L: sdhci-devel@list.drzeus.cx S: Maintained +SECURITY SUBSYSTEM +F: security/ +P: James Morris +M: jmorris@namei.org +L: linux-kernel@vger.kernel.org +L: linux-security-module@vger.kernel.org (suggested Cc:) +T: git kernel.org:pub/scm/linux/kernel/git/jmorris/security-testing-2.6.git +S: Supported + SECURITY CONTACT P: Security Officers M: security@kernel.org @@ -3799,7 +3871,7 @@ S: Maintained SIS 96X I2C/SMBUS DRIVER P: Mark M. Hoffman M: mhoffman@lightlink.com -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained SIS FRAMEBUFFER DRIVER @@ -3866,8 +3938,6 @@ M: bootc@bootc.net S: Maintained SOFTWARE RAID (Multiple Disks) SUPPORT -P: Ingo Molnar -M: mingo@redhat.com P: Neil Brown M: neilb@suse.de L: linux-raid@vger.kernel.org @@ -4175,7 +4245,7 @@ M: dedekind@infradead.org P: Adrian Hunter M: ext-adrian.hunter@nokia.com L: linux-mtd@lists.infradead.org -T: git git://git.infradead.org/~dedekind/ubifs-2.6.git +T: git git://git.infradead.org/ubifs-2.6.git W: http://www.linux-mtd.infradead.org/doc/ubifs.html S: Maintained @@ -4229,7 +4299,7 @@ P: Artem Bityutskiy M: dedekind@infradead.org W: http://www.linux-mtd.infradead.org/ L: linux-mtd@lists.infradead.org -T: git git://git.infradead.org/~dedekind/ubi-2.6.git +T: git git://git.infradead.org/ubi-2.6.git S: Maintained USB ACM DRIVER @@ -4546,7 +4616,7 @@ S: Maintained VIAPRO SMBUS DRIVER P: Jean Delvare M: khali@linux-fr.org -L: i2c@lm-sensors.org +L: linux-i2c@vger.kernel.org S: Maintained VIA UNICHROME(PRO)/CHROME9 FRAMEBUFFER DRIVER diff --git a/Makefile b/Makefile index e9c5d47f31cd..4c8d79710b84 100644 --- a/Makefile +++ b/Makefile @@ -1,8 +1,8 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 28 -EXTRAVERSION = -rc2 -NAME = Killer Bat of Doom +EXTRAVERSION = -rc9 +NAME = Erotic Pickled Herring # *DOCUMENTATION* # To see a list of typical targets execute "make help" @@ -536,7 +536,7 @@ KBUILD_CFLAGS += -g KBUILD_AFLAGS += -gdwarf-2 endif -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER KBUILD_CFLAGS += -pg endif @@ -961,6 +961,7 @@ export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH) # The asm symlink changes when $(ARCH) changes. # Detect this and ask user to run make mrproper +# If asm is a stale symlink (point to dir that does not exist) remove it define check-symlink set -e; \ if [ -L include/asm ]; then \ @@ -970,6 +971,10 @@ define check-symlink echo " set ARCH or save .config and run 'make mrproper' to fix it"; \ exit 1; \ fi; \ + test -e $$asmlink || rm include/asm; \ + elif [ -d include/asm ]; then \ + echo "ERROR: $@ is a directory but a symlink was expected";\ + exit 1; \ fi endef @@ -1431,7 +1436,8 @@ ALLSOURCE_ARCHS := $(SRCARCH) define find-sources ( for arch in $(ALLSOURCE_ARCHS) ; do \ find $(__srctree)arch/$${arch} $(RCS_FIND_IGNORE) \ - -name $1 -print; \ + -wholename $(__srctree)arch/$${arch}/include/asm -type d -prune \ + -o -name $1 -print; \ done ; \ find $(__srctree)security/selinux/include $(RCS_FIND_IGNORE) \ -name $1 -print; \ diff --git a/arch/Kconfig b/arch/Kconfig index e6ab550bceb3..471e72dbaf8b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -21,7 +21,7 @@ config OPROFILE_IBS Instruction-Based Sampling (IBS) is a new profiling technique that provides rich, precise program performance information. IBS is introduced by AMD Family10h processors - (AMD Opteron Quad-Core processor “Barcelona”) to overcome + (AMD Opteron Quad-Core processor "Barcelona") to overcome the limitations of conventional performance counter sampling. @@ -79,8 +79,6 @@ config HAVE_KRETPROBES # task_pt_regs() in asm/processor.h or asm/ptrace.h # arch_has_single_step() if there is hardware single-step support # arch_has_block_step() if there is hardware block-step support -# arch_ptrace() and not #define __ARCH_SYS_PTRACE -# compat_arch_ptrace() and #define __ARCH_WANT_COMPAT_SYS_PTRACE # asm/syscall.h supplying asm-generic/syscall.h interface # linux/regset.h user_regset interfaces # CORE_DUMP_USE_REGSET #define'd in linux/elf.h diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c index 5cf45fc51343..ff8cb638472e 100644 --- a/arch/alpha/kernel/pci.c +++ b/arch/alpha/kernel/pci.c @@ -338,7 +338,7 @@ common_swizzle(struct pci_dev *dev, u8 *pinp) return PCI_SLOT(dev->devfn); } -void __devinit +void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res) { diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c index e657c45d91d2..cf7da10097bb 100644 --- a/arch/alpha/kernel/smp.c +++ b/arch/alpha/kernel/smp.c @@ -121,7 +121,7 @@ wait_boot_cpu_to_stop(int cpuid) /* * Where secondaries begin a life of C. */ -void __init +void __cpuinit smp_callin(void) { int cpuid = hard_smp_processor_id(); @@ -198,7 +198,7 @@ wait_for_txrdy (unsigned long cpumask) * Send a message to a secondary's console. "START" is one such * interesting message. ;-) */ -static void __init +static void __cpuinit send_secondary_console_msg(char *str, int cpuid) { struct percpu_struct *cpu; @@ -289,7 +289,7 @@ recv_secondary_console_msg(void) /* * Convince the console to have a secondary cpu begin execution. */ -static int __init +static int __cpuinit secondary_cpu_start(int cpuid, struct task_struct *idle) { struct percpu_struct *cpu; diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index c778779007fc..cefc5a355ef9 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -31,7 +31,7 @@ static int opDEC_fix; -static void __init +static void __cpuinit opDEC_check(void) { __asm__ __volatile__ ( @@ -1072,7 +1072,7 @@ give_sigbus: return; } -void __init +void __cpuinit trap_init(void) { /* Tell PAL-code what global pointer we want in the kernel. */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5021db2217ed..9722f8bb506c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,8 +16,7 @@ config ARM select HAVE_ARCH_KGDB select HAVE_KPROBES if (!XIP_KERNEL) select HAVE_KRETPROBES if (HAVE_KPROBES) - select HAVE_FTRACE if (!XIP_KERNEL) - select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE) + select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) select HAVE_GENERIC_DMA_COHERENT help The ARM series is a line of low-power-consumption RISC chip designs diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 7a03f2007882..c47f2a3f8f8f 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -70,7 +70,7 @@ SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \ head.o misc.o $(OBJS) -ifeq ($(CONFIG_FTRACE),y) +ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 47ccec95f3e8..ef12794c3c68 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -630,7 +630,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) return -ENOMEM; sachip->clk = clk_get(me, "SA1111_CLK"); - if (!sachip->clk) { + if (IS_ERR(sachip->clk)) { ret = PTR_ERR(sachip->clk); goto err_free; } diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index db8309161408..780bbf7cb26f 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -54,11 +54,13 @@ /* * Prototypes */ +#ifdef CONFIG_PM static int sharpsl_off_charge_battery(void); -static int sharpsl_check_battery_temp(void); static int sharpsl_check_battery_voltage(void); -static int sharpsl_ac_check(void); static int sharpsl_fatal_check(void); +#endif +static int sharpsl_check_battery_temp(void); +static int sharpsl_ac_check(void); static int sharpsl_average_value(int ad); static void sharpsl_average_clear(void); static void sharpsl_charge_toggle(struct work_struct *private_); @@ -424,6 +426,7 @@ static int sharpsl_check_battery_temp(void) return 0; } +#ifdef CONFIG_PM static int sharpsl_check_battery_voltage(void) { int val, i, buff[5]; @@ -455,6 +458,7 @@ static int sharpsl_check_battery_voltage(void) return 0; } +#endif static int sharpsl_ac_check(void) { @@ -586,8 +590,6 @@ static int corgi_pxa_pm_enter(suspend_state_t state) return 0; } -#endif - /* * Check for fatal battery errors @@ -738,7 +740,10 @@ static int sharpsl_off_charge_battery(void) } } } - +#else +#define sharpsl_pm_suspend NULL +#define sharpsl_pm_resume NULL +#endif static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -768,10 +773,12 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info) info->battery_life = sharpsl_pm.battstat.mainbat_percent; } +#ifdef CONFIG_PM static struct platform_suspend_ops sharpsl_pm_ops = { .enter = corgi_pxa_pm_enter, .valid = suspend_valid_only_mem, }; +#endif static int __init sharpsl_pm_probe(struct platform_device *pdev) { @@ -802,7 +809,9 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) apm_get_power_status = sharpsl_apm_get_power_status; +#ifdef CONFIG_PM suspend_set_ops(&sharpsl_pm_ops); +#endif mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250)); diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index f3af0b593eb0..98765438048d 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -179,7 +179,7 @@ CONFIG_MACH_HUSKY=y # CONFIG_MACH_AKITA is not set # CONFIG_MACH_SPITZ is not set # CONFIG_MACH_BORZOI is not set -CONFIG_MACH_TOSA=y +# CONFIG_MACH_TOSA is not set # CONFIG_ARCH_VIPER is not set # CONFIG_ARCH_PXA_ESERIES is not set # CONFIG_TRIZEPS_PXA is not set diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 9a1db20e032a..63a481fbbed4 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -237,6 +237,7 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); #if __LINUX_ARM_ARCH__ < 5 #include +#include #include #include #include @@ -277,16 +278,19 @@ static inline int constant_fls(int x) * the clz instruction for much better code efficiency. */ -#define __fls(x) \ - ( __builtin_constant_p(x) ? constant_fls(x) : \ - ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) ) - -/* Implement fls() in C so that 64-bit args are suitably truncated */ static inline int fls(int x) { - return __fls(x); + int ret; + + if (__builtin_constant_p(x)) + return constant_fls(x); + + asm("clz\t%0, %1" : "=r" (ret) : "r" (x) : "cc"); + ret = 32 - ret; + return ret; } +#define __fls(x) (fls(x) - 1) #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) #define __ffs(x) (ffs(x) - 1) #define ffz(x) __ffs( ~(x) ) diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 1cb8602dd9d5..4ed149cbb32a 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -256,8 +256,17 @@ int dmabounce_sync_for_cpu(struct device *, dma_addr_t, unsigned long, int dmabounce_sync_for_device(struct device *, dma_addr_t, unsigned long, size_t, enum dma_data_direction); #else -#define dmabounce_sync_for_cpu(dev,dma,off,sz,dir) (1) -#define dmabounce_sync_for_device(dev,dma,off,sz,dir) (1) +static inline int dmabounce_sync_for_cpu(struct device *d, dma_addr_t addr, + unsigned long offset, size_t size, enum dma_data_direction dir) +{ + return 1; +} + +static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr, + unsigned long offset, size_t size, enum dma_data_direction dir) +{ + return 1; +} /** diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index 584ef9a8e5a5..39c8bc1a006a 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h @@ -1,7 +1,7 @@ #ifndef _ASM_ARM_FTRACE #define _ASM_ARM_FTRACE -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #define MCOUNT_ADDR ((long)(mcount)) #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h index 87bff09633aa..83e6ba338e2c 100644 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ b/arch/arm/include/asm/hardware/iop3xx-adma.h @@ -730,7 +730,8 @@ static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, { /* hw_desc->next_desc is the same location for all channels */ union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - BUG_ON(hw_desc.dma->next_desc); + + iop_paranoia(hw_desc.dma->next_desc); hw_desc.dma->next_desc = next_desc_addr; } @@ -760,7 +761,7 @@ static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) struct iop3xx_desc_aau *hw_desc = desc->hw_desc; struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; - BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); + iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); return desc_ctrl.zero_result_err; } diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h index cb7e3611bcba..385c6e8cbbd2 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/arch/arm/include/asm/hardware/iop_adma.h @@ -23,6 +23,12 @@ #define IOP_ADMA_SLOT_SIZE 32 #define IOP_ADMA_THRESHOLD 4 +#ifdef DEBUG +#define IOP_PARANOIA 1 +#else +#define IOP_PARANOIA 0 +#endif +#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) /** * struct iop_adma_device - internal representation of an ADMA device diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index cb1139ac1943..39d949b63e80 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -19,12 +19,13 @@ struct map_desc { }; /* types 0-3 are defined in asm/io.h */ -#define MT_CACHECLEAN 4 -#define MT_MINICLEAN 5 -#define MT_LOW_VECTORS 6 -#define MT_HIGH_VECTORS 7 -#define MT_MEMORY 8 -#define MT_ROM 9 +#define MT_UNCACHED 4 +#define MT_CACHECLEAN 5 +#define MT_MINICLEAN 6 +#define MT_LOW_VECTORS 7 +#define MT_HIGH_VECTORS 8 +#define MT_MEMORY 9 +#define MT_ROM 10 #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 809ff9ab853a..77764301844b 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -44,10 +44,10 @@ * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 32MB of the kernel text. */ -#define MODULE_END (PAGE_OFFSET) -#define MODULE_START (MODULE_END - 16*1048576) +#define MODULES_END (PAGE_OFFSET) +#define MODULES_VADDR (MODULES_END - 16*1048576) -#if TASK_SIZE > MODULE_START +#if TASK_SIZE > MODULES_VADDR #error Top of user space clashes with start of module space #endif @@ -56,7 +56,7 @@ * Since we use sections to map it, this macro replaces the physical address * with its virtual address while keeping offset from the base section. */ -#define XIP_VIRT_ADDR(physaddr) (MODULE_START + ((physaddr) & 0x000fffff)) +#define XIP_VIRT_ADDR(physaddr) (MODULES_VADDR + ((physaddr) & 0x000fffff)) /* * Allow 16MB-aligned ioremap pages @@ -94,8 +94,8 @@ /* * The module can be at any place in ram in nommu mode. */ -#define MODULE_END (END_MEM) -#define MODULE_START (PHYS_OFFSET) +#define MODULES_END (END_MEM) +#define MODULES_VADDR (PHYS_OFFSET) #endif /* !CONFIG_MMU */ diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 517a4d6ffc74..6ff33790f47b 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -23,7 +23,7 @@ #include #ifdef __KERNEL__ -#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ +#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ TASK_SIZE : TASK_SIZE_26) #define STACK_TOP_MAX TASK_SIZE #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7aad78420f18..568020b34e3e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -42,6 +42,10 @@ #define CR_U (1 << 22) /* Unaligned access operation */ #define CR_XP (1 << 23) /* Extended page tables */ #define CR_VE (1 << 24) /* Vectored interrupts */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ +#define CR_TRE (1 << 28) /* TEX remap enable */ +#define CR_AFE (1 << 29) /* Access flag enable */ +#define CR_TE (1 << 30) /* Thumb exception enable */ /* * This is used to ensure the compiler did actually allocate the register we diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 2357b1cf1cf9..23af3c972c9a 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -115,6 +115,8 @@ EXPORT_SYMBOL(__strnlen_user); EXPORT_SYMBOL(__strncpy_from_user); #ifdef CONFIG_MMU +EXPORT_SYMBOL(copy_page); + EXPORT_SYMBOL(__copy_from_user); EXPORT_SYMBOL(__copy_to_user); EXPORT_SYMBOL(__clear_user); @@ -181,8 +183,6 @@ EXPORT_SYMBOL(_find_first_bit_be); EXPORT_SYMBOL(_find_next_bit_be); #endif -EXPORT_SYMBOL(copy_page); - -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER EXPORT_SYMBOL(mcount); #endif diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c index 513f332f040d..84849098c8e8 100644 --- a/arch/arm/kernel/elf.c +++ b/arch/arm/kernel/elf.c @@ -21,12 +21,16 @@ int elf_check_arch(const struct elf32_hdr *x) eflags = x->e_flags; if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) { + unsigned int flt_fmt; + /* APCS26 is only allowed if the CPU supports it */ if ((eflags & EF_ARM_APCS_26) && !(elf_hwcap & HWCAP_26BIT)) return 0; + flt_fmt = eflags & (EF_ARM_VFP_FLOAT | EF_ARM_SOFT_FLOAT); + /* VFP requires the supporting code */ - if ((eflags & EF_ARM_VFP_FLOAT) && !(elf_hwcap & HWCAP_VFP)) + if (flt_fmt == EF_ARM_VFP_FLOAT && !(elf_hwcap & HWCAP_VFP)) return 0; } return 1; diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 3aa14dcc5bab..06269ea375c5 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -101,7 +101,7 @@ ENDPROC(ret_from_fork) #undef CALL #define CALL(x) .long x -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(mcount) stmdb sp!, {r0-r3, lr} @@ -149,7 +149,7 @@ trace: ftrace_stub: mov pc, lr -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ /*============================================================================= * SWI handler diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 76d50e6091bc..6c90479e8974 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -95,19 +95,6 @@ int ftrace_update_ftrace_func(ftrace_func_t func) return ret; } -int ftrace_mcount_set(unsigned long *data) -{ - unsigned long pc, old; - unsigned long *addr = data; - unsigned char *new; - - pc = (unsigned long)&mcount_call; - memcpy(&old, &mcount_call, MCOUNT_INSN_SIZE); - new = ftrace_call_replace(pc, *addr); - *addr = ftrace_modify_code(pc, (unsigned char *)&old, new); - return 0; -} - /* run from kstop_machine */ int __init ftrace_dyn_arch_init(void *data) { diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 9203ba7d58ee..b8d965dcd6fd 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -26,12 +26,12 @@ /* * The XIP kernel text is mapped in the module area for modules and * some other stuff to work without any indirect relocations. - * MODULE_START is redefined here and not in asm/memory.h to avoid + * MODULES_VADDR is redefined here and not in asm/memory.h to avoid * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. */ extern void _etext; -#undef MODULE_START -#define MODULE_START (((unsigned long)&_etext + ~PGDIR_MASK) & PGDIR_MASK) +#undef MODULES_VADDR +#define MODULES_VADDR (((unsigned long)&_etext + ~PGDIR_MASK) & PGDIR_MASK) #endif #ifdef CONFIG_MMU @@ -43,7 +43,7 @@ void *module_alloc(unsigned long size) if (!size) return NULL; - area = __get_vm_area(size, VM_ALLOC, MODULE_START, MODULE_END); + area = __get_vm_area(size, VM_ALLOC, MODULES_VADDR, MODULES_END); if (!area) return NULL; diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 57e6874d0b80..79abc4ddc0cf 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 9c040c78889a..e263fda3e2d1 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -165,6 +165,7 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = { static struct i2c_board_info __initdata afeb9260_i2c_devices[] = { { I2C_BOARD_INFO("fm3130", 0x68), + }, { I2C_BOARD_INFO("24c64", 0x50), }, }; diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 76d76e2fa69e..bffa6741a751 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARCH_AT91RM9200_GPIO_H #define __ASM_ARCH_AT91RM9200_GPIO_H +#include #include #define PIN_BASE NR_AIC_IRQS @@ -220,6 +221,7 @@ static inline int gpio_request(unsigned gpio, const char *label) static inline void gpio_free(unsigned gpio) { + might_sleep(); } extern int gpio_direction_input(unsigned gpio); diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 4c3e101b96c9..b3ebe9e4871f 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -94,20 +94,6 @@ #include #include -/* dynamic ioremap() areas */ -#define FLASH_START 0x00000000 -#define FLASH_SIZE 0x800000 -#define FLASH_WIDTH 4 - -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0xc000 -#define SRAM_WIDTH 4 - -#define BOOTROM_START 0x70000000 -#define BOOTROM_SIZE 0x80 -#define BOOTROM_WIDTH 4 - - /* static cdb89712_map_io() areas */ #define REGISTER_START 0x80000000 #define REGISTER_SIZE 0x4000 @@ -198,14 +184,6 @@ #define CEIVA_FLASH_SIZE 0x100000 #define CEIVA_FLASH_WIDTH 2 -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0xc000 -#define SRAM_WIDTH 4 - -#define BOOTROM_START 0x70000000 -#define BOOTROM_SIZE 0x80 -#define BOOTROM_WIDTH 4 - /* * SED1355 LCD controller */ diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c index c3a33b8a5aac..7e247c04d41c 100644 --- a/arch/arm/mach-clps7500/core.c +++ b/arch/arm/mach-clps7500/core.c @@ -275,9 +275,9 @@ static struct map_desc cl7500_io_desc[] __initdata = { .length = ISA_SIZE, .type = MT_DEVICE }, { /* Flash */ - .virtual = FLASH_BASE, - .pfn = __phys_to_pfn(FLASH_START), - .length = FLASH_SIZE, + .virtual = CLPS7500_FLASH_BASE, + .pfn = __phys_to_pfn(CLPS7500_FLASH_START), + .length = CLPS7500_FLASH_SIZE, .type = MT_DEVICE }, { /* LED */ .virtual = LED_BASE, diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h index d66578a3371c..a6ad1d44badf 100644 --- a/arch/arm/mach-clps7500/include/mach/hardware.h +++ b/arch/arm/mach-clps7500/include/mach/hardware.h @@ -39,9 +39,9 @@ #define ISA_SIZE 0x00010000 #define ISA_BASE 0xe1000000 -#define FLASH_START 0x01000000 /* XXX */ -#define FLASH_SIZE 0x01000000 -#define FLASH_BASE 0xe2000000 +#define CLPS7500_FLASH_START 0x01000000 /* XXX */ +#define CLPS7500_FLASH_SIZE 0x01000000 +#define CLPS7500_FLASH_BASE 0xe2000000 #define LED_START 0x0302B000 #define LED_SIZE 0x00001000 diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index de53f0be71b9..48345fb34613 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -449,12 +450,13 @@ static struct resource ep93xx_ohci_resources[] = { }, }; + static struct platform_device ep93xx_ohci_device = { .name = "ep93xx-ohci", .id = -1, .dev = { - .dma_mask = (void *)0xffffffff, - .coherent_dma_mask = 0xffffffff, + .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), .resource = ep93xx_ohci_resources, diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h index 079b279e1242..38b8e0d61fbf 100644 --- a/arch/arm/mach-h720x/include/mach/boards.h +++ b/arch/arm/mach-h720x/include/mach/boards.h @@ -19,9 +19,9 @@ #ifdef CONFIG_ARCH_H7202 /* FLASH */ -#define FLASH_VIRT 0xd0000000 -#define FLASH_PHYS 0x00000000 -#define FLASH_SIZE 0x02000000 +#define H720X_FLASH_VIRT 0xd0000000 +#define H720X_FLASH_PHYS 0x00000000 +#define H720X_FLASH_SIZE 0x02000000 /* onboard LAN controller */ # define ETH0_PHYS 0x08000000 diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h index 6e3d795f2264..502d5aa2c093 100644 --- a/arch/arm/mach-imx/include/mach/gpio.h +++ b/arch/arm/mach-imx/include/mach/gpio.h @@ -1,5 +1,6 @@ #ifndef _IMX_GPIO_H +#include #include #define IMX_GPIO_ALLOC_MODE_NORMAL 0 @@ -63,6 +64,8 @@ static inline int gpio_request(unsigned gpio, const char *label) static inline void gpio_free(unsigned gpio) { + might_sleep(); + imx_gpio_free(gpio); } diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index 028b87839c0f..e00a2624f269 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -407,28 +407,11 @@ */ #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE -/* - * Application Flash - * - */ -#define FLASH_BASE INTEGRATOR_FLASH_BASE -#define FLASH_SIZE INTEGRATOR_FLASH_SIZE -#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) -#define FLASH_BLOCK_SIZE SZ_128K - -/* - * Boot Flash - * - */ -#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI -#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE -#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) - /* * Clean base - dummy * */ -#define CLEAN_BASE EPROM_BASE +#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI /* * Timer definitions diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h index 60019c8e6465..5722e86f2174 100644 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ b/arch/arm/mach-iop13xx/include/mach/adma.h @@ -404,7 +404,8 @@ static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, u32 next_desc_addr) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - BUG_ON(hw_desc->next_desc); + + iop_paranoia(hw_desc->next_desc); hw_desc->next_desc = next_desc_addr; } diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h index 9fbde177920f..cd5aec26c072 100644 --- a/arch/arm/mach-ixp4xx/include/mach/gpio.h +++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h @@ -25,6 +25,7 @@ #ifndef __ASM_ARCH_IXP4XX_GPIO_H #define __ASM_ARCH_IXP4XX_GPIO_H +#include #include static inline int gpio_request(unsigned gpio, const char *label) @@ -34,6 +35,8 @@ static inline int gpio_request(unsigned gpio, const char *label) static inline void gpio_free(unsigned gpio) { + might_sleep(); + return; } diff --git a/arch/arm/mach-ks8695/include/mach/gpio.h b/arch/arm/mach-ks8695/include/mach/gpio.h index 73c84168761c..d4af5c335f16 100644 --- a/arch/arm/mach-ks8695/include/mach/gpio.h +++ b/arch/arm/mach-ks8695/include/mach/gpio.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_GPIO_H_ #define __ASM_ARCH_GPIO_H_ +#include + #define KS8695_GPIO_0 0 #define KS8695_GPIO_1 1 #define KS8695_GPIO_2 2 @@ -74,6 +76,7 @@ static inline int gpio_request(unsigned int pin, const char *label) static inline void gpio_free(unsigned int pin) { + might_sleep(); } #endif diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index 1be4a390c63f..f902a7c37c31 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -35,6 +35,8 @@ #include #include +#include "devices.h" + /*! * @file mx31ads.c * diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 11fda95c86a5..843f68c8ead1 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c @@ -91,12 +91,12 @@ static struct map_desc pcm037_io_desc[] __initdata = { .virtual = AIPS1_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), .length = AIPS1_SIZE, - .type = MT_DEVICE + .type = MT_DEVICE_NONSHARED }, { .virtual = AIPS2_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), .length = AIPS2_SIZE, - .type = MT_DEVICE + .type = MT_DEVICE_NONSHARED }, }; diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c index 5241e6a286cc..5503ca09c4ae 100644 --- a/arch/arm/mach-ns9xxx/gpio.c +++ b/arch/arm/mach-ns9xxx/gpio.c @@ -8,6 +8,7 @@ * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ +#include #include #include #include @@ -63,6 +64,7 @@ EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned gpio) { + might_sleep(); clear_bit(gpio, gpiores); return; } diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index b3bd8ca85118..4c3e582f3d3c 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -128,7 +128,7 @@ void __init omap1_map_common_io(void) * Common low-level hardware init for omap1. This should only get called from * board specific init. */ -void __init omap1_init_common_hw() +void __init omap1_init_common_hw(void) { /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort * on a Posted Write in the TIPB Bridge". diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 763bdbeaf681..2249049c1d5a 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -429,18 +429,16 @@ void __init gpmc_init(void) gpmc_l3_clk = clk_get(NULL, ck); if (IS_ERR(gpmc_l3_clk)) { printk(KERN_ERR "Could not get GPMC clock %s\n", ck); - return -ENODEV; + BUG(); } gpmc_base = ioremap(l, SZ_4K); if (!gpmc_base) { clk_put(gpmc_l3_clk); printk(KERN_ERR "Could not get GPMC register memory\n"); - return -ENOMEM; + BUG(); } - BUG_ON(IS_ERR(gpmc_l3_clk)); - l = gpmc_read_reg(GPMC_REVISION); printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); /* Set smart idle mode and automatic L3 clock gating */ diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c index fc419868e39f..f99d08811e5a 100644 --- a/arch/arm/mach-orion5x/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c @@ -165,6 +165,8 @@ EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned pin) { + might_sleep(); + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { pr_debug("%s: invalid GPIO %d\n", __func__, pin); return; diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index eb7d6c94aa42..e35259032813 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -204,7 +204,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = { .read_devdata = corgipm_read_devdata, .charger_wakeup = corgi_charger_wakeup, .should_wakeup = corgi_should_wakeup, -#ifdef CONFIG_BACKLIGHT_CORGI +#if defined(CONFIG_LCD_CORGI) + .backlight_limit = corgi_lcd_limit_intensity, +#elif defined(CONFIG_BACKLIGHT_CORGI) .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index 8e591118371e..cbda4d35c421 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -33,6 +33,7 @@ #define LCD_CONN_TYPE(_x) ((_x) & 0x0f) #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f) +#define LCD_TYPE_MASK 0xf #define LCD_TYPE_UNKNOWN 0 #define LCD_TYPE_MONO_STN 1 #define LCD_TYPE_MONO_DSTN 2 diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h index 7b8842cfa5fc..31e6a7b6ad80 100644 --- a/arch/arm/mach-pxa/include/mach/reset.h +++ b/arch/arm/mach-pxa/include/mach/reset.h @@ -12,9 +12,8 @@ extern void clear_reset_status(unsigned int mask); /** * init_gpio_reset() - register GPIO as reset generator - * - * @gpio - gpio nr - * @output - set gpio as out/low instead of input during normal work + * @gpio: gpio nr + * @output: set gpio as out/low instead of input during normal work */ extern int init_gpio_reset(int gpio, int output); diff --git a/arch/arm/mach-pxa/include/mach/sharpsl.h b/arch/arm/mach-pxa/include/mach/sharpsl.h index 3b1d4a72d4d1..8242e14a44fa 100644 --- a/arch/arm/mach-pxa/include/mach/sharpsl.h +++ b/arch/arm/mach-pxa/include/mach/sharpsl.h @@ -26,6 +26,7 @@ struct corgits_machinfo { * SharpSL Backlight */ extern void corgibl_limit_intensity(int limit); +extern void corgi_lcd_limit_intensity(int limit); /* diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 0842c531ee4d..782903fe9c6c 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -565,7 +565,7 @@ static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state) u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR); /* Devices prepare suspend */ - is_bt_on = gpio_get_value(GPIO83_BT_ON); + is_bt_on = !!gpio_get_value(GPIO83_BT_ON); pxa2xx_mfp_set_lpm(GPIO83_BT_ON, is_bt_on ? MFP_LPM_DRIVE_HIGH : MFP_LPM_DRIVE_LOW); diff --git a/arch/arm/mach-pxa/mioa701_bootresume.S b/arch/arm/mach-pxa/mioa701_bootresume.S index a647693d9856..324d25a48c85 100644 --- a/arch/arm/mach-pxa/mioa701_bootresume.S +++ b/arch/arm/mach-pxa/mioa701_bootresume.S @@ -24,6 +24,7 @@ ENTRY(mioa701_jumpaddr) 1: mov r0, #0xa0000000 @ Don't suppose memory access works orr r0, r0, #0x00200000 @ even if it's supposed to + orr r0, r0, #0x0000b000 mov r1, #0 str r1, [r0] @ Early disable resume for next boot ldr r0, mioa701_jumpaddr @ (Murphy's Law) diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 4447711c9fc6..a9d94f5dbec4 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -56,6 +56,9 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO110_MMC_DAT_2, GPIO111_MMC_DAT_3, GPIO112_MMC_CMD, + GPIO14_GPIO, /* SD detect */ + GPIO114_GPIO, /* SD power */ + GPIO115_GPIO, /* SD r/o switch */ /* AC97 */ GPIO28_AC97_BITCLK, @@ -64,6 +67,7 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO31_AC97_SYNC, /* IrDA */ + GPIO40_GPIO, /* ir disable */ GPIO46_FICP_RXD, GPIO47_FICP_TXD, @@ -71,7 +75,8 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO16_PWM0_OUT, /* USB */ - GPIO13_GPIO, + GPIO13_GPIO, /* usb detect */ + GPIO95_GPIO, /* usb power */ /* PCMCIA */ GPIO48_nPOE, @@ -84,6 +89,45 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO55_nPREG, GPIO56_nPWAIT, GPIO57_nIOIS16, + GPIO94_GPIO, /* wifi power 1 */ + GPIO108_GPIO, /* wifi power 2 */ + GPIO116_GPIO, /* wifi ready */ + + /* MATRIX KEYPAD */ + GPIO100_KP_MKIN_0, + GPIO101_KP_MKIN_1, + GPIO102_KP_MKIN_2, + GPIO97_KP_MKIN_3, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + + /* LCD */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + GPIO77_LCD_BIAS, + + /* MISC. */ + GPIO10_GPIO, /* hotsync button */ + GPIO12_GPIO, /* power detect */ + GPIO107_GPIO, /* earphone detect */ }; /****************************************************************************** @@ -95,32 +139,49 @@ static int palmtx_mci_init(struct device *dev, irq_handler_t palmtx_detect_int, int err = 0; /* Setup an interrupt for detecting card insert/remove events */ - err = request_irq(IRQ_GPIO_PALMTX_SD_DETECT_N, palmtx_detect_int, - IRQF_DISABLED | IRQF_SAMPLE_RANDOM | + err = gpio_request(GPIO_NR_PALMTX_SD_DETECT_N, "SD IRQ"); + if (err) + goto err; + err = gpio_direction_input(GPIO_NR_PALMTX_SD_DETECT_N); + if (err) + goto err2; + err = request_irq(gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N), + palmtx_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "SD/MMC card detect", data); if (err) { printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", __func__); - return err; + goto err2; } err = gpio_request(GPIO_NR_PALMTX_SD_POWER, "SD_POWER"); if (err) - goto pwr_err; + goto err3; + err = gpio_direction_output(GPIO_NR_PALMTX_SD_POWER, 0); + if (err) + goto err4; err = gpio_request(GPIO_NR_PALMTX_SD_READONLY, "SD_READONLY"); if (err) - goto ro_err; + goto err4; + err = gpio_direction_input(GPIO_NR_PALMTX_SD_READONLY); + if (err) + goto err5; printk(KERN_DEBUG "%s: irq registered\n", __func__); return 0; -ro_err: +err5: + gpio_free(GPIO_NR_PALMTX_SD_READONLY); +err4: gpio_free(GPIO_NR_PALMTX_SD_POWER); -pwr_err: - free_irq(IRQ_GPIO_PALMTX_SD_DETECT_N, data); +err3: + free_irq(gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N), data); +err2: + gpio_free(GPIO_NR_PALMTX_SD_DETECT_N); +err: return err; } @@ -128,7 +189,8 @@ static void palmtx_mci_exit(struct device *dev, void *data) { gpio_free(GPIO_NR_PALMTX_SD_READONLY); gpio_free(GPIO_NR_PALMTX_SD_POWER); - free_irq(IRQ_GPIO_PALMTX_SD_DETECT_N, data); + free_irq(gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N), data); + gpio_free(GPIO_NR_PALMTX_SD_DETECT_N); } static void palmtx_mci_power(struct device *dev, unsigned int vdd) @@ -167,7 +229,6 @@ static unsigned int palmtx_matrix_keys[] = { KEY(3, 0, KEY_RIGHT), KEY(3, 2, KEY_LEFT), - }; static struct pxa27x_keypad_platform_data palmtx_keypad_platform_data = { @@ -209,11 +270,19 @@ static int palmtx_backlight_init(struct device *dev) ret = gpio_request(GPIO_NR_PALMTX_BL_POWER, "BL POWER"); if (ret) goto err; + ret = gpio_direction_output(GPIO_NR_PALMTX_BL_POWER, 0); + if (ret) + goto err2; ret = gpio_request(GPIO_NR_PALMTX_LCD_POWER, "LCD POWER"); if (ret) goto err2; + ret = gpio_direction_output(GPIO_NR_PALMTX_LCD_POWER, 0); + if (ret) + goto err3; return 0; +err3: + gpio_free(GPIO_NR_PALMTX_LCD_POWER); err2: gpio_free(GPIO_NR_PALMTX_BL_POWER); err: @@ -254,6 +323,24 @@ static struct platform_device palmtx_backlight = { /****************************************************************************** * IrDA ******************************************************************************/ +static int palmtx_irda_startup(struct device *dev) +{ + int err; + err = gpio_request(GPIO_NR_PALMTX_IR_DISABLE, "IR DISABLE"); + if (err) + goto err; + err = gpio_direction_output(GPIO_NR_PALMTX_IR_DISABLE, 1); + if (err) + gpio_free(GPIO_NR_PALMTX_IR_DISABLE); +err: + return err; +} + +static void palmtx_irda_shutdown(struct device *dev) +{ + gpio_free(GPIO_NR_PALMTX_IR_DISABLE); +} + static void palmtx_irda_transceiver_mode(struct device *dev, int mode) { gpio_set_value(GPIO_NR_PALMTX_IR_DISABLE, mode & IR_OFF); @@ -261,6 +348,8 @@ static void palmtx_irda_transceiver_mode(struct device *dev, int mode) } static struct pxaficp_platform_data palmtx_ficp_platform_data = { + .startup = palmtx_irda_startup, + .shutdown = palmtx_irda_shutdown, .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, .transceiver_mode = palmtx_irda_transceiver_mode, }; @@ -268,17 +357,11 @@ static struct pxaficp_platform_data palmtx_ficp_platform_data = { /****************************************************************************** * UDC ******************************************************************************/ -static void palmtx_udc_command(int cmd) -{ - gpio_set_value(GPIO_NR_PALMTX_USB_POWER, !cmd); - udelay(50); - gpio_set_value(GPIO_NR_PALMTX_USB_PULLUP, !cmd); -} - static struct pxa2xx_udc_mach_info palmtx_udc_info __initdata = { .gpio_vbus = GPIO_NR_PALMTX_USB_DETECT_N, .gpio_vbus_inverted = 1, - .udc_command = palmtx_udc_command, + .gpio_pullup = GPIO_NR_PALMTX_USB_POWER, + .gpio_pullup_inverted = 0, }; /****************************************************************************** @@ -290,17 +373,16 @@ static int power_supply_init(struct device *dev) ret = gpio_request(GPIO_NR_PALMTX_POWER_DETECT, "CABLE_STATE_AC"); if (ret) - goto err_cs_ac; - - ret = gpio_request(GPIO_NR_PALMTX_USB_DETECT_N, "CABLE_STATE_USB"); + goto err1; + ret = gpio_direction_input(GPIO_NR_PALMTX_POWER_DETECT); if (ret) - goto err_cs_usb; + goto err2; return 0; -err_cs_usb: +err2: gpio_free(GPIO_NR_PALMTX_POWER_DETECT); -err_cs_ac: +err1: return ret; } @@ -309,14 +391,8 @@ static int palmtx_is_ac_online(void) return gpio_get_value(GPIO_NR_PALMTX_POWER_DETECT); } -static int palmtx_is_usb_online(void) -{ - return !gpio_get_value(GPIO_NR_PALMTX_USB_DETECT_N); -} - static void power_supply_exit(struct device *dev) { - gpio_free(GPIO_NR_PALMTX_USB_DETECT_N); gpio_free(GPIO_NR_PALMTX_POWER_DETECT); } @@ -327,7 +403,6 @@ static char *palmtx_supplicants[] = { static struct pda_power_pdata power_supply_info = { .init = power_supply_init, .is_ac_online = palmtx_is_ac_online, - .is_usb_online = palmtx_is_usb_online, .exit = power_supply_exit, .supplied_to = palmtx_supplicants, .num_supplicants = ARRAY_SIZE(palmtx_supplicants), @@ -410,12 +485,23 @@ static void __init palmtx_map_io(void) iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc)); } +/* setup udc GPIOs initial state */ +static void __init palmtx_udc_init(void) +{ + if (!gpio_request(GPIO_NR_PALMTX_USB_POWER, "UDC Vbus")) { + gpio_direction_output(GPIO_NR_PALMTX_USB_POWER, 1); + gpio_free(GPIO_NR_PALMTX_USB_POWER); + } +} + + static void __init palmtx_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config)); set_pxa_fb_info(&palmtx_lcd_screen); pxa_set_mci_info(&palmtx_mci_platform_data); + palmtx_udc_init(); pxa_set_udc_info(&palmtx_udc_info); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&palmtx_ficp_platform_data); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index f601425f1b1e..b36cec5c9eed 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -385,6 +385,7 @@ static struct soc_camera_link iclink[] = { .gpio = NR_BUILTIN_GPIO + 1, }, { .bus_id = 0, /* Must match with the camera ID above */ + .gpio = -ENXIO, } }; diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index 1b2af575c40f..00b2dc2a1074 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c @@ -90,12 +90,13 @@ void arch_reset(char mode) /* Jump into ROM at address 0 */ cpu_reset(0); break; - case 'h': - do_hw_reset(); - break; case 'g': do_gpio_reset(); break; + case 'h': + default: + do_hw_reset(); + break; } } diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 524f656dc56d..3be76ee2bdbf 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -67,6 +67,7 @@ static unsigned long spitz_pin_config[] __initdata = { /* Chip Selects */ GPIO78_nCS_2, /* SCOOP #2 */ + GPIO79_nCS_3, /* NAND */ GPIO80_nCS_4, /* SCOOP #1 */ /* LCD - 16bpp Active TFT */ @@ -97,10 +98,10 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO51_nPIOW, GPIO85_nPCE_1, GPIO54_nPCE_2, - GPIO79_PSKTSEL, GPIO55_nPREG, GPIO56_nPWAIT, GPIO57_nIOIS16, + GPIO104_PSKTSEL, /* MMC */ GPIO32_MMC_CLK, @@ -385,6 +386,16 @@ static void __init spitz_init_spi(void) if (err) goto err_free_2; + err = gpio_direction_output(SPITZ_GPIO_ADS7846_CS, 1); + if (err) + goto err_free_3; + err = gpio_direction_output(SPITZ_GPIO_LCDCON_CS, 1); + if (err) + goto err_free_3; + err = gpio_direction_output(SPITZ_GPIO_MAX1111_CS, 1); + if (err) + goto err_free_3; + if (machine_is_akita()) { spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; @@ -394,6 +405,8 @@ static void __init spitz_init_spi(void) spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices)); return; +err_free_3: + gpio_free(SPITZ_GPIO_MAX1111_CS); err_free_2: gpio_free(SPITZ_GPIO_LCDCON_CS); err_free_1: @@ -674,7 +687,6 @@ static void __init akita_init(void) spitz_pcmcia_config.num_devs = 1; platform_scoop_config = &spitz_pcmcia_config; - pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info)); common_init(); diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 53018db106ac..072e77cfe5a3 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -198,7 +198,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { .read_devdata = spitzpm_read_devdata, .charger_wakeup = spitz_charger_wakeup, .should_wakeup = spitz_should_wakeup, -#ifdef CONFIG_BACKLIGHT_CORGI +#if defined(CONFIG_LCD_CORGI) + .backlight_limit = corgi_lcd_limit_intensity, +#elif defined(CONFIG_BACKLIGHT_CORGI) .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c index 3e706c57833a..3347c4236a60 100644 --- a/arch/arm/mach-realview/clock.c +++ b/arch/arm/mach-realview/clock.c @@ -104,7 +104,7 @@ static struct clk uart_clk = { static struct clk mmci_clk = { .name = "MCLK", - .rate = 33000000, + .rate = 24000000, }; int clk_register(struct clk *clk) diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h index 4034b54950c2..793a3a332712 100644 --- a/arch/arm/mach-realview/include/mach/platform.h +++ b/arch/arm/mach-realview/include/mach/platform.h @@ -238,28 +238,11 @@ #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ -/* - * Application Flash - * - */ -#define FLASH_BASE REALVIEW_FLASH_BASE -#define FLASH_SIZE REALVIEW_FLASH_SIZE -#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) -#define FLASH_BLOCK_SIZE SZ_128K - -/* - * Boot Flash - * - */ -#define EPROM_BASE REALVIEW_BOOT_ROM_HI -#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE -#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) - /* * Clean base - dummy * */ -#define CLEAN_BASE EPROM_BASE +#define CLEAN_BASE REALVIEW_BOOT_ROM_HI /* * System controller bit assignment diff --git a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h index 3fe8be9ca110..980a099e209c 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h @@ -18,6 +18,7 @@ struct s3c2410_spigpio_info { unsigned long pin_mosi; unsigned long pin_miso; + int num_chipselect; int bus_num; void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs); diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c index 9336508ec0b2..58937f1fb38c 100644 --- a/arch/arm/mach-versatile/clock.c +++ b/arch/arm/mach-versatile/clock.c @@ -105,7 +105,7 @@ static struct clk uart_clk = { static struct clk mmci_clk = { .name = "MCLK", - .rate = 33000000, + .rate = 24000000, }; int clk_register(struct clk *clk) diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index 27cbe6a3f220..f91ba930ca8a 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h @@ -436,28 +436,12 @@ #define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) #define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) #define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) -/* - * Application Flash - * - */ -#define FLASH_BASE VERSATILE_FLASH_BASE -#define FLASH_SIZE VERSATILE_FLASH_SIZE -#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) -#define FLASH_BLOCK_SIZE SZ_128K - -/* - * Boot Flash - * - */ -#define EPROM_BASE VERSATILE_BOOT_ROM_HI -#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE -#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) /* * Clean base - dummy * */ -#define CLEAN_BASE EPROM_BASE +#define CLEAN_BASE VERSATILE_BOOT_ROM_HI /* * System controller bit assignment diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 133e65d166b3..2d5884ce0435 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -70,6 +70,10 @@ static unsigned long ai_dword; static unsigned long ai_multi; static int ai_usermode; +#define UM_WARN (1 << 0) +#define UM_FIXUP (1 << 1) +#define UM_SIGNAL (1 << 2) + #ifdef CONFIG_PROC_FS static const char *usermode_action[] = { "ignored", @@ -754,7 +758,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) user: ai_user += 1; - if (ai_usermode & 1) + if (ai_usermode & UM_WARN) printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " "Address=0x%08lx FSR 0x%03x\n", current->comm, task_pid_nr(current), instrptr, @@ -762,10 +766,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) thumb_mode(regs) ? tinstr : instr, addr, fsr); - if (ai_usermode & 2) + if (ai_usermode & UM_FIXUP) goto fixup; - if (ai_usermode & 4) + if (ai_usermode & UM_SIGNAL) force_sig(SIGBUS, current); else set_cr(cr_no_alignment); @@ -796,6 +800,22 @@ static int __init alignment_init(void) res->write_proc = proc_alignment_write; #endif + /* + * ARMv6 and later CPUs can perform unaligned accesses for + * most single load and store instructions up to word size. + * LDM, STM, LDRD and STRD still need to be handled. + * + * Ignoring the alignment fault is not an option on these + * CPUs since we spin re-faulting the instruction without + * making any progress. + */ + if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) { + cr_alignment &= ~CR_A; + cr_no_alignment &= ~CR_A; + set_cr(cr_alignment); + ai_usermode = UM_FIXUP; + } + hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 13cdae8b0d44..80cd207cbaea 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -150,7 +150,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) /* * Clean and invalidate partial last cache line. */ - if (end & (CACHE_LINE_SIZE - 1)) { + if (start < end && end & (CACHE_LINE_SIZE - 1)) { l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); end &= ~(CACHE_LINE_SIZE - 1); } @@ -158,7 +158,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) /* * Invalidate all full cache lines between 'start' and 'end'. */ - while (start != end) { + while (start < end) { unsigned long range_end = calc_range_end(start, end); l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); start = range_end; diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 10b1bae1a258..464de893a988 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -98,7 +98,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end) /* * Clean and invalidate partial last cache line. */ - if (end & (CACHE_LINE_SIZE - 1)) { + if (start < end && (end & (CACHE_LINE_SIZE - 1))) { xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1)); xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); end &= ~(CACHE_LINE_SIZE - 1); @@ -107,7 +107,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end) /* * Invalidate all full cache lines between 'start' and 'end'. */ - while (start != end) { + while (start < end) { xsc3_l2_inv_pa(start); start += CACHE_LINE_SIZE; } diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 2df8d9facf57..22c9530e91e2 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 8ba754064559..7f36c825718d 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -180,20 +180,20 @@ void adjust_cr(unsigned long mask, unsigned long set) #endif #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE -#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE +#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE static struct mem_type mem_types[] = { [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | L_PTE_SHARED, .prot_l1 = PMD_TYPE_TABLE, - .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED, + .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, .domain = DOMAIN_IO, }, [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, .prot_l1 = PMD_TYPE_TABLE, - .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2), + .prot_sect = PROT_SECT_DEVICE, .domain = DOMAIN_IO, }, [MT_DEVICE_CACHED] = { /* ioremap_cached */ @@ -205,7 +205,13 @@ static struct mem_type mem_types[] = { [MT_DEVICE_WC] = { /* ioremap_wc */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, .prot_l1 = PMD_TYPE_TABLE, - .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE, + .prot_sect = PROT_SECT_DEVICE, + .domain = DOMAIN_IO, + }, + [MT_UNCACHED] = { + .prot_pte = PROT_PTE_DEVICE, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, .domain = DOMAIN_IO, }, [MT_CACHECLEAN] = { @@ -273,22 +279,23 @@ static void __init build_mem_type_table(void) #endif /* - * On non-Xscale3 ARMv5-and-older systems, use CB=01 - * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3 - * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable - * in xsc3 parlance, Uncached Normal in ARMv6 parlance). + * Strip out features not present on earlier architectures. + * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those + * without extended page tables don't have the 'Shared' bit. */ - if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) { - mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); - mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE; - } + if (cpu_arch < CPU_ARCH_ARMv5) + for (i = 0; i < ARRAY_SIZE(mem_types); i++) + mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); + if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) + for (i = 0; i < ARRAY_SIZE(mem_types); i++) + mem_types[i].prot_sect &= ~PMD_SECT_S; /* - * ARMv5 and lower, bit 4 must be set for page tables. - * (was: cache "update-able on write" bit on ARM610) - * However, Xscale cores require this bit to be cleared. + * ARMv5 and lower, bit 4 must be set for page tables (was: cache + * "update-able on write" bit on ARM610). However, Xscale and + * Xscale3 require this bit to be cleared. */ - if (cpu_is_xscale()) { + if (cpu_is_xscale() || cpu_is_xsc3()) { for (i = 0; i < ARRAY_SIZE(mem_types); i++) { mem_types[i].prot_sect &= ~PMD_BIT4; mem_types[i].prot_l1 &= ~PMD_BIT4; @@ -302,6 +309,64 @@ static void __init build_mem_type_table(void) } } + /* + * Mark the device areas according to the CPU/architecture. + */ + if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { + if (!cpu_is_xsc3()) { + /* + * Mark device regions on ARMv6+ as execute-never + * to prevent speculative instruction fetches. + */ + mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; + mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; + mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; + } + if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { + /* + * For ARMv7 with TEX remapping, + * - shared device is SXCB=1100 + * - nonshared device is SXCB=0100 + * - write combine device mem is SXCB=0001 + * (Uncached Normal memory) + */ + mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); + mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; + } else if (cpu_is_xsc3()) { + /* + * For Xscale3, + * - shared device is TEXCB=00101 + * - nonshared device is TEXCB=01000 + * - write combine device mem is TEXCB=00100 + * (Inner/Outer Uncacheable in xsc3 parlance) + */ + mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; + mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); + } else { + /* + * For ARMv6 and ARMv7 without TEX remapping, + * - shared device is TEXCB=00001 + * - nonshared device is TEXCB=01000 + * - write combine device mem is TEXCB=00100 + * (Uncached Normal in ARMv6 parlance). + */ + mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; + mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); + } + } else { + /* + * On others, write combining is "Uncached/Buffered" + */ + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; + } + + /* + * Now deal with the memory-type mappings + */ cp = &cache_policies[cachepolicy]; vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; @@ -317,12 +382,8 @@ static void __init build_mem_type_table(void) * Enable CPU-specific coherency if supported. * (Only available on XSC3 at the moment.) */ - if (arch_is_coherent()) { - if (cpu_is_xsc3()) { - mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; - mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; - } - } + if (arch_is_coherent() && cpu_is_xsc3()) + mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; /* * ARMv6 and above have extended page tables. @@ -336,11 +397,6 @@ static void __init build_mem_type_table(void) mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; - /* - * Mark the device area as "shared device" - */ - mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; - #ifdef CONFIG_SMP /* * Mark memory with the "shared" attribute for SMP systems @@ -360,9 +416,6 @@ static void __init build_mem_type_table(void) mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; - if (cpu_arch < CPU_ARCH_ARMv5) - mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); - pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_WRITE | @@ -654,7 +707,7 @@ static inline void prepare_page_table(struct meminfo *mi) /* * Clear out all the mappings below the kernel image. */ - for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) + for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) pmd_clear(pmd_off_k(addr)); #ifdef CONFIG_XIP_KERNEL @@ -766,7 +819,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) */ #ifdef CONFIG_XIP_KERNEL map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); - map.virtual = MODULE_START; + map.virtual = MODULES_VADDR; map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; map.type = MT_ROM; create_mapping(&map); diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 07f82db70945..4d3c0a73e7fb 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -115,7 +115,7 @@ ENTRY(cpu_v7_set_pte_ext) orr r3, r3, r2 orr r3, r3, #PTE_EXT_AP0 | 2 - tst r2, #1 << 4 + tst r1, #1 << 4 orrne r3, r3, #PTE_EXT_TEX(1) tst r1, #L_PTE_WRITE @@ -192,11 +192,11 @@ __v7_setup: mov pc, lr @ return to head.S:__ret ENDPROC(__v7_setup) - /* - * V X F I D LR - * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM - * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced - * 0 110 0011 1.00 .111 1101 < we want + /* AT + * TFR EV X F I D LR + * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM + * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced + * 1 0 110 0011 1.00 .111 1101 < we want */ .type v7_crval, #object v7_crval: diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 04dc8b65401b..8f6cf56c11c0 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -349,7 +349,7 @@ ENTRY(cpu_xsc3_switch_mm) cpu_xsc3_mt_table: .long 0x00 @ L_PTE_MT_UNCACHED .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE - .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH + .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED .long 0x00 @ unused diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c index 4689db638e95..9e573e78176a 100644 --- a/arch/arm/plat-iop/setup.c +++ b/arch/arm/plat-iop/setup.c @@ -16,14 +16,15 @@ #include /* - * Standard IO mapping for all IOP3xx based systems + * Standard IO mapping for all IOP3xx based systems. Note that + * the IOP3xx OCCDR must be mapped uncached and unbuffered. */ static struct map_desc iop3xx_std_desc[] __initdata = { { /* mem mapped registers */ .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), .length = IOP3XX_PERIPHERAL_SIZE, - .type = MT_DEVICE, + .type = MT_UNCACHED, }, { /* PCI IO space */ .virtual = IOP3XX_PCI_LOWER_IO_VA, .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 733e0acac916..de5c4747453f 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -188,7 +188,7 @@ static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) struct mxc_gpio_port *port = container_of(chip, struct mxc_gpio_port, chip); - return (__raw_readl(port->base + GPIO_DR) >> offset) & 1; + return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1; } static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index 65b6810124c1..5d4cb1196441 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -14,6 +14,26 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff +#ifdef CONFIG_ARCH_MX3 +#define __arch_ioremap __mx3_ioremap +#define __arch_iounmap __iounmap + +static inline void __iomem * +__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +{ + if (mtype == MT_DEVICE) { + /* Access all peripherals below 0x80000000 as nonshared device + * but leave l2cc alone. + */ + if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) || + (phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE))) + mtype = MT_DEVICE_NONSHARED; + } + + return __arm_ioremap(phys_addr, size, mtype); +} +#endif + /* io address mapping macro */ #define __io(a) ((void __iomem *)(a)) diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index bf6a10c5fc4f..be6aab9c6834 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -428,23 +428,23 @@ static int clk_debugfs_register_one(struct clk *c) if (c->id != 0) sprintf(p, ":%d", c->id); d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); - if (IS_ERR(d)) - return PTR_ERR(d); + if (!d) + return -ENOMEM; c->dent = d; d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount); - if (IS_ERR(d)) { - err = PTR_ERR(d); + if (!d) { + err = -ENOMEM; goto err_out; } d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); - if (IS_ERR(d)) { - err = PTR_ERR(d); + if (!d) { + err = -ENOMEM; goto err_out; } d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); - if (IS_ERR(d)) { - err = PTR_ERR(d); + if (!d) { + err = -ENOMEM; goto err_out; } return 0; @@ -483,8 +483,8 @@ static int __init clk_debugfs_init(void) int err; d = debugfs_create_dir("clock", NULL); - if (IS_ERR(d)) - return PTR_ERR(d); + if (!d) + return -ENOMEM; clk_debugfs_root = d; list_for_each_entry(c, &clocks, node) { diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 8679fbca6bbe..424049d83fbe 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -101,6 +101,7 @@ #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 #define OMAP24XX_GPIO_IRQENABLE2 0x002c #define OMAP24XX_GPIO_IRQENABLE1 0x001c +#define OMAP24XX_GPIO_WAKE_EN 0x0020 #define OMAP24XX_GPIO_CTRL 0x0030 #define OMAP24XX_GPIO_OE 0x0034 #define OMAP24XX_GPIO_DATAIN 0x0038 @@ -1551,7 +1552,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) #endif #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) case METHOD_GPIO_24XX: - wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; + wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; break; @@ -1574,7 +1575,7 @@ static int omap_gpio_resume(struct sys_device *dev) { int i; - if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) + if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) return 0; for (i = 0; i < gpio_bank_count; i++) { diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S index 030118ee204a..2276f89671d8 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/plat-omap/include/mach/entry-macro.S @@ -65,7 +65,8 @@ #include #endif -#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */ +#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ +#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ .macro disable_fiq .endm @@ -88,6 +89,7 @@ cmp \irqnr, #0x0 2222: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] + and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ .endm diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index a2929ac8c687..bed5274c910a 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h @@ -372,7 +372,7 @@ /* External TWL4030 gpio interrupts are optional */ #define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END -#ifdef CONFIG_TWL4030_GPIO +#ifdef CONFIG_GPIO_TWL4030 #define TWL4030_GPIO_NR_IRQS 18 #else #define TWL4030_GPIO_NR_IRQS 0 diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h index ec67fb428607..7b74d1255e0b 100644 --- a/arch/arm/plat-omap/include/mach/omapfb.h +++ b/arch/arm/plat-omap/include/mach/omapfb.h @@ -353,8 +353,8 @@ struct omapfb_device { u32 pseudo_palette[17]; struct lcd_panel *panel; /* LCD panel */ - struct lcd_ctrl *ctrl; /* LCD controller */ - struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ + const struct lcd_ctrl *ctrl; /* LCD controller */ + const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ struct lcd_ctrl_extif *ext_if; /* LCD ctrl external interface */ struct device *dev; diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h index 768eb6e7abcf..2a9c27ad4c37 100644 --- a/arch/arm/plat-omap/include/mach/pm.h +++ b/arch/arm/plat-omap/include/mach/pm.h @@ -128,7 +128,7 @@ void clk_deny_idle(struct clk *clk); * clk_allow_idle - Counters previous clk_deny_idle * @clk: clock signal handle */ -void clk_deny_idle(struct clk *clk); +void clk_allow_idle(struct clk *clk); extern void omap_pm_idle(void); extern void omap_pm_suspend(void); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 9f9a921829c0..dcd9d16da2e9 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -255,7 +255,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) if (!_omap_sram_reprogram_clock) omap_sram_error(); - return _omap_sram_reprogram_clock(dpllctl, ckctl); + _omap_sram_reprogram_clock(dpllctl, ckctl); } int __init omap1_sram_init(void) @@ -282,8 +282,8 @@ void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, if (!_omap2_sram_ddr_init) omap_sram_error(); - return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, - base_cs, force_unlock); + _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, + base_cs, force_unlock); } static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, @@ -294,7 +294,7 @@ void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) if (!_omap2_sram_reprogram_sdrc) omap_sram_error(); - return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); + _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); } static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index 883902fead89..d41d41d78ad9 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -35,7 +35,7 @@ #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 #define PCIE_CTRL_OFF 0x1a00 diff --git a/arch/avr32/boards/favr-32/flash.c b/arch/avr32/boards/favr-32/flash.c index 5f139b7cb5f7..604bbd5e41d9 100644 --- a/arch/avr32/boards/favr-32/flash.c +++ b/arch/avr32/boards/favr-32/flash.c @@ -13,7 +13,7 @@ #include #include -#include +#include static struct smc_timing flash_timing __initdata = { .ncs_read_setup = 0, diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c index 7538f3d2b9e0..1ee4faf0742d 100644 --- a/arch/avr32/boards/favr-32/setup.c +++ b/arch/avr32/boards/favr-32/setup.c @@ -25,10 +25,10 @@ #include -#include -#include -#include -#include +#include +#include +#include +#include /* Oscillator frequencies. These are board-specific */ unsigned long at32_board_osc_rates[3] = { diff --git a/arch/avr32/boot/images/Makefile b/arch/avr32/boot/images/Makefile index 219720a47bf9..1848bf0d7f62 100644 --- a/arch/avr32/boot/images/Makefile +++ b/arch/avr32/boot/images/Makefile @@ -10,7 +10,7 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh extra-y := vmlinux.bin vmlinux.gz -OBJCOPYFLAGS_vmlinux.bin := -O binary +OBJCOPYFLAGS_vmlinux.bin := -O binary -R .note.gnu.build-id $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig index 8b6e54c9946a..6c45a3b77aa3 100644 --- a/arch/avr32/configs/atstk1006_defconfig +++ b/arch/avr32/configs/atstk1006_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 15:40:26 2008 +# Linux kernel version: 2.6.28-rc8 +# Thu Dec 18 11:22:23 2008 # CONFIG_AVR32=y CONFIG_GENERIC_GPIO=y @@ -67,6 +67,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -77,15 +78,8 @@ CONFIG_PROFILING=y CONFIG_OPROFILE=m CONFIG_HAVE_OPROFILE=y CONFIG_KPROBES=y -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -118,6 +112,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # System Type and features @@ -134,6 +129,8 @@ CONFIG_CPU_AT32AP700X=y CONFIG_CPU_AT32AP7000=y CONFIG_BOARD_ATSTK1000=y # CONFIG_BOARD_ATNGW100 is not set +# CONFIG_BOARD_FAVR_32 is not set +# CONFIG_BOARD_MIMC200 is not set # CONFIG_BOARD_ATSTK1002 is not set # CONFIG_BOARD_ATSTK1003 is not set # CONFIG_BOARD_ATSTK1004 is not set @@ -171,14 +168,14 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_NR_QUICK=2 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # CONFIG_OWNERSHIP_TRACE is not set CONFIG_NMI_DEBUGGING=y # CONFIG_HZ_100 is not set @@ -186,7 +183,7 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y CONFIG_CMDLINE="" # @@ -228,6 +225,8 @@ CONFIG_CPU_FREQ_AT32AP=y # Executable file formats # CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_NET=y @@ -299,6 +298,7 @@ CONFIG_IPV6_TUNNEL=m # CONFIG_ATM is not set CONFIG_STP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -321,14 +321,8 @@ CONFIG_LLC=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -359,6 +353,7 @@ CONFIG_MTD_CMDLINE_PARTS=y # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_HAVE_MTD_OTP=y CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set @@ -407,6 +402,8 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # Self-contained MTD device drivers # CONFIG_MTD_DATAFLASH=m +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_DATAFLASH_OTP=y CONFIG_MTD_M25P80=m CONFIG_M25PXX_USE_FAST_READ=y # CONFIG_MTD_SLRAM is not set @@ -464,9 +461,10 @@ CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_TCB_CLKSRC=y CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0 # CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set CONFIG_ATMEL_SSC=m # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HAVE_IDE is not set +# CONFIG_C2PORT is not set # # SCSI device support @@ -548,6 +546,9 @@ CONFIG_MACB=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -653,6 +654,7 @@ CONFIG_UNIX98_PTYS=y CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=m # @@ -716,6 +718,10 @@ CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y +# +# Memory mapped GPIO expanders: +# + # # I2C GPIO expanders: # @@ -745,11 +751,11 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_AT32AP700X_WDT=y +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -758,6 +764,10 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -783,6 +793,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -804,10 +815,13 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_S1D13XXX is not set CONFIG_FB_ATMEL=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_LTV350QV=y # CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set # CONFIG_LCD_VGG2432A4 is not set # CONFIG_LCD_PLATFORM is not set # CONFIG_BACKLIGHT_CLASS_DEVICE is not set @@ -818,6 +832,7 @@ CONFIG_LCD_LTV350QV=y # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_LOGO is not set CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -848,28 +863,32 @@ CONFIG_USB_SUPPORT=y # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_USB_ATMEL_USBA=y # CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set # CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_ZERO=m @@ -887,7 +906,7 @@ CONFIG_MMC=y # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y @@ -895,10 +914,11 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set CONFIG_MMC_ATMELMCI=y +# CONFIG_MMC_ATMELMCI_DMA is not set CONFIG_MMC_SPI=m # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -918,6 +938,7 @@ CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y @@ -950,25 +971,31 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers # # CONFIG_RTC_DRV_M41T94 is not set # CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -989,6 +1016,8 @@ CONFIG_DMA_ENGINE=y # CONFIG_NET_DMA is not set CONFIG_DMATEST=m # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -998,12 +1027,17 @@ CONFIG_EXT2_FS=m # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=m # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=m +CONFIG_EXT4DEV_COMPAT=y +# CONFIG_EXT4_FS_XATTR is not set CONFIG_JBD=m # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -1036,6 +1070,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1054,7 +1089,8 @@ CONFIG_TMPFS=y # CONFIG_EFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_WRITEBUFFER is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set @@ -1088,6 +1124,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1185,10 +1222,21 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -1196,17 +1244,26 @@ CONFIG_FRAME_POINTER=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -1257,7 +1314,7 @@ CONFIG_CRYPTO_SHA1=m # # Ciphers # -# CONFIG_CRYPTO_AES is not set +CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set @@ -1278,14 +1335,17 @@ CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=m diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index 0c6e02f80a31..066252eebf61 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c @@ -967,28 +967,28 @@ static inline void configure_usart0_pins(void) { u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */ - select_peripheral(PIOA, pin_mask, PERIPH_B, 0); + select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); } static inline void configure_usart1_pins(void) { u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */ - select_peripheral(PIOA, pin_mask, PERIPH_A, 0); + select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP); } static inline void configure_usart2_pins(void) { u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */ - select_peripheral(PIOB, pin_mask, PERIPH_B, 0); + select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); } static inline void configure_usart3_pins(void) { u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */ - select_peripheral(PIOB, pin_mask, PERIPH_B, 0); + select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); } static struct platform_device *__initdata at32_usarts[4]; diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 56dcb0a2d244..77295666c34b 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h @@ -101,7 +101,7 @@ extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ extern unsigned long _ramstart, _ramend, _rambase; extern unsigned long memory_start, memory_end, physical_mem_end; extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], - _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[], + _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], _ebss_l2[], _l2_lma_start[]; diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h index ede748d67efd..d7d9148e433c 100644 --- a/arch/blackfin/include/asm/dma-mapping.h +++ b/arch/blackfin/include/asm/dma-mapping.h @@ -15,7 +15,11 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) -#define dma_mapping_error +static inline +int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return 0; +} /* * Map a single buffer of the indicated size for DMA in streaming mode. diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 6e08f425bb44..5c0800adb4dd 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -218,7 +218,7 @@ inline int check_gpio(unsigned gpio) if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 || gpio == GPIO_PH14 || gpio == GPIO_PH15 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 - || gpio > MAX_BLACKFIN_GPIOS) + || gpio >= MAX_BLACKFIN_GPIOS) return -EINVAL; return 0; } diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 512f8c92ead5..2debc900e246 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -188,10 +188,11 @@ static struct cplb_desc cplb_data[] = { static u16 __init lock_kernel_check(u32 start, u32 end) { - if ((end <= (u32) _end && end >= (u32)_stext) || - (start <= (u32) _end && start >= (u32)_stext)) - return IN_KERNEL; - return 0; + if (start >= (u32)_end || end <= (u32)_stext) + return 0; + + /* This cplb block overlapped with kernel area. */ + return IN_KERNEL; } static unsigned short __init diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 77800dd83e57..0c3ea118b657 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -351,9 +351,14 @@ int _access_ok(unsigned long addr, unsigned long size) return 1; #endif #if L1_DATA_B_LENGTH != 0 - if (addr >= L1_DATA_B_START + if (addr >= L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1) && addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH) return 1; +#endif +#if L2_LENGTH != 0 + if (addr >= L2_START + (_ebss_l2 - _stext_l2) + && addr + size <= L2_START + L2_LENGTH) + return 1; #endif return 0; } diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 7f35d1046cd8..71a9a8c53cea 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -119,23 +119,23 @@ void __init bfin_relocate_l1_mem(void) /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); - l1_data_a_length = _ebss_l1 - _sdata_l1; + l1_data_a_length = _sbss_l1 - _sdata_l1; if (l1_data_a_length > L1_DATA_A_LENGTH) panic("L1 Data SRAM Bank A Overflow\n"); - /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */ + /* Copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); - l1_data_b_length = _ebss_b_l1 - _sdata_b_l1; + l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; if (l1_data_b_length > L1_DATA_B_LENGTH) panic("L1 Data SRAM Bank B Overflow\n"); - /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */ + /* Copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + l1_data_a_length, l1_data_b_length); if (L2_LENGTH != 0) { - l2_length = _ebss_l2 - _stext_l2; + l2_length = _sbss_l2 - _stext_l2; if (l2_length > L2_LENGTH) panic("L2 SRAM Overflow\n"); @@ -827,7 +827,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", bfin_compiled_revid(), bfin_revid()); } - if (bfin_revid() <= CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) + if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", CPU, bfin_revid()); } diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 1aa2c788e228..bef025b07443 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -59,7 +59,7 @@ #endif -#ifdef CONFIG_VERBOSE_DEBUG +#ifdef CONFIG_DEBUG_VERBOSE #define verbose_printk(fmt, arg...) \ printk(fmt, ##arg) #else @@ -147,9 +147,12 @@ static void decode_address(char *buf, unsigned long address) char *name = p->comm; struct file *file = vma->vm_file; - if (file) - name = d_path(&file->f_path, _tmpbuf, + if (file) { + char *d_name = d_path(&file->f_path, _tmpbuf, sizeof(_tmpbuf)); + if (!IS_ERR(d_name)) + name = d_name; + } /* FLAT does not have its text aligned to the start of * the map while FDPIC ELF does ... @@ -571,7 +574,7 @@ asmlinkage void trap_c(struct pt_regs *fp) #endif panic("Kernel exception"); } else { -#ifdef CONFIG_VERBOSE_DEBUG +#ifdef CONFIG_DEBUG_VERBOSE unsigned long *stack; /* Dump the user space stack */ stack = (unsigned long *)rdusp(); diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index db532181fbde..a028e9450419 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -25,9 +25,13 @@ */ .macro do_flush flushins:req optflushins optnopins label + R2 = -L1_CACHE_BYTES; + + /* start = (start & -L1_CACHE_BYTES) */ + R0 = R0 & R2; + /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ R1 += -1; - R2 = -L1_CACHE_BYTES; R1 = R1 & R2; R1 += L1_CACHE_BYTES; @@ -63,7 +67,7 @@ ENDPROC(_blackfin_icache_flush_range) /* Flush all cache lines assocoiated with this area of memory. */ ENTRY(_blackfin_icache_dcache_flush_range) - do_flush IFLUSH, FLUSH + do_flush FLUSH, IFLUSH ENDPROC(_blackfin_icache_dcache_flush_range) /* Throw away all D-cached data in specified region without any obligation to diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index c22c47b60127..dda5443b37ed 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -72,13 +72,13 @@ unsigned int __bfin_cycles_mod; /**************************************************************************/ -static unsigned int bfin_getfreq(unsigned int cpu) +static unsigned int bfin_getfreq_khz(unsigned int cpu) { /* The driver only support single cpu */ if (cpu != 0) return -1; - return get_cclk(); + return get_cclk() / 1000; } @@ -96,7 +96,7 @@ static int bfin_target(struct cpufreq_policy *policy, cclk_hz = bfin_freq_table[index].frequency; - freqs.old = bfin_getfreq(0); + freqs.old = bfin_getfreq_khz(0); freqs.new = cclk_hz; freqs.cpu = 0; @@ -137,8 +137,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) if (policy->cpu != 0) return -EINVAL; - cclk = get_cclk(); - sclk = get_sclk(); + cclk = get_cclk() / 1000; + sclk = get_sclk() / 1000; #if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) min_cclk = sclk * 2; @@ -152,7 +152,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; - pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n", + pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", bfin_freq_table[index].frequency, dpm_state_table[index].csel, dpm_state_table[index].tscale); @@ -173,7 +173,7 @@ static struct freq_attr *bfin_freq_attr[] = { static struct cpufreq_driver bfin_driver = { .verify = bfin_verify_speed, .target = bfin_target, - .get = bfin_getfreq, + .get = bfin_getfreq_khz, .init = __bfin_cpu_init, .name = "bfin cpufreq", .owner = THIS_MODULE, diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index c13fa8da28c7..bde6dc4e2614 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -277,7 +277,7 @@ ENTRY(_bfin_return_from_exception) p5.h = hi(ILAT); r6 = [p5]; r7 = 0x20; /* Did I just cause anther HW error? */ - r7 = r7 & r1; + r6 = r7 & r6; CC = R7 == R6; if CC JUMP _double_fault; #endif diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 0f1ca6930c16..cc6f336e7313 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c @@ -183,10 +183,10 @@ static void __init l2_sram_init(void) return; } - free_l2_sram_head.next->paddr = (void *)L2_START + - (_etext_l2 - _stext_l2) + (_edata_l2 - _sdata_l2); - free_l2_sram_head.next->size = L2_LENGTH - - (_etext_l2 - _stext_l2) + (_edata_l2 - _sdata_l2); + free_l2_sram_head.next->paddr = + (void *)L2_START + (_ebss_l2 - _stext_l2); + free_l2_sram_head.next->size = + L2_LENGTH - (_ebss_l2 - _stext_l2); free_l2_sram_head.next->pid = 0; free_l2_sram_head.next->next = NULL; diff --git a/arch/cris/Makefile b/arch/cris/Makefile index c6f5f5a2ffdf..3662cfb7b61d 100644 --- a/arch/cris/Makefile +++ b/arch/cris/Makefile @@ -23,12 +23,17 @@ mach-$(CONFIG_ETRAXFS) := fs ifneq ($(arch-y),) SARCH := arch-$(arch-y) +inc := -Iarch/cris/include/$(SARCH) +inc += -Iarch/cris/include/$(SARCH)/arch else SARCH := +inc := endif ifneq ($(mach-y),) MACH := mach-$(mach-y) +inc += -Iarch/cris/include/$(SARCH)/$(MACH)/ +inc += -Iarch/cris/include/$(SARCH)/$(MACH)/mach else MACH := endif @@ -39,95 +44,57 @@ OBJCOPYFLAGS := -O binary -R .note -R .comment -S CPPFLAGS_vmlinux.lds = -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE) -KBUILD_AFLAGS += -mlinux -march=$(arch-y) -Iinclude/asm/arch/mach -Iinclude/asm/arch - -KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -Iinclude/asm/arch/mach -Iinclude/asm/arch +KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) +KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) +KBUILD_CPPFLAGS += $(inc) ifdef CONFIG_FRAME_POINTER KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g KBUILD_CFLAGS += -fno-omit-frame-pointer endif -head-y := arch/$(ARCH)/$(SARCH)/kernel/head.o +head-y := arch/cris/$(SARCH)/kernel/head.o LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libgcc.a) -core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ -core-y += arch/$(ARCH)/$(SARCH)/kernel/ arch/$(ARCH)/$(SARCH)/mm/ +core-y += arch/cris/kernel/ arch/cris/mm/ +core-y += arch/cris/$(SARCH)/kernel/ arch/cris/$(SARCH)/mm/ ifdef CONFIG_ETRAX_ARCH_V32 -core-y += arch/$(ARCH)/$(SARCH)/$(MACH)/ +core-y += arch/cris/$(SARCH)/$(MACH)/ endif -drivers-y += arch/$(ARCH)/$(SARCH)/drivers/ -libs-y += arch/$(ARCH)/$(SARCH)/lib/ $(LIBGCC) +drivers-y += arch/cris/$(SARCH)/drivers/ +libs-y += arch/cris/$(SARCH)/lib/ $(LIBGCC) # cris source path -SRC_ARCH = $(srctree)/arch/$(ARCH) +SRC_ARCH = $(srctree)/arch/cris # cris object files path -OBJ_ARCH = $(objtree)/arch/$(ARCH) +OBJ_ARCH = $(objtree)/arch/cris -boot := arch/$(ARCH)/boot -MACHINE := arch/$(ARCH)/$(SARCH) +boot := arch/cris/$(SARCH)/boot +MACHINE := arch/cris/$(SARCH) all: zImage zImage Image: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ -archprepare: $(SRC_ARCH)/.links $(srctree)/include/asm-$(ARCH)/.arch FORCE - -# Create some links to make all tools happy -$(SRC_ARCH)/.links: - @rm -rf $(SRC_ARCH)/drivers - @ln -sfn $(SARCH)/drivers $(SRC_ARCH)/drivers - @rm -rf $(SRC_ARCH)/boot - @ln -sfn $(SARCH)/boot $(SRC_ARCH)/boot - @rm -rf $(SRC_ARCH)/lib - @ln -sfn $(SARCH)/lib $(SRC_ARCH)/lib - @rm -f $(SRC_ARCH)/arch/mach - @rm -rf $(SRC_ARCH)/arch - @ln -sfn $(SARCH) $(SRC_ARCH)/arch -ifdef CONFIG_ETRAX_ARCH_V32 - @ln -sfn ../$(SARCH)/$(MACH) $(SRC_ARCH)/arch/mach -endif - @rm -rf $(SRC_ARCH)/kernel/vmlinux.lds.S - @ln -sfn ../$(SARCH)/vmlinux.lds.S $(SRC_ARCH)/kernel/vmlinux.lds.S - @rm -rf $(SRC_ARCH)/kernel/asm-offsets.c - @ln -sfn ../$(SARCH)/kernel/asm-offsets.c $(SRC_ARCH)/kernel/asm-offsets.c - @touch $@ - -# Create link to sub arch includes -$(srctree)/include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h) - @echo ' SYMLINK include/asm-$(ARCH)/arch -> include/asm-$(ARCH)/$(SARCH)' - @rm -f $(srctree)/include/asm-$(ARCH)/arch/mach - @rm -f $(srctree)/include/asm-$(ARCH)/arch - @ln -sf $(SARCH) $(srctree)/include/asm-$(ARCH)/arch -ifdef CONFIG_ETRAX_ARCH_V32 - @ln -sf $(MACH) $(srctree)/include/asm-$(ARCH)/arch/mach -endif - @touch $@ +archprepare: archclean: - $(Q)if [ -e arch/$(ARCH)/boot ]; then \ - $(MAKE) $(clean)=arch/$(ARCH)/boot; \ + $(Q)if [ -e arch/cris/$(SARCH)/boot ]; then \ + $(MAKE) $(clean)=arch/cris/$(SARCH)/boot; \ fi CLEAN_FILES += \ $(MACHINE)/boot/zImage \ $(MACHINE)/boot/compressed/decompress.bin \ $(MACHINE)/boot/compressed/piggy.gz \ - $(MACHINE)/boot/rescue/rescue.bin \ - $(SRC_ARCH)/.links \ - $(srctree)/include/asm-$(ARCH)/.arch - -MRPROPER_FILES += \ - $(SRC_ARCH)/drivers \ - $(SRC_ARCH)/boot \ - $(SRC_ARCH)/lib \ - $(SRC_ARCH)/arch \ - $(SRC_ARCH)/kernel/vmlinux.lds.S \ - $(SRC_ARCH)/kernel/asm-offsets.c + $(MACHINE)/boot/rescue/rescue.bin + + +# MRPROPER_FILES += define archhelp - echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' - echo '* Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)' + echo '* zImage - Compressed kernel image (arch/cris/boot/zImage)' + echo '* Image - Uncompressed kernel image (arch/cris/boot/Image)' endef diff --git a/arch/cris/arch-v10/boot/.gitignore b/arch/cris/arch-v10/boot/.gitignore new file mode 100644 index 000000000000..171a0853caf8 --- /dev/null +++ b/arch/cris/arch-v10/boot/.gitignore @@ -0,0 +1,2 @@ +Image +zImage diff --git a/arch/cris/arch-v10/boot/compressed/head.S b/arch/cris/arch-v10/boot/compressed/head.S index 981fbae84959..0bb4dcc29254 100644 --- a/arch/cris/arch-v10/boot/compressed/head.S +++ b/arch/cris/arch-v10/boot/compressed/head.S @@ -9,7 +9,7 @@ */ #define ASSEMBLER_MACROS_ONLY -#include +#include #define RAM_INIT_MAGIC 0x56902387 #define COMMAND_LINE_MAGIC 0x87109563 diff --git a/arch/cris/arch-v10/boot/compressed/misc.c b/arch/cris/arch-v10/boot/compressed/misc.c index d933c89889db..a4db1507d3b1 100644 --- a/arch/cris/arch-v10/boot/compressed/misc.c +++ b/arch/cris/arch-v10/boot/compressed/misc.c @@ -20,7 +20,7 @@ #include -#include +#include /* * gzip declarations diff --git a/arch/cris/arch-v10/boot/rescue/head.S b/arch/cris/arch-v10/boot/rescue/head.S index 6ba7be8ac4a0..fb503d1eeea4 100644 --- a/arch/cris/arch-v10/boot/rescue/head.S +++ b/arch/cris/arch-v10/boot/rescue/head.S @@ -65,7 +65,7 @@ #ifdef CONFIG_ETRAX_AXISFLASHMAP #define ASSEMBLER_MACROS_ONLY -#include +#include ;; The partitiontable is looked for at the first sector after the boot ;; sector. Sector size is 65536 bytes in all flashes we use. diff --git a/arch/cris/arch-v10/boot/rescue/kimagerescue.S b/arch/cris/arch-v10/boot/rescue/kimagerescue.S index 55eeff8bb08e..6f7b3e61260b 100644 --- a/arch/cris/arch-v10/boot/rescue/kimagerescue.S +++ b/arch/cris/arch-v10/boot/rescue/kimagerescue.S @@ -6,7 +6,7 @@ */ #define ASSEMBLER_MACROS_ONLY -#include +#include #define CODE_START 0x40004000 #define CODE_LENGTH 784 diff --git a/arch/cris/arch-v10/boot/rescue/testrescue.S b/arch/cris/arch-v10/boot/rescue/testrescue.S index 2d937f9afe23..fc7ec674eca5 100644 --- a/arch/cris/arch-v10/boot/rescue/testrescue.S +++ b/arch/cris/arch-v10/boot/rescue/testrescue.S @@ -6,7 +6,7 @@ */ #define ASSEMBLER_MACROS_ONLY -#include +#include .text diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c index b3bdda93ffef..b2079703af7e 100644 --- a/arch/cris/arch-v10/drivers/axisflashmap.c +++ b/arch/cris/arch-v10/drivers/axisflashmap.c @@ -26,7 +26,7 @@ #include #include -#include +#include #ifdef CONFIG_CRIS_LOW_MAP #define FLASH_UNCACHED_ADDR KSEG_8 diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c index 3bdfaf43390c..77630df94343 100644 --- a/arch/cris/arch-v10/drivers/ds1302.c +++ b/arch/cris/arch-v10/drivers/ds1302.c @@ -24,10 +24,10 @@ #include #include -#include +#include #include #include -#include +#include #include "i2c.h" diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c index 86048e697eb5..4b0f65fac8e8 100644 --- a/arch/cris/arch-v10/drivers/gpio.c +++ b/arch/cris/arch-v10/drivers/gpio.c @@ -23,11 +23,11 @@ #include #include -#include +#include #include #include #include -#include +#include #define GPIO_MAJOR 120 /* experimental MAJOR number */ diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c index 2797e67ce4f4..7f656ae0b21d 100644 --- a/arch/cris/arch-v10/drivers/i2c.c +++ b/arch/cris/arch-v10/drivers/i2c.c @@ -25,10 +25,10 @@ #include #include -#include +#include #include #include -#include +#include #include "i2c.h" diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c index 91fea623c7c9..6cc1a0319a5d 100644 --- a/arch/cris/arch-v10/drivers/sync_serial.c +++ b/arch/cris/arch-v10/drivers/sync_serial.c @@ -26,11 +26,11 @@ #include #include #include -#include +#include #include #include #include -#include +#include /* The receiver is a bit tricky beacuse of the continuous stream of data.*/ /* */ diff --git a/arch/cris/arch-v10/kernel/asm-offsets.c b/arch/cris/arch-v10/kernel/asm-offsets.c deleted file mode 100644 index 1aa3cc4e7107..000000000000 --- a/arch/cris/arch-v10/kernel/asm-offsets.c +++ /dev/null @@ -1,47 +0,0 @@ -#include -#include - -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - */ - -#define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) - -#define BLANK() asm volatile("\n->" : : ) - -int main(void) -{ -#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry)) - ENTRY(orig_r10); - ENTRY(r13); - ENTRY(r12); - ENTRY(r11); - ENTRY(r10); - ENTRY(r9); - ENTRY(mof); - ENTRY(dccr); - ENTRY(srp); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) - ENTRY(task); - ENTRY(flags); - ENTRY(preempt_count); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry)) - ENTRY(ksp); - ENTRY(usp); - ENTRY(dccr); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry)) - ENTRY(pid); - BLANK(); - DEFINE(LCLONE_VM, CLONE_VM); - DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED); - return 0; -} diff --git a/arch/cris/arch-v10/kernel/crisksyms.c b/arch/cris/arch-v10/kernel/crisksyms.c index e6b80135502f..1ca6fc283232 100644 --- a/arch/cris/arch-v10/kernel/crisksyms.c +++ b/arch/cris/arch-v10/kernel/crisksyms.c @@ -1,6 +1,6 @@ #include #include -#include +#include /* Export shadow registers for the CPU I/O pins */ EXPORT_SYMBOL(genconfig_shadow); diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c index 3dc6e91ba39e..99851ba8e5fa 100644 --- a/arch/cris/arch-v10/kernel/debugport.c +++ b/arch/cris/arch-v10/kernel/debugport.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include /* Get SIMCOUT. */ extern void reset_watchdog(void); diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c index eb1fa0d2b49f..929e68666299 100644 --- a/arch/cris/arch-v10/kernel/dma.c +++ b/arch/cris/arch-v10/kernel/dma.c @@ -7,7 +7,7 @@ #include #include -#include +#include /* Macro to access ETRAX 100 registers */ #define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S index 3a65f322ae07..ed171d389e65 100644 --- a/arch/cris/arch-v10/kernel/entry.S +++ b/arch/cris/arch-v10/kernel/entry.S @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/cris/arch-v10/kernel/fasttimer.c b/arch/cris/arch-v10/kernel/fasttimer.c index 31ff35cff02c..5ff08a8695e9 100644 --- a/arch/cris/arch-v10/kernel/fasttimer.c +++ b/arch/cris/arch-v10/kernel/fasttimer.c @@ -24,7 +24,7 @@ #include -#include +#include #include #include diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S index 96344afc4ebc..fc4577102933 100644 --- a/arch/cris/arch-v10/kernel/head.S +++ b/arch/cris/arch-v10/kernel/head.S @@ -10,7 +10,7 @@ #define ASSEMBLER_MACROS_ONLY /* The IO_* macros use the ## token concatenation operator, so -traditional must not be used when assembling this file. */ -#include +#include #define CRAMFS_MAGIC 0x28cd3d45 #define RAM_INIT_MAGIC 0x56902387 diff --git a/arch/cris/arch-v10/kernel/io_interface_mux.c b/arch/cris/arch-v10/kernel/io_interface_mux.c index add98e0941b5..29f97e962795 100644 --- a/arch/cris/arch-v10/kernel/io_interface_mux.c +++ b/arch/cris/arch-v10/kernel/io_interface_mux.c @@ -11,9 +11,9 @@ #include #include -#include +#include #include -#include +#include #define DBG(s) diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c index 6fea45f2e40c..b9f9c8ce2169 100644 --- a/arch/cris/arch-v10/kernel/kgdb.c +++ b/arch/cris/arch-v10/kernel/kgdb.c @@ -176,7 +176,7 @@ #include #include -#include +#include #include static int kgdb_started = 0; diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c index 53117f07cc1a..bd9b3ff63f6c 100644 --- a/arch/cris/arch-v10/kernel/process.c +++ b/arch/cris/arch-v10/kernel/process.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #ifdef CONFIG_ETRAX_GPIO diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c index 525483f0ddf8..c685ba4c3387 100644 --- a/arch/cris/arch-v10/kernel/time.c +++ b/arch/cris/arch-v10/kernel/time.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/cris/arch-v10/kernel/traps.c b/arch/cris/arch-v10/kernel/traps.c index 9eada5d8893b..8bebb96bbca1 100644 --- a/arch/cris/arch-v10/kernel/traps.c +++ b/arch/cris/arch-v10/kernel/traps.c @@ -10,7 +10,7 @@ #include #include -#include +#include void show_registers(struct pt_regs *regs) diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c index 65504fd80928..087a2096f221 100644 --- a/arch/cris/arch-v10/mm/fault.c +++ b/arch/cris/arch-v10/mm/fault.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include /* debug of low-level TLB reload */ diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c index 742fd1974c2e..baa746ce4e74 100644 --- a/arch/cris/arch-v10/mm/init.c +++ b/arch/cris/arch-v10/mm/init.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include extern void tlb_init(void); diff --git a/arch/cris/arch-v10/mm/tlb.c b/arch/cris/arch-v10/mm/tlb.c index 6baf5bd209e7..4a496e4ffacc 100644 --- a/arch/cris/arch-v10/mm/tlb.c +++ b/arch/cris/arch-v10/mm/tlb.c @@ -12,7 +12,7 @@ #include #include -#include +#include #define D(x) diff --git a/arch/cris/arch-v10/vmlinux.lds.S b/arch/cris/arch-v10/vmlinux.lds.S deleted file mode 100644 index 93c9f0ea286b..000000000000 --- a/arch/cris/arch-v10/vmlinux.lds.S +++ /dev/null @@ -1,118 +0,0 @@ -/* ld script to make the Linux/CRIS kernel - * Authors: Bjorn Wesen (bjornw@axis.com) - * - * It is VERY DANGEROUS to fiddle around with the symbols in this - * script. It is for example quite vital that all generated sections - * that are used are actually named here, otherwise the linker will - * put them at the end, where the init stuff is which is FREED after - * the kernel has booted. - */ - -#include -#include - -jiffies = jiffies_64; -SECTIONS -{ - . = DRAM_VIRTUAL_BASE; - dram_start = .; - ibr_start = .; - . = . + 0x4000; /* see head.S and pages reserved at the start */ - - _text = .; /* Text and read-only data */ - text_start = .; /* lots of aliases */ - _stext = .; - __stext = .; - .text : { - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT - *(.fixup) - *(.text.__*) - } - - _etext = . ; /* End of text section */ - __etext = .; - - . = ALIGN(4); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - RODATA - - . = ALIGN (4); - ___data_start = . ; - __Sdata = . ; - .data : { /* Data */ - DATA_DATA - } - __edata = . ; /* End of data section */ - _edata = . ; - - . = ALIGN(PAGE_SIZE); /* init_task and stack, must be aligned */ - .data.init_task : { *(.data.init_task) } - - . = ALIGN(PAGE_SIZE); /* Init code and data */ - __init_begin = .; - .init.text : { - _sinittext = .; - INIT_TEXT - _einittext = .; - } - .init.data : { INIT_DATA } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - .initcall.init : { - __initcall_start = .; - INITCALLS - __initcall_end = .; - } - - .con_initcall.init : { - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - } - SECURITY_INIT - -#ifdef CONFIG_BLK_DEV_INITRD - .init.ramfs : { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } -#endif - __vmlinux_end = .; /* last address of the physical file */ - - /* - * We fill to the next page, so we can discard all init - * pages without needing to consider what payload might be - * appended to the kernel image. - */ - . = ALIGN(PAGE_SIZE); - - __init_end = .; - - __data_end = . ; /* Move to _edata ? */ - __bss_start = .; /* BSS */ - .bss : { - *(COMMON) - *(.bss) - } - - . = ALIGN (0x20); - _end = .; - __end = .; - - /* Sections to be discarded */ - /DISCARD/ : { - EXIT_TEXT - EXIT_DATA - *(.exitcall.exit) - } - - dram_end = dram_start + CONFIG_ETRAX_DRAM_SIZE*1024*1024; -} diff --git a/arch/cris/arch-v32/boot/compressed/head.S b/arch/cris/arch-v32/boot/compressed/head.S index f86208caf32d..a4a65c5c669e 100644 --- a/arch/cris/arch-v32/boot/compressed/head.S +++ b/arch/cris/arch-v32/boot/compressed/head.S @@ -7,7 +7,7 @@ #define ASSEMBLER_MACROS_ONLY #include -#include +#include #define RAM_INIT_MAGIC 0x56902387 #define COMMAND_LINE_MAGIC 0x87109563 @@ -17,7 +17,7 @@ .globl input_data .text -start: +_start: di ;; Start clocks for used blocks. @@ -28,7 +28,13 @@ start: beq dram_init_finished nop -#include "../../mach/dram_init.S" +#if defined CONFIG_ETRAXFS +#include "../../mach-fs/dram_init.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../../mach-a3/dram_init.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif dram_init_finished: @@ -130,4 +136,10 @@ _cmd_line_addr: _boot_source: .dword 0 -#include "../../mach/hw_settings.S" +#if defined CONFIG_ETRAXFS +#include "../../mach-fs/hw_settings.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../../mach-a3/hw_settings.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c index ef98608e5067..7a87bc0ae2e8 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c +++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #ifdef CONFIG_ETRAX_VIRTUAL_GPIO #include "../i2c.h" diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c index 01ed0be2d0d1..25d6f2b3a721 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c +++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c index aa01b134458a..c5a0f54763cc 100644 --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c +++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c index 5b79a7a772d4..77ee319193c3 100644 --- a/arch/cris/arch-v32/drivers/pci/bios.c +++ b/arch/cris/arch-v32/drivers/pci/bios.c @@ -1,6 +1,6 @@ #include #include -#include +#include void __devinit pcibios_fixup_bus(struct pci_bus *b) { diff --git a/arch/cris/arch-v32/kernel/asm-offsets.c b/arch/cris/arch-v32/kernel/asm-offsets.c deleted file mode 100644 index 15b3d93a0496..000000000000 --- a/arch/cris/arch-v32/kernel/asm-offsets.c +++ /dev/null @@ -1,49 +0,0 @@ -#include -#include - -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - */ - -#define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) - -#define BLANK() asm volatile("\n->" : : ) - -int main(void) -{ -#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry)) - ENTRY(orig_r10); - ENTRY(r13); - ENTRY(r12); - ENTRY(r11); - ENTRY(r10); - ENTRY(r9); - ENTRY(acr); - ENTRY(srs); - ENTRY(mof); - ENTRY(ccs); - ENTRY(srp); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) - ENTRY(task); - ENTRY(flags); - ENTRY(preempt_count); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry)) - ENTRY(ksp); - ENTRY(usp); - ENTRY(ccs); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry)) - ENTRY(pid); - BLANK(); - DEFINE(LCLONE_VM, CLONE_VM); - DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED); - return 0; -} diff --git a/arch/cris/arch-v32/kernel/cache.c b/arch/cris/arch-v32/kernel/cache.c index 80da7b88a72b..f38433b1f861 100644 --- a/arch/cris/arch-v32/kernel/cache.c +++ b/arch/cris/arch-v32/kernel/cache.c @@ -1,7 +1,7 @@ #include #include -#include -#include +#include +#include /* This file is used to workaround a cache bug, Guinness TR 106. */ diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c index 77d02c15a7fc..64933e2c0f5b 100644 --- a/arch/cris/arch-v32/kernel/crisksyms.c +++ b/arch/cris/arch-v32/kernel/crisksyms.c @@ -1,9 +1,9 @@ #include #include -#include -#include -#include -#include +#include +#include +#include +#include /* Functions for allocating DMA channels */ EXPORT_SYMBOL(crisv32_request_dma); diff --git a/arch/cris/arch-v32/kernel/debugport.c b/arch/cris/arch-v32/kernel/debugport.c index 15af4c293157..794b364d9f7d 100644 --- a/arch/cris/arch-v32/kernel/debugport.c +++ b/arch/cris/arch-v32/kernel/debugport.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include struct dbg_port { diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S index eebbaba45430..7f6f93e6b70e 100644 --- a/arch/cris/arch-v32/kernel/entry.S +++ b/arch/cris/arch-v32/kernel/entry.S @@ -24,8 +24,8 @@ #include #include -#include -#include +#include +#include ;; Exported functions. .globl system_call diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S index 2d66a7c320e1..3db478eb5155 100644 --- a/arch/cris/arch-v32/kernel/head.S +++ b/arch/cris/arch-v32/kernel/head.S @@ -10,12 +10,13 @@ * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so * -traditional must not be used when assembling this file. */ +#include +#include #include -#include #include #include #include -#include +#include #define CRAMFS_MAGIC 0x28cd3d45 #define JHEAD_MAGIC 0x1FF528A6 @@ -217,7 +218,14 @@ _inflash: beq _dram_initialized nop -#include "../mach/dram_init.S" +#if defined CONFIG_ETRAXFS +#include "../mach-fs/dram_init.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../mach-a3/dram_init.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif + _dram_initialized: ;; Copy the text and data section to DRAM. This depends on that the @@ -472,4 +480,10 @@ swapper_pg_dir = 0xc0002000 .section ".init.data", "aw" -#include "../mach/hw_settings.S" +#if defined CONFIG_ETRAXFS +#include "../mach-fs/hw_settings.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../mach-a3/hw_settings.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif diff --git a/arch/cris/arch-v32/kernel/kgdb.c b/arch/cris/arch-v32/kernel/kgdb.c index 8bd5a5bc0dc7..c981fd663323 100644 --- a/arch/cris/arch-v32/kernel/kgdb.c +++ b/arch/cris/arch-v32/kernel/kgdb.c @@ -174,10 +174,10 @@ #include #include -#include -#include -#include -#include +#include +#include +#include +#include /* From entry.S. */ extern void gdb_handle_exception(void); diff --git a/arch/cris/arch-v32/kernel/kgdb_asm.S b/arch/cris/arch-v32/kernel/kgdb_asm.S index 3e7fa9ef8510..eba93e7e4aad 100644 --- a/arch/cris/arch-v32/kernel/kgdb_asm.S +++ b/arch/cris/arch-v32/kernel/kgdb_asm.S @@ -5,7 +5,7 @@ * port exceptions for kernel debugging purposes. */ -#include +#include ;; Exported functions. .globl kgdb_handle_exception diff --git a/arch/cris/arch-v32/kernel/pinmux.c b/arch/cris/arch-v32/kernel/pinmux.c index a2b8aa37c1bf..6eb54ea1c976 100644 --- a/arch/cris/arch-v32/kernel/pinmux.c +++ b/arch/cris/arch-v32/kernel/pinmux.c @@ -11,10 +11,10 @@ #include #include #include -#include -#include -#include -#include +#include +#include +#include +#include #undef DEBUG diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c index e27f4670e88e..dd401473f5b5 100644 --- a/arch/cris/arch-v32/kernel/ptrace.c +++ b/arch/cris/arch-v32/kernel/ptrace.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include /* * Determines which bits in CCS the user has access to. diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c index 58c1866804e3..da7d2be000ba 100644 --- a/arch/cris/arch-v32/kernel/signal.c +++ b/arch/cris/arch-v32/kernel/signal.c @@ -18,8 +18,8 @@ #include #include #include -#include -#include +#include +#include extern unsigned long cris_signal_return_page; diff --git a/arch/cris/arch-v32/lib/nand_init.S b/arch/cris/arch-v32/lib/nand_init.S index e019816facd7..e705f5cce969 100644 --- a/arch/cris/arch-v32/lib/nand_init.S +++ b/arch/cris/arch-v32/lib/nand_init.S @@ -22,11 +22,11 @@ ## ##============================================================================= -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include ;; There are 8-bit NAND flashes and 16-bit NAND flashes. ;; We need to treat them slightly different. diff --git a/arch/cris/arch-v32/mach-a3/dma.c b/arch/cris/arch-v32/mach-a3/dma.c index 25f236ef0b81..f35e4f65f4ef 100644 --- a/arch/cris/arch-v32/mach-a3/dma.c +++ b/arch/cris/arch-v32/mach-a3/dma.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/cris/arch-v32/mach-a3/io.c b/arch/cris/arch-v32/mach-a3/io.c index 9eeaf3eca474..c22f67ecd9f3 100644 --- a/arch/cris/arch-v32/mach-a3/io.c +++ b/arch/cris/arch-v32/mach-a3/io.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include struct crisv32_ioport crisv32_ioports[] = { diff --git a/arch/cris/arch-v32/mach-fs/cpufreq.c b/arch/cris/arch-v32/mach-fs/cpufreq.c index 58bd71e5bda9..d92cf70d1cbe 100644 --- a/arch/cris/arch-v32/mach-fs/cpufreq.c +++ b/arch/cris/arch-v32/mach-fs/cpufreq.c @@ -2,9 +2,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include static int cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val, diff --git a/arch/cris/arch-v32/mach-fs/dma.c b/arch/cris/arch-v32/mach-fs/dma.c index a6acf4e6345c..2d970d7505c9 100644 --- a/arch/cris/arch-v32/mach-fs/dma.c +++ b/arch/cris/arch-v32/mach-fs/dma.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include static char used_dma_channels[MAX_DMA_CHANNELS]; static const char *used_dma_channels_users[MAX_DMA_CHANNELS]; diff --git a/arch/cris/arch-v32/mach-fs/io.c b/arch/cris/arch-v32/mach-fs/io.c index a03a3ad3a188..cb6327b1f8f8 100644 --- a/arch/cris/arch-v32/mach-fs/io.c +++ b/arch/cris/arch-v32/mach-fs/io.c @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #ifndef DEBUG #define DEBUG(x) diff --git a/arch/cris/arch-v32/mach-fs/vcs_hook.c b/arch/cris/arch-v32/mach-fs/vcs_hook.c index 593b10f07ef1..b11594ae0cb6 100644 --- a/arch/cris/arch-v32/mach-fs/vcs_hook.c +++ b/arch/cris/arch-v32/mach-fs/vcs_hook.c @@ -5,8 +5,8 @@ #include "vcs_hook.h" #include -#include -#include +#include +#include #define HOOK_TRIG_ADDR 0xb7000000 /* hook cvlog model reg address */ #define HOOK_MEM_BASE_ADDR 0xa0000000 /* csp4 (shared mem) base addr */ diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c index 8a34b8b74293..caeb921a92ea 100644 --- a/arch/cris/arch-v32/mm/init.c +++ b/arch/cris/arch-v32/mm/init.c @@ -16,8 +16,8 @@ #include #include #include -#include -#include +#include +#include extern void tlb_init(void); diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c index eda5ebcaea54..55ade36fe8a8 100644 --- a/arch/cris/arch-v32/mm/tlb.c +++ b/arch/cris/arch-v32/mm/tlb.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include #define UPDATE_TLB_SEL_IDX(val) \ do { \ diff --git a/arch/cris/arch-v32/vmlinux.lds.S b/arch/cris/arch-v32/vmlinux.lds.S deleted file mode 100644 index d5f28e40717c..000000000000 --- a/arch/cris/arch-v32/vmlinux.lds.S +++ /dev/null @@ -1,133 +0,0 @@ -/* ld script to make the Linux/CRIS kernel - * Authors: Bjorn Wesen (bjornw@axis.com) - * - * It is VERY DANGEROUS to fiddle around with the symbols in this - * script. It is for example quite vital that all generated sections - * that are used are actually named here, otherwise the linker will - * put them at the end, where the init stuff is which is FREED after - * the kernel has booted. - */ - -#include -#include - -#ifdef CONFIG_ETRAX_VMEM_SIZE -#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE -#else -#define __CONFIG_ETRAX_VMEM_SIZE 0 -#endif - -jiffies = jiffies_64; -SECTIONS -{ - . = DRAM_VIRTUAL_BASE; - dram_start = .; - ebp_start = .; - - /* The boot section is only necessary until the VCS top */ - /* level testbench includes both flash and DRAM. */ - .boot : { *(.boot) } - - /* See head.S and pages reserved at the start. */ - . = DRAM_VIRTUAL_BASE + 0x4000; - - _text = .; /* Text and read-only data. */ - text_start = .; /* Lots of aliases. */ - _stext = .; - __stext = .; - .text : { - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT - *(.fixup) - *(.text.__*) - } - - _etext = . ; /* End of text section. */ - __etext = .; - - . = ALIGN(4); /* Exception table. */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - RODATA - - . = ALIGN (4); - ___data_start = . ; - __Sdata = . ; - .data : { /* Data */ - DATA_DATA - } - __edata = . ; /* End of data section. */ - _edata = . ; - - . = ALIGN(PAGE_SIZE); /* init_task and stack, must be aligned. */ - .data.init_task : { *(.data.init_task) } - - . = ALIGN(PAGE_SIZE); /* Init code and data. */ - __init_begin = .; - .init.text : { - _sinittext = .; - INIT_TEXT - _einittext = .; - } - .init.data : { INIT_DATA } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - __start___param = .; - __param : { *(__param) } - __stop___param = .; - .initcall.init : { - __initcall_start = .; - INITCALLS - __initcall_end = .; - } - - .con_initcall.init : { - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - } - SECURITY_INIT - - __vmlinux_end = .; /* Last address of the physical file. */ - PERCPU(PAGE_SIZE) - - .init.ramfs : { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } - - /* - * We fill to the next page, so we can discard all init - * pages without needing to consider what payload might be - * appended to the kernel image. - */ - . = ALIGN (PAGE_SIZE); - - __init_end = .; - - __data_end = . ; /* Move to _edata? */ - __bss_start = .; /* BSS. */ - .bss : { - *(COMMON) - *(.bss) - } - - . = ALIGN (0x20); - _end = .; - __end = .; - - /* Sections to be discarded */ - /DISCARD/ : { - EXIT_TEXT - EXIT_DATA - *(.exitcall.exit) - } - - dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024; -} diff --git a/arch/cris/include/arch-v10/arch/Kbuild b/arch/cris/include/arch-v10/arch/Kbuild new file mode 100644 index 000000000000..7a192e1290b1 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/Kbuild @@ -0,0 +1,4 @@ +header-y += user.h +header-y += svinto.h +header-y += sv_addr_ag.h +header-y += sv_addr.agh diff --git a/arch/cris/include/arch-v10/arch/atomic.h b/arch/cris/include/arch-v10/arch/atomic.h new file mode 100644 index 000000000000..6ef5e7d09024 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/atomic.h @@ -0,0 +1,7 @@ +#ifndef __ASM_CRIS_ARCH_ATOMIC__ +#define __ASM_CRIS_ARCH_ATOMIC__ + +#define cris_atomic_save(addr, flags) local_irq_save(flags); +#define cris_atomic_restore(addr, flags) local_irq_restore(flags); + +#endif diff --git a/arch/cris/include/arch-v10/arch/bitops.h b/arch/cris/include/arch-v10/arch/bitops.h new file mode 100644 index 000000000000..be85f6de25d3 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/bitops.h @@ -0,0 +1,73 @@ +/* asm/arch/bitops.h for Linux/CRISv10 */ + +#ifndef _CRIS_ARCH_BITOPS_H +#define _CRIS_ARCH_BITOPS_H + +/* + * Helper functions for the core of the ff[sz] functions, wrapping the + * syntactically awkward asms. The asms compute the number of leading + * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped + * number. They differ in that the first function also inverts all bits + * in the input. + */ +static inline unsigned long cris_swapnwbrlz(unsigned long w) +{ + /* Let's just say we return the result in the same register as the + input. Saying we clobber the input but can return the result + in another register: + ! __asm__ ("swapnwbr %2\n\tlz %2,%0" + ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); + confuses gcc (sched.c, gcc from cris-dist-1.14). */ + + unsigned long res; + __asm__ ("swapnwbr %0 \n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + return res; +} + +static inline unsigned long cris_swapwbrlz(unsigned long w) +{ + unsigned res; + __asm__ ("swapwbr %0 \n\t" + "lz %0,%0" + : "=r" (res) + : "0" (w)); + return res; +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long w) +{ + return cris_swapnwbrlz(w); +} + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline unsigned long __ffs(unsigned long word) +{ + return cris_swapnwbrlz(~word); +} + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +static inline unsigned long kernel_ffs(unsigned long w) +{ + return w ? cris_swapwbrlz (w) + 1 : 0; +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h new file mode 100644 index 000000000000..3485d6b34bb0 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/bug.h @@ -0,0 +1,66 @@ +#ifndef __ASM_CRISv10_ARCH_BUG_H +#define __ASM_CRISv10_ARCH_BUG_H + +#include + +#ifdef CONFIG_BUG +#ifdef CONFIG_DEBUG_BUGVERBOSE +/* The BUG() macro is used for marking obviously incorrect code paths. + * It will cause a message with the file name and line number to be printed, + * and then cause an oops. The message is actually printed by handle_BUG() + * in arch/cris/kernel/traps.c, and the reason we use this method of storing + * the file name and line number is that we do not want to affect the registers + * by calling printk() before causing the oops. + */ + +#define BUG_PREFIX 0x0D7F +#define BUG_MAGIC 0x00001234 + +struct bug_frame { + unsigned short prefix; + unsigned int magic; + unsigned short clear; + unsigned short movu; + unsigned short line; + unsigned short jump; + unsigned char *filename; +}; + +#if 0 +/* Unfortunately this version of the macro does not work due to a problem + * with the compiler (aka a bug) when compiling with -O2, which sometimes + * erroneously causes the second input to be stored in a register... + */ +#define BUG() \ + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ + "movu.w %0,$r0\n\t" \ + "jump %1\n\t" \ + : : "i" (__LINE__), "i" (__FILE__)) +#else +/* This version will have to do for now, until the compiler is fixed. + * The drawbacks of this version are that the file name will appear multiple + * times in the .rodata section, and that __LINE__ and __FILE__ can probably + * not be used like this with newer versions of gcc. + */ +#define BUG() \ + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ + "movu.w " __stringify(__LINE__) ",$r0\n\t"\ + "jump 0f\n\t" \ + ".section .rodata\n" \ + "0:\t.string \"" __FILE__ "\"\n\t" \ + ".previous") +#endif + +#else + +/* This just causes an oops. */ +#define BUG() (*(int *)0 = 0) + +#endif + +#define HAVE_ARCH_BUG +#endif + +#include + +#endif diff --git a/arch/cris/include/arch-v10/arch/byteorder.h b/arch/cris/include/arch-v10/arch/byteorder.h new file mode 100644 index 000000000000..255b646b7fa8 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/byteorder.h @@ -0,0 +1,26 @@ +#ifndef _CRIS_ARCH_BYTEORDER_H +#define _CRIS_ARCH_BYTEORDER_H + +#include +#include + +/* we just define these two (as we can do the swap in a single + * asm instruction in CRIS) and the arch-independent files will put + * them together into ntohl etc. + */ + +static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); + + return(x); +} + +static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__ ("swapb %0" : "=r" (x) : "0" (x)); + + return(x); +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/cache.h b/arch/cris/include/arch-v10/arch/cache.h new file mode 100644 index 000000000000..aea27184d2d2 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/cache.h @@ -0,0 +1,8 @@ +#ifndef _ASM_ARCH_CACHE_H +#define _ASM_ARCH_CACHE_H + +/* Etrax 100LX have 32-byte cache-lines. */ +#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 + +#endif /* _ASM_ARCH_CACHE_H */ diff --git a/arch/cris/include/arch-v10/arch/checksum.h b/arch/cris/include/arch-v10/arch/checksum.h new file mode 100644 index 000000000000..b8000c5d7fe1 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/checksum.h @@ -0,0 +1,29 @@ +#ifndef _CRIS_ARCH_CHECKSUM_H +#define _CRIS_ARCH_CHECKSUM_H + +/* Checksum some values used in TCP/UDP headers. + * + * The gain by doing this in asm is that C will not generate carry-additions + * for the 32-bit components of the checksum, so otherwise we would have had + * to split all of those into 16-bit components, then add. + */ + +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + __wsum res; + __asm__ ("add.d %2, %0\n\t" + "ax\n\t" + "add.d %3, %0\n\t" + "ax\n\t" + "add.d %4, %0\n\t" + "ax\n\t" + "addq 0, %0\n" + : "=r" (res) + : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8)); + + return res; +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/delay.h b/arch/cris/include/arch-v10/arch/delay.h new file mode 100644 index 000000000000..39481f6e0c30 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/delay.h @@ -0,0 +1,20 @@ +#ifndef _CRIS_ARCH_DELAY_H +#define _CRIS_ARCH_DELAY_H + +static inline void __delay(int loops) +{ + __asm__ __volatile__ ( + "move.d %0,$r9\n\t" + "beq 2f\n\t" + "subq 1,$r9\n\t" + "1:\n\t" + "bne 1b\n\t" + "subq 1,$r9\n" + "2:" + : : "g" (loops) : "r9"); +} + +#endif /* defined(_CRIS_ARCH_DELAY_H) */ + + + diff --git a/arch/cris/include/arch-v10/arch/dma.h b/arch/cris/include/arch-v10/arch/dma.h new file mode 100644 index 000000000000..ecb9dba6fa4f --- /dev/null +++ b/arch/cris/include/arch-v10/arch/dma.h @@ -0,0 +1,74 @@ +/* Defines for using and allocating dma channels. */ + +#ifndef _ASM_ARCH_DMA_H +#define _ASM_ARCH_DMA_H + +#define MAX_DMA_CHANNELS 10 + +/* dma0 and dma1 used for network (ethernet) */ +#define NETWORK_TX_DMA_NBR 0 +#define NETWORK_RX_DMA_NBR 1 + +/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ +#define PAR0_TX_DMA_NBR 2 +#define PAR0_RX_DMA_NBR 3 +#define SCSI0_TX_DMA_NBR 2 +#define SCSI0_RX_DMA_NBR 3 +#define SER2_TX_DMA_NBR 2 +#define SER2_RX_DMA_NBR 3 +#define ATA_TX_DMA_NBR 2 +#define ATA_RX_DMA_NBR 3 + +/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ +#define PAR1_TX_DMA_NBR 4 +#define PAR1_RX_DMA_NBR 5 +#define SCSI1_TX_DMA_NBR 4 +#define SCSI1_RX_DMA_NBR 5 +#define SER3_TX_DMA_NBR 4 +#define SER3_RX_DMA_NBR 5 +#define EXTDMA0_TX_DMA_NBR 4 +#define EXTDMA0_RX_DMA_NBR 5 + +/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ +#define SER0_TX_DMA_NBR 6 +#define SER0_RX_DMA_NBR 7 +#define EXTDMA1_TX_DMA_NBR 6 +#define EXTDMA1_RX_DMA_NBR 7 +#define MEM2MEM_TX_DMA_NBR 6 +#define MEM2MEM_RX_DMA_NBR 7 + +/* dma8 and dma9 shared by ser1 and usb */ +#define SER1_TX_DMA_NBR 8 +#define SER1_RX_DMA_NBR 9 +#define USB_TX_DMA_NBR 8 +#define USB_RX_DMA_NBR 9 + +#endif + +enum dma_owner +{ + dma_eth, + dma_ser0, + dma_ser1, /* Async and sync */ + dma_ser2, + dma_ser3, /* Async and sync */ + dma_ata, + dma_par0, + dma_par1, + dma_ext0, + dma_ext1, + dma_int6, + dma_int7, + dma_usb, + dma_scsi0, + dma_scsi1 +}; + +/* Masks used by cris_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR (1<<0) +#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) + +int cris_request_dma(unsigned int dmanr, const char * device_id, + unsigned options, enum dma_owner owner); + +void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/arch/cris/include/arch-v10/arch/elf.h b/arch/cris/include/arch-v10/arch/elf.h new file mode 100644 index 000000000000..1c38ee728b17 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/elf.h @@ -0,0 +1,81 @@ +#ifndef __ASMCRIS_ARCH_ELF_H +#define __ASMCRIS_ARCH_ELF_H + +#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_CRIS \ + && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ + || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) + +/* + * ELF register definitions.. + */ + +#include + +/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program + starts (a register; assume first param register for CRIS) + contains a pointer to a function which might be + registered using `atexit'. This provides a mean for the + dynamic linker to call DT_FINI functions for shared libraries + that have been loaded before the code runs. + + A value of 0 tells we have no such handler. */ + +/* Explicitly set registers to 0 to increase determinism. */ +#define ELF_PLAT_INIT(_r, load_addr) do { \ + (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ + (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ + (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ + (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ +} while (0) + +/* The additional layer below is because the stack pointer is missing in + the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, + and should be filled in according to the layout of the user_regs_struct + struct; regs is a pt_regs struct. We dump all registers, though several are + obviously unnecessary. That way there's less need for intelligence at + the receiving end (i.e. gdb). */ +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + pr_reg[0] = regs->r0; \ + pr_reg[1] = regs->r1; \ + pr_reg[2] = regs->r2; \ + pr_reg[3] = regs->r3; \ + pr_reg[4] = regs->r4; \ + pr_reg[5] = regs->r5; \ + pr_reg[6] = regs->r6; \ + pr_reg[7] = regs->r7; \ + pr_reg[8] = regs->r8; \ + pr_reg[9] = regs->r9; \ + pr_reg[10] = regs->r10; \ + pr_reg[11] = regs->r11; \ + pr_reg[12] = regs->r12; \ + pr_reg[13] = regs->r13; \ + pr_reg[14] = rdusp(); /* sp */ \ + pr_reg[15] = regs->irp; /* pc */ \ + pr_reg[16] = 0; /* p0 */ \ + pr_reg[17] = rdvr(); /* vr */ \ + pr_reg[18] = 0; /* p2 */ \ + pr_reg[19] = 0; /* p3 */ \ + pr_reg[20] = 0; /* p4 */ \ + pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ + pr_reg[22] = 0; /* p6 */ \ + pr_reg[23] = regs->mof; /* mof */ \ + pr_reg[24] = 0; /* p8 */ \ + pr_reg[25] = 0; /* ibr */ \ + pr_reg[26] = 0; /* irp */ \ + pr_reg[27] = regs->srp; /* srp */ \ + pr_reg[28] = 0; /* bar */ \ + pr_reg[29] = regs->dccr; /* dccr */ \ + pr_reg[30] = 0; /* brp */ \ + pr_reg[31] = rdusp(); /* usp */ \ + pr_reg[32] = 0; /* csrinstr */ \ + pr_reg[33] = 0; /* csraddr */ \ + pr_reg[34] = 0; /* csrdata */ + + +#endif diff --git a/arch/cris/include/arch-v10/arch/io.h b/arch/cris/include/arch-v10/arch/io.h new file mode 100644 index 000000000000..f627ad0b8a3d --- /dev/null +++ b/arch/cris/include/arch-v10/arch/io.h @@ -0,0 +1,199 @@ +#ifndef _ASM_ARCH_CRIS_IO_H +#define _ASM_ARCH_CRIS_IO_H + +#include + +/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ + +extern unsigned long gen_config_ii_shadow; +extern unsigned long port_g_data_shadow; +extern unsigned char port_pa_dir_shadow; +extern unsigned char port_pa_data_shadow; +extern unsigned char port_pb_i2c_shadow; +extern unsigned char port_pb_config_shadow; +extern unsigned char port_pb_dir_shadow; +extern unsigned char port_pb_data_shadow; +extern unsigned long r_timer_ctrl_shadow; + +extern unsigned long port_cse1_shadow; +extern unsigned long port_csp0_shadow; +extern unsigned long port_csp4_shadow; + +extern volatile unsigned long *port_cse1_addr; +extern volatile unsigned long *port_csp0_addr; +extern volatile unsigned long *port_csp4_addr; + +/* macro for setting regs through a shadow - + * r = register name (like R_PORT_PA_DATA) + * s = shadow name (like port_pa_data_shadow) + * b = bit number + * v = value (0 or 1) + */ + +#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) + +/* The LED's on various Etrax-based products are set differently. */ + +#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM) +#undef CONFIG_ETRAX_PA_LEDS +#undef CONFIG_ETRAX_PB_LEDS +#undef CONFIG_ETRAX_CSP0_LEDS +#define CRIS_LED_NETWORK_SET_G(x) +#define CRIS_LED_NETWORK_SET_R(x) +#define CRIS_LED_ACTIVE_SET_G(x) +#define CRIS_LED_ACTIVE_SET_R(x) +#define CRIS_LED_DISK_WRITE(x) +#define CRIS_LED_DISK_READ(x) +#endif + +#if !defined(CONFIG_ETRAX_CSP0_LEDS) +#define CRIS_LED_BIT_SET(x) +#define CRIS_LED_BIT_CLR(x) +#endif + +#define CRIS_LED_OFF 0x00 +#define CRIS_LED_GREEN 0x01 +#define CRIS_LED_RED 0x02 +#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) + +#if defined(CONFIG_ETRAX_NO_LEDS) +#define CRIS_LED_NETWORK_SET(x) +#else +#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R +#define CRIS_LED_NETWORK_SET(x) \ + do { \ + CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ + } while (0) +#else +#define CRIS_LED_NETWORK_SET(x) \ + do { \ + CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#endif +#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R +#define CRIS_LED_ACTIVE_SET(x) \ + do { \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + } while (0) +#else +#define CRIS_LED_ACTIVE_SET(x) \ + do { \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#endif +#endif + +#ifdef CONFIG_ETRAX_PA_LEDS +#define CRIS_LED_NETWORK_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) +#define CRIS_LED_NETWORK_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) +#define CRIS_LED_ACTIVE_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) +#define CRIS_LED_ACTIVE_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ + CONFIG_ETRAX_LED3G, !(x)) +#endif + +#ifdef CONFIG_ETRAX_PB_LEDS +#define CRIS_LED_NETWORK_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) +#define CRIS_LED_NETWORK_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) +#define CRIS_LED_ACTIVE_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) +#define CRIS_LED_ACTIVE_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ + CONFIG_ETRAX_LED3G, !(x)) +#endif + +#ifdef CONFIG_ETRAX_CSP0_LEDS +#define CONFIGURABLE_LEDS\ + ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ + (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ + (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ + (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ + (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ + (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ + (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ + (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ + (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ + (1 << CONFIG_ETRAX_LED12R )) + +#define CRIS_LED_NETWORK_SET_G(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) +#define CRIS_LED_NETWORK_SET_R(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) +#define CRIS_LED_ACTIVE_SET_G(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) +#define CRIS_LED_ACTIVE_SET_R(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) +#define CRIS_LED_BIT_SET(x)\ + do{\ + if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ + }while(0) +#define CRIS_LED_BIT_CLR(x)\ + do{\ + if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ + }while(0) +#endif + +# +#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN +#define SOFT_SHUTDOWN() \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) +#else +#define SOFT_SHUTDOWN() +#endif + +/* Console I/O for simulated etrax100. Use #ifdef so erroneous + use will be evident. */ +#ifdef CONFIG_SVINTO_SIM + /* Let's use the ucsim interface since it lets us do write(2, ...) */ +#define SIMCOUT(s,len) \ + asm ("moveq 4,$r9 \n\t" \ + "moveq 2,$r10 \n\t" \ + "move.d %0,$r11 \n\t" \ + "move.d %1,$r12 \n\t" \ + "push $irp \n\t" \ + "move 0f,$irp \n\t" \ + "jump -6809 \n" \ + "0: \n\t" \ + "pop $irp" \ + : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory") +#define TRACE_ON() __extension__ \ + ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \ + (255)); _Foofoo; }) + +#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0) +#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0) +#define CRIS_CYCLES() __extension__ \ + ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;}) +#endif /* ! defined CONFIG_SVINTO_SIM */ + +#endif diff --git a/arch/cris/include/arch-v10/arch/io_interface_mux.h b/arch/cris/include/arch-v10/arch/io_interface_mux.h new file mode 100644 index 000000000000..d92500080883 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/io_interface_mux.h @@ -0,0 +1,75 @@ +/* IO interface mux allocator for ETRAX100LX. + * Copyright 2004, Axis Communications AB + * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ + */ + + +#ifndef _IO_INTERFACE_MUX_H +#define _IO_INTERFACE_MUX_H + + +/* C.f. ETRAX100LX Designer's Reference 20.9 */ + +/* The order in enum must match the order of interfaces[] in + * io_interface_mux.c */ +enum cris_io_interface { + /* Begin Non-multiplexed interfaces */ + if_eth = 0, + if_serial_0, + /* End Non-multiplexed interfaces */ + if_serial_1, + if_serial_2, + if_serial_3, + if_sync_serial_1, + if_sync_serial_3, + if_shared_ram, + if_shared_ram_w, + if_par_0, + if_par_1, + if_par_w, + if_scsi8_0, + if_scsi8_1, + if_scsi_w, + if_ata, + if_csp, + if_i2c, + if_usb_1, + if_usb_2, + /* GPIO pins */ + if_gpio_grp_a, + if_gpio_grp_b, + if_gpio_grp_c, + if_gpio_grp_d, + if_gpio_grp_e, + if_gpio_grp_f, + if_max_interfaces, + if_unclaimed +}; + +int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); + +void cris_free_io_interface(enum cris_io_interface ioif); + +/* port can be 'a', 'b' or 'g' */ +int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, + const char port, + const unsigned start_bit, + const unsigned stop_bit); + +/* port can be 'a', 'b' or 'g' */ +int cris_io_interface_free_pins(const enum cris_io_interface ioif, + const char port, + const unsigned start_bit, + const unsigned stop_bit); + +int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)); + +void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)); + +#endif /* _IO_INTERFACE_MUX_H */ diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h new file mode 100644 index 000000000000..6248004eca1c --- /dev/null +++ b/arch/cris/include/arch-v10/arch/irq.h @@ -0,0 +1,160 @@ +/* + * Interrupt handling assembler and defines for Linux/CRISv10 + */ + +#ifndef _ASM_ARCH_IRQ_H +#define _ASM_ARCH_IRQ_H + +#include + +#define NR_IRQS 32 + +/* The first vector number used for IRQs in v10 is really 0x20 */ +/* but all the code and constants are offseted to make 0 the first */ +#define FIRST_IRQ 0 + +#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ +#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ +#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ +#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ +/* mio, ata, par0, scsi0 on 4 */ +/* par1, scsi1 on 5 */ +#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ + +#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ +#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ +/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ +#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) +#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) + +/* dma0-9 is irq 16..25 */ +/* 16,17: network */ +#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) +#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) +#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR +#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR + +/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ +#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) +#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) +#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR +#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR + +/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ +#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) +#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) +#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR +#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR + +/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ +#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) +#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) +#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR +#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR +#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR +#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR + +/* 24,25: dma8 and dma9 shared by ser1 and usb */ +#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) +#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) +#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR +#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR +#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR +#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR + +/* usb: controller at irq 31 + uses DMA8 and DMA9 */ +#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) + +/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ + +typedef void (*irqvectptr)(void); + +struct etrax_interrupt_vector { + irqvectptr v[256]; +}; + +extern struct etrax_interrupt_vector *etrax_irv; +void set_int_vector(int n, irqvectptr addr); +void set_break_vector(int n, irqvectptr addr); + +#define __STR(x) #x +#define STR(x) __STR(x) + +/* SAVE_ALL saves registers so they match pt_regs */ + +#define SAVE_ALL \ + "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ + "push $srp\n\t" /* push subroutine return pointer */ \ + "push $dccr\n\t" /* push condition codes */ \ + "push $mof\n\t" /* push multiply overflow reg */ \ + "di\n\t" /* need to disable irq's at this point */\ + "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ + "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ + "push $r10\n\t" /* push orig_r10 */ \ + "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ + + /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */ + +#define BLOCK_IRQ(mask,nr) \ + "move.d " #mask ",$r0\n\t" \ + "move.d $r0,[0xb00000d8]\n\t" + +#define UNBLOCK_IRQ(mask) \ + "move.d " #mask ",$r0\n\t" \ + "move.d $r0,[0xb00000dc]\n\t" + +#define IRQ_NAME2(nr) nr##_interrupt(void) +#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) +#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) +#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) + + /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls + * do_IRQ (with irq disabled still). after that it unblocks and jumps to + * ret_from_intr (entry.S) + * + * The reason the IRQ is blocked is to allow an sti() before the handler which + * will acknowledge the interrupt is run. + */ + +#define BUILD_IRQ(nr,mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ + "moveq "#nr",$r10\n\t" \ + "move.d $sp,$r11\n\t" \ + "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ + UNBLOCK_IRQ(mask) \ + "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ + "jump ret_from_intr\n\t"); + +/* This is subtle. The timer interrupt is crucial and it should not be disabled for + * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would + * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. + * If the softirq's take too much time to run, the timer irq won't run and the + * watchdog will kill us. + * + * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq + * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed + * it here, we would not get the multiple_irq at all. + * + * The non-blocking here is based on the knowledge that the timer interrupt is + * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not + * be an sti() before the timer irq handler is run to acknowledge the interrupt. + */ + +#define BUILD_TIMER_IRQ(nr,mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + "moveq "#nr",$r10\n\t" \ + "move.d $sp,$r11\n\t" \ + "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ + "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ + "jump ret_from_intr\n\t"); + +#endif diff --git a/arch/cris/include/arch-v10/arch/memmap.h b/arch/cris/include/arch-v10/arch/memmap.h new file mode 100644 index 000000000000..13f3b971407f --- /dev/null +++ b/arch/cris/include/arch-v10/arch/memmap.h @@ -0,0 +1,22 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/arch/cris/include/arch-v10/arch/mmu.h b/arch/cris/include/arch-v10/arch/mmu.h new file mode 100644 index 000000000000..df84f1716e6b --- /dev/null +++ b/arch/cris/include/arch-v10/arch/mmu.h @@ -0,0 +1,109 @@ +/* + * CRIS MMU constants and PTE layout + */ + +#ifndef _CRIS_ARCH_MMU_H +#define _CRIS_ARCH_MMU_H + +/* type used in struct mm to couple an MMU context to an active mm */ + +typedef struct +{ + unsigned int page_id; +} mm_context_t; + +/* kernel memory segments */ + +#define KSEG_F 0xf0000000UL +#define KSEG_E 0xe0000000UL +#define KSEG_D 0xd0000000UL +#define KSEG_C 0xc0000000UL +#define KSEG_B 0xb0000000UL +#define KSEG_A 0xa0000000UL +#define KSEG_9 0x90000000UL +#define KSEG_8 0x80000000UL +#define KSEG_7 0x70000000UL +#define KSEG_6 0x60000000UL +#define KSEG_5 0x50000000UL +#define KSEG_4 0x40000000UL +#define KSEG_3 0x30000000UL +#define KSEG_2 0x20000000UL +#define KSEG_1 0x10000000UL +#define KSEG_0 0x00000000UL + +/* CRIS PTE bits (see R_TLB_LO in the register description) + * + * Bit: 31-13 12-------4 3 2 1 0 + * ________________________________________________ + * | pfn | reserved | global | valid | kernel | we | + * |_____|__________|________|_______|________|_____| + * + * (pfn = physical frame number) + */ + +/* Real HW-based PTE bits. We use some synonym names so that + * things become less confusing in combination with the SW-based + * bits further below. + * + */ + +#define _PAGE_WE (1<<0) /* page is write-enabled */ +#define _PAGE_SILENT_WRITE (1<<0) /* synonym */ +#define _PAGE_KERNEL (1<<1) /* page is kernel only */ +#define _PAGE_VALID (1<<2) /* page is valid */ +#define _PAGE_SILENT_READ (1<<2) /* synonym */ +#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ + +/* Bits the HW doesn't care about but the kernel uses them in SW */ + +#define _PAGE_PRESENT (1<<4) /* page present in memory */ +#define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */ +#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ +#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ +#define _PAGE_READ (1<<7) /* read-enabled */ +#define _PAGE_WRITE (1<<8) /* write-enabled */ + +/* Define some higher level generic page attributes. */ + +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) + +#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED) +#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) + +/* + * CRIS can't do page protection for execute, and considers read the same. + * Also, write permissions imply read permissions. This is the closest we can + * get.. + */ + +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED + +#define PTE_FILE_MAX_BITS 26 + +#endif diff --git a/arch/cris/include/arch-v10/arch/offset.h b/arch/cris/include/arch-v10/arch/offset.h new file mode 100644 index 000000000000..675b51d85639 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/offset.h @@ -0,0 +1,33 @@ +#ifndef __ASM_OFFSETS_H__ +#define __ASM_OFFSETS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by arch/cris/Makefile + * + */ + +#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ +#define PT_r13 8 /* offsetof(struct pt_regs, r13) */ +#define PT_r12 12 /* offsetof(struct pt_regs, r12) */ +#define PT_r11 16 /* offsetof(struct pt_regs, r11) */ +#define PT_r10 20 /* offsetof(struct pt_regs, r10) */ +#define PT_r9 24 /* offsetof(struct pt_regs, r9) */ +#define PT_mof 64 /* offsetof(struct pt_regs, mof) */ +#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ +#define PT_srp 72 /* offsetof(struct pt_regs, srp) */ + +#define TI_task 0 /* offsetof(struct thread_info, task) */ +#define TI_flags 8 /* offsetof(struct thread_info, flags) */ +#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ + +#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ +#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ +#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ + +#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ + +#define LCLONE_VM 256 /* CLONE_VM */ +#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ + +#endif diff --git a/arch/cris/include/arch-v10/arch/page.h b/arch/cris/include/arch-v10/arch/page.h new file mode 100644 index 000000000000..ffafc99c3472 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/page.h @@ -0,0 +1,30 @@ +#ifndef _CRIS_ARCH_PAGE_H +#define _CRIS_ARCH_PAGE_H + + +#ifdef __KERNEL__ + +/* This handles the memory map.. */ +#ifdef CONFIG_CRIS_LOW_MAP +#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ +#else +#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ +#endif + +/* macros to convert between really physical and virtual addresses + * by stripping a selected bit, we can convert between KSEG_x and + * 0x40000000 where the DRAM really resides + */ + +#ifdef CONFIG_CRIS_LOW_MAP +/* we have DRAM virtually at 0x6 */ +#define __pa(x) ((unsigned long)(x) & 0xdfffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) +#else +/* we have DRAM virtually at 0xc */ +#define __pa(x) ((unsigned long)(x) & 0x7fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) +#endif + +#endif +#endif diff --git a/arch/cris/include/arch-v10/arch/pgtable.h b/arch/cris/include/arch-v10/arch/pgtable.h new file mode 100644 index 000000000000..2a2576d1fc97 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/pgtable.h @@ -0,0 +1,17 @@ +#ifndef _CRIS_ARCH_PGTABLE_H +#define _CRIS_ARCH_PGTABLE_H + +/* + * Kernels own virtual memory area. + */ + +#ifdef CONFIG_CRIS_LOW_MAP +#define VMALLOC_START KSEG_7 +#define VMALLOC_END KSEG_8 +#else +#define VMALLOC_START KSEG_D +#define VMALLOC_END KSEG_E +#endif + +#endif + diff --git a/arch/cris/include/arch-v10/arch/processor.h b/arch/cris/include/arch-v10/arch/processor.h new file mode 100644 index 000000000000..cc692c7a0660 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/processor.h @@ -0,0 +1,70 @@ +#ifndef __ASM_CRIS_ARCH_PROCESSOR_H +#define __ASM_CRIS_ARCH_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) + +/* CRIS has no problems with write protection */ +#define wp_works_ok 1 + +/* CRIS thread_struct. this really has nothing to do with the processor itself, since + * CRIS does not do any hardware task-switching, but it's here for legacy reasons. + * The thread_struct here is used when task-switching using _resume defined in entry.S. + * The offsets here are hardcoded into _resume - if you change this struct, you need to + * change them as well!!! +*/ + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned long dccr; /* saved flag register */ +}; + +/* + * User space process size. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ + +#ifdef CONFIG_CRIS_LOW_MAP +#define TASK_SIZE (0x50000000UL) /* 1.25 GB */ +#else +#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ +#endif + +#define INIT_THREAD { \ + 0, 0, 0x20 } /* ccr = int enable, nothing else */ + +#define KSTK_EIP(tsk) \ +({ \ + unsigned long eip = 0; \ + unsigned long regs = (unsigned long)task_pt_regs(tsk); \ + if (regs > PAGE_SIZE && \ + virt_addr_valid(regs)) \ + eip = ((struct pt_regs *)regs)->irp; \ + eip; \ +}) + +/* give the thread a program location + * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) + * switch user-stackpointer + */ + +#define start_thread(regs, ip, usp) do { \ + set_fs(USER_DS); \ + regs->irp = ip; \ + regs->dccr |= 1 << U_DCCR_BITNR; \ + wrusp(usp); \ +} while(0) + +/* Called when handling a kernel bus fault fixup. + * + * After a fixup we do not want to return by restoring the CPU-state + * anymore, so switch frame-types (see ptrace.h) + */ +#define arch_fixup(regs) \ + regs->frametype = CRIS_FRAME_NORMAL; + +#endif diff --git a/arch/cris/include/arch-v10/arch/ptrace.h b/arch/cris/include/arch-v10/arch/ptrace.h new file mode 100644 index 000000000000..2f464eab3a51 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/ptrace.h @@ -0,0 +1,119 @@ +#ifndef _CRIS_ARCH_PTRACE_H +#define _CRIS_ARCH_PTRACE_H + +/* Frame types */ + +#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ +#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return + path */ + +/* Register numbers in the ptrace system call interface */ + +#define PT_FRAMETYPE 0 +#define PT_ORIG_R10 1 +#define PT_R13 2 +#define PT_R12 3 +#define PT_R11 4 +#define PT_R10 5 +#define PT_R9 6 +#define PT_R8 7 +#define PT_R7 8 +#define PT_R6 9 +#define PT_R5 10 +#define PT_R4 11 +#define PT_R3 12 +#define PT_R2 13 +#define PT_R1 14 +#define PT_R0 15 +#define PT_MOF 16 +#define PT_DCCR 17 +#define PT_SRP 18 +#define PT_IRP 19 /* This is actually the debugged process' PC */ +#define PT_CSRINSTR 20 /* CPU Status record remnants - + valid if frametype == busfault */ +#define PT_CSRADDR 21 +#define PT_CSRDATA 22 +#define PT_USP 23 /* special case - USP is not in the pt_regs */ +#define PT_MAX 23 + +/* Condition code bit numbers. The same numbers apply to CCR of course, + but we use DCCR everywhere else, so let's try and be consistent. */ +#define C_DCCR_BITNR 0 +#define V_DCCR_BITNR 1 +#define Z_DCCR_BITNR 2 +#define N_DCCR_BITNR 3 +#define X_DCCR_BITNR 4 +#define I_DCCR_BITNR 5 +#define B_DCCR_BITNR 6 +#define M_DCCR_BITNR 7 +#define U_DCCR_BITNR 8 +#define P_DCCR_BITNR 9 +#define F_DCCR_BITNR 10 + +/* pt_regs not only specifices the format in the user-struct during + * ptrace but is also the frame format used in the kernel prologue/epilogues + * themselves + */ + +struct pt_regs { + unsigned long frametype; /* type of stackframe */ + unsigned long orig_r10; + /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ + unsigned long r13; + unsigned long r12; + unsigned long r11; + unsigned long r10; + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + unsigned long mof; + unsigned long dccr; + unsigned long srp; + unsigned long irp; /* This is actually the debugged process' PC */ + unsigned long csrinstr; + unsigned long csraddr; + unsigned long csrdata; +}; + +/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) + * when doing a context-switch. it is used (apart from in resume) when a new + * thread is made and we need to make _resume (which is starting it for the + * first time) realise what is going on. + * + * Actually, the use is very close to the thread struct (TSS) in that both the + * switch_stack and the TSS are used to keep thread stuff when switching in + * _resume. + */ + +struct switch_stack { + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + unsigned long return_ip; /* ip that _resume will return to */ +}; + +#ifdef __KERNEL__ + +/* bit 8 is user-mode flag */ +#define user_mode(regs) (((regs)->dccr & 0x100) != 0) +#define instruction_pointer(regs) ((regs)->irp) +#define profile_pc(regs) instruction_pointer(regs) +extern void show_regs(struct pt_regs *); + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/cris/include/arch-v10/arch/sv_addr.agh b/arch/cris/include/arch-v10/arch/sv_addr.agh new file mode 100644 index 000000000000..6ac3a7bc9760 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/sv_addr.agh @@ -0,0 +1,7306 @@ +/* +!* This file was automatically generated by /n/asic/bin/reg_macro_gen +!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. +!* Editing within this file is thus not recommended, +!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. +!*/ + + +/* +!* Bus interface configuration registers +!*/ + +#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) +#define R_WAITSTATES__pcs4_7_zw__BITNR 30 +#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 +#define R_WAITSTATES__pcs4_7_ew__BITNR 28 +#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 +#define R_WAITSTATES__pcs4_7_lw__BITNR 24 +#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 +#define R_WAITSTATES__pcs0_3_zw__BITNR 22 +#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 +#define R_WAITSTATES__pcs0_3_ew__BITNR 20 +#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 +#define R_WAITSTATES__pcs0_3_lw__BITNR 16 +#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 +#define R_WAITSTATES__sram_zw__BITNR 14 +#define R_WAITSTATES__sram_zw__WIDTH 2 +#define R_WAITSTATES__sram_ew__BITNR 12 +#define R_WAITSTATES__sram_ew__WIDTH 2 +#define R_WAITSTATES__sram_lw__BITNR 8 +#define R_WAITSTATES__sram_lw__WIDTH 4 +#define R_WAITSTATES__flash_zw__BITNR 6 +#define R_WAITSTATES__flash_zw__WIDTH 2 +#define R_WAITSTATES__flash_ew__BITNR 4 +#define R_WAITSTATES__flash_ew__WIDTH 2 +#define R_WAITSTATES__flash_lw__BITNR 0 +#define R_WAITSTATES__flash_lw__WIDTH 4 + +#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) +#define R_BUS_CONFIG__sram_type__BITNR 9 +#define R_BUS_CONFIG__sram_type__WIDTH 1 +#define R_BUS_CONFIG__sram_type__cwe 1 +#define R_BUS_CONFIG__sram_type__bwe 0 +#define R_BUS_CONFIG__dma_burst__BITNR 8 +#define R_BUS_CONFIG__dma_burst__WIDTH 1 +#define R_BUS_CONFIG__dma_burst__burst16 1 +#define R_BUS_CONFIG__dma_burst__burst32 0 +#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 +#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 +#define R_BUS_CONFIG__pcs4_7_wr__ext 1 +#define R_BUS_CONFIG__pcs4_7_wr__norm 0 +#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 +#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 +#define R_BUS_CONFIG__pcs0_3_wr__ext 1 +#define R_BUS_CONFIG__pcs0_3_wr__norm 0 +#define R_BUS_CONFIG__sram_wr__BITNR 5 +#define R_BUS_CONFIG__sram_wr__WIDTH 1 +#define R_BUS_CONFIG__sram_wr__ext 1 +#define R_BUS_CONFIG__sram_wr__norm 0 +#define R_BUS_CONFIG__flash_wr__BITNR 4 +#define R_BUS_CONFIG__flash_wr__WIDTH 1 +#define R_BUS_CONFIG__flash_wr__ext 1 +#define R_BUS_CONFIG__flash_wr__norm 0 +#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 +#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 +#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 +#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 +#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 +#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 +#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 +#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 +#define R_BUS_CONFIG__sram_bw__BITNR 1 +#define R_BUS_CONFIG__sram_bw__WIDTH 1 +#define R_BUS_CONFIG__sram_bw__bw32 1 +#define R_BUS_CONFIG__sram_bw__bw16 0 +#define R_BUS_CONFIG__flash_bw__BITNR 0 +#define R_BUS_CONFIG__flash_bw__WIDTH 1 +#define R_BUS_CONFIG__flash_bw__bw32 1 +#define R_BUS_CONFIG__flash_bw__bw16 0 + +#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) +#define R_BUS_STATUS__pll_lock_tm__BITNR 5 +#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 +#define R_BUS_STATUS__pll_lock_tm__expired 0 +#define R_BUS_STATUS__pll_lock_tm__counting 1 +#define R_BUS_STATUS__both_faults__BITNR 4 +#define R_BUS_STATUS__both_faults__WIDTH 1 +#define R_BUS_STATUS__both_faults__no 0 +#define R_BUS_STATUS__both_faults__yes 1 +#define R_BUS_STATUS__bsen___BITNR 3 +#define R_BUS_STATUS__bsen___WIDTH 1 +#define R_BUS_STATUS__bsen___enable 0 +#define R_BUS_STATUS__bsen___disable 1 +#define R_BUS_STATUS__boot__BITNR 1 +#define R_BUS_STATUS__boot__WIDTH 2 +#define R_BUS_STATUS__boot__uncached 0 +#define R_BUS_STATUS__boot__serial 1 +#define R_BUS_STATUS__boot__network 2 +#define R_BUS_STATUS__boot__parallel 3 +#define R_BUS_STATUS__flashw__BITNR 0 +#define R_BUS_STATUS__flashw__WIDTH 1 +#define R_BUS_STATUS__flashw__bw32 1 +#define R_BUS_STATUS__flashw__bw16 0 + +#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) +#define R_DRAM_TIMING__sdram__BITNR 31 +#define R_DRAM_TIMING__sdram__WIDTH 1 +#define R_DRAM_TIMING__sdram__enable 1 +#define R_DRAM_TIMING__sdram__disable 0 +#define R_DRAM_TIMING__ref__BITNR 14 +#define R_DRAM_TIMING__ref__WIDTH 2 +#define R_DRAM_TIMING__ref__e52us 0 +#define R_DRAM_TIMING__ref__e13us 1 +#define R_DRAM_TIMING__ref__e8700ns 2 +#define R_DRAM_TIMING__ref__disable 3 +#define R_DRAM_TIMING__rp__BITNR 12 +#define R_DRAM_TIMING__rp__WIDTH 2 +#define R_DRAM_TIMING__rs__BITNR 10 +#define R_DRAM_TIMING__rs__WIDTH 2 +#define R_DRAM_TIMING__rh__BITNR 8 +#define R_DRAM_TIMING__rh__WIDTH 2 +#define R_DRAM_TIMING__w__BITNR 7 +#define R_DRAM_TIMING__w__WIDTH 1 +#define R_DRAM_TIMING__w__norm 0 +#define R_DRAM_TIMING__w__ext 1 +#define R_DRAM_TIMING__c__BITNR 6 +#define R_DRAM_TIMING__c__WIDTH 1 +#define R_DRAM_TIMING__c__norm 0 +#define R_DRAM_TIMING__c__ext 1 +#define R_DRAM_TIMING__cz__BITNR 4 +#define R_DRAM_TIMING__cz__WIDTH 2 +#define R_DRAM_TIMING__cp__BITNR 2 +#define R_DRAM_TIMING__cp__WIDTH 2 +#define R_DRAM_TIMING__cw__BITNR 0 +#define R_DRAM_TIMING__cw__WIDTH 2 + +#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) +#define R_SDRAM_TIMING__sdram__BITNR 31 +#define R_SDRAM_TIMING__sdram__WIDTH 1 +#define R_SDRAM_TIMING__sdram__enable 1 +#define R_SDRAM_TIMING__sdram__disable 0 +#define R_SDRAM_TIMING__mrs_data__BITNR 16 +#define R_SDRAM_TIMING__mrs_data__WIDTH 15 +#define R_SDRAM_TIMING__ref__BITNR 14 +#define R_SDRAM_TIMING__ref__WIDTH 2 +#define R_SDRAM_TIMING__ref__e52us 0 +#define R_SDRAM_TIMING__ref__e13us 1 +#define R_SDRAM_TIMING__ref__e6500ns 2 +#define R_SDRAM_TIMING__ref__disable 3 +#define R_SDRAM_TIMING__ddr__BITNR 13 +#define R_SDRAM_TIMING__ddr__WIDTH 1 +#define R_SDRAM_TIMING__ddr__on 1 +#define R_SDRAM_TIMING__ddr__off 0 +#define R_SDRAM_TIMING__clk100__BITNR 12 +#define R_SDRAM_TIMING__clk100__WIDTH 1 +#define R_SDRAM_TIMING__clk100__on 1 +#define R_SDRAM_TIMING__clk100__off 0 +#define R_SDRAM_TIMING__ps__BITNR 11 +#define R_SDRAM_TIMING__ps__WIDTH 1 +#define R_SDRAM_TIMING__ps__on 1 +#define R_SDRAM_TIMING__ps__off 0 +#define R_SDRAM_TIMING__cmd__BITNR 9 +#define R_SDRAM_TIMING__cmd__WIDTH 2 +#define R_SDRAM_TIMING__cmd__pre 3 +#define R_SDRAM_TIMING__cmd__ref 2 +#define R_SDRAM_TIMING__cmd__mrs 1 +#define R_SDRAM_TIMING__cmd__nop 0 +#define R_SDRAM_TIMING__pde__BITNR 8 +#define R_SDRAM_TIMING__pde__WIDTH 1 +#define R_SDRAM_TIMING__rc__BITNR 6 +#define R_SDRAM_TIMING__rc__WIDTH 2 +#define R_SDRAM_TIMING__rp__BITNR 4 +#define R_SDRAM_TIMING__rp__WIDTH 2 +#define R_SDRAM_TIMING__rcd__BITNR 2 +#define R_SDRAM_TIMING__rcd__WIDTH 2 +#define R_SDRAM_TIMING__cl__BITNR 0 +#define R_SDRAM_TIMING__cl__WIDTH 2 + +#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) +#define R_DRAM_CONFIG__wmm1__BITNR 31 +#define R_DRAM_CONFIG__wmm1__WIDTH 1 +#define R_DRAM_CONFIG__wmm1__wmm 1 +#define R_DRAM_CONFIG__wmm1__norm 0 +#define R_DRAM_CONFIG__wmm0__BITNR 30 +#define R_DRAM_CONFIG__wmm0__WIDTH 1 +#define R_DRAM_CONFIG__wmm0__wmm 1 +#define R_DRAM_CONFIG__wmm0__norm 0 +#define R_DRAM_CONFIG__sh1__BITNR 27 +#define R_DRAM_CONFIG__sh1__WIDTH 3 +#define R_DRAM_CONFIG__sh0__BITNR 24 +#define R_DRAM_CONFIG__sh0__WIDTH 3 +#define R_DRAM_CONFIG__w__BITNR 23 +#define R_DRAM_CONFIG__w__WIDTH 1 +#define R_DRAM_CONFIG__w__bw16 0 +#define R_DRAM_CONFIG__w__bw32 1 +#define R_DRAM_CONFIG__c__BITNR 22 +#define R_DRAM_CONFIG__c__WIDTH 1 +#define R_DRAM_CONFIG__c__byte 0 +#define R_DRAM_CONFIG__c__bank 1 +#define R_DRAM_CONFIG__e__BITNR 21 +#define R_DRAM_CONFIG__e__WIDTH 1 +#define R_DRAM_CONFIG__e__fast 0 +#define R_DRAM_CONFIG__e__edo 1 +#define R_DRAM_CONFIG__group_sel__BITNR 16 +#define R_DRAM_CONFIG__group_sel__WIDTH 5 +#define R_DRAM_CONFIG__group_sel__grp0 0 +#define R_DRAM_CONFIG__group_sel__grp1 1 +#define R_DRAM_CONFIG__group_sel__bit9 9 +#define R_DRAM_CONFIG__group_sel__bit10 10 +#define R_DRAM_CONFIG__group_sel__bit11 11 +#define R_DRAM_CONFIG__group_sel__bit12 12 +#define R_DRAM_CONFIG__group_sel__bit13 13 +#define R_DRAM_CONFIG__group_sel__bit14 14 +#define R_DRAM_CONFIG__group_sel__bit15 15 +#define R_DRAM_CONFIG__group_sel__bit16 16 +#define R_DRAM_CONFIG__group_sel__bit17 17 +#define R_DRAM_CONFIG__group_sel__bit18 18 +#define R_DRAM_CONFIG__group_sel__bit19 19 +#define R_DRAM_CONFIG__group_sel__bit20 20 +#define R_DRAM_CONFIG__group_sel__bit21 21 +#define R_DRAM_CONFIG__group_sel__bit22 22 +#define R_DRAM_CONFIG__group_sel__bit23 23 +#define R_DRAM_CONFIG__group_sel__bit24 24 +#define R_DRAM_CONFIG__group_sel__bit25 25 +#define R_DRAM_CONFIG__group_sel__bit26 26 +#define R_DRAM_CONFIG__group_sel__bit27 27 +#define R_DRAM_CONFIG__group_sel__bit28 28 +#define R_DRAM_CONFIG__group_sel__bit29 29 +#define R_DRAM_CONFIG__ca1__BITNR 13 +#define R_DRAM_CONFIG__ca1__WIDTH 3 +#define R_DRAM_CONFIG__bank23sel__BITNR 8 +#define R_DRAM_CONFIG__bank23sel__WIDTH 5 +#define R_DRAM_CONFIG__bank23sel__bank0 0 +#define R_DRAM_CONFIG__bank23sel__bank1 1 +#define R_DRAM_CONFIG__bank23sel__bit9 9 +#define R_DRAM_CONFIG__bank23sel__bit10 10 +#define R_DRAM_CONFIG__bank23sel__bit11 11 +#define R_DRAM_CONFIG__bank23sel__bit12 12 +#define R_DRAM_CONFIG__bank23sel__bit13 13 +#define R_DRAM_CONFIG__bank23sel__bit14 14 +#define R_DRAM_CONFIG__bank23sel__bit15 15 +#define R_DRAM_CONFIG__bank23sel__bit16 16 +#define R_DRAM_CONFIG__bank23sel__bit17 17 +#define R_DRAM_CONFIG__bank23sel__bit18 18 +#define R_DRAM_CONFIG__bank23sel__bit19 19 +#define R_DRAM_CONFIG__bank23sel__bit20 20 +#define R_DRAM_CONFIG__bank23sel__bit21 21 +#define R_DRAM_CONFIG__bank23sel__bit22 22 +#define R_DRAM_CONFIG__bank23sel__bit23 23 +#define R_DRAM_CONFIG__bank23sel__bit24 24 +#define R_DRAM_CONFIG__bank23sel__bit25 25 +#define R_DRAM_CONFIG__bank23sel__bit26 26 +#define R_DRAM_CONFIG__bank23sel__bit27 27 +#define R_DRAM_CONFIG__bank23sel__bit28 28 +#define R_DRAM_CONFIG__bank23sel__bit29 29 +#define R_DRAM_CONFIG__ca0__BITNR 5 +#define R_DRAM_CONFIG__ca0__WIDTH 3 +#define R_DRAM_CONFIG__bank01sel__BITNR 0 +#define R_DRAM_CONFIG__bank01sel__WIDTH 5 +#define R_DRAM_CONFIG__bank01sel__bank0 0 +#define R_DRAM_CONFIG__bank01sel__bank1 1 +#define R_DRAM_CONFIG__bank01sel__bit9 9 +#define R_DRAM_CONFIG__bank01sel__bit10 10 +#define R_DRAM_CONFIG__bank01sel__bit11 11 +#define R_DRAM_CONFIG__bank01sel__bit12 12 +#define R_DRAM_CONFIG__bank01sel__bit13 13 +#define R_DRAM_CONFIG__bank01sel__bit14 14 +#define R_DRAM_CONFIG__bank01sel__bit15 15 +#define R_DRAM_CONFIG__bank01sel__bit16 16 +#define R_DRAM_CONFIG__bank01sel__bit17 17 +#define R_DRAM_CONFIG__bank01sel__bit18 18 +#define R_DRAM_CONFIG__bank01sel__bit19 19 +#define R_DRAM_CONFIG__bank01sel__bit20 20 +#define R_DRAM_CONFIG__bank01sel__bit21 21 +#define R_DRAM_CONFIG__bank01sel__bit22 22 +#define R_DRAM_CONFIG__bank01sel__bit23 23 +#define R_DRAM_CONFIG__bank01sel__bit24 24 +#define R_DRAM_CONFIG__bank01sel__bit25 25 +#define R_DRAM_CONFIG__bank01sel__bit26 26 +#define R_DRAM_CONFIG__bank01sel__bit27 27 +#define R_DRAM_CONFIG__bank01sel__bit28 28 +#define R_DRAM_CONFIG__bank01sel__bit29 29 + +#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) +#define R_SDRAM_CONFIG__wmm1__BITNR 31 +#define R_SDRAM_CONFIG__wmm1__WIDTH 1 +#define R_SDRAM_CONFIG__wmm1__wmm 1 +#define R_SDRAM_CONFIG__wmm1__norm 0 +#define R_SDRAM_CONFIG__wmm0__BITNR 30 +#define R_SDRAM_CONFIG__wmm0__WIDTH 1 +#define R_SDRAM_CONFIG__wmm0__wmm 1 +#define R_SDRAM_CONFIG__wmm0__norm 0 +#define R_SDRAM_CONFIG__sh1__BITNR 27 +#define R_SDRAM_CONFIG__sh1__WIDTH 3 +#define R_SDRAM_CONFIG__sh0__BITNR 24 +#define R_SDRAM_CONFIG__sh0__WIDTH 3 +#define R_SDRAM_CONFIG__w__BITNR 23 +#define R_SDRAM_CONFIG__w__WIDTH 1 +#define R_SDRAM_CONFIG__w__bw16 0 +#define R_SDRAM_CONFIG__w__bw32 1 +#define R_SDRAM_CONFIG__type1__BITNR 22 +#define R_SDRAM_CONFIG__type1__WIDTH 1 +#define R_SDRAM_CONFIG__type1__bank2 0 +#define R_SDRAM_CONFIG__type1__bank4 1 +#define R_SDRAM_CONFIG__type0__BITNR 21 +#define R_SDRAM_CONFIG__type0__WIDTH 1 +#define R_SDRAM_CONFIG__type0__bank2 0 +#define R_SDRAM_CONFIG__type0__bank4 1 +#define R_SDRAM_CONFIG__group_sel__BITNR 16 +#define R_SDRAM_CONFIG__group_sel__WIDTH 5 +#define R_SDRAM_CONFIG__group_sel__grp0 0 +#define R_SDRAM_CONFIG__group_sel__grp1 1 +#define R_SDRAM_CONFIG__group_sel__bit9 9 +#define R_SDRAM_CONFIG__group_sel__bit10 10 +#define R_SDRAM_CONFIG__group_sel__bit11 11 +#define R_SDRAM_CONFIG__group_sel__bit12 12 +#define R_SDRAM_CONFIG__group_sel__bit13 13 +#define R_SDRAM_CONFIG__group_sel__bit14 14 +#define R_SDRAM_CONFIG__group_sel__bit15 15 +#define R_SDRAM_CONFIG__group_sel__bit16 16 +#define R_SDRAM_CONFIG__group_sel__bit17 17 +#define R_SDRAM_CONFIG__group_sel__bit18 18 +#define R_SDRAM_CONFIG__group_sel__bit19 19 +#define R_SDRAM_CONFIG__group_sel__bit20 20 +#define R_SDRAM_CONFIG__group_sel__bit21 21 +#define R_SDRAM_CONFIG__group_sel__bit22 22 +#define R_SDRAM_CONFIG__group_sel__bit23 23 +#define R_SDRAM_CONFIG__group_sel__bit24 24 +#define R_SDRAM_CONFIG__group_sel__bit25 25 +#define R_SDRAM_CONFIG__group_sel__bit26 26 +#define R_SDRAM_CONFIG__group_sel__bit27 27 +#define R_SDRAM_CONFIG__group_sel__bit28 28 +#define R_SDRAM_CONFIG__group_sel__bit29 29 +#define R_SDRAM_CONFIG__ca1__BITNR 13 +#define R_SDRAM_CONFIG__ca1__WIDTH 3 +#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 +#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 +#define R_SDRAM_CONFIG__bank_sel1__bit9 9 +#define R_SDRAM_CONFIG__bank_sel1__bit10 10 +#define R_SDRAM_CONFIG__bank_sel1__bit11 11 +#define R_SDRAM_CONFIG__bank_sel1__bit12 12 +#define R_SDRAM_CONFIG__bank_sel1__bit13 13 +#define R_SDRAM_CONFIG__bank_sel1__bit14 14 +#define R_SDRAM_CONFIG__bank_sel1__bit15 15 +#define R_SDRAM_CONFIG__bank_sel1__bit16 16 +#define R_SDRAM_CONFIG__bank_sel1__bit17 17 +#define R_SDRAM_CONFIG__bank_sel1__bit18 18 +#define R_SDRAM_CONFIG__bank_sel1__bit19 19 +#define R_SDRAM_CONFIG__bank_sel1__bit20 20 +#define R_SDRAM_CONFIG__bank_sel1__bit21 21 +#define R_SDRAM_CONFIG__bank_sel1__bit22 22 +#define R_SDRAM_CONFIG__bank_sel1__bit23 23 +#define R_SDRAM_CONFIG__bank_sel1__bit24 24 +#define R_SDRAM_CONFIG__bank_sel1__bit25 25 +#define R_SDRAM_CONFIG__bank_sel1__bit26 26 +#define R_SDRAM_CONFIG__bank_sel1__bit27 27 +#define R_SDRAM_CONFIG__bank_sel1__bit28 28 +#define R_SDRAM_CONFIG__bank_sel1__bit29 29 +#define R_SDRAM_CONFIG__ca0__BITNR 5 +#define R_SDRAM_CONFIG__ca0__WIDTH 3 +#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 +#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 +#define R_SDRAM_CONFIG__bank_sel0__bit9 9 +#define R_SDRAM_CONFIG__bank_sel0__bit10 10 +#define R_SDRAM_CONFIG__bank_sel0__bit11 11 +#define R_SDRAM_CONFIG__bank_sel0__bit12 12 +#define R_SDRAM_CONFIG__bank_sel0__bit13 13 +#define R_SDRAM_CONFIG__bank_sel0__bit14 14 +#define R_SDRAM_CONFIG__bank_sel0__bit15 15 +#define R_SDRAM_CONFIG__bank_sel0__bit16 16 +#define R_SDRAM_CONFIG__bank_sel0__bit17 17 +#define R_SDRAM_CONFIG__bank_sel0__bit18 18 +#define R_SDRAM_CONFIG__bank_sel0__bit19 19 +#define R_SDRAM_CONFIG__bank_sel0__bit20 20 +#define R_SDRAM_CONFIG__bank_sel0__bit21 21 +#define R_SDRAM_CONFIG__bank_sel0__bit22 22 +#define R_SDRAM_CONFIG__bank_sel0__bit23 23 +#define R_SDRAM_CONFIG__bank_sel0__bit24 24 +#define R_SDRAM_CONFIG__bank_sel0__bit25 25 +#define R_SDRAM_CONFIG__bank_sel0__bit26 26 +#define R_SDRAM_CONFIG__bank_sel0__bit27 27 +#define R_SDRAM_CONFIG__bank_sel0__bit28 28 +#define R_SDRAM_CONFIG__bank_sel0__bit29 29 + +/* +!* External DMA registers +!*/ + +#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) +#define R_EXT_DMA_0_CMD__cnt__BITNR 23 +#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 +#define R_EXT_DMA_0_CMD__cnt__enable 1 +#define R_EXT_DMA_0_CMD__cnt__disable 0 +#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 +#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 +#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 +#define R_EXT_DMA_0_CMD__rqpol__alow 1 +#define R_EXT_DMA_0_CMD__apol__BITNR 21 +#define R_EXT_DMA_0_CMD__apol__WIDTH 1 +#define R_EXT_DMA_0_CMD__apol__ahigh 0 +#define R_EXT_DMA_0_CMD__apol__alow 1 +#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 +#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 +#define R_EXT_DMA_0_CMD__rq_ack__burst 0 +#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 +#define R_EXT_DMA_0_CMD__wid__BITNR 18 +#define R_EXT_DMA_0_CMD__wid__WIDTH 2 +#define R_EXT_DMA_0_CMD__wid__byte 0 +#define R_EXT_DMA_0_CMD__wid__word 1 +#define R_EXT_DMA_0_CMD__wid__dword 2 +#define R_EXT_DMA_0_CMD__dir__BITNR 17 +#define R_EXT_DMA_0_CMD__dir__WIDTH 1 +#define R_EXT_DMA_0_CMD__dir__input 0 +#define R_EXT_DMA_0_CMD__dir__output 1 +#define R_EXT_DMA_0_CMD__run__BITNR 16 +#define R_EXT_DMA_0_CMD__run__WIDTH 1 +#define R_EXT_DMA_0_CMD__run__start 1 +#define R_EXT_DMA_0_CMD__run__stop 0 +#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 +#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 + +#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) +#define R_EXT_DMA_0_STAT__run__BITNR 16 +#define R_EXT_DMA_0_STAT__run__WIDTH 1 +#define R_EXT_DMA_0_STAT__run__start 1 +#define R_EXT_DMA_0_STAT__run__stop 0 +#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 +#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 + +#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) +#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 +#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 + +#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) +#define R_EXT_DMA_1_CMD__cnt__BITNR 23 +#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 +#define R_EXT_DMA_1_CMD__cnt__enable 1 +#define R_EXT_DMA_1_CMD__cnt__disable 0 +#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 +#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 +#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 +#define R_EXT_DMA_1_CMD__rqpol__alow 1 +#define R_EXT_DMA_1_CMD__apol__BITNR 21 +#define R_EXT_DMA_1_CMD__apol__WIDTH 1 +#define R_EXT_DMA_1_CMD__apol__ahigh 0 +#define R_EXT_DMA_1_CMD__apol__alow 1 +#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 +#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 +#define R_EXT_DMA_1_CMD__rq_ack__burst 0 +#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 +#define R_EXT_DMA_1_CMD__wid__BITNR 18 +#define R_EXT_DMA_1_CMD__wid__WIDTH 2 +#define R_EXT_DMA_1_CMD__wid__byte 0 +#define R_EXT_DMA_1_CMD__wid__word 1 +#define R_EXT_DMA_1_CMD__wid__dword 2 +#define R_EXT_DMA_1_CMD__dir__BITNR 17 +#define R_EXT_DMA_1_CMD__dir__WIDTH 1 +#define R_EXT_DMA_1_CMD__dir__input 0 +#define R_EXT_DMA_1_CMD__dir__output 1 +#define R_EXT_DMA_1_CMD__run__BITNR 16 +#define R_EXT_DMA_1_CMD__run__WIDTH 1 +#define R_EXT_DMA_1_CMD__run__start 1 +#define R_EXT_DMA_1_CMD__run__stop 0 +#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 +#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 + +#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) +#define R_EXT_DMA_1_STAT__run__BITNR 16 +#define R_EXT_DMA_1_STAT__run__WIDTH 1 +#define R_EXT_DMA_1_STAT__run__start 1 +#define R_EXT_DMA_1_STAT__run__stop 0 +#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 +#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 + +#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) +#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 +#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 + +/* +!* Timer registers +!*/ + +#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) +#define R_TIMER_CTRL__timerdiv1__BITNR 24 +#define R_TIMER_CTRL__timerdiv1__WIDTH 8 +#define R_TIMER_CTRL__timerdiv0__BITNR 16 +#define R_TIMER_CTRL__timerdiv0__WIDTH 8 +#define R_TIMER_CTRL__presc_timer1__BITNR 15 +#define R_TIMER_CTRL__presc_timer1__WIDTH 1 +#define R_TIMER_CTRL__presc_timer1__normal 0 +#define R_TIMER_CTRL__presc_timer1__prescale 1 +#define R_TIMER_CTRL__i1__BITNR 14 +#define R_TIMER_CTRL__i1__WIDTH 1 +#define R_TIMER_CTRL__i1__clr 1 +#define R_TIMER_CTRL__i1__nop 0 +#define R_TIMER_CTRL__tm1__BITNR 12 +#define R_TIMER_CTRL__tm1__WIDTH 2 +#define R_TIMER_CTRL__tm1__stop_ld 0 +#define R_TIMER_CTRL__tm1__freeze 1 +#define R_TIMER_CTRL__tm1__run 2 +#define R_TIMER_CTRL__tm1__reserved 3 +#define R_TIMER_CTRL__clksel1__BITNR 8 +#define R_TIMER_CTRL__clksel1__WIDTH 4 +#define R_TIMER_CTRL__clksel1__c300Hz 0 +#define R_TIMER_CTRL__clksel1__c600Hz 1 +#define R_TIMER_CTRL__clksel1__c1200Hz 2 +#define R_TIMER_CTRL__clksel1__c2400Hz 3 +#define R_TIMER_CTRL__clksel1__c4800Hz 4 +#define R_TIMER_CTRL__clksel1__c9600Hz 5 +#define R_TIMER_CTRL__clksel1__c19k2Hz 6 +#define R_TIMER_CTRL__clksel1__c38k4Hz 7 +#define R_TIMER_CTRL__clksel1__c57k6Hz 8 +#define R_TIMER_CTRL__clksel1__c115k2Hz 9 +#define R_TIMER_CTRL__clksel1__c230k4Hz 10 +#define R_TIMER_CTRL__clksel1__c460k8Hz 11 +#define R_TIMER_CTRL__clksel1__c921k6Hz 12 +#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 +#define R_TIMER_CTRL__clksel1__c6250kHz 14 +#define R_TIMER_CTRL__clksel1__cascade0 15 +#define R_TIMER_CTRL__presc_ext__BITNR 7 +#define R_TIMER_CTRL__presc_ext__WIDTH 1 +#define R_TIMER_CTRL__presc_ext__prescale 0 +#define R_TIMER_CTRL__presc_ext__external 1 +#define R_TIMER_CTRL__i0__BITNR 6 +#define R_TIMER_CTRL__i0__WIDTH 1 +#define R_TIMER_CTRL__i0__clr 1 +#define R_TIMER_CTRL__i0__nop 0 +#define R_TIMER_CTRL__tm0__BITNR 4 +#define R_TIMER_CTRL__tm0__WIDTH 2 +#define R_TIMER_CTRL__tm0__stop_ld 0 +#define R_TIMER_CTRL__tm0__freeze 1 +#define R_TIMER_CTRL__tm0__run 2 +#define R_TIMER_CTRL__tm0__reserved 3 +#define R_TIMER_CTRL__clksel0__BITNR 0 +#define R_TIMER_CTRL__clksel0__WIDTH 4 +#define R_TIMER_CTRL__clksel0__c300Hz 0 +#define R_TIMER_CTRL__clksel0__c600Hz 1 +#define R_TIMER_CTRL__clksel0__c1200Hz 2 +#define R_TIMER_CTRL__clksel0__c2400Hz 3 +#define R_TIMER_CTRL__clksel0__c4800Hz 4 +#define R_TIMER_CTRL__clksel0__c9600Hz 5 +#define R_TIMER_CTRL__clksel0__c19k2Hz 6 +#define R_TIMER_CTRL__clksel0__c38k4Hz 7 +#define R_TIMER_CTRL__clksel0__c57k6Hz 8 +#define R_TIMER_CTRL__clksel0__c115k2Hz 9 +#define R_TIMER_CTRL__clksel0__c230k4Hz 10 +#define R_TIMER_CTRL__clksel0__c460k8Hz 11 +#define R_TIMER_CTRL__clksel0__c921k6Hz 12 +#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 +#define R_TIMER_CTRL__clksel0__c6250kHz 14 +#define R_TIMER_CTRL__clksel0__flexible 15 + +#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) +#define R_TIMER_DATA__timer1__BITNR 24 +#define R_TIMER_DATA__timer1__WIDTH 8 +#define R_TIMER_DATA__timer0__BITNR 16 +#define R_TIMER_DATA__timer0__WIDTH 8 +#define R_TIMER_DATA__clkdiv_high__BITNR 8 +#define R_TIMER_DATA__clkdiv_high__WIDTH 8 +#define R_TIMER_DATA__clkdiv_low__BITNR 0 +#define R_TIMER_DATA__clkdiv_low__WIDTH 8 + +#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) +#define R_TIMER01_DATA__count__BITNR 0 +#define R_TIMER01_DATA__count__WIDTH 16 + +#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) +#define R_TIMER0_DATA__count__BITNR 0 +#define R_TIMER0_DATA__count__WIDTH 8 + +#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) +#define R_TIMER1_DATA__count__BITNR 0 +#define R_TIMER1_DATA__count__WIDTH 8 + +#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) +#define R_WATCHDOG__key__BITNR 1 +#define R_WATCHDOG__key__WIDTH 3 +#define R_WATCHDOG__enable__BITNR 0 +#define R_WATCHDOG__enable__WIDTH 1 +#define R_WATCHDOG__enable__stop 0 +#define R_WATCHDOG__enable__start 1 + +#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) +#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 +#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 +#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 +#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 + +#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) +#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 +#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 + +#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) +#define R_TIMER_PRESCALE__tim_presc__BITNR 0 +#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 + +#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) +#define R_PRESCALE_STATUS__ser_status__BITNR 16 +#define R_PRESCALE_STATUS__ser_status__WIDTH 16 +#define R_PRESCALE_STATUS__tim_status__BITNR 0 +#define R_PRESCALE_STATUS__tim_status__WIDTH 16 + +#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) +#define R_SER_PRESC_STATUS__ser_status__BITNR 0 +#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 + +#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) +#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 +#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 + +#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 +#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 +#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 +#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 +#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 +#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 +#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 + +/* +!* Shared RAM interface registers +!*/ + +#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) +#define R_SHARED_RAM_CONFIG__width__BITNR 3 +#define R_SHARED_RAM_CONFIG__width__WIDTH 1 +#define R_SHARED_RAM_CONFIG__width__byte 0 +#define R_SHARED_RAM_CONFIG__width__word 1 +#define R_SHARED_RAM_CONFIG__enable__BITNR 2 +#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 +#define R_SHARED_RAM_CONFIG__enable__yes 1 +#define R_SHARED_RAM_CONFIG__enable__no 0 +#define R_SHARED_RAM_CONFIG__pint__BITNR 1 +#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 +#define R_SHARED_RAM_CONFIG__pint__int 1 +#define R_SHARED_RAM_CONFIG__pint__nop 0 +#define R_SHARED_RAM_CONFIG__clri__BITNR 0 +#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 +#define R_SHARED_RAM_CONFIG__clri__clr 1 +#define R_SHARED_RAM_CONFIG__clri__nop 0 + +#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) +#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 +#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 + +/* +!* General config registers +!*/ + +#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) +#define R_GEN_CONFIG__par_w__BITNR 31 +#define R_GEN_CONFIG__par_w__WIDTH 1 +#define R_GEN_CONFIG__par_w__select 1 +#define R_GEN_CONFIG__par_w__disable 0 +#define R_GEN_CONFIG__usb2__BITNR 30 +#define R_GEN_CONFIG__usb2__WIDTH 1 +#define R_GEN_CONFIG__usb2__select 1 +#define R_GEN_CONFIG__usb2__disable 0 +#define R_GEN_CONFIG__usb1__BITNR 29 +#define R_GEN_CONFIG__usb1__WIDTH 1 +#define R_GEN_CONFIG__usb1__select 1 +#define R_GEN_CONFIG__usb1__disable 0 +#define R_GEN_CONFIG__g24dir__BITNR 27 +#define R_GEN_CONFIG__g24dir__WIDTH 1 +#define R_GEN_CONFIG__g24dir__in 0 +#define R_GEN_CONFIG__g24dir__out 1 +#define R_GEN_CONFIG__g16_23dir__BITNR 26 +#define R_GEN_CONFIG__g16_23dir__WIDTH 1 +#define R_GEN_CONFIG__g16_23dir__in 0 +#define R_GEN_CONFIG__g16_23dir__out 1 +#define R_GEN_CONFIG__g8_15dir__BITNR 25 +#define R_GEN_CONFIG__g8_15dir__WIDTH 1 +#define R_GEN_CONFIG__g8_15dir__in 0 +#define R_GEN_CONFIG__g8_15dir__out 1 +#define R_GEN_CONFIG__g0dir__BITNR 24 +#define R_GEN_CONFIG__g0dir__WIDTH 1 +#define R_GEN_CONFIG__g0dir__in 0 +#define R_GEN_CONFIG__g0dir__out 1 +#define R_GEN_CONFIG__dma9__BITNR 23 +#define R_GEN_CONFIG__dma9__WIDTH 1 +#define R_GEN_CONFIG__dma9__usb 0 +#define R_GEN_CONFIG__dma9__serial1 1 +#define R_GEN_CONFIG__dma8__BITNR 22 +#define R_GEN_CONFIG__dma8__WIDTH 1 +#define R_GEN_CONFIG__dma8__usb 0 +#define R_GEN_CONFIG__dma8__serial1 1 +#define R_GEN_CONFIG__dma7__BITNR 20 +#define R_GEN_CONFIG__dma7__WIDTH 2 +#define R_GEN_CONFIG__dma7__unused 0 +#define R_GEN_CONFIG__dma7__serial0 1 +#define R_GEN_CONFIG__dma7__extdma1 2 +#define R_GEN_CONFIG__dma7__intdma6 3 +#define R_GEN_CONFIG__dma6__BITNR 18 +#define R_GEN_CONFIG__dma6__WIDTH 2 +#define R_GEN_CONFIG__dma6__unused 0 +#define R_GEN_CONFIG__dma6__serial0 1 +#define R_GEN_CONFIG__dma6__extdma1 2 +#define R_GEN_CONFIG__dma6__intdma7 3 +#define R_GEN_CONFIG__dma5__BITNR 16 +#define R_GEN_CONFIG__dma5__WIDTH 2 +#define R_GEN_CONFIG__dma5__par1 0 +#define R_GEN_CONFIG__dma5__scsi1 1 +#define R_GEN_CONFIG__dma5__serial3 2 +#define R_GEN_CONFIG__dma5__extdma0 3 +#define R_GEN_CONFIG__dma4__BITNR 14 +#define R_GEN_CONFIG__dma4__WIDTH 2 +#define R_GEN_CONFIG__dma4__par1 0 +#define R_GEN_CONFIG__dma4__scsi1 1 +#define R_GEN_CONFIG__dma4__serial3 2 +#define R_GEN_CONFIG__dma4__extdma0 3 +#define R_GEN_CONFIG__dma3__BITNR 12 +#define R_GEN_CONFIG__dma3__WIDTH 2 +#define R_GEN_CONFIG__dma3__par0 0 +#define R_GEN_CONFIG__dma3__scsi0 1 +#define R_GEN_CONFIG__dma3__serial2 2 +#define R_GEN_CONFIG__dma3__ata 3 +#define R_GEN_CONFIG__dma2__BITNR 10 +#define R_GEN_CONFIG__dma2__WIDTH 2 +#define R_GEN_CONFIG__dma2__par0 0 +#define R_GEN_CONFIG__dma2__scsi0 1 +#define R_GEN_CONFIG__dma2__serial2 2 +#define R_GEN_CONFIG__dma2__ata 3 +#define R_GEN_CONFIG__mio_w__BITNR 9 +#define R_GEN_CONFIG__mio_w__WIDTH 1 +#define R_GEN_CONFIG__mio_w__select 1 +#define R_GEN_CONFIG__mio_w__disable 0 +#define R_GEN_CONFIG__ser3__BITNR 8 +#define R_GEN_CONFIG__ser3__WIDTH 1 +#define R_GEN_CONFIG__ser3__select 1 +#define R_GEN_CONFIG__ser3__disable 0 +#define R_GEN_CONFIG__par1__BITNR 7 +#define R_GEN_CONFIG__par1__WIDTH 1 +#define R_GEN_CONFIG__par1__select 1 +#define R_GEN_CONFIG__par1__disable 0 +#define R_GEN_CONFIG__scsi0w__BITNR 6 +#define R_GEN_CONFIG__scsi0w__WIDTH 1 +#define R_GEN_CONFIG__scsi0w__select 1 +#define R_GEN_CONFIG__scsi0w__disable 0 +#define R_GEN_CONFIG__scsi1__BITNR 5 +#define R_GEN_CONFIG__scsi1__WIDTH 1 +#define R_GEN_CONFIG__scsi1__select 1 +#define R_GEN_CONFIG__scsi1__disable 0 +#define R_GEN_CONFIG__mio__BITNR 4 +#define R_GEN_CONFIG__mio__WIDTH 1 +#define R_GEN_CONFIG__mio__select 1 +#define R_GEN_CONFIG__mio__disable 0 +#define R_GEN_CONFIG__ser2__BITNR 3 +#define R_GEN_CONFIG__ser2__WIDTH 1 +#define R_GEN_CONFIG__ser2__select 1 +#define R_GEN_CONFIG__ser2__disable 0 +#define R_GEN_CONFIG__par0__BITNR 2 +#define R_GEN_CONFIG__par0__WIDTH 1 +#define R_GEN_CONFIG__par0__select 1 +#define R_GEN_CONFIG__par0__disable 0 +#define R_GEN_CONFIG__ata__BITNR 1 +#define R_GEN_CONFIG__ata__WIDTH 1 +#define R_GEN_CONFIG__ata__select 1 +#define R_GEN_CONFIG__ata__disable 0 +#define R_GEN_CONFIG__scsi0__BITNR 0 +#define R_GEN_CONFIG__scsi0__WIDTH 1 +#define R_GEN_CONFIG__scsi0__select 1 +#define R_GEN_CONFIG__scsi0__disable 0 + +#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) +#define R_GEN_CONFIG_II__sermode3__BITNR 6 +#define R_GEN_CONFIG_II__sermode3__WIDTH 1 +#define R_GEN_CONFIG_II__sermode3__async 0 +#define R_GEN_CONFIG_II__sermode3__sync 1 +#define R_GEN_CONFIG_II__sermode1__BITNR 4 +#define R_GEN_CONFIG_II__sermode1__WIDTH 1 +#define R_GEN_CONFIG_II__sermode1__async 0 +#define R_GEN_CONFIG_II__sermode1__sync 1 +#define R_GEN_CONFIG_II__ext_clk__BITNR 2 +#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 +#define R_GEN_CONFIG_II__ext_clk__select 1 +#define R_GEN_CONFIG_II__ext_clk__disable 0 +#define R_GEN_CONFIG_II__ser2__BITNR 1 +#define R_GEN_CONFIG_II__ser2__WIDTH 1 +#define R_GEN_CONFIG_II__ser2__select 1 +#define R_GEN_CONFIG_II__ser2__disable 0 +#define R_GEN_CONFIG_II__ser3__BITNR 0 +#define R_GEN_CONFIG_II__ser3__WIDTH 1 +#define R_GEN_CONFIG_II__ser3__select 1 +#define R_GEN_CONFIG_II__ser3__disable 0 + +#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) +#define R_PORT_G_DATA__data__BITNR 0 +#define R_PORT_G_DATA__data__WIDTH 32 + +/* +!* General port configuration registers +!*/ + +#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) +#define R_PORT_PA_SET__dir7__BITNR 15 +#define R_PORT_PA_SET__dir7__WIDTH 1 +#define R_PORT_PA_SET__dir7__input 0 +#define R_PORT_PA_SET__dir7__output 1 +#define R_PORT_PA_SET__dir6__BITNR 14 +#define R_PORT_PA_SET__dir6__WIDTH 1 +#define R_PORT_PA_SET__dir6__input 0 +#define R_PORT_PA_SET__dir6__output 1 +#define R_PORT_PA_SET__dir5__BITNR 13 +#define R_PORT_PA_SET__dir5__WIDTH 1 +#define R_PORT_PA_SET__dir5__input 0 +#define R_PORT_PA_SET__dir5__output 1 +#define R_PORT_PA_SET__dir4__BITNR 12 +#define R_PORT_PA_SET__dir4__WIDTH 1 +#define R_PORT_PA_SET__dir4__input 0 +#define R_PORT_PA_SET__dir4__output 1 +#define R_PORT_PA_SET__dir3__BITNR 11 +#define R_PORT_PA_SET__dir3__WIDTH 1 +#define R_PORT_PA_SET__dir3__input 0 +#define R_PORT_PA_SET__dir3__output 1 +#define R_PORT_PA_SET__dir2__BITNR 10 +#define R_PORT_PA_SET__dir2__WIDTH 1 +#define R_PORT_PA_SET__dir2__input 0 +#define R_PORT_PA_SET__dir2__output 1 +#define R_PORT_PA_SET__dir1__BITNR 9 +#define R_PORT_PA_SET__dir1__WIDTH 1 +#define R_PORT_PA_SET__dir1__input 0 +#define R_PORT_PA_SET__dir1__output 1 +#define R_PORT_PA_SET__dir0__BITNR 8 +#define R_PORT_PA_SET__dir0__WIDTH 1 +#define R_PORT_PA_SET__dir0__input 0 +#define R_PORT_PA_SET__dir0__output 1 +#define R_PORT_PA_SET__data_out__BITNR 0 +#define R_PORT_PA_SET__data_out__WIDTH 8 + +#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) +#define R_PORT_PA_DATA__data_out__BITNR 0 +#define R_PORT_PA_DATA__data_out__WIDTH 8 + +#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) +#define R_PORT_PA_DIR__dir7__BITNR 7 +#define R_PORT_PA_DIR__dir7__WIDTH 1 +#define R_PORT_PA_DIR__dir7__input 0 +#define R_PORT_PA_DIR__dir7__output 1 +#define R_PORT_PA_DIR__dir6__BITNR 6 +#define R_PORT_PA_DIR__dir6__WIDTH 1 +#define R_PORT_PA_DIR__dir6__input 0 +#define R_PORT_PA_DIR__dir6__output 1 +#define R_PORT_PA_DIR__dir5__BITNR 5 +#define R_PORT_PA_DIR__dir5__WIDTH 1 +#define R_PORT_PA_DIR__dir5__input 0 +#define R_PORT_PA_DIR__dir5__output 1 +#define R_PORT_PA_DIR__dir4__BITNR 4 +#define R_PORT_PA_DIR__dir4__WIDTH 1 +#define R_PORT_PA_DIR__dir4__input 0 +#define R_PORT_PA_DIR__dir4__output 1 +#define R_PORT_PA_DIR__dir3__BITNR 3 +#define R_PORT_PA_DIR__dir3__WIDTH 1 +#define R_PORT_PA_DIR__dir3__input 0 +#define R_PORT_PA_DIR__dir3__output 1 +#define R_PORT_PA_DIR__dir2__BITNR 2 +#define R_PORT_PA_DIR__dir2__WIDTH 1 +#define R_PORT_PA_DIR__dir2__input 0 +#define R_PORT_PA_DIR__dir2__output 1 +#define R_PORT_PA_DIR__dir1__BITNR 1 +#define R_PORT_PA_DIR__dir1__WIDTH 1 +#define R_PORT_PA_DIR__dir1__input 0 +#define R_PORT_PA_DIR__dir1__output 1 +#define R_PORT_PA_DIR__dir0__BITNR 0 +#define R_PORT_PA_DIR__dir0__WIDTH 1 +#define R_PORT_PA_DIR__dir0__input 0 +#define R_PORT_PA_DIR__dir0__output 1 + +#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) +#define R_PORT_PA_READ__data_in__BITNR 0 +#define R_PORT_PA_READ__data_in__WIDTH 8 + +#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) +#define R_PORT_PB_SET__syncser3__BITNR 29 +#define R_PORT_PB_SET__syncser3__WIDTH 1 +#define R_PORT_PB_SET__syncser3__port_cs 0 +#define R_PORT_PB_SET__syncser3__ss3extra 1 +#define R_PORT_PB_SET__syncser1__BITNR 28 +#define R_PORT_PB_SET__syncser1__WIDTH 1 +#define R_PORT_PB_SET__syncser1__port_cs 0 +#define R_PORT_PB_SET__syncser1__ss1extra 1 +#define R_PORT_PB_SET__i2c_en__BITNR 27 +#define R_PORT_PB_SET__i2c_en__WIDTH 1 +#define R_PORT_PB_SET__i2c_en__off 0 +#define R_PORT_PB_SET__i2c_en__on 1 +#define R_PORT_PB_SET__i2c_d__BITNR 26 +#define R_PORT_PB_SET__i2c_d__WIDTH 1 +#define R_PORT_PB_SET__i2c_clk__BITNR 25 +#define R_PORT_PB_SET__i2c_clk__WIDTH 1 +#define R_PORT_PB_SET__i2c_oe___BITNR 24 +#define R_PORT_PB_SET__i2c_oe___WIDTH 1 +#define R_PORT_PB_SET__i2c_oe___enable 0 +#define R_PORT_PB_SET__i2c_oe___disable 1 +#define R_PORT_PB_SET__cs7__BITNR 23 +#define R_PORT_PB_SET__cs7__WIDTH 1 +#define R_PORT_PB_SET__cs7__port 0 +#define R_PORT_PB_SET__cs7__cs 1 +#define R_PORT_PB_SET__cs6__BITNR 22 +#define R_PORT_PB_SET__cs6__WIDTH 1 +#define R_PORT_PB_SET__cs6__port 0 +#define R_PORT_PB_SET__cs6__cs 1 +#define R_PORT_PB_SET__cs5__BITNR 21 +#define R_PORT_PB_SET__cs5__WIDTH 1 +#define R_PORT_PB_SET__cs5__port 0 +#define R_PORT_PB_SET__cs5__cs 1 +#define R_PORT_PB_SET__cs4__BITNR 20 +#define R_PORT_PB_SET__cs4__WIDTH 1 +#define R_PORT_PB_SET__cs4__port 0 +#define R_PORT_PB_SET__cs4__cs 1 +#define R_PORT_PB_SET__cs3__BITNR 19 +#define R_PORT_PB_SET__cs3__WIDTH 1 +#define R_PORT_PB_SET__cs3__port 0 +#define R_PORT_PB_SET__cs3__cs 1 +#define R_PORT_PB_SET__cs2__BITNR 18 +#define R_PORT_PB_SET__cs2__WIDTH 1 +#define R_PORT_PB_SET__cs2__port 0 +#define R_PORT_PB_SET__cs2__cs 1 +#define R_PORT_PB_SET__scsi1__BITNR 17 +#define R_PORT_PB_SET__scsi1__WIDTH 1 +#define R_PORT_PB_SET__scsi1__port_cs 0 +#define R_PORT_PB_SET__scsi1__enph 1 +#define R_PORT_PB_SET__scsi0__BITNR 16 +#define R_PORT_PB_SET__scsi0__WIDTH 1 +#define R_PORT_PB_SET__scsi0__port_cs 0 +#define R_PORT_PB_SET__scsi0__enph 1 +#define R_PORT_PB_SET__dir7__BITNR 15 +#define R_PORT_PB_SET__dir7__WIDTH 1 +#define R_PORT_PB_SET__dir7__input 0 +#define R_PORT_PB_SET__dir7__output 1 +#define R_PORT_PB_SET__dir6__BITNR 14 +#define R_PORT_PB_SET__dir6__WIDTH 1 +#define R_PORT_PB_SET__dir6__input 0 +#define R_PORT_PB_SET__dir6__output 1 +#define R_PORT_PB_SET__dir5__BITNR 13 +#define R_PORT_PB_SET__dir5__WIDTH 1 +#define R_PORT_PB_SET__dir5__input 0 +#define R_PORT_PB_SET__dir5__output 1 +#define R_PORT_PB_SET__dir4__BITNR 12 +#define R_PORT_PB_SET__dir4__WIDTH 1 +#define R_PORT_PB_SET__dir4__input 0 +#define R_PORT_PB_SET__dir4__output 1 +#define R_PORT_PB_SET__dir3__BITNR 11 +#define R_PORT_PB_SET__dir3__WIDTH 1 +#define R_PORT_PB_SET__dir3__input 0 +#define R_PORT_PB_SET__dir3__output 1 +#define R_PORT_PB_SET__dir2__BITNR 10 +#define R_PORT_PB_SET__dir2__WIDTH 1 +#define R_PORT_PB_SET__dir2__input 0 +#define R_PORT_PB_SET__dir2__output 1 +#define R_PORT_PB_SET__dir1__BITNR 9 +#define R_PORT_PB_SET__dir1__WIDTH 1 +#define R_PORT_PB_SET__dir1__input 0 +#define R_PORT_PB_SET__dir1__output 1 +#define R_PORT_PB_SET__dir0__BITNR 8 +#define R_PORT_PB_SET__dir0__WIDTH 1 +#define R_PORT_PB_SET__dir0__input 0 +#define R_PORT_PB_SET__dir0__output 1 +#define R_PORT_PB_SET__data_out__BITNR 0 +#define R_PORT_PB_SET__data_out__WIDTH 8 + +#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) +#define R_PORT_PB_DATA__data_out__BITNR 0 +#define R_PORT_PB_DATA__data_out__WIDTH 8 + +#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) +#define R_PORT_PB_DIR__dir7__BITNR 7 +#define R_PORT_PB_DIR__dir7__WIDTH 1 +#define R_PORT_PB_DIR__dir7__input 0 +#define R_PORT_PB_DIR__dir7__output 1 +#define R_PORT_PB_DIR__dir6__BITNR 6 +#define R_PORT_PB_DIR__dir6__WIDTH 1 +#define R_PORT_PB_DIR__dir6__input 0 +#define R_PORT_PB_DIR__dir6__output 1 +#define R_PORT_PB_DIR__dir5__BITNR 5 +#define R_PORT_PB_DIR__dir5__WIDTH 1 +#define R_PORT_PB_DIR__dir5__input 0 +#define R_PORT_PB_DIR__dir5__output 1 +#define R_PORT_PB_DIR__dir4__BITNR 4 +#define R_PORT_PB_DIR__dir4__WIDTH 1 +#define R_PORT_PB_DIR__dir4__input 0 +#define R_PORT_PB_DIR__dir4__output 1 +#define R_PORT_PB_DIR__dir3__BITNR 3 +#define R_PORT_PB_DIR__dir3__WIDTH 1 +#define R_PORT_PB_DIR__dir3__input 0 +#define R_PORT_PB_DIR__dir3__output 1 +#define R_PORT_PB_DIR__dir2__BITNR 2 +#define R_PORT_PB_DIR__dir2__WIDTH 1 +#define R_PORT_PB_DIR__dir2__input 0 +#define R_PORT_PB_DIR__dir2__output 1 +#define R_PORT_PB_DIR__dir1__BITNR 1 +#define R_PORT_PB_DIR__dir1__WIDTH 1 +#define R_PORT_PB_DIR__dir1__input 0 +#define R_PORT_PB_DIR__dir1__output 1 +#define R_PORT_PB_DIR__dir0__BITNR 0 +#define R_PORT_PB_DIR__dir0__WIDTH 1 +#define R_PORT_PB_DIR__dir0__input 0 +#define R_PORT_PB_DIR__dir0__output 1 + +#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) +#define R_PORT_PB_CONFIG__cs7__BITNR 7 +#define R_PORT_PB_CONFIG__cs7__WIDTH 1 +#define R_PORT_PB_CONFIG__cs7__port 0 +#define R_PORT_PB_CONFIG__cs7__cs 1 +#define R_PORT_PB_CONFIG__cs6__BITNR 6 +#define R_PORT_PB_CONFIG__cs6__WIDTH 1 +#define R_PORT_PB_CONFIG__cs6__port 0 +#define R_PORT_PB_CONFIG__cs6__cs 1 +#define R_PORT_PB_CONFIG__cs5__BITNR 5 +#define R_PORT_PB_CONFIG__cs5__WIDTH 1 +#define R_PORT_PB_CONFIG__cs5__port 0 +#define R_PORT_PB_CONFIG__cs5__cs 1 +#define R_PORT_PB_CONFIG__cs4__BITNR 4 +#define R_PORT_PB_CONFIG__cs4__WIDTH 1 +#define R_PORT_PB_CONFIG__cs4__port 0 +#define R_PORT_PB_CONFIG__cs4__cs 1 +#define R_PORT_PB_CONFIG__cs3__BITNR 3 +#define R_PORT_PB_CONFIG__cs3__WIDTH 1 +#define R_PORT_PB_CONFIG__cs3__port 0 +#define R_PORT_PB_CONFIG__cs3__cs 1 +#define R_PORT_PB_CONFIG__cs2__BITNR 2 +#define R_PORT_PB_CONFIG__cs2__WIDTH 1 +#define R_PORT_PB_CONFIG__cs2__port 0 +#define R_PORT_PB_CONFIG__cs2__cs 1 +#define R_PORT_PB_CONFIG__scsi1__BITNR 1 +#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 +#define R_PORT_PB_CONFIG__scsi1__port_cs 0 +#define R_PORT_PB_CONFIG__scsi1__enph 1 +#define R_PORT_PB_CONFIG__scsi0__BITNR 0 +#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 +#define R_PORT_PB_CONFIG__scsi0__port_cs 0 +#define R_PORT_PB_CONFIG__scsi0__enph 1 + +#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) +#define R_PORT_PB_I2C__syncser3__BITNR 5 +#define R_PORT_PB_I2C__syncser3__WIDTH 1 +#define R_PORT_PB_I2C__syncser3__port_cs 0 +#define R_PORT_PB_I2C__syncser3__ss3extra 1 +#define R_PORT_PB_I2C__syncser1__BITNR 4 +#define R_PORT_PB_I2C__syncser1__WIDTH 1 +#define R_PORT_PB_I2C__syncser1__port_cs 0 +#define R_PORT_PB_I2C__syncser1__ss1extra 1 +#define R_PORT_PB_I2C__i2c_en__BITNR 3 +#define R_PORT_PB_I2C__i2c_en__WIDTH 1 +#define R_PORT_PB_I2C__i2c_en__off 0 +#define R_PORT_PB_I2C__i2c_en__on 1 +#define R_PORT_PB_I2C__i2c_d__BITNR 2 +#define R_PORT_PB_I2C__i2c_d__WIDTH 1 +#define R_PORT_PB_I2C__i2c_clk__BITNR 1 +#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 +#define R_PORT_PB_I2C__i2c_oe___BITNR 0 +#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 +#define R_PORT_PB_I2C__i2c_oe___enable 0 +#define R_PORT_PB_I2C__i2c_oe___disable 1 + +#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) +#define R_PORT_PB_READ__data_in__BITNR 0 +#define R_PORT_PB_READ__data_in__WIDTH 8 + +/* +!* Serial port registers +!*/ + +#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) +#define R_SERIAL0_CTRL__tr_baud__BITNR 28 +#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL0_CTRL__tr_baud__reserved 15 +#define R_SERIAL0_CTRL__rec_baud__BITNR 24 +#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL0_CTRL__rec_baud__reserved 15 +#define R_SERIAL0_CTRL__dma_err__BITNR 23 +#define R_SERIAL0_CTRL__dma_err__WIDTH 1 +#define R_SERIAL0_CTRL__dma_err__stop 0 +#define R_SERIAL0_CTRL__dma_err__ignore 1 +#define R_SERIAL0_CTRL__rec_enable__BITNR 22 +#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL0_CTRL__rec_enable__disable 0 +#define R_SERIAL0_CTRL__rec_enable__enable 1 +#define R_SERIAL0_CTRL__rts___BITNR 21 +#define R_SERIAL0_CTRL__rts___WIDTH 1 +#define R_SERIAL0_CTRL__rts___active 0 +#define R_SERIAL0_CTRL__rts___inactive 1 +#define R_SERIAL0_CTRL__sampling__BITNR 20 +#define R_SERIAL0_CTRL__sampling__WIDTH 1 +#define R_SERIAL0_CTRL__sampling__middle 0 +#define R_SERIAL0_CTRL__sampling__majority 1 +#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL0_CTRL__rec_stick_par__normal 0 +#define R_SERIAL0_CTRL__rec_stick_par__stick 1 +#define R_SERIAL0_CTRL__rec_par__BITNR 18 +#define R_SERIAL0_CTRL__rec_par__WIDTH 1 +#define R_SERIAL0_CTRL__rec_par__even 0 +#define R_SERIAL0_CTRL__rec_par__odd 1 +#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL0_CTRL__rec_par_en__disable 0 +#define R_SERIAL0_CTRL__rec_par_en__enable 1 +#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL0_CTRL__txd__BITNR 15 +#define R_SERIAL0_CTRL__txd__WIDTH 1 +#define R_SERIAL0_CTRL__tr_enable__BITNR 14 +#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL0_CTRL__tr_enable__disable 0 +#define R_SERIAL0_CTRL__tr_enable__enable 1 +#define R_SERIAL0_CTRL__auto_cts__BITNR 13 +#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL0_CTRL__auto_cts__disabled 0 +#define R_SERIAL0_CTRL__auto_cts__active 1 +#define R_SERIAL0_CTRL__stop_bits__BITNR 12 +#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL0_CTRL__stop_bits__one_bit 0 +#define R_SERIAL0_CTRL__stop_bits__two_bits 1 +#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL0_CTRL__tr_stick_par__normal 0 +#define R_SERIAL0_CTRL__tr_stick_par__stick 1 +#define R_SERIAL0_CTRL__tr_par__BITNR 10 +#define R_SERIAL0_CTRL__tr_par__WIDTH 1 +#define R_SERIAL0_CTRL__tr_par__even 0 +#define R_SERIAL0_CTRL__tr_par__odd 1 +#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL0_CTRL__tr_par_en__disable 0 +#define R_SERIAL0_CTRL__tr_par_en__enable 1 +#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL0_CTRL__data_out__BITNR 0 +#define R_SERIAL0_CTRL__data_out__WIDTH 8 + +#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) +#define R_SERIAL0_BAUD__tr_baud__BITNR 4 +#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL0_BAUD__tr_baud__reserved 15 +#define R_SERIAL0_BAUD__rec_baud__BITNR 0 +#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL0_BAUD__rec_baud__reserved 15 + +#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) +#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL0_REC_CTRL__dma_err__stop 0 +#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL0_REC_CTRL__rts___BITNR 5 +#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL0_REC_CTRL__rts___active 0 +#define R_SERIAL0_REC_CTRL__rts___inactive 1 +#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL0_REC_CTRL__sampling__middle 0 +#define R_SERIAL0_REC_CTRL__sampling__majority 1 +#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_par__even 0 +#define R_SERIAL0_REC_CTRL__rec_par__odd 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) +#define R_SERIAL0_TR_CTRL__txd__BITNR 7 +#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL0_TR_CTRL__auto_cts__active 1 +#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_par__even 0 +#define R_SERIAL0_TR_CTRL__tr_par__odd 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) +#define R_SERIAL0_TR_DATA__data_out__BITNR 0 +#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) +#define R_SERIAL0_READ__xoff_detect__BITNR 15 +#define R_SERIAL0_READ__xoff_detect__WIDTH 1 +#define R_SERIAL0_READ__xoff_detect__no_xoff 0 +#define R_SERIAL0_READ__xoff_detect__xoff 1 +#define R_SERIAL0_READ__cts___BITNR 14 +#define R_SERIAL0_READ__cts___WIDTH 1 +#define R_SERIAL0_READ__cts___active 0 +#define R_SERIAL0_READ__cts___inactive 1 +#define R_SERIAL0_READ__tr_ready__BITNR 13 +#define R_SERIAL0_READ__tr_ready__WIDTH 1 +#define R_SERIAL0_READ__tr_ready__full 0 +#define R_SERIAL0_READ__tr_ready__ready 1 +#define R_SERIAL0_READ__rxd__BITNR 12 +#define R_SERIAL0_READ__rxd__WIDTH 1 +#define R_SERIAL0_READ__overrun__BITNR 11 +#define R_SERIAL0_READ__overrun__WIDTH 1 +#define R_SERIAL0_READ__overrun__no 0 +#define R_SERIAL0_READ__overrun__yes 1 +#define R_SERIAL0_READ__par_err__BITNR 10 +#define R_SERIAL0_READ__par_err__WIDTH 1 +#define R_SERIAL0_READ__par_err__no 0 +#define R_SERIAL0_READ__par_err__yes 1 +#define R_SERIAL0_READ__framing_err__BITNR 9 +#define R_SERIAL0_READ__framing_err__WIDTH 1 +#define R_SERIAL0_READ__framing_err__no 0 +#define R_SERIAL0_READ__framing_err__yes 1 +#define R_SERIAL0_READ__data_avail__BITNR 8 +#define R_SERIAL0_READ__data_avail__WIDTH 1 +#define R_SERIAL0_READ__data_avail__no 0 +#define R_SERIAL0_READ__data_avail__yes 1 +#define R_SERIAL0_READ__data_in__BITNR 0 +#define R_SERIAL0_READ__data_in__WIDTH 8 + +#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) +#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL0_STATUS__xoff_detect__xoff 1 +#define R_SERIAL0_STATUS__cts___BITNR 6 +#define R_SERIAL0_STATUS__cts___WIDTH 1 +#define R_SERIAL0_STATUS__cts___active 0 +#define R_SERIAL0_STATUS__cts___inactive 1 +#define R_SERIAL0_STATUS__tr_ready__BITNR 5 +#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL0_STATUS__tr_ready__full 0 +#define R_SERIAL0_STATUS__tr_ready__ready 1 +#define R_SERIAL0_STATUS__rxd__BITNR 4 +#define R_SERIAL0_STATUS__rxd__WIDTH 1 +#define R_SERIAL0_STATUS__overrun__BITNR 3 +#define R_SERIAL0_STATUS__overrun__WIDTH 1 +#define R_SERIAL0_STATUS__overrun__no 0 +#define R_SERIAL0_STATUS__overrun__yes 1 +#define R_SERIAL0_STATUS__par_err__BITNR 2 +#define R_SERIAL0_STATUS__par_err__WIDTH 1 +#define R_SERIAL0_STATUS__par_err__no 0 +#define R_SERIAL0_STATUS__par_err__yes 1 +#define R_SERIAL0_STATUS__framing_err__BITNR 1 +#define R_SERIAL0_STATUS__framing_err__WIDTH 1 +#define R_SERIAL0_STATUS__framing_err__no 0 +#define R_SERIAL0_STATUS__framing_err__yes 1 +#define R_SERIAL0_STATUS__data_avail__BITNR 0 +#define R_SERIAL0_STATUS__data_avail__WIDTH 1 +#define R_SERIAL0_STATUS__data_avail__no 0 +#define R_SERIAL0_STATUS__data_avail__yes 1 + +#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) +#define R_SERIAL0_REC_DATA__data_in__BITNR 0 +#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) +#define R_SERIAL0_XOFF__tx_stop__BITNR 9 +#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL0_XOFF__tx_stop__enable 0 +#define R_SERIAL0_XOFF__tx_stop__stop 1 +#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL0_XOFF__auto_xoff__disable 0 +#define R_SERIAL0_XOFF__auto_xoff__enable 1 +#define R_SERIAL0_XOFF__xoff_char__BITNR 0 +#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) +#define R_SERIAL1_CTRL__tr_baud__BITNR 28 +#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL1_CTRL__tr_baud__reserved 15 +#define R_SERIAL1_CTRL__rec_baud__BITNR 24 +#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL1_CTRL__rec_baud__reserved 15 +#define R_SERIAL1_CTRL__dma_err__BITNR 23 +#define R_SERIAL1_CTRL__dma_err__WIDTH 1 +#define R_SERIAL1_CTRL__dma_err__stop 0 +#define R_SERIAL1_CTRL__dma_err__ignore 1 +#define R_SERIAL1_CTRL__rec_enable__BITNR 22 +#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL1_CTRL__rec_enable__disable 0 +#define R_SERIAL1_CTRL__rec_enable__enable 1 +#define R_SERIAL1_CTRL__rts___BITNR 21 +#define R_SERIAL1_CTRL__rts___WIDTH 1 +#define R_SERIAL1_CTRL__rts___active 0 +#define R_SERIAL1_CTRL__rts___inactive 1 +#define R_SERIAL1_CTRL__sampling__BITNR 20 +#define R_SERIAL1_CTRL__sampling__WIDTH 1 +#define R_SERIAL1_CTRL__sampling__middle 0 +#define R_SERIAL1_CTRL__sampling__majority 1 +#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL1_CTRL__rec_stick_par__normal 0 +#define R_SERIAL1_CTRL__rec_stick_par__stick 1 +#define R_SERIAL1_CTRL__rec_par__BITNR 18 +#define R_SERIAL1_CTRL__rec_par__WIDTH 1 +#define R_SERIAL1_CTRL__rec_par__even 0 +#define R_SERIAL1_CTRL__rec_par__odd 1 +#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL1_CTRL__rec_par_en__disable 0 +#define R_SERIAL1_CTRL__rec_par_en__enable 1 +#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL1_CTRL__txd__BITNR 15 +#define R_SERIAL1_CTRL__txd__WIDTH 1 +#define R_SERIAL1_CTRL__tr_enable__BITNR 14 +#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL1_CTRL__tr_enable__disable 0 +#define R_SERIAL1_CTRL__tr_enable__enable 1 +#define R_SERIAL1_CTRL__auto_cts__BITNR 13 +#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL1_CTRL__auto_cts__disabled 0 +#define R_SERIAL1_CTRL__auto_cts__active 1 +#define R_SERIAL1_CTRL__stop_bits__BITNR 12 +#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL1_CTRL__stop_bits__one_bit 0 +#define R_SERIAL1_CTRL__stop_bits__two_bits 1 +#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL1_CTRL__tr_stick_par__normal 0 +#define R_SERIAL1_CTRL__tr_stick_par__stick 1 +#define R_SERIAL1_CTRL__tr_par__BITNR 10 +#define R_SERIAL1_CTRL__tr_par__WIDTH 1 +#define R_SERIAL1_CTRL__tr_par__even 0 +#define R_SERIAL1_CTRL__tr_par__odd 1 +#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL1_CTRL__tr_par_en__disable 0 +#define R_SERIAL1_CTRL__tr_par_en__enable 1 +#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL1_CTRL__data_out__BITNR 0 +#define R_SERIAL1_CTRL__data_out__WIDTH 8 + +#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) +#define R_SERIAL1_BAUD__tr_baud__BITNR 4 +#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL1_BAUD__tr_baud__reserved 15 +#define R_SERIAL1_BAUD__rec_baud__BITNR 0 +#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL1_BAUD__rec_baud__reserved 15 + +#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) +#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL1_REC_CTRL__dma_err__stop 0 +#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL1_REC_CTRL__rts___BITNR 5 +#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL1_REC_CTRL__rts___active 0 +#define R_SERIAL1_REC_CTRL__rts___inactive 1 +#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL1_REC_CTRL__sampling__middle 0 +#define R_SERIAL1_REC_CTRL__sampling__majority 1 +#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_par__even 0 +#define R_SERIAL1_REC_CTRL__rec_par__odd 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) +#define R_SERIAL1_TR_CTRL__txd__BITNR 7 +#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL1_TR_CTRL__auto_cts__active 1 +#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_par__even 0 +#define R_SERIAL1_TR_CTRL__tr_par__odd 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) +#define R_SERIAL1_TR_DATA__data_out__BITNR 0 +#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) +#define R_SERIAL1_READ__xoff_detect__BITNR 15 +#define R_SERIAL1_READ__xoff_detect__WIDTH 1 +#define R_SERIAL1_READ__xoff_detect__no_xoff 0 +#define R_SERIAL1_READ__xoff_detect__xoff 1 +#define R_SERIAL1_READ__cts___BITNR 14 +#define R_SERIAL1_READ__cts___WIDTH 1 +#define R_SERIAL1_READ__cts___active 0 +#define R_SERIAL1_READ__cts___inactive 1 +#define R_SERIAL1_READ__tr_ready__BITNR 13 +#define R_SERIAL1_READ__tr_ready__WIDTH 1 +#define R_SERIAL1_READ__tr_ready__full 0 +#define R_SERIAL1_READ__tr_ready__ready 1 +#define R_SERIAL1_READ__rxd__BITNR 12 +#define R_SERIAL1_READ__rxd__WIDTH 1 +#define R_SERIAL1_READ__overrun__BITNR 11 +#define R_SERIAL1_READ__overrun__WIDTH 1 +#define R_SERIAL1_READ__overrun__no 0 +#define R_SERIAL1_READ__overrun__yes 1 +#define R_SERIAL1_READ__par_err__BITNR 10 +#define R_SERIAL1_READ__par_err__WIDTH 1 +#define R_SERIAL1_READ__par_err__no 0 +#define R_SERIAL1_READ__par_err__yes 1 +#define R_SERIAL1_READ__framing_err__BITNR 9 +#define R_SERIAL1_READ__framing_err__WIDTH 1 +#define R_SERIAL1_READ__framing_err__no 0 +#define R_SERIAL1_READ__framing_err__yes 1 +#define R_SERIAL1_READ__data_avail__BITNR 8 +#define R_SERIAL1_READ__data_avail__WIDTH 1 +#define R_SERIAL1_READ__data_avail__no 0 +#define R_SERIAL1_READ__data_avail__yes 1 +#define R_SERIAL1_READ__data_in__BITNR 0 +#define R_SERIAL1_READ__data_in__WIDTH 8 + +#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) +#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL1_STATUS__xoff_detect__xoff 1 +#define R_SERIAL1_STATUS__cts___BITNR 6 +#define R_SERIAL1_STATUS__cts___WIDTH 1 +#define R_SERIAL1_STATUS__cts___active 0 +#define R_SERIAL1_STATUS__cts___inactive 1 +#define R_SERIAL1_STATUS__tr_ready__BITNR 5 +#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL1_STATUS__tr_ready__full 0 +#define R_SERIAL1_STATUS__tr_ready__ready 1 +#define R_SERIAL1_STATUS__rxd__BITNR 4 +#define R_SERIAL1_STATUS__rxd__WIDTH 1 +#define R_SERIAL1_STATUS__overrun__BITNR 3 +#define R_SERIAL1_STATUS__overrun__WIDTH 1 +#define R_SERIAL1_STATUS__overrun__no 0 +#define R_SERIAL1_STATUS__overrun__yes 1 +#define R_SERIAL1_STATUS__par_err__BITNR 2 +#define R_SERIAL1_STATUS__par_err__WIDTH 1 +#define R_SERIAL1_STATUS__par_err__no 0 +#define R_SERIAL1_STATUS__par_err__yes 1 +#define R_SERIAL1_STATUS__framing_err__BITNR 1 +#define R_SERIAL1_STATUS__framing_err__WIDTH 1 +#define R_SERIAL1_STATUS__framing_err__no 0 +#define R_SERIAL1_STATUS__framing_err__yes 1 +#define R_SERIAL1_STATUS__data_avail__BITNR 0 +#define R_SERIAL1_STATUS__data_avail__WIDTH 1 +#define R_SERIAL1_STATUS__data_avail__no 0 +#define R_SERIAL1_STATUS__data_avail__yes 1 + +#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) +#define R_SERIAL1_REC_DATA__data_in__BITNR 0 +#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) +#define R_SERIAL1_XOFF__tx_stop__BITNR 9 +#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL1_XOFF__tx_stop__enable 0 +#define R_SERIAL1_XOFF__tx_stop__stop 1 +#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL1_XOFF__auto_xoff__disable 0 +#define R_SERIAL1_XOFF__auto_xoff__enable 1 +#define R_SERIAL1_XOFF__xoff_char__BITNR 0 +#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) +#define R_SERIAL2_CTRL__tr_baud__BITNR 28 +#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL2_CTRL__tr_baud__reserved 15 +#define R_SERIAL2_CTRL__rec_baud__BITNR 24 +#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL2_CTRL__rec_baud__reserved 15 +#define R_SERIAL2_CTRL__dma_err__BITNR 23 +#define R_SERIAL2_CTRL__dma_err__WIDTH 1 +#define R_SERIAL2_CTRL__dma_err__stop 0 +#define R_SERIAL2_CTRL__dma_err__ignore 1 +#define R_SERIAL2_CTRL__rec_enable__BITNR 22 +#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL2_CTRL__rec_enable__disable 0 +#define R_SERIAL2_CTRL__rec_enable__enable 1 +#define R_SERIAL2_CTRL__rts___BITNR 21 +#define R_SERIAL2_CTRL__rts___WIDTH 1 +#define R_SERIAL2_CTRL__rts___active 0 +#define R_SERIAL2_CTRL__rts___inactive 1 +#define R_SERIAL2_CTRL__sampling__BITNR 20 +#define R_SERIAL2_CTRL__sampling__WIDTH 1 +#define R_SERIAL2_CTRL__sampling__middle 0 +#define R_SERIAL2_CTRL__sampling__majority 1 +#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL2_CTRL__rec_stick_par__normal 0 +#define R_SERIAL2_CTRL__rec_stick_par__stick 1 +#define R_SERIAL2_CTRL__rec_par__BITNR 18 +#define R_SERIAL2_CTRL__rec_par__WIDTH 1 +#define R_SERIAL2_CTRL__rec_par__even 0 +#define R_SERIAL2_CTRL__rec_par__odd 1 +#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL2_CTRL__rec_par_en__disable 0 +#define R_SERIAL2_CTRL__rec_par_en__enable 1 +#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL2_CTRL__txd__BITNR 15 +#define R_SERIAL2_CTRL__txd__WIDTH 1 +#define R_SERIAL2_CTRL__tr_enable__BITNR 14 +#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL2_CTRL__tr_enable__disable 0 +#define R_SERIAL2_CTRL__tr_enable__enable 1 +#define R_SERIAL2_CTRL__auto_cts__BITNR 13 +#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL2_CTRL__auto_cts__disabled 0 +#define R_SERIAL2_CTRL__auto_cts__active 1 +#define R_SERIAL2_CTRL__stop_bits__BITNR 12 +#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL2_CTRL__stop_bits__one_bit 0 +#define R_SERIAL2_CTRL__stop_bits__two_bits 1 +#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL2_CTRL__tr_stick_par__normal 0 +#define R_SERIAL2_CTRL__tr_stick_par__stick 1 +#define R_SERIAL2_CTRL__tr_par__BITNR 10 +#define R_SERIAL2_CTRL__tr_par__WIDTH 1 +#define R_SERIAL2_CTRL__tr_par__even 0 +#define R_SERIAL2_CTRL__tr_par__odd 1 +#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL2_CTRL__tr_par_en__disable 0 +#define R_SERIAL2_CTRL__tr_par_en__enable 1 +#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL2_CTRL__data_out__BITNR 0 +#define R_SERIAL2_CTRL__data_out__WIDTH 8 + +#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) +#define R_SERIAL2_BAUD__tr_baud__BITNR 4 +#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL2_BAUD__tr_baud__reserved 15 +#define R_SERIAL2_BAUD__rec_baud__BITNR 0 +#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL2_BAUD__rec_baud__reserved 15 + +#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) +#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL2_REC_CTRL__dma_err__stop 0 +#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL2_REC_CTRL__rts___BITNR 5 +#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL2_REC_CTRL__rts___active 0 +#define R_SERIAL2_REC_CTRL__rts___inactive 1 +#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL2_REC_CTRL__sampling__middle 0 +#define R_SERIAL2_REC_CTRL__sampling__majority 1 +#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_par__even 0 +#define R_SERIAL2_REC_CTRL__rec_par__odd 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) +#define R_SERIAL2_TR_CTRL__txd__BITNR 7 +#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL2_TR_CTRL__auto_cts__active 1 +#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_par__even 0 +#define R_SERIAL2_TR_CTRL__tr_par__odd 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) +#define R_SERIAL2_TR_DATA__data_out__BITNR 0 +#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) +#define R_SERIAL2_READ__xoff_detect__BITNR 15 +#define R_SERIAL2_READ__xoff_detect__WIDTH 1 +#define R_SERIAL2_READ__xoff_detect__no_xoff 0 +#define R_SERIAL2_READ__xoff_detect__xoff 1 +#define R_SERIAL2_READ__cts___BITNR 14 +#define R_SERIAL2_READ__cts___WIDTH 1 +#define R_SERIAL2_READ__cts___active 0 +#define R_SERIAL2_READ__cts___inactive 1 +#define R_SERIAL2_READ__tr_ready__BITNR 13 +#define R_SERIAL2_READ__tr_ready__WIDTH 1 +#define R_SERIAL2_READ__tr_ready__full 0 +#define R_SERIAL2_READ__tr_ready__ready 1 +#define R_SERIAL2_READ__rxd__BITNR 12 +#define R_SERIAL2_READ__rxd__WIDTH 1 +#define R_SERIAL2_READ__overrun__BITNR 11 +#define R_SERIAL2_READ__overrun__WIDTH 1 +#define R_SERIAL2_READ__overrun__no 0 +#define R_SERIAL2_READ__overrun__yes 1 +#define R_SERIAL2_READ__par_err__BITNR 10 +#define R_SERIAL2_READ__par_err__WIDTH 1 +#define R_SERIAL2_READ__par_err__no 0 +#define R_SERIAL2_READ__par_err__yes 1 +#define R_SERIAL2_READ__framing_err__BITNR 9 +#define R_SERIAL2_READ__framing_err__WIDTH 1 +#define R_SERIAL2_READ__framing_err__no 0 +#define R_SERIAL2_READ__framing_err__yes 1 +#define R_SERIAL2_READ__data_avail__BITNR 8 +#define R_SERIAL2_READ__data_avail__WIDTH 1 +#define R_SERIAL2_READ__data_avail__no 0 +#define R_SERIAL2_READ__data_avail__yes 1 +#define R_SERIAL2_READ__data_in__BITNR 0 +#define R_SERIAL2_READ__data_in__WIDTH 8 + +#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) +#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL2_STATUS__xoff_detect__xoff 1 +#define R_SERIAL2_STATUS__cts___BITNR 6 +#define R_SERIAL2_STATUS__cts___WIDTH 1 +#define R_SERIAL2_STATUS__cts___active 0 +#define R_SERIAL2_STATUS__cts___inactive 1 +#define R_SERIAL2_STATUS__tr_ready__BITNR 5 +#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL2_STATUS__tr_ready__full 0 +#define R_SERIAL2_STATUS__tr_ready__ready 1 +#define R_SERIAL2_STATUS__rxd__BITNR 4 +#define R_SERIAL2_STATUS__rxd__WIDTH 1 +#define R_SERIAL2_STATUS__overrun__BITNR 3 +#define R_SERIAL2_STATUS__overrun__WIDTH 1 +#define R_SERIAL2_STATUS__overrun__no 0 +#define R_SERIAL2_STATUS__overrun__yes 1 +#define R_SERIAL2_STATUS__par_err__BITNR 2 +#define R_SERIAL2_STATUS__par_err__WIDTH 1 +#define R_SERIAL2_STATUS__par_err__no 0 +#define R_SERIAL2_STATUS__par_err__yes 1 +#define R_SERIAL2_STATUS__framing_err__BITNR 1 +#define R_SERIAL2_STATUS__framing_err__WIDTH 1 +#define R_SERIAL2_STATUS__framing_err__no 0 +#define R_SERIAL2_STATUS__framing_err__yes 1 +#define R_SERIAL2_STATUS__data_avail__BITNR 0 +#define R_SERIAL2_STATUS__data_avail__WIDTH 1 +#define R_SERIAL2_STATUS__data_avail__no 0 +#define R_SERIAL2_STATUS__data_avail__yes 1 + +#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) +#define R_SERIAL2_REC_DATA__data_in__BITNR 0 +#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) +#define R_SERIAL2_XOFF__tx_stop__BITNR 9 +#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL2_XOFF__tx_stop__enable 0 +#define R_SERIAL2_XOFF__tx_stop__stop 1 +#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL2_XOFF__auto_xoff__disable 0 +#define R_SERIAL2_XOFF__auto_xoff__enable 1 +#define R_SERIAL2_XOFF__xoff_char__BITNR 0 +#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) +#define R_SERIAL3_CTRL__tr_baud__BITNR 28 +#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL3_CTRL__tr_baud__reserved 15 +#define R_SERIAL3_CTRL__rec_baud__BITNR 24 +#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL3_CTRL__rec_baud__reserved 15 +#define R_SERIAL3_CTRL__dma_err__BITNR 23 +#define R_SERIAL3_CTRL__dma_err__WIDTH 1 +#define R_SERIAL3_CTRL__dma_err__stop 0 +#define R_SERIAL3_CTRL__dma_err__ignore 1 +#define R_SERIAL3_CTRL__rec_enable__BITNR 22 +#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL3_CTRL__rec_enable__disable 0 +#define R_SERIAL3_CTRL__rec_enable__enable 1 +#define R_SERIAL3_CTRL__rts___BITNR 21 +#define R_SERIAL3_CTRL__rts___WIDTH 1 +#define R_SERIAL3_CTRL__rts___active 0 +#define R_SERIAL3_CTRL__rts___inactive 1 +#define R_SERIAL3_CTRL__sampling__BITNR 20 +#define R_SERIAL3_CTRL__sampling__WIDTH 1 +#define R_SERIAL3_CTRL__sampling__middle 0 +#define R_SERIAL3_CTRL__sampling__majority 1 +#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL3_CTRL__rec_stick_par__normal 0 +#define R_SERIAL3_CTRL__rec_stick_par__stick 1 +#define R_SERIAL3_CTRL__rec_par__BITNR 18 +#define R_SERIAL3_CTRL__rec_par__WIDTH 1 +#define R_SERIAL3_CTRL__rec_par__even 0 +#define R_SERIAL3_CTRL__rec_par__odd 1 +#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL3_CTRL__rec_par_en__disable 0 +#define R_SERIAL3_CTRL__rec_par_en__enable 1 +#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL3_CTRL__txd__BITNR 15 +#define R_SERIAL3_CTRL__txd__WIDTH 1 +#define R_SERIAL3_CTRL__tr_enable__BITNR 14 +#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL3_CTRL__tr_enable__disable 0 +#define R_SERIAL3_CTRL__tr_enable__enable 1 +#define R_SERIAL3_CTRL__auto_cts__BITNR 13 +#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL3_CTRL__auto_cts__disabled 0 +#define R_SERIAL3_CTRL__auto_cts__active 1 +#define R_SERIAL3_CTRL__stop_bits__BITNR 12 +#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL3_CTRL__stop_bits__one_bit 0 +#define R_SERIAL3_CTRL__stop_bits__two_bits 1 +#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL3_CTRL__tr_stick_par__normal 0 +#define R_SERIAL3_CTRL__tr_stick_par__stick 1 +#define R_SERIAL3_CTRL__tr_par__BITNR 10 +#define R_SERIAL3_CTRL__tr_par__WIDTH 1 +#define R_SERIAL3_CTRL__tr_par__even 0 +#define R_SERIAL3_CTRL__tr_par__odd 1 +#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL3_CTRL__tr_par_en__disable 0 +#define R_SERIAL3_CTRL__tr_par_en__enable 1 +#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL3_CTRL__data_out__BITNR 0 +#define R_SERIAL3_CTRL__data_out__WIDTH 8 + +#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) +#define R_SERIAL3_BAUD__tr_baud__BITNR 4 +#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL3_BAUD__tr_baud__reserved 15 +#define R_SERIAL3_BAUD__rec_baud__BITNR 0 +#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL3_BAUD__rec_baud__reserved 15 + +#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) +#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL3_REC_CTRL__dma_err__stop 0 +#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL3_REC_CTRL__rts___BITNR 5 +#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL3_REC_CTRL__rts___active 0 +#define R_SERIAL3_REC_CTRL__rts___inactive 1 +#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL3_REC_CTRL__sampling__middle 0 +#define R_SERIAL3_REC_CTRL__sampling__majority 1 +#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_par__even 0 +#define R_SERIAL3_REC_CTRL__rec_par__odd 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) +#define R_SERIAL3_TR_CTRL__txd__BITNR 7 +#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL3_TR_CTRL__auto_cts__active 1 +#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_par__even 0 +#define R_SERIAL3_TR_CTRL__tr_par__odd 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) +#define R_SERIAL3_TR_DATA__data_out__BITNR 0 +#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) +#define R_SERIAL3_READ__xoff_detect__BITNR 15 +#define R_SERIAL3_READ__xoff_detect__WIDTH 1 +#define R_SERIAL3_READ__xoff_detect__no_xoff 0 +#define R_SERIAL3_READ__xoff_detect__xoff 1 +#define R_SERIAL3_READ__cts___BITNR 14 +#define R_SERIAL3_READ__cts___WIDTH 1 +#define R_SERIAL3_READ__cts___active 0 +#define R_SERIAL3_READ__cts___inactive 1 +#define R_SERIAL3_READ__tr_ready__BITNR 13 +#define R_SERIAL3_READ__tr_ready__WIDTH 1 +#define R_SERIAL3_READ__tr_ready__full 0 +#define R_SERIAL3_READ__tr_ready__ready 1 +#define R_SERIAL3_READ__rxd__BITNR 12 +#define R_SERIAL3_READ__rxd__WIDTH 1 +#define R_SERIAL3_READ__overrun__BITNR 11 +#define R_SERIAL3_READ__overrun__WIDTH 1 +#define R_SERIAL3_READ__overrun__no 0 +#define R_SERIAL3_READ__overrun__yes 1 +#define R_SERIAL3_READ__par_err__BITNR 10 +#define R_SERIAL3_READ__par_err__WIDTH 1 +#define R_SERIAL3_READ__par_err__no 0 +#define R_SERIAL3_READ__par_err__yes 1 +#define R_SERIAL3_READ__framing_err__BITNR 9 +#define R_SERIAL3_READ__framing_err__WIDTH 1 +#define R_SERIAL3_READ__framing_err__no 0 +#define R_SERIAL3_READ__framing_err__yes 1 +#define R_SERIAL3_READ__data_avail__BITNR 8 +#define R_SERIAL3_READ__data_avail__WIDTH 1 +#define R_SERIAL3_READ__data_avail__no 0 +#define R_SERIAL3_READ__data_avail__yes 1 +#define R_SERIAL3_READ__data_in__BITNR 0 +#define R_SERIAL3_READ__data_in__WIDTH 8 + +#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) +#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL3_STATUS__xoff_detect__xoff 1 +#define R_SERIAL3_STATUS__cts___BITNR 6 +#define R_SERIAL3_STATUS__cts___WIDTH 1 +#define R_SERIAL3_STATUS__cts___active 0 +#define R_SERIAL3_STATUS__cts___inactive 1 +#define R_SERIAL3_STATUS__tr_ready__BITNR 5 +#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL3_STATUS__tr_ready__full 0 +#define R_SERIAL3_STATUS__tr_ready__ready 1 +#define R_SERIAL3_STATUS__rxd__BITNR 4 +#define R_SERIAL3_STATUS__rxd__WIDTH 1 +#define R_SERIAL3_STATUS__overrun__BITNR 3 +#define R_SERIAL3_STATUS__overrun__WIDTH 1 +#define R_SERIAL3_STATUS__overrun__no 0 +#define R_SERIAL3_STATUS__overrun__yes 1 +#define R_SERIAL3_STATUS__par_err__BITNR 2 +#define R_SERIAL3_STATUS__par_err__WIDTH 1 +#define R_SERIAL3_STATUS__par_err__no 0 +#define R_SERIAL3_STATUS__par_err__yes 1 +#define R_SERIAL3_STATUS__framing_err__BITNR 1 +#define R_SERIAL3_STATUS__framing_err__WIDTH 1 +#define R_SERIAL3_STATUS__framing_err__no 0 +#define R_SERIAL3_STATUS__framing_err__yes 1 +#define R_SERIAL3_STATUS__data_avail__BITNR 0 +#define R_SERIAL3_STATUS__data_avail__WIDTH 1 +#define R_SERIAL3_STATUS__data_avail__no 0 +#define R_SERIAL3_STATUS__data_avail__yes 1 + +#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) +#define R_SERIAL3_REC_DATA__data_in__BITNR 0 +#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) +#define R_SERIAL3_XOFF__tx_stop__BITNR 9 +#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL3_XOFF__tx_stop__enable 0 +#define R_SERIAL3_XOFF__tx_stop__stop 1 +#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL3_XOFF__auto_xoff__disable 0 +#define R_SERIAL3_XOFF__auto_xoff__enable 1 +#define R_SERIAL3_XOFF__xoff_char__BITNR 0 +#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 + +#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) +#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 +#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 +#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 +#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 +#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 +#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 +#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 +#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 +#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 + +/* +!* Network interface registers +!*/ + +#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) +#define R_NETWORK_SA_0__ma0_low__BITNR 0 +#define R_NETWORK_SA_0__ma0_low__WIDTH 32 + +#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) +#define R_NETWORK_SA_1__ma1_low__BITNR 16 +#define R_NETWORK_SA_1__ma1_low__WIDTH 16 +#define R_NETWORK_SA_1__ma0_high__BITNR 0 +#define R_NETWORK_SA_1__ma0_high__WIDTH 16 + +#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) +#define R_NETWORK_SA_2__ma1_high__BITNR 0 +#define R_NETWORK_SA_2__ma1_high__WIDTH 32 + +#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) +#define R_NETWORK_GA_0__ga_low__BITNR 0 +#define R_NETWORK_GA_0__ga_low__WIDTH 32 + +#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) +#define R_NETWORK_GA_1__ga_high__BITNR 0 +#define R_NETWORK_GA_1__ga_high__WIDTH 32 + +#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) +#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 +#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 +#define R_NETWORK_REC_CONFIG__max_size__size1518 0 +#define R_NETWORK_REC_CONFIG__max_size__size1522 1 +#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 +#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 +#define R_NETWORK_REC_CONFIG__duplex__full 1 +#define R_NETWORK_REC_CONFIG__duplex__half 0 +#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 +#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 +#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 +#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 +#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 +#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 +#define R_NETWORK_REC_CONFIG__oversize__receive 1 +#define R_NETWORK_REC_CONFIG__oversize__discard 0 +#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 +#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 +#define R_NETWORK_REC_CONFIG__undersize__receive 1 +#define R_NETWORK_REC_CONFIG__undersize__discard 0 +#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 +#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 +#define R_NETWORK_REC_CONFIG__all_roots__receive 1 +#define R_NETWORK_REC_CONFIG__all_roots__discard 0 +#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 +#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 +#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 +#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 +#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 +#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 +#define R_NETWORK_REC_CONFIG__broadcast__receive 1 +#define R_NETWORK_REC_CONFIG__broadcast__discard 0 +#define R_NETWORK_REC_CONFIG__individual__BITNR 2 +#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 +#define R_NETWORK_REC_CONFIG__individual__receive 1 +#define R_NETWORK_REC_CONFIG__individual__discard 0 +#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 +#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 +#define R_NETWORK_REC_CONFIG__ma1__enable 1 +#define R_NETWORK_REC_CONFIG__ma1__disable 0 +#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 +#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 +#define R_NETWORK_REC_CONFIG__ma0__enable 1 +#define R_NETWORK_REC_CONFIG__ma0__disable 0 + +#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) +#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 +#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__loopback__on 1 +#define R_NETWORK_GEN_CONFIG__loopback__off 0 +#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 +#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 +#define R_NETWORK_GEN_CONFIG__frame__ether 0 +#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 +#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__vg__on 1 +#define R_NETWORK_GEN_CONFIG__vg__off 0 +#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 +#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 +#define R_NETWORK_GEN_CONFIG__phy__sni 0 +#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 +#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 +#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 +#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 +#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__enable__on 1 +#define R_NETWORK_GEN_CONFIG__enable__off 0 + +#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) +#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 +#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 +#define R_NETWORK_TR_CTRL__clr_error__clr 1 +#define R_NETWORK_TR_CTRL__clr_error__nop 0 +#define R_NETWORK_TR_CTRL__delay__BITNR 5 +#define R_NETWORK_TR_CTRL__delay__WIDTH 1 +#define R_NETWORK_TR_CTRL__delay__d2us 1 +#define R_NETWORK_TR_CTRL__delay__none 0 +#define R_NETWORK_TR_CTRL__cancel__BITNR 4 +#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 +#define R_NETWORK_TR_CTRL__cancel__do 1 +#define R_NETWORK_TR_CTRL__cancel__dont 0 +#define R_NETWORK_TR_CTRL__cd__BITNR 3 +#define R_NETWORK_TR_CTRL__cd__WIDTH 1 +#define R_NETWORK_TR_CTRL__cd__enable 0 +#define R_NETWORK_TR_CTRL__cd__disable 1 +#define R_NETWORK_TR_CTRL__cd__ack_col 0 +#define R_NETWORK_TR_CTRL__cd__ack_crs 1 +#define R_NETWORK_TR_CTRL__retry__BITNR 2 +#define R_NETWORK_TR_CTRL__retry__WIDTH 1 +#define R_NETWORK_TR_CTRL__retry__enable 0 +#define R_NETWORK_TR_CTRL__retry__disable 1 +#define R_NETWORK_TR_CTRL__pad__BITNR 1 +#define R_NETWORK_TR_CTRL__pad__WIDTH 1 +#define R_NETWORK_TR_CTRL__pad__enable 1 +#define R_NETWORK_TR_CTRL__pad__disable 0 +#define R_NETWORK_TR_CTRL__crc__BITNR 0 +#define R_NETWORK_TR_CTRL__crc__WIDTH 1 +#define R_NETWORK_TR_CTRL__crc__enable 0 +#define R_NETWORK_TR_CTRL__crc__disable 1 + +#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) +#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 +#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 +#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 +#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 +#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 +#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdoe__enable 1 +#define R_NETWORK_MGM_CTRL__mdoe__disable 0 +#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 +#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 + +#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) +#define R_NETWORK_STAT__rxd_pins__BITNR 4 +#define R_NETWORK_STAT__rxd_pins__WIDTH 4 +#define R_NETWORK_STAT__rxer__BITNR 3 +#define R_NETWORK_STAT__rxer__WIDTH 1 +#define R_NETWORK_STAT__underrun__BITNR 2 +#define R_NETWORK_STAT__underrun__WIDTH 1 +#define R_NETWORK_STAT__underrun__yes 1 +#define R_NETWORK_STAT__underrun__no 0 +#define R_NETWORK_STAT__exc_col__BITNR 1 +#define R_NETWORK_STAT__exc_col__WIDTH 1 +#define R_NETWORK_STAT__exc_col__yes 1 +#define R_NETWORK_STAT__exc_col__no 0 +#define R_NETWORK_STAT__mdio__BITNR 0 +#define R_NETWORK_STAT__mdio__WIDTH 1 + +#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) +#define R_REC_COUNTERS__congestion__BITNR 24 +#define R_REC_COUNTERS__congestion__WIDTH 8 +#define R_REC_COUNTERS__oversize__BITNR 16 +#define R_REC_COUNTERS__oversize__WIDTH 8 +#define R_REC_COUNTERS__alignment_error__BITNR 8 +#define R_REC_COUNTERS__alignment_error__WIDTH 8 +#define R_REC_COUNTERS__crc_error__BITNR 0 +#define R_REC_COUNTERS__crc_error__WIDTH 8 + +#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) +#define R_TR_COUNTERS__deferred__BITNR 24 +#define R_TR_COUNTERS__deferred__WIDTH 8 +#define R_TR_COUNTERS__late_col__BITNR 16 +#define R_TR_COUNTERS__late_col__WIDTH 8 +#define R_TR_COUNTERS__multiple_col__BITNR 8 +#define R_TR_COUNTERS__multiple_col__WIDTH 8 +#define R_TR_COUNTERS__single_col__BITNR 0 +#define R_TR_COUNTERS__single_col__WIDTH 8 + +#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) +#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 +#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 +#define R_PHY_COUNTERS__carrier_loss__BITNR 0 +#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 + +/* +!* Parallel printer port registers +!*/ + +#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 +#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 +#define R_PAR0_CTRL_DATA__peri_int__ack 1 +#define R_PAR0_CTRL_DATA__peri_int__nop 0 +#define R_PAR0_CTRL_DATA__oe__BITNR 20 +#define R_PAR0_CTRL_DATA__oe__WIDTH 1 +#define R_PAR0_CTRL_DATA__oe__enable 1 +#define R_PAR0_CTRL_DATA__oe__disable 0 +#define R_PAR0_CTRL_DATA__seli__BITNR 19 +#define R_PAR0_CTRL_DATA__seli__WIDTH 1 +#define R_PAR0_CTRL_DATA__seli__active 1 +#define R_PAR0_CTRL_DATA__seli__inactive 0 +#define R_PAR0_CTRL_DATA__autofd__BITNR 18 +#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 +#define R_PAR0_CTRL_DATA__autofd__active 1 +#define R_PAR0_CTRL_DATA__autofd__inactive 0 +#define R_PAR0_CTRL_DATA__strb__BITNR 17 +#define R_PAR0_CTRL_DATA__strb__WIDTH 1 +#define R_PAR0_CTRL_DATA__strb__active 1 +#define R_PAR0_CTRL_DATA__strb__inactive 0 +#define R_PAR0_CTRL_DATA__init__BITNR 16 +#define R_PAR0_CTRL_DATA__init__WIDTH 1 +#define R_PAR0_CTRL_DATA__init__active 1 +#define R_PAR0_CTRL_DATA__init__inactive 0 +#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 +#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 +#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 +#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 +#define R_PAR0_CTRL_DATA__data__BITNR 0 +#define R_PAR0_CTRL_DATA__data__WIDTH 8 + +#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) +#define R_PAR0_CTRL__ctrl__BITNR 0 +#define R_PAR0_CTRL__ctrl__WIDTH 5 + +#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) +#define R_PAR0_STATUS_DATA__mode__BITNR 29 +#define R_PAR0_STATUS_DATA__mode__WIDTH 3 +#define R_PAR0_STATUS_DATA__mode__manual 0 +#define R_PAR0_STATUS_DATA__mode__centronics 1 +#define R_PAR0_STATUS_DATA__mode__fastbyte 2 +#define R_PAR0_STATUS_DATA__mode__nibble 3 +#define R_PAR0_STATUS_DATA__mode__byte 4 +#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 +#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 +#define R_PAR0_STATUS_DATA__mode__off 7 +#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 +#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 +#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 +#define R_PAR0_STATUS_DATA__mode__epp_rd 0 +#define R_PAR0_STATUS_DATA__perr__BITNR 28 +#define R_PAR0_STATUS_DATA__perr__WIDTH 1 +#define R_PAR0_STATUS_DATA__perr__active 1 +#define R_PAR0_STATUS_DATA__perr__inactive 0 +#define R_PAR0_STATUS_DATA__ack__BITNR 27 +#define R_PAR0_STATUS_DATA__ack__WIDTH 1 +#define R_PAR0_STATUS_DATA__ack__active 0 +#define R_PAR0_STATUS_DATA__ack__inactive 1 +#define R_PAR0_STATUS_DATA__busy__BITNR 26 +#define R_PAR0_STATUS_DATA__busy__WIDTH 1 +#define R_PAR0_STATUS_DATA__busy__active 1 +#define R_PAR0_STATUS_DATA__busy__inactive 0 +#define R_PAR0_STATUS_DATA__fault__BITNR 25 +#define R_PAR0_STATUS_DATA__fault__WIDTH 1 +#define R_PAR0_STATUS_DATA__fault__active 0 +#define R_PAR0_STATUS_DATA__fault__inactive 1 +#define R_PAR0_STATUS_DATA__sel__BITNR 24 +#define R_PAR0_STATUS_DATA__sel__WIDTH 1 +#define R_PAR0_STATUS_DATA__sel__active 1 +#define R_PAR0_STATUS_DATA__sel__inactive 0 +#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 +#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 +#define R_PAR0_STATUS_DATA__ext_mode__enable 1 +#define R_PAR0_STATUS_DATA__ext_mode__disable 0 +#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 +#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 +#define R_PAR0_STATUS_DATA__ecp_16__active 1 +#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 +#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 +#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 +#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 +#define R_PAR0_STATUS_DATA__dav__BITNR 16 +#define R_PAR0_STATUS_DATA__dav__WIDTH 1 +#define R_PAR0_STATUS_DATA__dav__data 1 +#define R_PAR0_STATUS_DATA__dav__nodata 0 +#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 +#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 +#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 +#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 +#define R_PAR0_STATUS_DATA__data__BITNR 0 +#define R_PAR0_STATUS_DATA__data__WIDTH 8 + +#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) +#define R_PAR0_STATUS__mode__BITNR 13 +#define R_PAR0_STATUS__mode__WIDTH 3 +#define R_PAR0_STATUS__mode__manual 0 +#define R_PAR0_STATUS__mode__centronics 1 +#define R_PAR0_STATUS__mode__fastbyte 2 +#define R_PAR0_STATUS__mode__nibble 3 +#define R_PAR0_STATUS__mode__byte 4 +#define R_PAR0_STATUS__mode__ecp_fwd 5 +#define R_PAR0_STATUS__mode__ecp_rev 6 +#define R_PAR0_STATUS__mode__off 7 +#define R_PAR0_STATUS__mode__epp_wr1 5 +#define R_PAR0_STATUS__mode__epp_wr2 6 +#define R_PAR0_STATUS__mode__epp_wr3 7 +#define R_PAR0_STATUS__mode__epp_rd 0 +#define R_PAR0_STATUS__perr__BITNR 12 +#define R_PAR0_STATUS__perr__WIDTH 1 +#define R_PAR0_STATUS__perr__active 1 +#define R_PAR0_STATUS__perr__inactive 0 +#define R_PAR0_STATUS__ack__BITNR 11 +#define R_PAR0_STATUS__ack__WIDTH 1 +#define R_PAR0_STATUS__ack__active 0 +#define R_PAR0_STATUS__ack__inactive 1 +#define R_PAR0_STATUS__busy__BITNR 10 +#define R_PAR0_STATUS__busy__WIDTH 1 +#define R_PAR0_STATUS__busy__active 1 +#define R_PAR0_STATUS__busy__inactive 0 +#define R_PAR0_STATUS__fault__BITNR 9 +#define R_PAR0_STATUS__fault__WIDTH 1 +#define R_PAR0_STATUS__fault__active 0 +#define R_PAR0_STATUS__fault__inactive 1 +#define R_PAR0_STATUS__sel__BITNR 8 +#define R_PAR0_STATUS__sel__WIDTH 1 +#define R_PAR0_STATUS__sel__active 1 +#define R_PAR0_STATUS__sel__inactive 0 +#define R_PAR0_STATUS__ext_mode__BITNR 7 +#define R_PAR0_STATUS__ext_mode__WIDTH 1 +#define R_PAR0_STATUS__ext_mode__enable 1 +#define R_PAR0_STATUS__ext_mode__disable 0 +#define R_PAR0_STATUS__ecp_16__BITNR 6 +#define R_PAR0_STATUS__ecp_16__WIDTH 1 +#define R_PAR0_STATUS__ecp_16__active 1 +#define R_PAR0_STATUS__ecp_16__inactive 0 +#define R_PAR0_STATUS__tr_rdy__BITNR 1 +#define R_PAR0_STATUS__tr_rdy__WIDTH 1 +#define R_PAR0_STATUS__tr_rdy__ready 1 +#define R_PAR0_STATUS__tr_rdy__busy 0 +#define R_PAR0_STATUS__dav__BITNR 0 +#define R_PAR0_STATUS__dav__WIDTH 1 +#define R_PAR0_STATUS__dav__data 1 +#define R_PAR0_STATUS__dav__nodata 0 + +#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) +#define R_PAR_ECP16_DATA__data__BITNR 0 +#define R_PAR_ECP16_DATA__data__WIDTH 16 + +#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) +#define R_PAR0_CONFIG__ioe__BITNR 25 +#define R_PAR0_CONFIG__ioe__WIDTH 1 +#define R_PAR0_CONFIG__ioe__inv 1 +#define R_PAR0_CONFIG__ioe__noninv 0 +#define R_PAR0_CONFIG__iseli__BITNR 24 +#define R_PAR0_CONFIG__iseli__WIDTH 1 +#define R_PAR0_CONFIG__iseli__inv 1 +#define R_PAR0_CONFIG__iseli__noninv 0 +#define R_PAR0_CONFIG__iautofd__BITNR 23 +#define R_PAR0_CONFIG__iautofd__WIDTH 1 +#define R_PAR0_CONFIG__iautofd__inv 1 +#define R_PAR0_CONFIG__iautofd__noninv 0 +#define R_PAR0_CONFIG__istrb__BITNR 22 +#define R_PAR0_CONFIG__istrb__WIDTH 1 +#define R_PAR0_CONFIG__istrb__inv 1 +#define R_PAR0_CONFIG__istrb__noninv 0 +#define R_PAR0_CONFIG__iinit__BITNR 21 +#define R_PAR0_CONFIG__iinit__WIDTH 1 +#define R_PAR0_CONFIG__iinit__inv 1 +#define R_PAR0_CONFIG__iinit__noninv 0 +#define R_PAR0_CONFIG__iperr__BITNR 20 +#define R_PAR0_CONFIG__iperr__WIDTH 1 +#define R_PAR0_CONFIG__iperr__inv 1 +#define R_PAR0_CONFIG__iperr__noninv 0 +#define R_PAR0_CONFIG__iack__BITNR 19 +#define R_PAR0_CONFIG__iack__WIDTH 1 +#define R_PAR0_CONFIG__iack__inv 1 +#define R_PAR0_CONFIG__iack__noninv 0 +#define R_PAR0_CONFIG__ibusy__BITNR 18 +#define R_PAR0_CONFIG__ibusy__WIDTH 1 +#define R_PAR0_CONFIG__ibusy__inv 1 +#define R_PAR0_CONFIG__ibusy__noninv 0 +#define R_PAR0_CONFIG__ifault__BITNR 17 +#define R_PAR0_CONFIG__ifault__WIDTH 1 +#define R_PAR0_CONFIG__ifault__inv 1 +#define R_PAR0_CONFIG__ifault__noninv 0 +#define R_PAR0_CONFIG__isel__BITNR 16 +#define R_PAR0_CONFIG__isel__WIDTH 1 +#define R_PAR0_CONFIG__isel__inv 1 +#define R_PAR0_CONFIG__isel__noninv 0 +#define R_PAR0_CONFIG__ext_mode__BITNR 11 +#define R_PAR0_CONFIG__ext_mode__WIDTH 1 +#define R_PAR0_CONFIG__ext_mode__enable 1 +#define R_PAR0_CONFIG__ext_mode__disable 0 +#define R_PAR0_CONFIG__wide__BITNR 10 +#define R_PAR0_CONFIG__wide__WIDTH 1 +#define R_PAR0_CONFIG__wide__enable 1 +#define R_PAR0_CONFIG__wide__disable 0 +#define R_PAR0_CONFIG__dma__BITNR 9 +#define R_PAR0_CONFIG__dma__WIDTH 1 +#define R_PAR0_CONFIG__dma__enable 1 +#define R_PAR0_CONFIG__dma__disable 0 +#define R_PAR0_CONFIG__rle_in__BITNR 8 +#define R_PAR0_CONFIG__rle_in__WIDTH 1 +#define R_PAR0_CONFIG__rle_in__enable 1 +#define R_PAR0_CONFIG__rle_in__disable 0 +#define R_PAR0_CONFIG__rle_out__BITNR 7 +#define R_PAR0_CONFIG__rle_out__WIDTH 1 +#define R_PAR0_CONFIG__rle_out__enable 1 +#define R_PAR0_CONFIG__rle_out__disable 0 +#define R_PAR0_CONFIG__enable__BITNR 6 +#define R_PAR0_CONFIG__enable__WIDTH 1 +#define R_PAR0_CONFIG__enable__on 1 +#define R_PAR0_CONFIG__enable__reset 0 +#define R_PAR0_CONFIG__force__BITNR 5 +#define R_PAR0_CONFIG__force__WIDTH 1 +#define R_PAR0_CONFIG__force__on 1 +#define R_PAR0_CONFIG__force__off 0 +#define R_PAR0_CONFIG__ign_ack__BITNR 4 +#define R_PAR0_CONFIG__ign_ack__WIDTH 1 +#define R_PAR0_CONFIG__ign_ack__ignore 1 +#define R_PAR0_CONFIG__ign_ack__wait 0 +#define R_PAR0_CONFIG__oe_ack__BITNR 3 +#define R_PAR0_CONFIG__oe_ack__WIDTH 1 +#define R_PAR0_CONFIG__oe_ack__wait_oe 1 +#define R_PAR0_CONFIG__oe_ack__dont_wait 0 +#define R_PAR0_CONFIG__oe_ack__epp_addr 1 +#define R_PAR0_CONFIG__oe_ack__epp_data 0 +#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 +#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 +#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 +#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 +#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 +#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 +#define R_PAR0_CONFIG__mode__BITNR 0 +#define R_PAR0_CONFIG__mode__WIDTH 3 +#define R_PAR0_CONFIG__mode__manual 0 +#define R_PAR0_CONFIG__mode__centronics 1 +#define R_PAR0_CONFIG__mode__fastbyte 2 +#define R_PAR0_CONFIG__mode__nibble 3 +#define R_PAR0_CONFIG__mode__byte 4 +#define R_PAR0_CONFIG__mode__ecp_fwd 5 +#define R_PAR0_CONFIG__mode__ecp_rev 6 +#define R_PAR0_CONFIG__mode__off 7 +#define R_PAR0_CONFIG__mode__epp_wr1 5 +#define R_PAR0_CONFIG__mode__epp_wr2 6 +#define R_PAR0_CONFIG__mode__epp_wr3 7 +#define R_PAR0_CONFIG__mode__epp_rd 0 + +#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) +#define R_PAR0_DELAY__fine_hold__BITNR 21 +#define R_PAR0_DELAY__fine_hold__WIDTH 3 +#define R_PAR0_DELAY__hold__BITNR 16 +#define R_PAR0_DELAY__hold__WIDTH 5 +#define R_PAR0_DELAY__fine_strb__BITNR 13 +#define R_PAR0_DELAY__fine_strb__WIDTH 3 +#define R_PAR0_DELAY__strobe__BITNR 8 +#define R_PAR0_DELAY__strobe__WIDTH 5 +#define R_PAR0_DELAY__fine_setup__BITNR 5 +#define R_PAR0_DELAY__fine_setup__WIDTH 3 +#define R_PAR0_DELAY__setup__BITNR 0 +#define R_PAR0_DELAY__setup__WIDTH 5 + +#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) +#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 +#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 +#define R_PAR1_CTRL_DATA__peri_int__ack 1 +#define R_PAR1_CTRL_DATA__peri_int__nop 0 +#define R_PAR1_CTRL_DATA__oe__BITNR 20 +#define R_PAR1_CTRL_DATA__oe__WIDTH 1 +#define R_PAR1_CTRL_DATA__oe__enable 1 +#define R_PAR1_CTRL_DATA__oe__disable 0 +#define R_PAR1_CTRL_DATA__seli__BITNR 19 +#define R_PAR1_CTRL_DATA__seli__WIDTH 1 +#define R_PAR1_CTRL_DATA__seli__active 1 +#define R_PAR1_CTRL_DATA__seli__inactive 0 +#define R_PAR1_CTRL_DATA__autofd__BITNR 18 +#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 +#define R_PAR1_CTRL_DATA__autofd__active 1 +#define R_PAR1_CTRL_DATA__autofd__inactive 0 +#define R_PAR1_CTRL_DATA__strb__BITNR 17 +#define R_PAR1_CTRL_DATA__strb__WIDTH 1 +#define R_PAR1_CTRL_DATA__strb__active 1 +#define R_PAR1_CTRL_DATA__strb__inactive 0 +#define R_PAR1_CTRL_DATA__init__BITNR 16 +#define R_PAR1_CTRL_DATA__init__WIDTH 1 +#define R_PAR1_CTRL_DATA__init__active 1 +#define R_PAR1_CTRL_DATA__init__inactive 0 +#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 +#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 +#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 +#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 +#define R_PAR1_CTRL_DATA__data__BITNR 0 +#define R_PAR1_CTRL_DATA__data__WIDTH 8 + +#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) +#define R_PAR1_CTRL__ctrl__BITNR 0 +#define R_PAR1_CTRL__ctrl__WIDTH 5 + +#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) +#define R_PAR1_STATUS_DATA__mode__BITNR 29 +#define R_PAR1_STATUS_DATA__mode__WIDTH 3 +#define R_PAR1_STATUS_DATA__mode__manual 0 +#define R_PAR1_STATUS_DATA__mode__centronics 1 +#define R_PAR1_STATUS_DATA__mode__fastbyte 2 +#define R_PAR1_STATUS_DATA__mode__nibble 3 +#define R_PAR1_STATUS_DATA__mode__byte 4 +#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 +#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 +#define R_PAR1_STATUS_DATA__mode__off 7 +#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 +#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 +#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 +#define R_PAR1_STATUS_DATA__mode__epp_rd 0 +#define R_PAR1_STATUS_DATA__perr__BITNR 28 +#define R_PAR1_STATUS_DATA__perr__WIDTH 1 +#define R_PAR1_STATUS_DATA__perr__active 1 +#define R_PAR1_STATUS_DATA__perr__inactive 0 +#define R_PAR1_STATUS_DATA__ack__BITNR 27 +#define R_PAR1_STATUS_DATA__ack__WIDTH 1 +#define R_PAR1_STATUS_DATA__ack__active 0 +#define R_PAR1_STATUS_DATA__ack__inactive 1 +#define R_PAR1_STATUS_DATA__busy__BITNR 26 +#define R_PAR1_STATUS_DATA__busy__WIDTH 1 +#define R_PAR1_STATUS_DATA__busy__active 1 +#define R_PAR1_STATUS_DATA__busy__inactive 0 +#define R_PAR1_STATUS_DATA__fault__BITNR 25 +#define R_PAR1_STATUS_DATA__fault__WIDTH 1 +#define R_PAR1_STATUS_DATA__fault__active 0 +#define R_PAR1_STATUS_DATA__fault__inactive 1 +#define R_PAR1_STATUS_DATA__sel__BITNR 24 +#define R_PAR1_STATUS_DATA__sel__WIDTH 1 +#define R_PAR1_STATUS_DATA__sel__active 1 +#define R_PAR1_STATUS_DATA__sel__inactive 0 +#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 +#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 +#define R_PAR1_STATUS_DATA__ext_mode__enable 1 +#define R_PAR1_STATUS_DATA__ext_mode__disable 0 +#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 +#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 +#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 +#define R_PAR1_STATUS_DATA__dav__BITNR 16 +#define R_PAR1_STATUS_DATA__dav__WIDTH 1 +#define R_PAR1_STATUS_DATA__dav__data 1 +#define R_PAR1_STATUS_DATA__dav__nodata 0 +#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 +#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 +#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 +#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 +#define R_PAR1_STATUS_DATA__data__BITNR 0 +#define R_PAR1_STATUS_DATA__data__WIDTH 8 + +#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) +#define R_PAR1_STATUS__mode__BITNR 13 +#define R_PAR1_STATUS__mode__WIDTH 3 +#define R_PAR1_STATUS__mode__manual 0 +#define R_PAR1_STATUS__mode__centronics 1 +#define R_PAR1_STATUS__mode__fastbyte 2 +#define R_PAR1_STATUS__mode__nibble 3 +#define R_PAR1_STATUS__mode__byte 4 +#define R_PAR1_STATUS__mode__ecp_fwd 5 +#define R_PAR1_STATUS__mode__ecp_rev 6 +#define R_PAR1_STATUS__mode__off 7 +#define R_PAR1_STATUS__mode__epp_wr1 5 +#define R_PAR1_STATUS__mode__epp_wr2 6 +#define R_PAR1_STATUS__mode__epp_wr3 7 +#define R_PAR1_STATUS__mode__epp_rd 0 +#define R_PAR1_STATUS__perr__BITNR 12 +#define R_PAR1_STATUS__perr__WIDTH 1 +#define R_PAR1_STATUS__perr__active 1 +#define R_PAR1_STATUS__perr__inactive 0 +#define R_PAR1_STATUS__ack__BITNR 11 +#define R_PAR1_STATUS__ack__WIDTH 1 +#define R_PAR1_STATUS__ack__active 0 +#define R_PAR1_STATUS__ack__inactive 1 +#define R_PAR1_STATUS__busy__BITNR 10 +#define R_PAR1_STATUS__busy__WIDTH 1 +#define R_PAR1_STATUS__busy__active 1 +#define R_PAR1_STATUS__busy__inactive 0 +#define R_PAR1_STATUS__fault__BITNR 9 +#define R_PAR1_STATUS__fault__WIDTH 1 +#define R_PAR1_STATUS__fault__active 0 +#define R_PAR1_STATUS__fault__inactive 1 +#define R_PAR1_STATUS__sel__BITNR 8 +#define R_PAR1_STATUS__sel__WIDTH 1 +#define R_PAR1_STATUS__sel__active 1 +#define R_PAR1_STATUS__sel__inactive 0 +#define R_PAR1_STATUS__ext_mode__BITNR 7 +#define R_PAR1_STATUS__ext_mode__WIDTH 1 +#define R_PAR1_STATUS__ext_mode__enable 1 +#define R_PAR1_STATUS__ext_mode__disable 0 +#define R_PAR1_STATUS__tr_rdy__BITNR 1 +#define R_PAR1_STATUS__tr_rdy__WIDTH 1 +#define R_PAR1_STATUS__tr_rdy__ready 1 +#define R_PAR1_STATUS__tr_rdy__busy 0 +#define R_PAR1_STATUS__dav__BITNR 0 +#define R_PAR1_STATUS__dav__WIDTH 1 +#define R_PAR1_STATUS__dav__data 1 +#define R_PAR1_STATUS__dav__nodata 0 + +#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) +#define R_PAR1_CONFIG__ioe__BITNR 25 +#define R_PAR1_CONFIG__ioe__WIDTH 1 +#define R_PAR1_CONFIG__ioe__inv 1 +#define R_PAR1_CONFIG__ioe__noninv 0 +#define R_PAR1_CONFIG__iseli__BITNR 24 +#define R_PAR1_CONFIG__iseli__WIDTH 1 +#define R_PAR1_CONFIG__iseli__inv 1 +#define R_PAR1_CONFIG__iseli__noninv 0 +#define R_PAR1_CONFIG__iautofd__BITNR 23 +#define R_PAR1_CONFIG__iautofd__WIDTH 1 +#define R_PAR1_CONFIG__iautofd__inv 1 +#define R_PAR1_CONFIG__iautofd__noninv 0 +#define R_PAR1_CONFIG__istrb__BITNR 22 +#define R_PAR1_CONFIG__istrb__WIDTH 1 +#define R_PAR1_CONFIG__istrb__inv 1 +#define R_PAR1_CONFIG__istrb__noninv 0 +#define R_PAR1_CONFIG__iinit__BITNR 21 +#define R_PAR1_CONFIG__iinit__WIDTH 1 +#define R_PAR1_CONFIG__iinit__inv 1 +#define R_PAR1_CONFIG__iinit__noninv 0 +#define R_PAR1_CONFIG__iperr__BITNR 20 +#define R_PAR1_CONFIG__iperr__WIDTH 1 +#define R_PAR1_CONFIG__iperr__inv 1 +#define R_PAR1_CONFIG__iperr__noninv 0 +#define R_PAR1_CONFIG__iack__BITNR 19 +#define R_PAR1_CONFIG__iack__WIDTH 1 +#define R_PAR1_CONFIG__iack__inv 1 +#define R_PAR1_CONFIG__iack__noninv 0 +#define R_PAR1_CONFIG__ibusy__BITNR 18 +#define R_PAR1_CONFIG__ibusy__WIDTH 1 +#define R_PAR1_CONFIG__ibusy__inv 1 +#define R_PAR1_CONFIG__ibusy__noninv 0 +#define R_PAR1_CONFIG__ifault__BITNR 17 +#define R_PAR1_CONFIG__ifault__WIDTH 1 +#define R_PAR1_CONFIG__ifault__inv 1 +#define R_PAR1_CONFIG__ifault__noninv 0 +#define R_PAR1_CONFIG__isel__BITNR 16 +#define R_PAR1_CONFIG__isel__WIDTH 1 +#define R_PAR1_CONFIG__isel__inv 1 +#define R_PAR1_CONFIG__isel__noninv 0 +#define R_PAR1_CONFIG__ext_mode__BITNR 11 +#define R_PAR1_CONFIG__ext_mode__WIDTH 1 +#define R_PAR1_CONFIG__ext_mode__enable 1 +#define R_PAR1_CONFIG__ext_mode__disable 0 +#define R_PAR1_CONFIG__dma__BITNR 9 +#define R_PAR1_CONFIG__dma__WIDTH 1 +#define R_PAR1_CONFIG__dma__enable 1 +#define R_PAR1_CONFIG__dma__disable 0 +#define R_PAR1_CONFIG__rle_in__BITNR 8 +#define R_PAR1_CONFIG__rle_in__WIDTH 1 +#define R_PAR1_CONFIG__rle_in__enable 1 +#define R_PAR1_CONFIG__rle_in__disable 0 +#define R_PAR1_CONFIG__rle_out__BITNR 7 +#define R_PAR1_CONFIG__rle_out__WIDTH 1 +#define R_PAR1_CONFIG__rle_out__enable 1 +#define R_PAR1_CONFIG__rle_out__disable 0 +#define R_PAR1_CONFIG__enable__BITNR 6 +#define R_PAR1_CONFIG__enable__WIDTH 1 +#define R_PAR1_CONFIG__enable__on 1 +#define R_PAR1_CONFIG__enable__reset 0 +#define R_PAR1_CONFIG__force__BITNR 5 +#define R_PAR1_CONFIG__force__WIDTH 1 +#define R_PAR1_CONFIG__force__on 1 +#define R_PAR1_CONFIG__force__off 0 +#define R_PAR1_CONFIG__ign_ack__BITNR 4 +#define R_PAR1_CONFIG__ign_ack__WIDTH 1 +#define R_PAR1_CONFIG__ign_ack__ignore 1 +#define R_PAR1_CONFIG__ign_ack__wait 0 +#define R_PAR1_CONFIG__oe_ack__BITNR 3 +#define R_PAR1_CONFIG__oe_ack__WIDTH 1 +#define R_PAR1_CONFIG__oe_ack__wait_oe 1 +#define R_PAR1_CONFIG__oe_ack__dont_wait 0 +#define R_PAR1_CONFIG__oe_ack__epp_addr 1 +#define R_PAR1_CONFIG__oe_ack__epp_data 0 +#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 +#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 +#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 +#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 +#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 +#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 +#define R_PAR1_CONFIG__mode__BITNR 0 +#define R_PAR1_CONFIG__mode__WIDTH 3 +#define R_PAR1_CONFIG__mode__manual 0 +#define R_PAR1_CONFIG__mode__centronics 1 +#define R_PAR1_CONFIG__mode__fastbyte 2 +#define R_PAR1_CONFIG__mode__nibble 3 +#define R_PAR1_CONFIG__mode__byte 4 +#define R_PAR1_CONFIG__mode__ecp_fwd 5 +#define R_PAR1_CONFIG__mode__ecp_rev 6 +#define R_PAR1_CONFIG__mode__off 7 +#define R_PAR1_CONFIG__mode__epp_wr1 5 +#define R_PAR1_CONFIG__mode__epp_wr2 6 +#define R_PAR1_CONFIG__mode__epp_wr3 7 +#define R_PAR1_CONFIG__mode__epp_rd 0 + +#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) +#define R_PAR1_DELAY__fine_hold__BITNR 21 +#define R_PAR1_DELAY__fine_hold__WIDTH 3 +#define R_PAR1_DELAY__hold__BITNR 16 +#define R_PAR1_DELAY__hold__WIDTH 5 +#define R_PAR1_DELAY__fine_strb__BITNR 13 +#define R_PAR1_DELAY__fine_strb__WIDTH 3 +#define R_PAR1_DELAY__strobe__BITNR 8 +#define R_PAR1_DELAY__strobe__WIDTH 5 +#define R_PAR1_DELAY__fine_setup__BITNR 5 +#define R_PAR1_DELAY__fine_setup__WIDTH 3 +#define R_PAR1_DELAY__setup__BITNR 0 +#define R_PAR1_DELAY__setup__WIDTH 5 + +/* +!* ATA interface registers +!*/ + +#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_ATA_CTRL_DATA__sel__BITNR 30 +#define R_ATA_CTRL_DATA__sel__WIDTH 2 +#define R_ATA_CTRL_DATA__cs1__BITNR 29 +#define R_ATA_CTRL_DATA__cs1__WIDTH 1 +#define R_ATA_CTRL_DATA__cs1__active 1 +#define R_ATA_CTRL_DATA__cs1__inactive 0 +#define R_ATA_CTRL_DATA__cs0__BITNR 28 +#define R_ATA_CTRL_DATA__cs0__WIDTH 1 +#define R_ATA_CTRL_DATA__cs0__active 1 +#define R_ATA_CTRL_DATA__cs0__inactive 0 +#define R_ATA_CTRL_DATA__addr__BITNR 25 +#define R_ATA_CTRL_DATA__addr__WIDTH 3 +#define R_ATA_CTRL_DATA__rw__BITNR 24 +#define R_ATA_CTRL_DATA__rw__WIDTH 1 +#define R_ATA_CTRL_DATA__rw__read 1 +#define R_ATA_CTRL_DATA__rw__write 0 +#define R_ATA_CTRL_DATA__src_dst__BITNR 23 +#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 +#define R_ATA_CTRL_DATA__src_dst__dma 1 +#define R_ATA_CTRL_DATA__src_dst__register 0 +#define R_ATA_CTRL_DATA__handsh__BITNR 22 +#define R_ATA_CTRL_DATA__handsh__WIDTH 1 +#define R_ATA_CTRL_DATA__handsh__dma 1 +#define R_ATA_CTRL_DATA__handsh__pio 0 +#define R_ATA_CTRL_DATA__multi__BITNR 21 +#define R_ATA_CTRL_DATA__multi__WIDTH 1 +#define R_ATA_CTRL_DATA__multi__on 1 +#define R_ATA_CTRL_DATA__multi__off 0 +#define R_ATA_CTRL_DATA__dma_size__BITNR 20 +#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 +#define R_ATA_CTRL_DATA__dma_size__byte 1 +#define R_ATA_CTRL_DATA__dma_size__word 0 +#define R_ATA_CTRL_DATA__data__BITNR 0 +#define R_ATA_CTRL_DATA__data__WIDTH 16 + +#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) +#define R_ATA_STATUS_DATA__busy__BITNR 18 +#define R_ATA_STATUS_DATA__busy__WIDTH 1 +#define R_ATA_STATUS_DATA__busy__yes 1 +#define R_ATA_STATUS_DATA__busy__no 0 +#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 +#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_ATA_STATUS_DATA__tr_rdy__ready 1 +#define R_ATA_STATUS_DATA__tr_rdy__busy 0 +#define R_ATA_STATUS_DATA__dav__BITNR 16 +#define R_ATA_STATUS_DATA__dav__WIDTH 1 +#define R_ATA_STATUS_DATA__dav__data 1 +#define R_ATA_STATUS_DATA__dav__nodata 0 +#define R_ATA_STATUS_DATA__data__BITNR 0 +#define R_ATA_STATUS_DATA__data__WIDTH 16 + +#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) +#define R_ATA_CONFIG__enable__BITNR 25 +#define R_ATA_CONFIG__enable__WIDTH 1 +#define R_ATA_CONFIG__enable__on 1 +#define R_ATA_CONFIG__enable__off 0 +#define R_ATA_CONFIG__dma_strobe__BITNR 20 +#define R_ATA_CONFIG__dma_strobe__WIDTH 5 +#define R_ATA_CONFIG__dma_hold__BITNR 15 +#define R_ATA_CONFIG__dma_hold__WIDTH 5 +#define R_ATA_CONFIG__pio_setup__BITNR 10 +#define R_ATA_CONFIG__pio_setup__WIDTH 5 +#define R_ATA_CONFIG__pio_strobe__BITNR 5 +#define R_ATA_CONFIG__pio_strobe__WIDTH 5 +#define R_ATA_CONFIG__pio_hold__BITNR 0 +#define R_ATA_CONFIG__pio_hold__WIDTH 5 + +#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) +#define R_ATA_TRANSFER_CNT__count__BITNR 0 +#define R_ATA_TRANSFER_CNT__count__WIDTH 17 + +/* +!* SCSI registers +!*/ + +#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) +#define R_SCSI0_CTRL__id_type__BITNR 31 +#define R_SCSI0_CTRL__id_type__WIDTH 1 +#define R_SCSI0_CTRL__id_type__software 1 +#define R_SCSI0_CTRL__id_type__hardware 0 +#define R_SCSI0_CTRL__sel_timeout__BITNR 24 +#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 +#define R_SCSI0_CTRL__synch_per__BITNR 16 +#define R_SCSI0_CTRL__synch_per__WIDTH 8 +#define R_SCSI0_CTRL__rst__BITNR 15 +#define R_SCSI0_CTRL__rst__WIDTH 1 +#define R_SCSI0_CTRL__rst__yes 1 +#define R_SCSI0_CTRL__rst__no 0 +#define R_SCSI0_CTRL__atn__BITNR 14 +#define R_SCSI0_CTRL__atn__WIDTH 1 +#define R_SCSI0_CTRL__atn__yes 1 +#define R_SCSI0_CTRL__atn__no 0 +#define R_SCSI0_CTRL__my_id__BITNR 9 +#define R_SCSI0_CTRL__my_id__WIDTH 4 +#define R_SCSI0_CTRL__target_id__BITNR 4 +#define R_SCSI0_CTRL__target_id__WIDTH 4 +#define R_SCSI0_CTRL__fast_20__BITNR 3 +#define R_SCSI0_CTRL__fast_20__WIDTH 1 +#define R_SCSI0_CTRL__fast_20__yes 1 +#define R_SCSI0_CTRL__fast_20__no 0 +#define R_SCSI0_CTRL__bus_width__BITNR 2 +#define R_SCSI0_CTRL__bus_width__WIDTH 1 +#define R_SCSI0_CTRL__bus_width__wide 1 +#define R_SCSI0_CTRL__bus_width__narrow 0 +#define R_SCSI0_CTRL__synch__BITNR 1 +#define R_SCSI0_CTRL__synch__WIDTH 1 +#define R_SCSI0_CTRL__synch__synch 1 +#define R_SCSI0_CTRL__synch__asynch 0 +#define R_SCSI0_CTRL__enable__BITNR 0 +#define R_SCSI0_CTRL__enable__WIDTH 1 +#define R_SCSI0_CTRL__enable__on 1 +#define R_SCSI0_CTRL__enable__off 0 + +#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 +#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 +#define R_SCSI0_CMD_DATA__parity_in__on 0 +#define R_SCSI0_CMD_DATA__parity_in__off 1 +#define R_SCSI0_CMD_DATA__skip__BITNR 25 +#define R_SCSI0_CMD_DATA__skip__WIDTH 1 +#define R_SCSI0_CMD_DATA__skip__on 1 +#define R_SCSI0_CMD_DATA__skip__off 0 +#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 +#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 +#define R_SCSI0_CMD_DATA__clr_status__yes 1 +#define R_SCSI0_CMD_DATA__clr_status__nop 0 +#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 +#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 +#define R_SCSI0_CMD_DATA__command__BITNR 16 +#define R_SCSI0_CMD_DATA__command__WIDTH 4 +#define R_SCSI0_CMD_DATA__command__full_din_1 0 +#define R_SCSI0_CMD_DATA__command__full_dout_1 1 +#define R_SCSI0_CMD_DATA__command__full_stat_1 2 +#define R_SCSI0_CMD_DATA__command__resel_din 3 +#define R_SCSI0_CMD_DATA__command__resel_dout 4 +#define R_SCSI0_CMD_DATA__command__resel_stat 5 +#define R_SCSI0_CMD_DATA__command__arb_only 6 +#define R_SCSI0_CMD_DATA__command__full_din_3 8 +#define R_SCSI0_CMD_DATA__command__full_dout_3 9 +#define R_SCSI0_CMD_DATA__command__full_stat_3 10 +#define R_SCSI0_CMD_DATA__command__man_data_in 11 +#define R_SCSI0_CMD_DATA__command__man_data_out 12 +#define R_SCSI0_CMD_DATA__command__man_rat 13 +#define R_SCSI0_CMD_DATA__data_out__BITNR 0 +#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 + +#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) +#define R_SCSI0_DATA__data_out__BITNR 0 +#define R_SCSI0_DATA__data_out__WIDTH 16 + +#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) +#define R_SCSI0_CMD__asynch_setup__BITNR 4 +#define R_SCSI0_CMD__asynch_setup__WIDTH 4 +#define R_SCSI0_CMD__command__BITNR 0 +#define R_SCSI0_CMD__command__WIDTH 4 +#define R_SCSI0_CMD__command__full_din_1 0 +#define R_SCSI0_CMD__command__full_dout_1 1 +#define R_SCSI0_CMD__command__full_stat_1 2 +#define R_SCSI0_CMD__command__resel_din 3 +#define R_SCSI0_CMD__command__resel_dout 4 +#define R_SCSI0_CMD__command__resel_stat 5 +#define R_SCSI0_CMD__command__arb_only 6 +#define R_SCSI0_CMD__command__full_din_3 8 +#define R_SCSI0_CMD__command__full_dout_3 9 +#define R_SCSI0_CMD__command__full_stat_3 10 +#define R_SCSI0_CMD__command__man_data_in 11 +#define R_SCSI0_CMD__command__man_data_out 12 +#define R_SCSI0_CMD__command__man_rat 13 + +#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) +#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 +#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__parity_in__on 0 +#define R_SCSI0_STATUS_CTRL__parity_in__off 1 +#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 +#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__skip__on 1 +#define R_SCSI0_STATUS_CTRL__skip__off 0 +#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 +#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 +#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 + +#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) +#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 +#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 +#define R_SCSI0_STATUS__tst_resel__BITNR 22 +#define R_SCSI0_STATUS__tst_resel__WIDTH 1 +#define R_SCSI0_STATUS__parity_error__BITNR 21 +#define R_SCSI0_STATUS__parity_error__WIDTH 1 +#define R_SCSI0_STATUS__bus_reset__BITNR 20 +#define R_SCSI0_STATUS__bus_reset__WIDTH 1 +#define R_SCSI0_STATUS__bus_reset__yes 1 +#define R_SCSI0_STATUS__bus_reset__no 0 +#define R_SCSI0_STATUS__resel_target__BITNR 15 +#define R_SCSI0_STATUS__resel_target__WIDTH 4 +#define R_SCSI0_STATUS__resel__BITNR 14 +#define R_SCSI0_STATUS__resel__WIDTH 1 +#define R_SCSI0_STATUS__resel__yes 1 +#define R_SCSI0_STATUS__resel__no 0 +#define R_SCSI0_STATUS__curr_phase__BITNR 11 +#define R_SCSI0_STATUS__curr_phase__WIDTH 3 +#define R_SCSI0_STATUS__curr_phase__ph_undef 0 +#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 +#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 +#define R_SCSI0_STATUS__curr_phase__ph_status 3 +#define R_SCSI0_STATUS__curr_phase__ph_command 2 +#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 +#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 +#define R_SCSI0_STATUS__curr_phase__ph_resel 1 +#define R_SCSI0_STATUS__last_seq_step__BITNR 6 +#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 +#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 +#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 +#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 +#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 +#define R_SCSI0_STATUS__last_seq_step__st_manual 28 +#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 +#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 +#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 +#define R_SCSI0_STATUS__last_seq_step__st_answer 3 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 +#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 +#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 +#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 +#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 +#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 +#define R_SCSI0_STATUS__last_seq_step__st_cc 31 +#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 +#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 +#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 +#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 +#define R_SCSI0_STATUS__valid_status__BITNR 5 +#define R_SCSI0_STATUS__valid_status__WIDTH 1 +#define R_SCSI0_STATUS__valid_status__yes 1 +#define R_SCSI0_STATUS__valid_status__no 0 +#define R_SCSI0_STATUS__seq_status__BITNR 0 +#define R_SCSI0_STATUS__seq_status__WIDTH 5 +#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 +#define R_SCSI0_STATUS__seq_status__info_parity_error 1 +#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 +#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 +#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 +#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 +#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 +#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 +#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 +#define R_SCSI0_STATUS__seq_status__info_reselected 9 +#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 +#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 +#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 +#define R_SCSI0_STATUS__seq_status__info_bus_free 13 + +#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) +#define R_SCSI0_DATA_IN__data_in__BITNR 0 +#define R_SCSI0_DATA_IN__data_in__WIDTH 16 + +#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) +#define R_SCSI1_CTRL__id_type__BITNR 31 +#define R_SCSI1_CTRL__id_type__WIDTH 1 +#define R_SCSI1_CTRL__id_type__software 1 +#define R_SCSI1_CTRL__id_type__hardware 0 +#define R_SCSI1_CTRL__sel_timeout__BITNR 24 +#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 +#define R_SCSI1_CTRL__synch_per__BITNR 16 +#define R_SCSI1_CTRL__synch_per__WIDTH 8 +#define R_SCSI1_CTRL__rst__BITNR 15 +#define R_SCSI1_CTRL__rst__WIDTH 1 +#define R_SCSI1_CTRL__rst__yes 1 +#define R_SCSI1_CTRL__rst__no 0 +#define R_SCSI1_CTRL__atn__BITNR 14 +#define R_SCSI1_CTRL__atn__WIDTH 1 +#define R_SCSI1_CTRL__atn__yes 1 +#define R_SCSI1_CTRL__atn__no 0 +#define R_SCSI1_CTRL__my_id__BITNR 9 +#define R_SCSI1_CTRL__my_id__WIDTH 4 +#define R_SCSI1_CTRL__target_id__BITNR 4 +#define R_SCSI1_CTRL__target_id__WIDTH 4 +#define R_SCSI1_CTRL__fast_20__BITNR 3 +#define R_SCSI1_CTRL__fast_20__WIDTH 1 +#define R_SCSI1_CTRL__fast_20__yes 1 +#define R_SCSI1_CTRL__fast_20__no 0 +#define R_SCSI1_CTRL__bus_width__BITNR 2 +#define R_SCSI1_CTRL__bus_width__WIDTH 1 +#define R_SCSI1_CTRL__bus_width__wide 1 +#define R_SCSI1_CTRL__bus_width__narrow 0 +#define R_SCSI1_CTRL__synch__BITNR 1 +#define R_SCSI1_CTRL__synch__WIDTH 1 +#define R_SCSI1_CTRL__synch__synch 1 +#define R_SCSI1_CTRL__synch__asynch 0 +#define R_SCSI1_CTRL__enable__BITNR 0 +#define R_SCSI1_CTRL__enable__WIDTH 1 +#define R_SCSI1_CTRL__enable__on 1 +#define R_SCSI1_CTRL__enable__off 0 + +#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) +#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 +#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 +#define R_SCSI1_CMD_DATA__parity_in__on 0 +#define R_SCSI1_CMD_DATA__parity_in__off 1 +#define R_SCSI1_CMD_DATA__skip__BITNR 25 +#define R_SCSI1_CMD_DATA__skip__WIDTH 1 +#define R_SCSI1_CMD_DATA__skip__on 1 +#define R_SCSI1_CMD_DATA__skip__off 0 +#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 +#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 +#define R_SCSI1_CMD_DATA__clr_status__yes 1 +#define R_SCSI1_CMD_DATA__clr_status__nop 0 +#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 +#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 +#define R_SCSI1_CMD_DATA__command__BITNR 16 +#define R_SCSI1_CMD_DATA__command__WIDTH 4 +#define R_SCSI1_CMD_DATA__command__full_din_1 0 +#define R_SCSI1_CMD_DATA__command__full_dout_1 1 +#define R_SCSI1_CMD_DATA__command__full_stat_1 2 +#define R_SCSI1_CMD_DATA__command__resel_din 3 +#define R_SCSI1_CMD_DATA__command__resel_dout 4 +#define R_SCSI1_CMD_DATA__command__resel_stat 5 +#define R_SCSI1_CMD_DATA__command__arb_only 6 +#define R_SCSI1_CMD_DATA__command__full_din_3 8 +#define R_SCSI1_CMD_DATA__command__full_dout_3 9 +#define R_SCSI1_CMD_DATA__command__full_stat_3 10 +#define R_SCSI1_CMD_DATA__command__man_data_in 11 +#define R_SCSI1_CMD_DATA__command__man_data_out 12 +#define R_SCSI1_CMD_DATA__command__man_rat 13 +#define R_SCSI1_CMD_DATA__data_out__BITNR 0 +#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 + +#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) +#define R_SCSI1_DATA__data_out__BITNR 0 +#define R_SCSI1_DATA__data_out__WIDTH 16 + +#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) +#define R_SCSI1_CMD__asynch_setup__BITNR 4 +#define R_SCSI1_CMD__asynch_setup__WIDTH 4 +#define R_SCSI1_CMD__command__BITNR 0 +#define R_SCSI1_CMD__command__WIDTH 4 +#define R_SCSI1_CMD__command__full_din_1 0 +#define R_SCSI1_CMD__command__full_dout_1 1 +#define R_SCSI1_CMD__command__full_stat_1 2 +#define R_SCSI1_CMD__command__resel_din 3 +#define R_SCSI1_CMD__command__resel_dout 4 +#define R_SCSI1_CMD__command__resel_stat 5 +#define R_SCSI1_CMD__command__arb_only 6 +#define R_SCSI1_CMD__command__full_din_3 8 +#define R_SCSI1_CMD__command__full_dout_3 9 +#define R_SCSI1_CMD__command__full_stat_3 10 +#define R_SCSI1_CMD__command__man_data_in 11 +#define R_SCSI1_CMD__command__man_data_out 12 +#define R_SCSI1_CMD__command__man_rat 13 + +#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) +#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 +#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__parity_in__on 0 +#define R_SCSI1_STATUS_CTRL__parity_in__off 1 +#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 +#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__skip__on 1 +#define R_SCSI1_STATUS_CTRL__skip__off 0 +#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 +#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 +#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 + +#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) +#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 +#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 +#define R_SCSI1_STATUS__tst_resel__BITNR 22 +#define R_SCSI1_STATUS__tst_resel__WIDTH 1 +#define R_SCSI1_STATUS__parity_error__BITNR 21 +#define R_SCSI1_STATUS__parity_error__WIDTH 1 +#define R_SCSI1_STATUS__bus_reset__BITNR 20 +#define R_SCSI1_STATUS__bus_reset__WIDTH 1 +#define R_SCSI1_STATUS__bus_reset__yes 1 +#define R_SCSI1_STATUS__bus_reset__no 0 +#define R_SCSI1_STATUS__resel_target__BITNR 15 +#define R_SCSI1_STATUS__resel_target__WIDTH 4 +#define R_SCSI1_STATUS__resel__BITNR 14 +#define R_SCSI1_STATUS__resel__WIDTH 1 +#define R_SCSI1_STATUS__resel__yes 1 +#define R_SCSI1_STATUS__resel__no 0 +#define R_SCSI1_STATUS__curr_phase__BITNR 11 +#define R_SCSI1_STATUS__curr_phase__WIDTH 3 +#define R_SCSI1_STATUS__curr_phase__ph_undef 0 +#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 +#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 +#define R_SCSI1_STATUS__curr_phase__ph_status 3 +#define R_SCSI1_STATUS__curr_phase__ph_command 2 +#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 +#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 +#define R_SCSI1_STATUS__curr_phase__ph_resel 1 +#define R_SCSI1_STATUS__last_seq_step__BITNR 6 +#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 +#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 +#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 +#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 +#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 +#define R_SCSI1_STATUS__last_seq_step__st_manual 28 +#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 +#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 +#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 +#define R_SCSI1_STATUS__last_seq_step__st_answer 3 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 +#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 +#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 +#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 +#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 +#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 +#define R_SCSI1_STATUS__last_seq_step__st_cc 31 +#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 +#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 +#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 +#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 +#define R_SCSI1_STATUS__valid_status__BITNR 5 +#define R_SCSI1_STATUS__valid_status__WIDTH 1 +#define R_SCSI1_STATUS__valid_status__yes 1 +#define R_SCSI1_STATUS__valid_status__no 0 +#define R_SCSI1_STATUS__seq_status__BITNR 0 +#define R_SCSI1_STATUS__seq_status__WIDTH 5 +#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 +#define R_SCSI1_STATUS__seq_status__info_parity_error 1 +#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 +#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 +#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 +#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 +#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 +#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 +#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 +#define R_SCSI1_STATUS__seq_status__info_reselected 9 +#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 +#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 +#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 +#define R_SCSI1_STATUS__seq_status__info_bus_free 13 + +#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) +#define R_SCSI1_DATA_IN__data_in__BITNR 0 +#define R_SCSI1_DATA_IN__data_in__WIDTH 16 + +/* +!* Interrupt mask and status registers +!*/ + +#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) +#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_RD__nmi_pin__active 1 +#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 +#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 +#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 +#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_RD__sqe_test_error__active 1 +#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 +#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_RD__carrier_loss__active 1 +#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 +#define R_IRQ_MASK0_RD__deferred__BITNR 27 +#define R_IRQ_MASK0_RD__deferred__WIDTH 1 +#define R_IRQ_MASK0_RD__deferred__active 1 +#define R_IRQ_MASK0_RD__deferred__inactive 0 +#define R_IRQ_MASK0_RD__late_col__BITNR 26 +#define R_IRQ_MASK0_RD__late_col__WIDTH 1 +#define R_IRQ_MASK0_RD__late_col__active 1 +#define R_IRQ_MASK0_RD__late_col__inactive 0 +#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 +#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_RD__multiple_col__active 1 +#define R_IRQ_MASK0_RD__multiple_col__inactive 0 +#define R_IRQ_MASK0_RD__single_col__BITNR 24 +#define R_IRQ_MASK0_RD__single_col__WIDTH 1 +#define R_IRQ_MASK0_RD__single_col__active 1 +#define R_IRQ_MASK0_RD__single_col__inactive 0 +#define R_IRQ_MASK0_RD__congestion__BITNR 23 +#define R_IRQ_MASK0_RD__congestion__WIDTH 1 +#define R_IRQ_MASK0_RD__congestion__active 1 +#define R_IRQ_MASK0_RD__congestion__inactive 0 +#define R_IRQ_MASK0_RD__oversize__BITNR 22 +#define R_IRQ_MASK0_RD__oversize__WIDTH 1 +#define R_IRQ_MASK0_RD__oversize__active 1 +#define R_IRQ_MASK0_RD__oversize__inactive 0 +#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 +#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_RD__alignment_error__active 1 +#define R_IRQ_MASK0_RD__alignment_error__inactive 0 +#define R_IRQ_MASK0_RD__crc_error__BITNR 20 +#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 +#define R_IRQ_MASK0_RD__crc_error__active 1 +#define R_IRQ_MASK0_RD__crc_error__inactive 0 +#define R_IRQ_MASK0_RD__overrun__BITNR 19 +#define R_IRQ_MASK0_RD__overrun__WIDTH 1 +#define R_IRQ_MASK0_RD__overrun__active 1 +#define R_IRQ_MASK0_RD__overrun__inactive 0 +#define R_IRQ_MASK0_RD__underrun__BITNR 18 +#define R_IRQ_MASK0_RD__underrun__WIDTH 1 +#define R_IRQ_MASK0_RD__underrun__active 1 +#define R_IRQ_MASK0_RD__underrun__inactive 0 +#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 +#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_RD__excessive_col__active 1 +#define R_IRQ_MASK0_RD__excessive_col__inactive 0 +#define R_IRQ_MASK0_RD__mdio__BITNR 16 +#define R_IRQ_MASK0_RD__mdio__WIDTH 1 +#define R_IRQ_MASK0_RD__mdio__active 1 +#define R_IRQ_MASK0_RD__mdio__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq3__active 1 +#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq2__active 1 +#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq1__active 1 +#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq0__active 1 +#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq3__active 1 +#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 +#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 +#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_peri__active 1 +#define R_IRQ_MASK0_RD__par0_peri__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq2__active 1 +#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 +#define R_IRQ_MASK0_RD__par0_data__BITNR 9 +#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_data__active 1 +#define R_IRQ_MASK0_RD__par0_data__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq1__active 1 +#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 +#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 +#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_ready__active 1 +#define R_IRQ_MASK0_RD__par0_ready__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq0__active 1 +#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 +#define R_IRQ_MASK0_RD__mio__BITNR 8 +#define R_IRQ_MASK0_RD__mio__WIDTH 1 +#define R_IRQ_MASK0_RD__mio__active 1 +#define R_IRQ_MASK0_RD__mio__inactive 0 +#define R_IRQ_MASK0_RD__scsi0__BITNR 8 +#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 +#define R_IRQ_MASK0_RD__scsi0__active 1 +#define R_IRQ_MASK0_RD__scsi0__inactive 0 +#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_dmaend__active 1 +#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 +#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_RD__ext_dma1__active 1 +#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 +#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_RD__ext_dma0__active 1 +#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 +#define R_IRQ_MASK0_RD__timer1__BITNR 1 +#define R_IRQ_MASK0_RD__timer1__WIDTH 1 +#define R_IRQ_MASK0_RD__timer1__active 1 +#define R_IRQ_MASK0_RD__timer1__inactive 0 +#define R_IRQ_MASK0_RD__timer0__BITNR 0 +#define R_IRQ_MASK0_RD__timer0__WIDTH 1 +#define R_IRQ_MASK0_RD__timer0__active 1 +#define R_IRQ_MASK0_RD__timer0__inactive 0 + +#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) +#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 +#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 +#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 +#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 +#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 +#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 +#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 +#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 +#define R_IRQ_MASK0_CLR__deferred__BITNR 27 +#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 +#define R_IRQ_MASK0_CLR__deferred__clr 1 +#define R_IRQ_MASK0_CLR__deferred__nop 0 +#define R_IRQ_MASK0_CLR__late_col__BITNR 26 +#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__late_col__clr 1 +#define R_IRQ_MASK0_CLR__late_col__nop 0 +#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 +#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__multiple_col__clr 1 +#define R_IRQ_MASK0_CLR__multiple_col__nop 0 +#define R_IRQ_MASK0_CLR__single_col__BITNR 24 +#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__single_col__clr 1 +#define R_IRQ_MASK0_CLR__single_col__nop 0 +#define R_IRQ_MASK0_CLR__congestion__BITNR 23 +#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 +#define R_IRQ_MASK0_CLR__congestion__clr 1 +#define R_IRQ_MASK0_CLR__congestion__nop 0 +#define R_IRQ_MASK0_CLR__oversize__BITNR 22 +#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 +#define R_IRQ_MASK0_CLR__oversize__clr 1 +#define R_IRQ_MASK0_CLR__oversize__nop 0 +#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 +#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__alignment_error__clr 1 +#define R_IRQ_MASK0_CLR__alignment_error__nop 0 +#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 +#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__crc_error__clr 1 +#define R_IRQ_MASK0_CLR__crc_error__nop 0 +#define R_IRQ_MASK0_CLR__overrun__BITNR 19 +#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 +#define R_IRQ_MASK0_CLR__overrun__clr 1 +#define R_IRQ_MASK0_CLR__overrun__nop 0 +#define R_IRQ_MASK0_CLR__underrun__BITNR 18 +#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 +#define R_IRQ_MASK0_CLR__underrun__clr 1 +#define R_IRQ_MASK0_CLR__underrun__nop 0 +#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 +#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__excessive_col__clr 1 +#define R_IRQ_MASK0_CLR__excessive_col__nop 0 +#define R_IRQ_MASK0_CLR__mdio__BITNR 16 +#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 +#define R_IRQ_MASK0_CLR__mdio__clr 1 +#define R_IRQ_MASK0_CLR__mdio__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 +#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 +#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_peri__clr 1 +#define R_IRQ_MASK0_CLR__par0_peri__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 +#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 +#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_data__clr 1 +#define R_IRQ_MASK0_CLR__par0_data__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 +#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 +#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_ready__clr 1 +#define R_IRQ_MASK0_CLR__par0_ready__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 +#define R_IRQ_MASK0_CLR__mio__BITNR 8 +#define R_IRQ_MASK0_CLR__mio__WIDTH 1 +#define R_IRQ_MASK0_CLR__mio__clr 1 +#define R_IRQ_MASK0_CLR__mio__nop 0 +#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 +#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 +#define R_IRQ_MASK0_CLR__scsi0__clr 1 +#define R_IRQ_MASK0_CLR__scsi0__nop 0 +#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 +#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 +#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 +#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 +#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 +#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 +#define R_IRQ_MASK0_CLR__timer1__BITNR 1 +#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 +#define R_IRQ_MASK0_CLR__timer1__clr 1 +#define R_IRQ_MASK0_CLR__timer1__nop 0 +#define R_IRQ_MASK0_CLR__timer0__BITNR 0 +#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 +#define R_IRQ_MASK0_CLR__timer0__clr 1 +#define R_IRQ_MASK0_CLR__timer0__nop 0 + +#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) +#define R_IRQ_READ0__nmi_pin__BITNR 31 +#define R_IRQ_READ0__nmi_pin__WIDTH 1 +#define R_IRQ_READ0__nmi_pin__active 1 +#define R_IRQ_READ0__nmi_pin__inactive 0 +#define R_IRQ_READ0__watchdog_nmi__BITNR 30 +#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 +#define R_IRQ_READ0__watchdog_nmi__active 1 +#define R_IRQ_READ0__watchdog_nmi__inactive 0 +#define R_IRQ_READ0__sqe_test_error__BITNR 29 +#define R_IRQ_READ0__sqe_test_error__WIDTH 1 +#define R_IRQ_READ0__sqe_test_error__active 1 +#define R_IRQ_READ0__sqe_test_error__inactive 0 +#define R_IRQ_READ0__carrier_loss__BITNR 28 +#define R_IRQ_READ0__carrier_loss__WIDTH 1 +#define R_IRQ_READ0__carrier_loss__active 1 +#define R_IRQ_READ0__carrier_loss__inactive 0 +#define R_IRQ_READ0__deferred__BITNR 27 +#define R_IRQ_READ0__deferred__WIDTH 1 +#define R_IRQ_READ0__deferred__active 1 +#define R_IRQ_READ0__deferred__inactive 0 +#define R_IRQ_READ0__late_col__BITNR 26 +#define R_IRQ_READ0__late_col__WIDTH 1 +#define R_IRQ_READ0__late_col__active 1 +#define R_IRQ_READ0__late_col__inactive 0 +#define R_IRQ_READ0__multiple_col__BITNR 25 +#define R_IRQ_READ0__multiple_col__WIDTH 1 +#define R_IRQ_READ0__multiple_col__active 1 +#define R_IRQ_READ0__multiple_col__inactive 0 +#define R_IRQ_READ0__single_col__BITNR 24 +#define R_IRQ_READ0__single_col__WIDTH 1 +#define R_IRQ_READ0__single_col__active 1 +#define R_IRQ_READ0__single_col__inactive 0 +#define R_IRQ_READ0__congestion__BITNR 23 +#define R_IRQ_READ0__congestion__WIDTH 1 +#define R_IRQ_READ0__congestion__active 1 +#define R_IRQ_READ0__congestion__inactive 0 +#define R_IRQ_READ0__oversize__BITNR 22 +#define R_IRQ_READ0__oversize__WIDTH 1 +#define R_IRQ_READ0__oversize__active 1 +#define R_IRQ_READ0__oversize__inactive 0 +#define R_IRQ_READ0__alignment_error__BITNR 21 +#define R_IRQ_READ0__alignment_error__WIDTH 1 +#define R_IRQ_READ0__alignment_error__active 1 +#define R_IRQ_READ0__alignment_error__inactive 0 +#define R_IRQ_READ0__crc_error__BITNR 20 +#define R_IRQ_READ0__crc_error__WIDTH 1 +#define R_IRQ_READ0__crc_error__active 1 +#define R_IRQ_READ0__crc_error__inactive 0 +#define R_IRQ_READ0__overrun__BITNR 19 +#define R_IRQ_READ0__overrun__WIDTH 1 +#define R_IRQ_READ0__overrun__active 1 +#define R_IRQ_READ0__overrun__inactive 0 +#define R_IRQ_READ0__underrun__BITNR 18 +#define R_IRQ_READ0__underrun__WIDTH 1 +#define R_IRQ_READ0__underrun__active 1 +#define R_IRQ_READ0__underrun__inactive 0 +#define R_IRQ_READ0__excessive_col__BITNR 17 +#define R_IRQ_READ0__excessive_col__WIDTH 1 +#define R_IRQ_READ0__excessive_col__active 1 +#define R_IRQ_READ0__excessive_col__inactive 0 +#define R_IRQ_READ0__mdio__BITNR 16 +#define R_IRQ_READ0__mdio__WIDTH 1 +#define R_IRQ_READ0__mdio__active 1 +#define R_IRQ_READ0__mdio__inactive 0 +#define R_IRQ_READ0__ata_drq3__BITNR 15 +#define R_IRQ_READ0__ata_drq3__WIDTH 1 +#define R_IRQ_READ0__ata_drq3__active 1 +#define R_IRQ_READ0__ata_drq3__inactive 0 +#define R_IRQ_READ0__ata_drq2__BITNR 14 +#define R_IRQ_READ0__ata_drq2__WIDTH 1 +#define R_IRQ_READ0__ata_drq2__active 1 +#define R_IRQ_READ0__ata_drq2__inactive 0 +#define R_IRQ_READ0__ata_drq1__BITNR 13 +#define R_IRQ_READ0__ata_drq1__WIDTH 1 +#define R_IRQ_READ0__ata_drq1__active 1 +#define R_IRQ_READ0__ata_drq1__inactive 0 +#define R_IRQ_READ0__ata_drq0__BITNR 12 +#define R_IRQ_READ0__ata_drq0__WIDTH 1 +#define R_IRQ_READ0__ata_drq0__active 1 +#define R_IRQ_READ0__ata_drq0__inactive 0 +#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 +#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_READ0__par0_ecp_cmd__active 1 +#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 +#define R_IRQ_READ0__ata_irq3__BITNR 11 +#define R_IRQ_READ0__ata_irq3__WIDTH 1 +#define R_IRQ_READ0__ata_irq3__active 1 +#define R_IRQ_READ0__ata_irq3__inactive 0 +#define R_IRQ_READ0__par0_peri__BITNR 10 +#define R_IRQ_READ0__par0_peri__WIDTH 1 +#define R_IRQ_READ0__par0_peri__active 1 +#define R_IRQ_READ0__par0_peri__inactive 0 +#define R_IRQ_READ0__ata_irq2__BITNR 10 +#define R_IRQ_READ0__ata_irq2__WIDTH 1 +#define R_IRQ_READ0__ata_irq2__active 1 +#define R_IRQ_READ0__ata_irq2__inactive 0 +#define R_IRQ_READ0__par0_data__BITNR 9 +#define R_IRQ_READ0__par0_data__WIDTH 1 +#define R_IRQ_READ0__par0_data__active 1 +#define R_IRQ_READ0__par0_data__inactive 0 +#define R_IRQ_READ0__ata_irq1__BITNR 9 +#define R_IRQ_READ0__ata_irq1__WIDTH 1 +#define R_IRQ_READ0__ata_irq1__active 1 +#define R_IRQ_READ0__ata_irq1__inactive 0 +#define R_IRQ_READ0__par0_ready__BITNR 8 +#define R_IRQ_READ0__par0_ready__WIDTH 1 +#define R_IRQ_READ0__par0_ready__active 1 +#define R_IRQ_READ0__par0_ready__inactive 0 +#define R_IRQ_READ0__ata_irq0__BITNR 8 +#define R_IRQ_READ0__ata_irq0__WIDTH 1 +#define R_IRQ_READ0__ata_irq0__active 1 +#define R_IRQ_READ0__ata_irq0__inactive 0 +#define R_IRQ_READ0__mio__BITNR 8 +#define R_IRQ_READ0__mio__WIDTH 1 +#define R_IRQ_READ0__mio__active 1 +#define R_IRQ_READ0__mio__inactive 0 +#define R_IRQ_READ0__scsi0__BITNR 8 +#define R_IRQ_READ0__scsi0__WIDTH 1 +#define R_IRQ_READ0__scsi0__active 1 +#define R_IRQ_READ0__scsi0__inactive 0 +#define R_IRQ_READ0__ata_dmaend__BITNR 7 +#define R_IRQ_READ0__ata_dmaend__WIDTH 1 +#define R_IRQ_READ0__ata_dmaend__active 1 +#define R_IRQ_READ0__ata_dmaend__inactive 0 +#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_READ0__irq_ext_vector_nr__active 1 +#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 +#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 +#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_READ0__irq_int_vector_nr__active 1 +#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 +#define R_IRQ_READ0__ext_dma1__BITNR 3 +#define R_IRQ_READ0__ext_dma1__WIDTH 1 +#define R_IRQ_READ0__ext_dma1__active 1 +#define R_IRQ_READ0__ext_dma1__inactive 0 +#define R_IRQ_READ0__ext_dma0__BITNR 2 +#define R_IRQ_READ0__ext_dma0__WIDTH 1 +#define R_IRQ_READ0__ext_dma0__active 1 +#define R_IRQ_READ0__ext_dma0__inactive 0 +#define R_IRQ_READ0__timer1__BITNR 1 +#define R_IRQ_READ0__timer1__WIDTH 1 +#define R_IRQ_READ0__timer1__active 1 +#define R_IRQ_READ0__timer1__inactive 0 +#define R_IRQ_READ0__timer0__BITNR 0 +#define R_IRQ_READ0__timer0__WIDTH 1 +#define R_IRQ_READ0__timer0__active 1 +#define R_IRQ_READ0__timer0__inactive 0 + +#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) +#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_SET__nmi_pin__set 1 +#define R_IRQ_MASK0_SET__nmi_pin__nop 0 +#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 +#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 +#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_SET__sqe_test_error__set 1 +#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 +#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_SET__carrier_loss__set 1 +#define R_IRQ_MASK0_SET__carrier_loss__nop 0 +#define R_IRQ_MASK0_SET__deferred__BITNR 27 +#define R_IRQ_MASK0_SET__deferred__WIDTH 1 +#define R_IRQ_MASK0_SET__deferred__set 1 +#define R_IRQ_MASK0_SET__deferred__nop 0 +#define R_IRQ_MASK0_SET__late_col__BITNR 26 +#define R_IRQ_MASK0_SET__late_col__WIDTH 1 +#define R_IRQ_MASK0_SET__late_col__set 1 +#define R_IRQ_MASK0_SET__late_col__nop 0 +#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 +#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_SET__multiple_col__set 1 +#define R_IRQ_MASK0_SET__multiple_col__nop 0 +#define R_IRQ_MASK0_SET__single_col__BITNR 24 +#define R_IRQ_MASK0_SET__single_col__WIDTH 1 +#define R_IRQ_MASK0_SET__single_col__set 1 +#define R_IRQ_MASK0_SET__single_col__nop 0 +#define R_IRQ_MASK0_SET__congestion__BITNR 23 +#define R_IRQ_MASK0_SET__congestion__WIDTH 1 +#define R_IRQ_MASK0_SET__congestion__set 1 +#define R_IRQ_MASK0_SET__congestion__nop 0 +#define R_IRQ_MASK0_SET__oversize__BITNR 22 +#define R_IRQ_MASK0_SET__oversize__WIDTH 1 +#define R_IRQ_MASK0_SET__oversize__set 1 +#define R_IRQ_MASK0_SET__oversize__nop 0 +#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 +#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_SET__alignment_error__set 1 +#define R_IRQ_MASK0_SET__alignment_error__nop 0 +#define R_IRQ_MASK0_SET__crc_error__BITNR 20 +#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 +#define R_IRQ_MASK0_SET__crc_error__set 1 +#define R_IRQ_MASK0_SET__crc_error__nop 0 +#define R_IRQ_MASK0_SET__overrun__BITNR 19 +#define R_IRQ_MASK0_SET__overrun__WIDTH 1 +#define R_IRQ_MASK0_SET__overrun__set 1 +#define R_IRQ_MASK0_SET__overrun__nop 0 +#define R_IRQ_MASK0_SET__underrun__BITNR 18 +#define R_IRQ_MASK0_SET__underrun__WIDTH 1 +#define R_IRQ_MASK0_SET__underrun__set 1 +#define R_IRQ_MASK0_SET__underrun__nop 0 +#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 +#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_SET__excessive_col__set 1 +#define R_IRQ_MASK0_SET__excessive_col__nop 0 +#define R_IRQ_MASK0_SET__mdio__BITNR 16 +#define R_IRQ_MASK0_SET__mdio__WIDTH 1 +#define R_IRQ_MASK0_SET__mdio__set 1 +#define R_IRQ_MASK0_SET__mdio__nop 0 +#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq3__set 1 +#define R_IRQ_MASK0_SET__ata_drq3__nop 0 +#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq2__set 1 +#define R_IRQ_MASK0_SET__ata_drq2__nop 0 +#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq1__set 1 +#define R_IRQ_MASK0_SET__ata_drq1__nop 0 +#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq0__set 1 +#define R_IRQ_MASK0_SET__ata_drq0__nop 0 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 +#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq3__set 1 +#define R_IRQ_MASK0_SET__ata_irq3__nop 0 +#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 +#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_peri__set 1 +#define R_IRQ_MASK0_SET__par0_peri__nop 0 +#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq2__set 1 +#define R_IRQ_MASK0_SET__ata_irq2__nop 0 +#define R_IRQ_MASK0_SET__par0_data__BITNR 9 +#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_data__set 1 +#define R_IRQ_MASK0_SET__par0_data__nop 0 +#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq1__set 1 +#define R_IRQ_MASK0_SET__ata_irq1__nop 0 +#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 +#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_ready__set 1 +#define R_IRQ_MASK0_SET__par0_ready__nop 0 +#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq0__set 1 +#define R_IRQ_MASK0_SET__ata_irq0__nop 0 +#define R_IRQ_MASK0_SET__mio__BITNR 8 +#define R_IRQ_MASK0_SET__mio__WIDTH 1 +#define R_IRQ_MASK0_SET__mio__set 1 +#define R_IRQ_MASK0_SET__mio__nop 0 +#define R_IRQ_MASK0_SET__scsi0__BITNR 8 +#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 +#define R_IRQ_MASK0_SET__scsi0__set 1 +#define R_IRQ_MASK0_SET__scsi0__nop 0 +#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_dmaend__set 1 +#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 +#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_SET__ext_dma1__set 1 +#define R_IRQ_MASK0_SET__ext_dma1__nop 0 +#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_SET__ext_dma0__set 1 +#define R_IRQ_MASK0_SET__ext_dma0__nop 0 +#define R_IRQ_MASK0_SET__timer1__BITNR 1 +#define R_IRQ_MASK0_SET__timer1__WIDTH 1 +#define R_IRQ_MASK0_SET__timer1__set 1 +#define R_IRQ_MASK0_SET__timer1__nop 0 +#define R_IRQ_MASK0_SET__timer0__BITNR 0 +#define R_IRQ_MASK0_SET__timer0__WIDTH 1 +#define R_IRQ_MASK0_SET__timer0__set 1 +#define R_IRQ_MASK0_SET__timer0__nop 0 + +#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) +#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 +#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int7__active 1 +#define R_IRQ_MASK1_RD__sw_int7__inactive 0 +#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 +#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int6__active 1 +#define R_IRQ_MASK1_RD__sw_int6__inactive 0 +#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 +#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int5__active 1 +#define R_IRQ_MASK1_RD__sw_int5__inactive 0 +#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 +#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int4__active 1 +#define R_IRQ_MASK1_RD__sw_int4__inactive 0 +#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 +#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int3__active 1 +#define R_IRQ_MASK1_RD__sw_int3__inactive 0 +#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 +#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int2__active 1 +#define R_IRQ_MASK1_RD__sw_int2__inactive 0 +#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 +#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int1__active 1 +#define R_IRQ_MASK1_RD__sw_int1__inactive 0 +#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 +#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int0__active 1 +#define R_IRQ_MASK1_RD__sw_int0__inactive 0 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 +#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 +#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_peri__active 1 +#define R_IRQ_MASK1_RD__par1_peri__inactive 0 +#define R_IRQ_MASK1_RD__par1_data__BITNR 17 +#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_data__active 1 +#define R_IRQ_MASK1_RD__par1_data__inactive 0 +#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 +#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_ready__active 1 +#define R_IRQ_MASK1_RD__par1_ready__inactive 0 +#define R_IRQ_MASK1_RD__scsi1__BITNR 16 +#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 +#define R_IRQ_MASK1_RD__scsi1__active 1 +#define R_IRQ_MASK1_RD__scsi1__inactive 0 +#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser3_ready__active 1 +#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 +#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser3_data__active 1 +#define R_IRQ_MASK1_RD__ser3_data__inactive 0 +#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser2_ready__active 1 +#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 +#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser2_data__active 1 +#define R_IRQ_MASK1_RD__ser2_data__inactive 0 +#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser1_ready__active 1 +#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 +#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser1_data__active 1 +#define R_IRQ_MASK1_RD__ser1_data__inactive 0 +#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser0_ready__active 1 +#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 +#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser0_data__active 1 +#define R_IRQ_MASK1_RD__ser0_data__inactive 0 +#define R_IRQ_MASK1_RD__pa7__BITNR 7 +#define R_IRQ_MASK1_RD__pa7__WIDTH 1 +#define R_IRQ_MASK1_RD__pa7__active 1 +#define R_IRQ_MASK1_RD__pa7__inactive 0 +#define R_IRQ_MASK1_RD__pa6__BITNR 6 +#define R_IRQ_MASK1_RD__pa6__WIDTH 1 +#define R_IRQ_MASK1_RD__pa6__active 1 +#define R_IRQ_MASK1_RD__pa6__inactive 0 +#define R_IRQ_MASK1_RD__pa5__BITNR 5 +#define R_IRQ_MASK1_RD__pa5__WIDTH 1 +#define R_IRQ_MASK1_RD__pa5__active 1 +#define R_IRQ_MASK1_RD__pa5__inactive 0 +#define R_IRQ_MASK1_RD__pa4__BITNR 4 +#define R_IRQ_MASK1_RD__pa4__WIDTH 1 +#define R_IRQ_MASK1_RD__pa4__active 1 +#define R_IRQ_MASK1_RD__pa4__inactive 0 +#define R_IRQ_MASK1_RD__pa3__BITNR 3 +#define R_IRQ_MASK1_RD__pa3__WIDTH 1 +#define R_IRQ_MASK1_RD__pa3__active 1 +#define R_IRQ_MASK1_RD__pa3__inactive 0 +#define R_IRQ_MASK1_RD__pa2__BITNR 2 +#define R_IRQ_MASK1_RD__pa2__WIDTH 1 +#define R_IRQ_MASK1_RD__pa2__active 1 +#define R_IRQ_MASK1_RD__pa2__inactive 0 +#define R_IRQ_MASK1_RD__pa1__BITNR 1 +#define R_IRQ_MASK1_RD__pa1__WIDTH 1 +#define R_IRQ_MASK1_RD__pa1__active 1 +#define R_IRQ_MASK1_RD__pa1__inactive 0 +#define R_IRQ_MASK1_RD__pa0__BITNR 0 +#define R_IRQ_MASK1_RD__pa0__WIDTH 1 +#define R_IRQ_MASK1_RD__pa0__active 1 +#define R_IRQ_MASK1_RD__pa0__inactive 0 + +#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) +#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 +#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int7__clr 1 +#define R_IRQ_MASK1_CLR__sw_int7__nop 0 +#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 +#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int6__clr 1 +#define R_IRQ_MASK1_CLR__sw_int6__nop 0 +#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 +#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int5__clr 1 +#define R_IRQ_MASK1_CLR__sw_int5__nop 0 +#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 +#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int4__clr 1 +#define R_IRQ_MASK1_CLR__sw_int4__nop 0 +#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 +#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int3__clr 1 +#define R_IRQ_MASK1_CLR__sw_int3__nop 0 +#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 +#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int2__clr 1 +#define R_IRQ_MASK1_CLR__sw_int2__nop 0 +#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 +#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int1__clr 1 +#define R_IRQ_MASK1_CLR__sw_int1__nop 0 +#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 +#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int0__clr 1 +#define R_IRQ_MASK1_CLR__sw_int0__nop 0 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 +#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 +#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_peri__clr 1 +#define R_IRQ_MASK1_CLR__par1_peri__nop 0 +#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 +#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_data__clr 1 +#define R_IRQ_MASK1_CLR__par1_data__nop 0 +#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 +#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_ready__clr 1 +#define R_IRQ_MASK1_CLR__par1_ready__nop 0 +#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 +#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 +#define R_IRQ_MASK1_CLR__scsi1__clr 1 +#define R_IRQ_MASK1_CLR__scsi1__nop 0 +#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 +#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser3_data__clr 1 +#define R_IRQ_MASK1_CLR__ser3_data__nop 0 +#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 +#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser2_data__clr 1 +#define R_IRQ_MASK1_CLR__ser2_data__nop 0 +#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 +#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser1_data__clr 1 +#define R_IRQ_MASK1_CLR__ser1_data__nop 0 +#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 +#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser0_data__clr 1 +#define R_IRQ_MASK1_CLR__ser0_data__nop 0 +#define R_IRQ_MASK1_CLR__pa7__BITNR 7 +#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa7__clr 1 +#define R_IRQ_MASK1_CLR__pa7__nop 0 +#define R_IRQ_MASK1_CLR__pa6__BITNR 6 +#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa6__clr 1 +#define R_IRQ_MASK1_CLR__pa6__nop 0 +#define R_IRQ_MASK1_CLR__pa5__BITNR 5 +#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa5__clr 1 +#define R_IRQ_MASK1_CLR__pa5__nop 0 +#define R_IRQ_MASK1_CLR__pa4__BITNR 4 +#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa4__clr 1 +#define R_IRQ_MASK1_CLR__pa4__nop 0 +#define R_IRQ_MASK1_CLR__pa3__BITNR 3 +#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa3__clr 1 +#define R_IRQ_MASK1_CLR__pa3__nop 0 +#define R_IRQ_MASK1_CLR__pa2__BITNR 2 +#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa2__clr 1 +#define R_IRQ_MASK1_CLR__pa2__nop 0 +#define R_IRQ_MASK1_CLR__pa1__BITNR 1 +#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa1__clr 1 +#define R_IRQ_MASK1_CLR__pa1__nop 0 +#define R_IRQ_MASK1_CLR__pa0__BITNR 0 +#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa0__clr 1 +#define R_IRQ_MASK1_CLR__pa0__nop 0 + +#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) +#define R_IRQ_READ1__sw_int7__BITNR 31 +#define R_IRQ_READ1__sw_int7__WIDTH 1 +#define R_IRQ_READ1__sw_int7__active 1 +#define R_IRQ_READ1__sw_int7__inactive 0 +#define R_IRQ_READ1__sw_int6__BITNR 30 +#define R_IRQ_READ1__sw_int6__WIDTH 1 +#define R_IRQ_READ1__sw_int6__active 1 +#define R_IRQ_READ1__sw_int6__inactive 0 +#define R_IRQ_READ1__sw_int5__BITNR 29 +#define R_IRQ_READ1__sw_int5__WIDTH 1 +#define R_IRQ_READ1__sw_int5__active 1 +#define R_IRQ_READ1__sw_int5__inactive 0 +#define R_IRQ_READ1__sw_int4__BITNR 28 +#define R_IRQ_READ1__sw_int4__WIDTH 1 +#define R_IRQ_READ1__sw_int4__active 1 +#define R_IRQ_READ1__sw_int4__inactive 0 +#define R_IRQ_READ1__sw_int3__BITNR 27 +#define R_IRQ_READ1__sw_int3__WIDTH 1 +#define R_IRQ_READ1__sw_int3__active 1 +#define R_IRQ_READ1__sw_int3__inactive 0 +#define R_IRQ_READ1__sw_int2__BITNR 26 +#define R_IRQ_READ1__sw_int2__WIDTH 1 +#define R_IRQ_READ1__sw_int2__active 1 +#define R_IRQ_READ1__sw_int2__inactive 0 +#define R_IRQ_READ1__sw_int1__BITNR 25 +#define R_IRQ_READ1__sw_int1__WIDTH 1 +#define R_IRQ_READ1__sw_int1__active 1 +#define R_IRQ_READ1__sw_int1__inactive 0 +#define R_IRQ_READ1__sw_int0__BITNR 24 +#define R_IRQ_READ1__sw_int0__WIDTH 1 +#define R_IRQ_READ1__sw_int0__active 1 +#define R_IRQ_READ1__sw_int0__inactive 0 +#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 +#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_READ1__par1_ecp_cmd__active 1 +#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 +#define R_IRQ_READ1__par1_peri__BITNR 18 +#define R_IRQ_READ1__par1_peri__WIDTH 1 +#define R_IRQ_READ1__par1_peri__active 1 +#define R_IRQ_READ1__par1_peri__inactive 0 +#define R_IRQ_READ1__par1_data__BITNR 17 +#define R_IRQ_READ1__par1_data__WIDTH 1 +#define R_IRQ_READ1__par1_data__active 1 +#define R_IRQ_READ1__par1_data__inactive 0 +#define R_IRQ_READ1__par1_ready__BITNR 16 +#define R_IRQ_READ1__par1_ready__WIDTH 1 +#define R_IRQ_READ1__par1_ready__active 1 +#define R_IRQ_READ1__par1_ready__inactive 0 +#define R_IRQ_READ1__scsi1__BITNR 16 +#define R_IRQ_READ1__scsi1__WIDTH 1 +#define R_IRQ_READ1__scsi1__active 1 +#define R_IRQ_READ1__scsi1__inactive 0 +#define R_IRQ_READ1__ser3_ready__BITNR 15 +#define R_IRQ_READ1__ser3_ready__WIDTH 1 +#define R_IRQ_READ1__ser3_ready__active 1 +#define R_IRQ_READ1__ser3_ready__inactive 0 +#define R_IRQ_READ1__ser3_data__BITNR 14 +#define R_IRQ_READ1__ser3_data__WIDTH 1 +#define R_IRQ_READ1__ser3_data__active 1 +#define R_IRQ_READ1__ser3_data__inactive 0 +#define R_IRQ_READ1__ser2_ready__BITNR 13 +#define R_IRQ_READ1__ser2_ready__WIDTH 1 +#define R_IRQ_READ1__ser2_ready__active 1 +#define R_IRQ_READ1__ser2_ready__inactive 0 +#define R_IRQ_READ1__ser2_data__BITNR 12 +#define R_IRQ_READ1__ser2_data__WIDTH 1 +#define R_IRQ_READ1__ser2_data__active 1 +#define R_IRQ_READ1__ser2_data__inactive 0 +#define R_IRQ_READ1__ser1_ready__BITNR 11 +#define R_IRQ_READ1__ser1_ready__WIDTH 1 +#define R_IRQ_READ1__ser1_ready__active 1 +#define R_IRQ_READ1__ser1_ready__inactive 0 +#define R_IRQ_READ1__ser1_data__BITNR 10 +#define R_IRQ_READ1__ser1_data__WIDTH 1 +#define R_IRQ_READ1__ser1_data__active 1 +#define R_IRQ_READ1__ser1_data__inactive 0 +#define R_IRQ_READ1__ser0_ready__BITNR 9 +#define R_IRQ_READ1__ser0_ready__WIDTH 1 +#define R_IRQ_READ1__ser0_ready__active 1 +#define R_IRQ_READ1__ser0_ready__inactive 0 +#define R_IRQ_READ1__ser0_data__BITNR 8 +#define R_IRQ_READ1__ser0_data__WIDTH 1 +#define R_IRQ_READ1__ser0_data__active 1 +#define R_IRQ_READ1__ser0_data__inactive 0 +#define R_IRQ_READ1__pa7__BITNR 7 +#define R_IRQ_READ1__pa7__WIDTH 1 +#define R_IRQ_READ1__pa7__active 1 +#define R_IRQ_READ1__pa7__inactive 0 +#define R_IRQ_READ1__pa6__BITNR 6 +#define R_IRQ_READ1__pa6__WIDTH 1 +#define R_IRQ_READ1__pa6__active 1 +#define R_IRQ_READ1__pa6__inactive 0 +#define R_IRQ_READ1__pa5__BITNR 5 +#define R_IRQ_READ1__pa5__WIDTH 1 +#define R_IRQ_READ1__pa5__active 1 +#define R_IRQ_READ1__pa5__inactive 0 +#define R_IRQ_READ1__pa4__BITNR 4 +#define R_IRQ_READ1__pa4__WIDTH 1 +#define R_IRQ_READ1__pa4__active 1 +#define R_IRQ_READ1__pa4__inactive 0 +#define R_IRQ_READ1__pa3__BITNR 3 +#define R_IRQ_READ1__pa3__WIDTH 1 +#define R_IRQ_READ1__pa3__active 1 +#define R_IRQ_READ1__pa3__inactive 0 +#define R_IRQ_READ1__pa2__BITNR 2 +#define R_IRQ_READ1__pa2__WIDTH 1 +#define R_IRQ_READ1__pa2__active 1 +#define R_IRQ_READ1__pa2__inactive 0 +#define R_IRQ_READ1__pa1__BITNR 1 +#define R_IRQ_READ1__pa1__WIDTH 1 +#define R_IRQ_READ1__pa1__active 1 +#define R_IRQ_READ1__pa1__inactive 0 +#define R_IRQ_READ1__pa0__BITNR 0 +#define R_IRQ_READ1__pa0__WIDTH 1 +#define R_IRQ_READ1__pa0__active 1 +#define R_IRQ_READ1__pa0__inactive 0 + +#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) +#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 +#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int7__set 1 +#define R_IRQ_MASK1_SET__sw_int7__nop 0 +#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 +#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int6__set 1 +#define R_IRQ_MASK1_SET__sw_int6__nop 0 +#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 +#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int5__set 1 +#define R_IRQ_MASK1_SET__sw_int5__nop 0 +#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 +#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int4__set 1 +#define R_IRQ_MASK1_SET__sw_int4__nop 0 +#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 +#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int3__set 1 +#define R_IRQ_MASK1_SET__sw_int3__nop 0 +#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 +#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int2__set 1 +#define R_IRQ_MASK1_SET__sw_int2__nop 0 +#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 +#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int1__set 1 +#define R_IRQ_MASK1_SET__sw_int1__nop 0 +#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 +#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int0__set 1 +#define R_IRQ_MASK1_SET__sw_int0__nop 0 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 +#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 +#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_peri__set 1 +#define R_IRQ_MASK1_SET__par1_peri__nop 0 +#define R_IRQ_MASK1_SET__par1_data__BITNR 17 +#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_data__set 1 +#define R_IRQ_MASK1_SET__par1_data__nop 0 +#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 +#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_ready__set 1 +#define R_IRQ_MASK1_SET__par1_ready__nop 0 +#define R_IRQ_MASK1_SET__scsi1__BITNR 16 +#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 +#define R_IRQ_MASK1_SET__scsi1__set 1 +#define R_IRQ_MASK1_SET__scsi1__nop 0 +#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser3_ready__set 1 +#define R_IRQ_MASK1_SET__ser3_ready__nop 0 +#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 +#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser3_data__set 1 +#define R_IRQ_MASK1_SET__ser3_data__nop 0 +#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser2_ready__set 1 +#define R_IRQ_MASK1_SET__ser2_ready__nop 0 +#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 +#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser2_data__set 1 +#define R_IRQ_MASK1_SET__ser2_data__nop 0 +#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser1_ready__set 1 +#define R_IRQ_MASK1_SET__ser1_ready__nop 0 +#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 +#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser1_data__set 1 +#define R_IRQ_MASK1_SET__ser1_data__nop 0 +#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser0_ready__set 1 +#define R_IRQ_MASK1_SET__ser0_ready__nop 0 +#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 +#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser0_data__set 1 +#define R_IRQ_MASK1_SET__ser0_data__nop 0 +#define R_IRQ_MASK1_SET__pa7__BITNR 7 +#define R_IRQ_MASK1_SET__pa7__WIDTH 1 +#define R_IRQ_MASK1_SET__pa7__set 1 +#define R_IRQ_MASK1_SET__pa7__nop 0 +#define R_IRQ_MASK1_SET__pa6__BITNR 6 +#define R_IRQ_MASK1_SET__pa6__WIDTH 1 +#define R_IRQ_MASK1_SET__pa6__set 1 +#define R_IRQ_MASK1_SET__pa6__nop 0 +#define R_IRQ_MASK1_SET__pa5__BITNR 5 +#define R_IRQ_MASK1_SET__pa5__WIDTH 1 +#define R_IRQ_MASK1_SET__pa5__set 1 +#define R_IRQ_MASK1_SET__pa5__nop 0 +#define R_IRQ_MASK1_SET__pa4__BITNR 4 +#define R_IRQ_MASK1_SET__pa4__WIDTH 1 +#define R_IRQ_MASK1_SET__pa4__set 1 +#define R_IRQ_MASK1_SET__pa4__nop 0 +#define R_IRQ_MASK1_SET__pa3__BITNR 3 +#define R_IRQ_MASK1_SET__pa3__WIDTH 1 +#define R_IRQ_MASK1_SET__pa3__set 1 +#define R_IRQ_MASK1_SET__pa3__nop 0 +#define R_IRQ_MASK1_SET__pa2__BITNR 2 +#define R_IRQ_MASK1_SET__pa2__WIDTH 1 +#define R_IRQ_MASK1_SET__pa2__set 1 +#define R_IRQ_MASK1_SET__pa2__nop 0 +#define R_IRQ_MASK1_SET__pa1__BITNR 1 +#define R_IRQ_MASK1_SET__pa1__WIDTH 1 +#define R_IRQ_MASK1_SET__pa1__set 1 +#define R_IRQ_MASK1_SET__pa1__nop 0 +#define R_IRQ_MASK1_SET__pa0__BITNR 0 +#define R_IRQ_MASK1_SET__pa0__WIDTH 1 +#define R_IRQ_MASK1_SET__pa0__set 1 +#define R_IRQ_MASK1_SET__pa0__nop 0 + +#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) +#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma9_eop__active 1 +#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma9_descr__active 1 +#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_eop__active 1 +#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma7_eop__active 1 +#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma7_descr__active 1 +#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma6_eop__active 1 +#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma6_descr__active 1 +#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma5_eop__active 1 +#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma5_descr__active 1 +#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma4_eop__active 1 +#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma4_descr__active 1 +#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma3_eop__active 1 +#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma3_descr__active 1 +#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma2_eop__active 1 +#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma2_descr__active 1 +#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma1_eop__active 1 +#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma1_descr__active 1 +#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma0_eop__active 1 +#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma0_descr__active 1 +#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 + +#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 + +#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) +#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 +#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub3_descr__active 1 +#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 +#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub2_descr__active 1 +#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 +#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub1_descr__active 1 +#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 +#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub0_descr__active 1 +#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 +#define R_IRQ_READ2__dma9_eop__BITNR 19 +#define R_IRQ_READ2__dma9_eop__WIDTH 1 +#define R_IRQ_READ2__dma9_eop__active 1 +#define R_IRQ_READ2__dma9_eop__inactive 0 +#define R_IRQ_READ2__dma9_descr__BITNR 18 +#define R_IRQ_READ2__dma9_descr__WIDTH 1 +#define R_IRQ_READ2__dma9_descr__active 1 +#define R_IRQ_READ2__dma9_descr__inactive 0 +#define R_IRQ_READ2__dma8_eop__BITNR 17 +#define R_IRQ_READ2__dma8_eop__WIDTH 1 +#define R_IRQ_READ2__dma8_eop__active 1 +#define R_IRQ_READ2__dma8_eop__inactive 0 +#define R_IRQ_READ2__dma8_descr__BITNR 16 +#define R_IRQ_READ2__dma8_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_descr__active 1 +#define R_IRQ_READ2__dma8_descr__inactive 0 +#define R_IRQ_READ2__dma7_eop__BITNR 15 +#define R_IRQ_READ2__dma7_eop__WIDTH 1 +#define R_IRQ_READ2__dma7_eop__active 1 +#define R_IRQ_READ2__dma7_eop__inactive 0 +#define R_IRQ_READ2__dma7_descr__BITNR 14 +#define R_IRQ_READ2__dma7_descr__WIDTH 1 +#define R_IRQ_READ2__dma7_descr__active 1 +#define R_IRQ_READ2__dma7_descr__inactive 0 +#define R_IRQ_READ2__dma6_eop__BITNR 13 +#define R_IRQ_READ2__dma6_eop__WIDTH 1 +#define R_IRQ_READ2__dma6_eop__active 1 +#define R_IRQ_READ2__dma6_eop__inactive 0 +#define R_IRQ_READ2__dma6_descr__BITNR 12 +#define R_IRQ_READ2__dma6_descr__WIDTH 1 +#define R_IRQ_READ2__dma6_descr__active 1 +#define R_IRQ_READ2__dma6_descr__inactive 0 +#define R_IRQ_READ2__dma5_eop__BITNR 11 +#define R_IRQ_READ2__dma5_eop__WIDTH 1 +#define R_IRQ_READ2__dma5_eop__active 1 +#define R_IRQ_READ2__dma5_eop__inactive 0 +#define R_IRQ_READ2__dma5_descr__BITNR 10 +#define R_IRQ_READ2__dma5_descr__WIDTH 1 +#define R_IRQ_READ2__dma5_descr__active 1 +#define R_IRQ_READ2__dma5_descr__inactive 0 +#define R_IRQ_READ2__dma4_eop__BITNR 9 +#define R_IRQ_READ2__dma4_eop__WIDTH 1 +#define R_IRQ_READ2__dma4_eop__active 1 +#define R_IRQ_READ2__dma4_eop__inactive 0 +#define R_IRQ_READ2__dma4_descr__BITNR 8 +#define R_IRQ_READ2__dma4_descr__WIDTH 1 +#define R_IRQ_READ2__dma4_descr__active 1 +#define R_IRQ_READ2__dma4_descr__inactive 0 +#define R_IRQ_READ2__dma3_eop__BITNR 7 +#define R_IRQ_READ2__dma3_eop__WIDTH 1 +#define R_IRQ_READ2__dma3_eop__active 1 +#define R_IRQ_READ2__dma3_eop__inactive 0 +#define R_IRQ_READ2__dma3_descr__BITNR 6 +#define R_IRQ_READ2__dma3_descr__WIDTH 1 +#define R_IRQ_READ2__dma3_descr__active 1 +#define R_IRQ_READ2__dma3_descr__inactive 0 +#define R_IRQ_READ2__dma2_eop__BITNR 5 +#define R_IRQ_READ2__dma2_eop__WIDTH 1 +#define R_IRQ_READ2__dma2_eop__active 1 +#define R_IRQ_READ2__dma2_eop__inactive 0 +#define R_IRQ_READ2__dma2_descr__BITNR 4 +#define R_IRQ_READ2__dma2_descr__WIDTH 1 +#define R_IRQ_READ2__dma2_descr__active 1 +#define R_IRQ_READ2__dma2_descr__inactive 0 +#define R_IRQ_READ2__dma1_eop__BITNR 3 +#define R_IRQ_READ2__dma1_eop__WIDTH 1 +#define R_IRQ_READ2__dma1_eop__active 1 +#define R_IRQ_READ2__dma1_eop__inactive 0 +#define R_IRQ_READ2__dma1_descr__BITNR 2 +#define R_IRQ_READ2__dma1_descr__WIDTH 1 +#define R_IRQ_READ2__dma1_descr__active 1 +#define R_IRQ_READ2__dma1_descr__inactive 0 +#define R_IRQ_READ2__dma0_eop__BITNR 1 +#define R_IRQ_READ2__dma0_eop__WIDTH 1 +#define R_IRQ_READ2__dma0_eop__active 1 +#define R_IRQ_READ2__dma0_eop__inactive 0 +#define R_IRQ_READ2__dma0_descr__BITNR 0 +#define R_IRQ_READ2__dma0_descr__WIDTH 1 +#define R_IRQ_READ2__dma0_descr__active 1 +#define R_IRQ_READ2__dma0_descr__inactive 0 + +#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) +#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 +#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma9_eop__set 1 +#define R_IRQ_MASK2_SET__dma9_eop__nop 0 +#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma9_descr__set 1 +#define R_IRQ_MASK2_SET__dma9_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_eop__set 1 +#define R_IRQ_MASK2_SET__dma8_eop__nop 0 +#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_descr__nop 0 +#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma7_eop__set 1 +#define R_IRQ_MASK2_SET__dma7_eop__nop 0 +#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma7_descr__set 1 +#define R_IRQ_MASK2_SET__dma7_descr__nop 0 +#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma6_eop__set 1 +#define R_IRQ_MASK2_SET__dma6_eop__nop 0 +#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma6_descr__set 1 +#define R_IRQ_MASK2_SET__dma6_descr__nop 0 +#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma5_eop__set 1 +#define R_IRQ_MASK2_SET__dma5_eop__nop 0 +#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma5_descr__set 1 +#define R_IRQ_MASK2_SET__dma5_descr__nop 0 +#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma4_eop__set 1 +#define R_IRQ_MASK2_SET__dma4_eop__nop 0 +#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma4_descr__set 1 +#define R_IRQ_MASK2_SET__dma4_descr__nop 0 +#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma3_eop__set 1 +#define R_IRQ_MASK2_SET__dma3_eop__nop 0 +#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma3_descr__set 1 +#define R_IRQ_MASK2_SET__dma3_descr__nop 0 +#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma2_eop__set 1 +#define R_IRQ_MASK2_SET__dma2_eop__nop 0 +#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma2_descr__set 1 +#define R_IRQ_MASK2_SET__dma2_descr__nop 0 +#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma1_eop__set 1 +#define R_IRQ_MASK2_SET__dma1_eop__nop 0 +#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma1_descr__set 1 +#define R_IRQ_MASK2_SET__dma1_descr__nop 0 +#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma0_eop__set 1 +#define R_IRQ_MASK2_SET__dma0_eop__nop 0 +#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma0_descr__set 1 +#define R_IRQ_MASK2_SET__dma0_descr__nop 0 + +#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) +#define R_VECT_MASK_RD__usb__BITNR 31 +#define R_VECT_MASK_RD__usb__WIDTH 1 +#define R_VECT_MASK_RD__usb__active 1 +#define R_VECT_MASK_RD__usb__inactive 0 +#define R_VECT_MASK_RD__dma9__BITNR 25 +#define R_VECT_MASK_RD__dma9__WIDTH 1 +#define R_VECT_MASK_RD__dma9__active 1 +#define R_VECT_MASK_RD__dma9__inactive 0 +#define R_VECT_MASK_RD__dma8__BITNR 24 +#define R_VECT_MASK_RD__dma8__WIDTH 1 +#define R_VECT_MASK_RD__dma8__active 1 +#define R_VECT_MASK_RD__dma8__inactive 0 +#define R_VECT_MASK_RD__dma7__BITNR 23 +#define R_VECT_MASK_RD__dma7__WIDTH 1 +#define R_VECT_MASK_RD__dma7__active 1 +#define R_VECT_MASK_RD__dma7__inactive 0 +#define R_VECT_MASK_RD__dma6__BITNR 22 +#define R_VECT_MASK_RD__dma6__WIDTH 1 +#define R_VECT_MASK_RD__dma6__active 1 +#define R_VECT_MASK_RD__dma6__inactive 0 +#define R_VECT_MASK_RD__dma5__BITNR 21 +#define R_VECT_MASK_RD__dma5__WIDTH 1 +#define R_VECT_MASK_RD__dma5__active 1 +#define R_VECT_MASK_RD__dma5__inactive 0 +#define R_VECT_MASK_RD__dma4__BITNR 20 +#define R_VECT_MASK_RD__dma4__WIDTH 1 +#define R_VECT_MASK_RD__dma4__active 1 +#define R_VECT_MASK_RD__dma4__inactive 0 +#define R_VECT_MASK_RD__dma3__BITNR 19 +#define R_VECT_MASK_RD__dma3__WIDTH 1 +#define R_VECT_MASK_RD__dma3__active 1 +#define R_VECT_MASK_RD__dma3__inactive 0 +#define R_VECT_MASK_RD__dma2__BITNR 18 +#define R_VECT_MASK_RD__dma2__WIDTH 1 +#define R_VECT_MASK_RD__dma2__active 1 +#define R_VECT_MASK_RD__dma2__inactive 0 +#define R_VECT_MASK_RD__dma1__BITNR 17 +#define R_VECT_MASK_RD__dma1__WIDTH 1 +#define R_VECT_MASK_RD__dma1__active 1 +#define R_VECT_MASK_RD__dma1__inactive 0 +#define R_VECT_MASK_RD__dma0__BITNR 16 +#define R_VECT_MASK_RD__dma0__WIDTH 1 +#define R_VECT_MASK_RD__dma0__active 1 +#define R_VECT_MASK_RD__dma0__inactive 0 +#define R_VECT_MASK_RD__ext_dma1__BITNR 13 +#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 +#define R_VECT_MASK_RD__ext_dma1__active 1 +#define R_VECT_MASK_RD__ext_dma1__inactive 0 +#define R_VECT_MASK_RD__ext_dma0__BITNR 12 +#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 +#define R_VECT_MASK_RD__ext_dma0__active 1 +#define R_VECT_MASK_RD__ext_dma0__inactive 0 +#define R_VECT_MASK_RD__pa__BITNR 11 +#define R_VECT_MASK_RD__pa__WIDTH 1 +#define R_VECT_MASK_RD__pa__active 1 +#define R_VECT_MASK_RD__pa__inactive 0 +#define R_VECT_MASK_RD__irq_intnr__BITNR 10 +#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 +#define R_VECT_MASK_RD__irq_intnr__active 1 +#define R_VECT_MASK_RD__irq_intnr__inactive 0 +#define R_VECT_MASK_RD__sw__BITNR 9 +#define R_VECT_MASK_RD__sw__WIDTH 1 +#define R_VECT_MASK_RD__sw__active 1 +#define R_VECT_MASK_RD__sw__inactive 0 +#define R_VECT_MASK_RD__serial__BITNR 8 +#define R_VECT_MASK_RD__serial__WIDTH 1 +#define R_VECT_MASK_RD__serial__active 1 +#define R_VECT_MASK_RD__serial__inactive 0 +#define R_VECT_MASK_RD__snmp__BITNR 7 +#define R_VECT_MASK_RD__snmp__WIDTH 1 +#define R_VECT_MASK_RD__snmp__active 1 +#define R_VECT_MASK_RD__snmp__inactive 0 +#define R_VECT_MASK_RD__network__BITNR 6 +#define R_VECT_MASK_RD__network__WIDTH 1 +#define R_VECT_MASK_RD__network__active 1 +#define R_VECT_MASK_RD__network__inactive 0 +#define R_VECT_MASK_RD__scsi1__BITNR 5 +#define R_VECT_MASK_RD__scsi1__WIDTH 1 +#define R_VECT_MASK_RD__scsi1__active 1 +#define R_VECT_MASK_RD__scsi1__inactive 0 +#define R_VECT_MASK_RD__par1__BITNR 5 +#define R_VECT_MASK_RD__par1__WIDTH 1 +#define R_VECT_MASK_RD__par1__active 1 +#define R_VECT_MASK_RD__par1__inactive 0 +#define R_VECT_MASK_RD__scsi0__BITNR 4 +#define R_VECT_MASK_RD__scsi0__WIDTH 1 +#define R_VECT_MASK_RD__scsi0__active 1 +#define R_VECT_MASK_RD__scsi0__inactive 0 +#define R_VECT_MASK_RD__par0__BITNR 4 +#define R_VECT_MASK_RD__par0__WIDTH 1 +#define R_VECT_MASK_RD__par0__active 1 +#define R_VECT_MASK_RD__par0__inactive 0 +#define R_VECT_MASK_RD__ata__BITNR 4 +#define R_VECT_MASK_RD__ata__WIDTH 1 +#define R_VECT_MASK_RD__ata__active 1 +#define R_VECT_MASK_RD__ata__inactive 0 +#define R_VECT_MASK_RD__mio__BITNR 4 +#define R_VECT_MASK_RD__mio__WIDTH 1 +#define R_VECT_MASK_RD__mio__active 1 +#define R_VECT_MASK_RD__mio__inactive 0 +#define R_VECT_MASK_RD__timer1__BITNR 3 +#define R_VECT_MASK_RD__timer1__WIDTH 1 +#define R_VECT_MASK_RD__timer1__active 1 +#define R_VECT_MASK_RD__timer1__inactive 0 +#define R_VECT_MASK_RD__timer0__BITNR 2 +#define R_VECT_MASK_RD__timer0__WIDTH 1 +#define R_VECT_MASK_RD__timer0__active 1 +#define R_VECT_MASK_RD__timer0__inactive 0 +#define R_VECT_MASK_RD__nmi__BITNR 1 +#define R_VECT_MASK_RD__nmi__WIDTH 1 +#define R_VECT_MASK_RD__nmi__active 1 +#define R_VECT_MASK_RD__nmi__inactive 0 +#define R_VECT_MASK_RD__some__BITNR 0 +#define R_VECT_MASK_RD__some__WIDTH 1 +#define R_VECT_MASK_RD__some__active 1 +#define R_VECT_MASK_RD__some__inactive 0 + +#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) +#define R_VECT_MASK_CLR__usb__BITNR 31 +#define R_VECT_MASK_CLR__usb__WIDTH 1 +#define R_VECT_MASK_CLR__usb__clr 1 +#define R_VECT_MASK_CLR__usb__nop 0 +#define R_VECT_MASK_CLR__dma9__BITNR 25 +#define R_VECT_MASK_CLR__dma9__WIDTH 1 +#define R_VECT_MASK_CLR__dma9__clr 1 +#define R_VECT_MASK_CLR__dma9__nop 0 +#define R_VECT_MASK_CLR__dma8__BITNR 24 +#define R_VECT_MASK_CLR__dma8__WIDTH 1 +#define R_VECT_MASK_CLR__dma8__clr 1 +#define R_VECT_MASK_CLR__dma8__nop 0 +#define R_VECT_MASK_CLR__dma7__BITNR 23 +#define R_VECT_MASK_CLR__dma7__WIDTH 1 +#define R_VECT_MASK_CLR__dma7__clr 1 +#define R_VECT_MASK_CLR__dma7__nop 0 +#define R_VECT_MASK_CLR__dma6__BITNR 22 +#define R_VECT_MASK_CLR__dma6__WIDTH 1 +#define R_VECT_MASK_CLR__dma6__clr 1 +#define R_VECT_MASK_CLR__dma6__nop 0 +#define R_VECT_MASK_CLR__dma5__BITNR 21 +#define R_VECT_MASK_CLR__dma5__WIDTH 1 +#define R_VECT_MASK_CLR__dma5__clr 1 +#define R_VECT_MASK_CLR__dma5__nop 0 +#define R_VECT_MASK_CLR__dma4__BITNR 20 +#define R_VECT_MASK_CLR__dma4__WIDTH 1 +#define R_VECT_MASK_CLR__dma4__clr 1 +#define R_VECT_MASK_CLR__dma4__nop 0 +#define R_VECT_MASK_CLR__dma3__BITNR 19 +#define R_VECT_MASK_CLR__dma3__WIDTH 1 +#define R_VECT_MASK_CLR__dma3__clr 1 +#define R_VECT_MASK_CLR__dma3__nop 0 +#define R_VECT_MASK_CLR__dma2__BITNR 18 +#define R_VECT_MASK_CLR__dma2__WIDTH 1 +#define R_VECT_MASK_CLR__dma2__clr 1 +#define R_VECT_MASK_CLR__dma2__nop 0 +#define R_VECT_MASK_CLR__dma1__BITNR 17 +#define R_VECT_MASK_CLR__dma1__WIDTH 1 +#define R_VECT_MASK_CLR__dma1__clr 1 +#define R_VECT_MASK_CLR__dma1__nop 0 +#define R_VECT_MASK_CLR__dma0__BITNR 16 +#define R_VECT_MASK_CLR__dma0__WIDTH 1 +#define R_VECT_MASK_CLR__dma0__clr 1 +#define R_VECT_MASK_CLR__dma0__nop 0 +#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 +#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 +#define R_VECT_MASK_CLR__ext_dma1__clr 1 +#define R_VECT_MASK_CLR__ext_dma1__nop 0 +#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 +#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 +#define R_VECT_MASK_CLR__ext_dma0__clr 1 +#define R_VECT_MASK_CLR__ext_dma0__nop 0 +#define R_VECT_MASK_CLR__pa__BITNR 11 +#define R_VECT_MASK_CLR__pa__WIDTH 1 +#define R_VECT_MASK_CLR__pa__clr 1 +#define R_VECT_MASK_CLR__pa__nop 0 +#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 +#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 +#define R_VECT_MASK_CLR__irq_intnr__clr 1 +#define R_VECT_MASK_CLR__irq_intnr__nop 0 +#define R_VECT_MASK_CLR__sw__BITNR 9 +#define R_VECT_MASK_CLR__sw__WIDTH 1 +#define R_VECT_MASK_CLR__sw__clr 1 +#define R_VECT_MASK_CLR__sw__nop 0 +#define R_VECT_MASK_CLR__serial__BITNR 8 +#define R_VECT_MASK_CLR__serial__WIDTH 1 +#define R_VECT_MASK_CLR__serial__clr 1 +#define R_VECT_MASK_CLR__serial__nop 0 +#define R_VECT_MASK_CLR__snmp__BITNR 7 +#define R_VECT_MASK_CLR__snmp__WIDTH 1 +#define R_VECT_MASK_CLR__snmp__clr 1 +#define R_VECT_MASK_CLR__snmp__nop 0 +#define R_VECT_MASK_CLR__network__BITNR 6 +#define R_VECT_MASK_CLR__network__WIDTH 1 +#define R_VECT_MASK_CLR__network__clr 1 +#define R_VECT_MASK_CLR__network__nop 0 +#define R_VECT_MASK_CLR__scsi1__BITNR 5 +#define R_VECT_MASK_CLR__scsi1__WIDTH 1 +#define R_VECT_MASK_CLR__scsi1__clr 1 +#define R_VECT_MASK_CLR__scsi1__nop 0 +#define R_VECT_MASK_CLR__par1__BITNR 5 +#define R_VECT_MASK_CLR__par1__WIDTH 1 +#define R_VECT_MASK_CLR__par1__clr 1 +#define R_VECT_MASK_CLR__par1__nop 0 +#define R_VECT_MASK_CLR__scsi0__BITNR 4 +#define R_VECT_MASK_CLR__scsi0__WIDTH 1 +#define R_VECT_MASK_CLR__scsi0__clr 1 +#define R_VECT_MASK_CLR__scsi0__nop 0 +#define R_VECT_MASK_CLR__par0__BITNR 4 +#define R_VECT_MASK_CLR__par0__WIDTH 1 +#define R_VECT_MASK_CLR__par0__clr 1 +#define R_VECT_MASK_CLR__par0__nop 0 +#define R_VECT_MASK_CLR__ata__BITNR 4 +#define R_VECT_MASK_CLR__ata__WIDTH 1 +#define R_VECT_MASK_CLR__ata__clr 1 +#define R_VECT_MASK_CLR__ata__nop 0 +#define R_VECT_MASK_CLR__mio__BITNR 4 +#define R_VECT_MASK_CLR__mio__WIDTH 1 +#define R_VECT_MASK_CLR__mio__clr 1 +#define R_VECT_MASK_CLR__mio__nop 0 +#define R_VECT_MASK_CLR__timer1__BITNR 3 +#define R_VECT_MASK_CLR__timer1__WIDTH 1 +#define R_VECT_MASK_CLR__timer1__clr 1 +#define R_VECT_MASK_CLR__timer1__nop 0 +#define R_VECT_MASK_CLR__timer0__BITNR 2 +#define R_VECT_MASK_CLR__timer0__WIDTH 1 +#define R_VECT_MASK_CLR__timer0__clr 1 +#define R_VECT_MASK_CLR__timer0__nop 0 +#define R_VECT_MASK_CLR__nmi__BITNR 1 +#define R_VECT_MASK_CLR__nmi__WIDTH 1 +#define R_VECT_MASK_CLR__nmi__clr 1 +#define R_VECT_MASK_CLR__nmi__nop 0 +#define R_VECT_MASK_CLR__some__BITNR 0 +#define R_VECT_MASK_CLR__some__WIDTH 1 +#define R_VECT_MASK_CLR__some__clr 1 +#define R_VECT_MASK_CLR__some__nop 0 + +#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) +#define R_VECT_READ__usb__BITNR 31 +#define R_VECT_READ__usb__WIDTH 1 +#define R_VECT_READ__usb__active 1 +#define R_VECT_READ__usb__inactive 0 +#define R_VECT_READ__dma9__BITNR 25 +#define R_VECT_READ__dma9__WIDTH 1 +#define R_VECT_READ__dma9__active 1 +#define R_VECT_READ__dma9__inactive 0 +#define R_VECT_READ__dma8__BITNR 24 +#define R_VECT_READ__dma8__WIDTH 1 +#define R_VECT_READ__dma8__active 1 +#define R_VECT_READ__dma8__inactive 0 +#define R_VECT_READ__dma7__BITNR 23 +#define R_VECT_READ__dma7__WIDTH 1 +#define R_VECT_READ__dma7__active 1 +#define R_VECT_READ__dma7__inactive 0 +#define R_VECT_READ__dma6__BITNR 22 +#define R_VECT_READ__dma6__WIDTH 1 +#define R_VECT_READ__dma6__active 1 +#define R_VECT_READ__dma6__inactive 0 +#define R_VECT_READ__dma5__BITNR 21 +#define R_VECT_READ__dma5__WIDTH 1 +#define R_VECT_READ__dma5__active 1 +#define R_VECT_READ__dma5__inactive 0 +#define R_VECT_READ__dma4__BITNR 20 +#define R_VECT_READ__dma4__WIDTH 1 +#define R_VECT_READ__dma4__active 1 +#define R_VECT_READ__dma4__inactive 0 +#define R_VECT_READ__dma3__BITNR 19 +#define R_VECT_READ__dma3__WIDTH 1 +#define R_VECT_READ__dma3__active 1 +#define R_VECT_READ__dma3__inactive 0 +#define R_VECT_READ__dma2__BITNR 18 +#define R_VECT_READ__dma2__WIDTH 1 +#define R_VECT_READ__dma2__active 1 +#define R_VECT_READ__dma2__inactive 0 +#define R_VECT_READ__dma1__BITNR 17 +#define R_VECT_READ__dma1__WIDTH 1 +#define R_VECT_READ__dma1__active 1 +#define R_VECT_READ__dma1__inactive 0 +#define R_VECT_READ__dma0__BITNR 16 +#define R_VECT_READ__dma0__WIDTH 1 +#define R_VECT_READ__dma0__active 1 +#define R_VECT_READ__dma0__inactive 0 +#define R_VECT_READ__ext_dma1__BITNR 13 +#define R_VECT_READ__ext_dma1__WIDTH 1 +#define R_VECT_READ__ext_dma1__active 1 +#define R_VECT_READ__ext_dma1__inactive 0 +#define R_VECT_READ__ext_dma0__BITNR 12 +#define R_VECT_READ__ext_dma0__WIDTH 1 +#define R_VECT_READ__ext_dma0__active 1 +#define R_VECT_READ__ext_dma0__inactive 0 +#define R_VECT_READ__pa__BITNR 11 +#define R_VECT_READ__pa__WIDTH 1 +#define R_VECT_READ__pa__active 1 +#define R_VECT_READ__pa__inactive 0 +#define R_VECT_READ__irq_intnr__BITNR 10 +#define R_VECT_READ__irq_intnr__WIDTH 1 +#define R_VECT_READ__irq_intnr__active 1 +#define R_VECT_READ__irq_intnr__inactive 0 +#define R_VECT_READ__sw__BITNR 9 +#define R_VECT_READ__sw__WIDTH 1 +#define R_VECT_READ__sw__active 1 +#define R_VECT_READ__sw__inactive 0 +#define R_VECT_READ__serial__BITNR 8 +#define R_VECT_READ__serial__WIDTH 1 +#define R_VECT_READ__serial__active 1 +#define R_VECT_READ__serial__inactive 0 +#define R_VECT_READ__snmp__BITNR 7 +#define R_VECT_READ__snmp__WIDTH 1 +#define R_VECT_READ__snmp__active 1 +#define R_VECT_READ__snmp__inactive 0 +#define R_VECT_READ__network__BITNR 6 +#define R_VECT_READ__network__WIDTH 1 +#define R_VECT_READ__network__active 1 +#define R_VECT_READ__network__inactive 0 +#define R_VECT_READ__scsi1__BITNR 5 +#define R_VECT_READ__scsi1__WIDTH 1 +#define R_VECT_READ__scsi1__active 1 +#define R_VECT_READ__scsi1__inactive 0 +#define R_VECT_READ__par1__BITNR 5 +#define R_VECT_READ__par1__WIDTH 1 +#define R_VECT_READ__par1__active 1 +#define R_VECT_READ__par1__inactive 0 +#define R_VECT_READ__scsi0__BITNR 4 +#define R_VECT_READ__scsi0__WIDTH 1 +#define R_VECT_READ__scsi0__active 1 +#define R_VECT_READ__scsi0__inactive 0 +#define R_VECT_READ__par0__BITNR 4 +#define R_VECT_READ__par0__WIDTH 1 +#define R_VECT_READ__par0__active 1 +#define R_VECT_READ__par0__inactive 0 +#define R_VECT_READ__ata__BITNR 4 +#define R_VECT_READ__ata__WIDTH 1 +#define R_VECT_READ__ata__active 1 +#define R_VECT_READ__ata__inactive 0 +#define R_VECT_READ__mio__BITNR 4 +#define R_VECT_READ__mio__WIDTH 1 +#define R_VECT_READ__mio__active 1 +#define R_VECT_READ__mio__inactive 0 +#define R_VECT_READ__timer1__BITNR 3 +#define R_VECT_READ__timer1__WIDTH 1 +#define R_VECT_READ__timer1__active 1 +#define R_VECT_READ__timer1__inactive 0 +#define R_VECT_READ__timer0__BITNR 2 +#define R_VECT_READ__timer0__WIDTH 1 +#define R_VECT_READ__timer0__active 1 +#define R_VECT_READ__timer0__inactive 0 +#define R_VECT_READ__nmi__BITNR 1 +#define R_VECT_READ__nmi__WIDTH 1 +#define R_VECT_READ__nmi__active 1 +#define R_VECT_READ__nmi__inactive 0 +#define R_VECT_READ__some__BITNR 0 +#define R_VECT_READ__some__WIDTH 1 +#define R_VECT_READ__some__active 1 +#define R_VECT_READ__some__inactive 0 + +#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) +#define R_VECT_MASK_SET__usb__BITNR 31 +#define R_VECT_MASK_SET__usb__WIDTH 1 +#define R_VECT_MASK_SET__usb__set 1 +#define R_VECT_MASK_SET__usb__nop 0 +#define R_VECT_MASK_SET__dma9__BITNR 25 +#define R_VECT_MASK_SET__dma9__WIDTH 1 +#define R_VECT_MASK_SET__dma9__set 1 +#define R_VECT_MASK_SET__dma9__nop 0 +#define R_VECT_MASK_SET__dma8__BITNR 24 +#define R_VECT_MASK_SET__dma8__WIDTH 1 +#define R_VECT_MASK_SET__dma8__set 1 +#define R_VECT_MASK_SET__dma8__nop 0 +#define R_VECT_MASK_SET__dma7__BITNR 23 +#define R_VECT_MASK_SET__dma7__WIDTH 1 +#define R_VECT_MASK_SET__dma7__set 1 +#define R_VECT_MASK_SET__dma7__nop 0 +#define R_VECT_MASK_SET__dma6__BITNR 22 +#define R_VECT_MASK_SET__dma6__WIDTH 1 +#define R_VECT_MASK_SET__dma6__set 1 +#define R_VECT_MASK_SET__dma6__nop 0 +#define R_VECT_MASK_SET__dma5__BITNR 21 +#define R_VECT_MASK_SET__dma5__WIDTH 1 +#define R_VECT_MASK_SET__dma5__set 1 +#define R_VECT_MASK_SET__dma5__nop 0 +#define R_VECT_MASK_SET__dma4__BITNR 20 +#define R_VECT_MASK_SET__dma4__WIDTH 1 +#define R_VECT_MASK_SET__dma4__set 1 +#define R_VECT_MASK_SET__dma4__nop 0 +#define R_VECT_MASK_SET__dma3__BITNR 19 +#define R_VECT_MASK_SET__dma3__WIDTH 1 +#define R_VECT_MASK_SET__dma3__set 1 +#define R_VECT_MASK_SET__dma3__nop 0 +#define R_VECT_MASK_SET__dma2__BITNR 18 +#define R_VECT_MASK_SET__dma2__WIDTH 1 +#define R_VECT_MASK_SET__dma2__set 1 +#define R_VECT_MASK_SET__dma2__nop 0 +#define R_VECT_MASK_SET__dma1__BITNR 17 +#define R_VECT_MASK_SET__dma1__WIDTH 1 +#define R_VECT_MASK_SET__dma1__set 1 +#define R_VECT_MASK_SET__dma1__nop 0 +#define R_VECT_MASK_SET__dma0__BITNR 16 +#define R_VECT_MASK_SET__dma0__WIDTH 1 +#define R_VECT_MASK_SET__dma0__set 1 +#define R_VECT_MASK_SET__dma0__nop 0 +#define R_VECT_MASK_SET__ext_dma1__BITNR 13 +#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 +#define R_VECT_MASK_SET__ext_dma1__set 1 +#define R_VECT_MASK_SET__ext_dma1__nop 0 +#define R_VECT_MASK_SET__ext_dma0__BITNR 12 +#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 +#define R_VECT_MASK_SET__ext_dma0__set 1 +#define R_VECT_MASK_SET__ext_dma0__nop 0 +#define R_VECT_MASK_SET__pa__BITNR 11 +#define R_VECT_MASK_SET__pa__WIDTH 1 +#define R_VECT_MASK_SET__pa__set 1 +#define R_VECT_MASK_SET__pa__nop 0 +#define R_VECT_MASK_SET__irq_intnr__BITNR 10 +#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 +#define R_VECT_MASK_SET__irq_intnr__set 1 +#define R_VECT_MASK_SET__irq_intnr__nop 0 +#define R_VECT_MASK_SET__sw__BITNR 9 +#define R_VECT_MASK_SET__sw__WIDTH 1 +#define R_VECT_MASK_SET__sw__set 1 +#define R_VECT_MASK_SET__sw__nop 0 +#define R_VECT_MASK_SET__serial__BITNR 8 +#define R_VECT_MASK_SET__serial__WIDTH 1 +#define R_VECT_MASK_SET__serial__set 1 +#define R_VECT_MASK_SET__serial__nop 0 +#define R_VECT_MASK_SET__snmp__BITNR 7 +#define R_VECT_MASK_SET__snmp__WIDTH 1 +#define R_VECT_MASK_SET__snmp__set 1 +#define R_VECT_MASK_SET__snmp__nop 0 +#define R_VECT_MASK_SET__network__BITNR 6 +#define R_VECT_MASK_SET__network__WIDTH 1 +#define R_VECT_MASK_SET__network__set 1 +#define R_VECT_MASK_SET__network__nop 0 +#define R_VECT_MASK_SET__scsi1__BITNR 5 +#define R_VECT_MASK_SET__scsi1__WIDTH 1 +#define R_VECT_MASK_SET__scsi1__set 1 +#define R_VECT_MASK_SET__scsi1__nop 0 +#define R_VECT_MASK_SET__par1__BITNR 5 +#define R_VECT_MASK_SET__par1__WIDTH 1 +#define R_VECT_MASK_SET__par1__set 1 +#define R_VECT_MASK_SET__par1__nop 0 +#define R_VECT_MASK_SET__scsi0__BITNR 4 +#define R_VECT_MASK_SET__scsi0__WIDTH 1 +#define R_VECT_MASK_SET__scsi0__set 1 +#define R_VECT_MASK_SET__scsi0__nop 0 +#define R_VECT_MASK_SET__par0__BITNR 4 +#define R_VECT_MASK_SET__par0__WIDTH 1 +#define R_VECT_MASK_SET__par0__set 1 +#define R_VECT_MASK_SET__par0__nop 0 +#define R_VECT_MASK_SET__ata__BITNR 4 +#define R_VECT_MASK_SET__ata__WIDTH 1 +#define R_VECT_MASK_SET__ata__set 1 +#define R_VECT_MASK_SET__ata__nop 0 +#define R_VECT_MASK_SET__mio__BITNR 4 +#define R_VECT_MASK_SET__mio__WIDTH 1 +#define R_VECT_MASK_SET__mio__set 1 +#define R_VECT_MASK_SET__mio__nop 0 +#define R_VECT_MASK_SET__timer1__BITNR 3 +#define R_VECT_MASK_SET__timer1__WIDTH 1 +#define R_VECT_MASK_SET__timer1__set 1 +#define R_VECT_MASK_SET__timer1__nop 0 +#define R_VECT_MASK_SET__timer0__BITNR 2 +#define R_VECT_MASK_SET__timer0__WIDTH 1 +#define R_VECT_MASK_SET__timer0__set 1 +#define R_VECT_MASK_SET__timer0__nop 0 +#define R_VECT_MASK_SET__nmi__BITNR 1 +#define R_VECT_MASK_SET__nmi__WIDTH 1 +#define R_VECT_MASK_SET__nmi__set 1 +#define R_VECT_MASK_SET__nmi__nop 0 +#define R_VECT_MASK_SET__some__BITNR 0 +#define R_VECT_MASK_SET__some__WIDTH 1 +#define R_VECT_MASK_SET__some__set 1 +#define R_VECT_MASK_SET__some__nop 0 + +/* +!* DMA registers +!*/ + +#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) +#define R_SET_EOP__ch9_eop__BITNR 3 +#define R_SET_EOP__ch9_eop__WIDTH 1 +#define R_SET_EOP__ch9_eop__set 1 +#define R_SET_EOP__ch9_eop__nop 0 +#define R_SET_EOP__ch7_eop__BITNR 2 +#define R_SET_EOP__ch7_eop__WIDTH 1 +#define R_SET_EOP__ch7_eop__set 1 +#define R_SET_EOP__ch7_eop__nop 0 +#define R_SET_EOP__ch5_eop__BITNR 1 +#define R_SET_EOP__ch5_eop__WIDTH 1 +#define R_SET_EOP__ch5_eop__set 1 +#define R_SET_EOP__ch5_eop__nop 0 +#define R_SET_EOP__ch3_eop__BITNR 0 +#define R_SET_EOP__ch3_eop__WIDTH 1 +#define R_SET_EOP__ch3_eop__set 1 +#define R_SET_EOP__ch3_eop__nop 0 + +#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) +#define R_DMA_CH0_HWSW__hw__BITNR 16 +#define R_DMA_CH0_HWSW__hw__WIDTH 16 +#define R_DMA_CH0_HWSW__sw__BITNR 0 +#define R_DMA_CH0_HWSW__sw__WIDTH 16 + +#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) +#define R_DMA_CH0_DESCR__descr__BITNR 0 +#define R_DMA_CH0_DESCR__descr__WIDTH 32 + +#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) +#define R_DMA_CH0_NEXT__next__BITNR 0 +#define R_DMA_CH0_NEXT__next__WIDTH 32 + +#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) +#define R_DMA_CH0_BUF__buf__BITNR 0 +#define R_DMA_CH0_BUF__buf__WIDTH 32 + +#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) +#define R_DMA_CH0_FIRST__first__BITNR 0 +#define R_DMA_CH0_FIRST__first__WIDTH 32 + +#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) +#define R_DMA_CH0_CMD__cmd__BITNR 0 +#define R_DMA_CH0_CMD__cmd__WIDTH 3 +#define R_DMA_CH0_CMD__cmd__hold 0 +#define R_DMA_CH0_CMD__cmd__start 1 +#define R_DMA_CH0_CMD__cmd__restart 3 +#define R_DMA_CH0_CMD__cmd__continue 3 +#define R_DMA_CH0_CMD__cmd__reset 4 + +#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) +#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) +#define R_DMA_CH0_STATUS__avail__BITNR 0 +#define R_DMA_CH0_STATUS__avail__WIDTH 7 + +#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) +#define R_DMA_CH1_HWSW__hw__BITNR 16 +#define R_DMA_CH1_HWSW__hw__WIDTH 16 +#define R_DMA_CH1_HWSW__sw__BITNR 0 +#define R_DMA_CH1_HWSW__sw__WIDTH 16 + +#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) +#define R_DMA_CH1_DESCR__descr__BITNR 0 +#define R_DMA_CH1_DESCR__descr__WIDTH 32 + +#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) +#define R_DMA_CH1_NEXT__next__BITNR 0 +#define R_DMA_CH1_NEXT__next__WIDTH 32 + +#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) +#define R_DMA_CH1_BUF__buf__BITNR 0 +#define R_DMA_CH1_BUF__buf__WIDTH 32 + +#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) +#define R_DMA_CH1_FIRST__first__BITNR 0 +#define R_DMA_CH1_FIRST__first__WIDTH 32 + +#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) +#define R_DMA_CH1_CMD__cmd__BITNR 0 +#define R_DMA_CH1_CMD__cmd__WIDTH 3 +#define R_DMA_CH1_CMD__cmd__hold 0 +#define R_DMA_CH1_CMD__cmd__start 1 +#define R_DMA_CH1_CMD__cmd__restart 3 +#define R_DMA_CH1_CMD__cmd__continue 3 +#define R_DMA_CH1_CMD__cmd__reset 4 + +#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) +#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) +#define R_DMA_CH1_STATUS__avail__BITNR 0 +#define R_DMA_CH1_STATUS__avail__WIDTH 7 + +#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) +#define R_DMA_CH2_HWSW__hw__BITNR 16 +#define R_DMA_CH2_HWSW__hw__WIDTH 16 +#define R_DMA_CH2_HWSW__sw__BITNR 0 +#define R_DMA_CH2_HWSW__sw__WIDTH 16 + +#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) +#define R_DMA_CH2_DESCR__descr__BITNR 0 +#define R_DMA_CH2_DESCR__descr__WIDTH 32 + +#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) +#define R_DMA_CH2_NEXT__next__BITNR 0 +#define R_DMA_CH2_NEXT__next__WIDTH 32 + +#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) +#define R_DMA_CH2_BUF__buf__BITNR 0 +#define R_DMA_CH2_BUF__buf__WIDTH 32 + +#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) +#define R_DMA_CH2_FIRST__first__BITNR 0 +#define R_DMA_CH2_FIRST__first__WIDTH 32 + +#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) +#define R_DMA_CH2_CMD__cmd__BITNR 0 +#define R_DMA_CH2_CMD__cmd__WIDTH 3 +#define R_DMA_CH2_CMD__cmd__hold 0 +#define R_DMA_CH2_CMD__cmd__start 1 +#define R_DMA_CH2_CMD__cmd__restart 3 +#define R_DMA_CH2_CMD__cmd__continue 3 +#define R_DMA_CH2_CMD__cmd__reset 4 + +#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) +#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) +#define R_DMA_CH2_STATUS__avail__BITNR 0 +#define R_DMA_CH2_STATUS__avail__WIDTH 7 + +#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) +#define R_DMA_CH3_HWSW__hw__BITNR 16 +#define R_DMA_CH3_HWSW__hw__WIDTH 16 +#define R_DMA_CH3_HWSW__sw__BITNR 0 +#define R_DMA_CH3_HWSW__sw__WIDTH 16 + +#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) +#define R_DMA_CH3_DESCR__descr__BITNR 0 +#define R_DMA_CH3_DESCR__descr__WIDTH 32 + +#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) +#define R_DMA_CH3_NEXT__next__BITNR 0 +#define R_DMA_CH3_NEXT__next__WIDTH 32 + +#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) +#define R_DMA_CH3_BUF__buf__BITNR 0 +#define R_DMA_CH3_BUF__buf__WIDTH 32 + +#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) +#define R_DMA_CH3_FIRST__first__BITNR 0 +#define R_DMA_CH3_FIRST__first__WIDTH 32 + +#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) +#define R_DMA_CH3_CMD__cmd__BITNR 0 +#define R_DMA_CH3_CMD__cmd__WIDTH 3 +#define R_DMA_CH3_CMD__cmd__hold 0 +#define R_DMA_CH3_CMD__cmd__start 1 +#define R_DMA_CH3_CMD__cmd__restart 3 +#define R_DMA_CH3_CMD__cmd__continue 3 +#define R_DMA_CH3_CMD__cmd__reset 4 + +#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) +#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) +#define R_DMA_CH3_STATUS__avail__BITNR 0 +#define R_DMA_CH3_STATUS__avail__WIDTH 7 + +#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) +#define R_DMA_CH4_HWSW__hw__BITNR 16 +#define R_DMA_CH4_HWSW__hw__WIDTH 16 +#define R_DMA_CH4_HWSW__sw__BITNR 0 +#define R_DMA_CH4_HWSW__sw__WIDTH 16 + +#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) +#define R_DMA_CH4_DESCR__descr__BITNR 0 +#define R_DMA_CH4_DESCR__descr__WIDTH 32 + +#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) +#define R_DMA_CH4_NEXT__next__BITNR 0 +#define R_DMA_CH4_NEXT__next__WIDTH 32 + +#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) +#define R_DMA_CH4_BUF__buf__BITNR 0 +#define R_DMA_CH4_BUF__buf__WIDTH 32 + +#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) +#define R_DMA_CH4_FIRST__first__BITNR 0 +#define R_DMA_CH4_FIRST__first__WIDTH 32 + +#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) +#define R_DMA_CH4_CMD__cmd__BITNR 0 +#define R_DMA_CH4_CMD__cmd__WIDTH 3 +#define R_DMA_CH4_CMD__cmd__hold 0 +#define R_DMA_CH4_CMD__cmd__start 1 +#define R_DMA_CH4_CMD__cmd__restart 3 +#define R_DMA_CH4_CMD__cmd__continue 3 +#define R_DMA_CH4_CMD__cmd__reset 4 + +#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) +#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) +#define R_DMA_CH4_STATUS__avail__BITNR 0 +#define R_DMA_CH4_STATUS__avail__WIDTH 7 + +#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) +#define R_DMA_CH5_HWSW__hw__BITNR 16 +#define R_DMA_CH5_HWSW__hw__WIDTH 16 +#define R_DMA_CH5_HWSW__sw__BITNR 0 +#define R_DMA_CH5_HWSW__sw__WIDTH 16 + +#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) +#define R_DMA_CH5_DESCR__descr__BITNR 0 +#define R_DMA_CH5_DESCR__descr__WIDTH 32 + +#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) +#define R_DMA_CH5_NEXT__next__BITNR 0 +#define R_DMA_CH5_NEXT__next__WIDTH 32 + +#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) +#define R_DMA_CH5_BUF__buf__BITNR 0 +#define R_DMA_CH5_BUF__buf__WIDTH 32 + +#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) +#define R_DMA_CH5_FIRST__first__BITNR 0 +#define R_DMA_CH5_FIRST__first__WIDTH 32 + +#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) +#define R_DMA_CH5_CMD__cmd__BITNR 0 +#define R_DMA_CH5_CMD__cmd__WIDTH 3 +#define R_DMA_CH5_CMD__cmd__hold 0 +#define R_DMA_CH5_CMD__cmd__start 1 +#define R_DMA_CH5_CMD__cmd__restart 3 +#define R_DMA_CH5_CMD__cmd__continue 3 +#define R_DMA_CH5_CMD__cmd__reset 4 + +#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) +#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) +#define R_DMA_CH5_STATUS__avail__BITNR 0 +#define R_DMA_CH5_STATUS__avail__WIDTH 7 + +#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) +#define R_DMA_CH6_HWSW__hw__BITNR 16 +#define R_DMA_CH6_HWSW__hw__WIDTH 16 +#define R_DMA_CH6_HWSW__sw__BITNR 0 +#define R_DMA_CH6_HWSW__sw__WIDTH 16 + +#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) +#define R_DMA_CH6_DESCR__descr__BITNR 0 +#define R_DMA_CH6_DESCR__descr__WIDTH 32 + +#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) +#define R_DMA_CH6_NEXT__next__BITNR 0 +#define R_DMA_CH6_NEXT__next__WIDTH 32 + +#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) +#define R_DMA_CH6_BUF__buf__BITNR 0 +#define R_DMA_CH6_BUF__buf__WIDTH 32 + +#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) +#define R_DMA_CH6_FIRST__first__BITNR 0 +#define R_DMA_CH6_FIRST__first__WIDTH 32 + +#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) +#define R_DMA_CH6_CMD__cmd__BITNR 0 +#define R_DMA_CH6_CMD__cmd__WIDTH 3 +#define R_DMA_CH6_CMD__cmd__hold 0 +#define R_DMA_CH6_CMD__cmd__start 1 +#define R_DMA_CH6_CMD__cmd__restart 3 +#define R_DMA_CH6_CMD__cmd__continue 3 +#define R_DMA_CH6_CMD__cmd__reset 4 + +#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) +#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) +#define R_DMA_CH6_STATUS__avail__BITNR 0 +#define R_DMA_CH6_STATUS__avail__WIDTH 7 + +#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) +#define R_DMA_CH7_HWSW__hw__BITNR 16 +#define R_DMA_CH7_HWSW__hw__WIDTH 16 +#define R_DMA_CH7_HWSW__sw__BITNR 0 +#define R_DMA_CH7_HWSW__sw__WIDTH 16 + +#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) +#define R_DMA_CH7_DESCR__descr__BITNR 0 +#define R_DMA_CH7_DESCR__descr__WIDTH 32 + +#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) +#define R_DMA_CH7_NEXT__next__BITNR 0 +#define R_DMA_CH7_NEXT__next__WIDTH 32 + +#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) +#define R_DMA_CH7_BUF__buf__BITNR 0 +#define R_DMA_CH7_BUF__buf__WIDTH 32 + +#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) +#define R_DMA_CH7_FIRST__first__BITNR 0 +#define R_DMA_CH7_FIRST__first__WIDTH 32 + +#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) +#define R_DMA_CH7_CMD__cmd__BITNR 0 +#define R_DMA_CH7_CMD__cmd__WIDTH 3 +#define R_DMA_CH7_CMD__cmd__hold 0 +#define R_DMA_CH7_CMD__cmd__start 1 +#define R_DMA_CH7_CMD__cmd__restart 3 +#define R_DMA_CH7_CMD__cmd__continue 3 +#define R_DMA_CH7_CMD__cmd__reset 4 + +#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) +#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) +#define R_DMA_CH7_STATUS__avail__BITNR 0 +#define R_DMA_CH7_STATUS__avail__WIDTH 7 + +#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) +#define R_DMA_CH8_HWSW__hw__BITNR 16 +#define R_DMA_CH8_HWSW__hw__WIDTH 16 +#define R_DMA_CH8_HWSW__sw__BITNR 0 +#define R_DMA_CH8_HWSW__sw__WIDTH 16 + +#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) +#define R_DMA_CH8_DESCR__descr__BITNR 0 +#define R_DMA_CH8_DESCR__descr__WIDTH 32 + +#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) +#define R_DMA_CH8_NEXT__next__BITNR 0 +#define R_DMA_CH8_NEXT__next__WIDTH 32 + +#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) +#define R_DMA_CH8_BUF__buf__BITNR 0 +#define R_DMA_CH8_BUF__buf__WIDTH 32 + +#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) +#define R_DMA_CH8_FIRST__first__BITNR 0 +#define R_DMA_CH8_FIRST__first__WIDTH 32 + +#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) +#define R_DMA_CH8_CMD__cmd__BITNR 0 +#define R_DMA_CH8_CMD__cmd__WIDTH 3 +#define R_DMA_CH8_CMD__cmd__hold 0 +#define R_DMA_CH8_CMD__cmd__start 1 +#define R_DMA_CH8_CMD__cmd__restart 3 +#define R_DMA_CH8_CMD__cmd__continue 3 +#define R_DMA_CH8_CMD__cmd__reset 4 + +#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) +#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) +#define R_DMA_CH8_STATUS__avail__BITNR 0 +#define R_DMA_CH8_STATUS__avail__WIDTH 7 + +#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) +#define R_DMA_CH8_SUB__sub__BITNR 0 +#define R_DMA_CH8_SUB__sub__WIDTH 32 + +#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) +#define R_DMA_CH8_NEP__nep__BITNR 0 +#define R_DMA_CH8_NEP__nep__WIDTH 32 + +#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) +#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) +#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB0_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) +#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) +#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB1_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) +#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) +#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB2_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) +#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) +#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB3_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) +#define R_DMA_CH9_HWSW__hw__BITNR 16 +#define R_DMA_CH9_HWSW__hw__WIDTH 16 +#define R_DMA_CH9_HWSW__sw__BITNR 0 +#define R_DMA_CH9_HWSW__sw__WIDTH 16 + +#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) +#define R_DMA_CH9_DESCR__descr__BITNR 0 +#define R_DMA_CH9_DESCR__descr__WIDTH 32 + +#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) +#define R_DMA_CH9_NEXT__next__BITNR 0 +#define R_DMA_CH9_NEXT__next__WIDTH 32 + +#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) +#define R_DMA_CH9_BUF__buf__BITNR 0 +#define R_DMA_CH9_BUF__buf__WIDTH 32 + +#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) +#define R_DMA_CH9_FIRST__first__BITNR 0 +#define R_DMA_CH9_FIRST__first__WIDTH 32 + +#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) +#define R_DMA_CH9_CMD__cmd__BITNR 0 +#define R_DMA_CH9_CMD__cmd__WIDTH 3 +#define R_DMA_CH9_CMD__cmd__hold 0 +#define R_DMA_CH9_CMD__cmd__start 1 +#define R_DMA_CH9_CMD__cmd__restart 3 +#define R_DMA_CH9_CMD__cmd__continue 3 +#define R_DMA_CH9_CMD__cmd__reset 4 + +#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) +#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) +#define R_DMA_CH9_STATUS__avail__BITNR 0 +#define R_DMA_CH9_STATUS__avail__WIDTH 7 + +/* +!* Test mode registers +!*/ + +#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) +#define R_TEST_MODE__single_step__BITNR 19 +#define R_TEST_MODE__single_step__WIDTH 1 +#define R_TEST_MODE__single_step__on 1 +#define R_TEST_MODE__single_step__off 0 +#define R_TEST_MODE__step_wr__BITNR 18 +#define R_TEST_MODE__step_wr__WIDTH 1 +#define R_TEST_MODE__step_wr__on 1 +#define R_TEST_MODE__step_wr__off 0 +#define R_TEST_MODE__step_rd__BITNR 17 +#define R_TEST_MODE__step_rd__WIDTH 1 +#define R_TEST_MODE__step_rd__on 1 +#define R_TEST_MODE__step_rd__off 0 +#define R_TEST_MODE__step_fetch__BITNR 16 +#define R_TEST_MODE__step_fetch__WIDTH 1 +#define R_TEST_MODE__step_fetch__on 1 +#define R_TEST_MODE__step_fetch__off 0 +#define R_TEST_MODE__mmu_test__BITNR 12 +#define R_TEST_MODE__mmu_test__WIDTH 1 +#define R_TEST_MODE__mmu_test__on 1 +#define R_TEST_MODE__mmu_test__off 0 +#define R_TEST_MODE__usb_test__BITNR 11 +#define R_TEST_MODE__usb_test__WIDTH 1 +#define R_TEST_MODE__usb_test__on 1 +#define R_TEST_MODE__usb_test__off 0 +#define R_TEST_MODE__scsi_timer_test__BITNR 10 +#define R_TEST_MODE__scsi_timer_test__WIDTH 1 +#define R_TEST_MODE__scsi_timer_test__on 1 +#define R_TEST_MODE__scsi_timer_test__off 0 +#define R_TEST_MODE__backoff__BITNR 9 +#define R_TEST_MODE__backoff__WIDTH 1 +#define R_TEST_MODE__backoff__on 1 +#define R_TEST_MODE__backoff__off 0 +#define R_TEST_MODE__snmp_test__BITNR 8 +#define R_TEST_MODE__snmp_test__WIDTH 1 +#define R_TEST_MODE__snmp_test__on 1 +#define R_TEST_MODE__snmp_test__off 0 +#define R_TEST_MODE__snmp_inc__BITNR 7 +#define R_TEST_MODE__snmp_inc__WIDTH 1 +#define R_TEST_MODE__snmp_inc__do 1 +#define R_TEST_MODE__snmp_inc__dont 0 +#define R_TEST_MODE__ser_loop__BITNR 6 +#define R_TEST_MODE__ser_loop__WIDTH 1 +#define R_TEST_MODE__ser_loop__on 1 +#define R_TEST_MODE__ser_loop__off 0 +#define R_TEST_MODE__baudrate__BITNR 5 +#define R_TEST_MODE__baudrate__WIDTH 1 +#define R_TEST_MODE__baudrate__on 1 +#define R_TEST_MODE__baudrate__off 0 +#define R_TEST_MODE__timer__BITNR 3 +#define R_TEST_MODE__timer__WIDTH 2 +#define R_TEST_MODE__timer__off 0 +#define R_TEST_MODE__timer__even 1 +#define R_TEST_MODE__timer__odd 2 +#define R_TEST_MODE__timer__all 3 +#define R_TEST_MODE__cache_test__BITNR 2 +#define R_TEST_MODE__cache_test__WIDTH 1 +#define R_TEST_MODE__cache_test__normal 0 +#define R_TEST_MODE__cache_test__test 1 +#define R_TEST_MODE__tag_test__BITNR 1 +#define R_TEST_MODE__tag_test__WIDTH 1 +#define R_TEST_MODE__tag_test__normal 0 +#define R_TEST_MODE__tag_test__test 1 +#define R_TEST_MODE__cache_enable__BITNR 0 +#define R_TEST_MODE__cache_enable__WIDTH 1 +#define R_TEST_MODE__cache_enable__enable 1 +#define R_TEST_MODE__cache_enable__disable 0 + +#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) +#define R_SINGLE_STEP__single_step__BITNR 3 +#define R_SINGLE_STEP__single_step__WIDTH 1 +#define R_SINGLE_STEP__single_step__on 1 +#define R_SINGLE_STEP__single_step__off 0 +#define R_SINGLE_STEP__step_wr__BITNR 2 +#define R_SINGLE_STEP__step_wr__WIDTH 1 +#define R_SINGLE_STEP__step_wr__on 1 +#define R_SINGLE_STEP__step_wr__off 0 +#define R_SINGLE_STEP__step_rd__BITNR 1 +#define R_SINGLE_STEP__step_rd__WIDTH 1 +#define R_SINGLE_STEP__step_rd__on 1 +#define R_SINGLE_STEP__step_rd__off 0 +#define R_SINGLE_STEP__step_fetch__BITNR 0 +#define R_SINGLE_STEP__step_fetch__WIDTH 1 +#define R_SINGLE_STEP__step_fetch__on 1 +#define R_SINGLE_STEP__step_fetch__off 0 + +/* +!* USB interface control registers +!*/ + +#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) +#define R_USB_REVISION__major__BITNR 4 +#define R_USB_REVISION__major__WIDTH 4 +#define R_USB_REVISION__minor__BITNR 0 +#define R_USB_REVISION__minor__WIDTH 4 + +#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) +#define R_USB_COMMAND__port_sel__BITNR 6 +#define R_USB_COMMAND__port_sel__WIDTH 2 +#define R_USB_COMMAND__port_sel__nop 0 +#define R_USB_COMMAND__port_sel__port1 1 +#define R_USB_COMMAND__port_sel__port2 2 +#define R_USB_COMMAND__port_sel__both 3 +#define R_USB_COMMAND__port_cmd__BITNR 4 +#define R_USB_COMMAND__port_cmd__WIDTH 2 +#define R_USB_COMMAND__port_cmd__reset 0 +#define R_USB_COMMAND__port_cmd__disable 1 +#define R_USB_COMMAND__port_cmd__suspend 2 +#define R_USB_COMMAND__port_cmd__resume 3 +#define R_USB_COMMAND__busy__BITNR 3 +#define R_USB_COMMAND__busy__WIDTH 1 +#define R_USB_COMMAND__busy__no 0 +#define R_USB_COMMAND__busy__yes 1 +#define R_USB_COMMAND__ctrl_cmd__BITNR 0 +#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 +#define R_USB_COMMAND__ctrl_cmd__nop 0 +#define R_USB_COMMAND__ctrl_cmd__reset 1 +#define R_USB_COMMAND__ctrl_cmd__deconfig 2 +#define R_USB_COMMAND__ctrl_cmd__host_config 3 +#define R_USB_COMMAND__ctrl_cmd__dev_config 4 +#define R_USB_COMMAND__ctrl_cmd__host_nop 5 +#define R_USB_COMMAND__ctrl_cmd__host_run 6 +#define R_USB_COMMAND__ctrl_cmd__host_stop 7 + +#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) +#define R_USB_COMMAND_DEV__port_sel__BITNR 6 +#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 +#define R_USB_COMMAND_DEV__port_sel__nop 0 +#define R_USB_COMMAND_DEV__port_sel__dummy1 1 +#define R_USB_COMMAND_DEV__port_sel__dummy2 2 +#define R_USB_COMMAND_DEV__port_sel__any 3 +#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 +#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 +#define R_USB_COMMAND_DEV__port_cmd__active 0 +#define R_USB_COMMAND_DEV__port_cmd__passive 1 +#define R_USB_COMMAND_DEV__port_cmd__nop 2 +#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 +#define R_USB_COMMAND_DEV__busy__BITNR 3 +#define R_USB_COMMAND_DEV__busy__WIDTH 1 +#define R_USB_COMMAND_DEV__busy__no 0 +#define R_USB_COMMAND_DEV__busy__yes 1 +#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 +#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 +#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 +#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 +#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 +#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 + +#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) +#define R_USB_STATUS__ourun__BITNR 5 +#define R_USB_STATUS__ourun__WIDTH 1 +#define R_USB_STATUS__ourun__no 0 +#define R_USB_STATUS__ourun__yes 1 +#define R_USB_STATUS__perror__BITNR 4 +#define R_USB_STATUS__perror__WIDTH 1 +#define R_USB_STATUS__perror__no 0 +#define R_USB_STATUS__perror__yes 1 +#define R_USB_STATUS__device_mode__BITNR 3 +#define R_USB_STATUS__device_mode__WIDTH 1 +#define R_USB_STATUS__device_mode__no 0 +#define R_USB_STATUS__device_mode__yes 1 +#define R_USB_STATUS__host_mode__BITNR 2 +#define R_USB_STATUS__host_mode__WIDTH 1 +#define R_USB_STATUS__host_mode__no 0 +#define R_USB_STATUS__host_mode__yes 1 +#define R_USB_STATUS__started__BITNR 1 +#define R_USB_STATUS__started__WIDTH 1 +#define R_USB_STATUS__started__no 0 +#define R_USB_STATUS__started__yes 1 +#define R_USB_STATUS__running__BITNR 0 +#define R_USB_STATUS__running__WIDTH 1 +#define R_USB_STATUS__running__no 0 +#define R_USB_STATUS__running__yes 1 + +#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 +#define R_USB_IRQ_MASK_SET__iso_eof__set 1 +#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 +#define R_USB_IRQ_MASK_SET__intr_eof__set 1 +#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 +#define R_USB_IRQ_MASK_SET__iso_eot__set 1 +#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 +#define R_USB_IRQ_MASK_SET__intr_eot__set 1 +#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 +#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 +#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 +#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 +#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 +#define R_USB_IRQ_MASK_SET__epid_attn__set 1 +#define R_USB_IRQ_MASK_SET__sof__BITNR 2 +#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__sof__nop 0 +#define R_USB_IRQ_MASK_SET__sof__set 1 +#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 +#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET__port_status__nop 0 +#define R_USB_IRQ_MASK_SET__port_status__set 1 +#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 +#define R_USB_IRQ_MASK_SET__ctl_status__set 1 + +#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 +#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 +#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 +#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 +#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 +#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 +#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 +#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 +#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 +#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 +#define R_USB_IRQ_MASK_READ__sof__BITNR 2 +#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__sof__no_pend 0 +#define R_USB_IRQ_MASK_READ__sof__pend 1 +#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 +#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 +#define R_USB_IRQ_MASK_READ__port_status__pend 1 +#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 +#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) +#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 +#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 +#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 +#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 +#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 +#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 +#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 +#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__sof__nop 0 +#define R_USB_IRQ_MASK_CLR__sof__clr 1 +#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 +#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__port_status__nop 0 +#define R_USB_IRQ_MASK_CLR__port_status__clr 1 +#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 +#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 + +#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) +#define R_USB_IRQ_READ__iso_eof__BITNR 13 +#define R_USB_IRQ_READ__iso_eof__WIDTH 1 +#define R_USB_IRQ_READ__iso_eof__no_pend 0 +#define R_USB_IRQ_READ__iso_eof__pend 1 +#define R_USB_IRQ_READ__intr_eof__BITNR 12 +#define R_USB_IRQ_READ__intr_eof__WIDTH 1 +#define R_USB_IRQ_READ__intr_eof__no_pend 0 +#define R_USB_IRQ_READ__intr_eof__pend 1 +#define R_USB_IRQ_READ__iso_eot__BITNR 11 +#define R_USB_IRQ_READ__iso_eot__WIDTH 1 +#define R_USB_IRQ_READ__iso_eot__no_pend 0 +#define R_USB_IRQ_READ__iso_eot__pend 1 +#define R_USB_IRQ_READ__intr_eot__BITNR 10 +#define R_USB_IRQ_READ__intr_eot__WIDTH 1 +#define R_USB_IRQ_READ__intr_eot__no_pend 0 +#define R_USB_IRQ_READ__intr_eot__pend 1 +#define R_USB_IRQ_READ__ctl_eot__BITNR 9 +#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 +#define R_USB_IRQ_READ__ctl_eot__no_pend 0 +#define R_USB_IRQ_READ__ctl_eot__pend 1 +#define R_USB_IRQ_READ__bulk_eot__BITNR 8 +#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 +#define R_USB_IRQ_READ__bulk_eot__no_pend 0 +#define R_USB_IRQ_READ__bulk_eot__pend 1 +#define R_USB_IRQ_READ__epid_attn__BITNR 3 +#define R_USB_IRQ_READ__epid_attn__WIDTH 1 +#define R_USB_IRQ_READ__epid_attn__no_pend 0 +#define R_USB_IRQ_READ__epid_attn__pend 1 +#define R_USB_IRQ_READ__sof__BITNR 2 +#define R_USB_IRQ_READ__sof__WIDTH 1 +#define R_USB_IRQ_READ__sof__no_pend 0 +#define R_USB_IRQ_READ__sof__pend 1 +#define R_USB_IRQ_READ__port_status__BITNR 1 +#define R_USB_IRQ_READ__port_status__WIDTH 1 +#define R_USB_IRQ_READ__port_status__no_pend 0 +#define R_USB_IRQ_READ__port_status__pend 1 +#define R_USB_IRQ_READ__ctl_status__BITNR 0 +#define R_USB_IRQ_READ__ctl_status__WIDTH 1 +#define R_USB_IRQ_READ__ctl_status__no_pend 0 +#define R_USB_IRQ_READ__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 +#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 + +#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 + +#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) +#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__out_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 +#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 +#define R_USB_IRQ_READ_DEV__sof__BITNR 2 +#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 +#define R_USB_IRQ_READ_DEV__sof__no_pend 0 +#define R_USB_IRQ_READ_DEV__sof__pend 1 +#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 +#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 +#define R_USB_IRQ_READ_DEV__port_status__pend 1 +#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 +#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 + +#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) +#define R_USB_FM_NUMBER__value__BITNR 0 +#define R_USB_FM_NUMBER__value__WIDTH 32 + +#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) +#define R_USB_FM_INTERVAL__fixed__BITNR 6 +#define R_USB_FM_INTERVAL__fixed__WIDTH 8 +#define R_USB_FM_INTERVAL__adj__BITNR 0 +#define R_USB_FM_INTERVAL__adj__WIDTH 6 + +#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) +#define R_USB_FM_REMAINING__value__BITNR 0 +#define R_USB_FM_REMAINING__value__WIDTH 14 + +#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) +#define R_USB_FM_PSTART__value__BITNR 0 +#define R_USB_FM_PSTART__value__WIDTH 14 + +#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) +#define R_USB_RH_STATUS__babble2__BITNR 7 +#define R_USB_RH_STATUS__babble2__WIDTH 1 +#define R_USB_RH_STATUS__babble2__no 0 +#define R_USB_RH_STATUS__babble2__yes 1 +#define R_USB_RH_STATUS__babble1__BITNR 6 +#define R_USB_RH_STATUS__babble1__WIDTH 1 +#define R_USB_RH_STATUS__babble1__no 0 +#define R_USB_RH_STATUS__babble1__yes 1 +#define R_USB_RH_STATUS__bus1__BITNR 4 +#define R_USB_RH_STATUS__bus1__WIDTH 2 +#define R_USB_RH_STATUS__bus1__SE0 0 +#define R_USB_RH_STATUS__bus1__Diff0 1 +#define R_USB_RH_STATUS__bus1__Diff1 2 +#define R_USB_RH_STATUS__bus1__SE1 3 +#define R_USB_RH_STATUS__bus2__BITNR 2 +#define R_USB_RH_STATUS__bus2__WIDTH 2 +#define R_USB_RH_STATUS__bus2__SE0 0 +#define R_USB_RH_STATUS__bus2__Diff0 1 +#define R_USB_RH_STATUS__bus2__Diff1 2 +#define R_USB_RH_STATUS__bus2__SE1 3 +#define R_USB_RH_STATUS__nports__BITNR 0 +#define R_USB_RH_STATUS__nports__WIDTH 2 + +#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) +#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 +#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__speed__full 0 +#define R_USB_RH_PORT_STATUS_1__speed__low 1 +#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 +#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 +#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__reset__no 0 +#define R_USB_RH_PORT_STATUS_1__reset__yes 1 +#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 +#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 +#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 +#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 +#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__suspended__no 0 +#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 +#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 +#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__enabled__no 0 +#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 +#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 +#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__connected__no 0 +#define R_USB_RH_PORT_STATUS_1__connected__yes 1 + +#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) +#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 +#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__speed__full 0 +#define R_USB_RH_PORT_STATUS_2__speed__low 1 +#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 +#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 +#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__reset__no 0 +#define R_USB_RH_PORT_STATUS_2__reset__yes 1 +#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 +#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 +#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 +#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 +#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__suspended__no 0 +#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 +#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 +#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__enabled__no 0 +#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 +#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 +#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__connected__no 0 +#define R_USB_RH_PORT_STATUS_2__connected__yes 1 + +#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) +#define R_USB_EPT_INDEX__value__BITNR 0 +#define R_USB_EPT_INDEX__value__WIDTH 5 + +#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA__valid__BITNR 31 +#define R_USB_EPT_DATA__valid__WIDTH 1 +#define R_USB_EPT_DATA__valid__no 0 +#define R_USB_EPT_DATA__valid__yes 1 +#define R_USB_EPT_DATA__hold__BITNR 30 +#define R_USB_EPT_DATA__hold__WIDTH 1 +#define R_USB_EPT_DATA__hold__no 0 +#define R_USB_EPT_DATA__hold__yes 1 +#define R_USB_EPT_DATA__error_count_in__BITNR 28 +#define R_USB_EPT_DATA__error_count_in__WIDTH 2 +#define R_USB_EPT_DATA__t_in__BITNR 27 +#define R_USB_EPT_DATA__t_in__WIDTH 1 +#define R_USB_EPT_DATA__low_speed__BITNR 26 +#define R_USB_EPT_DATA__low_speed__WIDTH 1 +#define R_USB_EPT_DATA__low_speed__no 0 +#define R_USB_EPT_DATA__low_speed__yes 1 +#define R_USB_EPT_DATA__port__BITNR 24 +#define R_USB_EPT_DATA__port__WIDTH 2 +#define R_USB_EPT_DATA__port__any 0 +#define R_USB_EPT_DATA__port__p1 1 +#define R_USB_EPT_DATA__port__p2 2 +#define R_USB_EPT_DATA__port__undef 3 +#define R_USB_EPT_DATA__error_code__BITNR 22 +#define R_USB_EPT_DATA__error_code__WIDTH 2 +#define R_USB_EPT_DATA__error_code__no_error 0 +#define R_USB_EPT_DATA__error_code__stall 1 +#define R_USB_EPT_DATA__error_code__bus_error 2 +#define R_USB_EPT_DATA__error_code__buffer_error 3 +#define R_USB_EPT_DATA__t_out__BITNR 21 +#define R_USB_EPT_DATA__t_out__WIDTH 1 +#define R_USB_EPT_DATA__error_count_out__BITNR 19 +#define R_USB_EPT_DATA__error_count_out__WIDTH 2 +#define R_USB_EPT_DATA__max_len__BITNR 11 +#define R_USB_EPT_DATA__max_len__WIDTH 7 +#define R_USB_EPT_DATA__ep__BITNR 7 +#define R_USB_EPT_DATA__ep__WIDTH 4 +#define R_USB_EPT_DATA__dev__BITNR 0 +#define R_USB_EPT_DATA__dev__WIDTH 7 + +#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA_ISO__valid__BITNR 31 +#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 +#define R_USB_EPT_DATA_ISO__valid__no 0 +#define R_USB_EPT_DATA_ISO__valid__yes 1 +#define R_USB_EPT_DATA_ISO__port__BITNR 24 +#define R_USB_EPT_DATA_ISO__port__WIDTH 2 +#define R_USB_EPT_DATA_ISO__port__any 0 +#define R_USB_EPT_DATA_ISO__port__p1 1 +#define R_USB_EPT_DATA_ISO__port__p2 2 +#define R_USB_EPT_DATA_ISO__port__undef 3 +#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 +#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 +#define R_USB_EPT_DATA_ISO__error_code__no_error 0 +#define R_USB_EPT_DATA_ISO__error_code__stall 1 +#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 +#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 +#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 +#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 +#define R_USB_EPT_DATA_ISO__ep__BITNR 7 +#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 +#define R_USB_EPT_DATA_ISO__dev__BITNR 0 +#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 + +#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA_DEV__valid__BITNR 31 +#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 +#define R_USB_EPT_DATA_DEV__valid__no 0 +#define R_USB_EPT_DATA_DEV__valid__yes 1 +#define R_USB_EPT_DATA_DEV__hold__BITNR 30 +#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 +#define R_USB_EPT_DATA_DEV__hold__no 0 +#define R_USB_EPT_DATA_DEV__hold__yes 1 +#define R_USB_EPT_DATA_DEV__stall__BITNR 29 +#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 +#define R_USB_EPT_DATA_DEV__stall__no 0 +#define R_USB_EPT_DATA_DEV__stall__yes 1 +#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 +#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 +#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 +#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 +#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 +#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 +#define R_USB_EPT_DATA_DEV__ctrl__no 0 +#define R_USB_EPT_DATA_DEV__ctrl__yes 1 +#define R_USB_EPT_DATA_DEV__iso__BITNR 26 +#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 +#define R_USB_EPT_DATA_DEV__iso__no 0 +#define R_USB_EPT_DATA_DEV__iso__yes 1 +#define R_USB_EPT_DATA_DEV__port__BITNR 24 +#define R_USB_EPT_DATA_DEV__port__WIDTH 2 +#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 +#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 +#define R_USB_EPT_DATA_DEV__t__BITNR 21 +#define R_USB_EPT_DATA_DEV__t__WIDTH 1 +#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 +#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 +#define R_USB_EPT_DATA_DEV__ep__BITNR 7 +#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 +#define R_USB_EPT_DATA_DEV__dev__BITNR 0 +#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 + +#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) +#define R_USB_SNMP_TERROR__value__BITNR 0 +#define R_USB_SNMP_TERROR__value__WIDTH 32 + +#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) +#define R_USB_EPID_ATTN__value__BITNR 0 +#define R_USB_EPID_ATTN__value__WIDTH 32 + +#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) +#define R_USB_PORT1_DISABLE__disable__BITNR 0 +#define R_USB_PORT1_DISABLE__disable__WIDTH 1 +#define R_USB_PORT1_DISABLE__disable__yes 0 +#define R_USB_PORT1_DISABLE__disable__no 1 + +#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) +#define R_USB_PORT2_DISABLE__disable__BITNR 0 +#define R_USB_PORT2_DISABLE__disable__WIDTH 1 +#define R_USB_PORT2_DISABLE__disable__yes 0 +#define R_USB_PORT2_DISABLE__disable__no 1 + +/* +!* MMU registers +!*/ + +#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) +#define R_MMU_CONFIG__mmu_enable__BITNR 31 +#define R_MMU_CONFIG__mmu_enable__WIDTH 1 +#define R_MMU_CONFIG__mmu_enable__enable 1 +#define R_MMU_CONFIG__mmu_enable__disable 0 +#define R_MMU_CONFIG__inv_excp__BITNR 18 +#define R_MMU_CONFIG__inv_excp__WIDTH 1 +#define R_MMU_CONFIG__inv_excp__enable 1 +#define R_MMU_CONFIG__inv_excp__disable 0 +#define R_MMU_CONFIG__acc_excp__BITNR 17 +#define R_MMU_CONFIG__acc_excp__WIDTH 1 +#define R_MMU_CONFIG__acc_excp__enable 1 +#define R_MMU_CONFIG__acc_excp__disable 0 +#define R_MMU_CONFIG__we_excp__BITNR 16 +#define R_MMU_CONFIG__we_excp__WIDTH 1 +#define R_MMU_CONFIG__we_excp__enable 1 +#define R_MMU_CONFIG__we_excp__disable 0 +#define R_MMU_CONFIG__seg_f__BITNR 15 +#define R_MMU_CONFIG__seg_f__WIDTH 1 +#define R_MMU_CONFIG__seg_f__seg 1 +#define R_MMU_CONFIG__seg_f__page 0 +#define R_MMU_CONFIG__seg_e__BITNR 14 +#define R_MMU_CONFIG__seg_e__WIDTH 1 +#define R_MMU_CONFIG__seg_e__seg 1 +#define R_MMU_CONFIG__seg_e__page 0 +#define R_MMU_CONFIG__seg_d__BITNR 13 +#define R_MMU_CONFIG__seg_d__WIDTH 1 +#define R_MMU_CONFIG__seg_d__seg 1 +#define R_MMU_CONFIG__seg_d__page 0 +#define R_MMU_CONFIG__seg_c__BITNR 12 +#define R_MMU_CONFIG__seg_c__WIDTH 1 +#define R_MMU_CONFIG__seg_c__seg 1 +#define R_MMU_CONFIG__seg_c__page 0 +#define R_MMU_CONFIG__seg_b__BITNR 11 +#define R_MMU_CONFIG__seg_b__WIDTH 1 +#define R_MMU_CONFIG__seg_b__seg 1 +#define R_MMU_CONFIG__seg_b__page 0 +#define R_MMU_CONFIG__seg_a__BITNR 10 +#define R_MMU_CONFIG__seg_a__WIDTH 1 +#define R_MMU_CONFIG__seg_a__seg 1 +#define R_MMU_CONFIG__seg_a__page 0 +#define R_MMU_CONFIG__seg_9__BITNR 9 +#define R_MMU_CONFIG__seg_9__WIDTH 1 +#define R_MMU_CONFIG__seg_9__seg 1 +#define R_MMU_CONFIG__seg_9__page 0 +#define R_MMU_CONFIG__seg_8__BITNR 8 +#define R_MMU_CONFIG__seg_8__WIDTH 1 +#define R_MMU_CONFIG__seg_8__seg 1 +#define R_MMU_CONFIG__seg_8__page 0 +#define R_MMU_CONFIG__seg_7__BITNR 7 +#define R_MMU_CONFIG__seg_7__WIDTH 1 +#define R_MMU_CONFIG__seg_7__seg 1 +#define R_MMU_CONFIG__seg_7__page 0 +#define R_MMU_CONFIG__seg_6__BITNR 6 +#define R_MMU_CONFIG__seg_6__WIDTH 1 +#define R_MMU_CONFIG__seg_6__seg 1 +#define R_MMU_CONFIG__seg_6__page 0 +#define R_MMU_CONFIG__seg_5__BITNR 5 +#define R_MMU_CONFIG__seg_5__WIDTH 1 +#define R_MMU_CONFIG__seg_5__seg 1 +#define R_MMU_CONFIG__seg_5__page 0 +#define R_MMU_CONFIG__seg_4__BITNR 4 +#define R_MMU_CONFIG__seg_4__WIDTH 1 +#define R_MMU_CONFIG__seg_4__seg 1 +#define R_MMU_CONFIG__seg_4__page 0 +#define R_MMU_CONFIG__seg_3__BITNR 3 +#define R_MMU_CONFIG__seg_3__WIDTH 1 +#define R_MMU_CONFIG__seg_3__seg 1 +#define R_MMU_CONFIG__seg_3__page 0 +#define R_MMU_CONFIG__seg_2__BITNR 2 +#define R_MMU_CONFIG__seg_2__WIDTH 1 +#define R_MMU_CONFIG__seg_2__seg 1 +#define R_MMU_CONFIG__seg_2__page 0 +#define R_MMU_CONFIG__seg_1__BITNR 1 +#define R_MMU_CONFIG__seg_1__WIDTH 1 +#define R_MMU_CONFIG__seg_1__seg 1 +#define R_MMU_CONFIG__seg_1__page 0 +#define R_MMU_CONFIG__seg_0__BITNR 0 +#define R_MMU_CONFIG__seg_0__WIDTH 1 +#define R_MMU_CONFIG__seg_0__seg 1 +#define R_MMU_CONFIG__seg_0__page 0 + +#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) +#define R_MMU_KSEG__seg_f__BITNR 15 +#define R_MMU_KSEG__seg_f__WIDTH 1 +#define R_MMU_KSEG__seg_f__seg 1 +#define R_MMU_KSEG__seg_f__page 0 +#define R_MMU_KSEG__seg_e__BITNR 14 +#define R_MMU_KSEG__seg_e__WIDTH 1 +#define R_MMU_KSEG__seg_e__seg 1 +#define R_MMU_KSEG__seg_e__page 0 +#define R_MMU_KSEG__seg_d__BITNR 13 +#define R_MMU_KSEG__seg_d__WIDTH 1 +#define R_MMU_KSEG__seg_d__seg 1 +#define R_MMU_KSEG__seg_d__page 0 +#define R_MMU_KSEG__seg_c__BITNR 12 +#define R_MMU_KSEG__seg_c__WIDTH 1 +#define R_MMU_KSEG__seg_c__seg 1 +#define R_MMU_KSEG__seg_c__page 0 +#define R_MMU_KSEG__seg_b__BITNR 11 +#define R_MMU_KSEG__seg_b__WIDTH 1 +#define R_MMU_KSEG__seg_b__seg 1 +#define R_MMU_KSEG__seg_b__page 0 +#define R_MMU_KSEG__seg_a__BITNR 10 +#define R_MMU_KSEG__seg_a__WIDTH 1 +#define R_MMU_KSEG__seg_a__seg 1 +#define R_MMU_KSEG__seg_a__page 0 +#define R_MMU_KSEG__seg_9__BITNR 9 +#define R_MMU_KSEG__seg_9__WIDTH 1 +#define R_MMU_KSEG__seg_9__seg 1 +#define R_MMU_KSEG__seg_9__page 0 +#define R_MMU_KSEG__seg_8__BITNR 8 +#define R_MMU_KSEG__seg_8__WIDTH 1 +#define R_MMU_KSEG__seg_8__seg 1 +#define R_MMU_KSEG__seg_8__page 0 +#define R_MMU_KSEG__seg_7__BITNR 7 +#define R_MMU_KSEG__seg_7__WIDTH 1 +#define R_MMU_KSEG__seg_7__seg 1 +#define R_MMU_KSEG__seg_7__page 0 +#define R_MMU_KSEG__seg_6__BITNR 6 +#define R_MMU_KSEG__seg_6__WIDTH 1 +#define R_MMU_KSEG__seg_6__seg 1 +#define R_MMU_KSEG__seg_6__page 0 +#define R_MMU_KSEG__seg_5__BITNR 5 +#define R_MMU_KSEG__seg_5__WIDTH 1 +#define R_MMU_KSEG__seg_5__seg 1 +#define R_MMU_KSEG__seg_5__page 0 +#define R_MMU_KSEG__seg_4__BITNR 4 +#define R_MMU_KSEG__seg_4__WIDTH 1 +#define R_MMU_KSEG__seg_4__seg 1 +#define R_MMU_KSEG__seg_4__page 0 +#define R_MMU_KSEG__seg_3__BITNR 3 +#define R_MMU_KSEG__seg_3__WIDTH 1 +#define R_MMU_KSEG__seg_3__seg 1 +#define R_MMU_KSEG__seg_3__page 0 +#define R_MMU_KSEG__seg_2__BITNR 2 +#define R_MMU_KSEG__seg_2__WIDTH 1 +#define R_MMU_KSEG__seg_2__seg 1 +#define R_MMU_KSEG__seg_2__page 0 +#define R_MMU_KSEG__seg_1__BITNR 1 +#define R_MMU_KSEG__seg_1__WIDTH 1 +#define R_MMU_KSEG__seg_1__seg 1 +#define R_MMU_KSEG__seg_1__page 0 +#define R_MMU_KSEG__seg_0__BITNR 0 +#define R_MMU_KSEG__seg_0__WIDTH 1 +#define R_MMU_KSEG__seg_0__seg 1 +#define R_MMU_KSEG__seg_0__page 0 + +#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) +#define R_MMU_CTRL__inv_excp__BITNR 2 +#define R_MMU_CTRL__inv_excp__WIDTH 1 +#define R_MMU_CTRL__inv_excp__enable 1 +#define R_MMU_CTRL__inv_excp__disable 0 +#define R_MMU_CTRL__acc_excp__BITNR 1 +#define R_MMU_CTRL__acc_excp__WIDTH 1 +#define R_MMU_CTRL__acc_excp__enable 1 +#define R_MMU_CTRL__acc_excp__disable 0 +#define R_MMU_CTRL__we_excp__BITNR 0 +#define R_MMU_CTRL__we_excp__WIDTH 1 +#define R_MMU_CTRL__we_excp__enable 1 +#define R_MMU_CTRL__we_excp__disable 0 + +#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) +#define R_MMU_ENABLE__mmu_enable__BITNR 7 +#define R_MMU_ENABLE__mmu_enable__WIDTH 1 +#define R_MMU_ENABLE__mmu_enable__enable 1 +#define R_MMU_ENABLE__mmu_enable__disable 0 + +#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) +#define R_MMU_KBASE_LO__base_7__BITNR 28 +#define R_MMU_KBASE_LO__base_7__WIDTH 4 +#define R_MMU_KBASE_LO__base_6__BITNR 24 +#define R_MMU_KBASE_LO__base_6__WIDTH 4 +#define R_MMU_KBASE_LO__base_5__BITNR 20 +#define R_MMU_KBASE_LO__base_5__WIDTH 4 +#define R_MMU_KBASE_LO__base_4__BITNR 16 +#define R_MMU_KBASE_LO__base_4__WIDTH 4 +#define R_MMU_KBASE_LO__base_3__BITNR 12 +#define R_MMU_KBASE_LO__base_3__WIDTH 4 +#define R_MMU_KBASE_LO__base_2__BITNR 8 +#define R_MMU_KBASE_LO__base_2__WIDTH 4 +#define R_MMU_KBASE_LO__base_1__BITNR 4 +#define R_MMU_KBASE_LO__base_1__WIDTH 4 +#define R_MMU_KBASE_LO__base_0__BITNR 0 +#define R_MMU_KBASE_LO__base_0__WIDTH 4 + +#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) +#define R_MMU_KBASE_HI__base_f__BITNR 28 +#define R_MMU_KBASE_HI__base_f__WIDTH 4 +#define R_MMU_KBASE_HI__base_e__BITNR 24 +#define R_MMU_KBASE_HI__base_e__WIDTH 4 +#define R_MMU_KBASE_HI__base_d__BITNR 20 +#define R_MMU_KBASE_HI__base_d__WIDTH 4 +#define R_MMU_KBASE_HI__base_c__BITNR 16 +#define R_MMU_KBASE_HI__base_c__WIDTH 4 +#define R_MMU_KBASE_HI__base_b__BITNR 12 +#define R_MMU_KBASE_HI__base_b__WIDTH 4 +#define R_MMU_KBASE_HI__base_a__BITNR 8 +#define R_MMU_KBASE_HI__base_a__WIDTH 4 +#define R_MMU_KBASE_HI__base_9__BITNR 4 +#define R_MMU_KBASE_HI__base_9__WIDTH 4 +#define R_MMU_KBASE_HI__base_8__BITNR 0 +#define R_MMU_KBASE_HI__base_8__WIDTH 4 + +#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) +#define R_MMU_CONTEXT__page_id__BITNR 0 +#define R_MMU_CONTEXT__page_id__WIDTH 6 + +#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) +#define R_MMU_CAUSE__vpn__BITNR 13 +#define R_MMU_CAUSE__vpn__WIDTH 19 +#define R_MMU_CAUSE__miss_excp__BITNR 12 +#define R_MMU_CAUSE__miss_excp__WIDTH 1 +#define R_MMU_CAUSE__miss_excp__yes 1 +#define R_MMU_CAUSE__miss_excp__no 0 +#define R_MMU_CAUSE__inv_excp__BITNR 11 +#define R_MMU_CAUSE__inv_excp__WIDTH 1 +#define R_MMU_CAUSE__inv_excp__yes 1 +#define R_MMU_CAUSE__inv_excp__no 0 +#define R_MMU_CAUSE__acc_excp__BITNR 10 +#define R_MMU_CAUSE__acc_excp__WIDTH 1 +#define R_MMU_CAUSE__acc_excp__yes 1 +#define R_MMU_CAUSE__acc_excp__no 0 +#define R_MMU_CAUSE__we_excp__BITNR 9 +#define R_MMU_CAUSE__we_excp__WIDTH 1 +#define R_MMU_CAUSE__we_excp__yes 1 +#define R_MMU_CAUSE__we_excp__no 0 +#define R_MMU_CAUSE__wr_rd__BITNR 8 +#define R_MMU_CAUSE__wr_rd__WIDTH 1 +#define R_MMU_CAUSE__wr_rd__write 1 +#define R_MMU_CAUSE__wr_rd__read 0 +#define R_MMU_CAUSE__page_id__BITNR 0 +#define R_MMU_CAUSE__page_id__WIDTH 6 + +#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) +#define R_TLB_SELECT__index__BITNR 0 +#define R_TLB_SELECT__index__WIDTH 6 + +#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) +#define R_TLB_LO__pfn__BITNR 13 +#define R_TLB_LO__pfn__WIDTH 19 +#define R_TLB_LO__global__BITNR 3 +#define R_TLB_LO__global__WIDTH 1 +#define R_TLB_LO__global__yes 1 +#define R_TLB_LO__global__no 0 +#define R_TLB_LO__valid__BITNR 2 +#define R_TLB_LO__valid__WIDTH 1 +#define R_TLB_LO__valid__yes 1 +#define R_TLB_LO__valid__no 0 +#define R_TLB_LO__kernel__BITNR 1 +#define R_TLB_LO__kernel__WIDTH 1 +#define R_TLB_LO__kernel__yes 1 +#define R_TLB_LO__kernel__no 0 +#define R_TLB_LO__we__BITNR 0 +#define R_TLB_LO__we__WIDTH 1 +#define R_TLB_LO__we__yes 1 +#define R_TLB_LO__we__no 0 + +#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) +#define R_TLB_HI__vpn__BITNR 13 +#define R_TLB_HI__vpn__WIDTH 19 +#define R_TLB_HI__page_id__BITNR 0 +#define R_TLB_HI__page_id__WIDTH 6 + +/* +!* Syncrounous serial port registers +!*/ + +#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) +#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 + +#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) +#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 + +#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) +#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 + +#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) +#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 +#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 +#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 +#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 +#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 +#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 +#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 +#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 +#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 +#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 +#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 +#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 +#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 +#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 +#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__underflow__no 0 +#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 +#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 +#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__overrun__no 0 +#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 +#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 +#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 +#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 +#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 +#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 + +#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) +#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 + +#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) +#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 + +#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) +#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 + +#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) +#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 +#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 +#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 +#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 +#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 +#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 +#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 +#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 +#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 +#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 +#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 +#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 +#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 +#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 +#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 +#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__error__normal 0 +#define R_SYNC_SERIAL1_CTRL__error__ignore 1 +#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 +#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 +#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 +#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 +#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 +#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 +#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 +#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 +#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 +#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 +#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 +#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 +#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 +#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 +#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 +#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 +#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 +#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 +#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 +#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 +#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 +#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 +#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 +#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 +#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 +#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 +#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 +#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 +#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 +#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 +#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 +#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 +#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 +#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 +#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 +#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 +#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 +#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 +#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 +#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 +#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 + +#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) +#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 + +#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) +#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 + +#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) +#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 + +#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) +#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 +#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 +#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 +#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 +#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 +#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 +#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 +#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 +#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 +#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 +#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 +#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 +#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 +#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 +#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__underflow__no 0 +#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 +#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 +#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__overrun__no 0 +#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 +#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 +#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 +#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 +#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 +#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 + +#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) +#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 + +#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) +#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 + +#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) +#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 + +#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) +#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 +#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 +#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 +#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 +#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 +#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 +#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 +#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 +#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 +#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 +#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 +#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 +#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 +#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 +#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 +#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__error__normal 0 +#define R_SYNC_SERIAL3_CTRL__error__ignore 1 +#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 +#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 +#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 +#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 +#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 +#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 +#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 +#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 +#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 +#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 +#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 +#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 +#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 +#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 +#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 +#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 +#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 +#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 +#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 +#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 +#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 +#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 +#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 +#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 +#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 +#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 +#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 +#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 +#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 +#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 +#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 +#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 +#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 +#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 +#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 +#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 +#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 +#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 +#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 +#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 +#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 + diff --git a/arch/cris/include/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/arch-v10/arch/sv_addr_ag.h new file mode 100644 index 000000000000..e4a6b68b8982 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/sv_addr_ag.h @@ -0,0 +1,139 @@ +/*!************************************************************************** +*! +*! MACROS: +*! IO_MASK(reg,field) +*! IO_STATE(reg,field,state) +*! IO_EXTRACT(reg,field,val) +*! IO_STATE_VALUE(reg,field,state) +*! IO_BITNR(reg,field) +*! IO_WIDTH(reg,field) +*! IO_FIELD(reg,field,val) +*! IO_RD(reg) +*! All moderegister addresses and fields of these. +*! +*!**************************************************************************/ + +#ifndef __sv_addr_ag_h__ +#define __sv_addr_ag_h__ + + +#define __test_sv_addr__ 0 + +/*------------------------------------------------------------ +!* General macros to manipulate moderegisters. +!*-----------------------------------------------------------*/ + +/* IO_MASK returns a mask for a specified bitfield in a register. + Note that this macro doesn't work when field width is 32 bits. */ +#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) +#define IO_MASK_(reg_, field_) \ + ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) + +/* IO_STATE returns a constant corresponding to a one of the symbolic + states that the bitfield can have. (Shifted to correct position) */ +#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) +#define IO_STATE_(reg_, field_, _state) \ + ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) + +/* IO_EXTRACT returns the masked and shifted value corresponding to the + bitfield can have. */ +#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) +#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ + - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) + +/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic + states that the bitfield can have. (Not shifted) */ +#define IO_STATE_VALUE(reg, field, state) \ + IO_STATE_VALUE_ (reg##_, field##_, _##state) +#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) + +/* IO_FIELD shifts the val parameter to be aligned with the bitfield + specified. */ +#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) +#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) + +/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is + LSB and the returned bitnumber is LSB of the field. */ +#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) +#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) + +/* IO_WIDTH returns the width, in bits, of a bitfield. */ +#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) +#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) + +/*--- Obsolete. Kept for backw compatibility. ---*/ +/* Reads (or writes) a byte/uword/udword from the specified mode + register. */ +#define IO_RD(reg) (*(volatile u32*)(reg)) +#define IO_RD_B(reg) (*(volatile u8*)(reg)) +#define IO_RD_W(reg) (*(volatile u16*)(reg)) +#define IO_RD_D(reg) (*(volatile u32*)(reg)) + +/*------------------------------------------------------------ +!* Start addresses of the different memory areas. +!*-----------------------------------------------------------*/ + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +/*------------------------------------------------------------ +!* Type casts used in mode register macros, making pointer +!* dereferencing possible. Empty in assembler. +!*-----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ +# define IO_TYPECAST_UDWORD (volatile u32*) +# define IO_TYPECAST_RO_UDWORD (const volatile u32*) +# define IO_TYPECAST_UWORD (volatile u16*) +# define IO_TYPECAST_RO_UWORD (const volatile u16*) +# define IO_TYPECAST_BYTE (volatile u8*) +# define IO_TYPECAST_RO_BYTE (const volatile u8*) +#else +# define IO_TYPECAST_UDWORD +# define IO_TYPECAST_RO_UDWORD +# define IO_TYPECAST_UWORD +# define IO_TYPECAST_RO_UWORD +# define IO_TYPECAST_BYTE +# define IO_TYPECAST_RO_BYTE +#endif + +/*------------------------------------------------------------*/ + +#include "sv_addr.agh" + +#if __test_sv_addr__ +/* IO_MASK( R_BUS_CONFIG , CE ) */ +IO_MASK( R_WAITSTATES , SRAM_WS ) +IO_MASK( R_TEST , W32 ) + +IO_STATE( R_BUS_CONFIG, CE, DISABLE ) +IO_STATE( R_BUS_CONFIG, CE, ENABLE ) + +IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) + +IO_MASK( R_DRAM_TIMING, REF ) + +IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) + +IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) + == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) +#endif + + +#endif /* ifndef __sv_addr_ag_h__ */ + diff --git a/arch/cris/include/arch-v10/arch/svinto.h b/arch/cris/include/arch-v10/arch/svinto.h new file mode 100644 index 000000000000..0881a1af7cee --- /dev/null +++ b/arch/cris/include/arch-v10/arch/svinto.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CRIS_SVINTO_H +#define _ASM_CRIS_SVINTO_H + +#include "sv_addr_ag.h" + +extern unsigned int genconfig_shadow; /* defined and set in head.S */ + +/* dma stuff */ + +enum { /* Available in: */ + d_eol = (1 << 0), /* flags */ + d_eop = (1 << 1), /* flags & status */ + d_wait = (1 << 2), /* flags */ + d_int = (1 << 3), /* flags */ + d_txerr = (1 << 4), /* flags */ + d_stop = (1 << 4), /* status */ + d_ecp = (1 << 4), /* flags & status */ + d_pri = (1 << 5), /* flags & status */ + d_alignerr = (1 << 6), /* status */ + d_crcerr = (1 << 7) /* status */ +}; + +/* Do remember that DMA does not go through the MMU and needs + * a real physical address, not an address virtually mapped or + * paged. Therefore the buf/next ptrs below are unsigned long instead + * of void * to give a warning if you try to put a pointer directly + * to them instead of going through virt_to_phys/phys_to_virt. + */ + +typedef struct etrax_dma_descr { + unsigned short sw_len; /* 0-1 */ + unsigned short ctrl; /* 2-3 */ + unsigned long next; /* 4-7 */ + unsigned long buf; /* 8-11 */ + unsigned short hw_len; /* 12-13 */ + unsigned char status; /* 14 */ + unsigned char fifo_len; /* 15 */ +} etrax_dma_descr; + + +/* Use this for constant numbers only */ +#define RESET_DMA_NUM( n ) \ + *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) + +/* Use this for constant numbers or symbols, + * having two macros makes it possible to use constant expressions. + */ +#define RESET_DMA( n ) RESET_DMA_NUM( n ) + + +/* Use this for constant numbers only */ +#define WAIT_DMA_NUM( n ) \ + while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ + IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) + +/* Use this for constant numbers or symbols + * having two macros makes it possible to use constant expressions. + */ +#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) + +extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); +extern void flush_etrax_cache(void); + +#endif diff --git a/arch/cris/include/arch-v10/arch/system.h b/arch/cris/include/arch-v10/arch/system.h new file mode 100644 index 000000000000..4a9cd36c9e16 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/system.h @@ -0,0 +1,63 @@ +#ifndef __ASM_CRIS_ARCH_SYSTEM_H +#define __ASM_CRIS_ARCH_SYSTEM_H + + +/* read the CPU version register */ + +static inline unsigned long rdvr(void) { + unsigned char vr; + __asm__ volatile ("move $vr,%0" : "=rm" (vr)); + return vr; +} + +#define cris_machine_name "cris" + +/* read/write the user-mode stackpointer */ + +static inline unsigned long rdusp(void) { + unsigned long usp; + __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); + return usp; +} + +#define wrusp(usp) \ + __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) + +/* read the current stackpointer */ + +static inline unsigned long rdsp(void) { + unsigned long sp; + __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); + return sp; +} + +static inline unsigned long _get_base(char * addr) +{ + return 0; +} + +#define nop() __asm__ __volatile__ ("nop"); + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* interrupt control.. */ +#define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory"); +#define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory"); +#define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory"); +#define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory"); + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + !(flags & (1<<5)); \ +}) + +/* For spinlocks etc */ +#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory"); + +#endif diff --git a/arch/cris/include/arch-v10/arch/thread_info.h b/arch/cris/include/arch-v10/arch/thread_info.h new file mode 100644 index 000000000000..218f4152d3e5 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/thread_info.h @@ -0,0 +1,12 @@ +#ifndef _ASM_ARCH_THREAD_INFO_H +#define _ASM_ARCH_THREAD_INFO_H + +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); + return ti; +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/timex.h b/arch/cris/include/arch-v10/arch/timex.h new file mode 100644 index 000000000000..e48447d94faf --- /dev/null +++ b/arch/cris/include/arch-v10/arch/timex.h @@ -0,0 +1,30 @@ +/* + * Use prescale timer at 25000 Hz instead of the baudrate timer at + * 19200 to get rid of the 64ppm to fast timer (and we get better + * resolution within a jiffie as well. + */ +#ifndef _ASM_CRIS_ARCH_TIMEX_H +#define _ASM_CRIS_ARCH_TIMEX_H + +/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ +/* If you change anything here you must check time.c as well... */ +#define PRESCALE_FREQ 25000000 +#define PRESCALE_VALUE 1000 +#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ +/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ +#define TIMER0_FREQ (CLOCK_TICK_RATE) +#define TIMER0_CLKSEL flexible +#define TIMER0_DIV (TIMER0_FREQ/(HZ)) + + +#define GET_JIFFIES_USEC() \ + ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) + +unsigned long get_ns_in_jiffie(void); + +static inline unsigned long get_us_in_jiffie_highres(void) +{ + return get_ns_in_jiffie()/1000; +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/tlb.h b/arch/cris/include/arch-v10/arch/tlb.h new file mode 100644 index 000000000000..31525bbe75c3 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/tlb.h @@ -0,0 +1,13 @@ +#ifndef _CRIS_ARCH_TLB_H +#define _CRIS_ARCH_TLB_H + +/* The TLB can host up to 64 different mm contexts at the same time. + * The last page_id is never running - it is used as an invalid page_id + * so we can make TLB entries that will never match. + */ +#define NUM_TLB_ENTRIES 64 +#define NUM_PAGEID 64 +#define INVALID_PAGEID 63 +#define NO_CONTEXT -1 + +#endif diff --git a/arch/cris/include/arch-v10/arch/uaccess.h b/arch/cris/include/arch-v10/arch/uaccess.h new file mode 100644 index 000000000000..65b02d9b605a --- /dev/null +++ b/arch/cris/include/arch-v10/arch/uaccess.h @@ -0,0 +1,660 @@ +/* + * Authors: Bjorn Wesen (bjornw@axis.com) + * Hans-Peter Nilsson (hp@axis.com) + * + */ +#ifndef _CRIS_ARCH_UACCESS_H +#define _CRIS_ARCH_UACCESS_H + +/* + * We don't tell gcc that we are accessing memory, but this is OK + * because we do not write to any memory gcc knows about, so there + * are no aliasing issues. + * + * Note that PC at a fault is the address *after* the faulting + * instruction. + */ +#define __put_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + " "op" %1,[%2]\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __put_user_asm_64(x, addr, err) \ + __asm__ __volatile__( \ + " move.d %M1,[%2]\n" \ + "2: move.d %H1,[%2+4]\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +/* See comment before __put_user_asm. */ + +#define __get_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + " "op" [%2],%1\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " moveq 0,%1\n" \ + " jump 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __get_user_asm_64(x, addr, err) \ + __asm__ __volatile__( \ + " move.d [%2],%M1\n" \ + "2: move.d [%2+4],%H1\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " moveq 0,%1\n" \ + " jump 4b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +/* + * Copy a null terminated string from userspace. + * + * Must return: + * -EFAULT for an exception + * count if we hit the buffer limit + * bytes copied if we hit a null byte + * (without the null byte) + */ +static inline long +__do_strncpy_from_user(char *dst, const char *src, long count) +{ + long res; + + if (count == 0) + return 0; + + /* + * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. + * So do we. + * + * This code is deduced from: + * + * char tmp2; + * long tmp1, tmp3 + * tmp1 = count; + * while ((*dst++ = (tmp2 = *src++)) != 0 + * && --tmp1) + * ; + * + * res = count - tmp1; + * + * with tweaks. + */ + + __asm__ __volatile__ ( + " move.d %3,%0\n" + " move.b [%2+],$r9\n" + "1: beq 2f\n" + " move.b $r9,[%1+]\n" + + " subq 1,%0\n" + " bne 1b\n" + " move.b [%2+],$r9\n" + + "2: sub.d %3,%0\n" + " neg.d %0,%0\n" + "3:\n" + " .section .fixup,\"ax\"\n" + "4: move.d %7,%0\n" + " jump 3b\n" + + /* There's one address for a fault at the first move, and + two possible PC values for a fault at the second move, + being a delay-slot filler. However, the branch-target + for the second move is the same as the first address. + Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 1b,4b\n" + " .dword 2b,4b\n" + " .previous" + : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) + : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) + : "r9"); + + return res; +} + +/* A few copy asms to build up the more complex ones from. + + Note again, a post-increment is performed regardless of whether a bus + fault occurred in that instruction, and PC for a faulted insn is the + address *after* the insn. */ + +#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + COPY \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " jump 1b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous\n" \ + : "=r" (to), "=r" (from), "=r" (ret) \ + : "0" (to), "1" (from), "2" (ret) \ + : "r9", "memory") + +#define __asm_copy_from_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "2: move.b $r9,[%0+]\n", \ + "3: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "2: move.w $r9,[%0+]\n" COPY, \ + "3: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_from_user_2(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_3(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "4: move.b $r9,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "2: move.d $r9,[%0+]\n" COPY, \ + "3: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_from_user_4(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_5(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "4: move.b $r9,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "4: move.w $r9,[%0+]\n" COPY, \ + "5: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_from_user_6(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_7(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "6: move.b $r9,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "4: move.d $r9,[%0+]\n" COPY, \ + "5: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_from_user_8(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_9(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "6: move.b $r9,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "6: move.w $r9,[%0+]\n" COPY, \ + "7: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_from_user_10(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_11(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "8: move.b $r9,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "6: move.d $r9,[%0+]\n" COPY, \ + "7: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_from_user_12(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_13(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "8: move.b $r9,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "8: move.w $r9,[%0+]\n" COPY, \ + "9: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_from_user_14(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_15(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "10: move.b $r9,[%0+]\n", \ + "11: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "8: move.d $r9,[%0+]\n" COPY, \ + "9: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_from_user_16(to, from, ret) \ + __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_16x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "10: move.d $r9,[%0+]\n" COPY, \ + "11: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 10b,11b\n" TENTRY) + +#define __asm_copy_from_user_20(to, from, ret) \ + __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_20x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "12: move.d $r9,[%0+]\n" COPY, \ + "13: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 12b,13b\n" TENTRY) + +#define __asm_copy_from_user_24(to, from, ret) \ + __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") + +/* And now, the to-user ones. */ + +#define __asm_copy_to_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n2:\n", \ + "3: addq 1,%2\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n2:\n" COPY, \ + "3: addq 2,%2\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_to_user_2(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_3(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n4:\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n2:\n" COPY, \ + "3: addq 4,%2\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_to_user_4(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_5(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n4:\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n4:\n" COPY, \ + "5: addq 2,%2\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_to_user_6(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_7(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n6:\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n4:\n" COPY, \ + "5: addq 4,%2\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_to_user_8(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_9(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n6:\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n6:\n" COPY, \ + "7: addq 2,%2\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_to_user_10(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_11(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n8:\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n6:\n" COPY, \ + "7: addq 4,%2\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_to_user_12(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_13(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n8:\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n8:\n" COPY, \ + "9: addq 2,%2\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_to_user_14(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_15(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n10:\n", \ + "11: addq 1,%2\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n8:\n" COPY, \ + "9: addq 4,%2\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_to_user_16(to, from, ret) \ + __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_16x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n10:\n" COPY, \ + "11: addq 4,%2\n" FIXUP, \ + " .dword 10b,11b\n" TENTRY) + +#define __asm_copy_to_user_20(to, from, ret) \ + __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_20x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n12:\n" COPY, \ + "13: addq 4,%2\n" FIXUP, \ + " .dword 12b,13b\n" TENTRY) + +#define __asm_copy_to_user_24(to, from, ret) \ + __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") + +/* Define a few clearing asms with exception handlers. */ + +/* This frame-asm is like the __asm_copy_user_cont one, but has one less + input. */ + +#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + CLEAR \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " jump 1b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous" \ + : "=r" (to), "=r" (ret) \ + : "0" (to), "1" (ret) \ + : "memory") + +#define __asm_clear_1(to, ret) \ + __asm_clear(to, ret, \ + " clear.b [%0+]\n2:\n", \ + "3: addq 1,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_2(to, ret) \ + __asm_clear(to, ret, \ + " clear.w [%0+]\n2:\n", \ + "3: addq 2,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_3(to, ret) \ + __asm_clear(to, ret, \ + " clear.w [%0+]\n" \ + "2: clear.b [%0+]\n3:\n", \ + "4: addq 2,%1\n" \ + "5: addq 1,%1\n", \ + " .dword 2b,4b\n" \ + " .dword 3b,5b\n") + +#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear(to, ret, \ + " clear.d [%0+]\n2:\n" CLEAR, \ + "3: addq 4,%1\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_clear_4(to, ret) \ + __asm_clear_4x_cont(to, ret, "", "", "") + +#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_4x_cont(to, ret, \ + " clear.d [%0+]\n4:\n" CLEAR, \ + "5: addq 4,%1\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_clear_8(to, ret) \ + __asm_clear_8x_cont(to, ret, "", "", "") + +#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_8x_cont(to, ret, \ + " clear.d [%0+]\n6:\n" CLEAR, \ + "7: addq 4,%1\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_clear_12(to, ret) \ + __asm_clear_12x_cont(to, ret, "", "", "") + +#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_12x_cont(to, ret, \ + " clear.d [%0+]\n8:\n" CLEAR, \ + "9: addq 4,%1\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_clear_16(to, ret) \ + __asm_clear_16x_cont(to, ret, "", "", "") + +#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_16x_cont(to, ret, \ + " clear.d [%0+]\n10:\n" CLEAR, \ + "11: addq 4,%1\n" FIXUP, \ + " .dword 10b,11b\n" TENTRY) + +#define __asm_clear_20(to, ret) \ + __asm_clear_20x_cont(to, ret, "", "", "") + +#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_20x_cont(to, ret, \ + " clear.d [%0+]\n12:\n" CLEAR, \ + "13: addq 4,%1\n" FIXUP, \ + " .dword 12b,13b\n" TENTRY) + +#define __asm_clear_24(to, ret) \ + __asm_clear_24x_cont(to, ret, "", "", "") + +/* + * Return the size of a string (including the ending 0) + * + * Return length of string in userspace including terminating 0 + * or 0 for error. Return a value greater than N if too long. + */ + +static inline long +strnlen_user(const char *s, long n) +{ + long res, tmp1; + + if (!access_ok(VERIFY_READ, s, 0)) + return 0; + + /* + * This code is deduced from: + * + * tmp1 = n; + * while (tmp1-- > 0 && *s++) + * ; + * + * res = n - tmp1; + * + * (with tweaks). + */ + + __asm__ __volatile__ ( + " move.d %1,$r9\n" + "0:\n" + " ble 1f\n" + " subq 1,$r9\n" + + " test.b [%0+]\n" + " bne 0b\n" + " test.d $r9\n" + "1:\n" + " move.d %1,%0\n" + " sub.d $r9,%0\n" + "2:\n" + " .section .fixup,\"ax\"\n" + + "3: clear.d %0\n" + " jump 2b\n" + + /* There's one address for a fault at the first move, and + two possible PC values for a fault at the second move, + being a delay-slot filler. However, the branch-target + for the second move is the same as the first address. + Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 0b,3b\n" + " .dword 1b,3b\n" + " .previous\n" + : "=r" (res), "=r" (tmp1) + : "0" (s), "1" (n) + : "r9"); + + return res; +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/unistd.h b/arch/cris/include/arch-v10/arch/unistd.h new file mode 100644 index 000000000000..d1a38b9e6264 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/unistd.h @@ -0,0 +1,148 @@ +#ifndef _ASM_CRIS_ARCH_UNISTD_H_ +#define _ASM_CRIS_ARCH_UNISTD_H_ + +/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ +/* + * Don't remove the .ifnc tests; they are an insurance against + * any hard-to-spot gcc register allocation bugs. + */ +#define _syscall0(type,name) \ +type name(void) \ +{ \ + register long __a __asm__ ("r10"); \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1,type2 arg2) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1,type2 arg2,type3 arg3) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "move %6,$mof\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "g" (arg5)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5,type6,arg6) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "move %6,$mof\n\tmove %7,$srp\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ + : "srp"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#endif diff --git a/arch/cris/include/arch-v10/arch/user.h b/arch/cris/include/arch-v10/arch/user.h new file mode 100644 index 000000000000..9303ea77c915 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/user.h @@ -0,0 +1,46 @@ +#ifndef __ASM_CRIS_ARCH_USER_H +#define __ASM_CRIS_ARCH_USER_H + +/* User mode registers, used for core dumps. In order to keep ELF_NGREG + sensible we let all registers be 32 bits. The csr registers are included + for future use. */ +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* Stack pointer. */ + unsigned long pc; /* Program counter. */ + unsigned long p0; /* Constant zero (only 8 bits). */ + unsigned long vr; /* Version register (only 8 bits). */ + unsigned long p2; /* Reserved. */ + unsigned long p3; /* Reserved. */ + unsigned long p4; /* Constant zero (only 16 bits). */ + unsigned long ccr; /* Condition code register (only 16 bits). */ + unsigned long p6; /* Reserved. */ + unsigned long mof; /* Multiply overflow register. */ + unsigned long p8; /* Constant zero. */ + unsigned long ibr; /* Not accessible. */ + unsigned long irp; /* Not accessible. */ + unsigned long srp; /* Subroutine return pointer. */ + unsigned long bar; /* Not accessible. */ + unsigned long dccr; /* Dword condition code register. */ + unsigned long brp; /* Not accessible. */ + unsigned long usp; /* User-mode stack pointer. Same as sp when + in user mode. */ + unsigned long csrinstr; /* Internal status registers. */ + unsigned long csraddr; + unsigned long csrdata; +}; + +#endif diff --git a/arch/cris/include/arch-v32/arch/Kbuild b/arch/cris/include/arch-v32/arch/Kbuild new file mode 100644 index 000000000000..35f2fc4f993e --- /dev/null +++ b/arch/cris/include/arch-v32/arch/Kbuild @@ -0,0 +1,2 @@ +header-y += user.h +header-y += cryptocop.h diff --git a/arch/cris/include/arch-v32/arch/atomic.h b/arch/cris/include/arch-v32/arch/atomic.h new file mode 100644 index 000000000000..852ceff8013f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/atomic.h @@ -0,0 +1,36 @@ +#ifndef __ASM_CRIS_ARCH_ATOMIC__ +#define __ASM_CRIS_ARCH_ATOMIC__ + +#include + +extern void cris_spin_unlock(void *l, int val); +extern void cris_spin_lock(void *l); +extern int cris_spin_trylock(void* l); + +#ifndef CONFIG_SMP +#define cris_atomic_save(addr, flags) local_irq_save(flags); +#define cris_atomic_restore(addr, flags) local_irq_restore(flags); +#else + +extern spinlock_t cris_atomic_locks[]; +#define LOCK_COUNT 128 +#define HASH_ADDR(a) (((int)a) & 127) + +#define cris_atomic_save(addr, flags) \ + local_irq_save(flags); \ + cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock); + +#define cris_atomic_restore(addr, flags) \ + { \ + spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ + __asm__ volatile ("move.d %1,%0" \ + : "=m" (lock->raw_lock.slock) \ + : "r" (1) \ + : "memory"); \ + local_irq_restore(flags); \ + } + +#endif + +#endif + diff --git a/arch/cris/include/arch-v32/arch/bitops.h b/arch/cris/include/arch-v32/arch/bitops.h new file mode 100644 index 000000000000..147689d6b624 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/bitops.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CRIS_ARCH_BITOPS_H +#define _ASM_CRIS_ARCH_BITOPS_H + +/* + * Helper functions for the core of the ff[sz] functions. They compute the + * number of leading zeroes of a bits-in-byte, byte-in-word and + * word-in-dword-swapped number. They differ in that the first function also + * inverts all bits in the input. + */ + +static inline unsigned long +cris_swapnwbrlz(unsigned long w) +{ + unsigned long res; + + __asm__ __volatile__ ("swapnwbr %0\n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + + return res; +} + +static inline unsigned long +cris_swapwbrlz(unsigned long w) +{ + unsigned long res; + + __asm__ __volatile__ ("swapwbr %0\n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + + return res; +} + +/* + * Find First Zero in word. Undefined if no zero exist, so the caller should + * check against ~0 first. + */ +static inline unsigned long +ffz(unsigned long w) +{ + return cris_swapnwbrlz(w); +} + +/* + * Find First Set bit in word. Undefined if no 1 exist, so the caller + * should check against 0 first. + */ +static inline unsigned long +__ffs(unsigned long w) +{ + return cris_swapnwbrlz(~w); +} + +/* + * Find First Bit that is set. + */ +static inline unsigned long +kernel_ffs(unsigned long w) +{ + return w ? cris_swapwbrlz (w) + 1 : 0; +} + +#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/arch/cris/include/arch-v32/arch/bug.h b/arch/cris/include/arch-v32/arch/bug.h new file mode 100644 index 000000000000..0f211e135248 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/bug.h @@ -0,0 +1,33 @@ +#ifndef __ASM_CRISv32_ARCH_BUG_H +#define __ASM_CRISv32_ARCH_BUG_H + +#include + +#ifdef CONFIG_BUG +#ifdef CONFIG_DEBUG_BUGVERBOSE +/* + * The penalty for the in-band code path will be the size of break 14. + * All other stuff is done out-of-band with exception handlers. + */ +#define BUG() \ + __asm__ __volatile__ ("0: break 14\n\t" \ + ".section .fixup,\"ax\"\n" \ + "1:\n\t" \ + "move.d %0, $r10\n\t" \ + "move.d %1, $r11\n\t" \ + "jump do_BUG\n\t" \ + "nop\n\t" \ + ".previous\n\t" \ + ".section __ex_table,\"a\"\n\t" \ + ".dword 0b, 1b\n\t" \ + ".previous\n\t" \ + : : "ri" (__FILE__), "i" (__LINE__)) +#else +#define BUG() __asm__ __volatile__ ("break 14\n\t") +#endif + +#define HAVE_ARCH_BUG +#endif + +#include +#endif diff --git a/arch/cris/include/arch-v32/arch/byteorder.h b/arch/cris/include/arch-v32/arch/byteorder.h new file mode 100644 index 000000000000..6ef8fb4a35f2 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/byteorder.h @@ -0,0 +1,20 @@ +#ifndef _ASM_CRIS_ARCH_BYTEORDER_H +#define _ASM_CRIS_ARCH_BYTEORDER_H + +#include + +static inline __const__ __u32 +___arch__swab32(__u32 x) +{ + __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); + return (x); +} + +static inline __const__ __u16 +___arch__swab16(__u16 x) +{ + __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); + return (x); +} + +#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */ diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h new file mode 100644 index 000000000000..dfc73050e6b4 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/cache.h @@ -0,0 +1,19 @@ +#ifndef _ASM_CRIS_ARCH_CACHE_H +#define _ASM_CRIS_ARCH_CACHE_H + +#include + +/* A cache-line is 32 bytes. */ +#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 + +void flush_dma_list(dma_descr_data *descr); +void flush_dma_descr(dma_descr_data *descr, int flush_buf); + +#define flush_dma_context(c) \ + flush_dma_list(phys_to_virt((c)->saved_data)); + +void cris_flush_cache_range(void *buf, unsigned long len); +void cris_flush_cache(void); + +#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/arch/cris/include/arch-v32/arch/checksum.h b/arch/cris/include/arch-v32/arch/checksum.h new file mode 100644 index 000000000000..e5dcfce6e0dc --- /dev/null +++ b/arch/cris/include/arch-v32/arch/checksum.h @@ -0,0 +1,29 @@ +#ifndef _ASM_CRIS_ARCH_CHECKSUM_H +#define _ASM_CRIS_ARCH_CHECKSUM_H + +/* + * Check values used in TCP/UDP headers. + * + * The gain of doing this in assembler instead of C, is that C doesn't + * generate carry-additions for the 32-bit components of the + * checksum. Which means it would be necessary to split all those into + * 16-bit components and then add. + */ +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, + unsigned short len, unsigned short proto, __wsum sum) +{ + __wsum res; + + __asm__ __volatile__ ("add.d %2, %0\n\t" + "addc %3, %0\n\t" + "addc %4, %0\n\t" + "addc 0, %0\n\t" + : "=r" (res) + : "0" (sum), "r" (daddr), "r" (saddr), \ + "r" ((len + proto) << 8)); + + return res; +} + +#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/arch/cris/include/arch-v32/arch/cryptocop.h b/arch/cris/include/arch-v32/arch/cryptocop.h new file mode 100644 index 000000000000..e1cd83dfabb5 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/cryptocop.h @@ -0,0 +1,272 @@ +/* + * The device /dev/cryptocop is accessible using this driver using + * CRYPTOCOP_MAJOR (254) and minor number 0. + */ + +#ifndef CRYPTOCOP_H +#define CRYPTOCOP_H + +#include + + +#define CRYPTOCOP_SESSION_ID_NONE (0) + +typedef unsigned long long int cryptocop_session_id; + +/* cryptocop ioctls */ +#define ETRAXCRYPTOCOP_IOCTYPE (250) + +#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) +#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) +#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) +#define CRYPTOCOP_IO_MAXNR (3) + +typedef enum { + cryptocop_cipher_des = 0, + cryptocop_cipher_3des = 1, + cryptocop_cipher_aes = 2, + cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ + cryptocop_cipher_none +} cryptocop_cipher_type; + +typedef enum { + cryptocop_digest_sha1 = 0, + cryptocop_digest_md5 = 1, + cryptocop_digest_none +} cryptocop_digest_type; + +typedef enum { + cryptocop_csum_le = 0, + cryptocop_csum_be = 1, + cryptocop_csum_none +} cryptocop_csum_type; + +typedef enum { + cryptocop_cipher_mode_ecb = 0, + cryptocop_cipher_mode_cbc, + cryptocop_cipher_mode_none +} cryptocop_cipher_mode; + +typedef enum { + cryptocop_3des_eee = 0, + cryptocop_3des_eed = 1, + cryptocop_3des_ede = 2, + cryptocop_3des_edd = 3, + cryptocop_3des_dee = 4, + cryptocop_3des_ded = 5, + cryptocop_3des_dde = 6, + cryptocop_3des_ddd = 7 +} cryptocop_3des_mode; + +/* Usermode accessible (ioctl) operations. */ +struct strcop_session_op{ + cryptocop_session_id ses_id; + + cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ + + cryptocop_cipher_mode cmode; /* ECB, CBC, none */ + cryptocop_3des_mode des3_mode; + + cryptocop_digest_type digest; /* MD5, SHA1, none */ + + cryptocop_csum_type csum; /* BE, LE, none */ + + unsigned char *key; + size_t keylen; +}; + +#define CRYPTOCOP_CSUM_LENGTH (2) +#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ +#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ +#define CRYPTOCOP_MAX_KEY_LENGTH (32) + +struct strcop_crypto_op{ + cryptocop_session_id ses_id; + + /* Indata. */ + unsigned char *indata; + size_t inlen; /* Total indata length. */ + + /* Cipher configuration. */ + unsigned char do_cipher:1; + unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ + unsigned char cipher_explicit:1; + size_t cipher_start; + size_t cipher_len; + /* cipher_iv is used if do_cipher and cipher_explicit and the cipher + mode is CBC. The length is controlled by the type of cipher, + e.g. DES/3DES 8 octets and AES 16 octets. */ + unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; + /* Outdata. */ + unsigned char *cipher_outdata; + size_t cipher_outlen; + + /* digest configuration. */ + unsigned char do_digest:1; + size_t digest_start; + size_t digest_len; + /* Outdata. The actual length is determined by the type of the digest. */ + unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; + + /* Checksum configuration. */ + unsigned char do_csum:1; + size_t csum_start; + size_t csum_len; + /* Outdata. */ + unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; +}; + + + +#ifdef __KERNEL__ + +/********** The API to use from inside the kernel. ************/ + +#include + +typedef enum { + cryptocop_alg_csum = 0, + cryptocop_alg_mem2mem, + cryptocop_alg_md5, + cryptocop_alg_sha1, + cryptocop_alg_des, + cryptocop_alg_3des, + cryptocop_alg_aes, + cryptocop_no_alg, +} cryptocop_algorithm; + +typedef u8 cryptocop_tfrm_id; + + +struct cryptocop_operation; + +typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); + +struct cryptocop_transform_init { + cryptocop_algorithm alg; + /* Keydata for ciphers. */ + unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; + unsigned int keylen; + cryptocop_cipher_mode cipher_mode; + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ + + cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ + struct cryptocop_transform_init *next; +}; + + +typedef enum { + cryptocop_source_dma = 0, + cryptocop_source_des, + cryptocop_source_3des, + cryptocop_source_aes, + cryptocop_source_md5, + cryptocop_source_sha1, + cryptocop_source_csum, + cryptocop_source_none, +} cryptocop_source; + + +struct cryptocop_desc_cfg { + cryptocop_tfrm_id tid; + cryptocop_source src; + unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ + struct cryptocop_desc_cfg *next; +}; + +struct cryptocop_desc { + size_t length; + struct cryptocop_desc_cfg *cfg; + struct cryptocop_desc *next; +}; + + +/* Flags for cryptocop_tfrm_cfg */ +#define CRYPTOCOP_NO_FLAG (0x00) +#define CRYPTOCOP_ENCRYPT (0x01) +#define CRYPTOCOP_DECRYPT (0x02) +#define CRYPTOCOP_EXPLICIT_IV (0x04) + +struct cryptocop_tfrm_cfg { + cryptocop_tfrm_id tid; + + unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ + + /* CBC initialisation vector for cihers. */ + u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; + + /* The position in output where to write the transform output. The order + in which the driver writes the output is unspecified, hence if several + transforms write on the same positions in the output the result is + unspecified. */ + size_t inject_ix; + + struct cryptocop_tfrm_cfg *next; +}; + + + +struct cryptocop_dma_list_operation{ + /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in + struct cryptocop_operation must be set for the driver to use them. outlist, + out_data_buf, inlist and in_data_buf must all be physical addresses since they will + be loaded to DMA . */ + dma_descr_data *outlist; /* Out from memory to the co-processor. */ + char *out_data_buf; + dma_descr_data *inlist; /* In from the co-processor to memory. */ + char *in_data_buf; + + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; +}; + + +struct cryptocop_tfrm_operation{ + /* Operation configuration, if not 'use_dmalists' is set. */ + struct cryptocop_tfrm_cfg *tfrm_cfg; + struct cryptocop_desc *desc; + + struct iovec *indata; + size_t incount; + size_t inlen; /* Total inlength. */ + + struct iovec *outdata; + size_t outcount; + size_t outlen; /* Total outlength. */ +}; + + +struct cryptocop_operation { + cryptocop_callback *cb; + void *cb_data; + + cryptocop_session_id sid; + + /* The status of the operation when returned to consumer. */ + int operation_status; /* 0, -EAGAIN */ + + /* Flags */ + unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ + unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ + unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ + + union{ + struct cryptocop_dma_list_operation list_op; + struct cryptocop_tfrm_operation tfrm_op; + }; +}; + + +int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); +int cryptocop_free_session(cryptocop_session_id sid); + +int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); + +int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); + +int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); + +#endif /* __KERNEL__ */ + +#endif /* CRYPTOCOP_H */ diff --git a/arch/cris/include/arch-v32/arch/delay.h b/arch/cris/include/arch-v32/arch/delay.h new file mode 100644 index 000000000000..e9fda03810a9 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/delay.h @@ -0,0 +1,28 @@ +#ifndef _ASM_CRIS_ARCH_DELAY_H +#define _ASM_CRIS_ARCH_DELAY_H + +extern void cris_delay10ns(u32 n10ns); +#define udelay(u) cris_delay10ns((u)*100) +#define ndelay(n) cris_delay10ns(((n)+9)/10) + +/* + * Not used anymore for udelay or ndelay. Referenced by + * e.g. init/calibrate.c. All other references are likely bugs; + * should be replaced by mdelay, udelay or ndelay. + */ + +static inline void +__delay(int loops) +{ + __asm__ __volatile__ ( + "move.d %0, $r9\n\t" + "beq 2f\n\t" + "subq 1, $r9\n\t" + "1:\n\t" + "bne 1b\n\t" + "subq 1, $r9\n" + "2:" + : : "g" (loops) : "r9"); +} + +#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/arch/cris/include/arch-v32/arch/dma.h b/arch/cris/include/arch-v32/arch/dma.h new file mode 100644 index 000000000000..3674081389fd --- /dev/null +++ b/arch/cris/include/arch-v32/arch/dma.h @@ -0,0 +1,79 @@ +#ifndef _ASM_ARCH_CRIS_DMA_H +#define _ASM_ARCH_CRIS_DMA_H + +/* Defines for using and allocating dma channels. */ + +#define MAX_DMA_CHANNELS 10 + +#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ +#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ + +#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ +#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ + +#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ +#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ + +#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ +#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ + +#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ +#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ + +#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ +#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ + +#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ +#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ + +#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ +#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ + +#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ +#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ + +#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ +#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ + +#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ +#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ + +#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ +#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ + +#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ +#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ + +#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ +#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ + +enum dma_owner +{ + dma_eth0, + dma_eth1, + dma_iop0, + dma_iop1, + dma_ser0, + dma_ser1, + dma_ser2, + dma_ser3, + dma_sser0, + dma_sser1, + dma_ata, + dma_strp, + dma_ext0, + dma_ext1, + dma_ext2, + dma_ext3 +}; + +int crisv32_request_dma(unsigned int dmanr, const char * device_id, + unsigned options, unsigned bandwidth, enum dma_owner owner); +void crisv32_free_dma(unsigned int dmanr); + +/* Masks used by crisv32_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR 1 +#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) +#define DMA_INT_MEM 4 + +#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/arch/cris/include/arch-v32/arch/elf.h b/arch/cris/include/arch-v32/arch/elf.h new file mode 100644 index 000000000000..1324e505a4d8 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/elf.h @@ -0,0 +1,73 @@ +#ifndef _ASM_CRIS_ELF_H +#define _ASM_CRIS_ELF_H + +#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_CRIS \ + && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ + || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) + +/* CRISv32 ELF register definitions. */ + +#include + +/* Explicitly zero out registers to increase determinism. */ +#define ELF_PLAT_INIT(_r, load_addr) do { \ + (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ + (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ + (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ + (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ + (_r)->acr = 0; \ +} while (0) + +/* + * An executable for which elf_read_implies_exec() returns TRUE will + * have the READ_IMPLIES_EXEC personality flag set automatically. + */ +#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) + +/* + * This is basically a pt_regs with the additional definition + * of the stack pointer since it's needed in a core dump. + * pr_regs is a elf_gregset_t and should be filled according + * to the layout of user_regs_struct. + */ +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + pr_reg[0] = regs->r0; \ + pr_reg[1] = regs->r1; \ + pr_reg[2] = regs->r2; \ + pr_reg[3] = regs->r3; \ + pr_reg[4] = regs->r4; \ + pr_reg[5] = regs->r5; \ + pr_reg[6] = regs->r6; \ + pr_reg[7] = regs->r7; \ + pr_reg[8] = regs->r8; \ + pr_reg[9] = regs->r9; \ + pr_reg[10] = regs->r10; \ + pr_reg[11] = regs->r11; \ + pr_reg[12] = regs->r12; \ + pr_reg[13] = regs->r13; \ + pr_reg[14] = rdusp(); /* SP */ \ + pr_reg[15] = regs->acr; /* ACR */ \ + pr_reg[16] = 0; /* BZ */ \ + pr_reg[17] = rdvr(); /* VR */ \ + pr_reg[18] = 0; /* PID */ \ + pr_reg[19] = regs->srs; /* SRS */ \ + pr_reg[20] = 0; /* WZ */ \ + pr_reg[21] = regs->exs; /* EXS */ \ + pr_reg[22] = regs->eda; /* EDA */ \ + pr_reg[23] = regs->mof; /* MOF */ \ + pr_reg[24] = 0; /* DZ */ \ + pr_reg[25] = 0; /* EBP */ \ + pr_reg[26] = regs->erp; /* ERP */ \ + pr_reg[27] = regs->srp; /* SRP */ \ + pr_reg[28] = 0; /* NRP */ \ + pr_reg[29] = regs->ccs; /* CCS */ \ + pr_reg[30] = rdusp(); /* USP */ \ + pr_reg[31] = regs->spc; /* SPC */ \ + +#endif /* _ASM_CRIS_ELF_H */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/Makefile b/arch/cris/include/arch-v32/arch/hwregs/Makefile new file mode 100644 index 000000000000..f9a05d2aa061 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/Makefile @@ -0,0 +1,186 @@ +# Makefile to generate or copy the latest register definitions +# and related datastructures and helpermacros. +# The offical place for these files is at: +RELEASE ?= r1_alfa5 +OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ + +# which is updated on each new release. +INCL_ASMFILES = +INCL_FILES = ata_defs.h +INCL_FILES += bif_core_defs.h +INCL_ASMFILES += bif_core_defs_asm.h +INCL_FILES += bif_slave_defs.h +#INCL_FILES += bif_slave_ext_defs.h +INCL_FILES += config_defs.h +INCL_ASMFILES += config_defs_asm.h +INCL_FILES += cpu_vect.h +#INCL_FILES += cris_defs.h +#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h +INCL_FILES += dma.h +INCL_FILES += dma_defs.h +INCL_FILES += eth_defs.h +INCL_FILES += extmem_defs.h +INCL_FILES += gio_defs.h +INCL_ASMFILES += gio_defs_asm.h +INCL_FILES += intr_vect.h +INCL_FILES += intr_vect_defs.h +INCL_ASMFILES += intr_vect_defs_asm.h +INCL_FILES += marb_bp_defs.h +INCL_FILES += marb_defs.h +INCL_ASMFILES += mmu_defs_asm.h +#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h +#INCL_FILES += par_defs.h # No useful content +INCL_FILES += pinmux_defs.h +INCL_FILES += reg_map.h +INCL_ASMFILES += reg_map_asm.h +INCL_FILES += reg_rdwr.h +INCL_FILES += ser_defs.h +#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h +INCL_FILES += sser_defs.h +INCL_FILES += strcop_defs.h +#INCL_FILES += strcop.h # Where is this? +INCL_FILES += strmux_defs.h +#INCL_FILES += supp_reg.h # Handcrafted instead +INCL_FILES += timer_defs.h + +REGDESC = +REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r +REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r +REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r +#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r +REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r +REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r +REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r +REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r +REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r +REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r +REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r +REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r +#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r +REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r +REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r +REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r +REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r +REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r +#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r + + +BASEDIR = /n/asic/design +DESIGNDIR = /n/asic/projects/guinness/design +RDES2C = /n/asic/bin/rdes2c +RDES2C = /n/asic/design/tools/rdesc/rdes2c +RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr +RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt + +## all - Just print help - you probably want to do 'make gen' +all: help + +# Disable implicit rule that may generate deleted files from RCS/ directory. +%.r: + +%.h: + +## help - This help +help: + @grep '^## ' Makefile + +## gen - Generate include files +gen: $(INCL_FILES) $(INCL_ASMFILES) + +ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r + $(RDES2C) $< +config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r + $(RDES2C) $< +config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r + $(RDES2C) -asm $< +# Can't generate cpu_vect.h yet +#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? +# $(RDES2INTR) $< +cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r + $(RDES2C) $< +$(BASEDIR)/core/dma/sw/dma.h: +dma.h: $(BASEDIR)/core/dma/sw/dma.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r + $(RDES2C) $< +extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r + $(RDES2C) $< +gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r + $(RDES2C) $< +intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r + $(RDES2C) $< +intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r + $(RDES2C) -asm $< +# Can't generate intr_vect.h yet +#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r +# $(RDES2INTR) $< +intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r + $(RDES2C) -asm $< +par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r + $(RDES2C) $< + +# From /n/asic/projects/guinness/design/ +reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap + $(RDES2C) -base 0xb0000000 $^ +reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap + $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ + +reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ + +ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r + $(RDES2C) $< +strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r + $(RDES2C) $< +strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r + $(RDES2C) $< +timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r + $(RDES2C) $< +usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r + $(RDES2C) $< + +## copy - Copy files from official location +copy: + @for HFILE in $(INCL_FILES); do \ + echo " $$HFILE"; \ + cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @for HFILE in $(INCL_ASMFILES); do \ + echo " $$HFILE"; \ + cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done +## ls_official - List official location +ls_official: + (cd $(OFFICIAL_INCDIR); ls -l *.h ) + +## diff_official - Diff current directory with official location +diff_official: + diff . $(OFFICIAL_INCDIR) + +## doc - Generate .axw files from register description. +doc: $(REGDESC) + for RDES in $^; do \ + $(RDES2TXT) $$RDES; \ + done + +.PHONY: axw +## %.axw - Generate the specified .axw file (doesn't work for all files +## due to inconsistent naming ir .r files. +%.axw: axw + @for RDES in $(REGDESC); do \ + if echo "$$RDES" | grep $* ; then \ + $(RDES2TXT) $$RDES; \ + fi \ + done + +.PHONY: clean +## clean - Remove .h files and .axw files. +clean: + rm -rf $(INCL_FILES) *.axw + diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h new file mode 100644 index 000000000000..866191418f9c --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h @@ -0,0 +1,222 @@ +#ifndef __ata_defs_asm_h +#define __ata_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/ata/rtl/ata_regs.r + * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp + * last modfied: Mon Apr 11 16:06:25 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r + * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ctrl0, scope ata, type rw */ +#define reg_ata_rw_ctrl0___pio_hold___lsb 0 +#define reg_ata_rw_ctrl0___pio_hold___width 6 +#define reg_ata_rw_ctrl0___pio_strb___lsb 6 +#define reg_ata_rw_ctrl0___pio_strb___width 6 +#define reg_ata_rw_ctrl0___pio_setup___lsb 12 +#define reg_ata_rw_ctrl0___pio_setup___width 6 +#define reg_ata_rw_ctrl0___dma_hold___lsb 18 +#define reg_ata_rw_ctrl0___dma_hold___width 6 +#define reg_ata_rw_ctrl0___dma_strb___lsb 24 +#define reg_ata_rw_ctrl0___dma_strb___width 6 +#define reg_ata_rw_ctrl0___rst___lsb 30 +#define reg_ata_rw_ctrl0___rst___width 1 +#define reg_ata_rw_ctrl0___rst___bit 30 +#define reg_ata_rw_ctrl0___en___lsb 31 +#define reg_ata_rw_ctrl0___en___width 1 +#define reg_ata_rw_ctrl0___en___bit 31 +#define reg_ata_rw_ctrl0_offset 12 + +/* Register rw_ctrl1, scope ata, type rw */ +#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 +#define reg_ata_rw_ctrl1___udma_tcyc___width 4 +#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 +#define reg_ata_rw_ctrl1___udma_tdvs___width 4 +#define reg_ata_rw_ctrl1_offset 16 + +/* Register rw_ctrl2, scope ata, type rw */ +#define reg_ata_rw_ctrl2___data___lsb 0 +#define reg_ata_rw_ctrl2___data___width 16 +#define reg_ata_rw_ctrl2___dma_size___lsb 19 +#define reg_ata_rw_ctrl2___dma_size___width 1 +#define reg_ata_rw_ctrl2___dma_size___bit 19 +#define reg_ata_rw_ctrl2___multi___lsb 20 +#define reg_ata_rw_ctrl2___multi___width 1 +#define reg_ata_rw_ctrl2___multi___bit 20 +#define reg_ata_rw_ctrl2___hsh___lsb 21 +#define reg_ata_rw_ctrl2___hsh___width 2 +#define reg_ata_rw_ctrl2___trf_mode___lsb 23 +#define reg_ata_rw_ctrl2___trf_mode___width 1 +#define reg_ata_rw_ctrl2___trf_mode___bit 23 +#define reg_ata_rw_ctrl2___rw___lsb 24 +#define reg_ata_rw_ctrl2___rw___width 1 +#define reg_ata_rw_ctrl2___rw___bit 24 +#define reg_ata_rw_ctrl2___addr___lsb 25 +#define reg_ata_rw_ctrl2___addr___width 3 +#define reg_ata_rw_ctrl2___cs0___lsb 28 +#define reg_ata_rw_ctrl2___cs0___width 1 +#define reg_ata_rw_ctrl2___cs0___bit 28 +#define reg_ata_rw_ctrl2___cs1___lsb 29 +#define reg_ata_rw_ctrl2___cs1___width 1 +#define reg_ata_rw_ctrl2___cs1___bit 29 +#define reg_ata_rw_ctrl2___sel___lsb 30 +#define reg_ata_rw_ctrl2___sel___width 2 +#define reg_ata_rw_ctrl2_offset 0 + +/* Register rs_stat_data, scope ata, type rs */ +#define reg_ata_rs_stat_data___data___lsb 0 +#define reg_ata_rs_stat_data___data___width 16 +#define reg_ata_rs_stat_data___dav___lsb 16 +#define reg_ata_rs_stat_data___dav___width 1 +#define reg_ata_rs_stat_data___dav___bit 16 +#define reg_ata_rs_stat_data___busy___lsb 17 +#define reg_ata_rs_stat_data___busy___width 1 +#define reg_ata_rs_stat_data___busy___bit 17 +#define reg_ata_rs_stat_data_offset 4 + +/* Register r_stat_data, scope ata, type r */ +#define reg_ata_r_stat_data___data___lsb 0 +#define reg_ata_r_stat_data___data___width 16 +#define reg_ata_r_stat_data___dav___lsb 16 +#define reg_ata_r_stat_data___dav___width 1 +#define reg_ata_r_stat_data___dav___bit 16 +#define reg_ata_r_stat_data___busy___lsb 17 +#define reg_ata_r_stat_data___busy___width 1 +#define reg_ata_r_stat_data___busy___bit 17 +#define reg_ata_r_stat_data_offset 8 + +/* Register rw_trf_cnt, scope ata, type rw */ +#define reg_ata_rw_trf_cnt___cnt___lsb 0 +#define reg_ata_rw_trf_cnt___cnt___width 17 +#define reg_ata_rw_trf_cnt_offset 20 + +/* Register r_stat_misc, scope ata, type r */ +#define reg_ata_r_stat_misc___crc___lsb 0 +#define reg_ata_r_stat_misc___crc___width 16 +#define reg_ata_r_stat_misc_offset 24 + +/* Register rw_intr_mask, scope ata, type rw */ +#define reg_ata_rw_intr_mask___bus0___lsb 0 +#define reg_ata_rw_intr_mask___bus0___width 1 +#define reg_ata_rw_intr_mask___bus0___bit 0 +#define reg_ata_rw_intr_mask___bus1___lsb 1 +#define reg_ata_rw_intr_mask___bus1___width 1 +#define reg_ata_rw_intr_mask___bus1___bit 1 +#define reg_ata_rw_intr_mask___bus2___lsb 2 +#define reg_ata_rw_intr_mask___bus2___width 1 +#define reg_ata_rw_intr_mask___bus2___bit 2 +#define reg_ata_rw_intr_mask___bus3___lsb 3 +#define reg_ata_rw_intr_mask___bus3___width 1 +#define reg_ata_rw_intr_mask___bus3___bit 3 +#define reg_ata_rw_intr_mask_offset 28 + +/* Register rw_ack_intr, scope ata, type rw */ +#define reg_ata_rw_ack_intr___bus0___lsb 0 +#define reg_ata_rw_ack_intr___bus0___width 1 +#define reg_ata_rw_ack_intr___bus0___bit 0 +#define reg_ata_rw_ack_intr___bus1___lsb 1 +#define reg_ata_rw_ack_intr___bus1___width 1 +#define reg_ata_rw_ack_intr___bus1___bit 1 +#define reg_ata_rw_ack_intr___bus2___lsb 2 +#define reg_ata_rw_ack_intr___bus2___width 1 +#define reg_ata_rw_ack_intr___bus2___bit 2 +#define reg_ata_rw_ack_intr___bus3___lsb 3 +#define reg_ata_rw_ack_intr___bus3___width 1 +#define reg_ata_rw_ack_intr___bus3___bit 3 +#define reg_ata_rw_ack_intr_offset 32 + +/* Register r_intr, scope ata, type r */ +#define reg_ata_r_intr___bus0___lsb 0 +#define reg_ata_r_intr___bus0___width 1 +#define reg_ata_r_intr___bus0___bit 0 +#define reg_ata_r_intr___bus1___lsb 1 +#define reg_ata_r_intr___bus1___width 1 +#define reg_ata_r_intr___bus1___bit 1 +#define reg_ata_r_intr___bus2___lsb 2 +#define reg_ata_r_intr___bus2___width 1 +#define reg_ata_r_intr___bus2___bit 2 +#define reg_ata_r_intr___bus3___lsb 3 +#define reg_ata_r_intr___bus3___width 1 +#define reg_ata_r_intr___bus3___bit 3 +#define reg_ata_r_intr_offset 36 + +/* Register r_masked_intr, scope ata, type r */ +#define reg_ata_r_masked_intr___bus0___lsb 0 +#define reg_ata_r_masked_intr___bus0___width 1 +#define reg_ata_r_masked_intr___bus0___bit 0 +#define reg_ata_r_masked_intr___bus1___lsb 1 +#define reg_ata_r_masked_intr___bus1___width 1 +#define reg_ata_r_masked_intr___bus1___bit 1 +#define reg_ata_r_masked_intr___bus2___lsb 2 +#define reg_ata_r_masked_intr___bus2___width 1 +#define reg_ata_r_masked_intr___bus2___bit 2 +#define reg_ata_r_masked_intr___bus3___lsb 3 +#define reg_ata_r_masked_intr___bus3___width 1 +#define reg_ata_r_masked_intr___bus3___bit 3 +#define reg_ata_r_masked_intr_offset 40 + + +/* Constants */ +#define regk_ata_active 0x00000001 +#define regk_ata_byte 0x00000001 +#define regk_ata_data 0x00000001 +#define regk_ata_dma 0x00000001 +#define regk_ata_inactive 0x00000000 +#define regk_ata_no 0x00000000 +#define regk_ata_nodata 0x00000000 +#define regk_ata_pio 0x00000000 +#define regk_ata_rd 0x00000001 +#define regk_ata_reg 0x00000000 +#define regk_ata_rw_ctrl0_default 0x00000000 +#define regk_ata_rw_ctrl2_default 0x00000000 +#define regk_ata_rw_intr_mask_default 0x00000000 +#define regk_ata_udma 0x00000002 +#define regk_ata_word 0x00000000 +#define regk_ata_wr 0x00000000 +#define regk_ata_yes 0x00000001 +#endif /* __ata_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 000000000000..c686cb335621 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h @@ -0,0 +1,319 @@ +#ifndef __bif_core_defs_asm_h +#define __bif_core_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp1_cfg___lw___width 6 +#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp1_cfg___ew___width 3 +#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp1_cfg___zw___width 3 +#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp1_cfg___aw___width 2 +#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp1_cfg___dw___width 2 +#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp1_cfg___ewb___width 2 +#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp1_cfg___bw___width 1 +#define reg_bif_core_rw_grp1_cfg___bw___bit 18 +#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp1_cfg___mode___width 1 +#define reg_bif_core_rw_grp1_cfg___mode___bit 21 +#define reg_bif_core_rw_grp1_cfg_offset 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp2_cfg___lw___width 6 +#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp2_cfg___ew___width 3 +#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp2_cfg___zw___width 3 +#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp2_cfg___aw___width 2 +#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp2_cfg___dw___width 2 +#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp2_cfg___ewb___width 2 +#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp2_cfg___bw___width 1 +#define reg_bif_core_rw_grp2_cfg___bw___bit 18 +#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp2_cfg___mode___width 1 +#define reg_bif_core_rw_grp2_cfg___mode___bit 21 +#define reg_bif_core_rw_grp2_cfg_offset 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp3_cfg___lw___width 6 +#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp3_cfg___ew___width 3 +#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp3_cfg___zw___width 3 +#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp3_cfg___aw___width 2 +#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp3_cfg___dw___width 2 +#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp3_cfg___ewb___width 2 +#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp3_cfg___bw___width 1 +#define reg_bif_core_rw_grp3_cfg___bw___bit 18 +#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp3_cfg___mode___width 1 +#define reg_bif_core_rw_grp3_cfg___mode___bit 21 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 +#define reg_bif_core_rw_grp3_cfg_offset 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp4_cfg___lw___width 6 +#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp4_cfg___ew___width 3 +#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp4_cfg___zw___width 3 +#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp4_cfg___aw___width 2 +#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp4_cfg___dw___width 2 +#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp4_cfg___ewb___width 2 +#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp4_cfg___bw___width 1 +#define reg_bif_core_rw_grp4_cfg___bw___bit 18 +#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp4_cfg___mode___width 1 +#define reg_bif_core_rw_grp4_cfg___mode___bit 21 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 +#define reg_bif_core_rw_grp4_cfg_offset 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_timing___cl___lsb 0 +#define reg_bif_core_rw_sdram_timing___cl___width 3 +#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 +#define reg_bif_core_rw_sdram_timing___rcd___width 3 +#define reg_bif_core_rw_sdram_timing___rp___lsb 6 +#define reg_bif_core_rw_sdram_timing___rp___width 3 +#define reg_bif_core_rw_sdram_timing___rc___lsb 9 +#define reg_bif_core_rw_sdram_timing___rc___width 2 +#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 +#define reg_bif_core_rw_sdram_timing___dpl___width 2 +#define reg_bif_core_rw_sdram_timing___pde___lsb 13 +#define reg_bif_core_rw_sdram_timing___pde___width 1 +#define reg_bif_core_rw_sdram_timing___pde___bit 13 +#define reg_bif_core_rw_sdram_timing___ref___lsb 14 +#define reg_bif_core_rw_sdram_timing___ref___width 2 +#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 +#define reg_bif_core_rw_sdram_timing___cpd___width 1 +#define reg_bif_core_rw_sdram_timing___cpd___bit 16 +#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 +#define reg_bif_core_rw_sdram_timing___sdcke___width 1 +#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 +#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 +#define reg_bif_core_rw_sdram_timing___sdclk___width 1 +#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 +#define reg_bif_core_rw_sdram_timing_offset 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 +#define reg_bif_core_rw_sdram_cmd___cmd___width 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 +#define reg_bif_core_rw_sdram_cmd_offset 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 +#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_rs_sdram_ref_stat_offset 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_r_sdram_ref_stat___ok___width 1 +#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_r_sdram_ref_stat_offset 36 + + +/* Constants */ +#define regk_bif_core_bank2 0x00000000 +#define regk_bif_core_bank4 0x00000001 +#define regk_bif_core_bit10 0x0000000a +#define regk_bif_core_bit11 0x0000000b +#define regk_bif_core_bit12 0x0000000c +#define regk_bif_core_bit13 0x0000000d +#define regk_bif_core_bit14 0x0000000e +#define regk_bif_core_bit15 0x0000000f +#define regk_bif_core_bit16 0x00000010 +#define regk_bif_core_bit17 0x00000011 +#define regk_bif_core_bit18 0x00000012 +#define regk_bif_core_bit19 0x00000013 +#define regk_bif_core_bit20 0x00000014 +#define regk_bif_core_bit21 0x00000015 +#define regk_bif_core_bit22 0x00000016 +#define regk_bif_core_bit23 0x00000017 +#define regk_bif_core_bit24 0x00000018 +#define regk_bif_core_bit25 0x00000019 +#define regk_bif_core_bit26 0x0000001a +#define regk_bif_core_bit27 0x0000001b +#define regk_bif_core_bit28 0x0000001c +#define regk_bif_core_bit29 0x0000001d +#define regk_bif_core_bit9 0x00000009 +#define regk_bif_core_bw16 0x00000001 +#define regk_bif_core_bw32 0x00000000 +#define regk_bif_core_bwe 0x00000000 +#define regk_bif_core_cwe 0x00000001 +#define regk_bif_core_e15us 0x00000001 +#define regk_bif_core_e7800ns 0x00000002 +#define regk_bif_core_grp0 0x00000000 +#define regk_bif_core_grp1 0x00000001 +#define regk_bif_core_mrs 0x00000003 +#define regk_bif_core_no 0x00000000 +#define regk_bif_core_none 0x00000000 +#define regk_bif_core_nop 0x00000000 +#define regk_bif_core_off 0x00000000 +#define regk_bif_core_pre 0x00000002 +#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rd 0x00000002 +#define regk_bif_core_ref 0x00000001 +#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rw_grp1_cfg_default 0x000006cf +#define regk_bif_core_rw_grp2_cfg_default 0x000006cf +#define regk_bif_core_rw_grp3_cfg_default 0x000006cf +#define regk_bif_core_rw_grp4_cfg_default 0x000006cf +#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 +#define regk_bif_core_slf 0x00000004 +#define regk_bif_core_wr 0x00000001 +#define regk_bif_core_yes 0x00000001 +#endif /* __bif_core_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h new file mode 100644 index 000000000000..71532aa18168 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h @@ -0,0 +1,495 @@ +#ifndef __bif_dma_defs_asm_h +#define __bif_dma_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 +#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 +#define reg_bif_dma_rw_ch0_ctrl_offset 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch0_addr___addr___width 32 +#define reg_bif_dma_rw_ch0_addr_offset 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_start___run___lsb 0 +#define reg_bif_dma_rw_ch0_start___run___width 1 +#define reg_bif_dma_rw_ch0_start___run___bit 0 +#define reg_bif_dma_rw_ch0_start_offset 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch0_cnt_offset 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch0_stat___cnt___width 16 +#define reg_bif_dma_r_ch0_stat___run___lsb 31 +#define reg_bif_dma_r_ch0_stat___run___width 1 +#define reg_bif_dma_r_ch0_stat___run___bit 31 +#define reg_bif_dma_r_ch0_stat_offset 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 +#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch1_ctrl_offset 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch1_addr___addr___width 32 +#define reg_bif_dma_rw_ch1_addr_offset 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_start___run___lsb 0 +#define reg_bif_dma_rw_ch1_start___run___width 1 +#define reg_bif_dma_rw_ch1_start___run___bit 0 +#define reg_bif_dma_rw_ch1_start_offset 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch1_cnt_offset 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch1_stat___cnt___width 16 +#define reg_bif_dma_r_ch1_stat___run___lsb 31 +#define reg_bif_dma_r_ch1_stat___run___width 1 +#define reg_bif_dma_r_ch1_stat___run___bit 31 +#define reg_bif_dma_r_ch1_stat_offset 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 +#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 +#define reg_bif_dma_rw_ch2_ctrl_offset 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch2_addr___addr___width 32 +#define reg_bif_dma_rw_ch2_addr_offset 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_start___run___lsb 0 +#define reg_bif_dma_rw_ch2_start___run___width 1 +#define reg_bif_dma_rw_ch2_start___run___bit 0 +#define reg_bif_dma_rw_ch2_start_offset 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch2_cnt_offset 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch2_stat___cnt___width 16 +#define reg_bif_dma_r_ch2_stat___run___lsb 31 +#define reg_bif_dma_r_ch2_stat___run___width 1 +#define reg_bif_dma_r_ch2_stat___run___bit 31 +#define reg_bif_dma_r_ch2_stat_offset 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 +#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch3_ctrl_offset 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch3_addr___addr___width 32 +#define reg_bif_dma_rw_ch3_addr_offset 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_start___run___lsb 0 +#define reg_bif_dma_rw_ch3_start___run___width 1 +#define reg_bif_dma_rw_ch3_start___run___bit 0 +#define reg_bif_dma_rw_ch3_start_offset 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch3_cnt_offset 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch3_stat___cnt___width 16 +#define reg_bif_dma_r_ch3_stat___run___lsb 31 +#define reg_bif_dma_r_ch3_stat___run___width 1 +#define reg_bif_dma_r_ch3_stat___run___bit 31 +#define reg_bif_dma_r_ch3_stat_offset 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 +#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 +#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 +#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 +#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 +#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 +#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 +#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 +#define reg_bif_dma_rw_intr_mask_offset 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 +#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 +#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 +#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 +#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 +#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 +#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 +#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 +#define reg_bif_dma_rw_ack_intr_offset 132 + +/* Register r_intr, scope bif_dma, type r */ +#define reg_bif_dma_r_intr___ext_dma0___lsb 0 +#define reg_bif_dma_r_intr___ext_dma0___width 1 +#define reg_bif_dma_r_intr___ext_dma0___bit 0 +#define reg_bif_dma_r_intr___ext_dma1___lsb 1 +#define reg_bif_dma_r_intr___ext_dma1___width 1 +#define reg_bif_dma_r_intr___ext_dma1___bit 1 +#define reg_bif_dma_r_intr___ext_dma2___lsb 2 +#define reg_bif_dma_r_intr___ext_dma2___width 1 +#define reg_bif_dma_r_intr___ext_dma2___bit 2 +#define reg_bif_dma_r_intr___ext_dma3___lsb 3 +#define reg_bif_dma_r_intr___ext_dma3___width 1 +#define reg_bif_dma_r_intr___ext_dma3___bit 3 +#define reg_bif_dma_r_intr_offset 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 +#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 +#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 +#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 +#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 +#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 +#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 +#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 +#define reg_bif_dma_r_masked_intr_offset 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin0_cfg_offset 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin1_cfg_offset 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin2_cfg_offset 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin3_cfg_offset 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin4_cfg_offset 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin5_cfg_offset 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin6_cfg_offset 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin7_cfg_offset 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_pin_stat___pin0___lsb 0 +#define reg_bif_dma_r_pin_stat___pin0___width 1 +#define reg_bif_dma_r_pin_stat___pin0___bit 0 +#define reg_bif_dma_r_pin_stat___pin1___lsb 1 +#define reg_bif_dma_r_pin_stat___pin1___width 1 +#define reg_bif_dma_r_pin_stat___pin1___bit 1 +#define reg_bif_dma_r_pin_stat___pin2___lsb 2 +#define reg_bif_dma_r_pin_stat___pin2___width 1 +#define reg_bif_dma_r_pin_stat___pin2___bit 2 +#define reg_bif_dma_r_pin_stat___pin3___lsb 3 +#define reg_bif_dma_r_pin_stat___pin3___width 1 +#define reg_bif_dma_r_pin_stat___pin3___bit 3 +#define reg_bif_dma_r_pin_stat___pin4___lsb 4 +#define reg_bif_dma_r_pin_stat___pin4___width 1 +#define reg_bif_dma_r_pin_stat___pin4___bit 4 +#define reg_bif_dma_r_pin_stat___pin5___lsb 5 +#define reg_bif_dma_r_pin_stat___pin5___width 1 +#define reg_bif_dma_r_pin_stat___pin5___bit 5 +#define reg_bif_dma_r_pin_stat___pin6___lsb 6 +#define reg_bif_dma_r_pin_stat___pin6___width 1 +#define reg_bif_dma_r_pin_stat___pin6___bit 6 +#define reg_bif_dma_r_pin_stat___pin7___lsb 7 +#define reg_bif_dma_r_pin_stat___pin7___width 1 +#define reg_bif_dma_r_pin_stat___pin7___bit 7 +#define reg_bif_dma_r_pin_stat_offset 192 + + +/* Constants */ +#define regk_bif_dma_as_master 0x00000001 +#define regk_bif_dma_as_slave 0x00000001 +#define regk_bif_dma_burst1 0x00000000 +#define regk_bif_dma_burst8 0x00000001 +#define regk_bif_dma_bw16 0x00000001 +#define regk_bif_dma_bw32 0x00000002 +#define regk_bif_dma_bw8 0x00000000 +#define regk_bif_dma_dack 0x00000006 +#define regk_bif_dma_dack_inv 0x00000007 +#define regk_bif_dma_force 0x00000001 +#define regk_bif_dma_hi 0x00000003 +#define regk_bif_dma_inv 0x00000003 +#define regk_bif_dma_lo 0x00000002 +#define regk_bif_dma_master 0x00000001 +#define regk_bif_dma_no 0x00000000 +#define regk_bif_dma_norm 0x00000002 +#define regk_bif_dma_off 0x00000000 +#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch0_start_default 0x00000000 +#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch1_start_default 0x00000000 +#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch2_start_default 0x00000000 +#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch3_start_default 0x00000000 +#define regk_bif_dma_rw_intr_mask_default 0x00000000 +#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 +#define regk_bif_dma_slave 0x00000002 +#define regk_bif_dma_sreq 0x00000006 +#define regk_bif_dma_sreq_inv 0x00000007 +#define regk_bif_dma_tc 0x00000004 +#define regk_bif_dma_tc_inv 0x00000005 +#define regk_bif_dma_yes 0x00000001 +#endif /* __bif_dma_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h new file mode 100644 index 000000000000..031f33a365bb --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_asm_h +#define __bif_slave_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 +#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 +#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 +#define reg_bif_slave_rw_slave_cfg___loopback___width 1 +#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 +#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 +#define reg_bif_slave_rw_slave_cfg___dis___width 1 +#define reg_bif_slave_rw_slave_cfg___dis___bit 6 +#define reg_bif_slave_rw_slave_cfg_offset 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 +#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 +#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 +#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 +#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 +#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 +#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 +#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 +#define reg_bif_slave_r_slave_mode_offset 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch0_cfg_offset 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch1_cfg_offset 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch2_cfg_offset 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch3_cfg_offset 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 +#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 +#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 +#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 +#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 +#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 +#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 +#define reg_bif_slave_rw_arb_cfg___release___lsb 7 +#define reg_bif_slave_rw_arb_cfg___release___width 2 +#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 +#define reg_bif_slave_rw_arb_cfg___acquire___width 1 +#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 +#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 +#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 +#define reg_bif_slave_rw_arb_cfg_offset 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 +#define reg_bif_slave_r_arb_stat___init_mode___width 1 +#define reg_bif_slave_r_arb_stat___init_mode___bit 0 +#define reg_bif_slave_r_arb_stat___mode___lsb 1 +#define reg_bif_slave_r_arb_stat___mode___width 1 +#define reg_bif_slave_r_arb_stat___mode___bit 1 +#define reg_bif_slave_r_arb_stat___brin___lsb 2 +#define reg_bif_slave_r_arb_stat___brin___width 1 +#define reg_bif_slave_r_arb_stat___brin___bit 2 +#define reg_bif_slave_r_arb_stat___brout___lsb 3 +#define reg_bif_slave_r_arb_stat___brout___width 1 +#define reg_bif_slave_r_arb_stat___brout___bit 3 +#define reg_bif_slave_r_arb_stat___bg___lsb 4 +#define reg_bif_slave_r_arb_stat___bg___width 1 +#define reg_bif_slave_r_arb_stat___bg___bit 4 +#define reg_bif_slave_r_arb_stat_offset 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 +#define reg_bif_slave_rw_intr_mask___bus_release___width 1 +#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 +#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 +#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 +#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 +#define reg_bif_slave_rw_intr_mask_offset 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 +#define reg_bif_slave_rw_ack_intr___bus_release___width 1 +#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 +#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 +#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 +#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 +#define reg_bif_slave_rw_ack_intr_offset 68 + +/* Register r_intr, scope bif_slave, type r */ +#define reg_bif_slave_r_intr___bus_release___lsb 0 +#define reg_bif_slave_r_intr___bus_release___width 1 +#define reg_bif_slave_r_intr___bus_release___bit 0 +#define reg_bif_slave_r_intr___bus_acquire___lsb 1 +#define reg_bif_slave_r_intr___bus_acquire___width 1 +#define reg_bif_slave_r_intr___bus_acquire___bit 1 +#define reg_bif_slave_r_intr_offset 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 +#define reg_bif_slave_r_masked_intr___bus_release___width 1 +#define reg_bif_slave_r_masked_intr___bus_release___bit 0 +#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 +#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 +#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 +#define reg_bif_slave_r_masked_intr_offset 76 + + +/* Constants */ +#define regk_bif_slave_active_hi 0x00000003 +#define regk_bif_slave_active_lo 0x00000002 +#define regk_bif_slave_addr 0x00000000 +#define regk_bif_slave_always 0x00000001 +#define regk_bif_slave_at_idle 0x00000002 +#define regk_bif_slave_burst_end 0x00000003 +#define regk_bif_slave_dma 0x00000001 +#define regk_bif_slave_hi 0x00000003 +#define regk_bif_slave_inv 0x00000001 +#define regk_bif_slave_lo 0x00000002 +#define regk_bif_slave_local 0x00000001 +#define regk_bif_slave_master 0x00000000 +#define regk_bif_slave_mode_reg 0x00000001 +#define regk_bif_slave_no 0x00000000 +#define regk_bif_slave_norm 0x00000000 +#define regk_bif_slave_on_access 0x00000000 +#define regk_bif_slave_rw_arb_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 +#define regk_bif_slave_rw_intr_mask_default 0x00000000 +#define regk_bif_slave_rw_slave_cfg_default 0x00000000 +#define regk_bif_slave_shared 0x00000000 +#define regk_bif_slave_slave 0x00000001 +#define regk_bif_slave_t0ns 0x00000003 +#define regk_bif_slave_t10ns 0x00000002 +#define regk_bif_slave_t20ns 0x00000003 +#define regk_bif_slave_t30ns 0x00000002 +#define regk_bif_slave_t40ns 0x00000001 +#define regk_bif_slave_t50ns 0x00000000 +#define regk_bif_slave_yes 0x00000001 +#define regk_bif_slave_z 0x00000004 +#endif /* __bif_slave_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h new file mode 100644 index 000000000000..e98476332e1f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h @@ -0,0 +1,131 @@ +#ifndef __config_defs_asm_h +#define __config_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r + * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope config, type r */ +#define reg_config_r_bootsel___boot_mode___lsb 0 +#define reg_config_r_bootsel___boot_mode___width 3 +#define reg_config_r_bootsel___full_duplex___lsb 3 +#define reg_config_r_bootsel___full_duplex___width 1 +#define reg_config_r_bootsel___full_duplex___bit 3 +#define reg_config_r_bootsel___user___lsb 4 +#define reg_config_r_bootsel___user___width 1 +#define reg_config_r_bootsel___user___bit 4 +#define reg_config_r_bootsel___pll___lsb 5 +#define reg_config_r_bootsel___pll___width 1 +#define reg_config_r_bootsel___pll___bit 5 +#define reg_config_r_bootsel___flash_bw___lsb 6 +#define reg_config_r_bootsel___flash_bw___width 1 +#define reg_config_r_bootsel___flash_bw___bit 6 +#define reg_config_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +#define reg_config_rw_clk_ctrl___pll___lsb 0 +#define reg_config_rw_clk_ctrl___pll___width 1 +#define reg_config_rw_clk_ctrl___pll___bit 0 +#define reg_config_rw_clk_ctrl___cpu___lsb 1 +#define reg_config_rw_clk_ctrl___cpu___width 1 +#define reg_config_rw_clk_ctrl___cpu___bit 1 +#define reg_config_rw_clk_ctrl___iop___lsb 2 +#define reg_config_rw_clk_ctrl___iop___width 1 +#define reg_config_rw_clk_ctrl___iop___bit 2 +#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 +#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 +#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 +#define reg_config_rw_clk_ctrl___dma23___lsb 4 +#define reg_config_rw_clk_ctrl___dma23___width 1 +#define reg_config_rw_clk_ctrl___dma23___bit 4 +#define reg_config_rw_clk_ctrl___dma45___lsb 5 +#define reg_config_rw_clk_ctrl___dma45___width 1 +#define reg_config_rw_clk_ctrl___dma45___bit 5 +#define reg_config_rw_clk_ctrl___dma67___lsb 6 +#define reg_config_rw_clk_ctrl___dma67___width 1 +#define reg_config_rw_clk_ctrl___dma67___bit 6 +#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 +#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 +#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 +#define reg_config_rw_clk_ctrl___bif___lsb 8 +#define reg_config_rw_clk_ctrl___bif___width 1 +#define reg_config_rw_clk_ctrl___bif___bit 8 +#define reg_config_rw_clk_ctrl___fix_io___lsb 9 +#define reg_config_rw_clk_ctrl___fix_io___width 1 +#define reg_config_rw_clk_ctrl___fix_io___bit 9 +#define reg_config_rw_clk_ctrl_offset 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 +#define reg_config_rw_pad_ctrl___usb_susp___width 1 +#define reg_config_rw_pad_ctrl___usb_susp___bit 0 +#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 +#define reg_config_rw_pad_ctrl___phyrst_n___width 1 +#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 +#define reg_config_rw_pad_ctrl_offset 8 + + +/* Constants */ +#define regk_config_bw16 0x00000000 +#define regk_config_bw32 0x00000001 +#define regk_config_master 0x00000005 +#define regk_config_nand 0x00000003 +#define regk_config_net_rx 0x00000001 +#define regk_config_net_tx_rx 0x00000002 +#define regk_config_no 0x00000000 +#define regk_config_none 0x00000007 +#define regk_config_nor 0x00000000 +#define regk_config_rw_clk_ctrl_default 0x00000002 +#define regk_config_rw_pad_ctrl_default 0x00000000 +#define regk_config_ser 0x00000004 +#define regk_config_slave 0x00000006 +#define regk_config_yes 0x00000001 +#endif /* __config_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h new file mode 100644 index 000000000000..8370aee8a14a --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/crisp/doc/cpu_vect.r +version . */ + +#ifndef _______INST_CRISP_DOC_CPU_VECT_R +#define _______INST_CRISP_DOC_CPU_VECT_R +#define NMI_INTR_VECT 0x00 +#define RESERVED_1_INTR_VECT 0x01 +#define RESERVED_2_INTR_VECT 0x02 +#define SINGLE_STEP_INTR_VECT 0x03 +#define INSTR_TLB_REFILL_INTR_VECT 0x04 +#define INSTR_TLB_INV_INTR_VECT 0x05 +#define INSTR_TLB_ACC_INTR_VECT 0x06 +#define TLB_EX_INTR_VECT 0x07 +#define DATA_TLB_REFILL_INTR_VECT 0x08 +#define DATA_TLB_INV_INTR_VECT 0x09 +#define DATA_TLB_ACC_INTR_VECT 0x0a +#define DATA_TLB_WE_INTR_VECT 0x0b +#define HW_BP_INTR_VECT 0x0c +#define RESERVED_D_INTR_VECT 0x0d +#define RESERVED_E_INTR_VECT 0x0e +#define RESERVED_F_INTR_VECT 0x0f +#define BREAK_0_INTR_VECT 0x10 +#define BREAK_1_INTR_VECT 0x11 +#define BREAK_2_INTR_VECT 0x12 +#define BREAK_3_INTR_VECT 0x13 +#define BREAK_4_INTR_VECT 0x14 +#define BREAK_5_INTR_VECT 0x15 +#define BREAK_6_INTR_VECT 0x16 +#define BREAK_7_INTR_VECT 0x17 +#define BREAK_8_INTR_VECT 0x18 +#define BREAK_9_INTR_VECT 0x19 +#define BREAK_10_INTR_VECT 0x1a +#define BREAK_11_INTR_VECT 0x1b +#define BREAK_12_INTR_VECT 0x1c +#define BREAK_13_INTR_VECT 0x1d +#define BREAK_14_INTR_VECT 0x1e +#define BREAK_15_INTR_VECT 0x1f +#define MULTIPLE_INTR_VECT 0x30 + +#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h new file mode 100644 index 000000000000..7f768db272e2 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h @@ -0,0 +1,114 @@ +#ifndef __cris_defs_asm_h +#define __cris_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/crisp/doc/cris.r + * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp + * last modfied: Mon Apr 11 16:06:39 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r + * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gc_cfg, scope cris, type rw */ +#define reg_cris_rw_gc_cfg___ic___lsb 0 +#define reg_cris_rw_gc_cfg___ic___width 1 +#define reg_cris_rw_gc_cfg___ic___bit 0 +#define reg_cris_rw_gc_cfg___dc___lsb 1 +#define reg_cris_rw_gc_cfg___dc___width 1 +#define reg_cris_rw_gc_cfg___dc___bit 1 +#define reg_cris_rw_gc_cfg___im___lsb 2 +#define reg_cris_rw_gc_cfg___im___width 1 +#define reg_cris_rw_gc_cfg___im___bit 2 +#define reg_cris_rw_gc_cfg___dm___lsb 3 +#define reg_cris_rw_gc_cfg___dm___width 1 +#define reg_cris_rw_gc_cfg___dm___bit 3 +#define reg_cris_rw_gc_cfg___gb___lsb 4 +#define reg_cris_rw_gc_cfg___gb___width 1 +#define reg_cris_rw_gc_cfg___gb___bit 4 +#define reg_cris_rw_gc_cfg___gk___lsb 5 +#define reg_cris_rw_gc_cfg___gk___width 1 +#define reg_cris_rw_gc_cfg___gk___bit 5 +#define reg_cris_rw_gc_cfg___gp___lsb 6 +#define reg_cris_rw_gc_cfg___gp___width 1 +#define reg_cris_rw_gc_cfg___gp___bit 6 +#define reg_cris_rw_gc_cfg_offset 0 + +/* Register rw_gc_ccs, scope cris, type rw */ +#define reg_cris_rw_gc_ccs_offset 4 + +/* Register rw_gc_srs, scope cris, type rw */ +#define reg_cris_rw_gc_srs___srs___lsb 0 +#define reg_cris_rw_gc_srs___srs___width 8 +#define reg_cris_rw_gc_srs_offset 8 + +/* Register rw_gc_nrp, scope cris, type rw */ +#define reg_cris_rw_gc_nrp_offset 12 + +/* Register rw_gc_exs, scope cris, type rw */ +#define reg_cris_rw_gc_exs_offset 16 + +/* Register rw_gc_eda, scope cris, type rw */ +#define reg_cris_rw_gc_eda_offset 20 + +/* Register rw_gc_r0, scope cris, type rw */ +#define reg_cris_rw_gc_r0_offset 32 + +/* Register rw_gc_r1, scope cris, type rw */ +#define reg_cris_rw_gc_r1_offset 36 + +/* Register rw_gc_r2, scope cris, type rw */ +#define reg_cris_rw_gc_r2_offset 40 + +/* Register rw_gc_r3, scope cris, type rw */ +#define reg_cris_rw_gc_r3_offset 44 + + +/* Constants */ +#define regk_cris_no 0x00000000 +#define regk_cris_rw_gc_cfg_default 0x00000000 +#define regk_cris_yes 0x00000001 +#endif /* __cris_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h new file mode 100644 index 000000000000..7d3689a6f80d --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h @@ -0,0 +1,10 @@ +#define RW_GC_CFG 0 +#define RW_GC_CCS 1 +#define RW_GC_SRS 2 +#define RW_GC_NRP 3 +#define RW_GC_EXS 4 +#define RW_GC_EDA 5 +#define RW_GC_R0 8 +#define RW_GC_R1 9 +#define RW_GC_R2 10 +#define RW_GC_R3 11 diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h new file mode 100644 index 000000000000..0cb71bc127ae --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h @@ -0,0 +1,368 @@ +#ifndef __dma_defs_asm_h +#define __dma_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp + * last modfied: Mon Apr 11 16:06:51 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_data, scope dma, type rw */ +#define reg_dma_rw_data_offset 0 + +/* Register rw_data_next, scope dma, type rw */ +#define reg_dma_rw_data_next_offset 4 + +/* Register rw_data_buf, scope dma, type rw */ +#define reg_dma_rw_data_buf_offset 8 + +/* Register rw_data_ctrl, scope dma, type rw */ +#define reg_dma_rw_data_ctrl___eol___lsb 0 +#define reg_dma_rw_data_ctrl___eol___width 1 +#define reg_dma_rw_data_ctrl___eol___bit 0 +#define reg_dma_rw_data_ctrl___out_eop___lsb 3 +#define reg_dma_rw_data_ctrl___out_eop___width 1 +#define reg_dma_rw_data_ctrl___out_eop___bit 3 +#define reg_dma_rw_data_ctrl___intr___lsb 4 +#define reg_dma_rw_data_ctrl___intr___width 1 +#define reg_dma_rw_data_ctrl___intr___bit 4 +#define reg_dma_rw_data_ctrl___wait___lsb 5 +#define reg_dma_rw_data_ctrl___wait___width 1 +#define reg_dma_rw_data_ctrl___wait___bit 5 +#define reg_dma_rw_data_ctrl_offset 12 + +/* Register rw_data_stat, scope dma, type rw */ +#define reg_dma_rw_data_stat___in_eop___lsb 3 +#define reg_dma_rw_data_stat___in_eop___width 1 +#define reg_dma_rw_data_stat___in_eop___bit 3 +#define reg_dma_rw_data_stat_offset 16 + +/* Register rw_data_md, scope dma, type rw */ +#define reg_dma_rw_data_md___md___lsb 0 +#define reg_dma_rw_data_md___md___width 16 +#define reg_dma_rw_data_md_offset 20 + +/* Register rw_data_md_s, scope dma, type rw */ +#define reg_dma_rw_data_md_s___md_s___lsb 0 +#define reg_dma_rw_data_md_s___md_s___width 16 +#define reg_dma_rw_data_md_s_offset 24 + +/* Register rw_data_after, scope dma, type rw */ +#define reg_dma_rw_data_after_offset 28 + +/* Register rw_ctxt, scope dma, type rw */ +#define reg_dma_rw_ctxt_offset 32 + +/* Register rw_ctxt_next, scope dma, type rw */ +#define reg_dma_rw_ctxt_next_offset 36 + +/* Register rw_ctxt_ctrl, scope dma, type rw */ +#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 +#define reg_dma_rw_ctxt_ctrl___eol___width 1 +#define reg_dma_rw_ctxt_ctrl___eol___bit 0 +#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 +#define reg_dma_rw_ctxt_ctrl___intr___width 1 +#define reg_dma_rw_ctxt_ctrl___intr___bit 4 +#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 +#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 +#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 +#define reg_dma_rw_ctxt_ctrl___en___lsb 7 +#define reg_dma_rw_ctxt_ctrl___en___width 1 +#define reg_dma_rw_ctxt_ctrl___en___bit 7 +#define reg_dma_rw_ctxt_ctrl_offset 40 + +/* Register rw_ctxt_stat, scope dma, type rw */ +#define reg_dma_rw_ctxt_stat___dis___lsb 7 +#define reg_dma_rw_ctxt_stat___dis___width 1 +#define reg_dma_rw_ctxt_stat___dis___bit 7 +#define reg_dma_rw_ctxt_stat_offset 44 + +/* Register rw_ctxt_md0, scope dma, type rw */ +#define reg_dma_rw_ctxt_md0___md0___lsb 0 +#define reg_dma_rw_ctxt_md0___md0___width 16 +#define reg_dma_rw_ctxt_md0_offset 48 + +/* Register rw_ctxt_md0_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 +#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 +#define reg_dma_rw_ctxt_md0_s_offset 52 + +/* Register rw_ctxt_md1, scope dma, type rw */ +#define reg_dma_rw_ctxt_md1_offset 56 + +/* Register rw_ctxt_md1_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md1_s_offset 60 + +/* Register rw_ctxt_md2, scope dma, type rw */ +#define reg_dma_rw_ctxt_md2_offset 64 + +/* Register rw_ctxt_md2_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md2_s_offset 68 + +/* Register rw_ctxt_md3, scope dma, type rw */ +#define reg_dma_rw_ctxt_md3_offset 72 + +/* Register rw_ctxt_md3_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md3_s_offset 76 + +/* Register rw_ctxt_md4, scope dma, type rw */ +#define reg_dma_rw_ctxt_md4_offset 80 + +/* Register rw_ctxt_md4_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md4_s_offset 84 + +/* Register rw_saved_data, scope dma, type rw */ +#define reg_dma_rw_saved_data_offset 88 + +/* Register rw_saved_data_buf, scope dma, type rw */ +#define reg_dma_rw_saved_data_buf_offset 92 + +/* Register rw_group, scope dma, type rw */ +#define reg_dma_rw_group_offset 96 + +/* Register rw_group_next, scope dma, type rw */ +#define reg_dma_rw_group_next_offset 100 + +/* Register rw_group_ctrl, scope dma, type rw */ +#define reg_dma_rw_group_ctrl___eol___lsb 0 +#define reg_dma_rw_group_ctrl___eol___width 1 +#define reg_dma_rw_group_ctrl___eol___bit 0 +#define reg_dma_rw_group_ctrl___tol___lsb 1 +#define reg_dma_rw_group_ctrl___tol___width 1 +#define reg_dma_rw_group_ctrl___tol___bit 1 +#define reg_dma_rw_group_ctrl___bol___lsb 2 +#define reg_dma_rw_group_ctrl___bol___width 1 +#define reg_dma_rw_group_ctrl___bol___bit 2 +#define reg_dma_rw_group_ctrl___intr___lsb 4 +#define reg_dma_rw_group_ctrl___intr___width 1 +#define reg_dma_rw_group_ctrl___intr___bit 4 +#define reg_dma_rw_group_ctrl___en___lsb 7 +#define reg_dma_rw_group_ctrl___en___width 1 +#define reg_dma_rw_group_ctrl___en___bit 7 +#define reg_dma_rw_group_ctrl_offset 104 + +/* Register rw_group_stat, scope dma, type rw */ +#define reg_dma_rw_group_stat___dis___lsb 7 +#define reg_dma_rw_group_stat___dis___width 1 +#define reg_dma_rw_group_stat___dis___bit 7 +#define reg_dma_rw_group_stat_offset 108 + +/* Register rw_group_md, scope dma, type rw */ +#define reg_dma_rw_group_md___md___lsb 0 +#define reg_dma_rw_group_md___md___width 16 +#define reg_dma_rw_group_md_offset 112 + +/* Register rw_group_md_s, scope dma, type rw */ +#define reg_dma_rw_group_md_s___md_s___lsb 0 +#define reg_dma_rw_group_md_s___md_s___width 16 +#define reg_dma_rw_group_md_s_offset 116 + +/* Register rw_group_up, scope dma, type rw */ +#define reg_dma_rw_group_up_offset 120 + +/* Register rw_group_down, scope dma, type rw */ +#define reg_dma_rw_group_down_offset 124 + +/* Register rw_cmd, scope dma, type rw */ +#define reg_dma_rw_cmd___cont_data___lsb 0 +#define reg_dma_rw_cmd___cont_data___width 1 +#define reg_dma_rw_cmd___cont_data___bit 0 +#define reg_dma_rw_cmd_offset 128 + +/* Register rw_cfg, scope dma, type rw */ +#define reg_dma_rw_cfg___en___lsb 0 +#define reg_dma_rw_cfg___en___width 1 +#define reg_dma_rw_cfg___en___bit 0 +#define reg_dma_rw_cfg___stop___lsb 1 +#define reg_dma_rw_cfg___stop___width 1 +#define reg_dma_rw_cfg___stop___bit 1 +#define reg_dma_rw_cfg_offset 132 + +/* Register rw_stat, scope dma, type rw */ +#define reg_dma_rw_stat___mode___lsb 0 +#define reg_dma_rw_stat___mode___width 5 +#define reg_dma_rw_stat___list_state___lsb 5 +#define reg_dma_rw_stat___list_state___width 3 +#define reg_dma_rw_stat___stream_cmd_src___lsb 8 +#define reg_dma_rw_stat___stream_cmd_src___width 8 +#define reg_dma_rw_stat___buf___lsb 24 +#define reg_dma_rw_stat___buf___width 8 +#define reg_dma_rw_stat_offset 136 + +/* Register rw_intr_mask, scope dma, type rw */ +#define reg_dma_rw_intr_mask___group___lsb 0 +#define reg_dma_rw_intr_mask___group___width 1 +#define reg_dma_rw_intr_mask___group___bit 0 +#define reg_dma_rw_intr_mask___ctxt___lsb 1 +#define reg_dma_rw_intr_mask___ctxt___width 1 +#define reg_dma_rw_intr_mask___ctxt___bit 1 +#define reg_dma_rw_intr_mask___data___lsb 2 +#define reg_dma_rw_intr_mask___data___width 1 +#define reg_dma_rw_intr_mask___data___bit 2 +#define reg_dma_rw_intr_mask___in_eop___lsb 3 +#define reg_dma_rw_intr_mask___in_eop___width 1 +#define reg_dma_rw_intr_mask___in_eop___bit 3 +#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 +#define reg_dma_rw_intr_mask___stream_cmd___width 1 +#define reg_dma_rw_intr_mask___stream_cmd___bit 4 +#define reg_dma_rw_intr_mask_offset 140 + +/* Register rw_ack_intr, scope dma, type rw */ +#define reg_dma_rw_ack_intr___group___lsb 0 +#define reg_dma_rw_ack_intr___group___width 1 +#define reg_dma_rw_ack_intr___group___bit 0 +#define reg_dma_rw_ack_intr___ctxt___lsb 1 +#define reg_dma_rw_ack_intr___ctxt___width 1 +#define reg_dma_rw_ack_intr___ctxt___bit 1 +#define reg_dma_rw_ack_intr___data___lsb 2 +#define reg_dma_rw_ack_intr___data___width 1 +#define reg_dma_rw_ack_intr___data___bit 2 +#define reg_dma_rw_ack_intr___in_eop___lsb 3 +#define reg_dma_rw_ack_intr___in_eop___width 1 +#define reg_dma_rw_ack_intr___in_eop___bit 3 +#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 +#define reg_dma_rw_ack_intr___stream_cmd___width 1 +#define reg_dma_rw_ack_intr___stream_cmd___bit 4 +#define reg_dma_rw_ack_intr_offset 144 + +/* Register r_intr, scope dma, type r */ +#define reg_dma_r_intr___group___lsb 0 +#define reg_dma_r_intr___group___width 1 +#define reg_dma_r_intr___group___bit 0 +#define reg_dma_r_intr___ctxt___lsb 1 +#define reg_dma_r_intr___ctxt___width 1 +#define reg_dma_r_intr___ctxt___bit 1 +#define reg_dma_r_intr___data___lsb 2 +#define reg_dma_r_intr___data___width 1 +#define reg_dma_r_intr___data___bit 2 +#define reg_dma_r_intr___in_eop___lsb 3 +#define reg_dma_r_intr___in_eop___width 1 +#define reg_dma_r_intr___in_eop___bit 3 +#define reg_dma_r_intr___stream_cmd___lsb 4 +#define reg_dma_r_intr___stream_cmd___width 1 +#define reg_dma_r_intr___stream_cmd___bit 4 +#define reg_dma_r_intr_offset 148 + +/* Register r_masked_intr, scope dma, type r */ +#define reg_dma_r_masked_intr___group___lsb 0 +#define reg_dma_r_masked_intr___group___width 1 +#define reg_dma_r_masked_intr___group___bit 0 +#define reg_dma_r_masked_intr___ctxt___lsb 1 +#define reg_dma_r_masked_intr___ctxt___width 1 +#define reg_dma_r_masked_intr___ctxt___bit 1 +#define reg_dma_r_masked_intr___data___lsb 2 +#define reg_dma_r_masked_intr___data___width 1 +#define reg_dma_r_masked_intr___data___bit 2 +#define reg_dma_r_masked_intr___in_eop___lsb 3 +#define reg_dma_r_masked_intr___in_eop___width 1 +#define reg_dma_r_masked_intr___in_eop___bit 3 +#define reg_dma_r_masked_intr___stream_cmd___lsb 4 +#define reg_dma_r_masked_intr___stream_cmd___width 1 +#define reg_dma_r_masked_intr___stream_cmd___bit 4 +#define reg_dma_r_masked_intr_offset 152 + +/* Register rw_stream_cmd, scope dma, type rw */ +#define reg_dma_rw_stream_cmd___cmd___lsb 0 +#define reg_dma_rw_stream_cmd___cmd___width 10 +#define reg_dma_rw_stream_cmd___n___lsb 16 +#define reg_dma_rw_stream_cmd___n___width 8 +#define reg_dma_rw_stream_cmd___busy___lsb 31 +#define reg_dma_rw_stream_cmd___busy___width 1 +#define reg_dma_rw_stream_cmd___busy___bit 31 +#define reg_dma_rw_stream_cmd_offset 156 + + +/* Constants */ +#define regk_dma_ack_pkt 0x00000100 +#define regk_dma_anytime 0x00000001 +#define regk_dma_array 0x00000008 +#define regk_dma_burst 0x00000020 +#define regk_dma_client 0x00000002 +#define regk_dma_copy_next 0x00000010 +#define regk_dma_copy_up 0x00000020 +#define regk_dma_data_at_eol 0x00000001 +#define regk_dma_dis_c 0x00000010 +#define regk_dma_dis_g 0x00000020 +#define regk_dma_idle 0x00000001 +#define regk_dma_intern 0x00000004 +#define regk_dma_load_c 0x00000200 +#define regk_dma_load_c_n 0x00000280 +#define regk_dma_load_c_next 0x00000240 +#define regk_dma_load_d 0x00000140 +#define regk_dma_load_g 0x00000300 +#define regk_dma_load_g_down 0x000003c0 +#define regk_dma_load_g_next 0x00000340 +#define regk_dma_load_g_up 0x00000380 +#define regk_dma_next_en 0x00000010 +#define regk_dma_next_pkt 0x00000010 +#define regk_dma_no 0x00000000 +#define regk_dma_only_at_wait 0x00000000 +#define regk_dma_restore 0x00000020 +#define regk_dma_rst 0x00000001 +#define regk_dma_running 0x00000004 +#define regk_dma_rw_cfg_default 0x00000000 +#define regk_dma_rw_cmd_default 0x00000000 +#define regk_dma_rw_intr_mask_default 0x00000000 +#define regk_dma_rw_stat_default 0x00000101 +#define regk_dma_rw_stream_cmd_default 0x00000000 +#define regk_dma_save_down 0x00000020 +#define regk_dma_save_up 0x00000020 +#define regk_dma_set_reg 0x00000050 +#define regk_dma_set_w_size1 0x00000190 +#define regk_dma_set_w_size2 0x000001a0 +#define regk_dma_set_w_size4 0x000001c0 +#define regk_dma_stopped 0x00000002 +#define regk_dma_store_c 0x00000002 +#define regk_dma_store_descr 0x00000000 +#define regk_dma_store_g 0x00000004 +#define regk_dma_store_md 0x00000001 +#define regk_dma_sw 0x00000008 +#define regk_dma_update_down 0x00000020 +#define regk_dma_yes 0x00000001 +#endif /* __dma_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h new file mode 100644 index 000000000000..c9f49864831b --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h @@ -0,0 +1,498 @@ +#ifndef __eth_defs_asm_h +#define __eth_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/eth/rtl/eth_regs.r + * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp + * last modfied: Mon Apr 11 16:07:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r + * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ma0_lo, scope eth, type rw */ +#define reg_eth_rw_ma0_lo___addr___lsb 0 +#define reg_eth_rw_ma0_lo___addr___width 32 +#define reg_eth_rw_ma0_lo_offset 0 + +/* Register rw_ma0_hi, scope eth, type rw */ +#define reg_eth_rw_ma0_hi___addr___lsb 0 +#define reg_eth_rw_ma0_hi___addr___width 16 +#define reg_eth_rw_ma0_hi_offset 4 + +/* Register rw_ma1_lo, scope eth, type rw */ +#define reg_eth_rw_ma1_lo___addr___lsb 0 +#define reg_eth_rw_ma1_lo___addr___width 32 +#define reg_eth_rw_ma1_lo_offset 8 + +/* Register rw_ma1_hi, scope eth, type rw */ +#define reg_eth_rw_ma1_hi___addr___lsb 0 +#define reg_eth_rw_ma1_hi___addr___width 16 +#define reg_eth_rw_ma1_hi_offset 12 + +/* Register rw_ga_lo, scope eth, type rw */ +#define reg_eth_rw_ga_lo___table___lsb 0 +#define reg_eth_rw_ga_lo___table___width 32 +#define reg_eth_rw_ga_lo_offset 16 + +/* Register rw_ga_hi, scope eth, type rw */ +#define reg_eth_rw_ga_hi___table___lsb 0 +#define reg_eth_rw_ga_hi___table___width 32 +#define reg_eth_rw_ga_hi_offset 20 + +/* Register rw_gen_ctrl, scope eth, type rw */ +#define reg_eth_rw_gen_ctrl___en___lsb 0 +#define reg_eth_rw_gen_ctrl___en___width 1 +#define reg_eth_rw_gen_ctrl___en___bit 0 +#define reg_eth_rw_gen_ctrl___phy___lsb 1 +#define reg_eth_rw_gen_ctrl___phy___width 2 +#define reg_eth_rw_gen_ctrl___protocol___lsb 3 +#define reg_eth_rw_gen_ctrl___protocol___width 1 +#define reg_eth_rw_gen_ctrl___protocol___bit 3 +#define reg_eth_rw_gen_ctrl___loopback___lsb 4 +#define reg_eth_rw_gen_ctrl___loopback___width 1 +#define reg_eth_rw_gen_ctrl___loopback___bit 4 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 +#define reg_eth_rw_gen_ctrl_offset 24 + +/* Register rw_rec_ctrl, scope eth, type rw */ +#define reg_eth_rw_rec_ctrl___ma0___lsb 0 +#define reg_eth_rw_rec_ctrl___ma0___width 1 +#define reg_eth_rw_rec_ctrl___ma0___bit 0 +#define reg_eth_rw_rec_ctrl___ma1___lsb 1 +#define reg_eth_rw_rec_ctrl___ma1___width 1 +#define reg_eth_rw_rec_ctrl___ma1___bit 1 +#define reg_eth_rw_rec_ctrl___individual___lsb 2 +#define reg_eth_rw_rec_ctrl___individual___width 1 +#define reg_eth_rw_rec_ctrl___individual___bit 2 +#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 +#define reg_eth_rw_rec_ctrl___broadcast___width 1 +#define reg_eth_rw_rec_ctrl___broadcast___bit 3 +#define reg_eth_rw_rec_ctrl___undersize___lsb 4 +#define reg_eth_rw_rec_ctrl___undersize___width 1 +#define reg_eth_rw_rec_ctrl___undersize___bit 4 +#define reg_eth_rw_rec_ctrl___oversize___lsb 5 +#define reg_eth_rw_rec_ctrl___oversize___width 1 +#define reg_eth_rw_rec_ctrl___oversize___bit 5 +#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 +#define reg_eth_rw_rec_ctrl___bad_crc___width 1 +#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 +#define reg_eth_rw_rec_ctrl___duplex___lsb 7 +#define reg_eth_rw_rec_ctrl___duplex___width 1 +#define reg_eth_rw_rec_ctrl___duplex___bit 7 +#define reg_eth_rw_rec_ctrl___max_size___lsb 8 +#define reg_eth_rw_rec_ctrl___max_size___width 1 +#define reg_eth_rw_rec_ctrl___max_size___bit 8 +#define reg_eth_rw_rec_ctrl_offset 28 + +/* Register rw_tr_ctrl, scope eth, type rw */ +#define reg_eth_rw_tr_ctrl___crc___lsb 0 +#define reg_eth_rw_tr_ctrl___crc___width 1 +#define reg_eth_rw_tr_ctrl___crc___bit 0 +#define reg_eth_rw_tr_ctrl___pad___lsb 1 +#define reg_eth_rw_tr_ctrl___pad___width 1 +#define reg_eth_rw_tr_ctrl___pad___bit 1 +#define reg_eth_rw_tr_ctrl___retry___lsb 2 +#define reg_eth_rw_tr_ctrl___retry___width 1 +#define reg_eth_rw_tr_ctrl___retry___bit 2 +#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 +#define reg_eth_rw_tr_ctrl___ignore_col___width 1 +#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 +#define reg_eth_rw_tr_ctrl___cancel___lsb 4 +#define reg_eth_rw_tr_ctrl___cancel___width 1 +#define reg_eth_rw_tr_ctrl___cancel___bit 4 +#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 +#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 +#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 +#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 +#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 +#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 +#define reg_eth_rw_tr_ctrl_offset 32 + +/* Register rw_clr_err, scope eth, type rw */ +#define reg_eth_rw_clr_err___clr___lsb 0 +#define reg_eth_rw_clr_err___clr___width 1 +#define reg_eth_rw_clr_err___clr___bit 0 +#define reg_eth_rw_clr_err_offset 36 + +/* Register rw_mgm_ctrl, scope eth, type rw */ +#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 +#define reg_eth_rw_mgm_ctrl___mdio___width 1 +#define reg_eth_rw_mgm_ctrl___mdio___bit 0 +#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 +#define reg_eth_rw_mgm_ctrl___mdoe___width 1 +#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 +#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 +#define reg_eth_rw_mgm_ctrl___mdc___width 1 +#define reg_eth_rw_mgm_ctrl___mdc___bit 2 +#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 +#define reg_eth_rw_mgm_ctrl___phyclk___width 1 +#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 +#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 +#define reg_eth_rw_mgm_ctrl___txdata___width 4 +#define reg_eth_rw_mgm_ctrl___txen___lsb 8 +#define reg_eth_rw_mgm_ctrl___txen___width 1 +#define reg_eth_rw_mgm_ctrl___txen___bit 8 +#define reg_eth_rw_mgm_ctrl_offset 40 + +/* Register r_stat, scope eth, type r */ +#define reg_eth_r_stat___mdio___lsb 0 +#define reg_eth_r_stat___mdio___width 1 +#define reg_eth_r_stat___mdio___bit 0 +#define reg_eth_r_stat___exc_col___lsb 1 +#define reg_eth_r_stat___exc_col___width 1 +#define reg_eth_r_stat___exc_col___bit 1 +#define reg_eth_r_stat___urun___lsb 2 +#define reg_eth_r_stat___urun___width 1 +#define reg_eth_r_stat___urun___bit 2 +#define reg_eth_r_stat___phyclk___lsb 3 +#define reg_eth_r_stat___phyclk___width 1 +#define reg_eth_r_stat___phyclk___bit 3 +#define reg_eth_r_stat___txdata___lsb 4 +#define reg_eth_r_stat___txdata___width 4 +#define reg_eth_r_stat___txen___lsb 8 +#define reg_eth_r_stat___txen___width 1 +#define reg_eth_r_stat___txen___bit 8 +#define reg_eth_r_stat___col___lsb 9 +#define reg_eth_r_stat___col___width 1 +#define reg_eth_r_stat___col___bit 9 +#define reg_eth_r_stat___crs___lsb 10 +#define reg_eth_r_stat___crs___width 1 +#define reg_eth_r_stat___crs___bit 10 +#define reg_eth_r_stat___txclk___lsb 11 +#define reg_eth_r_stat___txclk___width 1 +#define reg_eth_r_stat___txclk___bit 11 +#define reg_eth_r_stat___rxdata___lsb 12 +#define reg_eth_r_stat___rxdata___width 4 +#define reg_eth_r_stat___rxer___lsb 16 +#define reg_eth_r_stat___rxer___width 1 +#define reg_eth_r_stat___rxer___bit 16 +#define reg_eth_r_stat___rxdv___lsb 17 +#define reg_eth_r_stat___rxdv___width 1 +#define reg_eth_r_stat___rxdv___bit 17 +#define reg_eth_r_stat___rxclk___lsb 18 +#define reg_eth_r_stat___rxclk___width 1 +#define reg_eth_r_stat___rxclk___bit 18 +#define reg_eth_r_stat_offset 44 + +/* Register rs_rec_cnt, scope eth, type rs */ +#define reg_eth_rs_rec_cnt___crc_err___lsb 0 +#define reg_eth_rs_rec_cnt___crc_err___width 8 +#define reg_eth_rs_rec_cnt___align_err___lsb 8 +#define reg_eth_rs_rec_cnt___align_err___width 8 +#define reg_eth_rs_rec_cnt___oversize___lsb 16 +#define reg_eth_rs_rec_cnt___oversize___width 8 +#define reg_eth_rs_rec_cnt___congestion___lsb 24 +#define reg_eth_rs_rec_cnt___congestion___width 8 +#define reg_eth_rs_rec_cnt_offset 48 + +/* Register r_rec_cnt, scope eth, type r */ +#define reg_eth_r_rec_cnt___crc_err___lsb 0 +#define reg_eth_r_rec_cnt___crc_err___width 8 +#define reg_eth_r_rec_cnt___align_err___lsb 8 +#define reg_eth_r_rec_cnt___align_err___width 8 +#define reg_eth_r_rec_cnt___oversize___lsb 16 +#define reg_eth_r_rec_cnt___oversize___width 8 +#define reg_eth_r_rec_cnt___congestion___lsb 24 +#define reg_eth_r_rec_cnt___congestion___width 8 +#define reg_eth_r_rec_cnt_offset 52 + +/* Register rs_tr_cnt, scope eth, type rs */ +#define reg_eth_rs_tr_cnt___single_col___lsb 0 +#define reg_eth_rs_tr_cnt___single_col___width 8 +#define reg_eth_rs_tr_cnt___mult_col___lsb 8 +#define reg_eth_rs_tr_cnt___mult_col___width 8 +#define reg_eth_rs_tr_cnt___late_col___lsb 16 +#define reg_eth_rs_tr_cnt___late_col___width 8 +#define reg_eth_rs_tr_cnt___deferred___lsb 24 +#define reg_eth_rs_tr_cnt___deferred___width 8 +#define reg_eth_rs_tr_cnt_offset 56 + +/* Register r_tr_cnt, scope eth, type r */ +#define reg_eth_r_tr_cnt___single_col___lsb 0 +#define reg_eth_r_tr_cnt___single_col___width 8 +#define reg_eth_r_tr_cnt___mult_col___lsb 8 +#define reg_eth_r_tr_cnt___mult_col___width 8 +#define reg_eth_r_tr_cnt___late_col___lsb 16 +#define reg_eth_r_tr_cnt___late_col___width 8 +#define reg_eth_r_tr_cnt___deferred___lsb 24 +#define reg_eth_r_tr_cnt___deferred___width 8 +#define reg_eth_r_tr_cnt_offset 60 + +/* Register rs_phy_cnt, scope eth, type rs */ +#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 +#define reg_eth_rs_phy_cnt___carrier_loss___width 8 +#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 +#define reg_eth_rs_phy_cnt___sqe_err___width 8 +#define reg_eth_rs_phy_cnt_offset 64 + +/* Register r_phy_cnt, scope eth, type r */ +#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 +#define reg_eth_r_phy_cnt___carrier_loss___width 8 +#define reg_eth_r_phy_cnt___sqe_err___lsb 8 +#define reg_eth_r_phy_cnt___sqe_err___width 8 +#define reg_eth_r_phy_cnt_offset 68 + +/* Register rw_test_ctrl, scope eth, type rw */ +#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 +#define reg_eth_rw_test_ctrl___snmp_inc___width 1 +#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 +#define reg_eth_rw_test_ctrl___snmp___lsb 1 +#define reg_eth_rw_test_ctrl___snmp___width 1 +#define reg_eth_rw_test_ctrl___snmp___bit 1 +#define reg_eth_rw_test_ctrl___backoff___lsb 2 +#define reg_eth_rw_test_ctrl___backoff___width 1 +#define reg_eth_rw_test_ctrl___backoff___bit 2 +#define reg_eth_rw_test_ctrl_offset 72 + +/* Register rw_intr_mask, scope eth, type rw */ +#define reg_eth_rw_intr_mask___crc___lsb 0 +#define reg_eth_rw_intr_mask___crc___width 1 +#define reg_eth_rw_intr_mask___crc___bit 0 +#define reg_eth_rw_intr_mask___align___lsb 1 +#define reg_eth_rw_intr_mask___align___width 1 +#define reg_eth_rw_intr_mask___align___bit 1 +#define reg_eth_rw_intr_mask___oversize___lsb 2 +#define reg_eth_rw_intr_mask___oversize___width 1 +#define reg_eth_rw_intr_mask___oversize___bit 2 +#define reg_eth_rw_intr_mask___congestion___lsb 3 +#define reg_eth_rw_intr_mask___congestion___width 1 +#define reg_eth_rw_intr_mask___congestion___bit 3 +#define reg_eth_rw_intr_mask___single_col___lsb 4 +#define reg_eth_rw_intr_mask___single_col___width 1 +#define reg_eth_rw_intr_mask___single_col___bit 4 +#define reg_eth_rw_intr_mask___mult_col___lsb 5 +#define reg_eth_rw_intr_mask___mult_col___width 1 +#define reg_eth_rw_intr_mask___mult_col___bit 5 +#define reg_eth_rw_intr_mask___late_col___lsb 6 +#define reg_eth_rw_intr_mask___late_col___width 1 +#define reg_eth_rw_intr_mask___late_col___bit 6 +#define reg_eth_rw_intr_mask___deferred___lsb 7 +#define reg_eth_rw_intr_mask___deferred___width 1 +#define reg_eth_rw_intr_mask___deferred___bit 7 +#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 +#define reg_eth_rw_intr_mask___carrier_loss___width 1 +#define reg_eth_rw_intr_mask___carrier_loss___bit 8 +#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 +#define reg_eth_rw_intr_mask___sqe_test_err___width 1 +#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 +#define reg_eth_rw_intr_mask___orun___lsb 10 +#define reg_eth_rw_intr_mask___orun___width 1 +#define reg_eth_rw_intr_mask___orun___bit 10 +#define reg_eth_rw_intr_mask___urun___lsb 11 +#define reg_eth_rw_intr_mask___urun___width 1 +#define reg_eth_rw_intr_mask___urun___bit 11 +#define reg_eth_rw_intr_mask___excessive_col___lsb 12 +#define reg_eth_rw_intr_mask___excessive_col___width 1 +#define reg_eth_rw_intr_mask___excessive_col___bit 12 +#define reg_eth_rw_intr_mask___mdio___lsb 13 +#define reg_eth_rw_intr_mask___mdio___width 1 +#define reg_eth_rw_intr_mask___mdio___bit 13 +#define reg_eth_rw_intr_mask_offset 76 + +/* Register rw_ack_intr, scope eth, type rw */ +#define reg_eth_rw_ack_intr___crc___lsb 0 +#define reg_eth_rw_ack_intr___crc___width 1 +#define reg_eth_rw_ack_intr___crc___bit 0 +#define reg_eth_rw_ack_intr___align___lsb 1 +#define reg_eth_rw_ack_intr___align___width 1 +#define reg_eth_rw_ack_intr___align___bit 1 +#define reg_eth_rw_ack_intr___oversize___lsb 2 +#define reg_eth_rw_ack_intr___oversize___width 1 +#define reg_eth_rw_ack_intr___oversize___bit 2 +#define reg_eth_rw_ack_intr___congestion___lsb 3 +#define reg_eth_rw_ack_intr___congestion___width 1 +#define reg_eth_rw_ack_intr___congestion___bit 3 +#define reg_eth_rw_ack_intr___single_col___lsb 4 +#define reg_eth_rw_ack_intr___single_col___width 1 +#define reg_eth_rw_ack_intr___single_col___bit 4 +#define reg_eth_rw_ack_intr___mult_col___lsb 5 +#define reg_eth_rw_ack_intr___mult_col___width 1 +#define reg_eth_rw_ack_intr___mult_col___bit 5 +#define reg_eth_rw_ack_intr___late_col___lsb 6 +#define reg_eth_rw_ack_intr___late_col___width 1 +#define reg_eth_rw_ack_intr___late_col___bit 6 +#define reg_eth_rw_ack_intr___deferred___lsb 7 +#define reg_eth_rw_ack_intr___deferred___width 1 +#define reg_eth_rw_ack_intr___deferred___bit 7 +#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 +#define reg_eth_rw_ack_intr___carrier_loss___width 1 +#define reg_eth_rw_ack_intr___carrier_loss___bit 8 +#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 +#define reg_eth_rw_ack_intr___sqe_test_err___width 1 +#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 +#define reg_eth_rw_ack_intr___orun___lsb 10 +#define reg_eth_rw_ack_intr___orun___width 1 +#define reg_eth_rw_ack_intr___orun___bit 10 +#define reg_eth_rw_ack_intr___urun___lsb 11 +#define reg_eth_rw_ack_intr___urun___width 1 +#define reg_eth_rw_ack_intr___urun___bit 11 +#define reg_eth_rw_ack_intr___excessive_col___lsb 12 +#define reg_eth_rw_ack_intr___excessive_col___width 1 +#define reg_eth_rw_ack_intr___excessive_col___bit 12 +#define reg_eth_rw_ack_intr___mdio___lsb 13 +#define reg_eth_rw_ack_intr___mdio___width 1 +#define reg_eth_rw_ack_intr___mdio___bit 13 +#define reg_eth_rw_ack_intr_offset 80 + +/* Register r_intr, scope eth, type r */ +#define reg_eth_r_intr___crc___lsb 0 +#define reg_eth_r_intr___crc___width 1 +#define reg_eth_r_intr___crc___bit 0 +#define reg_eth_r_intr___align___lsb 1 +#define reg_eth_r_intr___align___width 1 +#define reg_eth_r_intr___align___bit 1 +#define reg_eth_r_intr___oversize___lsb 2 +#define reg_eth_r_intr___oversize___width 1 +#define reg_eth_r_intr___oversize___bit 2 +#define reg_eth_r_intr___congestion___lsb 3 +#define reg_eth_r_intr___congestion___width 1 +#define reg_eth_r_intr___congestion___bit 3 +#define reg_eth_r_intr___single_col___lsb 4 +#define reg_eth_r_intr___single_col___width 1 +#define reg_eth_r_intr___single_col___bit 4 +#define reg_eth_r_intr___mult_col___lsb 5 +#define reg_eth_r_intr___mult_col___width 1 +#define reg_eth_r_intr___mult_col___bit 5 +#define reg_eth_r_intr___late_col___lsb 6 +#define reg_eth_r_intr___late_col___width 1 +#define reg_eth_r_intr___late_col___bit 6 +#define reg_eth_r_intr___deferred___lsb 7 +#define reg_eth_r_intr___deferred___width 1 +#define reg_eth_r_intr___deferred___bit 7 +#define reg_eth_r_intr___carrier_loss___lsb 8 +#define reg_eth_r_intr___carrier_loss___width 1 +#define reg_eth_r_intr___carrier_loss___bit 8 +#define reg_eth_r_intr___sqe_test_err___lsb 9 +#define reg_eth_r_intr___sqe_test_err___width 1 +#define reg_eth_r_intr___sqe_test_err___bit 9 +#define reg_eth_r_intr___orun___lsb 10 +#define reg_eth_r_intr___orun___width 1 +#define reg_eth_r_intr___orun___bit 10 +#define reg_eth_r_intr___urun___lsb 11 +#define reg_eth_r_intr___urun___width 1 +#define reg_eth_r_intr___urun___bit 11 +#define reg_eth_r_intr___excessive_col___lsb 12 +#define reg_eth_r_intr___excessive_col___width 1 +#define reg_eth_r_intr___excessive_col___bit 12 +#define reg_eth_r_intr___mdio___lsb 13 +#define reg_eth_r_intr___mdio___width 1 +#define reg_eth_r_intr___mdio___bit 13 +#define reg_eth_r_intr_offset 84 + +/* Register r_masked_intr, scope eth, type r */ +#define reg_eth_r_masked_intr___crc___lsb 0 +#define reg_eth_r_masked_intr___crc___width 1 +#define reg_eth_r_masked_intr___crc___bit 0 +#define reg_eth_r_masked_intr___align___lsb 1 +#define reg_eth_r_masked_intr___align___width 1 +#define reg_eth_r_masked_intr___align___bit 1 +#define reg_eth_r_masked_intr___oversize___lsb 2 +#define reg_eth_r_masked_intr___oversize___width 1 +#define reg_eth_r_masked_intr___oversize___bit 2 +#define reg_eth_r_masked_intr___congestion___lsb 3 +#define reg_eth_r_masked_intr___congestion___width 1 +#define reg_eth_r_masked_intr___congestion___bit 3 +#define reg_eth_r_masked_intr___single_col___lsb 4 +#define reg_eth_r_masked_intr___single_col___width 1 +#define reg_eth_r_masked_intr___single_col___bit 4 +#define reg_eth_r_masked_intr___mult_col___lsb 5 +#define reg_eth_r_masked_intr___mult_col___width 1 +#define reg_eth_r_masked_intr___mult_col___bit 5 +#define reg_eth_r_masked_intr___late_col___lsb 6 +#define reg_eth_r_masked_intr___late_col___width 1 +#define reg_eth_r_masked_intr___late_col___bit 6 +#define reg_eth_r_masked_intr___deferred___lsb 7 +#define reg_eth_r_masked_intr___deferred___width 1 +#define reg_eth_r_masked_intr___deferred___bit 7 +#define reg_eth_r_masked_intr___carrier_loss___lsb 8 +#define reg_eth_r_masked_intr___carrier_loss___width 1 +#define reg_eth_r_masked_intr___carrier_loss___bit 8 +#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 +#define reg_eth_r_masked_intr___sqe_test_err___width 1 +#define reg_eth_r_masked_intr___sqe_test_err___bit 9 +#define reg_eth_r_masked_intr___orun___lsb 10 +#define reg_eth_r_masked_intr___orun___width 1 +#define reg_eth_r_masked_intr___orun___bit 10 +#define reg_eth_r_masked_intr___urun___lsb 11 +#define reg_eth_r_masked_intr___urun___width 1 +#define reg_eth_r_masked_intr___urun___bit 11 +#define reg_eth_r_masked_intr___excessive_col___lsb 12 +#define reg_eth_r_masked_intr___excessive_col___width 1 +#define reg_eth_r_masked_intr___excessive_col___bit 12 +#define reg_eth_r_masked_intr___mdio___lsb 13 +#define reg_eth_r_masked_intr___mdio___width 1 +#define reg_eth_r_masked_intr___mdio___bit 13 +#define reg_eth_r_masked_intr_offset 88 + + +/* Constants */ +#define regk_eth_discard 0x00000000 +#define regk_eth_ether 0x00000000 +#define regk_eth_full 0x00000001 +#define regk_eth_half 0x00000000 +#define regk_eth_hsh 0x00000001 +#define regk_eth_mii 0x00000001 +#define regk_eth_mii_clk 0x00000000 +#define regk_eth_mii_rec 0x00000002 +#define regk_eth_no 0x00000000 +#define regk_eth_rec 0x00000001 +#define regk_eth_rw_ga_hi_default 0x00000000 +#define regk_eth_rw_ga_lo_default 0x00000000 +#define regk_eth_rw_gen_ctrl_default 0x00000000 +#define regk_eth_rw_intr_mask_default 0x00000000 +#define regk_eth_rw_ma0_hi_default 0x00000000 +#define regk_eth_rw_ma0_lo_default 0x00000000 +#define regk_eth_rw_ma1_hi_default 0x00000000 +#define regk_eth_rw_ma1_lo_default 0x00000000 +#define regk_eth_rw_mgm_ctrl_default 0x00000000 +#define regk_eth_rw_test_ctrl_default 0x00000000 +#define regk_eth_size1518 0x00000000 +#define regk_eth_size1522 0x00000001 +#define regk_eth_yes 0x00000001 +#endif /* __eth_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000000..35356bc08629 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 8 +#define reg_gio_rw_pa_dout_offset 0 + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 8 +#define reg_gio_r_pa_din_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 8 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___pa0___lsb 0 +#define reg_gio_rw_intr_cfg___pa0___width 3 +#define reg_gio_rw_intr_cfg___pa1___lsb 3 +#define reg_gio_rw_intr_cfg___pa1___width 3 +#define reg_gio_rw_intr_cfg___pa2___lsb 6 +#define reg_gio_rw_intr_cfg___pa2___width 3 +#define reg_gio_rw_intr_cfg___pa3___lsb 9 +#define reg_gio_rw_intr_cfg___pa3___width 3 +#define reg_gio_rw_intr_cfg___pa4___lsb 12 +#define reg_gio_rw_intr_cfg___pa4___width 3 +#define reg_gio_rw_intr_cfg___pa5___lsb 15 +#define reg_gio_rw_intr_cfg___pa5___width 3 +#define reg_gio_rw_intr_cfg___pa6___lsb 18 +#define reg_gio_rw_intr_cfg___pa6___width 3 +#define reg_gio_rw_intr_cfg___pa7___lsb 21 +#define reg_gio_rw_intr_cfg___pa7___width 3 +#define reg_gio_rw_intr_cfg_offset 12 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___pa0___lsb 0 +#define reg_gio_rw_intr_mask___pa0___width 1 +#define reg_gio_rw_intr_mask___pa0___bit 0 +#define reg_gio_rw_intr_mask___pa1___lsb 1 +#define reg_gio_rw_intr_mask___pa1___width 1 +#define reg_gio_rw_intr_mask___pa1___bit 1 +#define reg_gio_rw_intr_mask___pa2___lsb 2 +#define reg_gio_rw_intr_mask___pa2___width 1 +#define reg_gio_rw_intr_mask___pa2___bit 2 +#define reg_gio_rw_intr_mask___pa3___lsb 3 +#define reg_gio_rw_intr_mask___pa3___width 1 +#define reg_gio_rw_intr_mask___pa3___bit 3 +#define reg_gio_rw_intr_mask___pa4___lsb 4 +#define reg_gio_rw_intr_mask___pa4___width 1 +#define reg_gio_rw_intr_mask___pa4___bit 4 +#define reg_gio_rw_intr_mask___pa5___lsb 5 +#define reg_gio_rw_intr_mask___pa5___width 1 +#define reg_gio_rw_intr_mask___pa5___bit 5 +#define reg_gio_rw_intr_mask___pa6___lsb 6 +#define reg_gio_rw_intr_mask___pa6___width 1 +#define reg_gio_rw_intr_mask___pa6___bit 6 +#define reg_gio_rw_intr_mask___pa7___lsb 7 +#define reg_gio_rw_intr_mask___pa7___width 1 +#define reg_gio_rw_intr_mask___pa7___bit 7 +#define reg_gio_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___pa0___lsb 0 +#define reg_gio_rw_ack_intr___pa0___width 1 +#define reg_gio_rw_ack_intr___pa0___bit 0 +#define reg_gio_rw_ack_intr___pa1___lsb 1 +#define reg_gio_rw_ack_intr___pa1___width 1 +#define reg_gio_rw_ack_intr___pa1___bit 1 +#define reg_gio_rw_ack_intr___pa2___lsb 2 +#define reg_gio_rw_ack_intr___pa2___width 1 +#define reg_gio_rw_ack_intr___pa2___bit 2 +#define reg_gio_rw_ack_intr___pa3___lsb 3 +#define reg_gio_rw_ack_intr___pa3___width 1 +#define reg_gio_rw_ack_intr___pa3___bit 3 +#define reg_gio_rw_ack_intr___pa4___lsb 4 +#define reg_gio_rw_ack_intr___pa4___width 1 +#define reg_gio_rw_ack_intr___pa4___bit 4 +#define reg_gio_rw_ack_intr___pa5___lsb 5 +#define reg_gio_rw_ack_intr___pa5___width 1 +#define reg_gio_rw_ack_intr___pa5___bit 5 +#define reg_gio_rw_ack_intr___pa6___lsb 6 +#define reg_gio_rw_ack_intr___pa6___width 1 +#define reg_gio_rw_ack_intr___pa6___bit 6 +#define reg_gio_rw_ack_intr___pa7___lsb 7 +#define reg_gio_rw_ack_intr___pa7___width 1 +#define reg_gio_rw_ack_intr___pa7___bit 7 +#define reg_gio_rw_ack_intr_offset 20 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___pa0___lsb 0 +#define reg_gio_r_intr___pa0___width 1 +#define reg_gio_r_intr___pa0___bit 0 +#define reg_gio_r_intr___pa1___lsb 1 +#define reg_gio_r_intr___pa1___width 1 +#define reg_gio_r_intr___pa1___bit 1 +#define reg_gio_r_intr___pa2___lsb 2 +#define reg_gio_r_intr___pa2___width 1 +#define reg_gio_r_intr___pa2___bit 2 +#define reg_gio_r_intr___pa3___lsb 3 +#define reg_gio_r_intr___pa3___width 1 +#define reg_gio_r_intr___pa3___bit 3 +#define reg_gio_r_intr___pa4___lsb 4 +#define reg_gio_r_intr___pa4___width 1 +#define reg_gio_r_intr___pa4___bit 4 +#define reg_gio_r_intr___pa5___lsb 5 +#define reg_gio_r_intr___pa5___width 1 +#define reg_gio_r_intr___pa5___bit 5 +#define reg_gio_r_intr___pa6___lsb 6 +#define reg_gio_r_intr___pa6___width 1 +#define reg_gio_r_intr___pa6___bit 6 +#define reg_gio_r_intr___pa7___lsb 7 +#define reg_gio_r_intr___pa7___width 1 +#define reg_gio_r_intr___pa7___bit 7 +#define reg_gio_r_intr_offset 24 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___pa0___lsb 0 +#define reg_gio_r_masked_intr___pa0___width 1 +#define reg_gio_r_masked_intr___pa0___bit 0 +#define reg_gio_r_masked_intr___pa1___lsb 1 +#define reg_gio_r_masked_intr___pa1___width 1 +#define reg_gio_r_masked_intr___pa1___bit 1 +#define reg_gio_r_masked_intr___pa2___lsb 2 +#define reg_gio_r_masked_intr___pa2___width 1 +#define reg_gio_r_masked_intr___pa2___bit 2 +#define reg_gio_r_masked_intr___pa3___lsb 3 +#define reg_gio_r_masked_intr___pa3___width 1 +#define reg_gio_r_masked_intr___pa3___bit 3 +#define reg_gio_r_masked_intr___pa4___lsb 4 +#define reg_gio_r_masked_intr___pa4___width 1 +#define reg_gio_r_masked_intr___pa4___bit 4 +#define reg_gio_r_masked_intr___pa5___lsb 5 +#define reg_gio_r_masked_intr___pa5___width 1 +#define reg_gio_r_masked_intr___pa5___bit 5 +#define reg_gio_r_masked_intr___pa6___lsb 6 +#define reg_gio_r_masked_intr___pa6___width 1 +#define reg_gio_r_masked_intr___pa6___bit 6 +#define reg_gio_r_masked_intr___pa7___lsb 7 +#define reg_gio_r_masked_intr___pa7___width 1 +#define reg_gio_r_masked_intr___pa7___bit 7 +#define reg_gio_r_masked_intr_offset 28 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 18 +#define reg_gio_rw_pb_dout_offset 32 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 18 +#define reg_gio_r_pb_din_offset 36 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 18 +#define reg_gio_rw_pb_oe_offset 40 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 18 +#define reg_gio_rw_pc_dout_offset 48 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 18 +#define reg_gio_r_pc_din_offset 52 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 18 +#define reg_gio_rw_pc_oe_offset 56 + +/* Register rw_pd_dout, scope gio, type rw */ +#define reg_gio_rw_pd_dout___data___lsb 0 +#define reg_gio_rw_pd_dout___data___width 18 +#define reg_gio_rw_pd_dout_offset 64 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 18 +#define reg_gio_r_pd_din_offset 68 + +/* Register rw_pd_oe, scope gio, type rw */ +#define reg_gio_rw_pd_oe___oe___lsb 0 +#define reg_gio_rw_pd_oe___oe___width 18 +#define reg_gio_rw_pd_oe_offset 72 + +/* Register rw_pe_dout, scope gio, type rw */ +#define reg_gio_rw_pe_dout___data___lsb 0 +#define reg_gio_rw_pe_dout___data___width 18 +#define reg_gio_rw_pe_dout_offset 80 + +/* Register r_pe_din, scope gio, type r */ +#define reg_gio_r_pe_din___data___lsb 0 +#define reg_gio_r_pe_din___data___width 18 +#define reg_gio_r_pe_din_offset 84 + +/* Register rw_pe_oe, scope gio, type rw */ +#define reg_gio_rw_pe_oe___oe___lsb 0 +#define reg_gio_rw_pe_oe___oe___width 18 +#define reg_gio_rw_pe_oe_offset 88 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_hi 0x00000001 +#define regk_gio_lo 0x00000002 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_off 0x00000000 +#define regk_gio_posedge 0x00000005 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_pd_oe_default 0x00000000 +#define regk_gio_rw_pe_oe_default 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h new file mode 100644 index 000000000000..c8315905c571 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h @@ -0,0 +1,38 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e + +#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h new file mode 100644 index 000000000000..6df2a433b02d --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h @@ -0,0 +1,355 @@ +#ifndef __intr_vect_defs_asm_h +#define __intr_vect_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * last modfied: Mon Apr 11 16:08:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mask, scope intr_vect, type rw */ +#define reg_intr_vect_rw_mask___memarb___lsb 0 +#define reg_intr_vect_rw_mask___memarb___width 1 +#define reg_intr_vect_rw_mask___memarb___bit 0 +#define reg_intr_vect_rw_mask___gen_io___lsb 1 +#define reg_intr_vect_rw_mask___gen_io___width 1 +#define reg_intr_vect_rw_mask___gen_io___bit 1 +#define reg_intr_vect_rw_mask___iop0___lsb 2 +#define reg_intr_vect_rw_mask___iop0___width 1 +#define reg_intr_vect_rw_mask___iop0___bit 2 +#define reg_intr_vect_rw_mask___iop1___lsb 3 +#define reg_intr_vect_rw_mask___iop1___width 1 +#define reg_intr_vect_rw_mask___iop1___bit 3 +#define reg_intr_vect_rw_mask___iop2___lsb 4 +#define reg_intr_vect_rw_mask___iop2___width 1 +#define reg_intr_vect_rw_mask___iop2___bit 4 +#define reg_intr_vect_rw_mask___iop3___lsb 5 +#define reg_intr_vect_rw_mask___iop3___width 1 +#define reg_intr_vect_rw_mask___iop3___bit 5 +#define reg_intr_vect_rw_mask___dma0___lsb 6 +#define reg_intr_vect_rw_mask___dma0___width 1 +#define reg_intr_vect_rw_mask___dma0___bit 6 +#define reg_intr_vect_rw_mask___dma1___lsb 7 +#define reg_intr_vect_rw_mask___dma1___width 1 +#define reg_intr_vect_rw_mask___dma1___bit 7 +#define reg_intr_vect_rw_mask___dma2___lsb 8 +#define reg_intr_vect_rw_mask___dma2___width 1 +#define reg_intr_vect_rw_mask___dma2___bit 8 +#define reg_intr_vect_rw_mask___dma3___lsb 9 +#define reg_intr_vect_rw_mask___dma3___width 1 +#define reg_intr_vect_rw_mask___dma3___bit 9 +#define reg_intr_vect_rw_mask___dma4___lsb 10 +#define reg_intr_vect_rw_mask___dma4___width 1 +#define reg_intr_vect_rw_mask___dma4___bit 10 +#define reg_intr_vect_rw_mask___dma5___lsb 11 +#define reg_intr_vect_rw_mask___dma5___width 1 +#define reg_intr_vect_rw_mask___dma5___bit 11 +#define reg_intr_vect_rw_mask___dma6___lsb 12 +#define reg_intr_vect_rw_mask___dma6___width 1 +#define reg_intr_vect_rw_mask___dma6___bit 12 +#define reg_intr_vect_rw_mask___dma7___lsb 13 +#define reg_intr_vect_rw_mask___dma7___width 1 +#define reg_intr_vect_rw_mask___dma7___bit 13 +#define reg_intr_vect_rw_mask___dma8___lsb 14 +#define reg_intr_vect_rw_mask___dma8___width 1 +#define reg_intr_vect_rw_mask___dma8___bit 14 +#define reg_intr_vect_rw_mask___dma9___lsb 15 +#define reg_intr_vect_rw_mask___dma9___width 1 +#define reg_intr_vect_rw_mask___dma9___bit 15 +#define reg_intr_vect_rw_mask___ata___lsb 16 +#define reg_intr_vect_rw_mask___ata___width 1 +#define reg_intr_vect_rw_mask___ata___bit 16 +#define reg_intr_vect_rw_mask___sser0___lsb 17 +#define reg_intr_vect_rw_mask___sser0___width 1 +#define reg_intr_vect_rw_mask___sser0___bit 17 +#define reg_intr_vect_rw_mask___sser1___lsb 18 +#define reg_intr_vect_rw_mask___sser1___width 1 +#define reg_intr_vect_rw_mask___sser1___bit 18 +#define reg_intr_vect_rw_mask___ser0___lsb 19 +#define reg_intr_vect_rw_mask___ser0___width 1 +#define reg_intr_vect_rw_mask___ser0___bit 19 +#define reg_intr_vect_rw_mask___ser1___lsb 20 +#define reg_intr_vect_rw_mask___ser1___width 1 +#define reg_intr_vect_rw_mask___ser1___bit 20 +#define reg_intr_vect_rw_mask___ser2___lsb 21 +#define reg_intr_vect_rw_mask___ser2___width 1 +#define reg_intr_vect_rw_mask___ser2___bit 21 +#define reg_intr_vect_rw_mask___ser3___lsb 22 +#define reg_intr_vect_rw_mask___ser3___width 1 +#define reg_intr_vect_rw_mask___ser3___bit 22 +#define reg_intr_vect_rw_mask___p21___lsb 23 +#define reg_intr_vect_rw_mask___p21___width 1 +#define reg_intr_vect_rw_mask___p21___bit 23 +#define reg_intr_vect_rw_mask___eth0___lsb 24 +#define reg_intr_vect_rw_mask___eth0___width 1 +#define reg_intr_vect_rw_mask___eth0___bit 24 +#define reg_intr_vect_rw_mask___eth1___lsb 25 +#define reg_intr_vect_rw_mask___eth1___width 1 +#define reg_intr_vect_rw_mask___eth1___bit 25 +#define reg_intr_vect_rw_mask___timer___lsb 26 +#define reg_intr_vect_rw_mask___timer___width 1 +#define reg_intr_vect_rw_mask___timer___bit 26 +#define reg_intr_vect_rw_mask___bif_arb___lsb 27 +#define reg_intr_vect_rw_mask___bif_arb___width 1 +#define reg_intr_vect_rw_mask___bif_arb___bit 27 +#define reg_intr_vect_rw_mask___bif_dma___lsb 28 +#define reg_intr_vect_rw_mask___bif_dma___width 1 +#define reg_intr_vect_rw_mask___bif_dma___bit 28 +#define reg_intr_vect_rw_mask___ext___lsb 29 +#define reg_intr_vect_rw_mask___ext___width 1 +#define reg_intr_vect_rw_mask___ext___bit 29 +#define reg_intr_vect_rw_mask_offset 0 + +/* Register r_vect, scope intr_vect, type r */ +#define reg_intr_vect_r_vect___memarb___lsb 0 +#define reg_intr_vect_r_vect___memarb___width 1 +#define reg_intr_vect_r_vect___memarb___bit 0 +#define reg_intr_vect_r_vect___gen_io___lsb 1 +#define reg_intr_vect_r_vect___gen_io___width 1 +#define reg_intr_vect_r_vect___gen_io___bit 1 +#define reg_intr_vect_r_vect___iop0___lsb 2 +#define reg_intr_vect_r_vect___iop0___width 1 +#define reg_intr_vect_r_vect___iop0___bit 2 +#define reg_intr_vect_r_vect___iop1___lsb 3 +#define reg_intr_vect_r_vect___iop1___width 1 +#define reg_intr_vect_r_vect___iop1___bit 3 +#define reg_intr_vect_r_vect___iop2___lsb 4 +#define reg_intr_vect_r_vect___iop2___width 1 +#define reg_intr_vect_r_vect___iop2___bit 4 +#define reg_intr_vect_r_vect___iop3___lsb 5 +#define reg_intr_vect_r_vect___iop3___width 1 +#define reg_intr_vect_r_vect___iop3___bit 5 +#define reg_intr_vect_r_vect___dma0___lsb 6 +#define reg_intr_vect_r_vect___dma0___width 1 +#define reg_intr_vect_r_vect___dma0___bit 6 +#define reg_intr_vect_r_vect___dma1___lsb 7 +#define reg_intr_vect_r_vect___dma1___width 1 +#define reg_intr_vect_r_vect___dma1___bit 7 +#define reg_intr_vect_r_vect___dma2___lsb 8 +#define reg_intr_vect_r_vect___dma2___width 1 +#define reg_intr_vect_r_vect___dma2___bit 8 +#define reg_intr_vect_r_vect___dma3___lsb 9 +#define reg_intr_vect_r_vect___dma3___width 1 +#define reg_intr_vect_r_vect___dma3___bit 9 +#define reg_intr_vect_r_vect___dma4___lsb 10 +#define reg_intr_vect_r_vect___dma4___width 1 +#define reg_intr_vect_r_vect___dma4___bit 10 +#define reg_intr_vect_r_vect___dma5___lsb 11 +#define reg_intr_vect_r_vect___dma5___width 1 +#define reg_intr_vect_r_vect___dma5___bit 11 +#define reg_intr_vect_r_vect___dma6___lsb 12 +#define reg_intr_vect_r_vect___dma6___width 1 +#define reg_intr_vect_r_vect___dma6___bit 12 +#define reg_intr_vect_r_vect___dma7___lsb 13 +#define reg_intr_vect_r_vect___dma7___width 1 +#define reg_intr_vect_r_vect___dma7___bit 13 +#define reg_intr_vect_r_vect___dma8___lsb 14 +#define reg_intr_vect_r_vect___dma8___width 1 +#define reg_intr_vect_r_vect___dma8___bit 14 +#define reg_intr_vect_r_vect___dma9___lsb 15 +#define reg_intr_vect_r_vect___dma9___width 1 +#define reg_intr_vect_r_vect___dma9___bit 15 +#define reg_intr_vect_r_vect___ata___lsb 16 +#define reg_intr_vect_r_vect___ata___width 1 +#define reg_intr_vect_r_vect___ata___bit 16 +#define reg_intr_vect_r_vect___sser0___lsb 17 +#define reg_intr_vect_r_vect___sser0___width 1 +#define reg_intr_vect_r_vect___sser0___bit 17 +#define reg_intr_vect_r_vect___sser1___lsb 18 +#define reg_intr_vect_r_vect___sser1___width 1 +#define reg_intr_vect_r_vect___sser1___bit 18 +#define reg_intr_vect_r_vect___ser0___lsb 19 +#define reg_intr_vect_r_vect___ser0___width 1 +#define reg_intr_vect_r_vect___ser0___bit 19 +#define reg_intr_vect_r_vect___ser1___lsb 20 +#define reg_intr_vect_r_vect___ser1___width 1 +#define reg_intr_vect_r_vect___ser1___bit 20 +#define reg_intr_vect_r_vect___ser2___lsb 21 +#define reg_intr_vect_r_vect___ser2___width 1 +#define reg_intr_vect_r_vect___ser2___bit 21 +#define reg_intr_vect_r_vect___ser3___lsb 22 +#define reg_intr_vect_r_vect___ser3___width 1 +#define reg_intr_vect_r_vect___ser3___bit 22 +#define reg_intr_vect_r_vect___p21___lsb 23 +#define reg_intr_vect_r_vect___p21___width 1 +#define reg_intr_vect_r_vect___p21___bit 23 +#define reg_intr_vect_r_vect___eth0___lsb 24 +#define reg_intr_vect_r_vect___eth0___width 1 +#define reg_intr_vect_r_vect___eth0___bit 24 +#define reg_intr_vect_r_vect___eth1___lsb 25 +#define reg_intr_vect_r_vect___eth1___width 1 +#define reg_intr_vect_r_vect___eth1___bit 25 +#define reg_intr_vect_r_vect___timer___lsb 26 +#define reg_intr_vect_r_vect___timer___width 1 +#define reg_intr_vect_r_vect___timer___bit 26 +#define reg_intr_vect_r_vect___bif_arb___lsb 27 +#define reg_intr_vect_r_vect___bif_arb___width 1 +#define reg_intr_vect_r_vect___bif_arb___bit 27 +#define reg_intr_vect_r_vect___bif_dma___lsb 28 +#define reg_intr_vect_r_vect___bif_dma___width 1 +#define reg_intr_vect_r_vect___bif_dma___bit 28 +#define reg_intr_vect_r_vect___ext___lsb 29 +#define reg_intr_vect_r_vect___ext___width 1 +#define reg_intr_vect_r_vect___ext___bit 29 +#define reg_intr_vect_r_vect_offset 4 + +/* Register r_masked_vect, scope intr_vect, type r */ +#define reg_intr_vect_r_masked_vect___memarb___lsb 0 +#define reg_intr_vect_r_masked_vect___memarb___width 1 +#define reg_intr_vect_r_masked_vect___memarb___bit 0 +#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 +#define reg_intr_vect_r_masked_vect___gen_io___width 1 +#define reg_intr_vect_r_masked_vect___gen_io___bit 1 +#define reg_intr_vect_r_masked_vect___iop0___lsb 2 +#define reg_intr_vect_r_masked_vect___iop0___width 1 +#define reg_intr_vect_r_masked_vect___iop0___bit 2 +#define reg_intr_vect_r_masked_vect___iop1___lsb 3 +#define reg_intr_vect_r_masked_vect___iop1___width 1 +#define reg_intr_vect_r_masked_vect___iop1___bit 3 +#define reg_intr_vect_r_masked_vect___iop2___lsb 4 +#define reg_intr_vect_r_masked_vect___iop2___width 1 +#define reg_intr_vect_r_masked_vect___iop2___bit 4 +#define reg_intr_vect_r_masked_vect___iop3___lsb 5 +#define reg_intr_vect_r_masked_vect___iop3___width 1 +#define reg_intr_vect_r_masked_vect___iop3___bit 5 +#define reg_intr_vect_r_masked_vect___dma0___lsb 6 +#define reg_intr_vect_r_masked_vect___dma0___width 1 +#define reg_intr_vect_r_masked_vect___dma0___bit 6 +#define reg_intr_vect_r_masked_vect___dma1___lsb 7 +#define reg_intr_vect_r_masked_vect___dma1___width 1 +#define reg_intr_vect_r_masked_vect___dma1___bit 7 +#define reg_intr_vect_r_masked_vect___dma2___lsb 8 +#define reg_intr_vect_r_masked_vect___dma2___width 1 +#define reg_intr_vect_r_masked_vect___dma2___bit 8 +#define reg_intr_vect_r_masked_vect___dma3___lsb 9 +#define reg_intr_vect_r_masked_vect___dma3___width 1 +#define reg_intr_vect_r_masked_vect___dma3___bit 9 +#define reg_intr_vect_r_masked_vect___dma4___lsb 10 +#define reg_intr_vect_r_masked_vect___dma4___width 1 +#define reg_intr_vect_r_masked_vect___dma4___bit 10 +#define reg_intr_vect_r_masked_vect___dma5___lsb 11 +#define reg_intr_vect_r_masked_vect___dma5___width 1 +#define reg_intr_vect_r_masked_vect___dma5___bit 11 +#define reg_intr_vect_r_masked_vect___dma6___lsb 12 +#define reg_intr_vect_r_masked_vect___dma6___width 1 +#define reg_intr_vect_r_masked_vect___dma6___bit 12 +#define reg_intr_vect_r_masked_vect___dma7___lsb 13 +#define reg_intr_vect_r_masked_vect___dma7___width 1 +#define reg_intr_vect_r_masked_vect___dma7___bit 13 +#define reg_intr_vect_r_masked_vect___dma8___lsb 14 +#define reg_intr_vect_r_masked_vect___dma8___width 1 +#define reg_intr_vect_r_masked_vect___dma8___bit 14 +#define reg_intr_vect_r_masked_vect___dma9___lsb 15 +#define reg_intr_vect_r_masked_vect___dma9___width 1 +#define reg_intr_vect_r_masked_vect___dma9___bit 15 +#define reg_intr_vect_r_masked_vect___ata___lsb 16 +#define reg_intr_vect_r_masked_vect___ata___width 1 +#define reg_intr_vect_r_masked_vect___ata___bit 16 +#define reg_intr_vect_r_masked_vect___sser0___lsb 17 +#define reg_intr_vect_r_masked_vect___sser0___width 1 +#define reg_intr_vect_r_masked_vect___sser0___bit 17 +#define reg_intr_vect_r_masked_vect___sser1___lsb 18 +#define reg_intr_vect_r_masked_vect___sser1___width 1 +#define reg_intr_vect_r_masked_vect___sser1___bit 18 +#define reg_intr_vect_r_masked_vect___ser0___lsb 19 +#define reg_intr_vect_r_masked_vect___ser0___width 1 +#define reg_intr_vect_r_masked_vect___ser0___bit 19 +#define reg_intr_vect_r_masked_vect___ser1___lsb 20 +#define reg_intr_vect_r_masked_vect___ser1___width 1 +#define reg_intr_vect_r_masked_vect___ser1___bit 20 +#define reg_intr_vect_r_masked_vect___ser2___lsb 21 +#define reg_intr_vect_r_masked_vect___ser2___width 1 +#define reg_intr_vect_r_masked_vect___ser2___bit 21 +#define reg_intr_vect_r_masked_vect___ser3___lsb 22 +#define reg_intr_vect_r_masked_vect___ser3___width 1 +#define reg_intr_vect_r_masked_vect___ser3___bit 22 +#define reg_intr_vect_r_masked_vect___p21___lsb 23 +#define reg_intr_vect_r_masked_vect___p21___width 1 +#define reg_intr_vect_r_masked_vect___p21___bit 23 +#define reg_intr_vect_r_masked_vect___eth0___lsb 24 +#define reg_intr_vect_r_masked_vect___eth0___width 1 +#define reg_intr_vect_r_masked_vect___eth0___bit 24 +#define reg_intr_vect_r_masked_vect___eth1___lsb 25 +#define reg_intr_vect_r_masked_vect___eth1___width 1 +#define reg_intr_vect_r_masked_vect___eth1___bit 25 +#define reg_intr_vect_r_masked_vect___timer___lsb 26 +#define reg_intr_vect_r_masked_vect___timer___width 1 +#define reg_intr_vect_r_masked_vect___timer___bit 26 +#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 +#define reg_intr_vect_r_masked_vect___bif_arb___width 1 +#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 +#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 +#define reg_intr_vect_r_masked_vect___bif_dma___width 1 +#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 +#define reg_intr_vect_r_masked_vect___ext___lsb 29 +#define reg_intr_vect_r_masked_vect___ext___width 1 +#define reg_intr_vect_r_masked_vect___ext___bit 29 +#define reg_intr_vect_r_masked_vect_offset 8 + +/* Register r_nmi, scope intr_vect, type r */ +#define reg_intr_vect_r_nmi___ext___lsb 0 +#define reg_intr_vect_r_nmi___ext___width 1 +#define reg_intr_vect_r_nmi___ext___bit 0 +#define reg_intr_vect_r_nmi___watchdog___lsb 1 +#define reg_intr_vect_r_nmi___watchdog___width 1 +#define reg_intr_vect_r_nmi___watchdog___bit 1 +#define reg_intr_vect_r_nmi_offset 12 + +/* Register r_guru, scope intr_vect, type r */ +#define reg_intr_vect_r_guru___jtag___lsb 0 +#define reg_intr_vect_r_guru___jtag___width 1 +#define reg_intr_vect_r_guru___jtag___bit 0 +#define reg_intr_vect_r_guru_offset 16 + + +/* Constants */ +#define regk_intr_vect_off 0x00000000 +#define regk_intr_vect_on 0x00000001 +#define regk_intr_vect_rw_mask_default 0x00000000 +#endif /* __intr_vect_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h new file mode 100644 index 000000000000..0c8084054840 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h @@ -0,0 +1,69 @@ +#ifndef __irq_nmi_defs_asm_h +#define __irq_nmi_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../mod/irq_nmi.r + * id: + * last modfied: Thu Jan 22 09:22:43 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r + * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cmd, scope irq_nmi, type rw */ +#define reg_irq_nmi_rw_cmd___delay___lsb 0 +#define reg_irq_nmi_rw_cmd___delay___width 16 +#define reg_irq_nmi_rw_cmd___op___lsb 16 +#define reg_irq_nmi_rw_cmd___op___width 2 +#define reg_irq_nmi_rw_cmd_offset 0 + + +/* Constants */ +#define regk_irq_nmi_ack_irq 0x00000002 +#define regk_irq_nmi_ack_nmi 0x00000003 +#define regk_irq_nmi_irq 0x00000000 +#define regk_irq_nmi_nmi 0x00000001 +#endif /* __irq_nmi_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h new file mode 100644 index 000000000000..45400eb8d389 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h @@ -0,0 +1,579 @@ +#ifndef __marb_defs_asm_h +#define __marb_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +#define reg_marb_rw_int_slots___owner___lsb 0 +#define reg_marb_rw_int_slots___owner___width 4 +#define reg_marb_rw_int_slots_offset 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +#define reg_marb_rw_ext_slots___owner___lsb 0 +#define reg_marb_rw_ext_slots___owner___width 4 +#define reg_marb_rw_ext_slots_offset 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +#define reg_marb_rw_regs_slots___owner___lsb 0 +#define reg_marb_rw_regs_slots___owner___width 4 +#define reg_marb_rw_regs_slots_offset 512 + +/* Register rw_intr_mask, scope marb, type rw */ +#define reg_marb_rw_intr_mask___bp0___lsb 0 +#define reg_marb_rw_intr_mask___bp0___width 1 +#define reg_marb_rw_intr_mask___bp0___bit 0 +#define reg_marb_rw_intr_mask___bp1___lsb 1 +#define reg_marb_rw_intr_mask___bp1___width 1 +#define reg_marb_rw_intr_mask___bp1___bit 1 +#define reg_marb_rw_intr_mask___bp2___lsb 2 +#define reg_marb_rw_intr_mask___bp2___width 1 +#define reg_marb_rw_intr_mask___bp2___bit 2 +#define reg_marb_rw_intr_mask___bp3___lsb 3 +#define reg_marb_rw_intr_mask___bp3___width 1 +#define reg_marb_rw_intr_mask___bp3___bit 3 +#define reg_marb_rw_intr_mask_offset 528 + +/* Register rw_ack_intr, scope marb, type rw */ +#define reg_marb_rw_ack_intr___bp0___lsb 0 +#define reg_marb_rw_ack_intr___bp0___width 1 +#define reg_marb_rw_ack_intr___bp0___bit 0 +#define reg_marb_rw_ack_intr___bp1___lsb 1 +#define reg_marb_rw_ack_intr___bp1___width 1 +#define reg_marb_rw_ack_intr___bp1___bit 1 +#define reg_marb_rw_ack_intr___bp2___lsb 2 +#define reg_marb_rw_ack_intr___bp2___width 1 +#define reg_marb_rw_ack_intr___bp2___bit 2 +#define reg_marb_rw_ack_intr___bp3___lsb 3 +#define reg_marb_rw_ack_intr___bp3___width 1 +#define reg_marb_rw_ack_intr___bp3___bit 3 +#define reg_marb_rw_ack_intr_offset 532 + +/* Register r_intr, scope marb, type r */ +#define reg_marb_r_intr___bp0___lsb 0 +#define reg_marb_r_intr___bp0___width 1 +#define reg_marb_r_intr___bp0___bit 0 +#define reg_marb_r_intr___bp1___lsb 1 +#define reg_marb_r_intr___bp1___width 1 +#define reg_marb_r_intr___bp1___bit 1 +#define reg_marb_r_intr___bp2___lsb 2 +#define reg_marb_r_intr___bp2___width 1 +#define reg_marb_r_intr___bp2___bit 2 +#define reg_marb_r_intr___bp3___lsb 3 +#define reg_marb_r_intr___bp3___width 1 +#define reg_marb_r_intr___bp3___bit 3 +#define reg_marb_r_intr_offset 536 + +/* Register r_masked_intr, scope marb, type r */ +#define reg_marb_r_masked_intr___bp0___lsb 0 +#define reg_marb_r_masked_intr___bp0___width 1 +#define reg_marb_r_masked_intr___bp0___bit 0 +#define reg_marb_r_masked_intr___bp1___lsb 1 +#define reg_marb_r_masked_intr___bp1___width 1 +#define reg_marb_r_masked_intr___bp1___bit 1 +#define reg_marb_r_masked_intr___bp2___lsb 2 +#define reg_marb_r_masked_intr___bp2___width 1 +#define reg_marb_r_masked_intr___bp2___bit 2 +#define reg_marb_r_masked_intr___bp3___lsb 3 +#define reg_marb_r_masked_intr___bp3___width 1 +#define reg_marb_r_masked_intr___bp3___bit 3 +#define reg_marb_r_masked_intr_offset 540 + +/* Register rw_stop_mask, scope marb, type rw */ +#define reg_marb_rw_stop_mask___dma0___lsb 0 +#define reg_marb_rw_stop_mask___dma0___width 1 +#define reg_marb_rw_stop_mask___dma0___bit 0 +#define reg_marb_rw_stop_mask___dma1___lsb 1 +#define reg_marb_rw_stop_mask___dma1___width 1 +#define reg_marb_rw_stop_mask___dma1___bit 1 +#define reg_marb_rw_stop_mask___dma2___lsb 2 +#define reg_marb_rw_stop_mask___dma2___width 1 +#define reg_marb_rw_stop_mask___dma2___bit 2 +#define reg_marb_rw_stop_mask___dma3___lsb 3 +#define reg_marb_rw_stop_mask___dma3___width 1 +#define reg_marb_rw_stop_mask___dma3___bit 3 +#define reg_marb_rw_stop_mask___dma4___lsb 4 +#define reg_marb_rw_stop_mask___dma4___width 1 +#define reg_marb_rw_stop_mask___dma4___bit 4 +#define reg_marb_rw_stop_mask___dma5___lsb 5 +#define reg_marb_rw_stop_mask___dma5___width 1 +#define reg_marb_rw_stop_mask___dma5___bit 5 +#define reg_marb_rw_stop_mask___dma6___lsb 6 +#define reg_marb_rw_stop_mask___dma6___width 1 +#define reg_marb_rw_stop_mask___dma6___bit 6 +#define reg_marb_rw_stop_mask___dma7___lsb 7 +#define reg_marb_rw_stop_mask___dma7___width 1 +#define reg_marb_rw_stop_mask___dma7___bit 7 +#define reg_marb_rw_stop_mask___dma8___lsb 8 +#define reg_marb_rw_stop_mask___dma8___width 1 +#define reg_marb_rw_stop_mask___dma8___bit 8 +#define reg_marb_rw_stop_mask___dma9___lsb 9 +#define reg_marb_rw_stop_mask___dma9___width 1 +#define reg_marb_rw_stop_mask___dma9___bit 9 +#define reg_marb_rw_stop_mask___cpui___lsb 10 +#define reg_marb_rw_stop_mask___cpui___width 1 +#define reg_marb_rw_stop_mask___cpui___bit 10 +#define reg_marb_rw_stop_mask___cpud___lsb 11 +#define reg_marb_rw_stop_mask___cpud___width 1 +#define reg_marb_rw_stop_mask___cpud___bit 11 +#define reg_marb_rw_stop_mask___iop___lsb 12 +#define reg_marb_rw_stop_mask___iop___width 1 +#define reg_marb_rw_stop_mask___iop___bit 12 +#define reg_marb_rw_stop_mask___slave___lsb 13 +#define reg_marb_rw_stop_mask___slave___width 1 +#define reg_marb_rw_stop_mask___slave___bit 13 +#define reg_marb_rw_stop_mask_offset 544 + +/* Register r_stopped, scope marb, type r */ +#define reg_marb_r_stopped___dma0___lsb 0 +#define reg_marb_r_stopped___dma0___width 1 +#define reg_marb_r_stopped___dma0___bit 0 +#define reg_marb_r_stopped___dma1___lsb 1 +#define reg_marb_r_stopped___dma1___width 1 +#define reg_marb_r_stopped___dma1___bit 1 +#define reg_marb_r_stopped___dma2___lsb 2 +#define reg_marb_r_stopped___dma2___width 1 +#define reg_marb_r_stopped___dma2___bit 2 +#define reg_marb_r_stopped___dma3___lsb 3 +#define reg_marb_r_stopped___dma3___width 1 +#define reg_marb_r_stopped___dma3___bit 3 +#define reg_marb_r_stopped___dma4___lsb 4 +#define reg_marb_r_stopped___dma4___width 1 +#define reg_marb_r_stopped___dma4___bit 4 +#define reg_marb_r_stopped___dma5___lsb 5 +#define reg_marb_r_stopped___dma5___width 1 +#define reg_marb_r_stopped___dma5___bit 5 +#define reg_marb_r_stopped___dma6___lsb 6 +#define reg_marb_r_stopped___dma6___width 1 +#define reg_marb_r_stopped___dma6___bit 6 +#define reg_marb_r_stopped___dma7___lsb 7 +#define reg_marb_r_stopped___dma7___width 1 +#define reg_marb_r_stopped___dma7___bit 7 +#define reg_marb_r_stopped___dma8___lsb 8 +#define reg_marb_r_stopped___dma8___width 1 +#define reg_marb_r_stopped___dma8___bit 8 +#define reg_marb_r_stopped___dma9___lsb 9 +#define reg_marb_r_stopped___dma9___width 1 +#define reg_marb_r_stopped___dma9___bit 9 +#define reg_marb_r_stopped___cpui___lsb 10 +#define reg_marb_r_stopped___cpui___width 1 +#define reg_marb_r_stopped___cpui___bit 10 +#define reg_marb_r_stopped___cpud___lsb 11 +#define reg_marb_r_stopped___cpud___width 1 +#define reg_marb_r_stopped___cpud___bit 11 +#define reg_marb_r_stopped___iop___lsb 12 +#define reg_marb_r_stopped___iop___width 1 +#define reg_marb_r_stopped___iop___bit 12 +#define reg_marb_r_stopped___slave___lsb 13 +#define reg_marb_r_stopped___slave___width 1 +#define reg_marb_r_stopped___slave___bit 13 +#define reg_marb_r_stopped_offset 548 + +/* Register rw_no_snoop, scope marb, type rw */ +#define reg_marb_rw_no_snoop___dma0___lsb 0 +#define reg_marb_rw_no_snoop___dma0___width 1 +#define reg_marb_rw_no_snoop___dma0___bit 0 +#define reg_marb_rw_no_snoop___dma1___lsb 1 +#define reg_marb_rw_no_snoop___dma1___width 1 +#define reg_marb_rw_no_snoop___dma1___bit 1 +#define reg_marb_rw_no_snoop___dma2___lsb 2 +#define reg_marb_rw_no_snoop___dma2___width 1 +#define reg_marb_rw_no_snoop___dma2___bit 2 +#define reg_marb_rw_no_snoop___dma3___lsb 3 +#define reg_marb_rw_no_snoop___dma3___width 1 +#define reg_marb_rw_no_snoop___dma3___bit 3 +#define reg_marb_rw_no_snoop___dma4___lsb 4 +#define reg_marb_rw_no_snoop___dma4___width 1 +#define reg_marb_rw_no_snoop___dma4___bit 4 +#define reg_marb_rw_no_snoop___dma5___lsb 5 +#define reg_marb_rw_no_snoop___dma5___width 1 +#define reg_marb_rw_no_snoop___dma5___bit 5 +#define reg_marb_rw_no_snoop___dma6___lsb 6 +#define reg_marb_rw_no_snoop___dma6___width 1 +#define reg_marb_rw_no_snoop___dma6___bit 6 +#define reg_marb_rw_no_snoop___dma7___lsb 7 +#define reg_marb_rw_no_snoop___dma7___width 1 +#define reg_marb_rw_no_snoop___dma7___bit 7 +#define reg_marb_rw_no_snoop___dma8___lsb 8 +#define reg_marb_rw_no_snoop___dma8___width 1 +#define reg_marb_rw_no_snoop___dma8___bit 8 +#define reg_marb_rw_no_snoop___dma9___lsb 9 +#define reg_marb_rw_no_snoop___dma9___width 1 +#define reg_marb_rw_no_snoop___dma9___bit 9 +#define reg_marb_rw_no_snoop___cpui___lsb 10 +#define reg_marb_rw_no_snoop___cpui___width 1 +#define reg_marb_rw_no_snoop___cpui___bit 10 +#define reg_marb_rw_no_snoop___cpud___lsb 11 +#define reg_marb_rw_no_snoop___cpud___width 1 +#define reg_marb_rw_no_snoop___cpud___bit 11 +#define reg_marb_rw_no_snoop___iop___lsb 12 +#define reg_marb_rw_no_snoop___iop___width 1 +#define reg_marb_rw_no_snoop___iop___bit 12 +#define reg_marb_rw_no_snoop___slave___lsb 13 +#define reg_marb_rw_no_snoop___slave___width 1 +#define reg_marb_rw_no_snoop___slave___bit 13 +#define reg_marb_rw_no_snoop_offset 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 +#define reg_marb_rw_no_snoop_rq___cpui___width 1 +#define reg_marb_rw_no_snoop_rq___cpui___bit 10 +#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 +#define reg_marb_rw_no_snoop_rq___cpud___width 1 +#define reg_marb_rw_no_snoop_rq___cpud___bit 11 +#define reg_marb_rw_no_snoop_rq_offset 836 + + +/* Constants */ +#define regk_marb_cpud 0x0000000b +#define regk_marb_cpui 0x0000000a +#define regk_marb_dma0 0x00000000 +#define regk_marb_dma1 0x00000001 +#define regk_marb_dma2 0x00000002 +#define regk_marb_dma3 0x00000003 +#define regk_marb_dma4 0x00000004 +#define regk_marb_dma5 0x00000005 +#define regk_marb_dma6 0x00000006 +#define regk_marb_dma7 0x00000007 +#define regk_marb_dma8 0x00000008 +#define regk_marb_dma9 0x00000009 +#define regk_marb_iop 0x0000000c +#define regk_marb_no 0x00000000 +#define regk_marb_r_stopped_default 0x00000000 +#define regk_marb_rw_ext_slots_default 0x00000000 +#define regk_marb_rw_ext_slots_size 0x00000040 +#define regk_marb_rw_int_slots_default 0x00000000 +#define regk_marb_rw_int_slots_size 0x00000040 +#define regk_marb_rw_intr_mask_default 0x00000000 +#define regk_marb_rw_no_snoop_default 0x00000000 +#define regk_marb_rw_no_snoop_rq_default 0x00000000 +#define regk_marb_rw_regs_slots_default 0x00000000 +#define regk_marb_rw_regs_slots_size 0x00000004 +#define regk_marb_rw_stop_mask_default 0x00000000 +#define regk_marb_slave 0x0000000d +#define regk_marb_yes 0x00000001 +#endif /* __marb_defs_asm_h */ +#ifndef __marb_bp_defs_asm_h +#define __marb_bp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_first_addr, scope marb_bp, type rw */ +#define reg_marb_bp_rw_first_addr_offset 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +#define reg_marb_bp_rw_last_addr_offset 4 + +/* Register rw_op, scope marb_bp, type rw */ +#define reg_marb_bp_rw_op___rd___lsb 0 +#define reg_marb_bp_rw_op___rd___width 1 +#define reg_marb_bp_rw_op___rd___bit 0 +#define reg_marb_bp_rw_op___wr___lsb 1 +#define reg_marb_bp_rw_op___wr___width 1 +#define reg_marb_bp_rw_op___wr___bit 1 +#define reg_marb_bp_rw_op___rd_excl___lsb 2 +#define reg_marb_bp_rw_op___rd_excl___width 1 +#define reg_marb_bp_rw_op___rd_excl___bit 2 +#define reg_marb_bp_rw_op___pri_wr___lsb 3 +#define reg_marb_bp_rw_op___pri_wr___width 1 +#define reg_marb_bp_rw_op___pri_wr___bit 3 +#define reg_marb_bp_rw_op___us_rd___lsb 4 +#define reg_marb_bp_rw_op___us_rd___width 1 +#define reg_marb_bp_rw_op___us_rd___bit 4 +#define reg_marb_bp_rw_op___us_wr___lsb 5 +#define reg_marb_bp_rw_op___us_wr___width 1 +#define reg_marb_bp_rw_op___us_wr___bit 5 +#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 +#define reg_marb_bp_rw_op___us_rd_excl___width 1 +#define reg_marb_bp_rw_op___us_rd_excl___bit 6 +#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 +#define reg_marb_bp_rw_op___us_pri_wr___width 1 +#define reg_marb_bp_rw_op___us_pri_wr___bit 7 +#define reg_marb_bp_rw_op_offset 8 + +/* Register rw_clients, scope marb_bp, type rw */ +#define reg_marb_bp_rw_clients___dma0___lsb 0 +#define reg_marb_bp_rw_clients___dma0___width 1 +#define reg_marb_bp_rw_clients___dma0___bit 0 +#define reg_marb_bp_rw_clients___dma1___lsb 1 +#define reg_marb_bp_rw_clients___dma1___width 1 +#define reg_marb_bp_rw_clients___dma1___bit 1 +#define reg_marb_bp_rw_clients___dma2___lsb 2 +#define reg_marb_bp_rw_clients___dma2___width 1 +#define reg_marb_bp_rw_clients___dma2___bit 2 +#define reg_marb_bp_rw_clients___dma3___lsb 3 +#define reg_marb_bp_rw_clients___dma3___width 1 +#define reg_marb_bp_rw_clients___dma3___bit 3 +#define reg_marb_bp_rw_clients___dma4___lsb 4 +#define reg_marb_bp_rw_clients___dma4___width 1 +#define reg_marb_bp_rw_clients___dma4___bit 4 +#define reg_marb_bp_rw_clients___dma5___lsb 5 +#define reg_marb_bp_rw_clients___dma5___width 1 +#define reg_marb_bp_rw_clients___dma5___bit 5 +#define reg_marb_bp_rw_clients___dma6___lsb 6 +#define reg_marb_bp_rw_clients___dma6___width 1 +#define reg_marb_bp_rw_clients___dma6___bit 6 +#define reg_marb_bp_rw_clients___dma7___lsb 7 +#define reg_marb_bp_rw_clients___dma7___width 1 +#define reg_marb_bp_rw_clients___dma7___bit 7 +#define reg_marb_bp_rw_clients___dma8___lsb 8 +#define reg_marb_bp_rw_clients___dma8___width 1 +#define reg_marb_bp_rw_clients___dma8___bit 8 +#define reg_marb_bp_rw_clients___dma9___lsb 9 +#define reg_marb_bp_rw_clients___dma9___width 1 +#define reg_marb_bp_rw_clients___dma9___bit 9 +#define reg_marb_bp_rw_clients___cpui___lsb 10 +#define reg_marb_bp_rw_clients___cpui___width 1 +#define reg_marb_bp_rw_clients___cpui___bit 10 +#define reg_marb_bp_rw_clients___cpud___lsb 11 +#define reg_marb_bp_rw_clients___cpud___width 1 +#define reg_marb_bp_rw_clients___cpud___bit 11 +#define reg_marb_bp_rw_clients___iop___lsb 12 +#define reg_marb_bp_rw_clients___iop___width 1 +#define reg_marb_bp_rw_clients___iop___bit 12 +#define reg_marb_bp_rw_clients___slave___lsb 13 +#define reg_marb_bp_rw_clients___slave___width 1 +#define reg_marb_bp_rw_clients___slave___bit 13 +#define reg_marb_bp_rw_clients_offset 12 + +/* Register rw_options, scope marb_bp, type rw */ +#define reg_marb_bp_rw_options___wrap___lsb 0 +#define reg_marb_bp_rw_options___wrap___width 1 +#define reg_marb_bp_rw_options___wrap___bit 0 +#define reg_marb_bp_rw_options_offset 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_addr_offset 20 + +/* Register r_brk_op, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_op___rd___lsb 0 +#define reg_marb_bp_r_brk_op___rd___width 1 +#define reg_marb_bp_r_brk_op___rd___bit 0 +#define reg_marb_bp_r_brk_op___wr___lsb 1 +#define reg_marb_bp_r_brk_op___wr___width 1 +#define reg_marb_bp_r_brk_op___wr___bit 1 +#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 +#define reg_marb_bp_r_brk_op___rd_excl___width 1 +#define reg_marb_bp_r_brk_op___rd_excl___bit 2 +#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 +#define reg_marb_bp_r_brk_op___pri_wr___width 1 +#define reg_marb_bp_r_brk_op___pri_wr___bit 3 +#define reg_marb_bp_r_brk_op___us_rd___lsb 4 +#define reg_marb_bp_r_brk_op___us_rd___width 1 +#define reg_marb_bp_r_brk_op___us_rd___bit 4 +#define reg_marb_bp_r_brk_op___us_wr___lsb 5 +#define reg_marb_bp_r_brk_op___us_wr___width 1 +#define reg_marb_bp_r_brk_op___us_wr___bit 5 +#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 +#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 +#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 +#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 +#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 +#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 +#define reg_marb_bp_r_brk_op_offset 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_clients___dma0___lsb 0 +#define reg_marb_bp_r_brk_clients___dma0___width 1 +#define reg_marb_bp_r_brk_clients___dma0___bit 0 +#define reg_marb_bp_r_brk_clients___dma1___lsb 1 +#define reg_marb_bp_r_brk_clients___dma1___width 1 +#define reg_marb_bp_r_brk_clients___dma1___bit 1 +#define reg_marb_bp_r_brk_clients___dma2___lsb 2 +#define reg_marb_bp_r_brk_clients___dma2___width 1 +#define reg_marb_bp_r_brk_clients___dma2___bit 2 +#define reg_marb_bp_r_brk_clients___dma3___lsb 3 +#define reg_marb_bp_r_brk_clients___dma3___width 1 +#define reg_marb_bp_r_brk_clients___dma3___bit 3 +#define reg_marb_bp_r_brk_clients___dma4___lsb 4 +#define reg_marb_bp_r_brk_clients___dma4___width 1 +#define reg_marb_bp_r_brk_clients___dma4___bit 4 +#define reg_marb_bp_r_brk_clients___dma5___lsb 5 +#define reg_marb_bp_r_brk_clients___dma5___width 1 +#define reg_marb_bp_r_brk_clients___dma5___bit 5 +#define reg_marb_bp_r_brk_clients___dma6___lsb 6 +#define reg_marb_bp_r_brk_clients___dma6___width 1 +#define reg_marb_bp_r_brk_clients___dma6___bit 6 +#define reg_marb_bp_r_brk_clients___dma7___lsb 7 +#define reg_marb_bp_r_brk_clients___dma7___width 1 +#define reg_marb_bp_r_brk_clients___dma7___bit 7 +#define reg_marb_bp_r_brk_clients___dma8___lsb 8 +#define reg_marb_bp_r_brk_clients___dma8___width 1 +#define reg_marb_bp_r_brk_clients___dma8___bit 8 +#define reg_marb_bp_r_brk_clients___dma9___lsb 9 +#define reg_marb_bp_r_brk_clients___dma9___width 1 +#define reg_marb_bp_r_brk_clients___dma9___bit 9 +#define reg_marb_bp_r_brk_clients___cpui___lsb 10 +#define reg_marb_bp_r_brk_clients___cpui___width 1 +#define reg_marb_bp_r_brk_clients___cpui___bit 10 +#define reg_marb_bp_r_brk_clients___cpud___lsb 11 +#define reg_marb_bp_r_brk_clients___cpud___width 1 +#define reg_marb_bp_r_brk_clients___cpud___bit 11 +#define reg_marb_bp_r_brk_clients___iop___lsb 12 +#define reg_marb_bp_r_brk_clients___iop___width 1 +#define reg_marb_bp_r_brk_clients___iop___bit 12 +#define reg_marb_bp_r_brk_clients___slave___lsb 13 +#define reg_marb_bp_r_brk_clients___slave___width 1 +#define reg_marb_bp_r_brk_clients___slave___bit 13 +#define reg_marb_bp_r_brk_clients_offset 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 +#define reg_marb_bp_r_brk_first_client___dma0___width 1 +#define reg_marb_bp_r_brk_first_client___dma0___bit 0 +#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 +#define reg_marb_bp_r_brk_first_client___dma1___width 1 +#define reg_marb_bp_r_brk_first_client___dma1___bit 1 +#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 +#define reg_marb_bp_r_brk_first_client___dma2___width 1 +#define reg_marb_bp_r_brk_first_client___dma2___bit 2 +#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 +#define reg_marb_bp_r_brk_first_client___dma3___width 1 +#define reg_marb_bp_r_brk_first_client___dma3___bit 3 +#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 +#define reg_marb_bp_r_brk_first_client___dma4___width 1 +#define reg_marb_bp_r_brk_first_client___dma4___bit 4 +#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 +#define reg_marb_bp_r_brk_first_client___dma5___width 1 +#define reg_marb_bp_r_brk_first_client___dma5___bit 5 +#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 +#define reg_marb_bp_r_brk_first_client___dma6___width 1 +#define reg_marb_bp_r_brk_first_client___dma6___bit 6 +#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 +#define reg_marb_bp_r_brk_first_client___dma7___width 1 +#define reg_marb_bp_r_brk_first_client___dma7___bit 7 +#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 +#define reg_marb_bp_r_brk_first_client___dma8___width 1 +#define reg_marb_bp_r_brk_first_client___dma8___bit 8 +#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 +#define reg_marb_bp_r_brk_first_client___dma9___width 1 +#define reg_marb_bp_r_brk_first_client___dma9___bit 9 +#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 +#define reg_marb_bp_r_brk_first_client___cpui___width 1 +#define reg_marb_bp_r_brk_first_client___cpui___bit 10 +#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 +#define reg_marb_bp_r_brk_first_client___cpud___width 1 +#define reg_marb_bp_r_brk_first_client___cpud___bit 11 +#define reg_marb_bp_r_brk_first_client___iop___lsb 12 +#define reg_marb_bp_r_brk_first_client___iop___width 1 +#define reg_marb_bp_r_brk_first_client___iop___bit 12 +#define reg_marb_bp_r_brk_first_client___slave___lsb 13 +#define reg_marb_bp_r_brk_first_client___slave___width 1 +#define reg_marb_bp_r_brk_first_client___slave___bit 13 +#define reg_marb_bp_r_brk_first_client_offset 32 + +/* Register r_brk_size, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_size_offset 36 + +/* Register rw_ack, scope marb_bp, type rw */ +#define reg_marb_bp_rw_ack_offset 40 + + +/* Constants */ +#define regk_marb_bp_no 0x00000000 +#define regk_marb_bp_rw_op_default 0x00000000 +#define regk_marb_bp_rw_options_default 0x00000000 +#define regk_marb_bp_yes 0x00000001 +#endif /* __marb_bp_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h new file mode 100644 index 000000000000..505b7a16d878 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h @@ -0,0 +1,212 @@ +#ifndef __mmu_defs_asm_h +#define __mmu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/mmu/doc/mmu_regs.r + * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp + * last modfied: Mon Apr 11 17:03:20 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r + * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mm_cfg, scope mmu, type rw */ +#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 +#define reg_mmu_rw_mm_cfg___seg_0___width 1 +#define reg_mmu_rw_mm_cfg___seg_0___bit 0 +#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 +#define reg_mmu_rw_mm_cfg___seg_1___width 1 +#define reg_mmu_rw_mm_cfg___seg_1___bit 1 +#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 +#define reg_mmu_rw_mm_cfg___seg_2___width 1 +#define reg_mmu_rw_mm_cfg___seg_2___bit 2 +#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 +#define reg_mmu_rw_mm_cfg___seg_3___width 1 +#define reg_mmu_rw_mm_cfg___seg_3___bit 3 +#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 +#define reg_mmu_rw_mm_cfg___seg_4___width 1 +#define reg_mmu_rw_mm_cfg___seg_4___bit 4 +#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 +#define reg_mmu_rw_mm_cfg___seg_5___width 1 +#define reg_mmu_rw_mm_cfg___seg_5___bit 5 +#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 +#define reg_mmu_rw_mm_cfg___seg_6___width 1 +#define reg_mmu_rw_mm_cfg___seg_6___bit 6 +#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 +#define reg_mmu_rw_mm_cfg___seg_7___width 1 +#define reg_mmu_rw_mm_cfg___seg_7___bit 7 +#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 +#define reg_mmu_rw_mm_cfg___seg_8___width 1 +#define reg_mmu_rw_mm_cfg___seg_8___bit 8 +#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 +#define reg_mmu_rw_mm_cfg___seg_9___width 1 +#define reg_mmu_rw_mm_cfg___seg_9___bit 9 +#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 +#define reg_mmu_rw_mm_cfg___seg_a___width 1 +#define reg_mmu_rw_mm_cfg___seg_a___bit 10 +#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 +#define reg_mmu_rw_mm_cfg___seg_b___width 1 +#define reg_mmu_rw_mm_cfg___seg_b___bit 11 +#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 +#define reg_mmu_rw_mm_cfg___seg_c___width 1 +#define reg_mmu_rw_mm_cfg___seg_c___bit 12 +#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 +#define reg_mmu_rw_mm_cfg___seg_d___width 1 +#define reg_mmu_rw_mm_cfg___seg_d___bit 13 +#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 +#define reg_mmu_rw_mm_cfg___seg_e___width 1 +#define reg_mmu_rw_mm_cfg___seg_e___bit 14 +#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 +#define reg_mmu_rw_mm_cfg___seg_f___width 1 +#define reg_mmu_rw_mm_cfg___seg_f___bit 15 +#define reg_mmu_rw_mm_cfg___inv___lsb 16 +#define reg_mmu_rw_mm_cfg___inv___width 1 +#define reg_mmu_rw_mm_cfg___inv___bit 16 +#define reg_mmu_rw_mm_cfg___ex___lsb 17 +#define reg_mmu_rw_mm_cfg___ex___width 1 +#define reg_mmu_rw_mm_cfg___ex___bit 17 +#define reg_mmu_rw_mm_cfg___acc___lsb 18 +#define reg_mmu_rw_mm_cfg___acc___width 1 +#define reg_mmu_rw_mm_cfg___acc___bit 18 +#define reg_mmu_rw_mm_cfg___we___lsb 19 +#define reg_mmu_rw_mm_cfg___we___width 1 +#define reg_mmu_rw_mm_cfg___we___bit 19 +#define reg_mmu_rw_mm_cfg_offset 0 + +/* Register rw_mm_kbase_lo, scope mmu, type rw */ +#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 +#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 +#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 +#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 +#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 +#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 +#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 +#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 +#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 +#define reg_mmu_rw_mm_kbase_lo_offset 4 + +/* Register rw_mm_kbase_hi, scope mmu, type rw */ +#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 +#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 +#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 +#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 +#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 +#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 +#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 +#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 +#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 +#define reg_mmu_rw_mm_kbase_hi_offset 8 + +/* Register r_mm_cause, scope mmu, type r */ +#define reg_mmu_r_mm_cause___pid___lsb 0 +#define reg_mmu_r_mm_cause___pid___width 8 +#define reg_mmu_r_mm_cause___op___lsb 8 +#define reg_mmu_r_mm_cause___op___width 2 +#define reg_mmu_r_mm_cause___vpn___lsb 13 +#define reg_mmu_r_mm_cause___vpn___width 19 +#define reg_mmu_r_mm_cause_offset 12 + +/* Register rw_mm_tlb_sel, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 +#define reg_mmu_rw_mm_tlb_sel___idx___width 4 +#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 +#define reg_mmu_rw_mm_tlb_sel___set___width 2 +#define reg_mmu_rw_mm_tlb_sel_offset 16 + +/* Register rw_mm_tlb_lo, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 +#define reg_mmu_rw_mm_tlb_lo___x___width 1 +#define reg_mmu_rw_mm_tlb_lo___x___bit 0 +#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 +#define reg_mmu_rw_mm_tlb_lo___w___width 1 +#define reg_mmu_rw_mm_tlb_lo___w___bit 1 +#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 +#define reg_mmu_rw_mm_tlb_lo___k___width 1 +#define reg_mmu_rw_mm_tlb_lo___k___bit 2 +#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 +#define reg_mmu_rw_mm_tlb_lo___v___width 1 +#define reg_mmu_rw_mm_tlb_lo___v___bit 3 +#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 +#define reg_mmu_rw_mm_tlb_lo___g___width 1 +#define reg_mmu_rw_mm_tlb_lo___g___bit 4 +#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 +#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 +#define reg_mmu_rw_mm_tlb_lo_offset 20 + +/* Register rw_mm_tlb_hi, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 +#define reg_mmu_rw_mm_tlb_hi___pid___width 8 +#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 +#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 +#define reg_mmu_rw_mm_tlb_hi_offset 24 + + +/* Constants */ +#define regk_mmu_execute 0x00000000 +#define regk_mmu_flush 0x00000003 +#define regk_mmu_linear 0x00000001 +#define regk_mmu_no 0x00000000 +#define regk_mmu_off 0x00000000 +#define regk_mmu_on 0x00000001 +#define regk_mmu_page 0x00000000 +#define regk_mmu_read 0x00000001 +#define regk_mmu_write 0x00000002 +#define regk_mmu_yes 0x00000001 +#endif /* __mmu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h new file mode 100644 index 000000000000..339500bf3bc0 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h @@ -0,0 +1,7 @@ +#define RW_MM_CFG 0 +#define RW_MM_KBASE_LO 1 +#define RW_MM_KBASE_HI 2 +#define R_MM_CAUSE 3 +#define RW_MM_TLB_SEL 4 +#define RW_MM_TLB_LO 5 +#define RW_MM_TLB_HI 6 diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h new file mode 100644 index 000000000000..10246f49fb28 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h @@ -0,0 +1,142 @@ +#ifndef __rt_trace_defs_asm_h +#define __rt_trace_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/rt_trace/rtl/rt_regs.r + * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp + * last modfied: Mon Apr 11 16:09:14 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r + * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope rt_trace, type rw */ +#define reg_rt_trace_rw_cfg___en___lsb 0 +#define reg_rt_trace_rw_cfg___en___width 1 +#define reg_rt_trace_rw_cfg___en___bit 0 +#define reg_rt_trace_rw_cfg___mode___lsb 1 +#define reg_rt_trace_rw_cfg___mode___width 1 +#define reg_rt_trace_rw_cfg___mode___bit 1 +#define reg_rt_trace_rw_cfg___owner___lsb 2 +#define reg_rt_trace_rw_cfg___owner___width 1 +#define reg_rt_trace_rw_cfg___owner___bit 2 +#define reg_rt_trace_rw_cfg___wp___lsb 3 +#define reg_rt_trace_rw_cfg___wp___width 1 +#define reg_rt_trace_rw_cfg___wp___bit 3 +#define reg_rt_trace_rw_cfg___stall___lsb 4 +#define reg_rt_trace_rw_cfg___stall___width 1 +#define reg_rt_trace_rw_cfg___stall___bit 4 +#define reg_rt_trace_rw_cfg___wp_start___lsb 8 +#define reg_rt_trace_rw_cfg___wp_start___width 7 +#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 +#define reg_rt_trace_rw_cfg___wp_stop___width 7 +#define reg_rt_trace_rw_cfg_offset 0 + +/* Register rw_tap_ctrl, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 +#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 +#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 +#define reg_rt_trace_rw_tap_ctrl_offset 4 + +/* Register r_tap_stat, scope rt_trace, type r */ +#define reg_rt_trace_r_tap_stat___dav___lsb 0 +#define reg_rt_trace_r_tap_stat___dav___width 1 +#define reg_rt_trace_r_tap_stat___dav___bit 0 +#define reg_rt_trace_r_tap_stat___empty___lsb 1 +#define reg_rt_trace_r_tap_stat___empty___width 1 +#define reg_rt_trace_r_tap_stat___empty___bit 1 +#define reg_rt_trace_r_tap_stat_offset 8 + +/* Register rw_tap_data, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_data_offset 12 + +/* Register rw_tap_hdata, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_hdata___op___lsb 0 +#define reg_rt_trace_rw_tap_hdata___op___width 4 +#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 +#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 +#define reg_rt_trace_rw_tap_hdata_offset 16 + +/* Register r_redir, scope rt_trace, type r */ +#define reg_rt_trace_r_redir_offset 20 + + +/* Constants */ +#define regk_rt_trace_brk 0x0000000c +#define regk_rt_trace_dbg 0x00000003 +#define regk_rt_trace_dbgdi 0x00000004 +#define regk_rt_trace_dbgdo 0x00000005 +#define regk_rt_trace_gmode 0x00000000 +#define regk_rt_trace_no 0x00000000 +#define regk_rt_trace_nop 0x00000000 +#define regk_rt_trace_normal 0x00000000 +#define regk_rt_trace_rdmem 0x00000007 +#define regk_rt_trace_rdmemb 0x00000009 +#define regk_rt_trace_rdpreg 0x00000002 +#define regk_rt_trace_rdreg 0x00000001 +#define regk_rt_trace_rdsreg 0x00000003 +#define regk_rt_trace_redir 0x00000006 +#define regk_rt_trace_ret 0x0000000b +#define regk_rt_trace_rw_cfg_default 0x00000000 +#define regk_rt_trace_trcfg 0x00000001 +#define regk_rt_trace_wp 0x00000001 +#define regk_rt_trace_wp0 0x00000001 +#define regk_rt_trace_wp1 0x00000002 +#define regk_rt_trace_wp2 0x00000004 +#define regk_rt_trace_wp3 0x00000008 +#define regk_rt_trace_wp4 0x00000010 +#define regk_rt_trace_wp5 0x00000020 +#define regk_rt_trace_wp6 0x00000040 +#define regk_rt_trace_wrmem 0x00000008 +#define regk_rt_trace_wrmemb 0x0000000a +#define regk_rt_trace_wrpreg 0x00000005 +#define regk_rt_trace_wrreg 0x00000004 +#define regk_rt_trace_wrsreg 0x00000006 +#define regk_rt_trace_yes 0x00000001 +#endif /* __rt_trace_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h new file mode 100644 index 000000000000..4a2808bdf390 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h @@ -0,0 +1,359 @@ +#ifndef __ser_defs_asm_h +#define __ser_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/ser/rtl/ser_regs.r + * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp + * last modfied: Mon Apr 11 16:09:21 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r + * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tr_ctrl, scope ser, type rw */ +#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 +#define reg_ser_rw_tr_ctrl___base_freq___width 3 +#define reg_ser_rw_tr_ctrl___en___lsb 3 +#define reg_ser_rw_tr_ctrl___en___width 1 +#define reg_ser_rw_tr_ctrl___en___bit 3 +#define reg_ser_rw_tr_ctrl___par___lsb 4 +#define reg_ser_rw_tr_ctrl___par___width 2 +#define reg_ser_rw_tr_ctrl___par_en___lsb 6 +#define reg_ser_rw_tr_ctrl___par_en___width 1 +#define reg_ser_rw_tr_ctrl___par_en___bit 6 +#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 +#define reg_ser_rw_tr_ctrl___data_bits___width 1 +#define reg_ser_rw_tr_ctrl___data_bits___bit 7 +#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 +#define reg_ser_rw_tr_ctrl___stop_bits___width 1 +#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 +#define reg_ser_rw_tr_ctrl___stop___lsb 9 +#define reg_ser_rw_tr_ctrl___stop___width 1 +#define reg_ser_rw_tr_ctrl___stop___bit 9 +#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 +#define reg_ser_rw_tr_ctrl___rts_delay___width 3 +#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 +#define reg_ser_rw_tr_ctrl___rts_setup___width 1 +#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 +#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 +#define reg_ser_rw_tr_ctrl___auto_rts___width 1 +#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 +#define reg_ser_rw_tr_ctrl___txd___lsb 15 +#define reg_ser_rw_tr_ctrl___txd___width 1 +#define reg_ser_rw_tr_ctrl___txd___bit 15 +#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 +#define reg_ser_rw_tr_ctrl___auto_cts___width 1 +#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 +#define reg_ser_rw_tr_ctrl_offset 0 + +/* Register rw_tr_dma_en, scope ser, type rw */ +#define reg_ser_rw_tr_dma_en___en___lsb 0 +#define reg_ser_rw_tr_dma_en___en___width 1 +#define reg_ser_rw_tr_dma_en___en___bit 0 +#define reg_ser_rw_tr_dma_en_offset 4 + +/* Register rw_rec_ctrl, scope ser, type rw */ +#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 +#define reg_ser_rw_rec_ctrl___base_freq___width 3 +#define reg_ser_rw_rec_ctrl___en___lsb 3 +#define reg_ser_rw_rec_ctrl___en___width 1 +#define reg_ser_rw_rec_ctrl___en___bit 3 +#define reg_ser_rw_rec_ctrl___par___lsb 4 +#define reg_ser_rw_rec_ctrl___par___width 2 +#define reg_ser_rw_rec_ctrl___par_en___lsb 6 +#define reg_ser_rw_rec_ctrl___par_en___width 1 +#define reg_ser_rw_rec_ctrl___par_en___bit 6 +#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 +#define reg_ser_rw_rec_ctrl___data_bits___width 1 +#define reg_ser_rw_rec_ctrl___data_bits___bit 7 +#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 +#define reg_ser_rw_rec_ctrl___dma_mode___width 1 +#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 +#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 +#define reg_ser_rw_rec_ctrl___dma_err___width 1 +#define reg_ser_rw_rec_ctrl___dma_err___bit 9 +#define reg_ser_rw_rec_ctrl___sampling___lsb 10 +#define reg_ser_rw_rec_ctrl___sampling___width 1 +#define reg_ser_rw_rec_ctrl___sampling___bit 10 +#define reg_ser_rw_rec_ctrl___timeout___lsb 11 +#define reg_ser_rw_rec_ctrl___timeout___width 3 +#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 +#define reg_ser_rw_rec_ctrl___auto_eop___width 1 +#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 +#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 +#define reg_ser_rw_rec_ctrl___half_duplex___width 1 +#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 +#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 +#define reg_ser_rw_rec_ctrl___rts_n___width 1 +#define reg_ser_rw_rec_ctrl___rts_n___bit 16 +#define reg_ser_rw_rec_ctrl___loopback___lsb 17 +#define reg_ser_rw_rec_ctrl___loopback___width 1 +#define reg_ser_rw_rec_ctrl___loopback___bit 17 +#define reg_ser_rw_rec_ctrl_offset 8 + +/* Register rw_tr_baud_div, scope ser, type rw */ +#define reg_ser_rw_tr_baud_div___div___lsb 0 +#define reg_ser_rw_tr_baud_div___div___width 16 +#define reg_ser_rw_tr_baud_div_offset 12 + +/* Register rw_rec_baud_div, scope ser, type rw */ +#define reg_ser_rw_rec_baud_div___div___lsb 0 +#define reg_ser_rw_rec_baud_div___div___width 16 +#define reg_ser_rw_rec_baud_div_offset 16 + +/* Register rw_xoff, scope ser, type rw */ +#define reg_ser_rw_xoff___chr___lsb 0 +#define reg_ser_rw_xoff___chr___width 8 +#define reg_ser_rw_xoff___automatic___lsb 8 +#define reg_ser_rw_xoff___automatic___width 1 +#define reg_ser_rw_xoff___automatic___bit 8 +#define reg_ser_rw_xoff_offset 20 + +/* Register rw_xoff_clr, scope ser, type rw */ +#define reg_ser_rw_xoff_clr___clr___lsb 0 +#define reg_ser_rw_xoff_clr___clr___width 1 +#define reg_ser_rw_xoff_clr___clr___bit 0 +#define reg_ser_rw_xoff_clr_offset 24 + +/* Register rw_dout, scope ser, type rw */ +#define reg_ser_rw_dout___data___lsb 0 +#define reg_ser_rw_dout___data___width 8 +#define reg_ser_rw_dout_offset 28 + +/* Register rs_stat_din, scope ser, type rs */ +#define reg_ser_rs_stat_din___data___lsb 0 +#define reg_ser_rs_stat_din___data___width 8 +#define reg_ser_rs_stat_din___dav___lsb 16 +#define reg_ser_rs_stat_din___dav___width 1 +#define reg_ser_rs_stat_din___dav___bit 16 +#define reg_ser_rs_stat_din___framing_err___lsb 17 +#define reg_ser_rs_stat_din___framing_err___width 1 +#define reg_ser_rs_stat_din___framing_err___bit 17 +#define reg_ser_rs_stat_din___par_err___lsb 18 +#define reg_ser_rs_stat_din___par_err___width 1 +#define reg_ser_rs_stat_din___par_err___bit 18 +#define reg_ser_rs_stat_din___orun___lsb 19 +#define reg_ser_rs_stat_din___orun___width 1 +#define reg_ser_rs_stat_din___orun___bit 19 +#define reg_ser_rs_stat_din___rec_err___lsb 20 +#define reg_ser_rs_stat_din___rec_err___width 1 +#define reg_ser_rs_stat_din___rec_err___bit 20 +#define reg_ser_rs_stat_din___rxd___lsb 21 +#define reg_ser_rs_stat_din___rxd___width 1 +#define reg_ser_rs_stat_din___rxd___bit 21 +#define reg_ser_rs_stat_din___tr_idle___lsb 22 +#define reg_ser_rs_stat_din___tr_idle___width 1 +#define reg_ser_rs_stat_din___tr_idle___bit 22 +#define reg_ser_rs_stat_din___tr_empty___lsb 23 +#define reg_ser_rs_stat_din___tr_empty___width 1 +#define reg_ser_rs_stat_din___tr_empty___bit 23 +#define reg_ser_rs_stat_din___tr_rdy___lsb 24 +#define reg_ser_rs_stat_din___tr_rdy___width 1 +#define reg_ser_rs_stat_din___tr_rdy___bit 24 +#define reg_ser_rs_stat_din___cts_n___lsb 25 +#define reg_ser_rs_stat_din___cts_n___width 1 +#define reg_ser_rs_stat_din___cts_n___bit 25 +#define reg_ser_rs_stat_din___xoff_detect___lsb 26 +#define reg_ser_rs_stat_din___xoff_detect___width 1 +#define reg_ser_rs_stat_din___xoff_detect___bit 26 +#define reg_ser_rs_stat_din___rts_n___lsb 27 +#define reg_ser_rs_stat_din___rts_n___width 1 +#define reg_ser_rs_stat_din___rts_n___bit 27 +#define reg_ser_rs_stat_din___txd___lsb 28 +#define reg_ser_rs_stat_din___txd___width 1 +#define reg_ser_rs_stat_din___txd___bit 28 +#define reg_ser_rs_stat_din_offset 32 + +/* Register r_stat_din, scope ser, type r */ +#define reg_ser_r_stat_din___data___lsb 0 +#define reg_ser_r_stat_din___data___width 8 +#define reg_ser_r_stat_din___dav___lsb 16 +#define reg_ser_r_stat_din___dav___width 1 +#define reg_ser_r_stat_din___dav___bit 16 +#define reg_ser_r_stat_din___framing_err___lsb 17 +#define reg_ser_r_stat_din___framing_err___width 1 +#define reg_ser_r_stat_din___framing_err___bit 17 +#define reg_ser_r_stat_din___par_err___lsb 18 +#define reg_ser_r_stat_din___par_err___width 1 +#define reg_ser_r_stat_din___par_err___bit 18 +#define reg_ser_r_stat_din___orun___lsb 19 +#define reg_ser_r_stat_din___orun___width 1 +#define reg_ser_r_stat_din___orun___bit 19 +#define reg_ser_r_stat_din___rec_err___lsb 20 +#define reg_ser_r_stat_din___rec_err___width 1 +#define reg_ser_r_stat_din___rec_err___bit 20 +#define reg_ser_r_stat_din___rxd___lsb 21 +#define reg_ser_r_stat_din___rxd___width 1 +#define reg_ser_r_stat_din___rxd___bit 21 +#define reg_ser_r_stat_din___tr_idle___lsb 22 +#define reg_ser_r_stat_din___tr_idle___width 1 +#define reg_ser_r_stat_din___tr_idle___bit 22 +#define reg_ser_r_stat_din___tr_empty___lsb 23 +#define reg_ser_r_stat_din___tr_empty___width 1 +#define reg_ser_r_stat_din___tr_empty___bit 23 +#define reg_ser_r_stat_din___tr_rdy___lsb 24 +#define reg_ser_r_stat_din___tr_rdy___width 1 +#define reg_ser_r_stat_din___tr_rdy___bit 24 +#define reg_ser_r_stat_din___cts_n___lsb 25 +#define reg_ser_r_stat_din___cts_n___width 1 +#define reg_ser_r_stat_din___cts_n___bit 25 +#define reg_ser_r_stat_din___xoff_detect___lsb 26 +#define reg_ser_r_stat_din___xoff_detect___width 1 +#define reg_ser_r_stat_din___xoff_detect___bit 26 +#define reg_ser_r_stat_din___rts_n___lsb 27 +#define reg_ser_r_stat_din___rts_n___width 1 +#define reg_ser_r_stat_din___rts_n___bit 27 +#define reg_ser_r_stat_din___txd___lsb 28 +#define reg_ser_r_stat_din___txd___width 1 +#define reg_ser_r_stat_din___txd___bit 28 +#define reg_ser_r_stat_din_offset 36 + +/* Register rw_rec_eop, scope ser, type rw */ +#define reg_ser_rw_rec_eop___set___lsb 0 +#define reg_ser_rw_rec_eop___set___width 1 +#define reg_ser_rw_rec_eop___set___bit 0 +#define reg_ser_rw_rec_eop_offset 40 + +/* Register rw_intr_mask, scope ser, type rw */ +#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 +#define reg_ser_rw_intr_mask___tr_rdy___width 1 +#define reg_ser_rw_intr_mask___tr_rdy___bit 0 +#define reg_ser_rw_intr_mask___tr_empty___lsb 1 +#define reg_ser_rw_intr_mask___tr_empty___width 1 +#define reg_ser_rw_intr_mask___tr_empty___bit 1 +#define reg_ser_rw_intr_mask___tr_idle___lsb 2 +#define reg_ser_rw_intr_mask___tr_idle___width 1 +#define reg_ser_rw_intr_mask___tr_idle___bit 2 +#define reg_ser_rw_intr_mask___dav___lsb 3 +#define reg_ser_rw_intr_mask___dav___width 1 +#define reg_ser_rw_intr_mask___dav___bit 3 +#define reg_ser_rw_intr_mask_offset 44 + +/* Register rw_ack_intr, scope ser, type rw */ +#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 +#define reg_ser_rw_ack_intr___tr_rdy___width 1 +#define reg_ser_rw_ack_intr___tr_rdy___bit 0 +#define reg_ser_rw_ack_intr___tr_empty___lsb 1 +#define reg_ser_rw_ack_intr___tr_empty___width 1 +#define reg_ser_rw_ack_intr___tr_empty___bit 1 +#define reg_ser_rw_ack_intr___tr_idle___lsb 2 +#define reg_ser_rw_ack_intr___tr_idle___width 1 +#define reg_ser_rw_ack_intr___tr_idle___bit 2 +#define reg_ser_rw_ack_intr___dav___lsb 3 +#define reg_ser_rw_ack_intr___dav___width 1 +#define reg_ser_rw_ack_intr___dav___bit 3 +#define reg_ser_rw_ack_intr_offset 48 + +/* Register r_intr, scope ser, type r */ +#define reg_ser_r_intr___tr_rdy___lsb 0 +#define reg_ser_r_intr___tr_rdy___width 1 +#define reg_ser_r_intr___tr_rdy___bit 0 +#define reg_ser_r_intr___tr_empty___lsb 1 +#define reg_ser_r_intr___tr_empty___width 1 +#define reg_ser_r_intr___tr_empty___bit 1 +#define reg_ser_r_intr___tr_idle___lsb 2 +#define reg_ser_r_intr___tr_idle___width 1 +#define reg_ser_r_intr___tr_idle___bit 2 +#define reg_ser_r_intr___dav___lsb 3 +#define reg_ser_r_intr___dav___width 1 +#define reg_ser_r_intr___dav___bit 3 +#define reg_ser_r_intr_offset 52 + +/* Register r_masked_intr, scope ser, type r */ +#define reg_ser_r_masked_intr___tr_rdy___lsb 0 +#define reg_ser_r_masked_intr___tr_rdy___width 1 +#define reg_ser_r_masked_intr___tr_rdy___bit 0 +#define reg_ser_r_masked_intr___tr_empty___lsb 1 +#define reg_ser_r_masked_intr___tr_empty___width 1 +#define reg_ser_r_masked_intr___tr_empty___bit 1 +#define reg_ser_r_masked_intr___tr_idle___lsb 2 +#define reg_ser_r_masked_intr___tr_idle___width 1 +#define reg_ser_r_masked_intr___tr_idle___bit 2 +#define reg_ser_r_masked_intr___dav___lsb 3 +#define reg_ser_r_masked_intr___dav___width 1 +#define reg_ser_r_masked_intr___dav___bit 3 +#define reg_ser_r_masked_intr_offset 56 + + +/* Constants */ +#define regk_ser_active 0x00000000 +#define regk_ser_bits1 0x00000000 +#define regk_ser_bits2 0x00000001 +#define regk_ser_bits7 0x00000001 +#define regk_ser_bits8 0x00000000 +#define regk_ser_del0_5 0x00000000 +#define regk_ser_del1 0x00000001 +#define regk_ser_del1_5 0x00000002 +#define regk_ser_del2 0x00000003 +#define regk_ser_del2_5 0x00000004 +#define regk_ser_del3 0x00000005 +#define regk_ser_del3_5 0x00000006 +#define regk_ser_del4 0x00000007 +#define regk_ser_even 0x00000000 +#define regk_ser_ext 0x00000001 +#define regk_ser_f100 0x00000007 +#define regk_ser_f29_493 0x00000004 +#define regk_ser_f32 0x00000005 +#define regk_ser_f32_768 0x00000006 +#define regk_ser_ignore 0x00000001 +#define regk_ser_inactive 0x00000001 +#define regk_ser_majority 0x00000001 +#define regk_ser_mark 0x00000002 +#define regk_ser_middle 0x00000000 +#define regk_ser_no 0x00000000 +#define regk_ser_odd 0x00000001 +#define regk_ser_off 0x00000000 +#define regk_ser_rw_intr_mask_default 0x00000000 +#define regk_ser_rw_rec_baud_div_default 0x00000000 +#define regk_ser_rw_rec_ctrl_default 0x00010000 +#define regk_ser_rw_tr_baud_div_default 0x00000000 +#define regk_ser_rw_tr_ctrl_default 0x00008000 +#define regk_ser_rw_tr_dma_en_default 0x00000000 +#define regk_ser_rw_xoff_default 0x00000000 +#define regk_ser_space 0x00000003 +#define regk_ser_stop 0x00000000 +#define regk_ser_yes 0x00000001 +#endif /* __ser_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h new file mode 100644 index 000000000000..27d4d91b3abd --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h @@ -0,0 +1,462 @@ +#ifndef __sser_defs_asm_h +#define __sser_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/syncser/rtl/sser_regs.r + * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp + * last modfied: Mon Apr 11 16:09:48 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r + * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope sser, type rw */ +#define reg_sser_rw_cfg___clk_div___lsb 0 +#define reg_sser_rw_cfg___clk_div___width 16 +#define reg_sser_rw_cfg___base_freq___lsb 16 +#define reg_sser_rw_cfg___base_freq___width 3 +#define reg_sser_rw_cfg___gate_clk___lsb 19 +#define reg_sser_rw_cfg___gate_clk___width 1 +#define reg_sser_rw_cfg___gate_clk___bit 19 +#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 +#define reg_sser_rw_cfg___clkgate_ctrl___width 1 +#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 +#define reg_sser_rw_cfg___clkgate_in___lsb 21 +#define reg_sser_rw_cfg___clkgate_in___width 1 +#define reg_sser_rw_cfg___clkgate_in___bit 21 +#define reg_sser_rw_cfg___clk_dir___lsb 22 +#define reg_sser_rw_cfg___clk_dir___width 1 +#define reg_sser_rw_cfg___clk_dir___bit 22 +#define reg_sser_rw_cfg___clk_od_mode___lsb 23 +#define reg_sser_rw_cfg___clk_od_mode___width 1 +#define reg_sser_rw_cfg___clk_od_mode___bit 23 +#define reg_sser_rw_cfg___out_clk_pol___lsb 24 +#define reg_sser_rw_cfg___out_clk_pol___width 1 +#define reg_sser_rw_cfg___out_clk_pol___bit 24 +#define reg_sser_rw_cfg___out_clk_src___lsb 25 +#define reg_sser_rw_cfg___out_clk_src___width 2 +#define reg_sser_rw_cfg___clk_in_sel___lsb 27 +#define reg_sser_rw_cfg___clk_in_sel___width 1 +#define reg_sser_rw_cfg___clk_in_sel___bit 27 +#define reg_sser_rw_cfg___hold_pol___lsb 28 +#define reg_sser_rw_cfg___hold_pol___width 1 +#define reg_sser_rw_cfg___hold_pol___bit 28 +#define reg_sser_rw_cfg___prepare___lsb 29 +#define reg_sser_rw_cfg___prepare___width 1 +#define reg_sser_rw_cfg___prepare___bit 29 +#define reg_sser_rw_cfg___en___lsb 30 +#define reg_sser_rw_cfg___en___width 1 +#define reg_sser_rw_cfg___en___bit 30 +#define reg_sser_rw_cfg_offset 0 + +/* Register rw_frm_cfg, scope sser, type rw */ +#define reg_sser_rw_frm_cfg___wordrate___lsb 0 +#define reg_sser_rw_frm_cfg___wordrate___width 10 +#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 +#define reg_sser_rw_frm_cfg___rec_delay___width 3 +#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 +#define reg_sser_rw_frm_cfg___tr_delay___width 3 +#define reg_sser_rw_frm_cfg___early_wend___lsb 16 +#define reg_sser_rw_frm_cfg___early_wend___width 1 +#define reg_sser_rw_frm_cfg___early_wend___bit 16 +#define reg_sser_rw_frm_cfg___level___lsb 17 +#define reg_sser_rw_frm_cfg___level___width 2 +#define reg_sser_rw_frm_cfg___type___lsb 19 +#define reg_sser_rw_frm_cfg___type___width 1 +#define reg_sser_rw_frm_cfg___type___bit 19 +#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 +#define reg_sser_rw_frm_cfg___clk_pol___width 1 +#define reg_sser_rw_frm_cfg___clk_pol___bit 20 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 +#define reg_sser_rw_frm_cfg___clk_src___lsb 22 +#define reg_sser_rw_frm_cfg___clk_src___width 1 +#define reg_sser_rw_frm_cfg___clk_src___bit 22 +#define reg_sser_rw_frm_cfg___out_off___lsb 23 +#define reg_sser_rw_frm_cfg___out_off___width 1 +#define reg_sser_rw_frm_cfg___out_off___bit 23 +#define reg_sser_rw_frm_cfg___out_on___lsb 24 +#define reg_sser_rw_frm_cfg___out_on___width 1 +#define reg_sser_rw_frm_cfg___out_on___bit 24 +#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 +#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 +#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 +#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 +#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 +#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 +#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 +#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 +#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 +#define reg_sser_rw_frm_cfg___status_pin_use___width 2 +#define reg_sser_rw_frm_cfg_offset 4 + +/* Register rw_tr_cfg, scope sser, type rw */ +#define reg_sser_rw_tr_cfg___tr_en___lsb 0 +#define reg_sser_rw_tr_cfg___tr_en___width 1 +#define reg_sser_rw_tr_cfg___tr_en___bit 0 +#define reg_sser_rw_tr_cfg___stop___lsb 1 +#define reg_sser_rw_tr_cfg___stop___width 1 +#define reg_sser_rw_tr_cfg___stop___bit 1 +#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 +#define reg_sser_rw_tr_cfg___urun_stop___width 1 +#define reg_sser_rw_tr_cfg___urun_stop___bit 2 +#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 +#define reg_sser_rw_tr_cfg___eop_stop___width 1 +#define reg_sser_rw_tr_cfg___eop_stop___bit 3 +#define reg_sser_rw_tr_cfg___sample_size___lsb 4 +#define reg_sser_rw_tr_cfg___sample_size___width 6 +#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 +#define reg_sser_rw_tr_cfg___sh_dir___width 1 +#define reg_sser_rw_tr_cfg___sh_dir___bit 10 +#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 +#define reg_sser_rw_tr_cfg___clk_pol___width 1 +#define reg_sser_rw_tr_cfg___clk_pol___bit 11 +#define reg_sser_rw_tr_cfg___clk_src___lsb 12 +#define reg_sser_rw_tr_cfg___clk_src___width 1 +#define reg_sser_rw_tr_cfg___clk_src___bit 12 +#define reg_sser_rw_tr_cfg___use_dma___lsb 13 +#define reg_sser_rw_tr_cfg___use_dma___width 1 +#define reg_sser_rw_tr_cfg___use_dma___bit 13 +#define reg_sser_rw_tr_cfg___mode___lsb 14 +#define reg_sser_rw_tr_cfg___mode___width 2 +#define reg_sser_rw_tr_cfg___frm_src___lsb 16 +#define reg_sser_rw_tr_cfg___frm_src___width 1 +#define reg_sser_rw_tr_cfg___frm_src___bit 16 +#define reg_sser_rw_tr_cfg___use60958___lsb 17 +#define reg_sser_rw_tr_cfg___use60958___width 1 +#define reg_sser_rw_tr_cfg___use60958___bit 17 +#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 +#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 +#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 +#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 +#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 +#define reg_sser_rw_tr_cfg___use_md___lsb 21 +#define reg_sser_rw_tr_cfg___use_md___width 1 +#define reg_sser_rw_tr_cfg___use_md___bit 21 +#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 +#define reg_sser_rw_tr_cfg___dual_i2s___width 1 +#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 +#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 +#define reg_sser_rw_tr_cfg___data_pin_use___width 2 +#define reg_sser_rw_tr_cfg___od_mode___lsb 25 +#define reg_sser_rw_tr_cfg___od_mode___width 1 +#define reg_sser_rw_tr_cfg___od_mode___bit 25 +#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 +#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 +#define reg_sser_rw_tr_cfg_offset 8 + +/* Register rw_rec_cfg, scope sser, type rw */ +#define reg_sser_rw_rec_cfg___rec_en___lsb 0 +#define reg_sser_rw_rec_cfg___rec_en___width 1 +#define reg_sser_rw_rec_cfg___rec_en___bit 0 +#define reg_sser_rw_rec_cfg___force_eop___lsb 1 +#define reg_sser_rw_rec_cfg___force_eop___width 1 +#define reg_sser_rw_rec_cfg___force_eop___bit 1 +#define reg_sser_rw_rec_cfg___stop___lsb 2 +#define reg_sser_rw_rec_cfg___stop___width 1 +#define reg_sser_rw_rec_cfg___stop___bit 2 +#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 +#define reg_sser_rw_rec_cfg___orun_stop___width 1 +#define reg_sser_rw_rec_cfg___orun_stop___bit 3 +#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 +#define reg_sser_rw_rec_cfg___eop_stop___width 1 +#define reg_sser_rw_rec_cfg___eop_stop___bit 4 +#define reg_sser_rw_rec_cfg___sample_size___lsb 5 +#define reg_sser_rw_rec_cfg___sample_size___width 6 +#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 +#define reg_sser_rw_rec_cfg___sh_dir___width 1 +#define reg_sser_rw_rec_cfg___sh_dir___bit 11 +#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 +#define reg_sser_rw_rec_cfg___clk_pol___width 1 +#define reg_sser_rw_rec_cfg___clk_pol___bit 12 +#define reg_sser_rw_rec_cfg___clk_src___lsb 13 +#define reg_sser_rw_rec_cfg___clk_src___width 1 +#define reg_sser_rw_rec_cfg___clk_src___bit 13 +#define reg_sser_rw_rec_cfg___use_dma___lsb 14 +#define reg_sser_rw_rec_cfg___use_dma___width 1 +#define reg_sser_rw_rec_cfg___use_dma___bit 14 +#define reg_sser_rw_rec_cfg___mode___lsb 15 +#define reg_sser_rw_rec_cfg___mode___width 2 +#define reg_sser_rw_rec_cfg___frm_src___lsb 17 +#define reg_sser_rw_rec_cfg___frm_src___width 2 +#define reg_sser_rw_rec_cfg___use60958___lsb 19 +#define reg_sser_rw_rec_cfg___use60958___width 1 +#define reg_sser_rw_rec_cfg___use60958___bit 19 +#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 +#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 +#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 +#define reg_sser_rw_rec_cfg___slave2_en___width 1 +#define reg_sser_rw_rec_cfg___slave2_en___bit 25 +#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 +#define reg_sser_rw_rec_cfg___slave3_en___width 1 +#define reg_sser_rw_rec_cfg___slave3_en___bit 26 +#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 +#define reg_sser_rw_rec_cfg___fifo_thr___width 2 +#define reg_sser_rw_rec_cfg_offset 12 + +/* Register rw_tr_data, scope sser, type rw */ +#define reg_sser_rw_tr_data___data___lsb 0 +#define reg_sser_rw_tr_data___data___width 16 +#define reg_sser_rw_tr_data___md___lsb 16 +#define reg_sser_rw_tr_data___md___width 1 +#define reg_sser_rw_tr_data___md___bit 16 +#define reg_sser_rw_tr_data_offset 16 + +/* Register r_rec_data, scope sser, type r */ +#define reg_sser_r_rec_data___data___lsb 0 +#define reg_sser_r_rec_data___data___width 16 +#define reg_sser_r_rec_data___md___lsb 16 +#define reg_sser_r_rec_data___md___width 1 +#define reg_sser_r_rec_data___md___bit 16 +#define reg_sser_r_rec_data___ext_clk___lsb 17 +#define reg_sser_r_rec_data___ext_clk___width 1 +#define reg_sser_r_rec_data___ext_clk___bit 17 +#define reg_sser_r_rec_data___status_in___lsb 18 +#define reg_sser_r_rec_data___status_in___width 1 +#define reg_sser_r_rec_data___status_in___bit 18 +#define reg_sser_r_rec_data___frame_in___lsb 19 +#define reg_sser_r_rec_data___frame_in___width 1 +#define reg_sser_r_rec_data___frame_in___bit 19 +#define reg_sser_r_rec_data___din___lsb 20 +#define reg_sser_r_rec_data___din___width 1 +#define reg_sser_r_rec_data___din___bit 20 +#define reg_sser_r_rec_data___data_in___lsb 21 +#define reg_sser_r_rec_data___data_in___width 1 +#define reg_sser_r_rec_data___data_in___bit 21 +#define reg_sser_r_rec_data___clk_in___lsb 22 +#define reg_sser_r_rec_data___clk_in___width 1 +#define reg_sser_r_rec_data___clk_in___bit 22 +#define reg_sser_r_rec_data_offset 20 + +/* Register rw_extra, scope sser, type rw */ +#define reg_sser_rw_extra___clkoff_cycles___lsb 0 +#define reg_sser_rw_extra___clkoff_cycles___width 20 +#define reg_sser_rw_extra___clkoff_en___lsb 20 +#define reg_sser_rw_extra___clkoff_en___width 1 +#define reg_sser_rw_extra___clkoff_en___bit 20 +#define reg_sser_rw_extra___clkon_en___lsb 21 +#define reg_sser_rw_extra___clkon_en___width 1 +#define reg_sser_rw_extra___clkon_en___bit 21 +#define reg_sser_rw_extra___dout_delay___lsb 22 +#define reg_sser_rw_extra___dout_delay___width 5 +#define reg_sser_rw_extra_offset 24 + +/* Register rw_intr_mask, scope sser, type rw */ +#define reg_sser_rw_intr_mask___trdy___lsb 0 +#define reg_sser_rw_intr_mask___trdy___width 1 +#define reg_sser_rw_intr_mask___trdy___bit 0 +#define reg_sser_rw_intr_mask___rdav___lsb 1 +#define reg_sser_rw_intr_mask___rdav___width 1 +#define reg_sser_rw_intr_mask___rdav___bit 1 +#define reg_sser_rw_intr_mask___tidle___lsb 2 +#define reg_sser_rw_intr_mask___tidle___width 1 +#define reg_sser_rw_intr_mask___tidle___bit 2 +#define reg_sser_rw_intr_mask___rstop___lsb 3 +#define reg_sser_rw_intr_mask___rstop___width 1 +#define reg_sser_rw_intr_mask___rstop___bit 3 +#define reg_sser_rw_intr_mask___urun___lsb 4 +#define reg_sser_rw_intr_mask___urun___width 1 +#define reg_sser_rw_intr_mask___urun___bit 4 +#define reg_sser_rw_intr_mask___orun___lsb 5 +#define reg_sser_rw_intr_mask___orun___width 1 +#define reg_sser_rw_intr_mask___orun___bit 5 +#define reg_sser_rw_intr_mask___md_rec___lsb 6 +#define reg_sser_rw_intr_mask___md_rec___width 1 +#define reg_sser_rw_intr_mask___md_rec___bit 6 +#define reg_sser_rw_intr_mask___md_sent___lsb 7 +#define reg_sser_rw_intr_mask___md_sent___width 1 +#define reg_sser_rw_intr_mask___md_sent___bit 7 +#define reg_sser_rw_intr_mask___r958err___lsb 8 +#define reg_sser_rw_intr_mask___r958err___width 1 +#define reg_sser_rw_intr_mask___r958err___bit 8 +#define reg_sser_rw_intr_mask_offset 28 + +/* Register rw_ack_intr, scope sser, type rw */ +#define reg_sser_rw_ack_intr___trdy___lsb 0 +#define reg_sser_rw_ack_intr___trdy___width 1 +#define reg_sser_rw_ack_intr___trdy___bit 0 +#define reg_sser_rw_ack_intr___rdav___lsb 1 +#define reg_sser_rw_ack_intr___rdav___width 1 +#define reg_sser_rw_ack_intr___rdav___bit 1 +#define reg_sser_rw_ack_intr___tidle___lsb 2 +#define reg_sser_rw_ack_intr___tidle___width 1 +#define reg_sser_rw_ack_intr___tidle___bit 2 +#define reg_sser_rw_ack_intr___rstop___lsb 3 +#define reg_sser_rw_ack_intr___rstop___width 1 +#define reg_sser_rw_ack_intr___rstop___bit 3 +#define reg_sser_rw_ack_intr___urun___lsb 4 +#define reg_sser_rw_ack_intr___urun___width 1 +#define reg_sser_rw_ack_intr___urun___bit 4 +#define reg_sser_rw_ack_intr___orun___lsb 5 +#define reg_sser_rw_ack_intr___orun___width 1 +#define reg_sser_rw_ack_intr___orun___bit 5 +#define reg_sser_rw_ack_intr___md_rec___lsb 6 +#define reg_sser_rw_ack_intr___md_rec___width 1 +#define reg_sser_rw_ack_intr___md_rec___bit 6 +#define reg_sser_rw_ack_intr___md_sent___lsb 7 +#define reg_sser_rw_ack_intr___md_sent___width 1 +#define reg_sser_rw_ack_intr___md_sent___bit 7 +#define reg_sser_rw_ack_intr___r958err___lsb 8 +#define reg_sser_rw_ack_intr___r958err___width 1 +#define reg_sser_rw_ack_intr___r958err___bit 8 +#define reg_sser_rw_ack_intr_offset 32 + +/* Register r_intr, scope sser, type r */ +#define reg_sser_r_intr___trdy___lsb 0 +#define reg_sser_r_intr___trdy___width 1 +#define reg_sser_r_intr___trdy___bit 0 +#define reg_sser_r_intr___rdav___lsb 1 +#define reg_sser_r_intr___rdav___width 1 +#define reg_sser_r_intr___rdav___bit 1 +#define reg_sser_r_intr___tidle___lsb 2 +#define reg_sser_r_intr___tidle___width 1 +#define reg_sser_r_intr___tidle___bit 2 +#define reg_sser_r_intr___rstop___lsb 3 +#define reg_sser_r_intr___rstop___width 1 +#define reg_sser_r_intr___rstop___bit 3 +#define reg_sser_r_intr___urun___lsb 4 +#define reg_sser_r_intr___urun___width 1 +#define reg_sser_r_intr___urun___bit 4 +#define reg_sser_r_intr___orun___lsb 5 +#define reg_sser_r_intr___orun___width 1 +#define reg_sser_r_intr___orun___bit 5 +#define reg_sser_r_intr___md_rec___lsb 6 +#define reg_sser_r_intr___md_rec___width 1 +#define reg_sser_r_intr___md_rec___bit 6 +#define reg_sser_r_intr___md_sent___lsb 7 +#define reg_sser_r_intr___md_sent___width 1 +#define reg_sser_r_intr___md_sent___bit 7 +#define reg_sser_r_intr___r958err___lsb 8 +#define reg_sser_r_intr___r958err___width 1 +#define reg_sser_r_intr___r958err___bit 8 +#define reg_sser_r_intr_offset 36 + +/* Register r_masked_intr, scope sser, type r */ +#define reg_sser_r_masked_intr___trdy___lsb 0 +#define reg_sser_r_masked_intr___trdy___width 1 +#define reg_sser_r_masked_intr___trdy___bit 0 +#define reg_sser_r_masked_intr___rdav___lsb 1 +#define reg_sser_r_masked_intr___rdav___width 1 +#define reg_sser_r_masked_intr___rdav___bit 1 +#define reg_sser_r_masked_intr___tidle___lsb 2 +#define reg_sser_r_masked_intr___tidle___width 1 +#define reg_sser_r_masked_intr___tidle___bit 2 +#define reg_sser_r_masked_intr___rstop___lsb 3 +#define reg_sser_r_masked_intr___rstop___width 1 +#define reg_sser_r_masked_intr___rstop___bit 3 +#define reg_sser_r_masked_intr___urun___lsb 4 +#define reg_sser_r_masked_intr___urun___width 1 +#define reg_sser_r_masked_intr___urun___bit 4 +#define reg_sser_r_masked_intr___orun___lsb 5 +#define reg_sser_r_masked_intr___orun___width 1 +#define reg_sser_r_masked_intr___orun___bit 5 +#define reg_sser_r_masked_intr___md_rec___lsb 6 +#define reg_sser_r_masked_intr___md_rec___width 1 +#define reg_sser_r_masked_intr___md_rec___bit 6 +#define reg_sser_r_masked_intr___md_sent___lsb 7 +#define reg_sser_r_masked_intr___md_sent___width 1 +#define reg_sser_r_masked_intr___md_sent___bit 7 +#define reg_sser_r_masked_intr___r958err___lsb 8 +#define reg_sser_r_masked_intr___r958err___width 1 +#define reg_sser_r_masked_intr___r958err___bit 8 +#define reg_sser_r_masked_intr_offset 40 + + +/* Constants */ +#define regk_sser_both 0x00000002 +#define regk_sser_bulk 0x00000001 +#define regk_sser_clk100 0x00000000 +#define regk_sser_clk_in 0x00000000 +#define regk_sser_const0 0x00000003 +#define regk_sser_dout 0x00000002 +#define regk_sser_edge 0x00000000 +#define regk_sser_ext 0x00000001 +#define regk_sser_ext_clk 0x00000001 +#define regk_sser_f100 0x00000000 +#define regk_sser_f29_493 0x00000004 +#define regk_sser_f32 0x00000005 +#define regk_sser_f32_768 0x00000006 +#define regk_sser_frm 0x00000003 +#define regk_sser_gio0 0x00000000 +#define regk_sser_gio1 0x00000001 +#define regk_sser_hispeed 0x00000001 +#define regk_sser_hold 0x00000002 +#define regk_sser_in 0x00000000 +#define regk_sser_inf 0x00000003 +#define regk_sser_intern 0x00000000 +#define regk_sser_intern_clk 0x00000001 +#define regk_sser_intern_tb 0x00000000 +#define regk_sser_iso 0x00000000 +#define regk_sser_level 0x00000001 +#define regk_sser_lospeed 0x00000000 +#define regk_sser_lsbfirst 0x00000000 +#define regk_sser_msbfirst 0x00000001 +#define regk_sser_neg 0x00000001 +#define regk_sser_neg_lo 0x00000000 +#define regk_sser_no 0x00000000 +#define regk_sser_no_clk 0x00000007 +#define regk_sser_nojitter 0x00000002 +#define regk_sser_out 0x00000001 +#define regk_sser_pos 0x00000000 +#define regk_sser_pos_hi 0x00000001 +#define regk_sser_rec 0x00000000 +#define regk_sser_rw_cfg_default 0x00000000 +#define regk_sser_rw_extra_default 0x00000000 +#define regk_sser_rw_frm_cfg_default 0x00000000 +#define regk_sser_rw_intr_mask_default 0x00000000 +#define regk_sser_rw_rec_cfg_default 0x00000000 +#define regk_sser_rw_tr_cfg_default 0x01800000 +#define regk_sser_rw_tr_data_default 0x00000000 +#define regk_sser_thr16 0x00000001 +#define regk_sser_thr32 0x00000002 +#define regk_sser_thr8 0x00000000 +#define regk_sser_tr 0x00000001 +#define regk_sser_ts_out 0x00000003 +#define regk_sser_tx_bulk 0x00000002 +#define regk_sser_wiresave 0x00000002 +#define regk_sser_yes 0x00000001 +#endif /* __sser_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h new file mode 100644 index 000000000000..55083e6aec93 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h @@ -0,0 +1,84 @@ +#ifndef __strcop_defs_asm_h +#define __strcop_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/strcop/rtl/strcop_regs.r + * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp + * last modfied: Mon Apr 11 16:09:38 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r + * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope strcop, type rw */ +#define reg_strcop_rw_cfg___td3___lsb 0 +#define reg_strcop_rw_cfg___td3___width 1 +#define reg_strcop_rw_cfg___td3___bit 0 +#define reg_strcop_rw_cfg___td2___lsb 1 +#define reg_strcop_rw_cfg___td2___width 1 +#define reg_strcop_rw_cfg___td2___bit 1 +#define reg_strcop_rw_cfg___td1___lsb 2 +#define reg_strcop_rw_cfg___td1___width 1 +#define reg_strcop_rw_cfg___td1___bit 2 +#define reg_strcop_rw_cfg___ipend___lsb 3 +#define reg_strcop_rw_cfg___ipend___width 1 +#define reg_strcop_rw_cfg___ipend___bit 3 +#define reg_strcop_rw_cfg___ignore_sync___lsb 4 +#define reg_strcop_rw_cfg___ignore_sync___width 1 +#define reg_strcop_rw_cfg___ignore_sync___bit 4 +#define reg_strcop_rw_cfg___en___lsb 5 +#define reg_strcop_rw_cfg___en___width 1 +#define reg_strcop_rw_cfg___en___bit 5 +#define reg_strcop_rw_cfg_offset 0 + + +/* Constants */ +#define regk_strcop_big 0x00000001 +#define regk_strcop_d 0x00000001 +#define regk_strcop_e 0x00000000 +#define regk_strcop_little 0x00000000 +#define regk_strcop_rw_cfg_default 0x00000002 +#endif /* __strcop_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h new file mode 100644 index 000000000000..69b299920f71 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h @@ -0,0 +1,100 @@ +#ifndef __strmux_defs_asm_h +#define __strmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope strmux, type rw */ +#define reg_strmux_rw_cfg___dma0___lsb 0 +#define reg_strmux_rw_cfg___dma0___width 3 +#define reg_strmux_rw_cfg___dma1___lsb 3 +#define reg_strmux_rw_cfg___dma1___width 3 +#define reg_strmux_rw_cfg___dma2___lsb 6 +#define reg_strmux_rw_cfg___dma2___width 3 +#define reg_strmux_rw_cfg___dma3___lsb 9 +#define reg_strmux_rw_cfg___dma3___width 3 +#define reg_strmux_rw_cfg___dma4___lsb 12 +#define reg_strmux_rw_cfg___dma4___width 3 +#define reg_strmux_rw_cfg___dma5___lsb 15 +#define reg_strmux_rw_cfg___dma5___width 3 +#define reg_strmux_rw_cfg___dma6___lsb 18 +#define reg_strmux_rw_cfg___dma6___width 3 +#define reg_strmux_rw_cfg___dma7___lsb 21 +#define reg_strmux_rw_cfg___dma7___width 3 +#define reg_strmux_rw_cfg___dma8___lsb 24 +#define reg_strmux_rw_cfg___dma8___width 3 +#define reg_strmux_rw_cfg___dma9___lsb 27 +#define reg_strmux_rw_cfg___dma9___width 3 +#define reg_strmux_rw_cfg_offset 0 + + +/* Constants */ +#define regk_strmux_ata 0x00000003 +#define regk_strmux_eth0 0x00000001 +#define regk_strmux_eth1 0x00000004 +#define regk_strmux_ext0 0x00000001 +#define regk_strmux_ext1 0x00000001 +#define regk_strmux_ext2 0x00000001 +#define regk_strmux_ext3 0x00000001 +#define regk_strmux_iop0 0x00000002 +#define regk_strmux_iop1 0x00000001 +#define regk_strmux_off 0x00000000 +#define regk_strmux_p21 0x00000004 +#define regk_strmux_rw_cfg_default 0x00000000 +#define regk_strmux_ser0 0x00000002 +#define regk_strmux_ser1 0x00000002 +#define regk_strmux_ser2 0x00000004 +#define regk_strmux_ser3 0x00000003 +#define regk_strmux_sser0 0x00000003 +#define regk_strmux_sser1 0x00000003 +#define regk_strmux_strcop 0x00000002 +#endif /* __strmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000000..43146021fc16 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,229 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h new file mode 100644 index 000000000000..43b6643ff0d3 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h @@ -0,0 +1,222 @@ +#ifndef __ata_defs_h +#define __ata_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ata/rtl/ata_regs.r + * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp + * last modfied: Mon Apr 11 16:06:25 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r + * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ata */ + +/* Register rw_ctrl0, scope ata, type rw */ +typedef struct { + unsigned int pio_hold : 6; + unsigned int pio_strb : 6; + unsigned int pio_setup : 6; + unsigned int dma_hold : 6; + unsigned int dma_strb : 6; + unsigned int rst : 1; + unsigned int en : 1; +} reg_ata_rw_ctrl0; +#define REG_RD_ADDR_ata_rw_ctrl0 12 +#define REG_WR_ADDR_ata_rw_ctrl0 12 + +/* Register rw_ctrl1, scope ata, type rw */ +typedef struct { + unsigned int udma_tcyc : 4; + unsigned int udma_tdvs : 4; + unsigned int dummy1 : 24; +} reg_ata_rw_ctrl1; +#define REG_RD_ADDR_ata_rw_ctrl1 16 +#define REG_WR_ADDR_ata_rw_ctrl1 16 + +/* Register rw_ctrl2, scope ata, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 3; + unsigned int dma_size : 1; + unsigned int multi : 1; + unsigned int hsh : 2; + unsigned int trf_mode : 1; + unsigned int rw : 1; + unsigned int addr : 3; + unsigned int cs0 : 1; + unsigned int cs1 : 1; + unsigned int sel : 2; +} reg_ata_rw_ctrl2; +#define REG_RD_ADDR_ata_rw_ctrl2 0 +#define REG_WR_ADDR_ata_rw_ctrl2 0 + +/* Register rs_stat_data, scope ata, type rs */ +typedef struct { + unsigned int data : 16; + unsigned int dav : 1; + unsigned int busy : 1; + unsigned int dummy1 : 14; +} reg_ata_rs_stat_data; +#define REG_RD_ADDR_ata_rs_stat_data 4 + +/* Register r_stat_data, scope ata, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dav : 1; + unsigned int busy : 1; + unsigned int dummy1 : 14; +} reg_ata_r_stat_data; +#define REG_RD_ADDR_ata_r_stat_data 8 + +/* Register rw_trf_cnt, scope ata, type rw */ +typedef struct { + unsigned int cnt : 17; + unsigned int dummy1 : 15; +} reg_ata_rw_trf_cnt; +#define REG_RD_ADDR_ata_rw_trf_cnt 20 +#define REG_WR_ADDR_ata_rw_trf_cnt 20 + +/* Register r_stat_misc, scope ata, type r */ +typedef struct { + unsigned int crc : 16; + unsigned int dummy1 : 16; +} reg_ata_r_stat_misc; +#define REG_RD_ADDR_ata_r_stat_misc 24 + +/* Register rw_intr_mask, scope ata, type rw */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_rw_intr_mask; +#define REG_RD_ADDR_ata_rw_intr_mask 28 +#define REG_WR_ADDR_ata_rw_intr_mask 28 + +/* Register rw_ack_intr, scope ata, type rw */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_rw_ack_intr; +#define REG_RD_ADDR_ata_rw_ack_intr 32 +#define REG_WR_ADDR_ata_rw_ack_intr 32 + +/* Register r_intr, scope ata, type r */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_r_intr; +#define REG_RD_ADDR_ata_r_intr 36 + +/* Register r_masked_intr, scope ata, type r */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_r_masked_intr; +#define REG_RD_ADDR_ata_r_masked_intr 40 + + +/* Constants */ +enum { + regk_ata_active = 0x00000001, + regk_ata_byte = 0x00000001, + regk_ata_data = 0x00000001, + regk_ata_dma = 0x00000001, + regk_ata_inactive = 0x00000000, + regk_ata_no = 0x00000000, + regk_ata_nodata = 0x00000000, + regk_ata_pio = 0x00000000, + regk_ata_rd = 0x00000001, + regk_ata_reg = 0x00000000, + regk_ata_rw_ctrl0_default = 0x00000000, + regk_ata_rw_ctrl2_default = 0x00000000, + regk_ata_rw_intr_mask_default = 0x00000000, + regk_ata_udma = 0x00000002, + regk_ata_word = 0x00000000, + regk_ata_wr = 0x00000000, + regk_ata_yes = 0x00000001 +}; +#endif /* __ata_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h new file mode 100644 index 000000000000..a56608b50359 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h @@ -0,0 +1,284 @@ +#ifndef __bif_core_defs_h +#define __bif_core_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_core */ + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp1_cfg; +#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 +#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp2_cfg; +#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 +#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 2; + unsigned int gated_csp0 : 2; + unsigned int gated_csp1 : 2; + unsigned int gated_csp2 : 2; + unsigned int gated_csp3 : 2; +} reg_bif_core_rw_grp3_cfg; +#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 +#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 4; + unsigned int gated_csp4 : 2; + unsigned int gated_csp5 : 2; + unsigned int gated_csp6 : 2; +} reg_bif_core_rw_grp4_cfg; +#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 +#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int grp_sel : 5; + unsigned int dummy1 : 12; +} reg_bif_core_rw_sdram_cfg_grp0; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int dummy1 : 17; +} reg_bif_core_rw_sdram_cfg_grp1; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +typedef struct { + unsigned int cl : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int rc : 2; + unsigned int dpl : 2; + unsigned int pde : 1; + unsigned int ref : 2; + unsigned int cpd : 1; + unsigned int sdcke : 1; + unsigned int sdclk : 1; + unsigned int dummy1 : 13; +} reg_bif_core_rw_sdram_timing; +#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 +#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +typedef struct { + unsigned int cmd : 3; + unsigned int mrs_data : 15; + unsigned int dummy1 : 14; +} reg_bif_core_rw_sdram_cmd; +#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 +#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_rs_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_r_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 + + +/* Constants */ +enum { + regk_bif_core_bank2 = 0x00000000, + regk_bif_core_bank4 = 0x00000001, + regk_bif_core_bit10 = 0x0000000a, + regk_bif_core_bit11 = 0x0000000b, + regk_bif_core_bit12 = 0x0000000c, + regk_bif_core_bit13 = 0x0000000d, + regk_bif_core_bit14 = 0x0000000e, + regk_bif_core_bit15 = 0x0000000f, + regk_bif_core_bit16 = 0x00000010, + regk_bif_core_bit17 = 0x00000011, + regk_bif_core_bit18 = 0x00000012, + regk_bif_core_bit19 = 0x00000013, + regk_bif_core_bit20 = 0x00000014, + regk_bif_core_bit21 = 0x00000015, + regk_bif_core_bit22 = 0x00000016, + regk_bif_core_bit23 = 0x00000017, + regk_bif_core_bit24 = 0x00000018, + regk_bif_core_bit25 = 0x00000019, + regk_bif_core_bit26 = 0x0000001a, + regk_bif_core_bit27 = 0x0000001b, + regk_bif_core_bit28 = 0x0000001c, + regk_bif_core_bit29 = 0x0000001d, + regk_bif_core_bit9 = 0x00000009, + regk_bif_core_bw16 = 0x00000001, + regk_bif_core_bw32 = 0x00000000, + regk_bif_core_bwe = 0x00000000, + regk_bif_core_cwe = 0x00000001, + regk_bif_core_e15us = 0x00000001, + regk_bif_core_e7800ns = 0x00000002, + regk_bif_core_grp0 = 0x00000000, + regk_bif_core_grp1 = 0x00000001, + regk_bif_core_mrs = 0x00000003, + regk_bif_core_no = 0x00000000, + regk_bif_core_none = 0x00000000, + regk_bif_core_nop = 0x00000000, + regk_bif_core_off = 0x00000000, + regk_bif_core_pre = 0x00000002, + regk_bif_core_r_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rd = 0x00000002, + regk_bif_core_ref = 0x00000001, + regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rw_grp1_cfg_default = 0x000006cf, + regk_bif_core_rw_grp2_cfg_default = 0x000006cf, + regk_bif_core_rw_grp3_cfg_default = 0x000006cf, + regk_bif_core_rw_grp4_cfg_default = 0x000006cf, + regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, + regk_bif_core_slf = 0x00000004, + regk_bif_core_wr = 0x00000001, + regk_bif_core_yes = 0x00000001 +}; +#endif /* __bif_core_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h new file mode 100644 index 000000000000..b931c1aab679 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h @@ -0,0 +1,473 @@ +#ifndef __bif_dma_defs_h +#define __bif_dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_dma */ + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch0_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 +#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch0_addr; +#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 +#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch0_start; +#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 +#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch0_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 +#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch0_stat; +#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch1_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 +#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch1_addr; +#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 +#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch1_start; +#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 +#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch1_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 +#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch1_stat; +#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch2_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 +#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch2_addr; +#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 +#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch2_start; +#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 +#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch2_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 +#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch2_stat; +#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch3_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 +#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch3_addr; +#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 +#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch3_start; +#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 +#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch3_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 +#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch3_stat; +#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_intr_mask; +#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 +#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_ack_intr; +#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 +#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 + +/* Register r_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_intr; +#define REG_RD_ADDR_bif_dma_r_intr 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_masked_intr; +#define REG_RD_ADDR_bif_dma_r_masked_intr 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin0_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 +#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin1_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 +#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin2_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 +#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin3_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 +#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin4_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 +#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin5_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 +#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin6_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 +#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin7_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 +#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +typedef struct { + unsigned int pin0 : 1; + unsigned int pin1 : 1; + unsigned int pin2 : 1; + unsigned int pin3 : 1; + unsigned int pin4 : 1; + unsigned int pin5 : 1; + unsigned int pin6 : 1; + unsigned int pin7 : 1; + unsigned int dummy1 : 24; +} reg_bif_dma_r_pin_stat; +#define REG_RD_ADDR_bif_dma_r_pin_stat 192 + + +/* Constants */ +enum { + regk_bif_dma_as_master = 0x00000001, + regk_bif_dma_as_slave = 0x00000001, + regk_bif_dma_burst1 = 0x00000000, + regk_bif_dma_burst8 = 0x00000001, + regk_bif_dma_bw16 = 0x00000001, + regk_bif_dma_bw32 = 0x00000002, + regk_bif_dma_bw8 = 0x00000000, + regk_bif_dma_dack = 0x00000006, + regk_bif_dma_dack_inv = 0x00000007, + regk_bif_dma_force = 0x00000001, + regk_bif_dma_hi = 0x00000003, + regk_bif_dma_inv = 0x00000003, + regk_bif_dma_lo = 0x00000002, + regk_bif_dma_master = 0x00000001, + regk_bif_dma_no = 0x00000000, + regk_bif_dma_norm = 0x00000002, + regk_bif_dma_off = 0x00000000, + regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch0_start_default = 0x00000000, + regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch1_start_default = 0x00000000, + regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch2_start_default = 0x00000000, + regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch3_start_default = 0x00000000, + regk_bif_dma_rw_intr_mask_default = 0x00000000, + regk_bif_dma_rw_pin0_cfg_default = 0x00000000, + regk_bif_dma_rw_pin1_cfg_default = 0x00000000, + regk_bif_dma_rw_pin2_cfg_default = 0x00000000, + regk_bif_dma_rw_pin3_cfg_default = 0x00000000, + regk_bif_dma_rw_pin4_cfg_default = 0x00000000, + regk_bif_dma_rw_pin5_cfg_default = 0x00000000, + regk_bif_dma_rw_pin6_cfg_default = 0x00000000, + regk_bif_dma_rw_pin7_cfg_default = 0x00000000, + regk_bif_dma_slave = 0x00000002, + regk_bif_dma_sreq = 0x00000006, + regk_bif_dma_sreq_inv = 0x00000007, + regk_bif_dma_tc = 0x00000004, + regk_bif_dma_tc_inv = 0x00000005, + regk_bif_dma_yes = 0x00000001 +}; +#endif /* __bif_dma_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h new file mode 100644 index 000000000000..d18fc3c9f569 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_h +#define __bif_slave_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_slave */ + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int slave_id : 3; + unsigned int use_slave_id : 1; + unsigned int boot_rdy : 1; + unsigned int loopback : 1; + unsigned int dis : 1; + unsigned int dummy1 : 25; +} reg_bif_slave_rw_slave_cfg; +#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 +#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +typedef struct { + unsigned int ch0_mode : 1; + unsigned int ch1_mode : 1; + unsigned int ch2_mode : 1; + unsigned int ch3_mode : 1; + unsigned int dummy1 : 28; +} reg_bif_slave_r_slave_mode; +#define REG_RD_ADDR_bif_slave_r_slave_mode 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch0_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 +#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch1_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 +#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch2_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 +#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch3_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 +#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int brin_mode : 1; + unsigned int brout_mode : 3; + unsigned int bg_mode : 3; + unsigned int release : 2; + unsigned int acquire : 1; + unsigned int settle_time : 2; + unsigned int dram_ctrl : 1; + unsigned int dummy1 : 19; +} reg_bif_slave_rw_arb_cfg; +#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 +#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +typedef struct { + unsigned int init_mode : 1; + unsigned int mode : 1; + unsigned int brin : 1; + unsigned int brout : 1; + unsigned int bg : 1; + unsigned int dummy1 : 27; +} reg_bif_slave_r_arb_stat; +#define REG_RD_ADDR_bif_slave_r_arb_stat 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_intr_mask; +#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 +#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_ack_intr; +#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 +#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 + +/* Register r_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_intr; +#define REG_RD_ADDR_bif_slave_r_intr 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_masked_intr; +#define REG_RD_ADDR_bif_slave_r_masked_intr 76 + + +/* Constants */ +enum { + regk_bif_slave_active_hi = 0x00000003, + regk_bif_slave_active_lo = 0x00000002, + regk_bif_slave_addr = 0x00000000, + regk_bif_slave_always = 0x00000001, + regk_bif_slave_at_idle = 0x00000002, + regk_bif_slave_burst_end = 0x00000003, + regk_bif_slave_dma = 0x00000001, + regk_bif_slave_hi = 0x00000003, + regk_bif_slave_inv = 0x00000001, + regk_bif_slave_lo = 0x00000002, + regk_bif_slave_local = 0x00000001, + regk_bif_slave_master = 0x00000000, + regk_bif_slave_mode_reg = 0x00000001, + regk_bif_slave_no = 0x00000000, + regk_bif_slave_norm = 0x00000000, + regk_bif_slave_on_access = 0x00000000, + regk_bif_slave_rw_arb_cfg_default = 0x00000000, + regk_bif_slave_rw_ch0_cfg_default = 0x00000000, + regk_bif_slave_rw_ch1_cfg_default = 0x00000000, + regk_bif_slave_rw_ch2_cfg_default = 0x00000000, + regk_bif_slave_rw_ch3_cfg_default = 0x00000000, + regk_bif_slave_rw_intr_mask_default = 0x00000000, + regk_bif_slave_rw_slave_cfg_default = 0x00000000, + regk_bif_slave_shared = 0x00000000, + regk_bif_slave_slave = 0x00000001, + regk_bif_slave_t0ns = 0x00000003, + regk_bif_slave_t10ns = 0x00000002, + regk_bif_slave_t20ns = 0x00000003, + regk_bif_slave_t30ns = 0x00000002, + regk_bif_slave_t40ns = 0x00000001, + regk_bif_slave_t50ns = 0x00000000, + regk_bif_slave_yes = 0x00000001, + regk_bif_slave_z = 0x00000004 +}; +#endif /* __bif_slave_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h b/arch/cris/include/arch-v32/arch/hwregs/config_defs.h new file mode 100644 index 000000000000..45457a4e3817 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/config_defs.h @@ -0,0 +1,142 @@ +#ifndef __config_defs_h +#define __config_defs_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r + * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope config */ + +/* Register r_bootsel, scope config, type r */ +typedef struct { + unsigned int boot_mode : 3; + unsigned int full_duplex : 1; + unsigned int user : 1; + unsigned int pll : 1; + unsigned int flash_bw : 1; + unsigned int dummy1 : 25; +} reg_config_r_bootsel; +#define REG_RD_ADDR_config_r_bootsel 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop : 1; + unsigned int dma01_eth0 : 1; + unsigned int dma23 : 1; + unsigned int dma45 : 1; + unsigned int dma67 : 1; + unsigned int dma89_strcop : 1; + unsigned int bif : 1; + unsigned int fix_io : 1; + unsigned int dummy1 : 22; +} reg_config_rw_clk_ctrl; +#define REG_RD_ADDR_config_rw_clk_ctrl 4 +#define REG_WR_ADDR_config_rw_clk_ctrl 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +typedef struct { + unsigned int usb_susp : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 30; +} reg_config_rw_pad_ctrl; +#define REG_RD_ADDR_config_rw_pad_ctrl 8 +#define REG_WR_ADDR_config_rw_pad_ctrl 8 + + +/* Constants */ +enum { + regk_config_bw16 = 0x00000000, + regk_config_bw32 = 0x00000001, + regk_config_master = 0x00000005, + regk_config_nand = 0x00000003, + regk_config_net_rx = 0x00000001, + regk_config_net_tx_rx = 0x00000002, + regk_config_no = 0x00000000, + regk_config_none = 0x00000007, + regk_config_nor = 0x00000000, + regk_config_rw_clk_ctrl_default = 0x00000002, + regk_config_rw_pad_ctrl_default = 0x00000000, + regk_config_ser = 0x00000004, + regk_config_slave = 0x00000006, + regk_config_yes = 0x00000001 +}; +#endif /* __config_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h new file mode 100644 index 000000000000..8370aee8a14a --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/crisp/doc/cpu_vect.r +version . */ + +#ifndef _______INST_CRISP_DOC_CPU_VECT_R +#define _______INST_CRISP_DOC_CPU_VECT_R +#define NMI_INTR_VECT 0x00 +#define RESERVED_1_INTR_VECT 0x01 +#define RESERVED_2_INTR_VECT 0x02 +#define SINGLE_STEP_INTR_VECT 0x03 +#define INSTR_TLB_REFILL_INTR_VECT 0x04 +#define INSTR_TLB_INV_INTR_VECT 0x05 +#define INSTR_TLB_ACC_INTR_VECT 0x06 +#define TLB_EX_INTR_VECT 0x07 +#define DATA_TLB_REFILL_INTR_VECT 0x08 +#define DATA_TLB_INV_INTR_VECT 0x09 +#define DATA_TLB_ACC_INTR_VECT 0x0a +#define DATA_TLB_WE_INTR_VECT 0x0b +#define HW_BP_INTR_VECT 0x0c +#define RESERVED_D_INTR_VECT 0x0d +#define RESERVED_E_INTR_VECT 0x0e +#define RESERVED_F_INTR_VECT 0x0f +#define BREAK_0_INTR_VECT 0x10 +#define BREAK_1_INTR_VECT 0x11 +#define BREAK_2_INTR_VECT 0x12 +#define BREAK_3_INTR_VECT 0x13 +#define BREAK_4_INTR_VECT 0x14 +#define BREAK_5_INTR_VECT 0x15 +#define BREAK_6_INTR_VECT 0x16 +#define BREAK_7_INTR_VECT 0x17 +#define BREAK_8_INTR_VECT 0x18 +#define BREAK_9_INTR_VECT 0x19 +#define BREAK_10_INTR_VECT 0x1a +#define BREAK_11_INTR_VECT 0x1b +#define BREAK_12_INTR_VECT 0x1c +#define BREAK_13_INTR_VECT 0x1d +#define BREAK_14_INTR_VECT 0x1e +#define BREAK_15_INTR_VECT 0x1f +#define MULTIPLE_INTR_VECT 0x30 + +#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma.h b/arch/cris/include/arch-v32/arch/hwregs/dma.h new file mode 100644 index 000000000000..3ce322b5c731 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/dma.h @@ -0,0 +1,127 @@ +/* + * DMA C definitions and help macros + * + */ + +#ifndef dma_h +#define dma_h + +/* registers */ /* Really needed, since both are listed in sw.list? */ +#include "dma_defs.h" + + +/* descriptors */ + +// ------------------------------------------------------------ dma_descr_group +typedef struct dma_descr_group { + struct dma_descr_group *next; + unsigned eol : 1; + unsigned tol : 1; + unsigned bol : 1; + unsigned : 1; + unsigned intr : 1; + unsigned : 2; + unsigned en : 1; + unsigned : 7; + unsigned dis : 1; + unsigned md : 16; + struct dma_descr_group *up; + union { + struct dma_descr_context *context; + struct dma_descr_group *group; + } down; +} dma_descr_group; + +// ---------------------------------------------------------- dma_descr_context +typedef struct dma_descr_context { + struct dma_descr_context *next; + unsigned eol : 1; + unsigned : 3; + unsigned intr : 1; + unsigned : 1; + unsigned store_mode : 1; + unsigned en : 1; + unsigned : 7; + unsigned dis : 1; + unsigned md0 : 16; + unsigned md1; + unsigned md2; + unsigned md3; + unsigned md4; + struct dma_descr_data *saved_data; + char *saved_data_buf; +} dma_descr_context; + +// ------------------------------------------------------------- dma_descr_data +typedef struct dma_descr_data { + struct dma_descr_data *next; + char *buf; + unsigned eol : 1; + unsigned : 2; + unsigned out_eop : 1; + unsigned intr : 1; + unsigned wait : 1; + unsigned : 2; + unsigned : 3; + unsigned in_eop : 1; + unsigned : 4; + unsigned md : 16; + char *after; +} dma_descr_data; + +// --------------------------------------------------------------------- macros + +// enable DMA channel +#define DMA_ENABLE( inst ) \ + do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ + e.en = regk_dma_yes; \ + REG_WR( dma, inst, rw_cfg, e); } while( 0 ) + +// reset DMA channel +#define DMA_RESET( inst ) \ + do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ + r.en = regk_dma_no; \ + REG_WR( dma, inst, rw_cfg, r); } while( 0 ) + +// stop DMA channel +#define DMA_STOP( inst ) \ + do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ + s.stop = regk_dma_yes; \ + REG_WR( dma, inst, rw_cfg, s); } while( 0 ) + +// continue DMA channel operation +#define DMA_CONTINUE( inst ) \ + do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ + c.stop = regk_dma_no; \ + REG_WR( dma, inst, rw_cfg, c); } while( 0 ) + +// give stream command +#define DMA_WR_CMD( inst, cmd_par ) \ + do { reg_dma_rw_stream_cmd __x = {0}; \ + do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ + __x.cmd = (cmd_par); \ + REG_WR(dma, inst, rw_stream_cmd, __x); \ + } while (0) + +// load: g,c,d:burst +#define DMA_START_GROUP( inst, group_descr ) \ + do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ + DMA_WR_CMD( inst, regk_dma_load_g ); \ + DMA_WR_CMD( inst, regk_dma_load_c ); \ + DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ + } while( 0 ) + +// load: c,d:burst +#define DMA_START_CONTEXT( inst, ctx_descr ) \ + do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ + DMA_WR_CMD( inst, regk_dma_load_c ); \ + DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ + } while( 0 ) + +// if the DMA is at the end of the data list, the last data descr is reloaded +#define DMA_CONTINUE_DATA( inst ) \ +do { reg_dma_rw_cmd c = {0}; \ + c.cont_data = regk_dma_yes;\ + REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) + +#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h new file mode 100644 index 000000000000..48ac8cef7ebe --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h @@ -0,0 +1,436 @@ +#ifndef __dma_defs_h +#define __dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp + * last modfied: Mon Apr 11 16:06:51 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope dma */ + +/* Register rw_data, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data; +#define REG_RD_ADDR_dma_rw_data 0 +#define REG_WR_ADDR_dma_rw_data 0 + +/* Register rw_data_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_next; +#define REG_RD_ADDR_dma_rw_data_next 4 +#define REG_WR_ADDR_dma_rw_data_next 4 + +/* Register rw_data_buf, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_buf; +#define REG_RD_ADDR_dma_rw_data_buf 8 +#define REG_WR_ADDR_dma_rw_data_buf 8 + +/* Register rw_data_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int dummy1 : 2; + unsigned int out_eop : 1; + unsigned int intr : 1; + unsigned int wait : 1; + unsigned int dummy2 : 26; +} reg_dma_rw_data_ctrl; +#define REG_RD_ADDR_dma_rw_data_ctrl 12 +#define REG_WR_ADDR_dma_rw_data_ctrl 12 + +/* Register rw_data_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 3; + unsigned int in_eop : 1; + unsigned int dummy2 : 28; +} reg_dma_rw_data_stat; +#define REG_RD_ADDR_dma_rw_data_stat 16 +#define REG_WR_ADDR_dma_rw_data_stat 16 + +/* Register rw_data_md, scope dma, type rw */ +typedef struct { + unsigned int md : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_data_md; +#define REG_RD_ADDR_dma_rw_data_md 20 +#define REG_WR_ADDR_dma_rw_data_md 20 + +/* Register rw_data_md_s, scope dma, type rw */ +typedef struct { + unsigned int md_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_data_md_s; +#define REG_RD_ADDR_dma_rw_data_md_s 24 +#define REG_WR_ADDR_dma_rw_data_md_s 24 + +/* Register rw_data_after, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_after; +#define REG_RD_ADDR_dma_rw_data_after 28 +#define REG_WR_ADDR_dma_rw_data_after 28 + +/* Register rw_ctxt, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt; +#define REG_RD_ADDR_dma_rw_ctxt 32 +#define REG_WR_ADDR_dma_rw_ctxt 32 + +/* Register rw_ctxt_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_next; +#define REG_RD_ADDR_dma_rw_ctxt_next 36 +#define REG_WR_ADDR_dma_rw_ctxt_next 36 + +/* Register rw_ctxt_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int dummy1 : 3; + unsigned int intr : 1; + unsigned int dummy2 : 1; + unsigned int store_mode : 1; + unsigned int en : 1; + unsigned int dummy3 : 24; +} reg_dma_rw_ctxt_ctrl; +#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 +#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 + +/* Register rw_ctxt_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int dis : 1; + unsigned int dummy2 : 24; +} reg_dma_rw_ctxt_stat; +#define REG_RD_ADDR_dma_rw_ctxt_stat 44 +#define REG_WR_ADDR_dma_rw_ctxt_stat 44 + +/* Register rw_ctxt_md0, scope dma, type rw */ +typedef struct { + unsigned int md0 : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_ctxt_md0; +#define REG_RD_ADDR_dma_rw_ctxt_md0 48 +#define REG_WR_ADDR_dma_rw_ctxt_md0 48 + +/* Register rw_ctxt_md0_s, scope dma, type rw */ +typedef struct { + unsigned int md0_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_ctxt_md0_s; +#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 +#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 + +/* Register rw_ctxt_md1, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md1; +#define REG_RD_ADDR_dma_rw_ctxt_md1 56 +#define REG_WR_ADDR_dma_rw_ctxt_md1 56 + +/* Register rw_ctxt_md1_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md1_s; +#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 +#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 + +/* Register rw_ctxt_md2, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md2; +#define REG_RD_ADDR_dma_rw_ctxt_md2 64 +#define REG_WR_ADDR_dma_rw_ctxt_md2 64 + +/* Register rw_ctxt_md2_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md2_s; +#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 +#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 + +/* Register rw_ctxt_md3, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md3; +#define REG_RD_ADDR_dma_rw_ctxt_md3 72 +#define REG_WR_ADDR_dma_rw_ctxt_md3 72 + +/* Register rw_ctxt_md3_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md3_s; +#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 +#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 + +/* Register rw_ctxt_md4, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md4; +#define REG_RD_ADDR_dma_rw_ctxt_md4 80 +#define REG_WR_ADDR_dma_rw_ctxt_md4 80 + +/* Register rw_ctxt_md4_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md4_s; +#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 +#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 + +/* Register rw_saved_data, scope dma, type rw */ +typedef unsigned int reg_dma_rw_saved_data; +#define REG_RD_ADDR_dma_rw_saved_data 88 +#define REG_WR_ADDR_dma_rw_saved_data 88 + +/* Register rw_saved_data_buf, scope dma, type rw */ +typedef unsigned int reg_dma_rw_saved_data_buf; +#define REG_RD_ADDR_dma_rw_saved_data_buf 92 +#define REG_WR_ADDR_dma_rw_saved_data_buf 92 + +/* Register rw_group, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group; +#define REG_RD_ADDR_dma_rw_group 96 +#define REG_WR_ADDR_dma_rw_group 96 + +/* Register rw_group_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_next; +#define REG_RD_ADDR_dma_rw_group_next 100 +#define REG_WR_ADDR_dma_rw_group_next 100 + +/* Register rw_group_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int tol : 1; + unsigned int bol : 1; + unsigned int dummy1 : 1; + unsigned int intr : 1; + unsigned int dummy2 : 2; + unsigned int en : 1; + unsigned int dummy3 : 24; +} reg_dma_rw_group_ctrl; +#define REG_RD_ADDR_dma_rw_group_ctrl 104 +#define REG_WR_ADDR_dma_rw_group_ctrl 104 + +/* Register rw_group_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int dis : 1; + unsigned int dummy2 : 24; +} reg_dma_rw_group_stat; +#define REG_RD_ADDR_dma_rw_group_stat 108 +#define REG_WR_ADDR_dma_rw_group_stat 108 + +/* Register rw_group_md, scope dma, type rw */ +typedef struct { + unsigned int md : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_group_md; +#define REG_RD_ADDR_dma_rw_group_md 112 +#define REG_WR_ADDR_dma_rw_group_md 112 + +/* Register rw_group_md_s, scope dma, type rw */ +typedef struct { + unsigned int md_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_group_md_s; +#define REG_RD_ADDR_dma_rw_group_md_s 116 +#define REG_WR_ADDR_dma_rw_group_md_s 116 + +/* Register rw_group_up, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_up; +#define REG_RD_ADDR_dma_rw_group_up 120 +#define REG_WR_ADDR_dma_rw_group_up 120 + +/* Register rw_group_down, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_down; +#define REG_RD_ADDR_dma_rw_group_down 124 +#define REG_WR_ADDR_dma_rw_group_down 124 + +/* Register rw_cmd, scope dma, type rw */ +typedef struct { + unsigned int cont_data : 1; + unsigned int dummy1 : 31; +} reg_dma_rw_cmd; +#define REG_RD_ADDR_dma_rw_cmd 128 +#define REG_WR_ADDR_dma_rw_cmd 128 + +/* Register rw_cfg, scope dma, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int stop : 1; + unsigned int dummy1 : 30; +} reg_dma_rw_cfg; +#define REG_RD_ADDR_dma_rw_cfg 132 +#define REG_WR_ADDR_dma_rw_cfg 132 + +/* Register rw_stat, scope dma, type rw */ +typedef struct { + unsigned int mode : 5; + unsigned int list_state : 3; + unsigned int stream_cmd_src : 8; + unsigned int dummy1 : 8; + unsigned int buf : 8; +} reg_dma_rw_stat; +#define REG_RD_ADDR_dma_rw_stat 136 +#define REG_WR_ADDR_dma_rw_stat 136 + +/* Register rw_intr_mask, scope dma, type rw */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_rw_intr_mask; +#define REG_RD_ADDR_dma_rw_intr_mask 140 +#define REG_WR_ADDR_dma_rw_intr_mask 140 + +/* Register rw_ack_intr, scope dma, type rw */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_rw_ack_intr; +#define REG_RD_ADDR_dma_rw_ack_intr 144 +#define REG_WR_ADDR_dma_rw_ack_intr 144 + +/* Register r_intr, scope dma, type r */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_r_intr; +#define REG_RD_ADDR_dma_r_intr 148 + +/* Register r_masked_intr, scope dma, type r */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_r_masked_intr; +#define REG_RD_ADDR_dma_r_masked_intr 152 + +/* Register rw_stream_cmd, scope dma, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 7; + unsigned int busy : 1; +} reg_dma_rw_stream_cmd; +#define REG_RD_ADDR_dma_rw_stream_cmd 156 +#define REG_WR_ADDR_dma_rw_stream_cmd 156 + + +/* Constants */ +enum { + regk_dma_ack_pkt = 0x00000100, + regk_dma_anytime = 0x00000001, + regk_dma_array = 0x00000008, + regk_dma_burst = 0x00000020, + regk_dma_client = 0x00000002, + regk_dma_copy_next = 0x00000010, + regk_dma_copy_up = 0x00000020, + regk_dma_data_at_eol = 0x00000001, + regk_dma_dis_c = 0x00000010, + regk_dma_dis_g = 0x00000020, + regk_dma_idle = 0x00000001, + regk_dma_intern = 0x00000004, + regk_dma_load_c = 0x00000200, + regk_dma_load_c_n = 0x00000280, + regk_dma_load_c_next = 0x00000240, + regk_dma_load_d = 0x00000140, + regk_dma_load_g = 0x00000300, + regk_dma_load_g_down = 0x000003c0, + regk_dma_load_g_next = 0x00000340, + regk_dma_load_g_up = 0x00000380, + regk_dma_next_en = 0x00000010, + regk_dma_next_pkt = 0x00000010, + regk_dma_no = 0x00000000, + regk_dma_only_at_wait = 0x00000000, + regk_dma_restore = 0x00000020, + regk_dma_rst = 0x00000001, + regk_dma_running = 0x00000004, + regk_dma_rw_cfg_default = 0x00000000, + regk_dma_rw_cmd_default = 0x00000000, + regk_dma_rw_intr_mask_default = 0x00000000, + regk_dma_rw_stat_default = 0x00000101, + regk_dma_rw_stream_cmd_default = 0x00000000, + regk_dma_save_down = 0x00000020, + regk_dma_save_up = 0x00000020, + regk_dma_set_reg = 0x00000050, + regk_dma_set_w_size1 = 0x00000190, + regk_dma_set_w_size2 = 0x000001a0, + regk_dma_set_w_size4 = 0x000001c0, + regk_dma_stopped = 0x00000002, + regk_dma_store_c = 0x00000002, + regk_dma_store_descr = 0x00000000, + regk_dma_store_g = 0x00000004, + regk_dma_store_md = 0x00000001, + regk_dma_sw = 0x00000008, + regk_dma_update_down = 0x00000020, + regk_dma_yes = 0x00000001 +}; +#endif /* __dma_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h new file mode 100644 index 000000000000..90fe8a28894f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h @@ -0,0 +1,378 @@ +#ifndef __eth_defs_h +#define __eth_defs_h + +/* + * This file is autogenerated from + * file: eth.r + * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp + * last modfied: Mon Jan 9 06:06:41 2006 + * + * by /n/asic/design/tools/rdesc/rdes2c eth.r + * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope eth */ + +/* Register rw_ma0_lo, scope eth, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_eth_rw_ma0_lo; +#define REG_RD_ADDR_eth_rw_ma0_lo 0 +#define REG_WR_ADDR_eth_rw_ma0_lo 0 + +/* Register rw_ma0_hi, scope eth, type rw */ +typedef struct { + unsigned int addr : 16; + unsigned int dummy1 : 16; +} reg_eth_rw_ma0_hi; +#define REG_RD_ADDR_eth_rw_ma0_hi 4 +#define REG_WR_ADDR_eth_rw_ma0_hi 4 + +/* Register rw_ma1_lo, scope eth, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_eth_rw_ma1_lo; +#define REG_RD_ADDR_eth_rw_ma1_lo 8 +#define REG_WR_ADDR_eth_rw_ma1_lo 8 + +/* Register rw_ma1_hi, scope eth, type rw */ +typedef struct { + unsigned int addr : 16; + unsigned int dummy1 : 16; +} reg_eth_rw_ma1_hi; +#define REG_RD_ADDR_eth_rw_ma1_hi 12 +#define REG_WR_ADDR_eth_rw_ma1_hi 12 + +/* Register rw_ga_lo, scope eth, type rw */ +typedef struct { + unsigned int tbl : 32; +} reg_eth_rw_ga_lo; +#define REG_RD_ADDR_eth_rw_ga_lo 16 +#define REG_WR_ADDR_eth_rw_ga_lo 16 + +/* Register rw_ga_hi, scope eth, type rw */ +typedef struct { + unsigned int tbl : 32; +} reg_eth_rw_ga_hi; +#define REG_RD_ADDR_eth_rw_ga_hi 20 +#define REG_WR_ADDR_eth_rw_ga_hi 20 + +/* Register rw_gen_ctrl, scope eth, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int phy : 2; + unsigned int protocol : 1; + unsigned int loopback : 1; + unsigned int flow_ctrl : 1; + unsigned int gtxclk_out : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 24; +} reg_eth_rw_gen_ctrl; +#define REG_RD_ADDR_eth_rw_gen_ctrl 24 +#define REG_WR_ADDR_eth_rw_gen_ctrl 24 + +/* Register rw_rec_ctrl, scope eth, type rw */ +typedef struct { + unsigned int ma0 : 1; + unsigned int ma1 : 1; + unsigned int individual : 1; + unsigned int broadcast : 1; + unsigned int undersize : 1; + unsigned int oversize : 1; + unsigned int bad_crc : 1; + unsigned int duplex : 1; + unsigned int max_size : 16; + unsigned int dummy1 : 8; +} reg_eth_rw_rec_ctrl; +#define REG_RD_ADDR_eth_rw_rec_ctrl 28 +#define REG_WR_ADDR_eth_rw_rec_ctrl 28 + +/* Register rw_tr_ctrl, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int pad : 1; + unsigned int retry : 1; + unsigned int ignore_col : 1; + unsigned int cancel : 1; + unsigned int hsh_delay : 1; + unsigned int ignore_crs : 1; + unsigned int carrier_ext : 1; + unsigned int dummy1 : 24; +} reg_eth_rw_tr_ctrl; +#define REG_RD_ADDR_eth_rw_tr_ctrl 32 +#define REG_WR_ADDR_eth_rw_tr_ctrl 32 + +/* Register rw_clr_err, scope eth, type rw */ +typedef struct { + unsigned int clr : 1; + unsigned int dummy1 : 31; +} reg_eth_rw_clr_err; +#define REG_RD_ADDR_eth_rw_clr_err 36 +#define REG_WR_ADDR_eth_rw_clr_err 36 + +/* Register rw_mgm_ctrl, scope eth, type rw */ +typedef struct { + unsigned int mdio : 1; + unsigned int mdoe : 1; + unsigned int mdc : 1; + unsigned int dummy1 : 29; +} reg_eth_rw_mgm_ctrl; +#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 +#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 + +/* Register r_stat, scope eth, type r */ +typedef struct { + unsigned int mdio : 1; + unsigned int exc_col : 1; + unsigned int urun : 1; + unsigned int clk_125 : 1; + unsigned int dummy1 : 28; +} reg_eth_r_stat; +#define REG_RD_ADDR_eth_r_stat 44 + +/* Register rs_rec_cnt, scope eth, type rs */ +typedef struct { + unsigned int crc_err : 8; + unsigned int align_err : 8; + unsigned int oversize : 8; + unsigned int congestion : 8; +} reg_eth_rs_rec_cnt; +#define REG_RD_ADDR_eth_rs_rec_cnt 48 + +/* Register r_rec_cnt, scope eth, type r */ +typedef struct { + unsigned int crc_err : 8; + unsigned int align_err : 8; + unsigned int oversize : 8; + unsigned int congestion : 8; +} reg_eth_r_rec_cnt; +#define REG_RD_ADDR_eth_r_rec_cnt 52 + +/* Register rs_tr_cnt, scope eth, type rs */ +typedef struct { + unsigned int single_col : 8; + unsigned int mult_col : 8; + unsigned int late_col : 8; + unsigned int deferred : 8; +} reg_eth_rs_tr_cnt; +#define REG_RD_ADDR_eth_rs_tr_cnt 56 + +/* Register r_tr_cnt, scope eth, type r */ +typedef struct { + unsigned int single_col : 8; + unsigned int mult_col : 8; + unsigned int late_col : 8; + unsigned int deferred : 8; +} reg_eth_r_tr_cnt; +#define REG_RD_ADDR_eth_r_tr_cnt 60 + +/* Register rs_phy_cnt, scope eth, type rs */ +typedef struct { + unsigned int carrier_loss : 8; + unsigned int sqe_err : 8; + unsigned int dummy1 : 16; +} reg_eth_rs_phy_cnt; +#define REG_RD_ADDR_eth_rs_phy_cnt 64 + +/* Register r_phy_cnt, scope eth, type r */ +typedef struct { + unsigned int carrier_loss : 8; + unsigned int sqe_err : 8; + unsigned int dummy1 : 16; +} reg_eth_r_phy_cnt; +#define REG_RD_ADDR_eth_r_phy_cnt 68 + +/* Register rw_test_ctrl, scope eth, type rw */ +typedef struct { + unsigned int snmp_inc : 1; + unsigned int snmp : 1; + unsigned int backoff : 1; + unsigned int dummy1 : 29; +} reg_eth_rw_test_ctrl; +#define REG_RD_ADDR_eth_rw_test_ctrl 72 +#define REG_WR_ADDR_eth_rw_test_ctrl 72 + +/* Register rw_intr_mask, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_rw_intr_mask; +#define REG_RD_ADDR_eth_rw_intr_mask 76 +#define REG_WR_ADDR_eth_rw_intr_mask 76 + +/* Register rw_ack_intr, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_rw_ack_intr; +#define REG_RD_ADDR_eth_rw_ack_intr 80 +#define REG_WR_ADDR_eth_rw_ack_intr 80 + +/* Register r_intr, scope eth, type r */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_r_intr; +#define REG_RD_ADDR_eth_r_intr 84 + +/* Register r_masked_intr, scope eth, type r */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_r_masked_intr; +#define REG_RD_ADDR_eth_r_masked_intr 88 + + +/* Constants */ +enum { + regk_eth_discard = 0x00000000, + regk_eth_ether = 0x00000000, + regk_eth_full = 0x00000001, + regk_eth_gmii = 0x00000003, + regk_eth_gtxclk = 0x00000001, + regk_eth_half = 0x00000000, + regk_eth_hsh = 0x00000001, + regk_eth_mii = 0x00000001, + regk_eth_mii_arec = 0x00000002, + regk_eth_mii_clk = 0x00000000, + regk_eth_no = 0x00000000, + regk_eth_phyrst = 0x00000000, + regk_eth_rec = 0x00000001, + regk_eth_rw_ga_hi_default = 0x00000000, + regk_eth_rw_ga_lo_default = 0x00000000, + regk_eth_rw_gen_ctrl_default = 0x00000000, + regk_eth_rw_intr_mask_default = 0x00000000, + regk_eth_rw_ma0_hi_default = 0x00000000, + regk_eth_rw_ma0_lo_default = 0x00000000, + regk_eth_rw_ma1_hi_default = 0x00000000, + regk_eth_rw_ma1_lo_default = 0x00000000, + regk_eth_rw_mgm_ctrl_default = 0x00000000, + regk_eth_rw_test_ctrl_default = 0x00000000, + regk_eth_size1518 = 0x000005ee, + regk_eth_size1522 = 0x000005f2, + regk_eth_yes = 0x00000001 +}; +#endif /* __eth_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h b/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h new file mode 100644 index 000000000000..c47b5ca48ece --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h @@ -0,0 +1,369 @@ +#ifndef __extmem_defs_h +#define __extmem_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ext_mem/mod/extmem_regs.r + * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp + * last modfied: Tue Mar 30 22:26:21 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r + * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope extmem */ + +/* Register rw_cse0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_cse0_cfg; +#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 +#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 + +/* Register rw_cse1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_cse1_cfg; +#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 +#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 + +/* Register rw_csr0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csr0_cfg; +#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 +#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 + +/* Register rw_csr1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csr1_cfg; +#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 +#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 + +/* Register rw_csp0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp0_cfg; +#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 +#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 + +/* Register rw_csp1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp1_cfg; +#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 +#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 + +/* Register rw_csp2_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp2_cfg; +#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 +#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 + +/* Register rw_csp3_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp3_cfg; +#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 +#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 + +/* Register rw_csp4_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp4_cfg; +#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 +#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 + +/* Register rw_csp5_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp5_cfg; +#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 +#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 + +/* Register rw_csp6_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp6_cfg; +#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 +#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 + +/* Register rw_css_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_css_cfg; +#define REG_RD_ADDR_extmem_rw_css_cfg 44 +#define REG_WR_ADDR_extmem_rw_css_cfg 44 + +/* Register rw_status_handle, scope extmem, type rw */ +typedef struct { + unsigned int h : 32; +} reg_extmem_rw_status_handle; +#define REG_RD_ADDR_extmem_rw_status_handle 48 +#define REG_WR_ADDR_extmem_rw_status_handle 48 + +/* Register rw_wait_pin, scope extmem, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 15; + unsigned int start : 1; +} reg_extmem_rw_wait_pin; +#define REG_RD_ADDR_extmem_rw_wait_pin 52 +#define REG_WR_ADDR_extmem_rw_wait_pin 52 + +/* Register rw_gated_csp, scope extmem, type rw */ +typedef struct { + unsigned int dummy1 : 31; + unsigned int en : 1; +} reg_extmem_rw_gated_csp; +#define REG_RD_ADDR_extmem_rw_gated_csp 56 +#define REG_WR_ADDR_extmem_rw_gated_csp 56 + + +/* Constants */ +enum { + regk_extmem_b16 = 0x00000001, + regk_extmem_b32 = 0x00000000, + regk_extmem_bwe = 0x00000000, + regk_extmem_cwe = 0x00000001, + regk_extmem_no = 0x00000000, + regk_extmem_rw_cse0_cfg_default = 0x000006cf, + regk_extmem_rw_cse1_cfg_default = 0x000006cf, + regk_extmem_rw_csp0_cfg_default = 0x000006cf, + regk_extmem_rw_csp1_cfg_default = 0x000006cf, + regk_extmem_rw_csp2_cfg_default = 0x000006cf, + regk_extmem_rw_csp3_cfg_default = 0x000006cf, + regk_extmem_rw_csp4_cfg_default = 0x000006cf, + regk_extmem_rw_csp5_cfg_default = 0x000006cf, + regk_extmem_rw_csp6_cfg_default = 0x000006cf, + regk_extmem_rw_csr0_cfg_default = 0x000006cf, + regk_extmem_rw_csr1_cfg_default = 0x000006cf, + regk_extmem_rw_css_cfg_default = 0x000006cf, + regk_extmem_s128KB = 0x00000000, + regk_extmem_s16MB = 0x00000005, + regk_extmem_s1MB = 0x00000001, + regk_extmem_s2MB = 0x00000002, + regk_extmem_s32MB = 0x00000006, + regk_extmem_s4MB = 0x00000003, + regk_extmem_s64MB = 0x00000007, + regk_extmem_s8MB = 0x00000004, + regk_extmem_yes = 0x00000001 +}; +#endif /* __extmem_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile new file mode 100644 index 000000000000..a90056a095e3 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile @@ -0,0 +1,146 @@ +# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ +# Makefile to generate or copy the latest register definitions +# and related datastructures and helpermacros. +# The offical place for these files is probably at: +RELEASE ?= r1_alfa5 +IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ + +IOPROCDIR = /n/asic/design/io/io_proc/rtl + +IOPROCINCL_FILES = +IOPROCINCL_FILES2= +IOPROCINCL_FILES += iop_crc_par_defs.h +IOPROCINCL_FILES += iop_dmc_in_defs.h +IOPROCINCL_FILES += iop_dmc_out_defs.h +IOPROCINCL_FILES += iop_fifo_in_defs.h +IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h +IOPROCINCL_FILES += iop_fifo_out_defs.h +IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h +IOPROCINCL_FILES += iop_mpu_defs.h +IOPROCINCL_FILES2+= iop_mpu_macros.h +IOPROCINCL_FILES2+= iop_reg_space.h +IOPROCINCL_FILES += iop_sap_in_defs.h +IOPROCINCL_FILES += iop_sap_out_defs.h +IOPROCINCL_FILES += iop_scrc_in_defs.h +IOPROCINCL_FILES += iop_scrc_out_defs.h +IOPROCINCL_FILES += iop_spu_defs.h +# in guiness/ +IOPROCINCL_FILES += iop_sw_cfg_defs.h +IOPROCINCL_FILES += iop_sw_cpu_defs.h +IOPROCINCL_FILES += iop_sw_mpu_defs.h +IOPROCINCL_FILES += iop_sw_spu_defs.h +# +IOPROCINCL_FILES += iop_timer_grp_defs.h +IOPROCINCL_FILES += iop_trigger_grp_defs.h +# in guiness/ +IOPROCINCL_FILES += iop_version_defs.h + +IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) +IOPROCASMINCL_FILES+= iop_reg_space_asm.h + + +IOPROCREGDESC = +IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r +#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r +IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r +IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r +IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r +IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r +IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r + + +RDES2C = /n/asic/bin/rdes2c +RDES2C = /n/asic/design/tools/rdesc/rdes2c +RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr +RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt + +## all - Just print help - you probably want to do 'make gen' +all: help + +## help - This help +help: + @grep '^## ' Makefile + +## gen - Generate include files +gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) + echo "INCL: $(IOPROCINCL_FILES)" + echo "INCL2: $(IOPROCINCL_FILES2)" + echo "ASMINCL: $(IOPROCASMINCL_FILES)" + +# From the official location... +iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ + +## copy - Copy files from official location +copy: + @echo "## Copying and fixing iop files ##" + @for HFILE in $(IOPROCINCL_FILES); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @for HFILE in $(IOPROCINCL_FILES2); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @echo "## Copying and fixing iop asm files ##" + @for HFILE in $(IOPROCASMINCL_FILES); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ + done + +# I/O processor files: +## iop - Generate I/O processor include files +iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) +iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r + $(RDES2C) $< +iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r + $(RDES2C) $< +%_defs.h: $(IOPROCDIR)/%.r + $(RDES2C) $< +%_defs_asm.h: $(IOPROCDIR)/%.r + $(RDES2C) -asm $< +iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r + $(RDES2C) -asm $< + +## doc - Generate .axw files from register description. +doc: $(IOPROCREGDESC) + for RDES in $^; do \ + $(RDES2TXT) $$RDES; \ + done + +.PHONY: axw +## %.axw - Generate the specified .axw file (doesn't work for all files +## due to inconsistent naming of .r files. +%.axw: axw + @for RDES in $(IOPROCREGDESC); do \ + if echo "$$RDES" | grep $* ; then \ + $(RDES2TXT) $$RDES; \ + fi \ + done + +.PHONY: clean +## clean - Remove .h files and .axw files. +clean: + rm -rf $(IOPROCINCL_FILES) *.axw + +.PHONY: cleandoc +## cleandoc - Remove .axw files. +cleandoc: + rm -rf *.axw + diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h new file mode 100644 index 000000000000..a4b58000c164 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h @@ -0,0 +1,171 @@ +#ifndef __iop_crc_par_defs_asm_h +#define __iop_crc_par_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_crc_par.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r + * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_cfg___mode___lsb 0 +#define reg_iop_crc_par_rw_cfg___mode___width 1 +#define reg_iop_crc_par_rw_cfg___mode___bit 0 +#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 +#define reg_iop_crc_par_rw_cfg___crc_out___width 1 +#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 +#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 +#define reg_iop_crc_par_rw_cfg___rev_out___width 1 +#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 +#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 +#define reg_iop_crc_par_rw_cfg___inv_out___width 1 +#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 +#define reg_iop_crc_par_rw_cfg___trig___lsb 4 +#define reg_iop_crc_par_rw_cfg___trig___width 2 +#define reg_iop_crc_par_rw_cfg___poly___lsb 6 +#define reg_iop_crc_par_rw_cfg___poly___width 3 +#define reg_iop_crc_par_rw_cfg_offset 0 + +/* Register rw_init_crc, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_init_crc_offset 4 + +/* Register rw_correct_crc, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_correct_crc_offset 8 + +/* Register rw_ctrl, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_ctrl___en___lsb 0 +#define reg_iop_crc_par_rw_ctrl___en___width 1 +#define reg_iop_crc_par_rw_ctrl___en___bit 0 +#define reg_iop_crc_par_rw_ctrl_offset 12 + +/* Register rw_set_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 +#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 +#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 +#define reg_iop_crc_par_rw_set_last_offset 16 + +/* Register rw_wr1byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr1byte___data___width 8 +#define reg_iop_crc_par_rw_wr1byte_offset 20 + +/* Register rw_wr2byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr2byte___data___width 16 +#define reg_iop_crc_par_rw_wr2byte_offset 24 + +/* Register rw_wr3byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr3byte___data___width 24 +#define reg_iop_crc_par_rw_wr3byte_offset 28 + +/* Register rw_wr4byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr4byte___data___width 32 +#define reg_iop_crc_par_rw_wr4byte_offset 32 + +/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 +#define reg_iop_crc_par_rw_wr1byte_last_offset 36 + +/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 +#define reg_iop_crc_par_rw_wr2byte_last_offset 40 + +/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 +#define reg_iop_crc_par_rw_wr3byte_last_offset 44 + +/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 +#define reg_iop_crc_par_rw_wr4byte_last_offset 48 + +/* Register r_stat, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_stat___err___lsb 0 +#define reg_iop_crc_par_r_stat___err___width 1 +#define reg_iop_crc_par_r_stat___err___bit 0 +#define reg_iop_crc_par_r_stat___busy___lsb 1 +#define reg_iop_crc_par_r_stat___busy___width 1 +#define reg_iop_crc_par_r_stat___busy___bit 1 +#define reg_iop_crc_par_r_stat_offset 52 + +/* Register r_sh_reg, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_sh_reg_offset 56 + +/* Register r_crc, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_crc_offset 60 + +/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 +#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 +#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 + + +/* Constants */ +#define regk_iop_crc_par_calc 0x00000001 +#define regk_iop_crc_par_ccitt 0x00000002 +#define regk_iop_crc_par_check 0x00000000 +#define regk_iop_crc_par_crc16 0x00000001 +#define regk_iop_crc_par_crc32 0x00000000 +#define regk_iop_crc_par_crc5 0x00000003 +#define regk_iop_crc_par_crc5_11 0x00000004 +#define regk_iop_crc_par_dif_in 0x00000002 +#define regk_iop_crc_par_hi 0x00000000 +#define regk_iop_crc_par_neg 0x00000002 +#define regk_iop_crc_par_no 0x00000000 +#define regk_iop_crc_par_pos 0x00000001 +#define regk_iop_crc_par_pos_neg 0x00000003 +#define regk_iop_crc_par_rw_cfg_default 0x00000000 +#define regk_iop_crc_par_rw_ctrl_default 0x00000000 +#define regk_iop_crc_par_yes 0x00000001 +#endif /* __iop_crc_par_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h new file mode 100644 index 000000000000..e7d539feccb1 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h @@ -0,0 +1,321 @@ +#ifndef __iop_dmc_in_defs_asm_h +#define __iop_dmc_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_in.r + * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r + * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 +#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 +#define reg_iop_dmc_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 +#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 +#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 +#define reg_iop_dmc_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 +#define reg_iop_dmc_in_r_stat___dif_en___width 1 +#define reg_iop_dmc_in_r_stat___dif_en___bit 0 +#define reg_iop_dmc_in_r_stat_offset 8 + +/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 +#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 +#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 +#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 +#define reg_iop_dmc_in_rw_stream_cmd_offset 12 + +/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 + +/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 + +/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 +#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 +#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 +#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 +#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 + +/* Register r_stream_stat, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 +#define reg_iop_dmc_in_r_stream_stat___sth___width 7 +#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 +#define reg_iop_dmc_in_r_stream_stat___full___width 1 +#define reg_iop_dmc_in_r_stream_stat___full___bit 16 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 +#define reg_iop_dmc_in_r_stream_stat_offset 28 + +/* Register r_data_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_data_descr___stat___width 8 +#define reg_iop_dmc_in_r_data_descr___md___lsb 16 +#define reg_iop_dmc_in_r_data_descr___md___width 16 +#define reg_iop_dmc_in_r_data_descr_offset 32 + +/* Register r_ctxt_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 +#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 +#define reg_iop_dmc_in_r_ctxt_descr_offset 36 + +/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 + +/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 + +/* Register r_group_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_group_descr___stat___width 8 +#define reg_iop_dmc_in_r_group_descr___md___lsb 16 +#define reg_iop_dmc_in_r_group_descr___md___width 16 +#define reg_iop_dmc_in_r_group_descr_offset 56 + +/* Register rw_data_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 +#define reg_iop_dmc_in_rw_data_descr___md___width 16 +#define reg_iop_dmc_in_rw_data_descr_offset 60 + +/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 +#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 + +/* Register rw_group_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 +#define reg_iop_dmc_in_rw_group_descr___md___width 16 +#define reg_iop_dmc_in_rw_group_descr_offset 84 + +/* Register rw_intr_mask, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 +#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 +#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 +#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 +#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 +#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 +#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 +#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 +#define reg_iop_dmc_in_rw_intr_mask___full___width 1 +#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 +#define reg_iop_dmc_in_rw_intr_mask_offset 88 + +/* Register rw_ack_intr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 +#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 +#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 +#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 +#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 +#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 +#define reg_iop_dmc_in_rw_ack_intr___full___width 1 +#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 +#define reg_iop_dmc_in_rw_ack_intr_offset 92 + +/* Register r_intr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_intr___data_md___lsb 0 +#define reg_iop_dmc_in_r_intr___data_md___width 1 +#define reg_iop_dmc_in_r_intr___data_md___bit 0 +#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_r_intr___group_md___lsb 2 +#define reg_iop_dmc_in_r_intr___group_md___width 1 +#define reg_iop_dmc_in_r_intr___group_md___bit 2 +#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_r_intr___sth___lsb 4 +#define reg_iop_dmc_in_r_intr___sth___width 1 +#define reg_iop_dmc_in_r_intr___sth___bit 4 +#define reg_iop_dmc_in_r_intr___full___lsb 5 +#define reg_iop_dmc_in_r_intr___full___width 1 +#define reg_iop_dmc_in_r_intr___full___bit 5 +#define reg_iop_dmc_in_r_intr_offset 96 + +/* Register r_masked_intr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 +#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 +#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 +#define reg_iop_dmc_in_r_masked_intr___sth___width 1 +#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 +#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 +#define reg_iop_dmc_in_r_masked_intr___full___width 1 +#define reg_iop_dmc_in_r_masked_intr___full___bit 5 +#define reg_iop_dmc_in_r_masked_intr_offset 100 + + +/* Constants */ +#define regk_iop_dmc_in_ack_pkt 0x00000100 +#define regk_iop_dmc_in_array 0x00000008 +#define regk_iop_dmc_in_burst 0x00000020 +#define regk_iop_dmc_in_copy_next 0x00000010 +#define regk_iop_dmc_in_copy_up 0x00000020 +#define regk_iop_dmc_in_dis_c 0x00000010 +#define regk_iop_dmc_in_dis_g 0x00000020 +#define regk_iop_dmc_in_lim1 0x00000000 +#define regk_iop_dmc_in_lim16 0x00000004 +#define regk_iop_dmc_in_lim2 0x00000001 +#define regk_iop_dmc_in_lim32 0x00000005 +#define regk_iop_dmc_in_lim4 0x00000002 +#define regk_iop_dmc_in_lim64 0x00000006 +#define regk_iop_dmc_in_lim8 0x00000003 +#define regk_iop_dmc_in_load_c 0x00000200 +#define regk_iop_dmc_in_load_c_n 0x00000280 +#define regk_iop_dmc_in_load_c_next 0x00000240 +#define regk_iop_dmc_in_load_d 0x00000140 +#define regk_iop_dmc_in_load_g 0x00000300 +#define regk_iop_dmc_in_load_g_down 0x000003c0 +#define regk_iop_dmc_in_load_g_next 0x00000340 +#define regk_iop_dmc_in_load_g_up 0x00000380 +#define regk_iop_dmc_in_next_en 0x00000010 +#define regk_iop_dmc_in_next_pkt 0x00000010 +#define regk_iop_dmc_in_no 0x00000000 +#define regk_iop_dmc_in_restore 0x00000020 +#define regk_iop_dmc_in_rw_cfg_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 +#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 +#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 +#define regk_iop_dmc_in_save_down 0x00000020 +#define regk_iop_dmc_in_save_up 0x00000020 +#define regk_iop_dmc_in_set_reg 0x00000050 +#define regk_iop_dmc_in_set_w_size1 0x00000190 +#define regk_iop_dmc_in_set_w_size2 0x000001a0 +#define regk_iop_dmc_in_set_w_size4 0x000001c0 +#define regk_iop_dmc_in_store_c 0x00000002 +#define regk_iop_dmc_in_store_descr 0x00000000 +#define regk_iop_dmc_in_store_g 0x00000004 +#define regk_iop_dmc_in_store_md 0x00000001 +#define regk_iop_dmc_in_update_down 0x00000020 +#define regk_iop_dmc_in_yes 0x00000001 +#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h new file mode 100644 index 000000000000..9fe1a8054371 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h @@ -0,0 +1,349 @@ +#ifndef __iop_dmc_out_defs_asm_h +#define __iop_dmc_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_out.r + * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r + * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 +#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 +#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 +#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 +#define reg_iop_dmc_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 +#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 +#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 +#define reg_iop_dmc_out_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 +#define reg_iop_dmc_out_r_stat___dif_en___width 1 +#define reg_iop_dmc_out_r_stat___dif_en___bit 0 +#define reg_iop_dmc_out_r_stat_offset 8 + +/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 +#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 +#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 +#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 +#define reg_iop_dmc_out_rw_stream_cmd_offset 12 + +/* Register rs_stream_data, scope iop_dmc_out, type rs */ +#define reg_iop_dmc_out_rs_stream_data_offset 16 + +/* Register r_stream_data, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stream_data_offset 20 + +/* Register r_stream_stat, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 +#define reg_iop_dmc_out_r_stream_stat___dth___width 7 +#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 +#define reg_iop_dmc_out_r_stream_stat___dv___width 1 +#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 +#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 +#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 +#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 +#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 +#define reg_iop_dmc_out_r_stream_stat___last___width 1 +#define reg_iop_dmc_out_r_stream_stat___last___bit 18 +#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 +#define reg_iop_dmc_out_r_stream_stat___size___width 3 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 +#define reg_iop_dmc_out_r_stream_stat_offset 24 + +/* Register r_data_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_data_descr___stat___width 8 +#define reg_iop_dmc_out_r_data_descr___md___lsb 16 +#define reg_iop_dmc_out_r_data_descr___md___width 16 +#define reg_iop_dmc_out_r_data_descr_offset 28 + +/* Register r_ctxt_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 +#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 +#define reg_iop_dmc_out_r_ctxt_descr_offset 32 + +/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 + +/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 + +/* Register r_group_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_group_descr___stat___width 8 +#define reg_iop_dmc_out_r_group_descr___md___lsb 16 +#define reg_iop_dmc_out_r_group_descr___md___width 16 +#define reg_iop_dmc_out_r_group_descr_offset 52 + +/* Register rw_data_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 +#define reg_iop_dmc_out_rw_data_descr___md___width 16 +#define reg_iop_dmc_out_rw_data_descr_offset 56 + +/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 +#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 + +/* Register rw_group_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 +#define reg_iop_dmc_out_rw_group_descr___md___width 16 +#define reg_iop_dmc_out_rw_group_descr_offset 80 + +/* Register rw_intr_mask, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 +#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 +#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 +#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 +#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 +#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 +#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 +#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 +#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 +#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 +#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 +#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 +#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 +#define reg_iop_dmc_out_rw_intr_mask_offset 84 + +/* Register rw_ack_intr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 +#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 +#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 +#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 +#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 +#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 +#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 +#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 +#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 +#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 +#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_rw_ack_intr_offset 88 + +/* Register r_intr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_intr___data_md___lsb 0 +#define reg_iop_dmc_out_r_intr___data_md___width 1 +#define reg_iop_dmc_out_r_intr___data_md___bit 0 +#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_r_intr___group_md___lsb 2 +#define reg_iop_dmc_out_r_intr___group_md___width 1 +#define reg_iop_dmc_out_r_intr___group_md___bit 2 +#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_r_intr___dth___lsb 4 +#define reg_iop_dmc_out_r_intr___dth___width 1 +#define reg_iop_dmc_out_r_intr___dth___bit 4 +#define reg_iop_dmc_out_r_intr___dv___lsb 5 +#define reg_iop_dmc_out_r_intr___dv___width 1 +#define reg_iop_dmc_out_r_intr___dv___bit 5 +#define reg_iop_dmc_out_r_intr___last_data___lsb 6 +#define reg_iop_dmc_out_r_intr___last_data___width 1 +#define reg_iop_dmc_out_r_intr___last_data___bit 6 +#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_r_intr___trf_lim___width 1 +#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_r_intr_offset 92 + +/* Register r_masked_intr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 +#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 +#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 +#define reg_iop_dmc_out_r_masked_intr___dth___width 1 +#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 +#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 +#define reg_iop_dmc_out_r_masked_intr___dv___width 1 +#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 +#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 +#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 +#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_r_masked_intr_offset 96 + + +/* Constants */ +#define regk_iop_dmc_out_ack_pkt 0x00000100 +#define regk_iop_dmc_out_array 0x00000008 +#define regk_iop_dmc_out_burst 0x00000020 +#define regk_iop_dmc_out_copy_next 0x00000010 +#define regk_iop_dmc_out_copy_up 0x00000020 +#define regk_iop_dmc_out_dis_c 0x00000010 +#define regk_iop_dmc_out_dis_g 0x00000020 +#define regk_iop_dmc_out_lim1 0x00000000 +#define regk_iop_dmc_out_lim16 0x00000004 +#define regk_iop_dmc_out_lim2 0x00000001 +#define regk_iop_dmc_out_lim32 0x00000005 +#define regk_iop_dmc_out_lim4 0x00000002 +#define regk_iop_dmc_out_lim64 0x00000006 +#define regk_iop_dmc_out_lim8 0x00000003 +#define regk_iop_dmc_out_load_c 0x00000200 +#define regk_iop_dmc_out_load_c_n 0x00000280 +#define regk_iop_dmc_out_load_c_next 0x00000240 +#define regk_iop_dmc_out_load_d 0x00000140 +#define regk_iop_dmc_out_load_g 0x00000300 +#define regk_iop_dmc_out_load_g_down 0x000003c0 +#define regk_iop_dmc_out_load_g_next 0x00000340 +#define regk_iop_dmc_out_load_g_up 0x00000380 +#define regk_iop_dmc_out_next_en 0x00000010 +#define regk_iop_dmc_out_next_pkt 0x00000010 +#define regk_iop_dmc_out_no 0x00000000 +#define regk_iop_dmc_out_restore 0x00000020 +#define regk_iop_dmc_out_rw_cfg_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 +#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 +#define regk_iop_dmc_out_save_down 0x00000020 +#define regk_iop_dmc_out_save_up 0x00000020 +#define regk_iop_dmc_out_set_reg 0x00000050 +#define regk_iop_dmc_out_set_w_size1 0x00000190 +#define regk_iop_dmc_out_set_w_size2 0x000001a0 +#define regk_iop_dmc_out_set_w_size4 0x000001c0 +#define regk_iop_dmc_out_store_c 0x00000002 +#define regk_iop_dmc_out_store_descr 0x00000000 +#define regk_iop_dmc_out_store_g 0x00000004 +#define regk_iop_dmc_out_store_md 0x00000001 +#define regk_iop_dmc_out_update_down 0x00000020 +#define regk_iop_dmc_out_yes 0x00000001 +#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h new file mode 100644 index 000000000000..974dee082f9f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h @@ -0,0 +1,234 @@ +#ifndef __iop_fifo_in_defs_asm_h +#define __iop_fifo_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in.r + * id: + * last modfied: Mon Apr 11 16:10:07 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r + * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 +#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 +#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 +#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 +#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 +#define reg_iop_fifo_in_rw_cfg___trig___width 2 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 +#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 +#define reg_iop_fifo_in_rw_cfg___mode___width 2 +#define reg_iop_fifo_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 +#define reg_iop_fifo_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_in_r_stat___last___lsb 4 +#define reg_iop_fifo_in_r_stat___last___width 8 +#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_in_r_stat_offset 8 + +/* Register rs_rd1byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd1byte___data___width 8 +#define reg_iop_fifo_in_rs_rd1byte_offset 12 + +/* Register r_rd1byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd1byte___data___width 8 +#define reg_iop_fifo_in_r_rd1byte_offset 16 + +/* Register rs_rd2byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd2byte___data___width 16 +#define reg_iop_fifo_in_rs_rd2byte_offset 20 + +/* Register r_rd2byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd2byte___data___width 16 +#define reg_iop_fifo_in_r_rd2byte_offset 24 + +/* Register rs_rd3byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd3byte___data___width 24 +#define reg_iop_fifo_in_rs_rd3byte_offset 28 + +/* Register r_rd3byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd3byte___data___width 24 +#define reg_iop_fifo_in_r_rd3byte_offset 32 + +/* Register rs_rd4byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd4byte___data___width 32 +#define reg_iop_fifo_in_rs_rd4byte_offset 36 + +/* Register r_rd4byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd4byte___data___width 32 +#define reg_iop_fifo_in_r_rd4byte_offset 40 + +/* Register rw_set_last, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_set_last_offset 44 + +/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 +#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 +#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 + +/* Register rw_intr_mask, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 +#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 +#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 +#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_in_rw_intr_mask_offset 52 + +/* Register rw_ack_intr, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 +#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 +#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 +#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_in_rw_ack_intr_offset 56 + +/* Register r_intr, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_intr___urun___lsb 0 +#define reg_iop_fifo_in_r_intr___urun___width 1 +#define reg_iop_fifo_in_r_intr___urun___bit 0 +#define reg_iop_fifo_in_r_intr___last_data___lsb 1 +#define reg_iop_fifo_in_r_intr___last_data___width 1 +#define reg_iop_fifo_in_r_intr___last_data___bit 1 +#define reg_iop_fifo_in_r_intr___dav___lsb 2 +#define reg_iop_fifo_in_r_intr___dav___width 1 +#define reg_iop_fifo_in_r_intr___dav___bit 2 +#define reg_iop_fifo_in_r_intr___avail___lsb 3 +#define reg_iop_fifo_in_r_intr___avail___width 1 +#define reg_iop_fifo_in_r_intr___avail___bit 3 +#define reg_iop_fifo_in_r_intr___orun___lsb 4 +#define reg_iop_fifo_in_r_intr___orun___width 1 +#define reg_iop_fifo_in_r_intr___orun___bit 4 +#define reg_iop_fifo_in_r_intr_offset 60 + +/* Register r_masked_intr, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_in_r_masked_intr___urun___width 1 +#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_in_r_masked_intr___dav___width 1 +#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 +#define reg_iop_fifo_in_r_masked_intr___avail___width 1 +#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 +#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_in_r_masked_intr___orun___width 1 +#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_in_r_masked_intr_offset 64 + + +/* Constants */ +#define regk_iop_fifo_in_dif_in 0x00000002 +#define regk_iop_fifo_in_hi 0x00000000 +#define regk_iop_fifo_in_neg 0x00000002 +#define regk_iop_fifo_in_no 0x00000000 +#define regk_iop_fifo_in_order16 0x00000001 +#define regk_iop_fifo_in_order24 0x00000002 +#define regk_iop_fifo_in_order32 0x00000003 +#define regk_iop_fifo_in_order8 0x00000000 +#define regk_iop_fifo_in_pos 0x00000001 +#define regk_iop_fifo_in_pos_neg 0x00000003 +#define regk_iop_fifo_in_rw_cfg_default 0x00000024 +#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 +#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_in_rw_set_last_default 0x00000000 +#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 +#define regk_iop_fifo_in_size16 0x00000002 +#define regk_iop_fifo_in_size24 0x00000001 +#define regk_iop_fifo_in_size32 0x00000000 +#define regk_iop_fifo_in_size8 0x00000003 +#define regk_iop_fifo_in_yes 0x00000001 +#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h new file mode 100644 index 000000000000..e00fab0c9335 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h @@ -0,0 +1,155 @@ +#ifndef __iop_fifo_in_extra_defs_asm_h +#define __iop_fifo_in_extra_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: + * last modfied: Mon Apr 11 16:10:08 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 + +/* Register r_stat, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 +#define reg_iop_fifo_in_extra_r_stat___last___width 8 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_in_extra_r_stat_offset 4 + +/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 +#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 +#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 + +/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 + +/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 + +/* Register r_intr, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_r_intr___urun___width 1 +#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_r_intr___dav___width 1 +#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_r_intr___avail___width 1 +#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_r_intr___orun___width 1 +#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_r_intr_offset 20 + +/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 + + +/* Constants */ +#define regk_iop_fifo_in_extra_fifo_in 0x00000002 +#define regk_iop_fifo_in_extra_no 0x00000000 +#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_in_extra_yes 0x00000001 +#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h new file mode 100644 index 000000000000..9ec5f4a826df --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h @@ -0,0 +1,254 @@ +#ifndef __iop_fifo_out_defs_asm_h +#define __iop_fifo_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out.r + * id: + * last modfied: Mon Apr 11 16:10:09 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r + * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 +#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 +#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 +#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 +#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 +#define reg_iop_fifo_out_rw_cfg___trig___width 2 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 +#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 +#define reg_iop_fifo_out_rw_cfg___mode___width 2 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 +#define reg_iop_fifo_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 +#define reg_iop_fifo_out_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_out_r_stat___last___lsb 4 +#define reg_iop_fifo_out_r_stat___last___width 8 +#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 +#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 +#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 +#define reg_iop_fifo_out_r_stat_offset 8 + +/* Register rw_wr1byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr1byte___data___width 8 +#define reg_iop_fifo_out_rw_wr1byte_offset 12 + +/* Register rw_wr2byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr2byte___data___width 16 +#define reg_iop_fifo_out_rw_wr2byte_offset 16 + +/* Register rw_wr3byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr3byte___data___width 24 +#define reg_iop_fifo_out_rw_wr3byte_offset 20 + +/* Register rw_wr4byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr4byte___data___width 32 +#define reg_iop_fifo_out_rw_wr4byte_offset 24 + +/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 +#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 + +/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 +#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 + +/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 +#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 + +/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 +#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 + +/* Register rw_set_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_set_last_offset 44 + +/* Register rs_rd_data, scope iop_fifo_out, type rs */ +#define reg_iop_fifo_out_rs_rd_data_offset 48 + +/* Register r_rd_data, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_rd_data_offset 52 + +/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 + +/* Register rw_intr_mask, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 +#define reg_iop_fifo_out_rw_intr_mask___free___width 1 +#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 +#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_out_rw_intr_mask_offset 60 + +/* Register rw_ack_intr, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 +#define reg_iop_fifo_out_rw_ack_intr___free___width 1 +#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 +#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_out_rw_ack_intr_offset 64 + +/* Register r_intr, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_intr___urun___lsb 0 +#define reg_iop_fifo_out_r_intr___urun___width 1 +#define reg_iop_fifo_out_r_intr___urun___bit 0 +#define reg_iop_fifo_out_r_intr___last_data___lsb 1 +#define reg_iop_fifo_out_r_intr___last_data___width 1 +#define reg_iop_fifo_out_r_intr___last_data___bit 1 +#define reg_iop_fifo_out_r_intr___dav___lsb 2 +#define reg_iop_fifo_out_r_intr___dav___width 1 +#define reg_iop_fifo_out_r_intr___dav___bit 2 +#define reg_iop_fifo_out_r_intr___free___lsb 3 +#define reg_iop_fifo_out_r_intr___free___width 1 +#define reg_iop_fifo_out_r_intr___free___bit 3 +#define reg_iop_fifo_out_r_intr___orun___lsb 4 +#define reg_iop_fifo_out_r_intr___orun___width 1 +#define reg_iop_fifo_out_r_intr___orun___bit 4 +#define reg_iop_fifo_out_r_intr_offset 68 + +/* Register r_masked_intr, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_out_r_masked_intr___urun___width 1 +#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_out_r_masked_intr___dav___width 1 +#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 +#define reg_iop_fifo_out_r_masked_intr___free___width 1 +#define reg_iop_fifo_out_r_masked_intr___free___bit 3 +#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_out_r_masked_intr___orun___width 1 +#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_out_r_masked_intr_offset 72 + + +/* Constants */ +#define regk_iop_fifo_out_hi 0x00000000 +#define regk_iop_fifo_out_neg 0x00000002 +#define regk_iop_fifo_out_no 0x00000000 +#define regk_iop_fifo_out_order16 0x00000001 +#define regk_iop_fifo_out_order24 0x00000002 +#define regk_iop_fifo_out_order32 0x00000003 +#define regk_iop_fifo_out_order8 0x00000000 +#define regk_iop_fifo_out_pos 0x00000001 +#define regk_iop_fifo_out_pos_neg 0x00000003 +#define regk_iop_fifo_out_rw_cfg_default 0x00000024 +#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 +#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_out_rw_set_last_default 0x00000000 +#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 +#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 +#define regk_iop_fifo_out_size16 0x00000002 +#define regk_iop_fifo_out_size24 0x00000001 +#define regk_iop_fifo_out_size32 0x00000000 +#define regk_iop_fifo_out_size8 0x00000003 +#define regk_iop_fifo_out_yes 0x00000001 +#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h new file mode 100644 index 000000000000..0f84a50cf77c --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h @@ -0,0 +1,158 @@ +#ifndef __iop_fifo_out_extra_defs_asm_h +#define __iop_fifo_out_extra_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: + * last modfied: Mon Apr 11 16:10:10 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ +#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 + +/* Register r_rd_data, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_rd_data_offset 4 + +/* Register r_stat, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 +#define reg_iop_fifo_out_extra_r_stat___last___width 8 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 +#define reg_iop_fifo_out_extra_r_stat_offset 8 + +/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 + +/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 + +/* Register r_intr, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_r_intr___urun___width 1 +#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_r_intr___dav___width 1 +#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_r_intr___free___width 1 +#define reg_iop_fifo_out_extra_r_intr___free___bit 3 +#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_r_intr___orun___width 1 +#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_r_intr_offset 24 + +/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 + + +/* Constants */ +#define regk_iop_fifo_out_extra_no 0x00000000 +#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_out_extra_yes 0x00000001 +#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h new file mode 100644 index 000000000000..80490c82cc29 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h @@ -0,0 +1,177 @@ +#ifndef __iop_mpu_defs_asm_h +#define __iop_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_mpu.r + * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r + * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_mpu_rw_r 4 +/* Register rw_r, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_r_offset 0 + +/* Register rw_ctrl, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_ctrl___en___lsb 0 +#define reg_iop_mpu_rw_ctrl___en___width 1 +#define reg_iop_mpu_rw_ctrl___en___bit 0 +#define reg_iop_mpu_rw_ctrl_offset 128 + +/* Register r_pc, scope iop_mpu, type r */ +#define reg_iop_mpu_r_pc___addr___lsb 0 +#define reg_iop_mpu_r_pc___addr___width 12 +#define reg_iop_mpu_r_pc_offset 132 + +/* Register r_stat, scope iop_mpu, type r */ +#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 +#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 +#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 +#define reg_iop_mpu_r_stat___intr_busy___lsb 1 +#define reg_iop_mpu_r_stat___intr_busy___width 1 +#define reg_iop_mpu_r_stat___intr_busy___bit 1 +#define reg_iop_mpu_r_stat___intr_vect___lsb 2 +#define reg_iop_mpu_r_stat___intr_vect___width 16 +#define reg_iop_mpu_r_stat_offset 136 + +/* Register rw_instr, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_instr_offset 140 + +/* Register rw_immediate, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_immediate_offset 144 + +/* Register r_trace, scope iop_mpu, type r */ +#define reg_iop_mpu_r_trace___intr_vect___lsb 0 +#define reg_iop_mpu_r_trace___intr_vect___width 16 +#define reg_iop_mpu_r_trace___pc___lsb 16 +#define reg_iop_mpu_r_trace___pc___width 12 +#define reg_iop_mpu_r_trace___en___lsb 28 +#define reg_iop_mpu_r_trace___en___width 1 +#define reg_iop_mpu_r_trace___en___bit 28 +#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 +#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 +#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 +#define reg_iop_mpu_r_trace___intr_busy___lsb 30 +#define reg_iop_mpu_r_trace___intr_busy___width 1 +#define reg_iop_mpu_r_trace___intr_busy___bit 30 +#define reg_iop_mpu_r_trace_offset 148 + +/* Register r_wr_stat, scope iop_mpu, type r */ +#define reg_iop_mpu_r_wr_stat___r0___lsb 0 +#define reg_iop_mpu_r_wr_stat___r0___width 1 +#define reg_iop_mpu_r_wr_stat___r0___bit 0 +#define reg_iop_mpu_r_wr_stat___r1___lsb 1 +#define reg_iop_mpu_r_wr_stat___r1___width 1 +#define reg_iop_mpu_r_wr_stat___r1___bit 1 +#define reg_iop_mpu_r_wr_stat___r2___lsb 2 +#define reg_iop_mpu_r_wr_stat___r2___width 1 +#define reg_iop_mpu_r_wr_stat___r2___bit 2 +#define reg_iop_mpu_r_wr_stat___r3___lsb 3 +#define reg_iop_mpu_r_wr_stat___r3___width 1 +#define reg_iop_mpu_r_wr_stat___r3___bit 3 +#define reg_iop_mpu_r_wr_stat___r4___lsb 4 +#define reg_iop_mpu_r_wr_stat___r4___width 1 +#define reg_iop_mpu_r_wr_stat___r4___bit 4 +#define reg_iop_mpu_r_wr_stat___r5___lsb 5 +#define reg_iop_mpu_r_wr_stat___r5___width 1 +#define reg_iop_mpu_r_wr_stat___r5___bit 5 +#define reg_iop_mpu_r_wr_stat___r6___lsb 6 +#define reg_iop_mpu_r_wr_stat___r6___width 1 +#define reg_iop_mpu_r_wr_stat___r6___bit 6 +#define reg_iop_mpu_r_wr_stat___r7___lsb 7 +#define reg_iop_mpu_r_wr_stat___r7___width 1 +#define reg_iop_mpu_r_wr_stat___r7___bit 7 +#define reg_iop_mpu_r_wr_stat___r8___lsb 8 +#define reg_iop_mpu_r_wr_stat___r8___width 1 +#define reg_iop_mpu_r_wr_stat___r8___bit 8 +#define reg_iop_mpu_r_wr_stat___r9___lsb 9 +#define reg_iop_mpu_r_wr_stat___r9___width 1 +#define reg_iop_mpu_r_wr_stat___r9___bit 9 +#define reg_iop_mpu_r_wr_stat___r10___lsb 10 +#define reg_iop_mpu_r_wr_stat___r10___width 1 +#define reg_iop_mpu_r_wr_stat___r10___bit 10 +#define reg_iop_mpu_r_wr_stat___r11___lsb 11 +#define reg_iop_mpu_r_wr_stat___r11___width 1 +#define reg_iop_mpu_r_wr_stat___r11___bit 11 +#define reg_iop_mpu_r_wr_stat___r12___lsb 12 +#define reg_iop_mpu_r_wr_stat___r12___width 1 +#define reg_iop_mpu_r_wr_stat___r12___bit 12 +#define reg_iop_mpu_r_wr_stat___r13___lsb 13 +#define reg_iop_mpu_r_wr_stat___r13___width 1 +#define reg_iop_mpu_r_wr_stat___r13___bit 13 +#define reg_iop_mpu_r_wr_stat___r14___lsb 14 +#define reg_iop_mpu_r_wr_stat___r14___width 1 +#define reg_iop_mpu_r_wr_stat___r14___bit 14 +#define reg_iop_mpu_r_wr_stat___r15___lsb 15 +#define reg_iop_mpu_r_wr_stat___r15___width 1 +#define reg_iop_mpu_r_wr_stat___r15___bit 15 +#define reg_iop_mpu_r_wr_stat_offset 152 + +#define STRIDE_iop_mpu_rw_thread 4 +/* Register rw_thread, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_thread___addr___lsb 0 +#define reg_iop_mpu_rw_thread___addr___width 12 +#define reg_iop_mpu_rw_thread_offset 156 + +#define STRIDE_iop_mpu_rw_intr 4 +/* Register rw_intr, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_intr___addr___lsb 0 +#define reg_iop_mpu_rw_intr___addr___width 12 +#define reg_iop_mpu_rw_intr_offset 196 + + +/* Constants */ +#define regk_iop_mpu_no 0x00000000 +#define regk_iop_mpu_r_pc_default 0x00000000 +#define regk_iop_mpu_rw_ctrl_default 0x00000000 +#define regk_iop_mpu_rw_intr_size 0x00000010 +#define regk_iop_mpu_rw_r_size 0x00000010 +#define regk_iop_mpu_rw_thread_default 0x00000000 +#define regk_iop_mpu_rw_thread_size 0x00000004 +#define regk_iop_mpu_yes 0x00000001 +#endif /* __iop_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 000000000000..a20b8857b4d0 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h @@ -0,0 +1,44 @@ +/* Autogenerated Changes here will be lost! + * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg + */ +#define iop_version 0 +#define iop_fifo_in0_extra 64 +#define iop_fifo_in1_extra 128 +#define iop_fifo_out0_extra 192 +#define iop_fifo_out1_extra 256 +#define iop_trigger_grp0 320 +#define iop_trigger_grp1 384 +#define iop_trigger_grp2 448 +#define iop_trigger_grp3 512 +#define iop_trigger_grp4 576 +#define iop_trigger_grp5 640 +#define iop_trigger_grp6 704 +#define iop_trigger_grp7 768 +#define iop_crc_par0 896 +#define iop_crc_par1 1024 +#define iop_dmc_in0 1152 +#define iop_dmc_in1 1280 +#define iop_dmc_out0 1408 +#define iop_dmc_out1 1536 +#define iop_fifo_in0 1664 +#define iop_fifo_in1 1792 +#define iop_fifo_out0 1920 +#define iop_fifo_out1 2048 +#define iop_scrc_in0 2176 +#define iop_scrc_in1 2304 +#define iop_scrc_out0 2432 +#define iop_scrc_out1 2560 +#define iop_timer_grp0 2688 +#define iop_timer_grp1 2816 +#define iop_timer_grp2 2944 +#define iop_timer_grp3 3072 +#define iop_sap_in 3328 +#define iop_sap_out 3584 +#define iop_spu0 3840 +#define iop_spu1 4096 +#define iop_sw_cfg 4352 +#define iop_sw_cpu 4608 +#define iop_sw_mpu 4864 +#define iop_sw_spu0 5120 +#define iop_sw_spu1 5376 +#define iop_mpu 5632 diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 000000000000..a4a10ff300b3 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h @@ -0,0 +1,182 @@ +#ifndef __iop_sap_in_defs_asm_h +#define __iop_sap_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_in.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r + * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_bus0_sync, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 +#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 +#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 +#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 +#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 +#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 +#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 +#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 +#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 +#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 +#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 +#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 +#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 +#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 +#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 +#define reg_iop_sap_in_rw_bus0_sync_offset 0 + +/* Register rw_bus1_sync, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 +#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 +#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 +#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 +#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 +#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 +#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 +#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 +#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 +#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 +#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 +#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 +#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 +#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 +#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 +#define reg_iop_sap_in_rw_bus1_sync_offset 4 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_gio___sync_sel___width 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_gio___sync_edge___width 2 +#define reg_iop_sap_in_rw_gio___delay___lsb 7 +#define reg_iop_sap_in_rw_gio___delay___width 1 +#define reg_iop_sap_in_rw_gio___delay___bit 7 +#define reg_iop_sap_in_rw_gio___logic___lsb 8 +#define reg_iop_sap_in_rw_gio___logic___width 2 +#define reg_iop_sap_in_rw_gio_offset 8 + + +/* Constants */ +#define regk_iop_sap_in_and 0x00000002 +#define regk_iop_sap_in_ext_clk200 0x00000003 +#define regk_iop_sap_in_gio1 0x00000000 +#define regk_iop_sap_in_gio13 0x00000005 +#define regk_iop_sap_in_gio18 0x00000003 +#define regk_iop_sap_in_gio19 0x00000004 +#define regk_iop_sap_in_gio21 0x00000006 +#define regk_iop_sap_in_gio23 0x00000005 +#define regk_iop_sap_in_gio29 0x00000007 +#define regk_iop_sap_in_gio5 0x00000004 +#define regk_iop_sap_in_gio6 0x00000001 +#define regk_iop_sap_in_gio7 0x00000002 +#define regk_iop_sap_in_inv 0x00000001 +#define regk_iop_sap_in_neg 0x00000002 +#define regk_iop_sap_in_no 0x00000000 +#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 +#define regk_iop_sap_in_none 0x00000000 +#define regk_iop_sap_in_or 0x00000003 +#define regk_iop_sap_in_pos 0x00000001 +#define regk_iop_sap_in_pos_neg 0x00000003 +#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 +#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 +#define regk_iop_sap_in_rw_gio_default 0x00000002 +#define regk_iop_sap_in_rw_gio_size 0x00000020 +#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 +#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 +#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 +#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 +#define regk_iop_sap_in_tmr_clk200 0x00000000 +#define regk_iop_sap_in_two_clk200 0x00000002 +#define regk_iop_sap_in_yes 0x00000001 +#endif /* __iop_sap_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 000000000000..0ec727f92a25 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h @@ -0,0 +1,346 @@ +#ifndef __iop_sap_out_defs_asm_h +#define __iop_sap_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_out.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r + * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 +#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 +#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 +#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 +#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 +#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 +#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 +#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated_offset 0 + +/* Register rw_bus0, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 +#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 +#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 +#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 +#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 +#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 +#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 +#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 +#define reg_iop_sap_out_rw_bus0_offset 4 + +/* Register rw_bus1, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 +#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 +#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 +#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 +#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 +#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 +#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 +#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 +#define reg_iop_sap_out_rw_bus1_offset 8 + +/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 + +/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 + +/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 + +/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 +#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 +#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 +#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 +#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 +#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 +#define reg_iop_sap_out_rw_gio___out_logic___width 1 +#define reg_iop_sap_out_rw_gio___out_logic___bit 10 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 +#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 +#define reg_iop_sap_out_rw_gio___oe_logic___width 2 +#define reg_iop_sap_out_rw_gio_offset 28 + + +/* Constants */ +#define regk_iop_sap_out_and 0x00000002 +#define regk_iop_sap_out_clk0 0x00000000 +#define regk_iop_sap_out_clk1 0x00000001 +#define regk_iop_sap_out_clk12 0x00000002 +#define regk_iop_sap_out_clk2 0x00000002 +#define regk_iop_sap_out_clk200 0x00000001 +#define regk_iop_sap_out_clk3 0x00000003 +#define regk_iop_sap_out_ext 0x00000003 +#define regk_iop_sap_out_gated 0x00000004 +#define regk_iop_sap_out_gio1 0x00000000 +#define regk_iop_sap_out_gio13 0x00000002 +#define regk_iop_sap_out_gio13_clk 0x0000000c +#define regk_iop_sap_out_gio15 0x00000001 +#define regk_iop_sap_out_gio18 0x00000003 +#define regk_iop_sap_out_gio18_clk 0x0000000d +#define regk_iop_sap_out_gio1_clk 0x00000008 +#define regk_iop_sap_out_gio21_clk 0x0000000e +#define regk_iop_sap_out_gio23 0x00000002 +#define regk_iop_sap_out_gio29_clk 0x0000000f +#define regk_iop_sap_out_gio31 0x00000003 +#define regk_iop_sap_out_gio5 0x00000001 +#define regk_iop_sap_out_gio5_clk 0x00000009 +#define regk_iop_sap_out_gio6_clk 0x0000000a +#define regk_iop_sap_out_gio7 0x00000000 +#define regk_iop_sap_out_gio7_clk 0x0000000b +#define regk_iop_sap_out_gio_in13 0x00000001 +#define regk_iop_sap_out_gio_in21 0x00000002 +#define regk_iop_sap_out_gio_in29 0x00000003 +#define regk_iop_sap_out_gio_in5 0x00000000 +#define regk_iop_sap_out_inv 0x00000001 +#define regk_iop_sap_out_nand 0x00000003 +#define regk_iop_sap_out_no 0x00000000 +#define regk_iop_sap_out_none 0x00000000 +#define regk_iop_sap_out_rw_bus0_default 0x00000000 +#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 +#define regk_iop_sap_out_rw_gio_default 0x00000000 +#define regk_iop_sap_out_rw_gio_size 0x00000020 +#define regk_iop_sap_out_spu0_gio0 0x00000002 +#define regk_iop_sap_out_spu0_gio1 0x00000003 +#define regk_iop_sap_out_spu0_gio12 0x00000004 +#define regk_iop_sap_out_spu0_gio13 0x00000004 +#define regk_iop_sap_out_spu0_gio14 0x00000004 +#define regk_iop_sap_out_spu0_gio15 0x00000004 +#define regk_iop_sap_out_spu0_gio2 0x00000002 +#define regk_iop_sap_out_spu0_gio3 0x00000003 +#define regk_iop_sap_out_spu0_gio4 0x00000002 +#define regk_iop_sap_out_spu0_gio5 0x00000003 +#define regk_iop_sap_out_spu0_gio6 0x00000002 +#define regk_iop_sap_out_spu0_gio7 0x00000003 +#define regk_iop_sap_out_spu1_gio0 0x00000005 +#define regk_iop_sap_out_spu1_gio1 0x00000006 +#define regk_iop_sap_out_spu1_gio12 0x00000007 +#define regk_iop_sap_out_spu1_gio13 0x00000007 +#define regk_iop_sap_out_spu1_gio14 0x00000007 +#define regk_iop_sap_out_spu1_gio15 0x00000007 +#define regk_iop_sap_out_spu1_gio2 0x00000005 +#define regk_iop_sap_out_spu1_gio3 0x00000006 +#define regk_iop_sap_out_spu1_gio4 0x00000005 +#define regk_iop_sap_out_spu1_gio5 0x00000006 +#define regk_iop_sap_out_spu1_gio6 0x00000005 +#define regk_iop_sap_out_spu1_gio7 0x00000006 +#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 +#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 +#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 +#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 +#define regk_iop_sap_out_tmr 0x00000005 +#define regk_iop_sap_out_yes 0x00000001 +#endif /* __iop_sap_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h new file mode 100644 index 000000000000..2cf5721597fc --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h @@ -0,0 +1,111 @@ +#ifndef __iop_scrc_in_defs_asm_h +#define __iop_scrc_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_in.r + * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r + * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 +#define reg_iop_scrc_in_rw_cfg___trig___width 2 +#define reg_iop_scrc_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_scrc_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_scrc_in, type r */ +#define reg_iop_scrc_in_r_stat___err___lsb 0 +#define reg_iop_scrc_in_r_stat___err___width 1 +#define reg_iop_scrc_in_r_stat___err___bit 0 +#define reg_iop_scrc_in_r_stat_offset 8 + +/* Register rw_init_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_init_crc_offset 12 + +/* Register rs_computed_crc, scope iop_scrc_in, type rs */ +#define reg_iop_scrc_in_rs_computed_crc_offset 16 + +/* Register r_computed_crc, scope iop_scrc_in, type r */ +#define reg_iop_scrc_in_r_computed_crc_offset 20 + +/* Register rw_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_crc_offset 24 + +/* Register rw_correct_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_correct_crc_offset 28 + +/* Register rw_wr1bit, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 +#define reg_iop_scrc_in_rw_wr1bit___data___width 2 +#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 +#define reg_iop_scrc_in_rw_wr1bit___last___width 2 +#define reg_iop_scrc_in_rw_wr1bit_offset 32 + + +/* Constants */ +#define regk_iop_scrc_in_dif_in 0x00000002 +#define regk_iop_scrc_in_hi 0x00000000 +#define regk_iop_scrc_in_neg 0x00000002 +#define regk_iop_scrc_in_no 0x00000000 +#define regk_iop_scrc_in_pos 0x00000001 +#define regk_iop_scrc_in_pos_neg 0x00000003 +#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 +#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 +#define regk_iop_scrc_in_rw_cfg_default 0x00000000 +#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 +#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 +#define regk_iop_scrc_in_set0 0x00000000 +#define regk_iop_scrc_in_set1 0x00000001 +#define regk_iop_scrc_in_yes 0x00000001 +#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h new file mode 100644 index 000000000000..640a25725f20 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h @@ -0,0 +1,105 @@ +#ifndef __iop_scrc_out_defs_asm_h +#define __iop_scrc_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_out.r + * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r + * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 +#define reg_iop_scrc_out_rw_cfg___trig___width 2 +#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 +#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 +#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 +#define reg_iop_scrc_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 +#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 +#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 +#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 +#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 +#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 +#define reg_iop_scrc_out_rw_ctrl_offset 4 + +/* Register rw_init_crc, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_init_crc_offset 8 + +/* Register rw_crc, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_crc_offset 12 + +/* Register rw_data, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_data___val___lsb 0 +#define reg_iop_scrc_out_rw_data___val___width 1 +#define reg_iop_scrc_out_rw_data___val___bit 0 +#define reg_iop_scrc_out_rw_data_offset 16 + +/* Register r_computed_crc, scope iop_scrc_out, type r */ +#define reg_iop_scrc_out_r_computed_crc_offset 20 + + +/* Constants */ +#define regk_iop_scrc_out_crc 0x00000001 +#define regk_iop_scrc_out_data 0x00000000 +#define regk_iop_scrc_out_dif 0x00000001 +#define regk_iop_scrc_out_hi 0x00000000 +#define regk_iop_scrc_out_neg 0x00000002 +#define regk_iop_scrc_out_no 0x00000000 +#define regk_iop_scrc_out_pos 0x00000001 +#define regk_iop_scrc_out_pos_neg 0x00000003 +#define regk_iop_scrc_out_reg 0x00000000 +#define regk_iop_scrc_out_rw_cfg_default 0x00000000 +#define regk_iop_scrc_out_rw_crc_default 0x00000000 +#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 +#define regk_iop_scrc_out_rw_data_default 0x00000000 +#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 +#define regk_iop_scrc_out_yes 0x00000001 +#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h new file mode 100644 index 000000000000..bb402c1aa761 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h @@ -0,0 +1,573 @@ +#ifndef __iop_spu_defs_asm_h +#define __iop_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_spu.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r + * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_spu_rw_r 4 +/* Register rw_r, scope iop_spu, type rw */ +#define reg_iop_spu_rw_r_offset 0 + +/* Register rw_seq_pc, scope iop_spu, type rw */ +#define reg_iop_spu_rw_seq_pc___addr___lsb 0 +#define reg_iop_spu_rw_seq_pc___addr___width 12 +#define reg_iop_spu_rw_seq_pc_offset 64 + +/* Register rw_fsm_pc, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 +#define reg_iop_spu_rw_fsm_pc___addr___width 12 +#define reg_iop_spu_rw_fsm_pc_offset 68 + +/* Register rw_ctrl, scope iop_spu, type rw */ +#define reg_iop_spu_rw_ctrl___fsm___lsb 0 +#define reg_iop_spu_rw_ctrl___fsm___width 1 +#define reg_iop_spu_rw_ctrl___fsm___bit 0 +#define reg_iop_spu_rw_ctrl___en___lsb 1 +#define reg_iop_spu_rw_ctrl___en___width 1 +#define reg_iop_spu_rw_ctrl___en___bit 1 +#define reg_iop_spu_rw_ctrl_offset 72 + +/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 +#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 +#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 +#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 +#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 +#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 +#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 +#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 + +/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 +#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 +#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 +#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 +#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 +#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 +#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 +#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 + +/* Register rw_gio_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_offset 84 + +/* Register rw_bus0_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_bus0_out_offset 88 + +/* Register rw_bus1_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_bus1_out_offset 92 + +/* Register r_gio_in, scope iop_spu, type r */ +#define reg_iop_spu_r_gio_in_offset 96 + +/* Register r_bus0_in, scope iop_spu, type r */ +#define reg_iop_spu_r_bus0_in_offset 100 + +/* Register r_bus1_in, scope iop_spu, type r */ +#define reg_iop_spu_r_bus1_in_offset 104 + +/* Register rw_gio_out_set, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_set_offset 108 + +/* Register rw_gio_out_clr, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_clr_offset 112 + +/* Register rs_wr_stat, scope iop_spu, type rs */ +#define reg_iop_spu_rs_wr_stat___r0___lsb 0 +#define reg_iop_spu_rs_wr_stat___r0___width 1 +#define reg_iop_spu_rs_wr_stat___r0___bit 0 +#define reg_iop_spu_rs_wr_stat___r1___lsb 1 +#define reg_iop_spu_rs_wr_stat___r1___width 1 +#define reg_iop_spu_rs_wr_stat___r1___bit 1 +#define reg_iop_spu_rs_wr_stat___r2___lsb 2 +#define reg_iop_spu_rs_wr_stat___r2___width 1 +#define reg_iop_spu_rs_wr_stat___r2___bit 2 +#define reg_iop_spu_rs_wr_stat___r3___lsb 3 +#define reg_iop_spu_rs_wr_stat___r3___width 1 +#define reg_iop_spu_rs_wr_stat___r3___bit 3 +#define reg_iop_spu_rs_wr_stat___r4___lsb 4 +#define reg_iop_spu_rs_wr_stat___r4___width 1 +#define reg_iop_spu_rs_wr_stat___r4___bit 4 +#define reg_iop_spu_rs_wr_stat___r5___lsb 5 +#define reg_iop_spu_rs_wr_stat___r5___width 1 +#define reg_iop_spu_rs_wr_stat___r5___bit 5 +#define reg_iop_spu_rs_wr_stat___r6___lsb 6 +#define reg_iop_spu_rs_wr_stat___r6___width 1 +#define reg_iop_spu_rs_wr_stat___r6___bit 6 +#define reg_iop_spu_rs_wr_stat___r7___lsb 7 +#define reg_iop_spu_rs_wr_stat___r7___width 1 +#define reg_iop_spu_rs_wr_stat___r7___bit 7 +#define reg_iop_spu_rs_wr_stat___r8___lsb 8 +#define reg_iop_spu_rs_wr_stat___r8___width 1 +#define reg_iop_spu_rs_wr_stat___r8___bit 8 +#define reg_iop_spu_rs_wr_stat___r9___lsb 9 +#define reg_iop_spu_rs_wr_stat___r9___width 1 +#define reg_iop_spu_rs_wr_stat___r9___bit 9 +#define reg_iop_spu_rs_wr_stat___r10___lsb 10 +#define reg_iop_spu_rs_wr_stat___r10___width 1 +#define reg_iop_spu_rs_wr_stat___r10___bit 10 +#define reg_iop_spu_rs_wr_stat___r11___lsb 11 +#define reg_iop_spu_rs_wr_stat___r11___width 1 +#define reg_iop_spu_rs_wr_stat___r11___bit 11 +#define reg_iop_spu_rs_wr_stat___r12___lsb 12 +#define reg_iop_spu_rs_wr_stat___r12___width 1 +#define reg_iop_spu_rs_wr_stat___r12___bit 12 +#define reg_iop_spu_rs_wr_stat___r13___lsb 13 +#define reg_iop_spu_rs_wr_stat___r13___width 1 +#define reg_iop_spu_rs_wr_stat___r13___bit 13 +#define reg_iop_spu_rs_wr_stat___r14___lsb 14 +#define reg_iop_spu_rs_wr_stat___r14___width 1 +#define reg_iop_spu_rs_wr_stat___r14___bit 14 +#define reg_iop_spu_rs_wr_stat___r15___lsb 15 +#define reg_iop_spu_rs_wr_stat___r15___width 1 +#define reg_iop_spu_rs_wr_stat___r15___bit 15 +#define reg_iop_spu_rs_wr_stat_offset 116 + +/* Register r_wr_stat, scope iop_spu, type r */ +#define reg_iop_spu_r_wr_stat___r0___lsb 0 +#define reg_iop_spu_r_wr_stat___r0___width 1 +#define reg_iop_spu_r_wr_stat___r0___bit 0 +#define reg_iop_spu_r_wr_stat___r1___lsb 1 +#define reg_iop_spu_r_wr_stat___r1___width 1 +#define reg_iop_spu_r_wr_stat___r1___bit 1 +#define reg_iop_spu_r_wr_stat___r2___lsb 2 +#define reg_iop_spu_r_wr_stat___r2___width 1 +#define reg_iop_spu_r_wr_stat___r2___bit 2 +#define reg_iop_spu_r_wr_stat___r3___lsb 3 +#define reg_iop_spu_r_wr_stat___r3___width 1 +#define reg_iop_spu_r_wr_stat___r3___bit 3 +#define reg_iop_spu_r_wr_stat___r4___lsb 4 +#define reg_iop_spu_r_wr_stat___r4___width 1 +#define reg_iop_spu_r_wr_stat___r4___bit 4 +#define reg_iop_spu_r_wr_stat___r5___lsb 5 +#define reg_iop_spu_r_wr_stat___r5___width 1 +#define reg_iop_spu_r_wr_stat___r5___bit 5 +#define reg_iop_spu_r_wr_stat___r6___lsb 6 +#define reg_iop_spu_r_wr_stat___r6___width 1 +#define reg_iop_spu_r_wr_stat___r6___bit 6 +#define reg_iop_spu_r_wr_stat___r7___lsb 7 +#define reg_iop_spu_r_wr_stat___r7___width 1 +#define reg_iop_spu_r_wr_stat___r7___bit 7 +#define reg_iop_spu_r_wr_stat___r8___lsb 8 +#define reg_iop_spu_r_wr_stat___r8___width 1 +#define reg_iop_spu_r_wr_stat___r8___bit 8 +#define reg_iop_spu_r_wr_stat___r9___lsb 9 +#define reg_iop_spu_r_wr_stat___r9___width 1 +#define reg_iop_spu_r_wr_stat___r9___bit 9 +#define reg_iop_spu_r_wr_stat___r10___lsb 10 +#define reg_iop_spu_r_wr_stat___r10___width 1 +#define reg_iop_spu_r_wr_stat___r10___bit 10 +#define reg_iop_spu_r_wr_stat___r11___lsb 11 +#define reg_iop_spu_r_wr_stat___r11___width 1 +#define reg_iop_spu_r_wr_stat___r11___bit 11 +#define reg_iop_spu_r_wr_stat___r12___lsb 12 +#define reg_iop_spu_r_wr_stat___r12___width 1 +#define reg_iop_spu_r_wr_stat___r12___bit 12 +#define reg_iop_spu_r_wr_stat___r13___lsb 13 +#define reg_iop_spu_r_wr_stat___r13___width 1 +#define reg_iop_spu_r_wr_stat___r13___bit 13 +#define reg_iop_spu_r_wr_stat___r14___lsb 14 +#define reg_iop_spu_r_wr_stat___r14___width 1 +#define reg_iop_spu_r_wr_stat___r14___bit 14 +#define reg_iop_spu_r_wr_stat___r15___lsb 15 +#define reg_iop_spu_r_wr_stat___r15___width 1 +#define reg_iop_spu_r_wr_stat___r15___bit 15 +#define reg_iop_spu_r_wr_stat_offset 120 + +/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ +#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 + +/* Register r_stat_in, scope iop_spu, type r */ +#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 +#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 +#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 +#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 +#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 +#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 +#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 +#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 +#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 +#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 +#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 +#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 +#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 +#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 +#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 +#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 +#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 +#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 +#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 +#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 +#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 +#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 +#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 +#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 +#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 +#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 +#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 +#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 +#define reg_iop_spu_r_stat_in___sync_clk12___width 1 +#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 +#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 +#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 +#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 +#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 +#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 +#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 +#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 +#define reg_iop_spu_r_stat_in___mc_busy___width 1 +#define reg_iop_spu_r_stat_in___mc_busy___bit 30 +#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 +#define reg_iop_spu_r_stat_in___mc_owned___width 1 +#define reg_iop_spu_r_stat_in___mc_owned___bit 31 +#define reg_iop_spu_r_stat_in_offset 128 + +/* Register r_trigger_in, scope iop_spu, type r */ +#define reg_iop_spu_r_trigger_in_offset 132 + +/* Register r_special_stat, scope iop_spu, type r */ +#define reg_iop_spu_r_special_stat___c_flag___lsb 0 +#define reg_iop_spu_r_special_stat___c_flag___width 1 +#define reg_iop_spu_r_special_stat___c_flag___bit 0 +#define reg_iop_spu_r_special_stat___v_flag___lsb 1 +#define reg_iop_spu_r_special_stat___v_flag___width 1 +#define reg_iop_spu_r_special_stat___v_flag___bit 1 +#define reg_iop_spu_r_special_stat___z_flag___lsb 2 +#define reg_iop_spu_r_special_stat___z_flag___width 1 +#define reg_iop_spu_r_special_stat___z_flag___bit 2 +#define reg_iop_spu_r_special_stat___n_flag___lsb 3 +#define reg_iop_spu_r_special_stat___n_flag___width 1 +#define reg_iop_spu_r_special_stat___n_flag___bit 3 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 +#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 +#define reg_iop_spu_r_special_stat___fsm_in0___width 1 +#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 +#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 +#define reg_iop_spu_r_special_stat___fsm_in1___width 1 +#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 +#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 +#define reg_iop_spu_r_special_stat___fsm_in2___width 1 +#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 +#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 +#define reg_iop_spu_r_special_stat___fsm_in3___width 1 +#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 +#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 +#define reg_iop_spu_r_special_stat___fsm_in4___width 1 +#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 +#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 +#define reg_iop_spu_r_special_stat___fsm_in5___width 1 +#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 +#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 +#define reg_iop_spu_r_special_stat___fsm_in6___width 1 +#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 +#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 +#define reg_iop_spu_r_special_stat___fsm_in7___width 1 +#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 +#define reg_iop_spu_r_special_stat___event0___lsb 16 +#define reg_iop_spu_r_special_stat___event0___width 1 +#define reg_iop_spu_r_special_stat___event0___bit 16 +#define reg_iop_spu_r_special_stat___event1___lsb 17 +#define reg_iop_spu_r_special_stat___event1___width 1 +#define reg_iop_spu_r_special_stat___event1___bit 17 +#define reg_iop_spu_r_special_stat___event2___lsb 18 +#define reg_iop_spu_r_special_stat___event2___width 1 +#define reg_iop_spu_r_special_stat___event2___bit 18 +#define reg_iop_spu_r_special_stat___event3___lsb 19 +#define reg_iop_spu_r_special_stat___event3___width 1 +#define reg_iop_spu_r_special_stat___event3___bit 19 +#define reg_iop_spu_r_special_stat_offset 136 + +/* Register rw_reg_access, scope iop_spu, type rw */ +#define reg_iop_spu_rw_reg_access___addr___lsb 0 +#define reg_iop_spu_rw_reg_access___addr___width 13 +#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 +#define reg_iop_spu_rw_reg_access___imm_hi___width 16 +#define reg_iop_spu_rw_reg_access_offset 140 + +#define STRIDE_iop_spu_rw_event_cfg 4 +/* Register rw_event_cfg, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_cfg___addr___lsb 0 +#define reg_iop_spu_rw_event_cfg___addr___width 12 +#define reg_iop_spu_rw_event_cfg___src___lsb 12 +#define reg_iop_spu_rw_event_cfg___src___width 2 +#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 +#define reg_iop_spu_rw_event_cfg___eq_en___width 1 +#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 +#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 +#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 +#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 +#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 +#define reg_iop_spu_rw_event_cfg___gt_en___width 1 +#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 +#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 +#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 +#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 +#define reg_iop_spu_rw_event_cfg_offset 144 + +#define STRIDE_iop_spu_rw_event_mask 4 +/* Register rw_event_mask, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_mask_offset 160 + +#define STRIDE_iop_spu_rw_event_val 4 +/* Register rw_event_val, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_val_offset 176 + +/* Register rw_event_ret, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_ret___addr___lsb 0 +#define reg_iop_spu_rw_event_ret___addr___width 12 +#define reg_iop_spu_rw_event_ret_offset 192 + +/* Register r_trace, scope iop_spu, type r */ +#define reg_iop_spu_r_trace___fsm___lsb 0 +#define reg_iop_spu_r_trace___fsm___width 1 +#define reg_iop_spu_r_trace___fsm___bit 0 +#define reg_iop_spu_r_trace___en___lsb 1 +#define reg_iop_spu_r_trace___en___width 1 +#define reg_iop_spu_r_trace___en___bit 1 +#define reg_iop_spu_r_trace___c_flag___lsb 2 +#define reg_iop_spu_r_trace___c_flag___width 1 +#define reg_iop_spu_r_trace___c_flag___bit 2 +#define reg_iop_spu_r_trace___v_flag___lsb 3 +#define reg_iop_spu_r_trace___v_flag___width 1 +#define reg_iop_spu_r_trace___v_flag___bit 3 +#define reg_iop_spu_r_trace___z_flag___lsb 4 +#define reg_iop_spu_r_trace___z_flag___width 1 +#define reg_iop_spu_r_trace___z_flag___bit 4 +#define reg_iop_spu_r_trace___n_flag___lsb 5 +#define reg_iop_spu_r_trace___n_flag___width 1 +#define reg_iop_spu_r_trace___n_flag___bit 5 +#define reg_iop_spu_r_trace___seq_addr___lsb 6 +#define reg_iop_spu_r_trace___seq_addr___width 12 +#define reg_iop_spu_r_trace___fsm_addr___lsb 20 +#define reg_iop_spu_r_trace___fsm_addr___width 12 +#define reg_iop_spu_r_trace_offset 196 + +/* Register r_fsm_trace, scope iop_spu, type r */ +#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 +#define reg_iop_spu_r_fsm_trace___fsm___width 1 +#define reg_iop_spu_r_fsm_trace___fsm___bit 0 +#define reg_iop_spu_r_fsm_trace___en___lsb 1 +#define reg_iop_spu_r_fsm_trace___en___width 1 +#define reg_iop_spu_r_fsm_trace___en___bit 1 +#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 +#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 +#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 +#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 +#define reg_iop_spu_r_fsm_trace___inp0___width 1 +#define reg_iop_spu_r_fsm_trace___inp0___bit 3 +#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 +#define reg_iop_spu_r_fsm_trace___inp1___width 1 +#define reg_iop_spu_r_fsm_trace___inp1___bit 4 +#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 +#define reg_iop_spu_r_fsm_trace___inp2___width 1 +#define reg_iop_spu_r_fsm_trace___inp2___bit 5 +#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 +#define reg_iop_spu_r_fsm_trace___inp3___width 1 +#define reg_iop_spu_r_fsm_trace___inp3___bit 6 +#define reg_iop_spu_r_fsm_trace___event0___lsb 7 +#define reg_iop_spu_r_fsm_trace___event0___width 1 +#define reg_iop_spu_r_fsm_trace___event0___bit 7 +#define reg_iop_spu_r_fsm_trace___event1___lsb 8 +#define reg_iop_spu_r_fsm_trace___event1___width 1 +#define reg_iop_spu_r_fsm_trace___event1___bit 8 +#define reg_iop_spu_r_fsm_trace___event2___lsb 9 +#define reg_iop_spu_r_fsm_trace___event2___width 1 +#define reg_iop_spu_r_fsm_trace___event2___bit 9 +#define reg_iop_spu_r_fsm_trace___event3___lsb 10 +#define reg_iop_spu_r_fsm_trace___event3___width 1 +#define reg_iop_spu_r_fsm_trace___event3___bit 10 +#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 +#define reg_iop_spu_r_fsm_trace___gio_out___width 8 +#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 +#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 +#define reg_iop_spu_r_fsm_trace_offset 200 + +#define STRIDE_iop_spu_rw_brp 4 +/* Register rw_brp, scope iop_spu, type rw */ +#define reg_iop_spu_rw_brp___addr___lsb 0 +#define reg_iop_spu_rw_brp___addr___width 12 +#define reg_iop_spu_rw_brp___fsm___lsb 12 +#define reg_iop_spu_rw_brp___fsm___width 1 +#define reg_iop_spu_rw_brp___fsm___bit 12 +#define reg_iop_spu_rw_brp___en___lsb 13 +#define reg_iop_spu_rw_brp___en___width 1 +#define reg_iop_spu_rw_brp___en___bit 13 +#define reg_iop_spu_rw_brp_offset 204 + + +/* Constants */ +#define regk_iop_spu_attn_hi 0x00000005 +#define regk_iop_spu_attn_lo 0x00000005 +#define regk_iop_spu_attn_r0 0x00000000 +#define regk_iop_spu_attn_r1 0x00000001 +#define regk_iop_spu_attn_r10 0x00000002 +#define regk_iop_spu_attn_r11 0x00000003 +#define regk_iop_spu_attn_r12 0x00000004 +#define regk_iop_spu_attn_r13 0x00000005 +#define regk_iop_spu_attn_r14 0x00000006 +#define regk_iop_spu_attn_r15 0x00000007 +#define regk_iop_spu_attn_r2 0x00000002 +#define regk_iop_spu_attn_r3 0x00000003 +#define regk_iop_spu_attn_r4 0x00000004 +#define regk_iop_spu_attn_r5 0x00000005 +#define regk_iop_spu_attn_r6 0x00000006 +#define regk_iop_spu_attn_r7 0x00000007 +#define regk_iop_spu_attn_r8 0x00000000 +#define regk_iop_spu_attn_r9 0x00000001 +#define regk_iop_spu_c 0x00000000 +#define regk_iop_spu_flag 0x00000002 +#define regk_iop_spu_gio_in 0x00000000 +#define regk_iop_spu_gio_out 0x00000005 +#define regk_iop_spu_gio_out0 0x00000008 +#define regk_iop_spu_gio_out1 0x00000009 +#define regk_iop_spu_gio_out2 0x0000000a +#define regk_iop_spu_gio_out3 0x0000000b +#define regk_iop_spu_gio_out4 0x0000000c +#define regk_iop_spu_gio_out5 0x0000000d +#define regk_iop_spu_gio_out6 0x0000000e +#define regk_iop_spu_gio_out7 0x0000000f +#define regk_iop_spu_n 0x00000003 +#define regk_iop_spu_no 0x00000000 +#define regk_iop_spu_r0 0x00000008 +#define regk_iop_spu_r1 0x00000009 +#define regk_iop_spu_r10 0x0000000a +#define regk_iop_spu_r11 0x0000000b +#define regk_iop_spu_r12 0x0000000c +#define regk_iop_spu_r13 0x0000000d +#define regk_iop_spu_r14 0x0000000e +#define regk_iop_spu_r15 0x0000000f +#define regk_iop_spu_r2 0x0000000a +#define regk_iop_spu_r3 0x0000000b +#define regk_iop_spu_r4 0x0000000c +#define regk_iop_spu_r5 0x0000000d +#define regk_iop_spu_r6 0x0000000e +#define regk_iop_spu_r7 0x0000000f +#define regk_iop_spu_r8 0x00000008 +#define regk_iop_spu_r9 0x00000009 +#define regk_iop_spu_reg_hi 0x00000002 +#define regk_iop_spu_reg_lo 0x00000002 +#define regk_iop_spu_rw_brp_default 0x00000000 +#define regk_iop_spu_rw_brp_size 0x00000004 +#define regk_iop_spu_rw_ctrl_default 0x00000000 +#define regk_iop_spu_rw_event_cfg_size 0x00000004 +#define regk_iop_spu_rw_event_mask_size 0x00000004 +#define regk_iop_spu_rw_event_val_size 0x00000004 +#define regk_iop_spu_rw_gio_out_default 0x00000000 +#define regk_iop_spu_rw_r_size 0x00000010 +#define regk_iop_spu_rw_reg_access_default 0x00000000 +#define regk_iop_spu_stat_in 0x00000002 +#define regk_iop_spu_statin_hi 0x00000004 +#define regk_iop_spu_statin_lo 0x00000004 +#define regk_iop_spu_trig 0x00000003 +#define regk_iop_spu_trigger 0x00000006 +#define regk_iop_spu_v 0x00000001 +#define regk_iop_spu_wsts_gioout_spec 0x00000001 +#define regk_iop_spu_xor 0x00000003 +#define regk_iop_spu_xor_bus0_r2_0 0x00000000 +#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 +#define regk_iop_spu_xor_bus1_r3_0 0x00000001 +#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 +#define regk_iop_spu_yes 0x00000001 +#define regk_iop_spu_z 0x00000002 +#endif /* __iop_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 000000000000..3be60f9b024c --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h @@ -0,0 +1,1052 @@ +#ifndef __iop_sw_cfg_defs_asm_h +#define __iop_sw_cfg_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 + +/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 + +/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 + +/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 + +/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 + +/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 + +/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 + +/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 + +/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 + +/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 + +/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 + +/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 + +/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 + +/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 + +/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 + +/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 + +/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 + +/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 + +/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 + +/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 + +/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 + +/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 + +/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 + +/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 + +/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 + +/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_mask_offset 152 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 +#define reg_iop_sw_cfg_rw_pinmapping_offset 160 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 + +/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 +#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 + +/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 +#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 + +/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 + +/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 + +/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 +#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 + +/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 +#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 + + +/* Constants */ +#define regk_iop_sw_cfg_a 0x00000001 +#define regk_iop_sw_cfg_b 0x00000002 +#define regk_iop_sw_cfg_bus0 0x00000000 +#define regk_iop_sw_cfg_bus0_rot16 0x00000004 +#define regk_iop_sw_cfg_bus0_rot24 0x00000006 +#define regk_iop_sw_cfg_bus0_rot8 0x00000002 +#define regk_iop_sw_cfg_bus1 0x00000001 +#define regk_iop_sw_cfg_bus1_rot16 0x00000005 +#define regk_iop_sw_cfg_bus1_rot24 0x00000007 +#define regk_iop_sw_cfg_bus1_rot8 0x00000003 +#define regk_iop_sw_cfg_clk12 0x00000000 +#define regk_iop_sw_cfg_cpu 0x00000000 +#define regk_iop_sw_cfg_dmc0 0x00000000 +#define regk_iop_sw_cfg_dmc1 0x00000001 +#define regk_iop_sw_cfg_gated_clk0 0x00000010 +#define regk_iop_sw_cfg_gated_clk1 0x00000011 +#define regk_iop_sw_cfg_gated_clk2 0x00000012 +#define regk_iop_sw_cfg_gated_clk3 0x00000013 +#define regk_iop_sw_cfg_gio0 0x00000004 +#define regk_iop_sw_cfg_gio1 0x00000001 +#define regk_iop_sw_cfg_gio2 0x00000005 +#define regk_iop_sw_cfg_gio3 0x00000002 +#define regk_iop_sw_cfg_gio4 0x00000006 +#define regk_iop_sw_cfg_gio5 0x00000003 +#define regk_iop_sw_cfg_gio6 0x00000007 +#define regk_iop_sw_cfg_gio7 0x00000004 +#define regk_iop_sw_cfg_gio_in0 0x00000000 +#define regk_iop_sw_cfg_gio_in1 0x00000001 +#define regk_iop_sw_cfg_gio_in10 0x00000002 +#define regk_iop_sw_cfg_gio_in11 0x00000003 +#define regk_iop_sw_cfg_gio_in14 0x00000004 +#define regk_iop_sw_cfg_gio_in15 0x00000005 +#define regk_iop_sw_cfg_gio_in18 0x00000002 +#define regk_iop_sw_cfg_gio_in19 0x00000003 +#define regk_iop_sw_cfg_gio_in20 0x00000004 +#define regk_iop_sw_cfg_gio_in21 0x00000005 +#define regk_iop_sw_cfg_gio_in26 0x00000006 +#define regk_iop_sw_cfg_gio_in27 0x00000007 +#define regk_iop_sw_cfg_gio_in28 0x00000006 +#define regk_iop_sw_cfg_gio_in29 0x00000007 +#define regk_iop_sw_cfg_gio_in4 0x00000000 +#define regk_iop_sw_cfg_gio_in5 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 +#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 +#define regk_iop_sw_cfg_mpu 0x00000001 +#define regk_iop_sw_cfg_none 0x00000000 +#define regk_iop_sw_cfg_par0 0x00000000 +#define regk_iop_sw_cfg_par1 0x00000001 +#define regk_iop_sw_cfg_pdp_out0 0x00000002 +#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 +#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 +#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 +#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 +#define regk_iop_sw_cfg_pdp_out1 0x00000003 +#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 +#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 +#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 +#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 +#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 +#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 +#define regk_iop_sw_cfg_sdp_out0 0x00000008 +#define regk_iop_sw_cfg_sdp_out1 0x00000009 +#define regk_iop_sw_cfg_size16 0x00000002 +#define regk_iop_sw_cfg_size24 0x00000003 +#define regk_iop_sw_cfg_size32 0x00000004 +#define regk_iop_sw_cfg_size8 0x00000001 +#define regk_iop_sw_cfg_spu0 0x00000002 +#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 +#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 +#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 +#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 +#define regk_iop_sw_cfg_spu0_g0 0x0000000e +#define regk_iop_sw_cfg_spu0_g1 0x0000000e +#define regk_iop_sw_cfg_spu0_g2 0x0000000e +#define regk_iop_sw_cfg_spu0_g3 0x0000000e +#define regk_iop_sw_cfg_spu0_g4 0x0000000e +#define regk_iop_sw_cfg_spu0_g5 0x0000000e +#define regk_iop_sw_cfg_spu0_g6 0x0000000e +#define regk_iop_sw_cfg_spu0_g7 0x0000000e +#define regk_iop_sw_cfg_spu0_gio0 0x00000000 +#define regk_iop_sw_cfg_spu0_gio1 0x00000001 +#define regk_iop_sw_cfg_spu0_gio2 0x00000000 +#define regk_iop_sw_cfg_spu0_gio5 0x00000005 +#define regk_iop_sw_cfg_spu0_gio6 0x00000006 +#define regk_iop_sw_cfg_spu0_gio7 0x00000007 +#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 +#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 +#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 +#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 +#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 +#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 +#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 +#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 +#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e +#define regk_iop_sw_cfg_spu1 0x00000003 +#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 +#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 +#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 +#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 +#define regk_iop_sw_cfg_spu1_g0 0x0000000f +#define regk_iop_sw_cfg_spu1_g1 0x0000000f +#define regk_iop_sw_cfg_spu1_g2 0x0000000f +#define regk_iop_sw_cfg_spu1_g3 0x0000000f +#define regk_iop_sw_cfg_spu1_g4 0x0000000f +#define regk_iop_sw_cfg_spu1_g5 0x0000000f +#define regk_iop_sw_cfg_spu1_g6 0x0000000f +#define regk_iop_sw_cfg_spu1_g7 0x0000000f +#define regk_iop_sw_cfg_spu1_gio0 0x00000002 +#define regk_iop_sw_cfg_spu1_gio1 0x00000003 +#define regk_iop_sw_cfg_spu1_gio2 0x00000002 +#define regk_iop_sw_cfg_spu1_gio5 0x00000005 +#define regk_iop_sw_cfg_spu1_gio6 0x00000006 +#define regk_iop_sw_cfg_spu1_gio7 0x00000007 +#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 +#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 +#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 +#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 +#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 +#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 +#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 +#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 +#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f +#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 +#define regk_iop_sw_cfg_timer_grp0 0x00000000 +#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 +#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 +#define regk_iop_sw_cfg_timer_grp1 0x00000000 +#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 +#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 +#define regk_iop_sw_cfg_timer_grp2 0x00000000 +#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 +#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 +#define regk_iop_sw_cfg_timer_grp3 0x00000000 +#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 +#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 +#define regk_iop_sw_cfg_trig0_0 0x00000000 +#define regk_iop_sw_cfg_trig0_1 0x00000000 +#define regk_iop_sw_cfg_trig0_2 0x00000000 +#define regk_iop_sw_cfg_trig0_3 0x00000000 +#define regk_iop_sw_cfg_trig1_0 0x00000000 +#define regk_iop_sw_cfg_trig1_1 0x00000000 +#define regk_iop_sw_cfg_trig1_2 0x00000000 +#define regk_iop_sw_cfg_trig1_3 0x00000000 +#define regk_iop_sw_cfg_trig2_0 0x00000000 +#define regk_iop_sw_cfg_trig2_1 0x00000000 +#define regk_iop_sw_cfg_trig2_2 0x00000000 +#define regk_iop_sw_cfg_trig2_3 0x00000000 +#define regk_iop_sw_cfg_trig3_0 0x00000000 +#define regk_iop_sw_cfg_trig3_1 0x00000000 +#define regk_iop_sw_cfg_trig3_2 0x00000000 +#define regk_iop_sw_cfg_trig3_3 0x00000000 +#define regk_iop_sw_cfg_trig4_0 0x00000001 +#define regk_iop_sw_cfg_trig4_1 0x00000001 +#define regk_iop_sw_cfg_trig4_2 0x00000001 +#define regk_iop_sw_cfg_trig4_3 0x00000001 +#define regk_iop_sw_cfg_trig5_0 0x00000001 +#define regk_iop_sw_cfg_trig5_1 0x00000001 +#define regk_iop_sw_cfg_trig5_2 0x00000001 +#define regk_iop_sw_cfg_trig5_3 0x00000001 +#define regk_iop_sw_cfg_trig6_0 0x00000001 +#define regk_iop_sw_cfg_trig6_1 0x00000001 +#define regk_iop_sw_cfg_trig6_2 0x00000001 +#define regk_iop_sw_cfg_trig6_3 0x00000001 +#define regk_iop_sw_cfg_trig7_0 0x00000001 +#define regk_iop_sw_cfg_trig7_1 0x00000001 +#define regk_iop_sw_cfg_trig7_2 0x00000001 +#define regk_iop_sw_cfg_trig7_3 0x00000001 +#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 000000000000..db347bcba025 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h @@ -0,0 +1,1758 @@ +#ifndef __iop_sw_cpu_defs_asm_h +#define __iop_sw_cpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_cpu_rw_mc_data___val___width 32 +#define reg_iop_sw_cpu_rw_mc_data_offset 4 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_addr_offset 8 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +#define reg_iop_sw_cpu_rs_mc_data_offset 12 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_data_offset 16 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_cpu_r_mc_stat_offset 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 + +/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 + +/* Register r_bus0_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus0_in_offset 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 + +/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 + +/* Register r_bus1_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus1_in_offset 60 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_gio_in_offset 80 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 +#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_r_intr0_offset 92 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_r_masked_intr0_offset 96 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 +#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_r_intr1_offset 108 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_r_masked_intr1_offset 112 + +/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 +#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 + +/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 + +/* Register r_intr2, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_intr2_offset 124 + +/* Register r_masked_intr2, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_masked_intr2_offset 128 + +/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 +#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 + +/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 + +/* Register r_intr3, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 +#define reg_iop_sw_cpu_r_intr3_offset 140 + +/* Register r_masked_intr3, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 +#define reg_iop_sw_cpu_r_masked_intr3_offset 144 + + +/* Constants */ +#define regk_iop_sw_cpu_copy 0x00000000 +#define regk_iop_sw_cpu_no 0x00000000 +#define regk_iop_sw_cpu_rd 0x00000002 +#define regk_iop_sw_cpu_reg_copy 0x00000001 +#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 +#define regk_iop_sw_cpu_wr 0x00000003 +#define regk_iop_sw_cpu_yes 0x00000001 +#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 000000000000..ee7dc0435b59 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h @@ -0,0 +1,1776 @@ +#ifndef __iop_sw_mpu_defs_asm_h +#define __iop_sw_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 +#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_mpu_rw_mc_data___val___width 32 +#define reg_iop_sw_mpu_rw_mc_data_offset 8 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_addr_offset 12 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +#define reg_iop_sw_mpu_rs_mc_data_offset 16 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_data_offset 20 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_mpu_r_mc_stat_offset 24 + +/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 + +/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 + +/* Register r_bus0_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus0_in_offset 44 + +/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 + +/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 + +/* Register r_bus1_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus1_in_offset 64 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_gio_in_offset 84 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_r_cpu_intr_offset 92 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp0_offset 104 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp1_offset 120 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp2_offset 136 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp3_offset 152 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 + + +/* Constants */ +#define regk_iop_sw_mpu_copy 0x00000000 +#define regk_iop_sw_mpu_cpu 0x00000000 +#define regk_iop_sw_mpu_mpu 0x00000001 +#define regk_iop_sw_mpu_no 0x00000000 +#define regk_iop_sw_mpu_nop 0x00000000 +#define regk_iop_sw_mpu_rd 0x00000002 +#define regk_iop_sw_mpu_reg_copy 0x00000001 +#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 +#define regk_iop_sw_mpu_set 0x00000001 +#define regk_iop_sw_mpu_spu0 0x00000002 +#define regk_iop_sw_mpu_spu1 0x00000003 +#define regk_iop_sw_mpu_wr 0x00000003 +#define regk_iop_sw_mpu_yes 0x00000001 +#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 000000000000..0929f144cfa1 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h @@ -0,0 +1,691 @@ +#ifndef __iop_sw_spu_defs_asm_h +#define __iop_sw_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_spu_rw_mc_data___val___width 32 +#define reg_iop_sw_spu_rw_mc_data_offset 4 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_addr_offset 8 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +#define reg_iop_sw_spu_rs_mc_data_offset 12 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_data_offset 16 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_spu_r_mc_stat_offset 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 + +/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 + +/* Register r_bus0_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus0_in_offset 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 + +/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 + +/* Register r_bus1_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus1_in_offset 60 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_gio_in_offset 80 + +/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 + +/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 + +/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 + +/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 + +/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 + +/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 + +/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 + +/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_cpu_intr_offset 148 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_cpu_intr_offset 152 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 +#define reg_iop_sw_spu_r_hw_intr_offset 156 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_mpu_intr_offset 160 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 +#define reg_iop_sw_spu_r_mpu_intr_offset 164 + + +/* Constants */ +#define regk_iop_sw_spu_copy 0x00000000 +#define regk_iop_sw_spu_no 0x00000000 +#define regk_iop_sw_spu_nop 0x00000000 +#define regk_iop_sw_spu_rd 0x00000002 +#define regk_iop_sw_spu_reg_copy 0x00000001 +#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_spu_set 0x00000001 +#define regk_iop_sw_spu_wr 0x00000003 +#define regk_iop_sw_spu_yes 0x00000001 +#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h new file mode 100644 index 000000000000..7129a9a4bedc --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h @@ -0,0 +1,237 @@ +#ifndef __iop_timer_grp_defs_asm_h +#define __iop_timer_grp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_timer_grp.r + * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r + * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 +#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 +#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 +#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 +#define reg_iop_timer_grp_rw_cfg___trig___width 2 +#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 +#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 +#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 +#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 +#define reg_iop_timer_grp_rw_cfg_offset 0 + +/* Register rw_half_period, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 +#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 +#define reg_iop_timer_grp_rw_half_period_offset 4 + +/* Register rw_half_period_len, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_half_period_len_offset 8 + +#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 +/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 +#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 +#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 +#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 +#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 +#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 +#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 +#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 +#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 +#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 + +#define STRIDE_iop_timer_grp_rw_tmr_len 4 +/* Register rw_tmr_len, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 +#define reg_iop_timer_grp_rw_tmr_len___val___width 16 +#define reg_iop_timer_grp_rw_tmr_len_offset 44 + +/* Register rw_cmd, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 +#define reg_iop_timer_grp_rw_cmd___rst___width 4 +#define reg_iop_timer_grp_rw_cmd___en___lsb 4 +#define reg_iop_timer_grp_rw_cmd___en___width 4 +#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 +#define reg_iop_timer_grp_rw_cmd___dis___width 4 +#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 +#define reg_iop_timer_grp_rw_cmd___strb___width 4 +#define reg_iop_timer_grp_rw_cmd_offset 60 + +/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 + +#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 +/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ +#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 +#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 +#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 + +#define STRIDE_iop_timer_grp_r_tmr_cnt 8 +/* Register r_tmr_cnt, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 +#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 +#define reg_iop_timer_grp_r_tmr_cnt_offset 72 + +/* Register rw_intr_mask, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 +#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 +#define reg_iop_timer_grp_rw_intr_mask_offset 100 + +/* Register rw_ack_intr, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 +#define reg_iop_timer_grp_rw_ack_intr_offset 104 + +/* Register r_intr, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_r_intr___tmr0___width 1 +#define reg_iop_timer_grp_r_intr___tmr0___bit 0 +#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_r_intr___tmr1___width 1 +#define reg_iop_timer_grp_r_intr___tmr1___bit 1 +#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_r_intr___tmr2___width 1 +#define reg_iop_timer_grp_r_intr___tmr2___bit 2 +#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_r_intr___tmr3___width 1 +#define reg_iop_timer_grp_r_intr___tmr3___bit 3 +#define reg_iop_timer_grp_r_intr_offset 108 + +/* Register r_masked_intr, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 +#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 +#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 +#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 +#define reg_iop_timer_grp_r_masked_intr_offset 112 + + +/* Constants */ +#define regk_iop_timer_grp_clk200 0x00000000 +#define regk_iop_timer_grp_clk_gen 0x00000002 +#define regk_iop_timer_grp_complete 0x00000002 +#define regk_iop_timer_grp_div_clk200 0x00000001 +#define regk_iop_timer_grp_div_clk_gen 0x00000003 +#define regk_iop_timer_grp_ext 0x00000001 +#define regk_iop_timer_grp_hi 0x00000000 +#define regk_iop_timer_grp_long_period 0x00000001 +#define regk_iop_timer_grp_neg 0x00000002 +#define regk_iop_timer_grp_no 0x00000000 +#define regk_iop_timer_grp_once 0x00000003 +#define regk_iop_timer_grp_pause 0x00000001 +#define regk_iop_timer_grp_pos 0x00000001 +#define regk_iop_timer_grp_pos_neg 0x00000003 +#define regk_iop_timer_grp_pulse 0x00000000 +#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 +#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 +#define regk_iop_timer_grp_rw_cfg_default 0x00000002 +#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 +#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 +#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 +#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 +#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 +#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 +#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 +#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 +#define regk_iop_timer_grp_short_period 0x00000000 +#define regk_iop_timer_grp_stop 0x00000000 +#define regk_iop_timer_grp_tmr 0x00000004 +#define regk_iop_timer_grp_toggle 0x00000001 +#define regk_iop_timer_grp_yes 0x00000001 +#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h new file mode 100644 index 000000000000..1005d9db80dc --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h @@ -0,0 +1,157 @@ +#ifndef __iop_trigger_grp_defs_asm_h +#define __iop_trigger_grp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_trigger_grp_rw_cfg 4 +/* Register rw_cfg, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 +#define reg_iop_trigger_grp_rw_cfg___action___width 2 +#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 +#define reg_iop_trigger_grp_rw_cfg___once___width 1 +#define reg_iop_trigger_grp_rw_cfg___once___bit 2 +#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 +#define reg_iop_trigger_grp_rw_cfg___trig___width 3 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 +#define reg_iop_trigger_grp_rw_cfg_offset 0 + +/* Register rw_cmd, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 +#define reg_iop_trigger_grp_rw_cmd___dis___width 4 +#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 +#define reg_iop_trigger_grp_rw_cmd___en___width 4 +#define reg_iop_trigger_grp_rw_cmd_offset 16 + +/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 +#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 +#define reg_iop_trigger_grp_rw_intr_mask_offset 20 + +/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 +#define reg_iop_trigger_grp_rw_ack_intr_offset 24 + +/* Register r_intr, scope iop_trigger_grp, type r */ +#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_r_intr___trig0___width 1 +#define reg_iop_trigger_grp_r_intr___trig0___bit 0 +#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_r_intr___trig1___width 1 +#define reg_iop_trigger_grp_r_intr___trig1___bit 1 +#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_r_intr___trig2___width 1 +#define reg_iop_trigger_grp_r_intr___trig2___bit 2 +#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_r_intr___trig3___width 1 +#define reg_iop_trigger_grp_r_intr___trig3___bit 3 +#define reg_iop_trigger_grp_r_intr_offset 28 + +/* Register r_masked_intr, scope iop_trigger_grp, type r */ +#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 +#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 +#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 +#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 +#define reg_iop_trigger_grp_r_masked_intr_offset 32 + + +/* Constants */ +#define regk_iop_trigger_grp_fall 0x00000002 +#define regk_iop_trigger_grp_fall_lo 0x00000006 +#define regk_iop_trigger_grp_no 0x00000000 +#define regk_iop_trigger_grp_off 0x00000000 +#define regk_iop_trigger_grp_pulse 0x00000000 +#define regk_iop_trigger_grp_rise 0x00000001 +#define regk_iop_trigger_grp_rise_fall 0x00000003 +#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 +#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 +#define regk_iop_trigger_grp_rise_hi 0x00000005 +#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 +#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 +#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 +#define regk_iop_trigger_grp_toggle 0x00000003 +#define regk_iop_trigger_grp_yes 0x00000001 +#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 000000000000..e13feb20a7e3 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h @@ -0,0 +1,64 @@ +#ifndef __iop_version_defs_asm_h +#define __iop_version_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_version.r + * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp + * last modfied: Mon Apr 11 16:08:44 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r + * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_version, scope iop_version, type r */ +#define reg_iop_version_r_version___nr___lsb 0 +#define reg_iop_version_r_version___nr___width 8 +#define reg_iop_version_r_version_offset 0 + + +/* Constants */ +#define regk_iop_version_v1_0 0x00000001 +#endif /* __iop_version_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h new file mode 100644 index 000000000000..90e4785b6474 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h @@ -0,0 +1,232 @@ +#ifndef __iop_crc_par_defs_h +#define __iop_crc_par_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_crc_par.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r + * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_crc_par */ + +/* Register rw_cfg, scope iop_crc_par, type rw */ +typedef struct { + unsigned int mode : 1; + unsigned int crc_out : 1; + unsigned int rev_out : 1; + unsigned int inv_out : 1; + unsigned int trig : 2; + unsigned int poly : 3; + unsigned int dummy1 : 23; +} reg_iop_crc_par_rw_cfg; +#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 +#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 + +/* Register rw_init_crc, scope iop_crc_par, type rw */ +typedef unsigned int reg_iop_crc_par_rw_init_crc; +#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 +#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 + +/* Register rw_correct_crc, scope iop_crc_par, type rw */ +typedef unsigned int reg_iop_crc_par_rw_correct_crc; +#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 +#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 + +/* Register rw_ctrl, scope iop_crc_par, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_iop_crc_par_rw_ctrl; +#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 +#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 + +/* Register rw_set_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int tr_dif : 1; + unsigned int dummy1 : 31; +} reg_iop_crc_par_rw_set_last; +#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 +#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 + +/* Register rw_wr1byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_crc_par_rw_wr1byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 +#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 + +/* Register rw_wr2byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_crc_par_rw_wr2byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 +#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 + +/* Register rw_wr3byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_crc_par_rw_wr3byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 +#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 + +/* Register rw_wr4byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_crc_par_rw_wr4byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 +#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 + +/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_crc_par_rw_wr1byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 +#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 + +/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_crc_par_rw_wr2byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 +#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 + +/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_crc_par_rw_wr3byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 +#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 + +/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_crc_par_rw_wr4byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 +#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 + +/* Register r_stat, scope iop_crc_par, type r */ +typedef struct { + unsigned int err : 1; + unsigned int busy : 1; + unsigned int dummy1 : 30; +} reg_iop_crc_par_r_stat; +#define REG_RD_ADDR_iop_crc_par_r_stat 52 + +/* Register r_sh_reg, scope iop_crc_par, type r */ +typedef unsigned int reg_iop_crc_par_r_sh_reg; +#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 + +/* Register r_crc, scope iop_crc_par, type r */ +typedef unsigned int reg_iop_crc_par_r_crc; +#define REG_RD_ADDR_iop_crc_par_r_crc 60 + +/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_crc_par_rw_strb_rec_dif_in; +#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 +#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 + + +/* Constants */ +enum { + regk_iop_crc_par_calc = 0x00000001, + regk_iop_crc_par_ccitt = 0x00000002, + regk_iop_crc_par_check = 0x00000000, + regk_iop_crc_par_crc16 = 0x00000001, + regk_iop_crc_par_crc32 = 0x00000000, + regk_iop_crc_par_crc5 = 0x00000003, + regk_iop_crc_par_crc5_11 = 0x00000004, + regk_iop_crc_par_dif_in = 0x00000002, + regk_iop_crc_par_hi = 0x00000000, + regk_iop_crc_par_neg = 0x00000002, + regk_iop_crc_par_no = 0x00000000, + regk_iop_crc_par_pos = 0x00000001, + regk_iop_crc_par_pos_neg = 0x00000003, + regk_iop_crc_par_rw_cfg_default = 0x00000000, + regk_iop_crc_par_rw_ctrl_default = 0x00000000, + regk_iop_crc_par_yes = 0x00000001 +}; +#endif /* __iop_crc_par_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h new file mode 100644 index 000000000000..76aec6e37f3e --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h @@ -0,0 +1,325 @@ +#ifndef __iop_dmc_in_defs_h +#define __iop_dmc_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_in.r + * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r + * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_dmc_in */ + +/* Register rw_cfg, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int sth_intr : 3; + unsigned int last_dis_dif : 1; + unsigned int dummy1 : 28; +} reg_iop_dmc_in_rw_cfg; +#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 +#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dif_dis : 1; + unsigned int stream_clr : 1; + unsigned int dummy1 : 29; +} reg_iop_dmc_in_rw_ctrl; +#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 + +/* Register r_stat, scope iop_dmc_in, type r */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dummy1 : 31; +} reg_iop_dmc_in_r_stat; +#define REG_RD_ADDR_iop_dmc_in_r_stat 8 + +/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 8; +} reg_iop_dmc_in_rw_stream_cmd; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 + +/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 + +/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 + +/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int eop : 1; + unsigned int wait : 1; + unsigned int keep_md : 1; + unsigned int size : 3; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_stream_ctrl; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 + +/* Register r_stream_stat, scope iop_dmc_in, type r */ +typedef struct { + unsigned int sth : 7; + unsigned int dummy1 : 9; + unsigned int full : 1; + unsigned int last_pkt : 1; + unsigned int data_md_valid : 1; + unsigned int ctxt_md_valid : 1; + unsigned int group_md_valid : 1; + unsigned int stream_busy : 1; + unsigned int cmd_rdy : 1; + unsigned int dummy2 : 9; +} reg_iop_dmc_in_r_stream_stat; +#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 + +/* Register r_data_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_in_r_data_descr; +#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 + +/* Register r_ctxt_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md0 : 16; +} reg_iop_dmc_in_r_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 + +/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ +typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 + +/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ +typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 + +/* Register r_group_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_in_r_group_descr; +#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 + +/* Register rw_data_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_in_rw_data_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 +#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 + +/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md0 : 16; +} reg_iop_dmc_in_rw_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 + +/* Register rw_group_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_in_rw_group_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 +#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 + +/* Register rw_intr_mask, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_intr_mask; +#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 +#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 + +/* Register rw_ack_intr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_ack_intr; +#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 +#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 + +/* Register r_intr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_r_intr; +#define REG_RD_ADDR_iop_dmc_in_r_intr 96 + +/* Register r_masked_intr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_r_masked_intr; +#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 + + +/* Constants */ +enum { + regk_iop_dmc_in_ack_pkt = 0x00000100, + regk_iop_dmc_in_array = 0x00000008, + regk_iop_dmc_in_burst = 0x00000020, + regk_iop_dmc_in_copy_next = 0x00000010, + regk_iop_dmc_in_copy_up = 0x00000020, + regk_iop_dmc_in_dis_c = 0x00000010, + regk_iop_dmc_in_dis_g = 0x00000020, + regk_iop_dmc_in_lim1 = 0x00000000, + regk_iop_dmc_in_lim16 = 0x00000004, + regk_iop_dmc_in_lim2 = 0x00000001, + regk_iop_dmc_in_lim32 = 0x00000005, + regk_iop_dmc_in_lim4 = 0x00000002, + regk_iop_dmc_in_lim64 = 0x00000006, + regk_iop_dmc_in_lim8 = 0x00000003, + regk_iop_dmc_in_load_c = 0x00000200, + regk_iop_dmc_in_load_c_n = 0x00000280, + regk_iop_dmc_in_load_c_next = 0x00000240, + regk_iop_dmc_in_load_d = 0x00000140, + regk_iop_dmc_in_load_g = 0x00000300, + regk_iop_dmc_in_load_g_down = 0x000003c0, + regk_iop_dmc_in_load_g_next = 0x00000340, + regk_iop_dmc_in_load_g_up = 0x00000380, + regk_iop_dmc_in_next_en = 0x00000010, + regk_iop_dmc_in_next_pkt = 0x00000010, + regk_iop_dmc_in_no = 0x00000000, + regk_iop_dmc_in_restore = 0x00000020, + regk_iop_dmc_in_rw_cfg_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, + regk_iop_dmc_in_rw_data_descr_default = 0x00000000, + regk_iop_dmc_in_rw_group_descr_default = 0x00000000, + regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, + regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, + regk_iop_dmc_in_save_down = 0x00000020, + regk_iop_dmc_in_save_up = 0x00000020, + regk_iop_dmc_in_set_reg = 0x00000050, + regk_iop_dmc_in_set_w_size1 = 0x00000190, + regk_iop_dmc_in_set_w_size2 = 0x000001a0, + regk_iop_dmc_in_set_w_size4 = 0x000001c0, + regk_iop_dmc_in_store_c = 0x00000002, + regk_iop_dmc_in_store_descr = 0x00000000, + regk_iop_dmc_in_store_g = 0x00000004, + regk_iop_dmc_in_store_md = 0x00000001, + regk_iop_dmc_in_update_down = 0x00000020, + regk_iop_dmc_in_yes = 0x00000001 +}; +#endif /* __iop_dmc_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h new file mode 100644 index 000000000000..938a0d4c4604 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h @@ -0,0 +1,326 @@ +#ifndef __iop_dmc_out_defs_h +#define __iop_dmc_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_out.r + * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r + * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_dmc_out */ + +/* Register rw_cfg, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int trf_lim : 16; + unsigned int last_at_trf_lim : 1; + unsigned int dth_intr : 3; + unsigned int dummy1 : 12; +} reg_iop_dmc_out_rw_cfg; +#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 +#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dif_dis : 1; + unsigned int dummy1 : 30; +} reg_iop_dmc_out_rw_ctrl; +#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 + +/* Register r_stat, scope iop_dmc_out, type r */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dummy1 : 31; +} reg_iop_dmc_out_r_stat; +#define REG_RD_ADDR_iop_dmc_out_r_stat 8 + +/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 8; +} reg_iop_dmc_out_rw_stream_cmd; +#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 +#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 + +/* Register rs_stream_data, scope iop_dmc_out, type rs */ +typedef unsigned int reg_iop_dmc_out_rs_stream_data; +#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 + +/* Register r_stream_data, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_stream_data; +#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 + +/* Register r_stream_stat, scope iop_dmc_out, type r */ +typedef struct { + unsigned int dth : 7; + unsigned int dummy1 : 9; + unsigned int dv : 1; + unsigned int all_avail : 1; + unsigned int last : 1; + unsigned int size : 3; + unsigned int data_md_valid : 1; + unsigned int ctxt_md_valid : 1; + unsigned int group_md_valid : 1; + unsigned int stream_busy : 1; + unsigned int cmd_rdy : 1; + unsigned int cmd_rq : 1; + unsigned int dummy2 : 4; +} reg_iop_dmc_out_r_stream_stat; +#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 + +/* Register r_data_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_out_r_data_descr; +#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 + +/* Register r_ctxt_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md0 : 16; +} reg_iop_dmc_out_r_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 + +/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 + +/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 + +/* Register r_group_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_out_r_group_descr; +#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 + +/* Register rw_data_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_out_rw_data_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 +#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 + +/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md0 : 16; +} reg_iop_dmc_out_rw_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ +typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ +typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 + +/* Register rw_group_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_out_rw_group_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 +#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 + +/* Register rw_intr_mask, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_rw_intr_mask; +#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 +#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 + +/* Register rw_ack_intr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_rw_ack_intr; +#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 +#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 + +/* Register r_intr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_r_intr; +#define REG_RD_ADDR_iop_dmc_out_r_intr 92 + +/* Register r_masked_intr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_r_masked_intr; +#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 + + +/* Constants */ +enum { + regk_iop_dmc_out_ack_pkt = 0x00000100, + regk_iop_dmc_out_array = 0x00000008, + regk_iop_dmc_out_burst = 0x00000020, + regk_iop_dmc_out_copy_next = 0x00000010, + regk_iop_dmc_out_copy_up = 0x00000020, + regk_iop_dmc_out_dis_c = 0x00000010, + regk_iop_dmc_out_dis_g = 0x00000020, + regk_iop_dmc_out_lim1 = 0x00000000, + regk_iop_dmc_out_lim16 = 0x00000004, + regk_iop_dmc_out_lim2 = 0x00000001, + regk_iop_dmc_out_lim32 = 0x00000005, + regk_iop_dmc_out_lim4 = 0x00000002, + regk_iop_dmc_out_lim64 = 0x00000006, + regk_iop_dmc_out_lim8 = 0x00000003, + regk_iop_dmc_out_load_c = 0x00000200, + regk_iop_dmc_out_load_c_n = 0x00000280, + regk_iop_dmc_out_load_c_next = 0x00000240, + regk_iop_dmc_out_load_d = 0x00000140, + regk_iop_dmc_out_load_g = 0x00000300, + regk_iop_dmc_out_load_g_down = 0x000003c0, + regk_iop_dmc_out_load_g_next = 0x00000340, + regk_iop_dmc_out_load_g_up = 0x00000380, + regk_iop_dmc_out_next_en = 0x00000010, + regk_iop_dmc_out_next_pkt = 0x00000010, + regk_iop_dmc_out_no = 0x00000000, + regk_iop_dmc_out_restore = 0x00000020, + regk_iop_dmc_out_rw_cfg_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, + regk_iop_dmc_out_rw_data_descr_default = 0x00000000, + regk_iop_dmc_out_rw_group_descr_default = 0x00000000, + regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, + regk_iop_dmc_out_save_down = 0x00000020, + regk_iop_dmc_out_save_up = 0x00000020, + regk_iop_dmc_out_set_reg = 0x00000050, + regk_iop_dmc_out_set_w_size1 = 0x00000190, + regk_iop_dmc_out_set_w_size2 = 0x000001a0, + regk_iop_dmc_out_set_w_size4 = 0x000001c0, + regk_iop_dmc_out_store_c = 0x00000002, + regk_iop_dmc_out_store_descr = 0x00000000, + regk_iop_dmc_out_store_g = 0x00000004, + regk_iop_dmc_out_store_md = 0x00000001, + regk_iop_dmc_out_update_down = 0x00000020, + regk_iop_dmc_out_yes = 0x00000001 +}; +#endif /* __iop_dmc_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h new file mode 100644 index 000000000000..e0c982b263fa --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h @@ -0,0 +1,255 @@ +#ifndef __iop_fifo_in_defs_h +#define __iop_fifo_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in.r + * id: + * last modfied: Mon Apr 11 16:10:07 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r + * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_in */ + +/* Register rw_cfg, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int avail_lim : 3; + unsigned int byte_order : 2; + unsigned int trig : 2; + unsigned int last_dis_dif_in : 1; + unsigned int mode : 2; + unsigned int dummy1 : 22; +} reg_iop_fifo_in_rw_cfg; +#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 +#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_rw_ctrl; +#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 + +/* Register r_stat, scope iop_fifo_in, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 18; +} reg_iop_fifo_in_r_stat; +#define REG_RD_ADDR_iop_fifo_in_r_stat 8 + +/* Register rs_rd1byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_in_rs_rd1byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 + +/* Register r_rd1byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_in_r_rd1byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 + +/* Register rs_rd2byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_in_rs_rd2byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 + +/* Register r_rd2byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_in_r_rd2byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 + +/* Register rs_rd3byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_in_rs_rd3byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 + +/* Register r_rd3byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_in_r_rd3byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 + +/* Register rs_rd4byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_in_rs_rd4byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 + +/* Register r_rd4byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_in_r_rd4byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 + +/* Register rw_set_last, scope iop_fifo_in, type rw */ +typedef unsigned int reg_iop_fifo_in_rw_set_last; +#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 +#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 + +/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_rw_strb_dif_in; +#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 +#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 + +/* Register rw_intr_mask, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 +#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 + +/* Register rw_ack_intr, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 +#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 + +/* Register r_intr, scope iop_fifo_in, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_r_intr; +#define REG_RD_ADDR_iop_fifo_in_r_intr 60 + +/* Register r_masked_intr, scope iop_fifo_in, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 + + +/* Constants */ +enum { + regk_iop_fifo_in_dif_in = 0x00000002, + regk_iop_fifo_in_hi = 0x00000000, + regk_iop_fifo_in_neg = 0x00000002, + regk_iop_fifo_in_no = 0x00000000, + regk_iop_fifo_in_order16 = 0x00000001, + regk_iop_fifo_in_order24 = 0x00000002, + regk_iop_fifo_in_order32 = 0x00000003, + regk_iop_fifo_in_order8 = 0x00000000, + regk_iop_fifo_in_pos = 0x00000001, + regk_iop_fifo_in_pos_neg = 0x00000003, + regk_iop_fifo_in_rw_cfg_default = 0x00000024, + regk_iop_fifo_in_rw_ctrl_default = 0x00000000, + regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_in_rw_set_last_default = 0x00000000, + regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, + regk_iop_fifo_in_size16 = 0x00000002, + regk_iop_fifo_in_size24 = 0x00000001, + regk_iop_fifo_in_size32 = 0x00000000, + regk_iop_fifo_in_size8 = 0x00000003, + regk_iop_fifo_in_yes = 0x00000001 +}; +#endif /* __iop_fifo_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h new file mode 100644 index 000000000000..798ac95870e9 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h @@ -0,0 +1,164 @@ +#ifndef __iop_fifo_in_extra_defs_h +#define __iop_fifo_in_extra_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: + * last modfied: Mon Apr 11 16:10:08 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_in_extra */ + +/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ +typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 + +/* Register r_stat, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 18; +} reg_iop_fifo_in_extra_r_stat; +#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 + +/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_extra_rw_strb_dif_in; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 + +/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 + +/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 + +/* Register r_intr, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_r_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 + +/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 + + +/* Constants */ +enum { + regk_iop_fifo_in_extra_fifo_in = 0x00000002, + regk_iop_fifo_in_extra_no = 0x00000000, + regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_in_extra_yes = 0x00000001 +}; +#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h new file mode 100644 index 000000000000..833e10f02526 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h @@ -0,0 +1,278 @@ +#ifndef __iop_fifo_out_defs_h +#define __iop_fifo_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out.r + * id: + * last modfied: Mon Apr 11 16:10:09 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r + * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_out */ + +/* Register rw_cfg, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int free_lim : 3; + unsigned int byte_order : 2; + unsigned int trig : 2; + unsigned int last_dis_dif_in : 1; + unsigned int mode : 2; + unsigned int delay_out_last : 1; + unsigned int last_dis_dif_out : 1; + unsigned int dummy1 : 20; +} reg_iop_fifo_out_rw_cfg; +#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 +#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 30; +} reg_iop_fifo_out_rw_ctrl; +#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 + +/* Register r_stat, scope iop_fifo_out, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int zero_data_last : 1; + unsigned int dummy1 : 17; +} reg_iop_fifo_out_r_stat; +#define REG_RD_ADDR_iop_fifo_out_r_stat 8 + +/* Register rw_wr1byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_out_rw_wr1byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 +#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 + +/* Register rw_wr2byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_out_rw_wr2byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 +#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 + +/* Register rw_wr3byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_out_rw_wr3byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 +#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 + +/* Register rw_wr4byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_out_rw_wr4byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 +#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 + +/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_out_rw_wr1byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 +#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 + +/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_out_rw_wr2byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 +#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 + +/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_out_rw_wr3byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 +#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 + +/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_out_rw_wr4byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 +#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 + +/* Register rw_set_last, scope iop_fifo_out, type rw */ +typedef unsigned int reg_iop_fifo_out_rw_set_last; +#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 +#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 + +/* Register rs_rd_data, scope iop_fifo_out, type rs */ +typedef unsigned int reg_iop_fifo_out_rs_rd_data; +#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 + +/* Register r_rd_data, scope iop_fifo_out, type r */ +typedef unsigned int reg_iop_fifo_out_r_rd_data; +#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 + +/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ +typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; +#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 +#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 + +/* Register rw_intr_mask, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 +#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 + +/* Register rw_ack_intr, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 +#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 + +/* Register r_intr, scope iop_fifo_out, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_r_intr; +#define REG_RD_ADDR_iop_fifo_out_r_intr 68 + +/* Register r_masked_intr, scope iop_fifo_out, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 + + +/* Constants */ +enum { + regk_iop_fifo_out_hi = 0x00000000, + regk_iop_fifo_out_neg = 0x00000002, + regk_iop_fifo_out_no = 0x00000000, + regk_iop_fifo_out_order16 = 0x00000001, + regk_iop_fifo_out_order24 = 0x00000002, + regk_iop_fifo_out_order32 = 0x00000003, + regk_iop_fifo_out_order8 = 0x00000000, + regk_iop_fifo_out_pos = 0x00000001, + regk_iop_fifo_out_pos_neg = 0x00000003, + regk_iop_fifo_out_rw_cfg_default = 0x00000024, + regk_iop_fifo_out_rw_ctrl_default = 0x00000000, + regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_out_rw_set_last_default = 0x00000000, + regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, + regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, + regk_iop_fifo_out_size16 = 0x00000002, + regk_iop_fifo_out_size24 = 0x00000001, + regk_iop_fifo_out_size32 = 0x00000000, + regk_iop_fifo_out_size8 = 0x00000003, + regk_iop_fifo_out_yes = 0x00000001 +}; +#endif /* __iop_fifo_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h new file mode 100644 index 000000000000..4a840aae84ee --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h @@ -0,0 +1,164 @@ +#ifndef __iop_fifo_out_extra_defs_h +#define __iop_fifo_out_extra_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: + * last modfied: Mon Apr 11 16:10:10 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_out_extra */ + +/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ +typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; +#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 + +/* Register r_rd_data, scope iop_fifo_out_extra, type r */ +typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; +#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 + +/* Register r_stat, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int zero_data_last : 1; + unsigned int dummy1 : 17; +} reg_iop_fifo_out_extra_r_stat; +#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 + +/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ +typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 + +/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 + +/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 + +/* Register r_intr, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_r_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 + +/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 + + +/* Constants */ +enum { + regk_iop_fifo_out_extra_no = 0x00000000, + regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_out_extra_yes = 0x00000001 +}; +#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h new file mode 100644 index 000000000000..c2b0ba1be60f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h @@ -0,0 +1,190 @@ +#ifndef __iop_mpu_defs_h +#define __iop_mpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_mpu.r + * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r + * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_mpu */ + +#define STRIDE_iop_mpu_rw_r 4 +/* Register rw_r, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_r; +#define REG_RD_ADDR_iop_mpu_rw_r 0 +#define REG_WR_ADDR_iop_mpu_rw_r 0 + +/* Register rw_ctrl, scope iop_mpu, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_iop_mpu_rw_ctrl; +#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 +#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 + +/* Register r_pc, scope iop_mpu, type r */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_r_pc; +#define REG_RD_ADDR_iop_mpu_r_pc 132 + +/* Register r_stat, scope iop_mpu, type r */ +typedef struct { + unsigned int instr_reg_busy : 1; + unsigned int intr_busy : 1; + unsigned int intr_vect : 16; + unsigned int dummy1 : 14; +} reg_iop_mpu_r_stat; +#define REG_RD_ADDR_iop_mpu_r_stat 136 + +/* Register rw_instr, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_instr; +#define REG_RD_ADDR_iop_mpu_rw_instr 140 +#define REG_WR_ADDR_iop_mpu_rw_instr 140 + +/* Register rw_immediate, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_immediate; +#define REG_RD_ADDR_iop_mpu_rw_immediate 144 +#define REG_WR_ADDR_iop_mpu_rw_immediate 144 + +/* Register r_trace, scope iop_mpu, type r */ +typedef struct { + unsigned int intr_vect : 16; + unsigned int pc : 12; + unsigned int en : 1; + unsigned int instr_reg_busy : 1; + unsigned int intr_busy : 1; + unsigned int dummy1 : 1; +} reg_iop_mpu_r_trace; +#define REG_RD_ADDR_iop_mpu_r_trace 148 + +/* Register r_wr_stat, scope iop_mpu, type r */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_mpu_r_wr_stat; +#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 + +#define STRIDE_iop_mpu_rw_thread 4 +/* Register rw_thread, scope iop_mpu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_rw_thread; +#define REG_RD_ADDR_iop_mpu_rw_thread 156 +#define REG_WR_ADDR_iop_mpu_rw_thread 156 + +#define STRIDE_iop_mpu_rw_intr 4 +/* Register rw_intr, scope iop_mpu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_rw_intr; +#define REG_RD_ADDR_iop_mpu_rw_intr 196 +#define REG_WR_ADDR_iop_mpu_rw_intr 196 + + +/* Constants */ +enum { + regk_iop_mpu_no = 0x00000000, + regk_iop_mpu_r_pc_default = 0x00000000, + regk_iop_mpu_rw_ctrl_default = 0x00000000, + regk_iop_mpu_rw_intr_size = 0x00000010, + regk_iop_mpu_rw_r_size = 0x00000010, + regk_iop_mpu_rw_thread_default = 0x00000000, + regk_iop_mpu_rw_thread_size = 0x00000004, + regk_iop_mpu_yes = 0x00000001 +}; +#endif /* __iop_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h new file mode 100644 index 000000000000..2ec897ced166 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h @@ -0,0 +1,764 @@ +/* ************************************************************************* */ +/* This file is autogenerated by IOPASM Version 1.2 */ +/* DO NOT EDIT THIS FILE - All changes will be lost! */ +/* ************************************************************************* */ + + + +#ifndef __IOP_MPU_MACROS_H__ +#define __IOP_MPU_MACROS_H__ + + +/* ************************************************************************* */ +/* REGISTER DEFINITIONS */ +/* ************************************************************************* */ +#define MPU_R0 (0x0) +#define MPU_R1 (0x1) +#define MPU_R2 (0x2) +#define MPU_R3 (0x3) +#define MPU_R4 (0x4) +#define MPU_R5 (0x5) +#define MPU_R6 (0x6) +#define MPU_R7 (0x7) +#define MPU_R8 (0x8) +#define MPU_R9 (0x9) +#define MPU_R10 (0xa) +#define MPU_R11 (0xb) +#define MPU_R12 (0xc) +#define MPU_R13 (0xd) +#define MPU_R14 (0xe) +#define MPU_R15 (0xf) +#define MPU_PC (0x2) +#define MPU_WSTS (0x3) +#define MPU_JADDR (0x4) +#define MPU_IRP (0x5) +#define MPU_SRP (0x6) +#define MPU_T0 (0x8) +#define MPU_T1 (0x9) +#define MPU_T2 (0xa) +#define MPU_T3 (0xb) +#define MPU_I0 (0x10) +#define MPU_I1 (0x11) +#define MPU_I2 (0x12) +#define MPU_I3 (0x13) +#define MPU_I4 (0x14) +#define MPU_I5 (0x15) +#define MPU_I6 (0x16) +#define MPU_I7 (0x17) +#define MPU_I8 (0x18) +#define MPU_I9 (0x19) +#define MPU_I10 (0x1a) +#define MPU_I11 (0x1b) +#define MPU_I12 (0x1c) +#define MPU_I13 (0x1d) +#define MPU_I14 (0x1e) +#define MPU_I15 (0x1f) +#define MPU_P2 (0x2) +#define MPU_P3 (0x3) +#define MPU_P5 (0x5) +#define MPU_P6 (0x6) +#define MPU_P8 (0x8) +#define MPU_P9 (0x9) +#define MPU_P10 (0xa) +#define MPU_P11 (0xb) +#define MPU_P16 (0x10) +#define MPU_P17 (0x12) +#define MPU_P18 (0x12) +#define MPU_P19 (0x13) +#define MPU_P20 (0x14) +#define MPU_P21 (0x15) +#define MPU_P22 (0x16) +#define MPU_P23 (0x17) +#define MPU_P24 (0x18) +#define MPU_P25 (0x19) +#define MPU_P26 (0x1a) +#define MPU_P27 (0x1b) +#define MPU_P28 (0x1c) +#define MPU_P29 (0x1d) +#define MPU_P30 (0x1e) +#define MPU_P31 (0x1f) +#define MPU_P1 (0x1) +#define MPU_REGA (0x1) + + + +/* ************************************************************************* */ +/* ADDRESS MACROS */ +/* ************************************************************************* */ +#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) +#define MK_BYTE_ADDR(ADDR) (ADDR) + + + +/* ************************************************************************* */ +/* INSTRUCTION MACROS */ +/* ************************************************************************* */ +#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 21)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 21)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_DI() (0x40000001) + +#define MPU_EI() (0x40000003) + +#define MPU_HALT() (0x40000002) + +#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JNT() (0x61000000) + +#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_NOP() (0x40000000) + +#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_RET() (0x63003000) + +#define MPU_RETI() (0x63602800) + +#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ + | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + + +#endif /* end of __IOP_MPU_MACROS_H__ */ +/* End of iop_mpu_macros.h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h new file mode 100644 index 000000000000..756550f5d6cb --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h @@ -0,0 +1,44 @@ +/* Autogenerated Changes here will be lost! + * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg + */ +#define regi_iop_version (regi_iop + 0) +#define regi_iop_fifo_in0_extra (regi_iop + 64) +#define regi_iop_fifo_in1_extra (regi_iop + 128) +#define regi_iop_fifo_out0_extra (regi_iop + 192) +#define regi_iop_fifo_out1_extra (regi_iop + 256) +#define regi_iop_trigger_grp0 (regi_iop + 320) +#define regi_iop_trigger_grp1 (regi_iop + 384) +#define regi_iop_trigger_grp2 (regi_iop + 448) +#define regi_iop_trigger_grp3 (regi_iop + 512) +#define regi_iop_trigger_grp4 (regi_iop + 576) +#define regi_iop_trigger_grp5 (regi_iop + 640) +#define regi_iop_trigger_grp6 (regi_iop + 704) +#define regi_iop_trigger_grp7 (regi_iop + 768) +#define regi_iop_crc_par0 (regi_iop + 896) +#define regi_iop_crc_par1 (regi_iop + 1024) +#define regi_iop_dmc_in0 (regi_iop + 1152) +#define regi_iop_dmc_in1 (regi_iop + 1280) +#define regi_iop_dmc_out0 (regi_iop + 1408) +#define regi_iop_dmc_out1 (regi_iop + 1536) +#define regi_iop_fifo_in0 (regi_iop + 1664) +#define regi_iop_fifo_in1 (regi_iop + 1792) +#define regi_iop_fifo_out0 (regi_iop + 1920) +#define regi_iop_fifo_out1 (regi_iop + 2048) +#define regi_iop_scrc_in0 (regi_iop + 2176) +#define regi_iop_scrc_in1 (regi_iop + 2304) +#define regi_iop_scrc_out0 (regi_iop + 2432) +#define regi_iop_scrc_out1 (regi_iop + 2560) +#define regi_iop_timer_grp0 (regi_iop + 2688) +#define regi_iop_timer_grp1 (regi_iop + 2816) +#define regi_iop_timer_grp2 (regi_iop + 2944) +#define regi_iop_timer_grp3 (regi_iop + 3072) +#define regi_iop_sap_in (regi_iop + 3328) +#define regi_iop_sap_out (regi_iop + 3584) +#define regi_iop_spu0 (regi_iop + 3840) +#define regi_iop_spu1 (regi_iop + 4096) +#define regi_iop_sw_cfg (regi_iop + 4352) +#define regi_iop_sw_cpu (regi_iop + 4608) +#define regi_iop_sw_mpu (regi_iop + 4864) +#define regi_iop_sw_spu0 (regi_iop + 5120) +#define regi_iop_sw_spu1 (regi_iop + 5376) +#define regi_iop_mpu (regi_iop + 5632) diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 000000000000..5548ac10074f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h @@ -0,0 +1,179 @@ +#ifndef __iop_sap_in_defs_h +#define __iop_sap_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_in.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r + * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_in */ + +/* Register rw_bus0_sync, scope iop_sap_in, type rw */ +typedef struct { + unsigned int byte0_sel : 2; + unsigned int byte0_ext_src : 3; + unsigned int byte0_edge : 2; + unsigned int byte0_delay : 1; + unsigned int byte1_sel : 2; + unsigned int byte1_ext_src : 3; + unsigned int byte1_edge : 2; + unsigned int byte1_delay : 1; + unsigned int byte2_sel : 2; + unsigned int byte2_ext_src : 3; + unsigned int byte2_edge : 2; + unsigned int byte2_delay : 1; + unsigned int byte3_sel : 2; + unsigned int byte3_ext_src : 3; + unsigned int byte3_edge : 2; + unsigned int byte3_delay : 1; +} reg_iop_sap_in_rw_bus0_sync; +#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 +#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 + +/* Register rw_bus1_sync, scope iop_sap_in, type rw */ +typedef struct { + unsigned int byte0_sel : 2; + unsigned int byte0_ext_src : 3; + unsigned int byte0_edge : 2; + unsigned int byte0_delay : 1; + unsigned int byte1_sel : 2; + unsigned int byte1_ext_src : 3; + unsigned int byte1_edge : 2; + unsigned int byte1_delay : 1; + unsigned int byte2_sel : 2; + unsigned int byte2_ext_src : 3; + unsigned int byte2_edge : 2; + unsigned int byte2_delay : 1; + unsigned int byte3_sel : 2; + unsigned int byte3_ext_src : 3; + unsigned int byte3_edge : 2; + unsigned int byte3_delay : 1; +} reg_iop_sap_in_rw_bus1_sync; +#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 +#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 1; + unsigned int logic : 2; + unsigned int dummy1 : 22; +} reg_iop_sap_in_rw_gio; +#define REG_RD_ADDR_iop_sap_in_rw_gio 8 +#define REG_WR_ADDR_iop_sap_in_rw_gio 8 + + +/* Constants */ +enum { + regk_iop_sap_in_and = 0x00000002, + regk_iop_sap_in_ext_clk200 = 0x00000003, + regk_iop_sap_in_gio1 = 0x00000000, + regk_iop_sap_in_gio13 = 0x00000005, + regk_iop_sap_in_gio18 = 0x00000003, + regk_iop_sap_in_gio19 = 0x00000004, + regk_iop_sap_in_gio21 = 0x00000006, + regk_iop_sap_in_gio23 = 0x00000005, + regk_iop_sap_in_gio29 = 0x00000007, + regk_iop_sap_in_gio5 = 0x00000004, + regk_iop_sap_in_gio6 = 0x00000001, + regk_iop_sap_in_gio7 = 0x00000002, + regk_iop_sap_in_inv = 0x00000001, + regk_iop_sap_in_neg = 0x00000002, + regk_iop_sap_in_no = 0x00000000, + regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, + regk_iop_sap_in_none = 0x00000000, + regk_iop_sap_in_or = 0x00000003, + regk_iop_sap_in_pos = 0x00000001, + regk_iop_sap_in_pos_neg = 0x00000003, + regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, + regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, + regk_iop_sap_in_rw_gio_default = 0x00000002, + regk_iop_sap_in_rw_gio_size = 0x00000020, + regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, + regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, + regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, + regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, + regk_iop_sap_in_tmr_clk200 = 0x00000000, + regk_iop_sap_in_two_clk200 = 0x00000002, + regk_iop_sap_in_yes = 0x00000001 +}; +#endif /* __iop_sap_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 000000000000..273936996183 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h @@ -0,0 +1,306 @@ +#ifndef __iop_sap_out_defs_h +#define __iop_sap_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_out.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r + * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_out */ + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +typedef struct { + unsigned int clk0_src : 2; + unsigned int clk0_gate_src : 2; + unsigned int clk0_force_src : 3; + unsigned int clk1_src : 2; + unsigned int clk1_gate_src : 2; + unsigned int clk1_force_src : 3; + unsigned int clk2_src : 2; + unsigned int clk2_gate_src : 2; + unsigned int clk2_force_src : 3; + unsigned int clk3_src : 2; + unsigned int clk3_gate_src : 2; + unsigned int clk3_force_src : 3; + unsigned int dummy1 : 4; +} reg_iop_sap_out_rw_gen_gated; +#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 +#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 + +/* Register rw_bus0, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte2_clk_sel : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_bus0; +#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 +#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 + +/* Register rw_bus1, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte2_clk_sel : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_bus1; +#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 +#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 + +/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_clk_ext : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_logic : 2; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_clk_ext : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus0_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 +#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 + +/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 3; + unsigned int byte2_clk_ext : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_logic : 2; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_clk_ext : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus0_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 +#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 + +/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_clk_ext : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_logic : 2; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_clk_ext : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus1_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 +#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 + +/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 3; + unsigned int byte2_clk_ext : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_logic : 2; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_clk_ext : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus1_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 +#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +typedef struct { + unsigned int out_clk_sel : 3; + unsigned int out_clk_ext : 4; + unsigned int out_gated_clk : 2; + unsigned int out_clk_inv : 1; + unsigned int out_logic : 1; + unsigned int oe_clk_sel : 3; + unsigned int oe_clk_ext : 3; + unsigned int oe_gated_clk : 2; + unsigned int oe_clk_inv : 1; + unsigned int oe_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_gio; +#define REG_RD_ADDR_iop_sap_out_rw_gio 28 +#define REG_WR_ADDR_iop_sap_out_rw_gio 28 + + +/* Constants */ +enum { + regk_iop_sap_out_and = 0x00000002, + regk_iop_sap_out_clk0 = 0x00000000, + regk_iop_sap_out_clk1 = 0x00000001, + regk_iop_sap_out_clk12 = 0x00000002, + regk_iop_sap_out_clk2 = 0x00000002, + regk_iop_sap_out_clk200 = 0x00000001, + regk_iop_sap_out_clk3 = 0x00000003, + regk_iop_sap_out_ext = 0x00000003, + regk_iop_sap_out_gated = 0x00000004, + regk_iop_sap_out_gio1 = 0x00000000, + regk_iop_sap_out_gio13 = 0x00000002, + regk_iop_sap_out_gio13_clk = 0x0000000c, + regk_iop_sap_out_gio15 = 0x00000001, + regk_iop_sap_out_gio18 = 0x00000003, + regk_iop_sap_out_gio18_clk = 0x0000000d, + regk_iop_sap_out_gio1_clk = 0x00000008, + regk_iop_sap_out_gio21_clk = 0x0000000e, + regk_iop_sap_out_gio23 = 0x00000002, + regk_iop_sap_out_gio29_clk = 0x0000000f, + regk_iop_sap_out_gio31 = 0x00000003, + regk_iop_sap_out_gio5 = 0x00000001, + regk_iop_sap_out_gio5_clk = 0x00000009, + regk_iop_sap_out_gio6_clk = 0x0000000a, + regk_iop_sap_out_gio7 = 0x00000000, + regk_iop_sap_out_gio7_clk = 0x0000000b, + regk_iop_sap_out_gio_in13 = 0x00000001, + regk_iop_sap_out_gio_in21 = 0x00000002, + regk_iop_sap_out_gio_in29 = 0x00000003, + regk_iop_sap_out_gio_in5 = 0x00000000, + regk_iop_sap_out_inv = 0x00000001, + regk_iop_sap_out_nand = 0x00000003, + regk_iop_sap_out_no = 0x00000000, + regk_iop_sap_out_none = 0x00000000, + regk_iop_sap_out_rw_bus0_default = 0x00000000, + regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus1_default = 0x00000000, + regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_gen_gated_default = 0x00000000, + regk_iop_sap_out_rw_gio_default = 0x00000000, + regk_iop_sap_out_rw_gio_size = 0x00000020, + regk_iop_sap_out_spu0_gio0 = 0x00000002, + regk_iop_sap_out_spu0_gio1 = 0x00000003, + regk_iop_sap_out_spu0_gio12 = 0x00000004, + regk_iop_sap_out_spu0_gio13 = 0x00000004, + regk_iop_sap_out_spu0_gio14 = 0x00000004, + regk_iop_sap_out_spu0_gio15 = 0x00000004, + regk_iop_sap_out_spu0_gio2 = 0x00000002, + regk_iop_sap_out_spu0_gio3 = 0x00000003, + regk_iop_sap_out_spu0_gio4 = 0x00000002, + regk_iop_sap_out_spu0_gio5 = 0x00000003, + regk_iop_sap_out_spu0_gio6 = 0x00000002, + regk_iop_sap_out_spu0_gio7 = 0x00000003, + regk_iop_sap_out_spu1_gio0 = 0x00000005, + regk_iop_sap_out_spu1_gio1 = 0x00000006, + regk_iop_sap_out_spu1_gio12 = 0x00000007, + regk_iop_sap_out_spu1_gio13 = 0x00000007, + regk_iop_sap_out_spu1_gio14 = 0x00000007, + regk_iop_sap_out_spu1_gio15 = 0x00000007, + regk_iop_sap_out_spu1_gio2 = 0x00000005, + regk_iop_sap_out_spu1_gio3 = 0x00000006, + regk_iop_sap_out_spu1_gio4 = 0x00000005, + regk_iop_sap_out_spu1_gio5 = 0x00000006, + regk_iop_sap_out_spu1_gio6 = 0x00000005, + regk_iop_sap_out_spu1_gio7 = 0x00000006, + regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, + regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, + regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, + regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, + regk_iop_sap_out_tmr = 0x00000005, + regk_iop_sap_out_yes = 0x00000001 +}; +#endif /* __iop_sap_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h new file mode 100644 index 000000000000..4f0a9a81e737 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h @@ -0,0 +1,160 @@ +#ifndef __iop_scrc_in_defs_h +#define __iop_scrc_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_in.r + * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r + * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_scrc_in */ + +/* Register rw_cfg, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int trig : 2; + unsigned int dummy1 : 30; +} reg_iop_scrc_in_rw_cfg; +#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 +#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_in_rw_ctrl; +#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 + +/* Register r_stat, scope iop_scrc_in, type r */ +typedef struct { + unsigned int err : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_in_r_stat; +#define REG_RD_ADDR_iop_scrc_in_r_stat 8 + +/* Register rw_init_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_init_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 +#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 + +/* Register rs_computed_crc, scope iop_scrc_in, type rs */ +typedef unsigned int reg_iop_scrc_in_rs_computed_crc; +#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 + +/* Register r_computed_crc, scope iop_scrc_in, type r */ +typedef unsigned int reg_iop_scrc_in_r_computed_crc; +#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 + +/* Register rw_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 +#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 + +/* Register rw_correct_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_correct_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 +#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 + +/* Register rw_wr1bit, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int data : 2; + unsigned int last : 2; + unsigned int dummy1 : 28; +} reg_iop_scrc_in_rw_wr1bit; +#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 +#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 + + +/* Constants */ +enum { + regk_iop_scrc_in_dif_in = 0x00000002, + regk_iop_scrc_in_hi = 0x00000000, + regk_iop_scrc_in_neg = 0x00000002, + regk_iop_scrc_in_no = 0x00000000, + regk_iop_scrc_in_pos = 0x00000001, + regk_iop_scrc_in_pos_neg = 0x00000003, + regk_iop_scrc_in_r_computed_crc_default = 0x00000000, + regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, + regk_iop_scrc_in_rw_cfg_default = 0x00000000, + regk_iop_scrc_in_rw_ctrl_default = 0x00000000, + regk_iop_scrc_in_rw_init_crc_default = 0x00000000, + regk_iop_scrc_in_set0 = 0x00000000, + regk_iop_scrc_in_set1 = 0x00000001, + regk_iop_scrc_in_yes = 0x00000001 +}; +#endif /* __iop_scrc_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h new file mode 100644 index 000000000000..fd1d6ea1d484 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h @@ -0,0 +1,146 @@ +#ifndef __iop_scrc_out_defs_h +#define __iop_scrc_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_out.r + * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r + * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_scrc_out */ + +/* Register rw_cfg, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int trig : 2; + unsigned int inv_crc : 1; + unsigned int dummy1 : 29; +} reg_iop_scrc_out_rw_cfg; +#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 +#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int strb_src : 1; + unsigned int out_src : 1; + unsigned int dummy1 : 30; +} reg_iop_scrc_out_rw_ctrl; +#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 + +/* Register rw_init_crc, scope iop_scrc_out, type rw */ +typedef unsigned int reg_iop_scrc_out_rw_init_crc; +#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 +#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 + +/* Register rw_crc, scope iop_scrc_out, type rw */ +typedef unsigned int reg_iop_scrc_out_rw_crc; +#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 +#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 + +/* Register rw_data, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int val : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_out_rw_data; +#define REG_RD_ADDR_iop_scrc_out_rw_data 16 +#define REG_WR_ADDR_iop_scrc_out_rw_data 16 + +/* Register r_computed_crc, scope iop_scrc_out, type r */ +typedef unsigned int reg_iop_scrc_out_r_computed_crc; +#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 + + +/* Constants */ +enum { + regk_iop_scrc_out_crc = 0x00000001, + regk_iop_scrc_out_data = 0x00000000, + regk_iop_scrc_out_dif = 0x00000001, + regk_iop_scrc_out_hi = 0x00000000, + regk_iop_scrc_out_neg = 0x00000002, + regk_iop_scrc_out_no = 0x00000000, + regk_iop_scrc_out_pos = 0x00000001, + regk_iop_scrc_out_pos_neg = 0x00000003, + regk_iop_scrc_out_reg = 0x00000000, + regk_iop_scrc_out_rw_cfg_default = 0x00000000, + regk_iop_scrc_out_rw_crc_default = 0x00000000, + regk_iop_scrc_out_rw_ctrl_default = 0x00000000, + regk_iop_scrc_out_rw_data_default = 0x00000000, + regk_iop_scrc_out_rw_init_crc_default = 0x00000000, + regk_iop_scrc_out_yes = 0x00000001 +}; +#endif /* __iop_scrc_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h new file mode 100644 index 000000000000..0fda26e2f06f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h @@ -0,0 +1,453 @@ +#ifndef __iop_spu_defs_h +#define __iop_spu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_spu.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r + * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_spu */ + +#define STRIDE_iop_spu_rw_r 4 +/* Register rw_r, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_r; +#define REG_RD_ADDR_iop_spu_rw_r 0 +#define REG_WR_ADDR_iop_spu_rw_r 0 + +/* Register rw_seq_pc, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_seq_pc; +#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 +#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 + +/* Register rw_fsm_pc, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_fsm_pc; +#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 +#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 + +/* Register rw_ctrl, scope iop_spu, type rw */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_iop_spu_rw_ctrl; +#define REG_RD_ADDR_iop_spu_rw_ctrl 72 +#define REG_WR_ADDR_iop_spu_rw_ctrl 72 + +/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ +typedef struct { + unsigned int val0 : 5; + unsigned int src0 : 3; + unsigned int val1 : 5; + unsigned int src1 : 3; + unsigned int val2 : 5; + unsigned int src2 : 3; + unsigned int val3 : 5; + unsigned int src3 : 3; +} reg_iop_spu_rw_fsm_inputs3_0; +#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 +#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 + +/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ +typedef struct { + unsigned int val4 : 5; + unsigned int src4 : 3; + unsigned int val5 : 5; + unsigned int src5 : 3; + unsigned int val6 : 5; + unsigned int src6 : 3; + unsigned int val7 : 5; + unsigned int src7 : 3; +} reg_iop_spu_rw_fsm_inputs7_4; +#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 +#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 + +/* Register rw_gio_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out; +#define REG_RD_ADDR_iop_spu_rw_gio_out 84 +#define REG_WR_ADDR_iop_spu_rw_gio_out 84 + +/* Register rw_bus0_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_bus0_out; +#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 +#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 + +/* Register rw_bus1_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_bus1_out; +#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 +#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 + +/* Register r_gio_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_gio_in; +#define REG_RD_ADDR_iop_spu_r_gio_in 96 + +/* Register r_bus0_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_bus0_in; +#define REG_RD_ADDR_iop_spu_r_bus0_in 100 + +/* Register r_bus1_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_bus1_in; +#define REG_RD_ADDR_iop_spu_r_bus1_in 104 + +/* Register rw_gio_out_set, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out_set; +#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 +#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 + +/* Register rw_gio_out_clr, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out_clr; +#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 +#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 + +/* Register rs_wr_stat, scope iop_spu, type rs */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_spu_rs_wr_stat; +#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 + +/* Register r_wr_stat, scope iop_spu, type r */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_spu_r_wr_stat; +#define REG_RD_ADDR_iop_spu_r_wr_stat 120 + +/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; +#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 + +/* Register r_stat_in, scope iop_spu, type r */ +typedef struct { + unsigned int timer_grp_lo : 4; + unsigned int fifo_out_last : 1; + unsigned int fifo_out_rdy : 1; + unsigned int fifo_out_all : 1; + unsigned int fifo_in_rdy : 1; + unsigned int dmc_out_all : 1; + unsigned int dmc_out_dth : 1; + unsigned int dmc_out_eop : 1; + unsigned int dmc_out_dv : 1; + unsigned int dmc_out_last : 1; + unsigned int dmc_out_cmd_rq : 1; + unsigned int dmc_out_cmd_rdy : 1; + unsigned int pcrc_correct : 1; + unsigned int timer_grp_hi : 4; + unsigned int dmc_in_sth : 1; + unsigned int dmc_in_full : 1; + unsigned int dmc_in_cmd_rdy : 1; + unsigned int spu_gio_out : 4; + unsigned int sync_clk12 : 1; + unsigned int scrc_out_data : 1; + unsigned int scrc_in_err : 1; + unsigned int mc_busy : 1; + unsigned int mc_owned : 1; +} reg_iop_spu_r_stat_in; +#define REG_RD_ADDR_iop_spu_r_stat_in 128 + +/* Register r_trigger_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_trigger_in; +#define REG_RD_ADDR_iop_spu_r_trigger_in 132 + +/* Register r_special_stat, scope iop_spu, type r */ +typedef struct { + unsigned int c_flag : 1; + unsigned int v_flag : 1; + unsigned int z_flag : 1; + unsigned int n_flag : 1; + unsigned int xor_bus0_r2_0 : 1; + unsigned int xor_bus1_r3_0 : 1; + unsigned int xor_bus0m_r2_0 : 1; + unsigned int xor_bus1m_r3_0 : 1; + unsigned int fsm_in0 : 1; + unsigned int fsm_in1 : 1; + unsigned int fsm_in2 : 1; + unsigned int fsm_in3 : 1; + unsigned int fsm_in4 : 1; + unsigned int fsm_in5 : 1; + unsigned int fsm_in6 : 1; + unsigned int fsm_in7 : 1; + unsigned int event0 : 1; + unsigned int event1 : 1; + unsigned int event2 : 1; + unsigned int event3 : 1; + unsigned int dummy1 : 12; +} reg_iop_spu_r_special_stat; +#define REG_RD_ADDR_iop_spu_r_special_stat 136 + +/* Register rw_reg_access, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 13; + unsigned int dummy1 : 3; + unsigned int imm_hi : 16; +} reg_iop_spu_rw_reg_access; +#define REG_RD_ADDR_iop_spu_rw_reg_access 140 +#define REG_WR_ADDR_iop_spu_rw_reg_access 140 + +#define STRIDE_iop_spu_rw_event_cfg 4 +/* Register rw_event_cfg, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int src : 2; + unsigned int eq_en : 1; + unsigned int eq_inv : 1; + unsigned int gt_en : 1; + unsigned int gt_inv : 1; + unsigned int dummy1 : 14; +} reg_iop_spu_rw_event_cfg; +#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 +#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 + +#define STRIDE_iop_spu_rw_event_mask 4 +/* Register rw_event_mask, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_event_mask; +#define REG_RD_ADDR_iop_spu_rw_event_mask 160 +#define REG_WR_ADDR_iop_spu_rw_event_mask 160 + +#define STRIDE_iop_spu_rw_event_val 4 +/* Register rw_event_val, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_event_val; +#define REG_RD_ADDR_iop_spu_rw_event_val 176 +#define REG_WR_ADDR_iop_spu_rw_event_val 176 + +/* Register rw_event_ret, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_event_ret; +#define REG_RD_ADDR_iop_spu_rw_event_ret 192 +#define REG_WR_ADDR_iop_spu_rw_event_ret 192 + +/* Register r_trace, scope iop_spu, type r */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int c_flag : 1; + unsigned int v_flag : 1; + unsigned int z_flag : 1; + unsigned int n_flag : 1; + unsigned int seq_addr : 12; + unsigned int dummy1 : 2; + unsigned int fsm_addr : 12; +} reg_iop_spu_r_trace; +#define REG_RD_ADDR_iop_spu_r_trace 196 + +/* Register r_fsm_trace, scope iop_spu, type r */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int tmr_done : 1; + unsigned int inp0 : 1; + unsigned int inp1 : 1; + unsigned int inp2 : 1; + unsigned int inp3 : 1; + unsigned int event0 : 1; + unsigned int event1 : 1; + unsigned int event2 : 1; + unsigned int event3 : 1; + unsigned int gio_out : 8; + unsigned int dummy1 : 1; + unsigned int fsm_addr : 12; +} reg_iop_spu_r_fsm_trace; +#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 + +#define STRIDE_iop_spu_rw_brp 4 +/* Register rw_brp, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int dummy1 : 18; +} reg_iop_spu_rw_brp; +#define REG_RD_ADDR_iop_spu_rw_brp 204 +#define REG_WR_ADDR_iop_spu_rw_brp 204 + + +/* Constants */ +enum { + regk_iop_spu_attn_hi = 0x00000005, + regk_iop_spu_attn_lo = 0x00000005, + regk_iop_spu_attn_r0 = 0x00000000, + regk_iop_spu_attn_r1 = 0x00000001, + regk_iop_spu_attn_r10 = 0x00000002, + regk_iop_spu_attn_r11 = 0x00000003, + regk_iop_spu_attn_r12 = 0x00000004, + regk_iop_spu_attn_r13 = 0x00000005, + regk_iop_spu_attn_r14 = 0x00000006, + regk_iop_spu_attn_r15 = 0x00000007, + regk_iop_spu_attn_r2 = 0x00000002, + regk_iop_spu_attn_r3 = 0x00000003, + regk_iop_spu_attn_r4 = 0x00000004, + regk_iop_spu_attn_r5 = 0x00000005, + regk_iop_spu_attn_r6 = 0x00000006, + regk_iop_spu_attn_r7 = 0x00000007, + regk_iop_spu_attn_r8 = 0x00000000, + regk_iop_spu_attn_r9 = 0x00000001, + regk_iop_spu_c = 0x00000000, + regk_iop_spu_flag = 0x00000002, + regk_iop_spu_gio_in = 0x00000000, + regk_iop_spu_gio_out = 0x00000005, + regk_iop_spu_gio_out0 = 0x00000008, + regk_iop_spu_gio_out1 = 0x00000009, + regk_iop_spu_gio_out2 = 0x0000000a, + regk_iop_spu_gio_out3 = 0x0000000b, + regk_iop_spu_gio_out4 = 0x0000000c, + regk_iop_spu_gio_out5 = 0x0000000d, + regk_iop_spu_gio_out6 = 0x0000000e, + regk_iop_spu_gio_out7 = 0x0000000f, + regk_iop_spu_n = 0x00000003, + regk_iop_spu_no = 0x00000000, + regk_iop_spu_r0 = 0x00000008, + regk_iop_spu_r1 = 0x00000009, + regk_iop_spu_r10 = 0x0000000a, + regk_iop_spu_r11 = 0x0000000b, + regk_iop_spu_r12 = 0x0000000c, + regk_iop_spu_r13 = 0x0000000d, + regk_iop_spu_r14 = 0x0000000e, + regk_iop_spu_r15 = 0x0000000f, + regk_iop_spu_r2 = 0x0000000a, + regk_iop_spu_r3 = 0x0000000b, + regk_iop_spu_r4 = 0x0000000c, + regk_iop_spu_r5 = 0x0000000d, + regk_iop_spu_r6 = 0x0000000e, + regk_iop_spu_r7 = 0x0000000f, + regk_iop_spu_r8 = 0x00000008, + regk_iop_spu_r9 = 0x00000009, + regk_iop_spu_reg_hi = 0x00000002, + regk_iop_spu_reg_lo = 0x00000002, + regk_iop_spu_rw_brp_default = 0x00000000, + regk_iop_spu_rw_brp_size = 0x00000004, + regk_iop_spu_rw_ctrl_default = 0x00000000, + regk_iop_spu_rw_event_cfg_size = 0x00000004, + regk_iop_spu_rw_event_mask_size = 0x00000004, + regk_iop_spu_rw_event_val_size = 0x00000004, + regk_iop_spu_rw_gio_out_default = 0x00000000, + regk_iop_spu_rw_r_size = 0x00000010, + regk_iop_spu_rw_reg_access_default = 0x00000000, + regk_iop_spu_stat_in = 0x00000002, + regk_iop_spu_statin_hi = 0x00000004, + regk_iop_spu_statin_lo = 0x00000004, + regk_iop_spu_trig = 0x00000003, + regk_iop_spu_trigger = 0x00000006, + regk_iop_spu_v = 0x00000001, + regk_iop_spu_wsts_gioout_spec = 0x00000001, + regk_iop_spu_xor = 0x00000003, + regk_iop_spu_xor_bus0_r2_0 = 0x00000000, + regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, + regk_iop_spu_xor_bus1_r3_0 = 0x00000001, + regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, + regk_iop_spu_yes = 0x00000001, + regk_iop_spu_z = 0x00000002 +}; +#endif /* __iop_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 000000000000..d7b6d75884d2 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h @@ -0,0 +1,1042 @@ +#ifndef __iop_sw_cfg_defs_h +#define __iop_sw_cfg_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cfg */ + +/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 + +/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 + +/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 + +/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 + +/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 + +/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 + +/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 + +/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 + +/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 + +/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 + +/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 + +/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 + +/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 + +/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 + +/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 + +/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 + +/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 + +/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 + +/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 + +/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 + +/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 + +/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp4_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp5_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp6_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp7_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 + +/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus0_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 + +/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus0_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 + +/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus1_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 + +/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus1_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_byte0 : 2; + unsigned int bus0_byte1 : 2; + unsigned int bus0_byte2 : 2; + unsigned int bus0_byte3 : 2; + unsigned int bus1_byte0 : 2; + unsigned int bus1_byte1 : 2; + unsigned int bus1_byte2 : 2; + unsigned int bus1_byte3 : 2; + unsigned int gio3_0 : 2; + unsigned int gio7_4 : 2; + unsigned int gio11_8 : 2; + unsigned int gio15_12 : 2; + unsigned int gio19_16 : 2; + unsigned int gio23_20 : 2; + unsigned int gio27_24 : 2; + unsigned int gio31_28 : 2; +} reg_iop_sw_cfg_rw_pinmapping; +#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 +#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_lo : 3; + unsigned int bus0_hi : 3; + unsigned int bus0_lo_oe : 3; + unsigned int bus0_hi_oe : 3; + unsigned int bus1_lo : 3; + unsigned int bus1_hi : 3; + unsigned int bus1_lo_oe : 3; + unsigned int bus1_hi_oe : 3; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_bus_out_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio0 : 4; + unsigned int gio0_oe : 2; + unsigned int gio1 : 4; + unsigned int gio1_oe : 2; + unsigned int gio2 : 4; + unsigned int gio2_oe : 2; + unsigned int gio3 : 4; + unsigned int gio3_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio4 : 4; + unsigned int gio4_oe : 2; + unsigned int gio5 : 4; + unsigned int gio5_oe : 2; + unsigned int gio6 : 4; + unsigned int gio6_oe : 2; + unsigned int gio7 : 4; + unsigned int gio7_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio8 : 4; + unsigned int gio8_oe : 2; + unsigned int gio9 : 4; + unsigned int gio9_oe : 2; + unsigned int gio10 : 4; + unsigned int gio10_oe : 2; + unsigned int gio11 : 4; + unsigned int gio11_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio12 : 4; + unsigned int gio12_oe : 2; + unsigned int gio13 : 4; + unsigned int gio13_oe : 2; + unsigned int gio14 : 4; + unsigned int gio14_oe : 2; + unsigned int gio15 : 4; + unsigned int gio15_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio16 : 4; + unsigned int gio16_oe : 2; + unsigned int gio17 : 4; + unsigned int gio17_oe : 2; + unsigned int gio18 : 4; + unsigned int gio18_oe : 2; + unsigned int gio19 : 4; + unsigned int gio19_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio20 : 4; + unsigned int gio20_oe : 2; + unsigned int gio21 : 4; + unsigned int gio21_oe : 2; + unsigned int gio22 : 4; + unsigned int gio22_oe : 2; + unsigned int gio23 : 4; + unsigned int gio23_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio24 : 4; + unsigned int gio24_oe : 2; + unsigned int gio25 : 4; + unsigned int gio25_oe : 2; + unsigned int gio26 : 4; + unsigned int gio26_oe : 2; + unsigned int gio27 : 4; + unsigned int gio27_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio28 : 4; + unsigned int gio28_oe : 2; + unsigned int gio29 : 4; + unsigned int gio29_oe : 2; + unsigned int gio30 : 4; + unsigned int gio30_oe : 2; + unsigned int gio31 : 4; + unsigned int gio31_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 + +/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 2; + unsigned int bus1_in : 2; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_spu0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 + +/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 2; + unsigned int bus1_in : 2; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_spu1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 + +/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 + +/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int grp0_dis : 1; + unsigned int grp0_en : 1; + unsigned int grp1_dis : 1; + unsigned int grp1_en : 1; + unsigned int grp2_dis : 1; + unsigned int grp2_en : 1; + unsigned int grp3_dis : 1; + unsigned int grp3_en : 1; + unsigned int grp4_dis : 1; + unsigned int grp4_en : 1; + unsigned int grp5_dis : 1; + unsigned int grp5_en : 1; + unsigned int grp6_dis : 1; + unsigned int grp6_en : 1; + unsigned int grp7_dis : 1; + unsigned int grp7_en : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_trigger_grps_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 + +/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int dmc0_usr : 1; + unsigned int out_strb : 5; + unsigned int in_src : 3; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int out_src : 1; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_pdp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 + +/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int dmc1_usr : 1; + unsigned int out_strb : 5; + unsigned int in_src : 3; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int out_src : 1; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_pdp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int sdp_out0_strb : 3; + unsigned int sdp_out1_strb : 3; + unsigned int sdp_in0_data : 3; + unsigned int sdp_in0_last : 2; + unsigned int sdp_in0_strb : 3; + unsigned int sdp_in1_data : 3; + unsigned int sdp_in1_last : 2; + unsigned int sdp_in1_strb : 3; + unsigned int dummy1 : 10; +} reg_iop_sw_cfg_rw_sdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 +#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 + + +/* Constants */ +enum { + regk_iop_sw_cfg_a = 0x00000001, + regk_iop_sw_cfg_b = 0x00000002, + regk_iop_sw_cfg_bus0 = 0x00000000, + regk_iop_sw_cfg_bus0_rot16 = 0x00000004, + regk_iop_sw_cfg_bus0_rot24 = 0x00000006, + regk_iop_sw_cfg_bus0_rot8 = 0x00000002, + regk_iop_sw_cfg_bus1 = 0x00000001, + regk_iop_sw_cfg_bus1_rot16 = 0x00000005, + regk_iop_sw_cfg_bus1_rot24 = 0x00000007, + regk_iop_sw_cfg_bus1_rot8 = 0x00000003, + regk_iop_sw_cfg_clk12 = 0x00000000, + regk_iop_sw_cfg_cpu = 0x00000000, + regk_iop_sw_cfg_dmc0 = 0x00000000, + regk_iop_sw_cfg_dmc1 = 0x00000001, + regk_iop_sw_cfg_gated_clk0 = 0x00000010, + regk_iop_sw_cfg_gated_clk1 = 0x00000011, + regk_iop_sw_cfg_gated_clk2 = 0x00000012, + regk_iop_sw_cfg_gated_clk3 = 0x00000013, + regk_iop_sw_cfg_gio0 = 0x00000004, + regk_iop_sw_cfg_gio1 = 0x00000001, + regk_iop_sw_cfg_gio2 = 0x00000005, + regk_iop_sw_cfg_gio3 = 0x00000002, + regk_iop_sw_cfg_gio4 = 0x00000006, + regk_iop_sw_cfg_gio5 = 0x00000003, + regk_iop_sw_cfg_gio6 = 0x00000007, + regk_iop_sw_cfg_gio7 = 0x00000004, + regk_iop_sw_cfg_gio_in0 = 0x00000000, + regk_iop_sw_cfg_gio_in1 = 0x00000001, + regk_iop_sw_cfg_gio_in10 = 0x00000002, + regk_iop_sw_cfg_gio_in11 = 0x00000003, + regk_iop_sw_cfg_gio_in14 = 0x00000004, + regk_iop_sw_cfg_gio_in15 = 0x00000005, + regk_iop_sw_cfg_gio_in18 = 0x00000002, + regk_iop_sw_cfg_gio_in19 = 0x00000003, + regk_iop_sw_cfg_gio_in20 = 0x00000004, + regk_iop_sw_cfg_gio_in21 = 0x00000005, + regk_iop_sw_cfg_gio_in26 = 0x00000006, + regk_iop_sw_cfg_gio_in27 = 0x00000007, + regk_iop_sw_cfg_gio_in28 = 0x00000006, + regk_iop_sw_cfg_gio_in29 = 0x00000007, + regk_iop_sw_cfg_gio_in4 = 0x00000000, + regk_iop_sw_cfg_gio_in5 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, + regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, + regk_iop_sw_cfg_mpu = 0x00000001, + regk_iop_sw_cfg_none = 0x00000000, + regk_iop_sw_cfg_par0 = 0x00000000, + regk_iop_sw_cfg_par1 = 0x00000001, + regk_iop_sw_cfg_pdp_out0 = 0x00000002, + regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, + regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, + regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, + regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, + regk_iop_sw_cfg_pdp_out1 = 0x00000003, + regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, + regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, + regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, + regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, + regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, + regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, + regk_iop_sw_cfg_sdp_out0 = 0x00000008, + regk_iop_sw_cfg_sdp_out1 = 0x00000009, + regk_iop_sw_cfg_size16 = 0x00000002, + regk_iop_sw_cfg_size24 = 0x00000003, + regk_iop_sw_cfg_size32 = 0x00000004, + regk_iop_sw_cfg_size8 = 0x00000001, + regk_iop_sw_cfg_spu0 = 0x00000002, + regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, + regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, + regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, + regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, + regk_iop_sw_cfg_spu0_g0 = 0x0000000e, + regk_iop_sw_cfg_spu0_g1 = 0x0000000e, + regk_iop_sw_cfg_spu0_g2 = 0x0000000e, + regk_iop_sw_cfg_spu0_g3 = 0x0000000e, + regk_iop_sw_cfg_spu0_g4 = 0x0000000e, + regk_iop_sw_cfg_spu0_g5 = 0x0000000e, + regk_iop_sw_cfg_spu0_g6 = 0x0000000e, + regk_iop_sw_cfg_spu0_g7 = 0x0000000e, + regk_iop_sw_cfg_spu0_gio0 = 0x00000000, + regk_iop_sw_cfg_spu0_gio1 = 0x00000001, + regk_iop_sw_cfg_spu0_gio2 = 0x00000000, + regk_iop_sw_cfg_spu0_gio5 = 0x00000005, + regk_iop_sw_cfg_spu0_gio6 = 0x00000006, + regk_iop_sw_cfg_spu0_gio7 = 0x00000007, + regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, + regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, + regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, + regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, + regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, + regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, + regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, + regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, + regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, + regk_iop_sw_cfg_spu1 = 0x00000003, + regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, + regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, + regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, + regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, + regk_iop_sw_cfg_spu1_g0 = 0x0000000f, + regk_iop_sw_cfg_spu1_g1 = 0x0000000f, + regk_iop_sw_cfg_spu1_g2 = 0x0000000f, + regk_iop_sw_cfg_spu1_g3 = 0x0000000f, + regk_iop_sw_cfg_spu1_g4 = 0x0000000f, + regk_iop_sw_cfg_spu1_g5 = 0x0000000f, + regk_iop_sw_cfg_spu1_g6 = 0x0000000f, + regk_iop_sw_cfg_spu1_g7 = 0x0000000f, + regk_iop_sw_cfg_spu1_gio0 = 0x00000002, + regk_iop_sw_cfg_spu1_gio1 = 0x00000003, + regk_iop_sw_cfg_spu1_gio2 = 0x00000002, + regk_iop_sw_cfg_spu1_gio5 = 0x00000005, + regk_iop_sw_cfg_spu1_gio6 = 0x00000006, + regk_iop_sw_cfg_spu1_gio7 = 0x00000007, + regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, + regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, + regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, + regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, + regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, + regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, + regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, + regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, + regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, + regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, + regk_iop_sw_cfg_timer_grp0 = 0x00000000, + regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, + regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, + regk_iop_sw_cfg_timer_grp1 = 0x00000000, + regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, + regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, + regk_iop_sw_cfg_timer_grp2 = 0x00000000, + regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, + regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, + regk_iop_sw_cfg_timer_grp3 = 0x00000000, + regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, + regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, + regk_iop_sw_cfg_trig0_0 = 0x00000000, + regk_iop_sw_cfg_trig0_1 = 0x00000000, + regk_iop_sw_cfg_trig0_2 = 0x00000000, + regk_iop_sw_cfg_trig0_3 = 0x00000000, + regk_iop_sw_cfg_trig1_0 = 0x00000000, + regk_iop_sw_cfg_trig1_1 = 0x00000000, + regk_iop_sw_cfg_trig1_2 = 0x00000000, + regk_iop_sw_cfg_trig1_3 = 0x00000000, + regk_iop_sw_cfg_trig2_0 = 0x00000000, + regk_iop_sw_cfg_trig2_1 = 0x00000000, + regk_iop_sw_cfg_trig2_2 = 0x00000000, + regk_iop_sw_cfg_trig2_3 = 0x00000000, + regk_iop_sw_cfg_trig3_0 = 0x00000000, + regk_iop_sw_cfg_trig3_1 = 0x00000000, + regk_iop_sw_cfg_trig3_2 = 0x00000000, + regk_iop_sw_cfg_trig3_3 = 0x00000000, + regk_iop_sw_cfg_trig4_0 = 0x00000001, + regk_iop_sw_cfg_trig4_1 = 0x00000001, + regk_iop_sw_cfg_trig4_2 = 0x00000001, + regk_iop_sw_cfg_trig4_3 = 0x00000001, + regk_iop_sw_cfg_trig5_0 = 0x00000001, + regk_iop_sw_cfg_trig5_1 = 0x00000001, + regk_iop_sw_cfg_trig5_2 = 0x00000001, + regk_iop_sw_cfg_trig5_3 = 0x00000001, + regk_iop_sw_cfg_trig6_0 = 0x00000001, + regk_iop_sw_cfg_trig6_1 = 0x00000001, + regk_iop_sw_cfg_trig6_2 = 0x00000001, + regk_iop_sw_cfg_trig6_3 = 0x00000001, + regk_iop_sw_cfg_trig7_0 = 0x00000001, + regk_iop_sw_cfg_trig7_1 = 0x00000001, + regk_iop_sw_cfg_trig7_2 = 0x00000001, + regk_iop_sw_cfg_trig7_3 = 0x00000001 +}; +#endif /* __iop_sw_cfg_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 000000000000..5fed844b19e2 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h @@ -0,0 +1,853 @@ +#ifndef __iop_sw_cpu_defs_h +#define __iop_sw_cpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cpu */ + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_cpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +typedef unsigned int reg_iop_sw_cpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_cpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 + +/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 + +/* Register r_bus0_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 + +/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 + +/* Register r_bus1_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_rw_intr0_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_rw_ack_intr0; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_r_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_r_masked_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_rw_intr1_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_rw_ack_intr1; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_r_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_r_masked_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 + +/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_rw_intr2_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 + +/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr2; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 + +/* Register r_intr2, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_intr2; +#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 + +/* Register r_masked_intr2, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_masked_intr2; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 + +/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_rw_intr3_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 + +/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr3; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 + +/* Register r_intr3, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_r_intr3; +#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 + +/* Register r_masked_intr3, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_r_masked_intr3; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 + + +/* Constants */ +enum { + regk_iop_sw_cpu_copy = 0x00000000, + regk_iop_sw_cpu_no = 0x00000000, + regk_iop_sw_cpu_rd = 0x00000002, + regk_iop_sw_cpu_reg_copy = 0x00000001, + regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, + regk_iop_sw_cpu_wr = 0x00000003, + regk_iop_sw_cpu_yes = 0x00000001 +}; +#endif /* __iop_sw_cpu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 000000000000..da718f2a8cad --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h @@ -0,0 +1,893 @@ +#ifndef __iop_sw_mpu_defs_h +#define __iop_sw_mpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_mpu */ + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_mpu_rw_sw_cfg_owner; +#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 +#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_mpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +typedef unsigned int reg_iop_sw_mpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_mpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 + +/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 + +/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 + +/* Register r_bus0_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 + +/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 + +/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 + +/* Register r_bus1_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 +#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp0_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp1_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp2_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp3_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 + + +/* Constants */ +enum { + regk_iop_sw_mpu_copy = 0x00000000, + regk_iop_sw_mpu_cpu = 0x00000000, + regk_iop_sw_mpu_mpu = 0x00000001, + regk_iop_sw_mpu_no = 0x00000000, + regk_iop_sw_mpu_nop = 0x00000000, + regk_iop_sw_mpu_rd = 0x00000002, + regk_iop_sw_mpu_reg_copy = 0x00000001, + regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, + regk_iop_sw_mpu_set = 0x00000001, + regk_iop_sw_mpu_spu0 = 0x00000002, + regk_iop_sw_mpu_spu1 = 0x00000003, + regk_iop_sw_mpu_wr = 0x00000003, + regk_iop_sw_mpu_yes = 0x00000001 +}; +#endif /* __iop_sw_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 000000000000..b59dde4bd0d1 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h @@ -0,0 +1,552 @@ +#ifndef __iop_sw_spu_defs_h +#define __iop_sw_spu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_spu */ + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_spu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +typedef unsigned int reg_iop_sw_spu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +typedef unsigned int reg_iop_sw_spu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mc_data; +#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_spu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 + +/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 + +/* Register r_bus0_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 + +/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 + +/* Register r_bus1_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_gio_in; +#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 + +/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 + +/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 + +/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 + +/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 + +/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 + +/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 + +/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 + +/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 +#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out1 : 1; + unsigned int dmc_in1 : 1; + unsigned int dummy1 : 8; +} reg_iop_sw_spu_r_hw_intr; +#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 +#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int other_spu_intr0 : 1; + unsigned int other_spu_intr1 : 1; + unsigned int other_spu_intr2 : 1; + unsigned int other_spu_intr3 : 1; + unsigned int other_spu_intr4 : 1; + unsigned int other_spu_intr5 : 1; + unsigned int other_spu_intr6 : 1; + unsigned int other_spu_intr7 : 1; + unsigned int other_spu_intr8 : 1; + unsigned int other_spu_intr9 : 1; + unsigned int other_spu_intr10 : 1; + unsigned int other_spu_intr11 : 1; + unsigned int other_spu_intr12 : 1; + unsigned int other_spu_intr13 : 1; + unsigned int other_spu_intr14 : 1; + unsigned int other_spu_intr15 : 1; +} reg_iop_sw_spu_r_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 + + +/* Constants */ +enum { + regk_iop_sw_spu_copy = 0x00000000, + regk_iop_sw_spu_no = 0x00000000, + regk_iop_sw_spu_nop = 0x00000000, + regk_iop_sw_spu_rd = 0x00000002, + regk_iop_sw_spu_reg_copy = 0x00000001, + regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_spu_set = 0x00000001, + regk_iop_sw_spu_wr = 0x00000003, + regk_iop_sw_spu_yes = 0x00000001 +}; +#endif /* __iop_sw_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h new file mode 100644 index 000000000000..c994114f3b51 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h @@ -0,0 +1,249 @@ +#ifndef __iop_timer_grp_defs_h +#define __iop_timer_grp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_timer_grp.r + * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r + * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_timer_grp */ + +/* Register rw_cfg, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int clk_src : 1; + unsigned int trig : 2; + unsigned int clk_gen_div : 8; + unsigned int clk_div : 8; + unsigned int dummy1 : 13; +} reg_iop_timer_grp_rw_cfg; +#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 +#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 + +/* Register rw_half_period, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int quota_lo : 15; + unsigned int quota_hi : 15; + unsigned int quota_hi_sel : 1; + unsigned int dummy1 : 1; +} reg_iop_timer_grp_rw_half_period; +#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 +#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 + +/* Register rw_half_period_len, scope iop_timer_grp, type rw */ +typedef unsigned int reg_iop_timer_grp_rw_half_period_len; +#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 +#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 + +#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 +/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int clk_src : 3; + unsigned int strb : 2; + unsigned int run_mode : 2; + unsigned int out_mode : 1; + unsigned int active_on_tmr : 2; + unsigned int inv : 1; + unsigned int en_by_tmr : 2; + unsigned int dis_by_tmr : 2; + unsigned int en_only_by_reg : 1; + unsigned int dis_only_by_reg : 1; + unsigned int rst_at_en_strb : 1; + unsigned int dummy1 : 14; +} reg_iop_timer_grp_rw_tmr_cfg; +#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 +#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 + +#define STRIDE_iop_timer_grp_rw_tmr_len 4 +/* Register rw_tmr_len, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rw_tmr_len; +#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 +#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 + +/* Register rw_cmd, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int rst : 4; + unsigned int en : 4; + unsigned int dis : 4; + unsigned int strb : 4; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rw_cmd; +#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 +#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 + +/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ +typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; +#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 + +#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 +/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rs_tmr_cnt; +#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 + +#define STRIDE_iop_timer_grp_r_tmr_cnt 8 +/* Register r_tmr_cnt, scope iop_timer_grp, type r */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_r_tmr_cnt; +#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 + +/* Register rw_intr_mask, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_rw_intr_mask; +#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 +#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 + +/* Register rw_ack_intr, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_rw_ack_intr; +#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 +#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 + +/* Register r_intr, scope iop_timer_grp, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_r_intr; +#define REG_RD_ADDR_iop_timer_grp_r_intr 108 + +/* Register r_masked_intr, scope iop_timer_grp, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_r_masked_intr; +#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 + + +/* Constants */ +enum { + regk_iop_timer_grp_clk200 = 0x00000000, + regk_iop_timer_grp_clk_gen = 0x00000002, + regk_iop_timer_grp_complete = 0x00000002, + regk_iop_timer_grp_div_clk200 = 0x00000001, + regk_iop_timer_grp_div_clk_gen = 0x00000003, + regk_iop_timer_grp_ext = 0x00000001, + regk_iop_timer_grp_hi = 0x00000000, + regk_iop_timer_grp_long_period = 0x00000001, + regk_iop_timer_grp_neg = 0x00000002, + regk_iop_timer_grp_no = 0x00000000, + regk_iop_timer_grp_once = 0x00000003, + regk_iop_timer_grp_pause = 0x00000001, + regk_iop_timer_grp_pos = 0x00000001, + regk_iop_timer_grp_pos_neg = 0x00000003, + regk_iop_timer_grp_pulse = 0x00000000, + regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, + regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, + regk_iop_timer_grp_rw_cfg_default = 0x00000002, + regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, + regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, + regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, + regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, + regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, + regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, + regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, + regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, + regk_iop_timer_grp_short_period = 0x00000000, + regk_iop_timer_grp_stop = 0x00000000, + regk_iop_timer_grp_tmr = 0x00000004, + regk_iop_timer_grp_toggle = 0x00000001, + regk_iop_timer_grp_yes = 0x00000001 +}; +#endif /* __iop_timer_grp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h new file mode 100644 index 000000000000..36e44282399d --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h @@ -0,0 +1,170 @@ +#ifndef __iop_trigger_grp_defs_h +#define __iop_trigger_grp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_trigger_grp */ + +#define STRIDE_iop_trigger_grp_rw_cfg 4 +/* Register rw_cfg, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int action : 2; + unsigned int once : 1; + unsigned int trig : 3; + unsigned int en_only_by_reg : 1; + unsigned int dis_only_by_reg : 1; + unsigned int dummy1 : 24; +} reg_iop_trigger_grp_rw_cfg; +#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 +#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 + +/* Register rw_cmd, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int dis : 4; + unsigned int en : 4; + unsigned int dummy1 : 24; +} reg_iop_trigger_grp_rw_cmd; +#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 +#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 + +/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_rw_intr_mask; +#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 +#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 + +/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_rw_ack_intr; +#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 +#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 + +/* Register r_intr, scope iop_trigger_grp, type r */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_r_intr; +#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 + +/* Register r_masked_intr, scope iop_trigger_grp, type r */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_r_masked_intr; +#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 + + +/* Constants */ +enum { + regk_iop_trigger_grp_fall = 0x00000002, + regk_iop_trigger_grp_fall_lo = 0x00000006, + regk_iop_trigger_grp_no = 0x00000000, + regk_iop_trigger_grp_off = 0x00000000, + regk_iop_trigger_grp_pulse = 0x00000000, + regk_iop_trigger_grp_rise = 0x00000001, + regk_iop_trigger_grp_rise_fall = 0x00000003, + regk_iop_trigger_grp_rise_fall_hi = 0x00000007, + regk_iop_trigger_grp_rise_fall_lo = 0x00000004, + regk_iop_trigger_grp_rise_hi = 0x00000005, + regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, + regk_iop_trigger_grp_rw_cfg_size = 0x00000004, + regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, + regk_iop_trigger_grp_toggle = 0x00000003, + regk_iop_trigger_grp_yes = 0x00000001 +}; +#endif /* __iop_trigger_grp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h new file mode 100644 index 000000000000..b8d6a910c71c --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h @@ -0,0 +1,99 @@ +#ifndef __iop_version_defs_h +#define __iop_version_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_version.r + * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp + * last modfied: Mon Apr 11 16:08:44 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r + * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_version */ + +/* Register r_version, scope iop_version, type r */ +typedef struct { + unsigned int nr : 8; + unsigned int dummy1 : 24; +} reg_iop_version_r_version; +#define REG_RD_ADDR_iop_version_r_version 0 + + +/* Constants */ +enum { + regk_iop_version_v1_0 = 0x00000001 +}; +#endif /* __iop_version_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h b/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h new file mode 100644 index 000000000000..7b167e3c0572 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h @@ -0,0 +1,104 @@ +#ifndef __irq_nmi_defs_h +#define __irq_nmi_defs_h + +/* + * This file is autogenerated from + * file: ../../mod/irq_nmi.r + * id: + * last modfied: Thu Jan 22 09:22:43 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r + * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope irq_nmi */ + +/* Register rw_cmd, scope irq_nmi, type rw */ +typedef struct { + unsigned int delay : 16; + unsigned int op : 2; + unsigned int dummy1 : 14; +} reg_irq_nmi_rw_cmd; +#define REG_RD_ADDR_irq_nmi_rw_cmd 0 +#define REG_WR_ADDR_irq_nmi_rw_cmd 0 + + +/* Constants */ +enum { + regk_irq_nmi_ack_irq = 0x00000002, + regk_irq_nmi_ack_nmi = 0x00000003, + regk_irq_nmi_irq = 0x00000000, + regk_irq_nmi_nmi = 0x00000001 +}; +#endif /* __irq_nmi_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h new file mode 100644 index 000000000000..a11fdd3cd907 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h @@ -0,0 +1,205 @@ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Fri Nov 7 15:36:04 2003 + * + * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_break_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_addr; +#define REG_RD_ADDR_marb_bp_r_break_addr 20 + +/* Register r_break_op, scope marb_bp, type r */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_break_op; +#define REG_RD_ADDR_marb_bp_r_break_op 24 + +/* Register r_break_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_clients; +#define REG_RD_ADDR_marb_bp_r_break_clients 28 + +/* Register r_break_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_first_client; +#define REG_RD_ADDR_marb_bp_r_break_first_client 32 + +/* Register r_break_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_size; +#define REG_RD_ADDR_marb_bp_r_break_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h new file mode 100644 index 000000000000..71e8af0bb3a4 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h @@ -0,0 +1,475 @@ +#ifndef __marb_defs_h +#define __marb_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb */ + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_int_slots; +#define REG_RD_ADDR_marb_rw_int_slots 0 +#define REG_WR_ADDR_marb_rw_int_slots 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_ext_slots; +#define REG_RD_ADDR_marb_rw_ext_slots 256 +#define REG_WR_ADDR_marb_rw_ext_slots 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_regs_slots; +#define REG_RD_ADDR_marb_rw_regs_slots 512 +#define REG_WR_ADDR_marb_rw_regs_slots 512 + +/* Register rw_intr_mask, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_intr_mask; +#define REG_RD_ADDR_marb_rw_intr_mask 528 +#define REG_WR_ADDR_marb_rw_intr_mask 528 + +/* Register rw_ack_intr, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_ack_intr; +#define REG_RD_ADDR_marb_rw_ack_intr 532 +#define REG_WR_ADDR_marb_rw_ack_intr 532 + +/* Register r_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_intr; +#define REG_RD_ADDR_marb_r_intr 536 + +/* Register r_masked_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_masked_intr; +#define REG_RD_ADDR_marb_r_masked_intr 540 + +/* Register rw_stop_mask, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_stop_mask; +#define REG_RD_ADDR_marb_rw_stop_mask 544 +#define REG_WR_ADDR_marb_rw_stop_mask 544 + +/* Register r_stopped, scope marb, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_r_stopped; +#define REG_RD_ADDR_marb_r_stopped 548 + +/* Register rw_no_snoop, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_no_snoop; +#define REG_RD_ADDR_marb_rw_no_snoop 832 +#define REG_WR_ADDR_marb_rw_no_snoop 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +typedef struct { + unsigned int dummy1 : 10; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 20; +} reg_marb_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 +#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 + + +/* Constants */ +enum { + regk_marb_cpud = 0x0000000b, + regk_marb_cpui = 0x0000000a, + regk_marb_dma0 = 0x00000000, + regk_marb_dma1 = 0x00000001, + regk_marb_dma2 = 0x00000002, + regk_marb_dma3 = 0x00000003, + regk_marb_dma4 = 0x00000004, + regk_marb_dma5 = 0x00000005, + regk_marb_dma6 = 0x00000006, + regk_marb_dma7 = 0x00000007, + regk_marb_dma8 = 0x00000008, + regk_marb_dma9 = 0x00000009, + regk_marb_iop = 0x0000000c, + regk_marb_no = 0x00000000, + regk_marb_r_stopped_default = 0x00000000, + regk_marb_rw_ext_slots_default = 0x00000000, + regk_marb_rw_ext_slots_size = 0x00000040, + regk_marb_rw_int_slots_default = 0x00000000, + regk_marb_rw_int_slots_size = 0x00000040, + regk_marb_rw_intr_mask_default = 0x00000000, + regk_marb_rw_no_snoop_default = 0x00000000, + regk_marb_rw_no_snoop_rq_default = 0x00000000, + regk_marb_rw_regs_slots_default = 0x00000000, + regk_marb_rw_regs_slots_size = 0x00000004, + regk_marb_rw_stop_mask_default = 0x00000000, + regk_marb_slave = 0x0000000d, + regk_marb_yes = 0x00000001 +}; +#endif /* __marb_defs_h */ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_brk_op; +#define REG_RD_ADDR_marb_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_size; +#define REG_RD_ADDR_marb_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h b/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h new file mode 100644 index 000000000000..236f91efe7e8 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h @@ -0,0 +1,17 @@ +/* + * Read/write register macros used by *_defs.h + */ + +#ifndef reg_rdwr_h +#define reg_rdwr_h + +#ifndef REG_READ +#define REG_READ(type, addr) (*((volatile type *) (addr))) +#endif + +#ifndef REG_WRITE +#define REG_WRITE(type, addr, val) \ + do { *((volatile type *) (addr)) = (val); } while(0) +#endif + +#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h b/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h new file mode 100644 index 000000000000..d9f0e924fb23 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h @@ -0,0 +1,173 @@ +#ifndef __rt_trace_defs_h +#define __rt_trace_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/rt_trace/rtl/rt_regs.r + * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp + * last modfied: Mon Apr 11 16:09:14 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r + * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope rt_trace */ + +/* Register rw_cfg, scope rt_trace, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int mode : 1; + unsigned int owner : 1; + unsigned int wp : 1; + unsigned int stall : 1; + unsigned int dummy1 : 3; + unsigned int wp_start : 7; + unsigned int dummy2 : 1; + unsigned int wp_stop : 7; + unsigned int dummy3 : 9; +} reg_rt_trace_rw_cfg; +#define REG_RD_ADDR_rt_trace_rw_cfg 0 +#define REG_WR_ADDR_rt_trace_rw_cfg 0 + +/* Register rw_tap_ctrl, scope rt_trace, type rw */ +typedef struct { + unsigned int ack_data : 1; + unsigned int ack_guru : 1; + unsigned int dummy1 : 30; +} reg_rt_trace_rw_tap_ctrl; +#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 +#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 + +/* Register r_tap_stat, scope rt_trace, type r */ +typedef struct { + unsigned int dav : 1; + unsigned int empty : 1; + unsigned int dummy1 : 30; +} reg_rt_trace_r_tap_stat; +#define REG_RD_ADDR_rt_trace_r_tap_stat 8 + +/* Register rw_tap_data, scope rt_trace, type rw */ +typedef unsigned int reg_rt_trace_rw_tap_data; +#define REG_RD_ADDR_rt_trace_rw_tap_data 12 +#define REG_WR_ADDR_rt_trace_rw_tap_data 12 + +/* Register rw_tap_hdata, scope rt_trace, type rw */ +typedef struct { + unsigned int op : 4; + unsigned int sub_op : 4; + unsigned int dummy1 : 24; +} reg_rt_trace_rw_tap_hdata; +#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 +#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 + +/* Register r_redir, scope rt_trace, type r */ +typedef unsigned int reg_rt_trace_r_redir; +#define REG_RD_ADDR_rt_trace_r_redir 20 + + +/* Constants */ +enum { + regk_rt_trace_brk = 0x0000000c, + regk_rt_trace_dbg = 0x00000003, + regk_rt_trace_dbgdi = 0x00000004, + regk_rt_trace_dbgdo = 0x00000005, + regk_rt_trace_gmode = 0x00000000, + regk_rt_trace_no = 0x00000000, + regk_rt_trace_nop = 0x00000000, + regk_rt_trace_normal = 0x00000000, + regk_rt_trace_rdmem = 0x00000007, + regk_rt_trace_rdmemb = 0x00000009, + regk_rt_trace_rdpreg = 0x00000002, + regk_rt_trace_rdreg = 0x00000001, + regk_rt_trace_rdsreg = 0x00000003, + regk_rt_trace_redir = 0x00000006, + regk_rt_trace_ret = 0x0000000b, + regk_rt_trace_rw_cfg_default = 0x00000000, + regk_rt_trace_trcfg = 0x00000001, + regk_rt_trace_wp = 0x00000001, + regk_rt_trace_wp0 = 0x00000001, + regk_rt_trace_wp1 = 0x00000002, + regk_rt_trace_wp2 = 0x00000004, + regk_rt_trace_wp3 = 0x00000008, + regk_rt_trace_wp4 = 0x00000010, + regk_rt_trace_wp5 = 0x00000020, + regk_rt_trace_wp6 = 0x00000040, + regk_rt_trace_wrmem = 0x00000008, + regk_rt_trace_wrmemb = 0x0000000a, + regk_rt_trace_wrpreg = 0x00000005, + regk_rt_trace_wrreg = 0x00000004, + regk_rt_trace_wrsreg = 0x00000006, + regk_rt_trace_yes = 0x00000001 +}; +#endif /* __rt_trace_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h new file mode 100644 index 000000000000..01c2fab97d43 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h @@ -0,0 +1,308 @@ +#ifndef __ser_defs_h +#define __ser_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ser/rtl/ser_regs.r + * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp + * last modfied: Mon Apr 11 16:09:21 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r + * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ser */ + +/* Register rw_tr_ctrl, scope ser, type rw */ +typedef struct { + unsigned int base_freq : 3; + unsigned int en : 1; + unsigned int par : 2; + unsigned int par_en : 1; + unsigned int data_bits : 1; + unsigned int stop_bits : 1; + unsigned int stop : 1; + unsigned int rts_delay : 3; + unsigned int rts_setup : 1; + unsigned int auto_rts : 1; + unsigned int txd : 1; + unsigned int auto_cts : 1; + unsigned int dummy1 : 15; +} reg_ser_rw_tr_ctrl; +#define REG_RD_ADDR_ser_rw_tr_ctrl 0 +#define REG_WR_ADDR_ser_rw_tr_ctrl 0 + +/* Register rw_tr_dma_en, scope ser, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_tr_dma_en; +#define REG_RD_ADDR_ser_rw_tr_dma_en 4 +#define REG_WR_ADDR_ser_rw_tr_dma_en 4 + +/* Register rw_rec_ctrl, scope ser, type rw */ +typedef struct { + unsigned int base_freq : 3; + unsigned int en : 1; + unsigned int par : 2; + unsigned int par_en : 1; + unsigned int data_bits : 1; + unsigned int dma_mode : 1; + unsigned int dma_err : 1; + unsigned int sampling : 1; + unsigned int timeout : 3; + unsigned int auto_eop : 1; + unsigned int half_duplex : 1; + unsigned int rts_n : 1; + unsigned int loopback : 1; + unsigned int dummy1 : 14; +} reg_ser_rw_rec_ctrl; +#define REG_RD_ADDR_ser_rw_rec_ctrl 8 +#define REG_WR_ADDR_ser_rw_rec_ctrl 8 + +/* Register rw_tr_baud_div, scope ser, type rw */ +typedef struct { + unsigned int div : 16; + unsigned int dummy1 : 16; +} reg_ser_rw_tr_baud_div; +#define REG_RD_ADDR_ser_rw_tr_baud_div 12 +#define REG_WR_ADDR_ser_rw_tr_baud_div 12 + +/* Register rw_rec_baud_div, scope ser, type rw */ +typedef struct { + unsigned int div : 16; + unsigned int dummy1 : 16; +} reg_ser_rw_rec_baud_div; +#define REG_RD_ADDR_ser_rw_rec_baud_div 16 +#define REG_WR_ADDR_ser_rw_rec_baud_div 16 + +/* Register rw_xoff, scope ser, type rw */ +typedef struct { + unsigned int chr : 8; + unsigned int automatic : 1; + unsigned int dummy1 : 23; +} reg_ser_rw_xoff; +#define REG_RD_ADDR_ser_rw_xoff 20 +#define REG_WR_ADDR_ser_rw_xoff 20 + +/* Register rw_xoff_clr, scope ser, type rw */ +typedef struct { + unsigned int clr : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_xoff_clr; +#define REG_RD_ADDR_ser_rw_xoff_clr 24 +#define REG_WR_ADDR_ser_rw_xoff_clr 24 + +/* Register rw_dout, scope ser, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_ser_rw_dout; +#define REG_RD_ADDR_ser_rw_dout 28 +#define REG_WR_ADDR_ser_rw_dout 28 + +/* Register rs_stat_din, scope ser, type rs */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 8; + unsigned int dav : 1; + unsigned int framing_err : 1; + unsigned int par_err : 1; + unsigned int orun : 1; + unsigned int rec_err : 1; + unsigned int rxd : 1; + unsigned int tr_idle : 1; + unsigned int tr_empty : 1; + unsigned int tr_rdy : 1; + unsigned int cts_n : 1; + unsigned int xoff_detect : 1; + unsigned int rts_n : 1; + unsigned int txd : 1; + unsigned int dummy2 : 3; +} reg_ser_rs_stat_din; +#define REG_RD_ADDR_ser_rs_stat_din 32 + +/* Register r_stat_din, scope ser, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 8; + unsigned int dav : 1; + unsigned int framing_err : 1; + unsigned int par_err : 1; + unsigned int orun : 1; + unsigned int rec_err : 1; + unsigned int rxd : 1; + unsigned int tr_idle : 1; + unsigned int tr_empty : 1; + unsigned int tr_rdy : 1; + unsigned int cts_n : 1; + unsigned int xoff_detect : 1; + unsigned int rts_n : 1; + unsigned int txd : 1; + unsigned int dummy2 : 3; +} reg_ser_r_stat_din; +#define REG_RD_ADDR_ser_r_stat_din 36 + +/* Register rw_rec_eop, scope ser, type rw */ +typedef struct { + unsigned int set : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_rec_eop; +#define REG_RD_ADDR_ser_rw_rec_eop 40 +#define REG_WR_ADDR_ser_rw_rec_eop 40 + +/* Register rw_intr_mask, scope ser, type rw */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_rw_intr_mask; +#define REG_RD_ADDR_ser_rw_intr_mask 44 +#define REG_WR_ADDR_ser_rw_intr_mask 44 + +/* Register rw_ack_intr, scope ser, type rw */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_rw_ack_intr; +#define REG_RD_ADDR_ser_rw_ack_intr 48 +#define REG_WR_ADDR_ser_rw_ack_intr 48 + +/* Register r_intr, scope ser, type r */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_r_intr; +#define REG_RD_ADDR_ser_r_intr 52 + +/* Register r_masked_intr, scope ser, type r */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_r_masked_intr; +#define REG_RD_ADDR_ser_r_masked_intr 56 + + +/* Constants */ +enum { + regk_ser_active = 0x00000000, + regk_ser_bits1 = 0x00000000, + regk_ser_bits2 = 0x00000001, + regk_ser_bits7 = 0x00000001, + regk_ser_bits8 = 0x00000000, + regk_ser_del0_5 = 0x00000000, + regk_ser_del1 = 0x00000001, + regk_ser_del1_5 = 0x00000002, + regk_ser_del2 = 0x00000003, + regk_ser_del2_5 = 0x00000004, + regk_ser_del3 = 0x00000005, + regk_ser_del3_5 = 0x00000006, + regk_ser_del4 = 0x00000007, + regk_ser_even = 0x00000000, + regk_ser_ext = 0x00000001, + regk_ser_f100 = 0x00000007, + regk_ser_f29_493 = 0x00000004, + regk_ser_f32 = 0x00000005, + regk_ser_f32_768 = 0x00000006, + regk_ser_ignore = 0x00000001, + regk_ser_inactive = 0x00000001, + regk_ser_majority = 0x00000001, + regk_ser_mark = 0x00000002, + regk_ser_middle = 0x00000000, + regk_ser_no = 0x00000000, + regk_ser_odd = 0x00000001, + regk_ser_off = 0x00000000, + regk_ser_rw_intr_mask_default = 0x00000000, + regk_ser_rw_rec_baud_div_default = 0x00000000, + regk_ser_rw_rec_ctrl_default = 0x00010000, + regk_ser_rw_tr_baud_div_default = 0x00000000, + regk_ser_rw_tr_ctrl_default = 0x00008000, + regk_ser_rw_tr_dma_en_default = 0x00000000, + regk_ser_rw_xoff_default = 0x00000000, + regk_ser_space = 0x00000003, + regk_ser_stop = 0x00000000, + regk_ser_yes = 0x00000001 +}; +#endif /* __ser_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h new file mode 100644 index 000000000000..8d1dab218b91 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h @@ -0,0 +1,331 @@ +#ifndef __sser_defs_h +#define __sser_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/syncser/rtl/sser_regs.r + * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp + * last modfied: Mon Apr 11 16:09:48 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r + * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope sser */ + +/* Register rw_cfg, scope sser, type rw */ +typedef struct { + unsigned int clk_div : 16; + unsigned int base_freq : 3; + unsigned int gate_clk : 1; + unsigned int clkgate_ctrl : 1; + unsigned int clkgate_in : 1; + unsigned int clk_dir : 1; + unsigned int clk_od_mode : 1; + unsigned int out_clk_pol : 1; + unsigned int out_clk_src : 2; + unsigned int clk_in_sel : 1; + unsigned int hold_pol : 1; + unsigned int prepare : 1; + unsigned int en : 1; + unsigned int dummy1 : 1; +} reg_sser_rw_cfg; +#define REG_RD_ADDR_sser_rw_cfg 0 +#define REG_WR_ADDR_sser_rw_cfg 0 + +/* Register rw_frm_cfg, scope sser, type rw */ +typedef struct { + unsigned int wordrate : 10; + unsigned int rec_delay : 3; + unsigned int tr_delay : 3; + unsigned int early_wend : 1; + unsigned int level : 2; + unsigned int type : 1; + unsigned int clk_pol : 1; + unsigned int fr_in_rxclk : 1; + unsigned int clk_src : 1; + unsigned int out_off : 1; + unsigned int out_on : 1; + unsigned int frame_pin_dir : 1; + unsigned int frame_pin_use : 2; + unsigned int status_pin_dir : 1; + unsigned int status_pin_use : 2; + unsigned int dummy1 : 1; +} reg_sser_rw_frm_cfg; +#define REG_RD_ADDR_sser_rw_frm_cfg 4 +#define REG_WR_ADDR_sser_rw_frm_cfg 4 + +/* Register rw_tr_cfg, scope sser, type rw */ +typedef struct { + unsigned int tr_en : 1; + unsigned int stop : 1; + unsigned int urun_stop : 1; + unsigned int eop_stop : 1; + unsigned int sample_size : 6; + unsigned int sh_dir : 1; + unsigned int clk_pol : 1; + unsigned int clk_src : 1; + unsigned int use_dma : 1; + unsigned int mode : 2; + unsigned int frm_src : 1; + unsigned int use60958 : 1; + unsigned int iec60958_ckdiv : 2; + unsigned int rate_ctrl : 1; + unsigned int use_md : 1; + unsigned int dual_i2s : 1; + unsigned int data_pin_use : 2; + unsigned int od_mode : 1; + unsigned int bulk_wspace : 2; + unsigned int dummy1 : 4; +} reg_sser_rw_tr_cfg; +#define REG_RD_ADDR_sser_rw_tr_cfg 8 +#define REG_WR_ADDR_sser_rw_tr_cfg 8 + +/* Register rw_rec_cfg, scope sser, type rw */ +typedef struct { + unsigned int rec_en : 1; + unsigned int force_eop : 1; + unsigned int stop : 1; + unsigned int orun_stop : 1; + unsigned int eop_stop : 1; + unsigned int sample_size : 6; + unsigned int sh_dir : 1; + unsigned int clk_pol : 1; + unsigned int clk_src : 1; + unsigned int use_dma : 1; + unsigned int mode : 2; + unsigned int frm_src : 2; + unsigned int use60958 : 1; + unsigned int iec60958_ui_len : 5; + unsigned int slave2_en : 1; + unsigned int slave3_en : 1; + unsigned int fifo_thr : 2; + unsigned int dummy1 : 3; +} reg_sser_rw_rec_cfg; +#define REG_RD_ADDR_sser_rw_rec_cfg 12 +#define REG_WR_ADDR_sser_rw_rec_cfg 12 + +/* Register rw_tr_data, scope sser, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int md : 1; + unsigned int dummy1 : 15; +} reg_sser_rw_tr_data; +#define REG_RD_ADDR_sser_rw_tr_data 16 +#define REG_WR_ADDR_sser_rw_tr_data 16 + +/* Register r_rec_data, scope sser, type r */ +typedef struct { + unsigned int data : 16; + unsigned int md : 1; + unsigned int ext_clk : 1; + unsigned int status_in : 1; + unsigned int frame_in : 1; + unsigned int din : 1; + unsigned int data_in : 1; + unsigned int clk_in : 1; + unsigned int dummy1 : 9; +} reg_sser_r_rec_data; +#define REG_RD_ADDR_sser_r_rec_data 20 + +/* Register rw_extra, scope sser, type rw */ +typedef struct { + unsigned int clkoff_cycles : 20; + unsigned int clkoff_en : 1; + unsigned int clkon_en : 1; + unsigned int dout_delay : 5; + unsigned int dummy1 : 5; +} reg_sser_rw_extra; +#define REG_RD_ADDR_sser_rw_extra 24 +#define REG_WR_ADDR_sser_rw_extra 24 + +/* Register rw_intr_mask, scope sser, type rw */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_rw_intr_mask; +#define REG_RD_ADDR_sser_rw_intr_mask 28 +#define REG_WR_ADDR_sser_rw_intr_mask 28 + +/* Register rw_ack_intr, scope sser, type rw */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_rw_ack_intr; +#define REG_RD_ADDR_sser_rw_ack_intr 32 +#define REG_WR_ADDR_sser_rw_ack_intr 32 + +/* Register r_intr, scope sser, type r */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_r_intr; +#define REG_RD_ADDR_sser_r_intr 36 + +/* Register r_masked_intr, scope sser, type r */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_r_masked_intr; +#define REG_RD_ADDR_sser_r_masked_intr 40 + + +/* Constants */ +enum { + regk_sser_both = 0x00000002, + regk_sser_bulk = 0x00000001, + regk_sser_clk100 = 0x00000000, + regk_sser_clk_in = 0x00000000, + regk_sser_const0 = 0x00000003, + regk_sser_dout = 0x00000002, + regk_sser_edge = 0x00000000, + regk_sser_ext = 0x00000001, + regk_sser_ext_clk = 0x00000001, + regk_sser_f100 = 0x00000000, + regk_sser_f29_493 = 0x00000004, + regk_sser_f32 = 0x00000005, + regk_sser_f32_768 = 0x00000006, + regk_sser_frm = 0x00000003, + regk_sser_gio0 = 0x00000000, + regk_sser_gio1 = 0x00000001, + regk_sser_hispeed = 0x00000001, + regk_sser_hold = 0x00000002, + regk_sser_in = 0x00000000, + regk_sser_inf = 0x00000003, + regk_sser_intern = 0x00000000, + regk_sser_intern_clk = 0x00000001, + regk_sser_intern_tb = 0x00000000, + regk_sser_iso = 0x00000000, + regk_sser_level = 0x00000001, + regk_sser_lospeed = 0x00000000, + regk_sser_lsbfirst = 0x00000000, + regk_sser_msbfirst = 0x00000001, + regk_sser_neg = 0x00000001, + regk_sser_neg_lo = 0x00000000, + regk_sser_no = 0x00000000, + regk_sser_no_clk = 0x00000007, + regk_sser_nojitter = 0x00000002, + regk_sser_out = 0x00000001, + regk_sser_pos = 0x00000000, + regk_sser_pos_hi = 0x00000001, + regk_sser_rec = 0x00000000, + regk_sser_rw_cfg_default = 0x00000000, + regk_sser_rw_extra_default = 0x00000000, + regk_sser_rw_frm_cfg_default = 0x00000000, + regk_sser_rw_intr_mask_default = 0x00000000, + regk_sser_rw_rec_cfg_default = 0x00000000, + regk_sser_rw_tr_cfg_default = 0x01800000, + regk_sser_rw_tr_data_default = 0x00000000, + regk_sser_thr16 = 0x00000001, + regk_sser_thr32 = 0x00000002, + regk_sser_thr8 = 0x00000000, + regk_sser_tr = 0x00000001, + regk_sser_ts_out = 0x00000003, + regk_sser_tx_bulk = 0x00000002, + regk_sser_wiresave = 0x00000002, + regk_sser_yes = 0x00000001 +}; +#endif /* __sser_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop.h b/arch/cris/include/arch-v32/arch/hwregs/strcop.h new file mode 100644 index 000000000000..35131ba466f3 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/strcop.h @@ -0,0 +1,57 @@ +// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ + +// Streamcop meta-data configuration structs + +struct strcop_meta_out { + unsigned char csumsel : 3; + unsigned char ciphsel : 3; + unsigned char ciphconf : 2; + unsigned char hashsel : 3; + unsigned char hashconf : 1; + unsigned char hashmode : 1; + unsigned char decrypt : 1; + unsigned char dlkey : 1; + unsigned char cbcmode : 1; +}; + +struct strcop_meta_in { + unsigned char dmasel : 3; + unsigned char sync : 1; + unsigned char res1 : 5; + unsigned char res2; +}; + +// Source definitions + +enum { + src_none = 0, + src_dma = 1, + src_des = 2, + src_sha1 = 3, + src_csum = 4, + src_aes = 5, + src_md5 = 6, + src_res = 7 +}; + +// Cipher definitions + +enum { + ciph_des = 0, + ciph_3des = 1, + ciph_aes = 2 +}; + +// Hash definitions + +enum { + hash_sha1 = 0, + hash_md5 = 1 +}; + +enum { + hash_noiv = 0, + hash_iv = 1 +}; + + diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h b/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h new file mode 100644 index 000000000000..bd145a49b2c4 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h @@ -0,0 +1,109 @@ +#ifndef __strcop_defs_h +#define __strcop_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strcop/rtl/strcop_regs.r + * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp + * last modfied: Mon Apr 11 16:09:38 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r + * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strcop */ + +/* Register rw_cfg, scope strcop, type rw */ +typedef struct { + unsigned int td3 : 1; + unsigned int td2 : 1; + unsigned int td1 : 1; + unsigned int ipend : 1; + unsigned int ignore_sync : 1; + unsigned int en : 1; + unsigned int dummy1 : 26; +} reg_strcop_rw_cfg; +#define REG_RD_ADDR_strcop_rw_cfg 0 +#define REG_WR_ADDR_strcop_rw_cfg 0 + + +/* Constants */ +enum { + regk_strcop_big = 0x00000001, + regk_strcop_d = 0x00000001, + regk_strcop_e = 0x00000000, + regk_strcop_little = 0x00000000, + regk_strcop_rw_cfg_default = 0x00000002 +}; +#endif /* __strcop_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h new file mode 100644 index 000000000000..ffe49625ae36 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h @@ -0,0 +1,78 @@ +#ifndef __SUPP_REG_H__ +#define __SUPP_REG_H__ + +/* Macros for reading and writing support/special registers. */ + +#ifndef STRINGIFYFY +#define STRINGIFYFY(i) #i +#endif + +#ifndef STRINGIFY +#define STRINGIFY(i) STRINGIFYFY(i) +#endif + +#define SPEC_REG_BZ "BZ" +#define SPEC_REG_VR "VR" +#define SPEC_REG_PID "PID" +#define SPEC_REG_SRS "SRS" +#define SPEC_REG_WZ "WZ" +#define SPEC_REG_EXS "EXS" +#define SPEC_REG_EDA "EDA" +#define SPEC_REG_MOF "MOF" +#define SPEC_REG_DZ "DZ" +#define SPEC_REG_EBP "EBP" +#define SPEC_REG_ERP "ERP" +#define SPEC_REG_SRP "SRP" +#define SPEC_REG_NRP "NRP" +#define SPEC_REG_CCS "CCS" +#define SPEC_REG_USP "USP" +#define SPEC_REG_SPC "SPC" + +#define RW_MM_CFG 0 +#define RW_MM_KBASE_LO 1 +#define RW_MM_KBASE_HI 2 +#define RW_MM_CAUSE 3 +#define RW_MM_TLB_SEL 4 +#define RW_MM_TLB_LO 5 +#define RW_MM_TLB_HI 6 +#define RW_MM_TLB_PGD 7 + +#define BANK_GC 0 +#define BANK_IM 1 +#define BANK_DM 2 +#define BANK_BP 3 + +#define RW_GC_CFG 0 +#define RW_GC_CCS 1 +#define RW_GC_SRS 2 +#define RW_GC_NRP 3 +#define RW_GC_EXS 4 +#define RW_GC_R0 8 +#define RW_GC_R1 9 + +#define SPEC_REG_WR(r,v) \ +__asm__ __volatile__ ("move %0, $" r : : "r" (v)); + +#define SPEC_REG_RD(r,v) \ +__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); + +#define NOP() \ + __asm__ __volatile__ ("nop"); + +#define SUPP_BANK_SEL(b) \ + SPEC_REG_WR(SPEC_REG_SRS,b); \ + NOP(); \ + NOP(); \ + NOP(); + +#define SUPP_REG_WR(r,v) \ +__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + : : "r" (v)); + +#define SUPP_REG_RD(r,v) \ +__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); + +#endif /* __SUPP_REG_H__ */ diff --git a/arch/cris/include/arch-v32/arch/intmem.h b/arch/cris/include/arch-v32/arch/intmem.h new file mode 100644 index 000000000000..c0ada33bf90f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/intmem.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_INTMEM_H +#define _ASM_CRIS_INTMEM_H + +void* crisv32_intmem_alloc(unsigned size, unsigned align); +void crisv32_intmem_free(void* addr); +void* crisv32_intmem_phys_to_virt(unsigned long addr); +unsigned long crisv32_intmem_virt_to_phys(void *addr); + +#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/arch/cris/include/arch-v32/arch/io.h b/arch/cris/include/arch-v32/arch/io.h new file mode 100644 index 000000000000..72024452cea9 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/io.h @@ -0,0 +1,136 @@ +#ifndef _ASM_ARCH_CRIS_IO_H +#define _ASM_ARCH_CRIS_IO_H + +#include +#include +#include +#include + +enum crisv32_io_dir +{ + crisv32_io_dir_in = 0, + crisv32_io_dir_out = 1 +}; + +struct crisv32_ioport +{ + volatile unsigned long *oe; + volatile unsigned long *data; + volatile unsigned long *data_in; + unsigned int pin_count; + spinlock_t lock; +}; + +struct crisv32_iopin +{ + struct crisv32_ioport* port; + int bit; +}; + +extern struct crisv32_ioport crisv32_ioports[]; + +extern struct crisv32_iopin crisv32_led1_green; +extern struct crisv32_iopin crisv32_led1_red; +extern struct crisv32_iopin crisv32_led2_green; +extern struct crisv32_iopin crisv32_led2_red; +extern struct crisv32_iopin crisv32_led3_green; +extern struct crisv32_iopin crisv32_led3_red; + +extern struct crisv32_iopin crisv32_led_net0_green; +extern struct crisv32_iopin crisv32_led_net0_red; +extern struct crisv32_iopin crisv32_led_net1_green; +extern struct crisv32_iopin crisv32_led_net1_red; + +static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) +{ + unsigned long flags; + spin_lock_irqsave(&iopin->port->lock, flags); + + if (val) + *iopin->port->data |= iopin->bit; + else + *iopin->port->data &= ~iopin->bit; + + spin_unlock_irqrestore(&iopin->port->lock, flags); +} + +static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, + enum crisv32_io_dir dir) +{ + unsigned long flags; + spin_lock_irqsave(&iopin->port->lock, flags); + + if (dir == crisv32_io_dir_in) + *iopin->port->oe &= ~iopin->bit; + else + *iopin->port->oe |= iopin->bit; + + spin_unlock_irqrestore(&iopin->port->lock, flags); +} + +static inline int crisv32_io_rd(struct crisv32_iopin* iopin) +{ + return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); +} + +int crisv32_io_get(struct crisv32_iopin* iopin, + unsigned int port, unsigned int pin); +int crisv32_io_get_name(struct crisv32_iopin* iopin, + const char *name); + +#define CRIS_LED_OFF 0x00 +#define CRIS_LED_GREEN 0x01 +#define CRIS_LED_RED 0x02 +#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) + +#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) +#define CRIS_LED_NETWORK_GRP0_SET(x) \ + do { \ + CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#else +#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} +#endif + +#define CRIS_LED_NETWORK_GRP0_SET_G(x) \ + crisv32_io_set(&crisv32_led_net0_green, !(x)); + +#define CRIS_LED_NETWORK_GRP0_SET_R(x) \ + crisv32_io_set(&crisv32_led_net0_red, !(x)); + +#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) +#define CRIS_LED_NETWORK_GRP1_SET(x) \ + do { \ + CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#else +#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} +#endif + +#define CRIS_LED_NETWORK_GRP1_SET_G(x) \ + crisv32_io_set(&crisv32_led_net1_green, !(x)); + +#define CRIS_LED_NETWORK_GRP1_SET_R(x) \ + crisv32_io_set(&crisv32_led_net1_red, !(x)); + +#define CRIS_LED_ACTIVE_SET(x) \ + do { \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ + } while (0) + +#define CRIS_LED_ACTIVE_SET_G(x) \ + crisv32_io_set(&crisv32_led2_green, !(x)); +#define CRIS_LED_ACTIVE_SET_R(x) \ + crisv32_io_set(&crisv32_led2_red, !(x)); +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + crisv32_io_set(&crisv32_led3_green, !(x)); \ + crisv32_io_set(&crisv32_led3_red, !(x)); \ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + crisv32_io_set(&crisv32_led3_green, !(x)); + +#endif diff --git a/arch/cris/include/arch-v32/arch/irq.h b/arch/cris/include/arch-v32/arch/irq.h new file mode 100644 index 000000000000..9e4c9fbdfddf --- /dev/null +++ b/arch/cris/include/arch-v32/arch/irq.h @@ -0,0 +1,124 @@ +#ifndef _ASM_ARCH_IRQ_H +#define _ASM_ARCH_IRQ_H + +#include + +/* Number of non-cpu interrupts. */ +#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ +#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ +#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ +#if NR_REAL_IRQS > 32 +#define MACH_IRQS 64 +#else +#define MACH_IRQS 32 +#endif + +#ifndef __ASSEMBLY__ +/* Global IRQ vector. */ +typedef void (*irqvectptr)(void); + +struct etrax_interrupt_vector { + irqvectptr v[256]; +}; + +extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ + +void mask_irq(int irq); +void unmask_irq(int irq); + +void set_exception_vector(int n, irqvectptr addr); + +/* Save registers so that they match pt_regs. */ +#define SAVE_ALL \ + "subq 12,$sp\n\t" \ + "move $erp,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $srp,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $ccs,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $spc,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $mof,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $srs,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move.d $acr,[$sp]\n\t" \ + "subq 14*4,$sp\n\t" \ + "movem $r13,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move.d $r10,[$sp]\n" + +#define STR2(x) #x +#define STR(x) STR2(x) + +#define IRQ_NAME2(nr) nr##_interrupt(void) +#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) + +/* + * The reason for setting the S-bit when debugging the kernel is that we want + * hardware breakpoints to remain active while we are in an exception handler. + * Note that we cannot simply copy S1, since we may come here from user-space, + * or any context where the S-bit wasn't set. + */ +#ifdef CONFIG_ETRAX_KGDB +#define KGDB_FIXUP \ + "move $ccs, $r10\n\t" \ + "or.d (1<<9), $r10\n\t" \ + "move $r10, $ccs\n\t" +#else +#define KGDB_FIXUP "" +#endif + +/* + * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock + * and jump to ret_from_intr which is found in entry.S. + * + * The reason for blocking the IRQ is to allow an sti() before the handler, + * which will acknowledge the interrupt, is run. The actual blocking is made + * by crisv32_do_IRQ. + */ +#define BUILD_IRQ(nr) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + KGDB_FIXUP \ + "move.d "#nr",$r10\n\t" \ + "move.d $sp, $r12\n\t" \ + "jsr crisv32_do_IRQ\n\t" \ + "moveq 1, $r11\n\t" \ + "jump ret_from_intr\n\t" \ + "nop\n\t"); +/* + * This is subtle. The timer interrupt is crucial and it should not be disabled + * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it + * would have been BLOCK'ed, and then softirq's are run before we return here to + * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run + * and the watchdog will kill us. + * + * Furthermore, if a lot of other irq's occur before we return here, the + * multiple_irq handler is run and it prioritizes the timer interrupt. However + * if we had BLOCK'edit here, we would not get the multiple_irq at all. + * + * The non-blocking here is based on the knowledge that the timer interrupt is + * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not + * be an sti() before the timer irq handler is run to acknowledge the interrupt. + */ +#define BUILD_TIMER_IRQ(nr, mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + KGDB_FIXUP \ + "move.d "#nr",$r10\n\t" \ + "move.d $sp,$r12\n\t" \ + "jsr crisv32_do_IRQ\n\t" \ + "moveq 0,$r11\n\t" \ + "jump ret_from_intr\n\t" \ + "nop\n\t"); + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_ARCH_IRQ_H */ diff --git a/arch/cris/include/arch-v32/arch/memmap.h b/arch/cris/include/arch-v32/arch/memmap.h new file mode 100644 index 000000000000..d29df5644d3e --- /dev/null +++ b/arch/cris/include/arch-v32/arch/memmap.h @@ -0,0 +1,24 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_INTMEM_START (0x38000000) +#define MEM_INTMEM_SIZE (0x00020000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/arch/cris/include/arch-v32/arch/mmu.h b/arch/cris/include/arch-v32/arch/mmu.h new file mode 100644 index 000000000000..6bcdc3fdf7dc --- /dev/null +++ b/arch/cris/include/arch-v32/arch/mmu.h @@ -0,0 +1,111 @@ +#ifndef _ASM_CRIS_ARCH_MMU_H +#define _ASM_CRIS_ARCH_MMU_H + +/* MMU context type. */ +typedef struct +{ + unsigned int page_id; +} mm_context_t; + +/* Kernel memory segments. */ +#define KSEG_F 0xf0000000UL +#define KSEG_E 0xe0000000UL +#define KSEG_D 0xd0000000UL +#define KSEG_C 0xc0000000UL +#define KSEG_B 0xb0000000UL +#define KSEG_A 0xa0000000UL +#define KSEG_9 0x90000000UL +#define KSEG_8 0x80000000UL +#define KSEG_7 0x70000000UL +#define KSEG_6 0x60000000UL +#define KSEG_5 0x50000000UL +#define KSEG_4 0x40000000UL +#define KSEG_3 0x30000000UL +#define KSEG_2 0x20000000UL +#define KSEG_1 0x10000000UL +#define KSEG_0 0x00000000UL + +/* + * CRISv32 PTE bits: + * + * Bit: 31-13 12-5 4 3 2 1 0 + * +-----+------+--------+-------+--------+-------+---------+ + * | pfn | zero | global | valid | kernel | write | execute | + * +-----+------+--------+-------+--------+-------+---------+ + */ + +/* + * Defines for accessing the bits. Also define some synonyms for use with + * the software-based defined bits below. + */ +#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ +#define _PAGE_WE (1 << 1) /* Write bit. */ +#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ +#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ +#define _PAGE_VALID (1 << 3) /* Page is valid. */ +#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ +#define _PAGE_GLOBAL (1 << 4) /* Global page. */ + +/* + * The hardware doesn't care about these bits, but the kernel uses them in + * software. + */ +#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ +#define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */ +#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ +#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ +#define _PAGE_READ (1 << 8) /* Read enabled. */ +#define _PAGE_WRITE (1 << 9) /* Write enabled. */ + +/* Define some higher level generic page attributes. */ +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) + +#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED) +#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED | _PAGE_EXECUTE) + +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) + +#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) +#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ + _PAGE_PRESENT | __READABLE) + +#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) + +/* CRISv32 can do page protection for execute. + * Write permissions imply read permissions. + * Note that the numbers are in Execute-Write-Read order! + */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY_EXEC +#define __P101 PAGE_READONLY_EXEC +#define __P110 PAGE_COPY_EXEC +#define __P111 PAGE_COPY_EXEC + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY_EXEC +#define __S101 PAGE_READONLY_EXEC +#define __S110 PAGE_SHARED_EXEC +#define __S111 PAGE_SHARED_EXEC + +#define PTE_FILE_MAX_BITS 25 + +#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/arch/cris/include/arch-v32/arch/offset.h b/arch/cris/include/arch-v32/arch/offset.h new file mode 100644 index 000000000000..4442c4bd52f4 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/offset.h @@ -0,0 +1,35 @@ +#ifndef __ASM_OFFSETS_H__ +#define __ASM_OFFSETS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by arch/cris/Makefile + * + */ + +#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ +#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ +#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ +#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ +#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ +#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ +#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ +#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ +#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ +#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ +#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ + +#define TI_task 0 /* offsetof(struct thread_info, task) */ +#define TI_flags 8 /* offsetof(struct thread_info, flags) */ +#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ + +#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ +#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ +#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ + +#define TASK_pid 151 /* offsetof(struct task_struct, pid) */ + +#define LCLONE_VM 256 /* CLONE_VM */ +#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ + +#endif diff --git a/arch/cris/include/arch-v32/arch/page.h b/arch/cris/include/arch-v32/arch/page.h new file mode 100644 index 000000000000..20f1b4806bfe --- /dev/null +++ b/arch/cris/include/arch-v32/arch/page.h @@ -0,0 +1,27 @@ +#ifndef _ASM_CRIS_ARCH_PAGE_H +#define _ASM_CRIS_ARCH_PAGE_H + + +#ifdef __KERNEL__ + +#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ + +/* + * Macros to convert between physical and virtual addresses. By stripping a + * selected bit it's possible to convert between KSEG_x and 0x40000000 where the + * DRAM really resides. DRAM is virtually at 0xc. + */ +#ifndef CONFIG_ETRAX_VCS_SIM +#define __pa(x) ((unsigned long)(x) & 0x7fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) +#else +#define __pa(x) ((unsigned long)(x) & 0x3fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000)) +#endif + +#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ + VM_MAYREAD | VM_MAYWRITE) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/arch/cris/include/arch-v32/arch/pgtable.h b/arch/cris/include/arch-v32/arch/pgtable.h new file mode 100644 index 000000000000..08cb7ff7e4e7 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/pgtable.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_ARCH_PGTABLE_H +#define _ASM_CRIS_ARCH_PGTABLE_H + +/* Define the kernels virtual memory area. */ +#define VMALLOC_START KSEG_D +#define VMALLOC_END KSEG_E +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) + +#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/arch/cris/include/arch-v32/arch/processor.h b/arch/cris/include/arch-v32/arch/processor.h new file mode 100644 index 000000000000..f80b47790ca6 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/processor.h @@ -0,0 +1,59 @@ +#ifndef _ASM_CRIS_ARCH_PROCESSOR_H +#define _ASM_CRIS_ARCH_PROCESSOR_H + + +/* Return current instruction pointer. */ +#define current_text_addr() \ + ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) + +/* + * Since CRIS doesn't do hardware task-switching this hasn't really anything to + * do with the proccessor itself, it's just here for legacy reasons. This is + * used when task-switching using _resume defined in entry.S. The offsets here + * are hardcoded into _resume, so if this struct is changed, entry.S needs to be + * changed as well. + */ +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer. */ + unsigned long usp; /* User stack pointer. */ + unsigned long ccs; /* Saved flags register. */ +}; + +/* + * User-space process size. This is hardcoded into a few places, so don't + * changed it unless everything's clear! + */ +#ifndef CONFIG_ETRAX_VCS_SIM +#define TASK_SIZE (0xB0000000UL) +#else +#define TASK_SIZE (0xA0000000UL) +#endif + +/* CCS I=1, enable interrupts. */ +#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) } + +#define KSTK_EIP(tsk) \ +({ \ + unsigned long eip = 0; \ + unsigned long regs = (unsigned long)task_pt_regs(tsk); \ + if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ + eip = ((struct pt_regs *)regs)->erp; \ + eip; \ +}) + +/* + * Give the thread a program location, set user-mode and switch user + * stackpointer. + */ +#define start_thread(regs, ip, usp) \ +do { \ + set_fs(USER_DS); \ + regs->erp = ip; \ + regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ + wrusp(usp); \ +} while(0) + +/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ +#define arch_fixup(regs) {}; + +#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/arch/cris/include/arch-v32/arch/ptrace.h b/arch/cris/include/arch-v32/arch/ptrace.h new file mode 100644 index 000000000000..41f4e8662bc2 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/ptrace.h @@ -0,0 +1,118 @@ +#ifndef _CRIS_ARCH_PTRACE_H +#define _CRIS_ARCH_PTRACE_H + +/* Register numbers in the ptrace system call interface */ + +#define PT_ORIG_R10 0 +#define PT_R0 1 +#define PT_R1 2 +#define PT_R2 3 +#define PT_R3 4 +#define PT_R4 5 +#define PT_R5 6 +#define PT_R6 7 +#define PT_R7 8 +#define PT_R8 9 +#define PT_R9 10 +#define PT_R10 11 +#define PT_R11 12 +#define PT_R12 13 +#define PT_R13 14 +#define PT_ACR 15 +#define PT_SRS 16 +#define PT_MOF 17 +#define PT_SPC 18 +#define PT_CCS 19 +#define PT_SRP 20 +#define PT_ERP 21 /* This is actually the debugged process' PC */ +#define PT_EXS 22 +#define PT_EDA 23 +#define PT_USP 24 /* special case - USP is not in the pt_regs */ +#define PT_PPC 25 /* special case - pseudo PC */ +#define PT_BP 26 /* Base number for BP registers. */ +#define PT_BP_CTRL 26 /* BP control register. */ +#define PT_MAX 40 + +/* Condition code bit numbers. */ +#define C_CCS_BITNR 0 +#define V_CCS_BITNR 1 +#define Z_CCS_BITNR 2 +#define N_CCS_BITNR 3 +#define X_CCS_BITNR 4 +#define I_CCS_BITNR 5 +#define U_CCS_BITNR 6 +#define P_CCS_BITNR 7 +#define R_CCS_BITNR 8 +#define S_CCS_BITNR 9 +#define M_CCS_BITNR 30 +#define Q_CCS_BITNR 31 +#define CCS_SHIFT 10 /* Shift count for each level in CCS */ + +/* pt_regs not only specifices the format in the user-struct during + * ptrace but is also the frame format used in the kernel prologue/epilogues + * themselves + */ + +struct pt_regs { + unsigned long orig_r10; + /* pushed by movem r13, [sp] in SAVE_ALL. */ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long acr; + unsigned long srs; + unsigned long mof; + unsigned long spc; + unsigned long ccs; + unsigned long srp; + unsigned long erp; /* This is actually the debugged process' PC */ + /* For debugging purposes; saved only when needed. */ + unsigned long exs; + unsigned long eda; +}; + +/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) + * when doing a context-switch. it is used (apart from in resume) when a new + * thread is made and we need to make _resume (which is starting it for the + * first time) realise what is going on. + * + * Actually, the use is very close to the thread struct (TSS) in that both the + * switch_stack and the TSS are used to keep thread stuff when switching in + * _resume. + */ + +struct switch_stack { + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long return_ip; /* ip that _resume will return to */ +}; + +#ifdef __KERNEL__ + +#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) +#define instruction_pointer(regs) ((regs)->erp) +extern void show_regs(struct pt_regs *); +#define profile_pc(regs) instruction_pointer(regs) + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/cris/include/arch-v32/arch/spinlock.h b/arch/cris/include/arch-v32/arch/spinlock.h new file mode 100644 index 000000000000..0d5709b983a1 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/spinlock.h @@ -0,0 +1,129 @@ +#ifndef __ASM_ARCH_SPINLOCK_H +#define __ASM_ARCH_SPINLOCK_H + +#include + +#define RW_LOCK_BIAS 0x01000000 + +extern void cris_spin_unlock(void *l, int val); +extern void cris_spin_lock(void *l); +extern int cris_spin_trylock(void *l); + +static inline int __raw_spin_is_locked(raw_spinlock_t *x) +{ + return *(volatile signed char *)(&(x)->slock) <= 0; +} + +static inline void __raw_spin_unlock(raw_spinlock_t *lock) +{ + __asm__ volatile ("move.d %1,%0" \ + : "=m" (lock->slock) \ + : "r" (1) \ + : "memory"); +} + +static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) +{ + while (__raw_spin_is_locked(lock)) + cpu_relax(); +} + +static inline int __raw_spin_trylock(raw_spinlock_t *lock) +{ + return cris_spin_trylock((void *)&lock->slock); +} + +static inline void __raw_spin_lock(raw_spinlock_t *lock) +{ + cris_spin_lock((void *)&lock->slock); +} + +static inline void +__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) +{ + __raw_spin_lock(lock); +} + +/* + * Read-write spinlocks, allowing multiple readers + * but only one writer. + * + * NOTE! it is quite common to have readers in interrupts + * but no interrupt writers. For those circumstances we + * can "mix" irq-safe locks - any writer needs to get a + * irq-safe write-lock, but readers can get non-irqsafe + * read-locks. + * + */ + +static inline int __raw_read_can_lock(raw_rwlock_t *x) +{ + return (int)(x)->lock > 0; +} + +static inline int __raw_write_can_lock(raw_rwlock_t *x) +{ + return (x)->lock == RW_LOCK_BIAS; +} + +static inline void __raw_read_lock(raw_rwlock_t *rw) +{ + __raw_spin_lock(&rw->slock); + while (rw->lock == 0); + rw->lock--; + __raw_spin_unlock(&rw->slock); +} + +static inline void __raw_write_lock(raw_rwlock_t *rw) +{ + __raw_spin_lock(&rw->slock); + while (rw->lock != RW_LOCK_BIAS); + rw->lock == 0; + __raw_spin_unlock(&rw->slock); +} + +static inline void __raw_read_unlock(raw_rwlock_t *rw) +{ + __raw_spin_lock(&rw->slock); + rw->lock++; + __raw_spin_unlock(&rw->slock); +} + +static inline void __raw_write_unlock(raw_rwlock_t *rw) +{ + __raw_spin_lock(&rw->slock); + while (rw->lock != RW_LOCK_BIAS); + rw->lock == RW_LOCK_BIAS; + __raw_spin_unlock(&rw->slock); +} + +static inline int __raw_read_trylock(raw_rwlock_t *rw) +{ + int ret = 0; + __raw_spin_lock(&rw->slock); + if (rw->lock != 0) { + rw->lock--; + ret = 1; + } + __raw_spin_unlock(&rw->slock); + return ret; +} + +static inline int __raw_write_trylock(raw_rwlock_t *rw) +{ + int ret = 0; + __raw_spin_lock(&rw->slock); + if (rw->lock == RW_LOCK_BIAS) { + rw->lock == 0; + ret = 1; + } + __raw_spin_unlock(&rw->slock); + return 1; +} + + +#define _raw_spin_relax(lock) cpu_relax() +#define _raw_read_relax(lock) cpu_relax() +#define _raw_write_relax(lock) cpu_relax() + +#endif /* __ASM_ARCH_SPINLOCK_H */ diff --git a/arch/cris/include/arch-v32/arch/system.h b/arch/cris/include/arch-v32/arch/system.h new file mode 100644 index 000000000000..6ca90f1f110a --- /dev/null +++ b/arch/cris/include/arch-v32/arch/system.h @@ -0,0 +1,69 @@ +#ifndef _ASM_CRIS_ARCH_SYSTEM_H +#define _ASM_CRIS_ARCH_SYSTEM_H + + +/* Read the CPU version register. */ +static inline unsigned long rdvr(void) +{ + unsigned char vr; + + __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); + return vr; +} + +#define cris_machine_name "crisv32" + +/* Read the user-mode stack pointer. */ +static inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); + return usp; +} + +/* Read the current stack pointer. */ +static inline unsigned long rdsp(void) +{ + unsigned long sp; + + __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); + return sp; +} + +/* Write the user-mode stack pointer. */ +#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) + +#define nop() __asm__ __volatile__ ("nop"); + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr)))) + +#define tas(ptr) (xchg((ptr),1)) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* Used for interrupt control. */ +#define local_save_flags(x) \ + __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); + +#define local_irq_restore(x) \ + __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); + +#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); +#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + \ + local_save_flags(flags);\ + !(flags & (1 << I_CCS_BITNR)); \ +}) + +/* Used for spinlocks, etc. */ +#define local_irq_save(x) \ + __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); + +#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/arch/cris/include/arch-v32/arch/thread_info.h b/arch/cris/include/arch-v32/arch/thread_info.h new file mode 100644 index 000000000000..d6936956a3c6 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/thread_info.h @@ -0,0 +1,13 @@ +#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H +#define _ASM_CRIS_ARCH_THREAD_INFO_H + +/* Return a thread_info struct. */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + + __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); + return ti; +} + +#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/arch/cris/include/arch-v32/arch/timex.h b/arch/cris/include/arch-v32/arch/timex.h new file mode 100644 index 000000000000..2591d3c5ed9d --- /dev/null +++ b/arch/cris/include/arch-v32/arch/timex.h @@ -0,0 +1,31 @@ +#ifndef _ASM_CRIS_ARCH_TIMEX_H +#define _ASM_CRIS_ARCH_TIMEX_H + +#include +#include +#include + +/* + * The clock runs at 100MHz, we divide it by 1000000. If you change anything + * here you must check time.c as well. + */ + +#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ + +/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ +#define TIMER0_FREQ (CLOCK_TICK_RATE) +#define TIMER0_DIV (TIMER0_FREQ/(HZ)) + +/* Convert the value in step of 10 ns to 1us without overflow: */ +#define GET_JIFFIES_USEC() \ + ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) + +extern unsigned long get_ns_in_jiffie(void); + +static inline unsigned long get_us_in_jiffie_highres(void) +{ + return get_ns_in_jiffie() / 1000; +} + +#endif + diff --git a/arch/cris/include/arch-v32/arch/tlb.h b/arch/cris/include/arch-v32/arch/tlb.h new file mode 100644 index 000000000000..4effb1253660 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/tlb.h @@ -0,0 +1,14 @@ +#ifndef _CRIS_ARCH_TLB_H +#define _CRIS_ARCH_TLB_H + +/* + * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used + * to store the "process" it belongs to (=> fast mm context switch). The + * last page_id is never used so we can make TLB entries that never matches. + */ +#define NUM_TLB_ENTRIES 64 +#define NUM_PAGEID 256 +#define INVALID_PAGEID 255 +#define NO_CONTEXT -1 + +#endif /* _CRIS_ARCH_TLB_H */ diff --git a/arch/cris/include/arch-v32/arch/uaccess.h b/arch/cris/include/arch-v32/arch/uaccess.h new file mode 100644 index 000000000000..6b207f1b6622 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/uaccess.h @@ -0,0 +1,748 @@ +/* + * Authors: Hans-Peter Nilsson (hp@axis.com) + * + */ +#ifndef _CRIS_ARCH_UACCESS_H +#define _CRIS_ARCH_UACCESS_H + +/* + * We don't tell gcc that we are accessing memory, but this is OK + * because we do not write to any memory gcc knows about, so there + * are no aliasing issues. + * + * Note that PC at a fault is the address *at* the faulting + * instruction for CRISv32. + */ +#define __put_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + "2: "op" %1,[%2]\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " nop\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __put_user_asm_64(x, addr, err) do { \ + int dummy_for_put_user_asm_64_; \ + __asm__ __volatile__( \ + "2: move.d %M2,[%1+]\n" \ + "4: move.d %H2,[%1]\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %4,%0\n" \ + " jump 5b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ + : "r" (x), "1" (addr), "g" (-EFAULT), \ + "0" (err)); \ + } while (0) + +/* See comment before __put_user_asm. */ + +#define __get_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + "2: "op" [%2],%1\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " moveq 0,%1\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __get_user_asm_64(x, addr, err) do { \ + int dummy_for_get_user_asm_64_; \ + __asm__ __volatile__( \ + "2: move.d [%2+],%M1\n" \ + "4: move.d [%2],%H1\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %4,%0\n" \ + " jump 5b\n" \ + " moveq 0,%1\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x), \ + "=b" (dummy_for_get_user_asm_64_) \ + : "2" (addr), "g" (-EFAULT), "0" (err));\ + } while (0) + +/* + * Copy a null terminated string from userspace. + * + * Must return: + * -EFAULT for an exception + * count if we hit the buffer limit + * bytes copied if we hit a null byte + * (without the null byte) + */ +static inline long +__do_strncpy_from_user(char *dst, const char *src, long count) +{ + long res; + + if (count == 0) + return 0; + + /* + * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. + * So do we. + * + * This code is deduced from: + * + * char tmp2; + * long tmp1, tmp3; + * tmp1 = count; + * while ((*dst++ = (tmp2 = *src++)) != 0 + * && --tmp1) + * ; + * + * res = count - tmp1; + * + * with tweaks. + */ + + __asm__ __volatile__ ( + " move.d %3,%0\n" + "5: move.b [%2+],$acr\n" + "1: beq 2f\n" + " move.b $acr,[%1+]\n" + + " subq 1,%0\n" + "2: bne 1b\n" + " move.b [%2+],$acr\n" + + " sub.d %3,%0\n" + " neg.d %0,%0\n" + "3:\n" + " .section .fixup,\"ax\"\n" + "4: move.d %7,%0\n" + " jump 3b\n" + " nop\n" + + /* The address for a fault at the first move is trivial. + The address for a fault at the second move is that of + the preceding branch insn, since the move insn is in + its delay-slot. That address is also a branch + target. Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 5b,4b\n" + " .dword 2b,4b\n" + " .previous" + : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) + : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) + : "acr"); + + return res; +} + +/* A few copy asms to build up the more complex ones from. + + Note again, a post-increment is performed regardless of whether a bus + fault occurred in that instruction, and PC for a faulted insn is the + address for the insn, or for the preceding branch when in a delay-slot. */ + +#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + COPY \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous\n" \ + : "=b" (to), "=b" (from), "=r" (ret) \ + : "0" (to), "1" (from), "2" (ret) \ + : "acr", "memory") + +#define __asm_copy_from_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + "2: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "3: addq 1,%2\n" \ + " jump 1b\n" \ + " clear.b [%0+]\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + "2: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "3: addq 2,%2\n" \ + " jump 1b\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_3(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, \ + "4: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + "2: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "3: addq 4,%2\n" \ + " jump 1b\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_4(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_5(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + "4: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + COPY \ + "4: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "5: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_7(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, \ + "6: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + COPY \ + "4: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "5: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_8(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_9(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + "6: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + COPY \ + "6: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "7: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_11(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, \ + "8: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + COPY \ + "6: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "7: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_12(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_13(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + "8: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + COPY \ + "8: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "9: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_15(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, \ + "10: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "11: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + COPY \ + "8: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "9: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_16(to, from, ret) \ + __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_16x_cont(to, from, ret, \ + COPY \ + "10: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "11: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_20(to, from, ret) \ + __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_20x_cont(to, from, ret, \ + COPY \ + "12: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "13: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_copy_from_user_24(to, from, ret) \ + __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") + +/* And now, the to-user ones. */ + +#define __asm_copy_to_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "2: move.b $acr,[%0+]\n", \ + "3: jump 1b\n" \ + " addq 1,%2\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "2: move.w $acr,[%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 2,%2\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_3(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "4: move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "2: move.d $acr,[%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 4,%2\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_4(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_5(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "4: move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "4: move.w $acr,[%0+]\n", \ + FIXUP \ + "5: addq 2,%2\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_7(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "6: move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "4: move.d $acr,[%0+]\n", \ + FIXUP \ + "5: addq 4,%2\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_8(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_9(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "6: move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "6: move.w $acr,[%0+]\n", \ + FIXUP \ + "7: addq 2,%2\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_11(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "8: move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "6: move.d $acr,[%0+]\n", \ + FIXUP \ + "7: addq 4,%2\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_12(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_13(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "8: move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "8: move.w $acr,[%0+]\n", \ + FIXUP \ + "9: addq 2,%2\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_15(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "10: move.b $acr,[%0+]\n", \ + "11: addq 1,%2\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "8: move.d $acr,[%0+]\n", \ + FIXUP \ + "9: addq 4,%2\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_16(to, from, ret) \ + __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_16x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "10: move.d $acr,[%0+]\n", \ + FIXUP \ + "11: addq 4,%2\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_20(to, from, ret) \ + __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_20x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "12: move.d $acr,[%0+]\n", \ + FIXUP \ + "13: addq 4,%2\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_copy_to_user_24(to, from, ret) \ + __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") + +/* Define a few clearing asms with exception handlers. */ + +/* This frame-asm is like the __asm_copy_user_cont one, but has one less + input. */ + +#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + CLEAR \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous" \ + : "=b" (to), "=r" (ret) \ + : "0" (to), "1" (ret) \ + : "memory") + +#define __asm_clear_1(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.b [%0+]\n", \ + "3: jump 1b\n" \ + " addq 1,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_2(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.w [%0+]\n", \ + "3: jump 1b\n" \ + " addq 2,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_3(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.w [%0+]\n" \ + "3: clear.b [%0+]\n", \ + "4: addq 2,%1\n" \ + "5: jump 1b\n" \ + " addq 1,%1\n", \ + " .dword 2b,4b\n" \ + " .dword 3b,5b\n") + +#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear(to, ret, \ + CLEAR \ + "2: clear.d [%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 4,%1\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_clear_4(to, ret) \ + __asm_clear_4x_cont(to, ret, "", "", "") + +#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_4x_cont(to, ret, \ + CLEAR \ + "4: clear.d [%0+]\n", \ + FIXUP \ + "5: addq 4,%1\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_clear_8(to, ret) \ + __asm_clear_8x_cont(to, ret, "", "", "") + +#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_8x_cont(to, ret, \ + CLEAR \ + "6: clear.d [%0+]\n", \ + FIXUP \ + "7: addq 4,%1\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_clear_12(to, ret) \ + __asm_clear_12x_cont(to, ret, "", "", "") + +#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_12x_cont(to, ret, \ + CLEAR \ + "8: clear.d [%0+]\n", \ + FIXUP \ + "9: addq 4,%1\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_clear_16(to, ret) \ + __asm_clear_16x_cont(to, ret, "", "", "") + +#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_16x_cont(to, ret, \ + CLEAR \ + "10: clear.d [%0+]\n", \ + FIXUP \ + "11: addq 4,%1\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_clear_20(to, ret) \ + __asm_clear_20x_cont(to, ret, "", "", "") + +#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_20x_cont(to, ret, \ + CLEAR \ + "12: clear.d [%0+]\n", \ + FIXUP \ + "13: addq 4,%1\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_clear_24(to, ret) \ + __asm_clear_24x_cont(to, ret, "", "", "") + +/* + * Return the size of a string (including the ending 0) + * + * Return length of string in userspace including terminating 0 + * or 0 for error. Return a value greater than N if too long. + */ + +static inline long +strnlen_user(const char *s, long n) +{ + long res, tmp1; + + if (!access_ok(VERIFY_READ, s, 0)) + return 0; + + /* + * This code is deduced from: + * + * tmp1 = n; + * while (tmp1-- > 0 && *s++) + * ; + * + * res = n - tmp1; + * + * (with tweaks). + */ + + __asm__ __volatile__ ( + " move.d %1,$acr\n" + " cmpq 0,$acr\n" + "0:\n" + " ble 1f\n" + " subq 1,$acr\n" + + "4: test.b [%0+]\n" + " bne 0b\n" + " cmpq 0,$acr\n" + "1:\n" + " move.d %1,%0\n" + " sub.d $acr,%0\n" + "2:\n" + " .section .fixup,\"ax\"\n" + + "3: jump 2b\n" + " clear.d %0\n" + + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 4b,3b\n" + " .previous\n" + : "=r" (res), "=r" (tmp1) + : "0" (s), "1" (n) + : "acr"); + + return res; +} + +#endif diff --git a/arch/cris/include/arch-v32/arch/unistd.h b/arch/cris/include/arch-v32/arch/unistd.h new file mode 100644 index 000000000000..0051114c63c7 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/unistd.h @@ -0,0 +1,155 @@ +#ifndef _ASM_CRIS_ARCH_UNISTD_H_ +#define _ASM_CRIS_ARCH_UNISTD_H_ + +/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ +/* + * Don't remove the .ifnc tests; they are an insurance against + * any hard-to-spot gcc register allocation bugs. + */ +#define _syscall0(type,name) \ +type name(void) \ +{ \ + register long __a __asm__ ("r10"); \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1,type2 arg2) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1,type2 arg2,type3 arg3) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d)\ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __e __asm__ ("mof") = (long) arg5; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "h" (__e) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5,type6,arg6) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __e __asm__ ("mof") = (long) arg5; \ + register long __f __asm__ ("srp") = (long) arg6; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#endif diff --git a/arch/cris/include/arch-v32/arch/user.h b/arch/cris/include/arch-v32/arch/user.h new file mode 100644 index 000000000000..03fa1f3c3c00 --- /dev/null +++ b/arch/cris/include/arch-v32/arch/user.h @@ -0,0 +1,41 @@ +#ifndef _ASM_CRIS_ARCH_USER_H +#define _ASM_CRIS_ARCH_USER_H + +/* User-mode register used for core dumps. */ + +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* R14, Stack pointer. */ + unsigned long acr; /* R15, Address calculation register. */ + unsigned long bz; /* P0, Constant zero (8-bits). */ + unsigned long vr; /* P1, Version register (8-bits). */ + unsigned long pid; /* P2, Process ID (8-bits). */ + unsigned long srs; /* P3, Support register select (8-bits). */ + unsigned long wz; /* P4, Constant zero (16-bits). */ + unsigned long exs; /* P5, Exception status. */ + unsigned long eda; /* P6, Exception data address. */ + unsigned long mof; /* P7, Multiply overflow regiter. */ + unsigned long dz; /* P8, Constant zero (32-bits). */ + unsigned long ebp; /* P9, Exception base pointer. */ + unsigned long erp; /* P10, Exception return pointer. */ + unsigned long srp; /* P11, Subroutine return pointer. */ + unsigned long nrp; /* P12, NMI return pointer. */ + unsigned long ccs; /* P13, Condition code stack. */ + unsigned long usp; /* P14, User mode stack pointer. */ + unsigned long spc; /* P15, Single step PC. */ +}; + +#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h b/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h new file mode 100644 index 000000000000..65e9d6ff0520 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h @@ -0,0 +1,34 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum { + arbiter_all_dmas = 0x7fe, + arbiter_cpu = 0x1800, + arbiter_all_clients = 0x7fff +}; + +enum { + arbiter_bar_all_clients = 0x1ff +}; + +enum { + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback * cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h new file mode 100644 index 000000000000..9e8eb13b601d --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/dma.h @@ -0,0 +1,31 @@ +#ifndef _ASM_ARCH_CRIS_DMA_H +#define _ASM_ARCH_CRIS_DMA_H + +/* Defines for using and allocating dma channels. */ + +#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ + +enum dma_owner { + dma_eth, + dma_ser0, + dma_ser1, + dma_ser2, + dma_ser3, + dma_ser4, + dma_iop, + dma_sser, + dma_strp, + dma_h264, + dma_jpeg +}; + +int crisv32_request_dma(unsigned int dmanr, const char *device_id, + unsigned options, unsigned bandwidth, enum dma_owner owner); +void crisv32_free_dma(unsigned int dmanr); + +/* Masks used by crisv32_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR 1 +#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) +#define DMA_INT_MEM 4 + +#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h new file mode 100644 index 000000000000..02855adf63e8 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h @@ -0,0 +1,164 @@ +#ifndef __clkgen_defs_asm_h +#define __clkgen_defs_asm_h + +/* + * This file is autogenerated from + * file: clkgen.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope clkgen, type r */ +#define reg_clkgen_r_bootsel___boot_mode___lsb 0 +#define reg_clkgen_r_bootsel___boot_mode___width 5 +#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 +#define reg_clkgen_r_bootsel___intern_main_clk___width 1 +#define reg_clkgen_r_bootsel___intern_main_clk___bit 5 +#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 +#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 +#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 +#define reg_clkgen_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope clkgen, type rw */ +#define reg_clkgen_rw_clk_ctrl___pll___lsb 0 +#define reg_clkgen_rw_clk_ctrl___pll___width 1 +#define reg_clkgen_rw_clk_ctrl___pll___bit 0 +#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 +#define reg_clkgen_rw_clk_ctrl___cpu___width 1 +#define reg_clkgen_rw_clk_ctrl___cpu___bit 1 +#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 +#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 +#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 +#define reg_clkgen_rw_clk_ctrl___vin___lsb 3 +#define reg_clkgen_rw_clk_ctrl___vin___width 1 +#define reg_clkgen_rw_clk_ctrl___vin___bit 3 +#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 +#define reg_clkgen_rw_clk_ctrl___sclr___width 1 +#define reg_clkgen_rw_clk_ctrl___sclr___bit 4 +#define reg_clkgen_rw_clk_ctrl___h264___lsb 5 +#define reg_clkgen_rw_clk_ctrl___h264___width 1 +#define reg_clkgen_rw_clk_ctrl___h264___bit 5 +#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 +#define reg_clkgen_rw_clk_ctrl___ddr2___width 1 +#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 +#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 +#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 +#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 +#define reg_clkgen_rw_clk_ctrl___eth___lsb 8 +#define reg_clkgen_rw_clk_ctrl___eth___width 1 +#define reg_clkgen_rw_clk_ctrl___eth___bit 8 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 +#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 +#define reg_clkgen_rw_clk_ctrl___jpeg___width 1 +#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 +#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 +#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 +#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 +#define reg_clkgen_rw_clk_ctrl_offset 4 + + +/* Constants */ +#define regk_clkgen_eth1000_rx 0x0000000c +#define regk_clkgen_eth1000_tx 0x0000000e +#define regk_clkgen_eth100_rx 0x0000001d +#define regk_clkgen_eth100_rx_half 0x0000001c +#define regk_clkgen_eth100_tx 0x0000001f +#define regk_clkgen_eth100_tx_half 0x0000001e +#define regk_clkgen_nand_3_2 0x00000000 +#define regk_clkgen_nand_3_2_0x30 0x00000002 +#define regk_clkgen_nand_3_2_0x30_pll 0x00000012 +#define regk_clkgen_nand_3_2_pll 0x00000010 +#define regk_clkgen_nand_3_3 0x00000001 +#define regk_clkgen_nand_3_3_0x30 0x00000003 +#define regk_clkgen_nand_3_3_0x30_pll 0x00000013 +#define regk_clkgen_nand_3_3_pll 0x00000011 +#define regk_clkgen_nand_4_2 0x00000004 +#define regk_clkgen_nand_4_2_0x30 0x00000006 +#define regk_clkgen_nand_4_2_0x30_pll 0x00000016 +#define regk_clkgen_nand_4_2_pll 0x00000014 +#define regk_clkgen_nand_4_3 0x00000005 +#define regk_clkgen_nand_4_3_0x30 0x00000007 +#define regk_clkgen_nand_4_3_0x30_pll 0x00000017 +#define regk_clkgen_nand_4_3_pll 0x00000015 +#define regk_clkgen_nand_5_2 0x00000008 +#define regk_clkgen_nand_5_2_0x30 0x0000000a +#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a +#define regk_clkgen_nand_5_2_pll 0x00000018 +#define regk_clkgen_nand_5_3 0x00000009 +#define regk_clkgen_nand_5_3_0x30 0x0000000b +#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b +#define regk_clkgen_nand_5_3_pll 0x00000019 +#define regk_clkgen_no 0x00000000 +#define regk_clkgen_rw_clk_ctrl_default 0x00000002 +#define regk_clkgen_ser 0x0000000d +#define regk_clkgen_ser_pll 0x0000000f +#define regk_clkgen_yes 0x00000001 +#endif /* __clkgen_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h new file mode 100644 index 000000000000..b12be03edacb --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h @@ -0,0 +1,266 @@ +#ifndef __ddr2_defs_asm_h +#define __ddr2_defs_asm_h + +/* + * This file is autogenerated from + * file: ddr2.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope ddr2, type rw */ +#define reg_ddr2_rw_cfg___col_width___lsb 0 +#define reg_ddr2_rw_cfg___col_width___width 4 +#define reg_ddr2_rw_cfg___nr_banks___lsb 4 +#define reg_ddr2_rw_cfg___nr_banks___width 1 +#define reg_ddr2_rw_cfg___nr_banks___bit 4 +#define reg_ddr2_rw_cfg___bw___lsb 5 +#define reg_ddr2_rw_cfg___bw___width 1 +#define reg_ddr2_rw_cfg___bw___bit 5 +#define reg_ddr2_rw_cfg___nr_ref___lsb 6 +#define reg_ddr2_rw_cfg___nr_ref___width 4 +#define reg_ddr2_rw_cfg___ref_interval___lsb 10 +#define reg_ddr2_rw_cfg___ref_interval___width 11 +#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 +#define reg_ddr2_rw_cfg___odt_ctrl___width 2 +#define reg_ddr2_rw_cfg___odt_mem___lsb 23 +#define reg_ddr2_rw_cfg___odt_mem___width 1 +#define reg_ddr2_rw_cfg___odt_mem___bit 23 +#define reg_ddr2_rw_cfg___imp_strength___lsb 24 +#define reg_ddr2_rw_cfg___imp_strength___width 1 +#define reg_ddr2_rw_cfg___imp_strength___bit 24 +#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 +#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 +#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 +#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 +#define reg_ddr2_rw_cfg___imp_cal_override___width 1 +#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 +#define reg_ddr2_rw_cfg___dll_override___lsb 27 +#define reg_ddr2_rw_cfg___dll_override___width 1 +#define reg_ddr2_rw_cfg___dll_override___bit 27 +#define reg_ddr2_rw_cfg_offset 0 + +/* Register rw_timing, scope ddr2, type rw */ +#define reg_ddr2_rw_timing___wr___lsb 0 +#define reg_ddr2_rw_timing___wr___width 3 +#define reg_ddr2_rw_timing___rcd___lsb 3 +#define reg_ddr2_rw_timing___rcd___width 3 +#define reg_ddr2_rw_timing___rp___lsb 6 +#define reg_ddr2_rw_timing___rp___width 3 +#define reg_ddr2_rw_timing___ras___lsb 9 +#define reg_ddr2_rw_timing___ras___width 4 +#define reg_ddr2_rw_timing___rfc___lsb 13 +#define reg_ddr2_rw_timing___rfc___width 7 +#define reg_ddr2_rw_timing___rc___lsb 20 +#define reg_ddr2_rw_timing___rc___width 5 +#define reg_ddr2_rw_timing___rtp___lsb 25 +#define reg_ddr2_rw_timing___rtp___width 2 +#define reg_ddr2_rw_timing___rtw___lsb 27 +#define reg_ddr2_rw_timing___rtw___width 3 +#define reg_ddr2_rw_timing___wtr___lsb 30 +#define reg_ddr2_rw_timing___wtr___width 2 +#define reg_ddr2_rw_timing_offset 4 + +/* Register rw_latency, scope ddr2, type rw */ +#define reg_ddr2_rw_latency___cas___lsb 0 +#define reg_ddr2_rw_latency___cas___width 3 +#define reg_ddr2_rw_latency___additive___lsb 3 +#define reg_ddr2_rw_latency___additive___width 3 +#define reg_ddr2_rw_latency_offset 8 + +/* Register rw_phy_cfg, scope ddr2, type rw */ +#define reg_ddr2_rw_phy_cfg___en___lsb 0 +#define reg_ddr2_rw_phy_cfg___en___width 1 +#define reg_ddr2_rw_phy_cfg___en___bit 0 +#define reg_ddr2_rw_phy_cfg_offset 12 + +/* Register rw_phy_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 +#define reg_ddr2_rw_phy_ctrl___rst___width 1 +#define reg_ddr2_rw_phy_ctrl___rst___bit 0 +#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 +#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 +#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 +#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 +#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 +#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 +#define reg_ddr2_rw_phy_ctrl_offset 16 + +/* Register rw_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 +#define reg_ddr2_rw_ctrl___mrs_data___width 16 +#define reg_ddr2_rw_ctrl___cmd___lsb 16 +#define reg_ddr2_rw_ctrl___cmd___width 8 +#define reg_ddr2_rw_ctrl_offset 20 + +/* Register rw_pwr_down, scope ddr2, type rw */ +#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 +#define reg_ddr2_rw_pwr_down___self_ref___width 2 +#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 +#define reg_ddr2_rw_pwr_down___phy_en___width 1 +#define reg_ddr2_rw_pwr_down___phy_en___bit 2 +#define reg_ddr2_rw_pwr_down_offset 24 + +/* Register r_stat, scope ddr2, type r */ +#define reg_ddr2_r_stat___dll_lock___lsb 0 +#define reg_ddr2_r_stat___dll_lock___width 1 +#define reg_ddr2_r_stat___dll_lock___bit 0 +#define reg_ddr2_r_stat___dll_delay_code___lsb 1 +#define reg_ddr2_r_stat___dll_delay_code___width 7 +#define reg_ddr2_r_stat___imp_cal_done___lsb 8 +#define reg_ddr2_r_stat___imp_cal_done___width 1 +#define reg_ddr2_r_stat___imp_cal_done___bit 8 +#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 +#define reg_ddr2_r_stat___imp_cal_fault___width 1 +#define reg_ddr2_r_stat___imp_cal_fault___bit 9 +#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 +#define reg_ddr2_r_stat___cal_imp_pu___width 4 +#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 +#define reg_ddr2_r_stat___cal_imp_pd___width 4 +#define reg_ddr2_r_stat_offset 28 + +/* Register rw_imp_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 +#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 +#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 +#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 +#define reg_ddr2_rw_imp_ctrl_offset 32 + +#define STRIDE_ddr2_rw_dll_ctrl 4 +/* Register rw_dll_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 +#define reg_ddr2_rw_dll_ctrl___mode___width 1 +#define reg_ddr2_rw_dll_ctrl___mode___bit 0 +#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 +#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 +#define reg_ddr2_rw_dll_ctrl_offset 36 + +#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 +/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 + + +/* Constants */ +#define regk_ddr2_al0 0x00000000 +#define regk_ddr2_al1 0x00000008 +#define regk_ddr2_al2 0x00000010 +#define regk_ddr2_al3 0x00000018 +#define regk_ddr2_al4 0x00000020 +#define regk_ddr2_auto 0x00000003 +#define regk_ddr2_bank4 0x00000000 +#define regk_ddr2_bank8 0x00000001 +#define regk_ddr2_bl4 0x00000002 +#define regk_ddr2_bl8 0x00000003 +#define regk_ddr2_bt_il 0x00000008 +#define regk_ddr2_bt_seq 0x00000000 +#define regk_ddr2_bw16 0x00000001 +#define regk_ddr2_bw32 0x00000000 +#define regk_ddr2_cas2 0x00000020 +#define regk_ddr2_cas3 0x00000030 +#define regk_ddr2_cas4 0x00000040 +#define regk_ddr2_cas5 0x00000050 +#define regk_ddr2_deselect 0x000000c0 +#define regk_ddr2_dic_weak 0x00000002 +#define regk_ddr2_direct 0x00000001 +#define regk_ddr2_dis 0x00000000 +#define regk_ddr2_dll_dis 0x00000001 +#define regk_ddr2_dll_en 0x00000000 +#define regk_ddr2_dll_rst 0x00000100 +#define regk_ddr2_emrs 0x00000081 +#define regk_ddr2_emrs2 0x00000082 +#define regk_ddr2_emrs3 0x00000083 +#define regk_ddr2_full 0x00000001 +#define regk_ddr2_hi_ref_rate 0x00000080 +#define regk_ddr2_mrs 0x00000080 +#define regk_ddr2_no 0x00000000 +#define regk_ddr2_nop 0x000000b8 +#define regk_ddr2_ocd_adj 0x00000200 +#define regk_ddr2_ocd_default 0x00000380 +#define regk_ddr2_ocd_drive0 0x00000100 +#define regk_ddr2_ocd_drive1 0x00000080 +#define regk_ddr2_ocd_exit 0x00000000 +#define regk_ddr2_odt_dis 0x00000000 +#define regk_ddr2_offs 0x00000000 +#define regk_ddr2_pre 0x00000090 +#define regk_ddr2_pre_all 0x00000400 +#define regk_ddr2_pwr_down_fast 0x00000000 +#define regk_ddr2_pwr_down_slow 0x00001000 +#define regk_ddr2_ref 0x00000088 +#define regk_ddr2_rtt150 0x00000040 +#define regk_ddr2_rtt50 0x00000044 +#define regk_ddr2_rtt75 0x00000004 +#define regk_ddr2_rw_cfg_default 0x00186000 +#define regk_ddr2_rw_dll_ctrl_default 0x00000000 +#define regk_ddr2_rw_dll_ctrl_size 0x00000004 +#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 +#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 +#define regk_ddr2_rw_latency_default 0x00000000 +#define regk_ddr2_rw_phy_cfg_default 0x00000000 +#define regk_ddr2_rw_pwr_down_default 0x00000000 +#define regk_ddr2_rw_timing_default 0x00000000 +#define regk_ddr2_s1Gb 0x0000001a +#define regk_ddr2_s256Mb 0x0000000f +#define regk_ddr2_s2Gb 0x00000027 +#define regk_ddr2_s4Gb 0x00000042 +#define regk_ddr2_s512Mb 0x00000015 +#define regk_ddr2_temp0_85 0x00000618 +#define regk_ddr2_temp85_95 0x0000030c +#define regk_ddr2_term150 0x00000002 +#define regk_ddr2_term50 0x00000003 +#define regk_ddr2_term75 0x00000001 +#define regk_ddr2_test 0x00000080 +#define regk_ddr2_weak 0x00000000 +#define regk_ddr2_wr2 0x00000200 +#define regk_ddr2_wr3 0x00000400 +#define regk_ddr2_yes 0x00000001 +#endif /* __ddr2_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000000..df6714fda179 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,849 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: gio.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 32 +#define reg_gio_r_pa_din_offset 0 + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 32 +#define reg_gio_rw_pa_dout_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 32 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_pa_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte0_dout___data___lsb 0 +#define reg_gio_rw_pa_byte0_dout___data___width 8 +#define reg_gio_rw_pa_byte0_dout_offset 12 + +/* Register rw_pa_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte0_oe___oe___width 8 +#define reg_gio_rw_pa_byte0_oe_offset 16 + +/* Register rw_pa_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte1_dout___data___lsb 0 +#define reg_gio_rw_pa_byte1_dout___data___width 8 +#define reg_gio_rw_pa_byte1_dout_offset 20 + +/* Register rw_pa_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte1_oe___oe___width 8 +#define reg_gio_rw_pa_byte1_oe_offset 24 + +/* Register rw_pa_byte2_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte2_dout___data___lsb 0 +#define reg_gio_rw_pa_byte2_dout___data___width 8 +#define reg_gio_rw_pa_byte2_dout_offset 28 + +/* Register rw_pa_byte2_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte2_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte2_oe___oe___width 8 +#define reg_gio_rw_pa_byte2_oe_offset 32 + +/* Register rw_pa_byte3_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte3_dout___data___lsb 0 +#define reg_gio_rw_pa_byte3_dout___data___width 8 +#define reg_gio_rw_pa_byte3_dout_offset 36 + +/* Register rw_pa_byte3_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte3_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte3_oe___oe___width 8 +#define reg_gio_rw_pa_byte3_oe_offset 40 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 32 +#define reg_gio_r_pb_din_offset 44 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 32 +#define reg_gio_rw_pb_dout_offset 48 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 32 +#define reg_gio_rw_pb_oe_offset 52 + +/* Register rw_pb_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte0_dout___data___lsb 0 +#define reg_gio_rw_pb_byte0_dout___data___width 8 +#define reg_gio_rw_pb_byte0_dout_offset 56 + +/* Register rw_pb_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte0_oe___oe___width 8 +#define reg_gio_rw_pb_byte0_oe_offset 60 + +/* Register rw_pb_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte1_dout___data___lsb 0 +#define reg_gio_rw_pb_byte1_dout___data___width 8 +#define reg_gio_rw_pb_byte1_dout_offset 64 + +/* Register rw_pb_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte1_oe___oe___width 8 +#define reg_gio_rw_pb_byte1_oe_offset 68 + +/* Register rw_pb_byte2_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte2_dout___data___lsb 0 +#define reg_gio_rw_pb_byte2_dout___data___width 8 +#define reg_gio_rw_pb_byte2_dout_offset 72 + +/* Register rw_pb_byte2_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte2_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte2_oe___oe___width 8 +#define reg_gio_rw_pb_byte2_oe_offset 76 + +/* Register rw_pb_byte3_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte3_dout___data___lsb 0 +#define reg_gio_rw_pb_byte3_dout___data___width 8 +#define reg_gio_rw_pb_byte3_dout_offset 80 + +/* Register rw_pb_byte3_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte3_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte3_oe___oe___width 8 +#define reg_gio_rw_pb_byte3_oe_offset 84 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 16 +#define reg_gio_r_pc_din_offset 88 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 16 +#define reg_gio_rw_pc_dout_offset 92 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 16 +#define reg_gio_rw_pc_oe_offset 96 + +/* Register rw_pc_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pc_byte0_dout___data___lsb 0 +#define reg_gio_rw_pc_byte0_dout___data___width 8 +#define reg_gio_rw_pc_byte0_dout_offset 100 + +/* Register rw_pc_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pc_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pc_byte0_oe___oe___width 8 +#define reg_gio_rw_pc_byte0_oe_offset 104 + +/* Register rw_pc_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pc_byte1_dout___data___lsb 0 +#define reg_gio_rw_pc_byte1_dout___data___width 8 +#define reg_gio_rw_pc_byte1_dout_offset 108 + +/* Register rw_pc_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pc_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pc_byte1_oe___oe___width 8 +#define reg_gio_rw_pc_byte1_oe_offset 112 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 32 +#define reg_gio_r_pd_din_offset 116 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___intr0___lsb 0 +#define reg_gio_rw_intr_cfg___intr0___width 3 +#define reg_gio_rw_intr_cfg___intr1___lsb 3 +#define reg_gio_rw_intr_cfg___intr1___width 3 +#define reg_gio_rw_intr_cfg___intr2___lsb 6 +#define reg_gio_rw_intr_cfg___intr2___width 3 +#define reg_gio_rw_intr_cfg___intr3___lsb 9 +#define reg_gio_rw_intr_cfg___intr3___width 3 +#define reg_gio_rw_intr_cfg___intr4___lsb 12 +#define reg_gio_rw_intr_cfg___intr4___width 3 +#define reg_gio_rw_intr_cfg___intr5___lsb 15 +#define reg_gio_rw_intr_cfg___intr5___width 3 +#define reg_gio_rw_intr_cfg___intr6___lsb 18 +#define reg_gio_rw_intr_cfg___intr6___width 3 +#define reg_gio_rw_intr_cfg___intr7___lsb 21 +#define reg_gio_rw_intr_cfg___intr7___width 3 +#define reg_gio_rw_intr_cfg_offset 120 + +/* Register rw_intr_pins, scope gio, type rw */ +#define reg_gio_rw_intr_pins___intr0___lsb 0 +#define reg_gio_rw_intr_pins___intr0___width 4 +#define reg_gio_rw_intr_pins___intr1___lsb 4 +#define reg_gio_rw_intr_pins___intr1___width 4 +#define reg_gio_rw_intr_pins___intr2___lsb 8 +#define reg_gio_rw_intr_pins___intr2___width 4 +#define reg_gio_rw_intr_pins___intr3___lsb 12 +#define reg_gio_rw_intr_pins___intr3___width 4 +#define reg_gio_rw_intr_pins___intr4___lsb 16 +#define reg_gio_rw_intr_pins___intr4___width 4 +#define reg_gio_rw_intr_pins___intr5___lsb 20 +#define reg_gio_rw_intr_pins___intr5___width 4 +#define reg_gio_rw_intr_pins___intr6___lsb 24 +#define reg_gio_rw_intr_pins___intr6___width 4 +#define reg_gio_rw_intr_pins___intr7___lsb 28 +#define reg_gio_rw_intr_pins___intr7___width 4 +#define reg_gio_rw_intr_pins_offset 124 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___intr0___lsb 0 +#define reg_gio_rw_intr_mask___intr0___width 1 +#define reg_gio_rw_intr_mask___intr0___bit 0 +#define reg_gio_rw_intr_mask___intr1___lsb 1 +#define reg_gio_rw_intr_mask___intr1___width 1 +#define reg_gio_rw_intr_mask___intr1___bit 1 +#define reg_gio_rw_intr_mask___intr2___lsb 2 +#define reg_gio_rw_intr_mask___intr2___width 1 +#define reg_gio_rw_intr_mask___intr2___bit 2 +#define reg_gio_rw_intr_mask___intr3___lsb 3 +#define reg_gio_rw_intr_mask___intr3___width 1 +#define reg_gio_rw_intr_mask___intr3___bit 3 +#define reg_gio_rw_intr_mask___intr4___lsb 4 +#define reg_gio_rw_intr_mask___intr4___width 1 +#define reg_gio_rw_intr_mask___intr4___bit 4 +#define reg_gio_rw_intr_mask___intr5___lsb 5 +#define reg_gio_rw_intr_mask___intr5___width 1 +#define reg_gio_rw_intr_mask___intr5___bit 5 +#define reg_gio_rw_intr_mask___intr6___lsb 6 +#define reg_gio_rw_intr_mask___intr6___width 1 +#define reg_gio_rw_intr_mask___intr6___bit 6 +#define reg_gio_rw_intr_mask___intr7___lsb 7 +#define reg_gio_rw_intr_mask___intr7___width 1 +#define reg_gio_rw_intr_mask___intr7___bit 7 +#define reg_gio_rw_intr_mask___i2c0_done___lsb 8 +#define reg_gio_rw_intr_mask___i2c0_done___width 1 +#define reg_gio_rw_intr_mask___i2c0_done___bit 8 +#define reg_gio_rw_intr_mask___i2c1_done___lsb 9 +#define reg_gio_rw_intr_mask___i2c1_done___width 1 +#define reg_gio_rw_intr_mask___i2c1_done___bit 9 +#define reg_gio_rw_intr_mask_offset 128 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___intr0___lsb 0 +#define reg_gio_rw_ack_intr___intr0___width 1 +#define reg_gio_rw_ack_intr___intr0___bit 0 +#define reg_gio_rw_ack_intr___intr1___lsb 1 +#define reg_gio_rw_ack_intr___intr1___width 1 +#define reg_gio_rw_ack_intr___intr1___bit 1 +#define reg_gio_rw_ack_intr___intr2___lsb 2 +#define reg_gio_rw_ack_intr___intr2___width 1 +#define reg_gio_rw_ack_intr___intr2___bit 2 +#define reg_gio_rw_ack_intr___intr3___lsb 3 +#define reg_gio_rw_ack_intr___intr3___width 1 +#define reg_gio_rw_ack_intr___intr3___bit 3 +#define reg_gio_rw_ack_intr___intr4___lsb 4 +#define reg_gio_rw_ack_intr___intr4___width 1 +#define reg_gio_rw_ack_intr___intr4___bit 4 +#define reg_gio_rw_ack_intr___intr5___lsb 5 +#define reg_gio_rw_ack_intr___intr5___width 1 +#define reg_gio_rw_ack_intr___intr5___bit 5 +#define reg_gio_rw_ack_intr___intr6___lsb 6 +#define reg_gio_rw_ack_intr___intr6___width 1 +#define reg_gio_rw_ack_intr___intr6___bit 6 +#define reg_gio_rw_ack_intr___intr7___lsb 7 +#define reg_gio_rw_ack_intr___intr7___width 1 +#define reg_gio_rw_ack_intr___intr7___bit 7 +#define reg_gio_rw_ack_intr___i2c0_done___lsb 8 +#define reg_gio_rw_ack_intr___i2c0_done___width 1 +#define reg_gio_rw_ack_intr___i2c0_done___bit 8 +#define reg_gio_rw_ack_intr___i2c1_done___lsb 9 +#define reg_gio_rw_ack_intr___i2c1_done___width 1 +#define reg_gio_rw_ack_intr___i2c1_done___bit 9 +#define reg_gio_rw_ack_intr_offset 132 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___intr0___lsb 0 +#define reg_gio_r_intr___intr0___width 1 +#define reg_gio_r_intr___intr0___bit 0 +#define reg_gio_r_intr___intr1___lsb 1 +#define reg_gio_r_intr___intr1___width 1 +#define reg_gio_r_intr___intr1___bit 1 +#define reg_gio_r_intr___intr2___lsb 2 +#define reg_gio_r_intr___intr2___width 1 +#define reg_gio_r_intr___intr2___bit 2 +#define reg_gio_r_intr___intr3___lsb 3 +#define reg_gio_r_intr___intr3___width 1 +#define reg_gio_r_intr___intr3___bit 3 +#define reg_gio_r_intr___intr4___lsb 4 +#define reg_gio_r_intr___intr4___width 1 +#define reg_gio_r_intr___intr4___bit 4 +#define reg_gio_r_intr___intr5___lsb 5 +#define reg_gio_r_intr___intr5___width 1 +#define reg_gio_r_intr___intr5___bit 5 +#define reg_gio_r_intr___intr6___lsb 6 +#define reg_gio_r_intr___intr6___width 1 +#define reg_gio_r_intr___intr6___bit 6 +#define reg_gio_r_intr___intr7___lsb 7 +#define reg_gio_r_intr___intr7___width 1 +#define reg_gio_r_intr___intr7___bit 7 +#define reg_gio_r_intr___i2c0_done___lsb 8 +#define reg_gio_r_intr___i2c0_done___width 1 +#define reg_gio_r_intr___i2c0_done___bit 8 +#define reg_gio_r_intr___i2c1_done___lsb 9 +#define reg_gio_r_intr___i2c1_done___width 1 +#define reg_gio_r_intr___i2c1_done___bit 9 +#define reg_gio_r_intr_offset 136 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___intr0___lsb 0 +#define reg_gio_r_masked_intr___intr0___width 1 +#define reg_gio_r_masked_intr___intr0___bit 0 +#define reg_gio_r_masked_intr___intr1___lsb 1 +#define reg_gio_r_masked_intr___intr1___width 1 +#define reg_gio_r_masked_intr___intr1___bit 1 +#define reg_gio_r_masked_intr___intr2___lsb 2 +#define reg_gio_r_masked_intr___intr2___width 1 +#define reg_gio_r_masked_intr___intr2___bit 2 +#define reg_gio_r_masked_intr___intr3___lsb 3 +#define reg_gio_r_masked_intr___intr3___width 1 +#define reg_gio_r_masked_intr___intr3___bit 3 +#define reg_gio_r_masked_intr___intr4___lsb 4 +#define reg_gio_r_masked_intr___intr4___width 1 +#define reg_gio_r_masked_intr___intr4___bit 4 +#define reg_gio_r_masked_intr___intr5___lsb 5 +#define reg_gio_r_masked_intr___intr5___width 1 +#define reg_gio_r_masked_intr___intr5___bit 5 +#define reg_gio_r_masked_intr___intr6___lsb 6 +#define reg_gio_r_masked_intr___intr6___width 1 +#define reg_gio_r_masked_intr___intr6___bit 6 +#define reg_gio_r_masked_intr___intr7___lsb 7 +#define reg_gio_r_masked_intr___intr7___width 1 +#define reg_gio_r_masked_intr___intr7___bit 7 +#define reg_gio_r_masked_intr___i2c0_done___lsb 8 +#define reg_gio_r_masked_intr___i2c0_done___width 1 +#define reg_gio_r_masked_intr___i2c0_done___bit 8 +#define reg_gio_r_masked_intr___i2c1_done___lsb 9 +#define reg_gio_r_masked_intr___i2c1_done___width 1 +#define reg_gio_r_masked_intr___i2c1_done___bit 9 +#define reg_gio_r_masked_intr_offset 140 + +/* Register rw_i2c0_start, scope gio, type rw */ +#define reg_gio_rw_i2c0_start___run___lsb 0 +#define reg_gio_rw_i2c0_start___run___width 1 +#define reg_gio_rw_i2c0_start___run___bit 0 +#define reg_gio_rw_i2c0_start_offset 144 + +/* Register rw_i2c0_cfg, scope gio, type rw */ +#define reg_gio_rw_i2c0_cfg___en___lsb 0 +#define reg_gio_rw_i2c0_cfg___en___width 1 +#define reg_gio_rw_i2c0_cfg___en___bit 0 +#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 +#define reg_gio_rw_i2c0_cfg___bit_order___width 1 +#define reg_gio_rw_i2c0_cfg___bit_order___bit 1 +#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 +#define reg_gio_rw_i2c0_cfg___scl_io___width 1 +#define reg_gio_rw_i2c0_cfg___scl_io___bit 2 +#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 +#define reg_gio_rw_i2c0_cfg___scl_inv___width 1 +#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 +#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 +#define reg_gio_rw_i2c0_cfg___sda_io___width 1 +#define reg_gio_rw_i2c0_cfg___sda_io___bit 4 +#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 +#define reg_gio_rw_i2c0_cfg___sda_idle___width 1 +#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 +#define reg_gio_rw_i2c0_cfg_offset 148 + +/* Register rw_i2c0_ctrl, scope gio, type rw */ +#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 +#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 +#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 +#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 +#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 +#define reg_gio_rw_i2c0_ctrl___extra_start___width 3 +#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 +#define reg_gio_rw_i2c0_ctrl___early_end___width 1 +#define reg_gio_rw_i2c0_ctrl___early_end___bit 15 +#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 +#define reg_gio_rw_i2c0_ctrl___start_stop___width 1 +#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 +#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 +#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 +#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 +#define reg_gio_rw_i2c0_ctrl___start_bit___width 1 +#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 +#define reg_gio_rw_i2c0_ctrl___freq___lsb 25 +#define reg_gio_rw_i2c0_ctrl___freq___width 2 +#define reg_gio_rw_i2c0_ctrl_offset 152 + +/* Register rw_i2c0_data, scope gio, type rw */ +#define reg_gio_rw_i2c0_data___data0___lsb 0 +#define reg_gio_rw_i2c0_data___data0___width 8 +#define reg_gio_rw_i2c0_data___data1___lsb 8 +#define reg_gio_rw_i2c0_data___data1___width 8 +#define reg_gio_rw_i2c0_data___data2___lsb 16 +#define reg_gio_rw_i2c0_data___data2___width 8 +#define reg_gio_rw_i2c0_data___data3___lsb 24 +#define reg_gio_rw_i2c0_data___data3___width 8 +#define reg_gio_rw_i2c0_data_offset 156 + +/* Register rw_i2c0_data2, scope gio, type rw */ +#define reg_gio_rw_i2c0_data2___data4___lsb 0 +#define reg_gio_rw_i2c0_data2___data4___width 8 +#define reg_gio_rw_i2c0_data2___data5___lsb 8 +#define reg_gio_rw_i2c0_data2___data5___width 8 +#define reg_gio_rw_i2c0_data2___start_val___lsb 16 +#define reg_gio_rw_i2c0_data2___start_val___width 6 +#define reg_gio_rw_i2c0_data2___ack_val___lsb 22 +#define reg_gio_rw_i2c0_data2___ack_val___width 6 +#define reg_gio_rw_i2c0_data2_offset 160 + +/* Register rw_i2c1_start, scope gio, type rw */ +#define reg_gio_rw_i2c1_start___run___lsb 0 +#define reg_gio_rw_i2c1_start___run___width 1 +#define reg_gio_rw_i2c1_start___run___bit 0 +#define reg_gio_rw_i2c1_start_offset 164 + +/* Register rw_i2c1_cfg, scope gio, type rw */ +#define reg_gio_rw_i2c1_cfg___en___lsb 0 +#define reg_gio_rw_i2c1_cfg___en___width 1 +#define reg_gio_rw_i2c1_cfg___en___bit 0 +#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 +#define reg_gio_rw_i2c1_cfg___bit_order___width 1 +#define reg_gio_rw_i2c1_cfg___bit_order___bit 1 +#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 +#define reg_gio_rw_i2c1_cfg___scl_io___width 1 +#define reg_gio_rw_i2c1_cfg___scl_io___bit 2 +#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 +#define reg_gio_rw_i2c1_cfg___scl_inv___width 1 +#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 +#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 +#define reg_gio_rw_i2c1_cfg___sda0_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 +#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 +#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 +#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 +#define reg_gio_rw_i2c1_cfg___sda1_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 +#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 +#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 +#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 +#define reg_gio_rw_i2c1_cfg___sda2_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 +#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 +#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 +#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 +#define reg_gio_rw_i2c1_cfg___sda3_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 +#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 +#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 +#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 +#define reg_gio_rw_i2c1_cfg___sda_sel___width 2 +#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 +#define reg_gio_rw_i2c1_cfg___sen_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 +#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 +#define reg_gio_rw_i2c1_cfg___sen_inv___width 1 +#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 +#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 +#define reg_gio_rw_i2c1_cfg___sen_sel___width 2 +#define reg_gio_rw_i2c1_cfg_offset 168 + +/* Register rw_i2c1_ctrl, scope gio, type rw */ +#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 +#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 +#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 +#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 +#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 +#define reg_gio_rw_i2c1_ctrl___extra_start___width 3 +#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 +#define reg_gio_rw_i2c1_ctrl___early_end___width 1 +#define reg_gio_rw_i2c1_ctrl___early_end___bit 15 +#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 +#define reg_gio_rw_i2c1_ctrl___start_stop___width 1 +#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 +#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 +#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 +#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 +#define reg_gio_rw_i2c1_ctrl___start_bit___width 1 +#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 +#define reg_gio_rw_i2c1_ctrl___freq___lsb 25 +#define reg_gio_rw_i2c1_ctrl___freq___width 2 +#define reg_gio_rw_i2c1_ctrl_offset 172 + +/* Register rw_i2c1_data, scope gio, type rw */ +#define reg_gio_rw_i2c1_data___data0___lsb 0 +#define reg_gio_rw_i2c1_data___data0___width 8 +#define reg_gio_rw_i2c1_data___data1___lsb 8 +#define reg_gio_rw_i2c1_data___data1___width 8 +#define reg_gio_rw_i2c1_data___data2___lsb 16 +#define reg_gio_rw_i2c1_data___data2___width 8 +#define reg_gio_rw_i2c1_data___data3___lsb 24 +#define reg_gio_rw_i2c1_data___data3___width 8 +#define reg_gio_rw_i2c1_data_offset 176 + +/* Register rw_i2c1_data2, scope gio, type rw */ +#define reg_gio_rw_i2c1_data2___data4___lsb 0 +#define reg_gio_rw_i2c1_data2___data4___width 8 +#define reg_gio_rw_i2c1_data2___data5___lsb 8 +#define reg_gio_rw_i2c1_data2___data5___width 8 +#define reg_gio_rw_i2c1_data2___start_val___lsb 16 +#define reg_gio_rw_i2c1_data2___start_val___width 6 +#define reg_gio_rw_i2c1_data2___ack_val___lsb 22 +#define reg_gio_rw_i2c1_data2___ack_val___width 6 +#define reg_gio_rw_i2c1_data2_offset 180 + +/* Register r_ppwm_stat, scope gio, type r */ +#define reg_gio_r_ppwm_stat___freq___lsb 0 +#define reg_gio_r_ppwm_stat___freq___width 2 +#define reg_gio_r_ppwm_stat_offset 184 + +/* Register rw_ppwm_data, scope gio, type rw */ +#define reg_gio_rw_ppwm_data___data___lsb 0 +#define reg_gio_rw_ppwm_data___data___width 8 +#define reg_gio_rw_ppwm_data_offset 188 + +/* Register rw_pwm0_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm0_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm0_ctrl___mode___width 2 +#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm0_ctrl_offset 192 + +/* Register rw_pwm0_var, scope gio, type rw */ +#define reg_gio_rw_pwm0_var___lo___lsb 0 +#define reg_gio_rw_pwm0_var___lo___width 13 +#define reg_gio_rw_pwm0_var___hi___lsb 13 +#define reg_gio_rw_pwm0_var___hi___width 13 +#define reg_gio_rw_pwm0_var_offset 196 + +/* Register rw_pwm0_data, scope gio, type rw */ +#define reg_gio_rw_pwm0_data___data___lsb 0 +#define reg_gio_rw_pwm0_data___data___width 8 +#define reg_gio_rw_pwm0_data_offset 200 + +/* Register rw_pwm1_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm1_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm1_ctrl___mode___width 2 +#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm1_ctrl_offset 204 + +/* Register rw_pwm1_var, scope gio, type rw */ +#define reg_gio_rw_pwm1_var___lo___lsb 0 +#define reg_gio_rw_pwm1_var___lo___width 13 +#define reg_gio_rw_pwm1_var___hi___lsb 13 +#define reg_gio_rw_pwm1_var___hi___width 13 +#define reg_gio_rw_pwm1_var_offset 208 + +/* Register rw_pwm1_data, scope gio, type rw */ +#define reg_gio_rw_pwm1_data___data___lsb 0 +#define reg_gio_rw_pwm1_data___data___width 8 +#define reg_gio_rw_pwm1_data_offset 212 + +/* Register rw_pwm2_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm2_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm2_ctrl___mode___width 2 +#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm2_ctrl_offset 216 + +/* Register rw_pwm2_var, scope gio, type rw */ +#define reg_gio_rw_pwm2_var___lo___lsb 0 +#define reg_gio_rw_pwm2_var___lo___width 13 +#define reg_gio_rw_pwm2_var___hi___lsb 13 +#define reg_gio_rw_pwm2_var___hi___width 13 +#define reg_gio_rw_pwm2_var_offset 220 + +/* Register rw_pwm2_data, scope gio, type rw */ +#define reg_gio_rw_pwm2_data___data___lsb 0 +#define reg_gio_rw_pwm2_data___data___width 8 +#define reg_gio_rw_pwm2_data_offset 224 + +/* Register rw_pwm_in_cfg, scope gio, type rw */ +#define reg_gio_rw_pwm_in_cfg___pin___lsb 0 +#define reg_gio_rw_pwm_in_cfg___pin___width 3 +#define reg_gio_rw_pwm_in_cfg_offset 228 + +/* Register r_pwm_in_lo, scope gio, type r */ +#define reg_gio_r_pwm_in_lo___data___lsb 0 +#define reg_gio_r_pwm_in_lo___data___width 32 +#define reg_gio_r_pwm_in_lo_offset 232 + +/* Register r_pwm_in_hi, scope gio, type r */ +#define reg_gio_r_pwm_in_hi___data___lsb 0 +#define reg_gio_r_pwm_in_hi___data___width 32 +#define reg_gio_r_pwm_in_hi_offset 236 + +/* Register r_pwm_in_cnt, scope gio, type r */ +#define reg_gio_r_pwm_in_cnt___data___lsb 0 +#define reg_gio_r_pwm_in_cnt___data___width 32 +#define reg_gio_r_pwm_in_cnt_offset 240 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_f100k 0x00000000 +#define regk_gio_f1562 0x00000000 +#define regk_gio_f195 0x00000003 +#define regk_gio_f1m 0x00000002 +#define regk_gio_f390 0x00000002 +#define regk_gio_f400k 0x00000001 +#define regk_gio_f5m 0x00000003 +#define regk_gio_f781 0x00000001 +#define regk_gio_hi 0x00000001 +#define regk_gio_in 0x00000000 +#define regk_gio_intr_pa0 0x00000000 +#define regk_gio_intr_pa1 0x00000000 +#define regk_gio_intr_pa10 0x00000001 +#define regk_gio_intr_pa11 0x00000001 +#define regk_gio_intr_pa12 0x00000001 +#define regk_gio_intr_pa13 0x00000001 +#define regk_gio_intr_pa14 0x00000001 +#define regk_gio_intr_pa15 0x00000001 +#define regk_gio_intr_pa16 0x00000002 +#define regk_gio_intr_pa17 0x00000002 +#define regk_gio_intr_pa18 0x00000002 +#define regk_gio_intr_pa19 0x00000002 +#define regk_gio_intr_pa2 0x00000000 +#define regk_gio_intr_pa20 0x00000002 +#define regk_gio_intr_pa21 0x00000002 +#define regk_gio_intr_pa22 0x00000002 +#define regk_gio_intr_pa23 0x00000002 +#define regk_gio_intr_pa24 0x00000003 +#define regk_gio_intr_pa25 0x00000003 +#define regk_gio_intr_pa26 0x00000003 +#define regk_gio_intr_pa27 0x00000003 +#define regk_gio_intr_pa28 0x00000003 +#define regk_gio_intr_pa29 0x00000003 +#define regk_gio_intr_pa3 0x00000000 +#define regk_gio_intr_pa30 0x00000003 +#define regk_gio_intr_pa31 0x00000003 +#define regk_gio_intr_pa4 0x00000000 +#define regk_gio_intr_pa5 0x00000000 +#define regk_gio_intr_pa6 0x00000000 +#define regk_gio_intr_pa7 0x00000000 +#define regk_gio_intr_pa8 0x00000001 +#define regk_gio_intr_pa9 0x00000001 +#define regk_gio_intr_pb0 0x00000004 +#define regk_gio_intr_pb1 0x00000004 +#define regk_gio_intr_pb10 0x00000005 +#define regk_gio_intr_pb11 0x00000005 +#define regk_gio_intr_pb12 0x00000005 +#define regk_gio_intr_pb13 0x00000005 +#define regk_gio_intr_pb14 0x00000005 +#define regk_gio_intr_pb15 0x00000005 +#define regk_gio_intr_pb16 0x00000006 +#define regk_gio_intr_pb17 0x00000006 +#define regk_gio_intr_pb18 0x00000006 +#define regk_gio_intr_pb19 0x00000006 +#define regk_gio_intr_pb2 0x00000004 +#define regk_gio_intr_pb20 0x00000006 +#define regk_gio_intr_pb21 0x00000006 +#define regk_gio_intr_pb22 0x00000006 +#define regk_gio_intr_pb23 0x00000006 +#define regk_gio_intr_pb24 0x00000007 +#define regk_gio_intr_pb25 0x00000007 +#define regk_gio_intr_pb26 0x00000007 +#define regk_gio_intr_pb27 0x00000007 +#define regk_gio_intr_pb28 0x00000007 +#define regk_gio_intr_pb29 0x00000007 +#define regk_gio_intr_pb3 0x00000004 +#define regk_gio_intr_pb30 0x00000007 +#define regk_gio_intr_pb31 0x00000007 +#define regk_gio_intr_pb4 0x00000004 +#define regk_gio_intr_pb5 0x00000004 +#define regk_gio_intr_pb6 0x00000004 +#define regk_gio_intr_pb7 0x00000004 +#define regk_gio_intr_pb8 0x00000005 +#define regk_gio_intr_pb9 0x00000005 +#define regk_gio_intr_pc0 0x00000008 +#define regk_gio_intr_pc1 0x00000008 +#define regk_gio_intr_pc10 0x00000009 +#define regk_gio_intr_pc11 0x00000009 +#define regk_gio_intr_pc12 0x00000009 +#define regk_gio_intr_pc13 0x00000009 +#define regk_gio_intr_pc14 0x00000009 +#define regk_gio_intr_pc15 0x00000009 +#define regk_gio_intr_pc2 0x00000008 +#define regk_gio_intr_pc3 0x00000008 +#define regk_gio_intr_pc4 0x00000008 +#define regk_gio_intr_pc5 0x00000008 +#define regk_gio_intr_pc6 0x00000008 +#define regk_gio_intr_pc7 0x00000008 +#define regk_gio_intr_pc8 0x00000009 +#define regk_gio_intr_pc9 0x00000009 +#define regk_gio_intr_pd0 0x0000000c +#define regk_gio_intr_pd1 0x0000000c +#define regk_gio_intr_pd10 0x0000000d +#define regk_gio_intr_pd11 0x0000000d +#define regk_gio_intr_pd12 0x0000000d +#define regk_gio_intr_pd13 0x0000000d +#define regk_gio_intr_pd14 0x0000000d +#define regk_gio_intr_pd15 0x0000000d +#define regk_gio_intr_pd16 0x0000000e +#define regk_gio_intr_pd17 0x0000000e +#define regk_gio_intr_pd18 0x0000000e +#define regk_gio_intr_pd19 0x0000000e +#define regk_gio_intr_pd2 0x0000000c +#define regk_gio_intr_pd20 0x0000000e +#define regk_gio_intr_pd21 0x0000000e +#define regk_gio_intr_pd22 0x0000000e +#define regk_gio_intr_pd23 0x0000000e +#define regk_gio_intr_pd24 0x0000000f +#define regk_gio_intr_pd25 0x0000000f +#define regk_gio_intr_pd26 0x0000000f +#define regk_gio_intr_pd27 0x0000000f +#define regk_gio_intr_pd28 0x0000000f +#define regk_gio_intr_pd29 0x0000000f +#define regk_gio_intr_pd3 0x0000000c +#define regk_gio_intr_pd30 0x0000000f +#define regk_gio_intr_pd31 0x0000000f +#define regk_gio_intr_pd4 0x0000000c +#define regk_gio_intr_pd5 0x0000000c +#define regk_gio_intr_pd6 0x0000000c +#define regk_gio_intr_pd7 0x0000000c +#define regk_gio_intr_pd8 0x0000000d +#define regk_gio_intr_pd9 0x0000000d +#define regk_gio_lo 0x00000002 +#define regk_gio_lsb 0x00000000 +#define regk_gio_msb 0x00000001 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_no_switch 0x0000003f +#define regk_gio_none 0x00000007 +#define regk_gio_off 0x00000000 +#define regk_gio_opendrain 0x00000000 +#define regk_gio_out 0x00000001 +#define regk_gio_posedge 0x00000005 +#define regk_gio_pwm_hfp 0x00000002 +#define regk_gio_pwm_pa0 0x00000001 +#define regk_gio_pwm_pa19 0x00000004 +#define regk_gio_pwm_pa6 0x00000002 +#define regk_gio_pwm_pa7 0x00000003 +#define regk_gio_pwm_pb26 0x00000005 +#define regk_gio_pwm_pd23 0x00000006 +#define regk_gio_pwm_pd31 0x00000007 +#define regk_gio_pwm_std 0x00000001 +#define regk_gio_pwm_var 0x00000003 +#define regk_gio_rw_i2c0_cfg_default 0x00000020 +#define regk_gio_rw_i2c0_ctrl_default 0x00010000 +#define regk_gio_rw_i2c0_start_default 0x00000000 +#define regk_gio_rw_i2c1_cfg_default 0x00000aa0 +#define regk_gio_rw_i2c1_ctrl_default 0x00010000 +#define regk_gio_rw_i2c1_start_default 0x00000000 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_ppwm_data_default 0x00000000 +#define regk_gio_rw_pwm0_ctrl_default 0x00000000 +#define regk_gio_rw_pwm1_ctrl_default 0x00000000 +#define regk_gio_rw_pwm2_ctrl_default 0x00000000 +#define regk_gio_rw_pwm_in_cfg_default 0x00000000 +#define regk_gio_sda0 0x00000000 +#define regk_gio_sda1 0x00000001 +#define regk_gio_sda2 0x00000002 +#define regk_gio_sda3 0x00000003 +#define regk_gio_sen 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000000..c3dc9c666c46 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,572 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: pinmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___eth___lsb 0 +#define reg_pinmux_rw_hwprot___eth___width 1 +#define reg_pinmux_rw_hwprot___eth___bit 0 +#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 +#define reg_pinmux_rw_hwprot___eth_mdio___width 1 +#define reg_pinmux_rw_hwprot___eth_mdio___bit 1 +#define reg_pinmux_rw_hwprot___geth___lsb 2 +#define reg_pinmux_rw_hwprot___geth___width 1 +#define reg_pinmux_rw_hwprot___geth___bit 2 +#define reg_pinmux_rw_hwprot___tg___lsb 3 +#define reg_pinmux_rw_hwprot___tg___width 1 +#define reg_pinmux_rw_hwprot___tg___bit 3 +#define reg_pinmux_rw_hwprot___tg_clk___lsb 4 +#define reg_pinmux_rw_hwprot___tg_clk___width 1 +#define reg_pinmux_rw_hwprot___tg_clk___bit 4 +#define reg_pinmux_rw_hwprot___vout___lsb 5 +#define reg_pinmux_rw_hwprot___vout___width 1 +#define reg_pinmux_rw_hwprot___vout___bit 5 +#define reg_pinmux_rw_hwprot___vout_sync___lsb 6 +#define reg_pinmux_rw_hwprot___vout_sync___width 1 +#define reg_pinmux_rw_hwprot___vout_sync___bit 6 +#define reg_pinmux_rw_hwprot___ser1___lsb 7 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 7 +#define reg_pinmux_rw_hwprot___ser2___lsb 8 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 8 +#define reg_pinmux_rw_hwprot___ser3___lsb 9 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 9 +#define reg_pinmux_rw_hwprot___ser4___lsb 10 +#define reg_pinmux_rw_hwprot___ser4___width 1 +#define reg_pinmux_rw_hwprot___ser4___bit 10 +#define reg_pinmux_rw_hwprot___sser___lsb 11 +#define reg_pinmux_rw_hwprot___sser___width 1 +#define reg_pinmux_rw_hwprot___sser___bit 11 +#define reg_pinmux_rw_hwprot___pwm0___lsb 12 +#define reg_pinmux_rw_hwprot___pwm0___width 1 +#define reg_pinmux_rw_hwprot___pwm0___bit 12 +#define reg_pinmux_rw_hwprot___pwm1___lsb 13 +#define reg_pinmux_rw_hwprot___pwm1___width 1 +#define reg_pinmux_rw_hwprot___pwm1___bit 13 +#define reg_pinmux_rw_hwprot___pwm2___lsb 14 +#define reg_pinmux_rw_hwprot___pwm2___width 1 +#define reg_pinmux_rw_hwprot___pwm2___bit 14 +#define reg_pinmux_rw_hwprot___timer0___lsb 15 +#define reg_pinmux_rw_hwprot___timer0___width 1 +#define reg_pinmux_rw_hwprot___timer0___bit 15 +#define reg_pinmux_rw_hwprot___timer1___lsb 16 +#define reg_pinmux_rw_hwprot___timer1___width 1 +#define reg_pinmux_rw_hwprot___timer1___bit 16 +#define reg_pinmux_rw_hwprot___pio___lsb 17 +#define reg_pinmux_rw_hwprot___pio___width 1 +#define reg_pinmux_rw_hwprot___pio___bit 17 +#define reg_pinmux_rw_hwprot___i2c0___lsb 18 +#define reg_pinmux_rw_hwprot___i2c0___width 1 +#define reg_pinmux_rw_hwprot___i2c0___bit 18 +#define reg_pinmux_rw_hwprot___i2c1___lsb 19 +#define reg_pinmux_rw_hwprot___i2c1___width 1 +#define reg_pinmux_rw_hwprot___i2c1___bit 19 +#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 +#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 +#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 +#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 +#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 +#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 +#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 +#define reg_pinmux_rw_hwprot___i2c1_sen___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 +#define reg_pinmux_rw_hwprot_offset 0 + +/* Register rw_gio_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pa___pa0___lsb 0 +#define reg_pinmux_rw_gio_pa___pa0___width 1 +#define reg_pinmux_rw_gio_pa___pa0___bit 0 +#define reg_pinmux_rw_gio_pa___pa1___lsb 1 +#define reg_pinmux_rw_gio_pa___pa1___width 1 +#define reg_pinmux_rw_gio_pa___pa1___bit 1 +#define reg_pinmux_rw_gio_pa___pa2___lsb 2 +#define reg_pinmux_rw_gio_pa___pa2___width 1 +#define reg_pinmux_rw_gio_pa___pa2___bit 2 +#define reg_pinmux_rw_gio_pa___pa3___lsb 3 +#define reg_pinmux_rw_gio_pa___pa3___width 1 +#define reg_pinmux_rw_gio_pa___pa3___bit 3 +#define reg_pinmux_rw_gio_pa___pa4___lsb 4 +#define reg_pinmux_rw_gio_pa___pa4___width 1 +#define reg_pinmux_rw_gio_pa___pa4___bit 4 +#define reg_pinmux_rw_gio_pa___pa5___lsb 5 +#define reg_pinmux_rw_gio_pa___pa5___width 1 +#define reg_pinmux_rw_gio_pa___pa5___bit 5 +#define reg_pinmux_rw_gio_pa___pa6___lsb 6 +#define reg_pinmux_rw_gio_pa___pa6___width 1 +#define reg_pinmux_rw_gio_pa___pa6___bit 6 +#define reg_pinmux_rw_gio_pa___pa7___lsb 7 +#define reg_pinmux_rw_gio_pa___pa7___width 1 +#define reg_pinmux_rw_gio_pa___pa7___bit 7 +#define reg_pinmux_rw_gio_pa___pa8___lsb 8 +#define reg_pinmux_rw_gio_pa___pa8___width 1 +#define reg_pinmux_rw_gio_pa___pa8___bit 8 +#define reg_pinmux_rw_gio_pa___pa9___lsb 9 +#define reg_pinmux_rw_gio_pa___pa9___width 1 +#define reg_pinmux_rw_gio_pa___pa9___bit 9 +#define reg_pinmux_rw_gio_pa___pa10___lsb 10 +#define reg_pinmux_rw_gio_pa___pa10___width 1 +#define reg_pinmux_rw_gio_pa___pa10___bit 10 +#define reg_pinmux_rw_gio_pa___pa11___lsb 11 +#define reg_pinmux_rw_gio_pa___pa11___width 1 +#define reg_pinmux_rw_gio_pa___pa11___bit 11 +#define reg_pinmux_rw_gio_pa___pa12___lsb 12 +#define reg_pinmux_rw_gio_pa___pa12___width 1 +#define reg_pinmux_rw_gio_pa___pa12___bit 12 +#define reg_pinmux_rw_gio_pa___pa13___lsb 13 +#define reg_pinmux_rw_gio_pa___pa13___width 1 +#define reg_pinmux_rw_gio_pa___pa13___bit 13 +#define reg_pinmux_rw_gio_pa___pa14___lsb 14 +#define reg_pinmux_rw_gio_pa___pa14___width 1 +#define reg_pinmux_rw_gio_pa___pa14___bit 14 +#define reg_pinmux_rw_gio_pa___pa15___lsb 15 +#define reg_pinmux_rw_gio_pa___pa15___width 1 +#define reg_pinmux_rw_gio_pa___pa15___bit 15 +#define reg_pinmux_rw_gio_pa___pa16___lsb 16 +#define reg_pinmux_rw_gio_pa___pa16___width 1 +#define reg_pinmux_rw_gio_pa___pa16___bit 16 +#define reg_pinmux_rw_gio_pa___pa17___lsb 17 +#define reg_pinmux_rw_gio_pa___pa17___width 1 +#define reg_pinmux_rw_gio_pa___pa17___bit 17 +#define reg_pinmux_rw_gio_pa___pa18___lsb 18 +#define reg_pinmux_rw_gio_pa___pa18___width 1 +#define reg_pinmux_rw_gio_pa___pa18___bit 18 +#define reg_pinmux_rw_gio_pa___pa19___lsb 19 +#define reg_pinmux_rw_gio_pa___pa19___width 1 +#define reg_pinmux_rw_gio_pa___pa19___bit 19 +#define reg_pinmux_rw_gio_pa___pa20___lsb 20 +#define reg_pinmux_rw_gio_pa___pa20___width 1 +#define reg_pinmux_rw_gio_pa___pa20___bit 20 +#define reg_pinmux_rw_gio_pa___pa21___lsb 21 +#define reg_pinmux_rw_gio_pa___pa21___width 1 +#define reg_pinmux_rw_gio_pa___pa21___bit 21 +#define reg_pinmux_rw_gio_pa___pa22___lsb 22 +#define reg_pinmux_rw_gio_pa___pa22___width 1 +#define reg_pinmux_rw_gio_pa___pa22___bit 22 +#define reg_pinmux_rw_gio_pa___pa23___lsb 23 +#define reg_pinmux_rw_gio_pa___pa23___width 1 +#define reg_pinmux_rw_gio_pa___pa23___bit 23 +#define reg_pinmux_rw_gio_pa___pa24___lsb 24 +#define reg_pinmux_rw_gio_pa___pa24___width 1 +#define reg_pinmux_rw_gio_pa___pa24___bit 24 +#define reg_pinmux_rw_gio_pa___pa25___lsb 25 +#define reg_pinmux_rw_gio_pa___pa25___width 1 +#define reg_pinmux_rw_gio_pa___pa25___bit 25 +#define reg_pinmux_rw_gio_pa___pa26___lsb 26 +#define reg_pinmux_rw_gio_pa___pa26___width 1 +#define reg_pinmux_rw_gio_pa___pa26___bit 26 +#define reg_pinmux_rw_gio_pa___pa27___lsb 27 +#define reg_pinmux_rw_gio_pa___pa27___width 1 +#define reg_pinmux_rw_gio_pa___pa27___bit 27 +#define reg_pinmux_rw_gio_pa___pa28___lsb 28 +#define reg_pinmux_rw_gio_pa___pa28___width 1 +#define reg_pinmux_rw_gio_pa___pa28___bit 28 +#define reg_pinmux_rw_gio_pa___pa29___lsb 29 +#define reg_pinmux_rw_gio_pa___pa29___width 1 +#define reg_pinmux_rw_gio_pa___pa29___bit 29 +#define reg_pinmux_rw_gio_pa___pa30___lsb 30 +#define reg_pinmux_rw_gio_pa___pa30___width 1 +#define reg_pinmux_rw_gio_pa___pa30___bit 30 +#define reg_pinmux_rw_gio_pa___pa31___lsb 31 +#define reg_pinmux_rw_gio_pa___pa31___width 1 +#define reg_pinmux_rw_gio_pa___pa31___bit 31 +#define reg_pinmux_rw_gio_pa_offset 4 + +/* Register rw_gio_pb, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pb___pb0___lsb 0 +#define reg_pinmux_rw_gio_pb___pb0___width 1 +#define reg_pinmux_rw_gio_pb___pb0___bit 0 +#define reg_pinmux_rw_gio_pb___pb1___lsb 1 +#define reg_pinmux_rw_gio_pb___pb1___width 1 +#define reg_pinmux_rw_gio_pb___pb1___bit 1 +#define reg_pinmux_rw_gio_pb___pb2___lsb 2 +#define reg_pinmux_rw_gio_pb___pb2___width 1 +#define reg_pinmux_rw_gio_pb___pb2___bit 2 +#define reg_pinmux_rw_gio_pb___pb3___lsb 3 +#define reg_pinmux_rw_gio_pb___pb3___width 1 +#define reg_pinmux_rw_gio_pb___pb3___bit 3 +#define reg_pinmux_rw_gio_pb___pb4___lsb 4 +#define reg_pinmux_rw_gio_pb___pb4___width 1 +#define reg_pinmux_rw_gio_pb___pb4___bit 4 +#define reg_pinmux_rw_gio_pb___pb5___lsb 5 +#define reg_pinmux_rw_gio_pb___pb5___width 1 +#define reg_pinmux_rw_gio_pb___pb5___bit 5 +#define reg_pinmux_rw_gio_pb___pb6___lsb 6 +#define reg_pinmux_rw_gio_pb___pb6___width 1 +#define reg_pinmux_rw_gio_pb___pb6___bit 6 +#define reg_pinmux_rw_gio_pb___pb7___lsb 7 +#define reg_pinmux_rw_gio_pb___pb7___width 1 +#define reg_pinmux_rw_gio_pb___pb7___bit 7 +#define reg_pinmux_rw_gio_pb___pb8___lsb 8 +#define reg_pinmux_rw_gio_pb___pb8___width 1 +#define reg_pinmux_rw_gio_pb___pb8___bit 8 +#define reg_pinmux_rw_gio_pb___pb9___lsb 9 +#define reg_pinmux_rw_gio_pb___pb9___width 1 +#define reg_pinmux_rw_gio_pb___pb9___bit 9 +#define reg_pinmux_rw_gio_pb___pb10___lsb 10 +#define reg_pinmux_rw_gio_pb___pb10___width 1 +#define reg_pinmux_rw_gio_pb___pb10___bit 10 +#define reg_pinmux_rw_gio_pb___pb11___lsb 11 +#define reg_pinmux_rw_gio_pb___pb11___width 1 +#define reg_pinmux_rw_gio_pb___pb11___bit 11 +#define reg_pinmux_rw_gio_pb___pb12___lsb 12 +#define reg_pinmux_rw_gio_pb___pb12___width 1 +#define reg_pinmux_rw_gio_pb___pb12___bit 12 +#define reg_pinmux_rw_gio_pb___pb13___lsb 13 +#define reg_pinmux_rw_gio_pb___pb13___width 1 +#define reg_pinmux_rw_gio_pb___pb13___bit 13 +#define reg_pinmux_rw_gio_pb___pb14___lsb 14 +#define reg_pinmux_rw_gio_pb___pb14___width 1 +#define reg_pinmux_rw_gio_pb___pb14___bit 14 +#define reg_pinmux_rw_gio_pb___pb15___lsb 15 +#define reg_pinmux_rw_gio_pb___pb15___width 1 +#define reg_pinmux_rw_gio_pb___pb15___bit 15 +#define reg_pinmux_rw_gio_pb___pb16___lsb 16 +#define reg_pinmux_rw_gio_pb___pb16___width 1 +#define reg_pinmux_rw_gio_pb___pb16___bit 16 +#define reg_pinmux_rw_gio_pb___pb17___lsb 17 +#define reg_pinmux_rw_gio_pb___pb17___width 1 +#define reg_pinmux_rw_gio_pb___pb17___bit 17 +#define reg_pinmux_rw_gio_pb___pb18___lsb 18 +#define reg_pinmux_rw_gio_pb___pb18___width 1 +#define reg_pinmux_rw_gio_pb___pb18___bit 18 +#define reg_pinmux_rw_gio_pb___pb19___lsb 19 +#define reg_pinmux_rw_gio_pb___pb19___width 1 +#define reg_pinmux_rw_gio_pb___pb19___bit 19 +#define reg_pinmux_rw_gio_pb___pb20___lsb 20 +#define reg_pinmux_rw_gio_pb___pb20___width 1 +#define reg_pinmux_rw_gio_pb___pb20___bit 20 +#define reg_pinmux_rw_gio_pb___pb21___lsb 21 +#define reg_pinmux_rw_gio_pb___pb21___width 1 +#define reg_pinmux_rw_gio_pb___pb21___bit 21 +#define reg_pinmux_rw_gio_pb___pb22___lsb 22 +#define reg_pinmux_rw_gio_pb___pb22___width 1 +#define reg_pinmux_rw_gio_pb___pb22___bit 22 +#define reg_pinmux_rw_gio_pb___pb23___lsb 23 +#define reg_pinmux_rw_gio_pb___pb23___width 1 +#define reg_pinmux_rw_gio_pb___pb23___bit 23 +#define reg_pinmux_rw_gio_pb___pb24___lsb 24 +#define reg_pinmux_rw_gio_pb___pb24___width 1 +#define reg_pinmux_rw_gio_pb___pb24___bit 24 +#define reg_pinmux_rw_gio_pb___pb25___lsb 25 +#define reg_pinmux_rw_gio_pb___pb25___width 1 +#define reg_pinmux_rw_gio_pb___pb25___bit 25 +#define reg_pinmux_rw_gio_pb___pb26___lsb 26 +#define reg_pinmux_rw_gio_pb___pb26___width 1 +#define reg_pinmux_rw_gio_pb___pb26___bit 26 +#define reg_pinmux_rw_gio_pb___pb27___lsb 27 +#define reg_pinmux_rw_gio_pb___pb27___width 1 +#define reg_pinmux_rw_gio_pb___pb27___bit 27 +#define reg_pinmux_rw_gio_pb___pb28___lsb 28 +#define reg_pinmux_rw_gio_pb___pb28___width 1 +#define reg_pinmux_rw_gio_pb___pb28___bit 28 +#define reg_pinmux_rw_gio_pb___pb29___lsb 29 +#define reg_pinmux_rw_gio_pb___pb29___width 1 +#define reg_pinmux_rw_gio_pb___pb29___bit 29 +#define reg_pinmux_rw_gio_pb___pb30___lsb 30 +#define reg_pinmux_rw_gio_pb___pb30___width 1 +#define reg_pinmux_rw_gio_pb___pb30___bit 30 +#define reg_pinmux_rw_gio_pb___pb31___lsb 31 +#define reg_pinmux_rw_gio_pb___pb31___width 1 +#define reg_pinmux_rw_gio_pb___pb31___bit 31 +#define reg_pinmux_rw_gio_pb_offset 8 + +/* Register rw_gio_pc, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pc___pc0___lsb 0 +#define reg_pinmux_rw_gio_pc___pc0___width 1 +#define reg_pinmux_rw_gio_pc___pc0___bit 0 +#define reg_pinmux_rw_gio_pc___pc1___lsb 1 +#define reg_pinmux_rw_gio_pc___pc1___width 1 +#define reg_pinmux_rw_gio_pc___pc1___bit 1 +#define reg_pinmux_rw_gio_pc___pc2___lsb 2 +#define reg_pinmux_rw_gio_pc___pc2___width 1 +#define reg_pinmux_rw_gio_pc___pc2___bit 2 +#define reg_pinmux_rw_gio_pc___pc3___lsb 3 +#define reg_pinmux_rw_gio_pc___pc3___width 1 +#define reg_pinmux_rw_gio_pc___pc3___bit 3 +#define reg_pinmux_rw_gio_pc___pc4___lsb 4 +#define reg_pinmux_rw_gio_pc___pc4___width 1 +#define reg_pinmux_rw_gio_pc___pc4___bit 4 +#define reg_pinmux_rw_gio_pc___pc5___lsb 5 +#define reg_pinmux_rw_gio_pc___pc5___width 1 +#define reg_pinmux_rw_gio_pc___pc5___bit 5 +#define reg_pinmux_rw_gio_pc___pc6___lsb 6 +#define reg_pinmux_rw_gio_pc___pc6___width 1 +#define reg_pinmux_rw_gio_pc___pc6___bit 6 +#define reg_pinmux_rw_gio_pc___pc7___lsb 7 +#define reg_pinmux_rw_gio_pc___pc7___width 1 +#define reg_pinmux_rw_gio_pc___pc7___bit 7 +#define reg_pinmux_rw_gio_pc___pc8___lsb 8 +#define reg_pinmux_rw_gio_pc___pc8___width 1 +#define reg_pinmux_rw_gio_pc___pc8___bit 8 +#define reg_pinmux_rw_gio_pc___pc9___lsb 9 +#define reg_pinmux_rw_gio_pc___pc9___width 1 +#define reg_pinmux_rw_gio_pc___pc9___bit 9 +#define reg_pinmux_rw_gio_pc___pc10___lsb 10 +#define reg_pinmux_rw_gio_pc___pc10___width 1 +#define reg_pinmux_rw_gio_pc___pc10___bit 10 +#define reg_pinmux_rw_gio_pc___pc11___lsb 11 +#define reg_pinmux_rw_gio_pc___pc11___width 1 +#define reg_pinmux_rw_gio_pc___pc11___bit 11 +#define reg_pinmux_rw_gio_pc___pc12___lsb 12 +#define reg_pinmux_rw_gio_pc___pc12___width 1 +#define reg_pinmux_rw_gio_pc___pc12___bit 12 +#define reg_pinmux_rw_gio_pc___pc13___lsb 13 +#define reg_pinmux_rw_gio_pc___pc13___width 1 +#define reg_pinmux_rw_gio_pc___pc13___bit 13 +#define reg_pinmux_rw_gio_pc___pc14___lsb 14 +#define reg_pinmux_rw_gio_pc___pc14___width 1 +#define reg_pinmux_rw_gio_pc___pc14___bit 14 +#define reg_pinmux_rw_gio_pc___pc15___lsb 15 +#define reg_pinmux_rw_gio_pc___pc15___width 1 +#define reg_pinmux_rw_gio_pc___pc15___bit 15 +#define reg_pinmux_rw_gio_pc_offset 12 + +/* Register rw_iop_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pa___pa0___lsb 0 +#define reg_pinmux_rw_iop_pa___pa0___width 1 +#define reg_pinmux_rw_iop_pa___pa0___bit 0 +#define reg_pinmux_rw_iop_pa___pa1___lsb 1 +#define reg_pinmux_rw_iop_pa___pa1___width 1 +#define reg_pinmux_rw_iop_pa___pa1___bit 1 +#define reg_pinmux_rw_iop_pa___pa2___lsb 2 +#define reg_pinmux_rw_iop_pa___pa2___width 1 +#define reg_pinmux_rw_iop_pa___pa2___bit 2 +#define reg_pinmux_rw_iop_pa___pa3___lsb 3 +#define reg_pinmux_rw_iop_pa___pa3___width 1 +#define reg_pinmux_rw_iop_pa___pa3___bit 3 +#define reg_pinmux_rw_iop_pa___pa4___lsb 4 +#define reg_pinmux_rw_iop_pa___pa4___width 1 +#define reg_pinmux_rw_iop_pa___pa4___bit 4 +#define reg_pinmux_rw_iop_pa___pa5___lsb 5 +#define reg_pinmux_rw_iop_pa___pa5___width 1 +#define reg_pinmux_rw_iop_pa___pa5___bit 5 +#define reg_pinmux_rw_iop_pa___pa6___lsb 6 +#define reg_pinmux_rw_iop_pa___pa6___width 1 +#define reg_pinmux_rw_iop_pa___pa6___bit 6 +#define reg_pinmux_rw_iop_pa___pa7___lsb 7 +#define reg_pinmux_rw_iop_pa___pa7___width 1 +#define reg_pinmux_rw_iop_pa___pa7___bit 7 +#define reg_pinmux_rw_iop_pa___pa8___lsb 8 +#define reg_pinmux_rw_iop_pa___pa8___width 1 +#define reg_pinmux_rw_iop_pa___pa8___bit 8 +#define reg_pinmux_rw_iop_pa___pa9___lsb 9 +#define reg_pinmux_rw_iop_pa___pa9___width 1 +#define reg_pinmux_rw_iop_pa___pa9___bit 9 +#define reg_pinmux_rw_iop_pa___pa10___lsb 10 +#define reg_pinmux_rw_iop_pa___pa10___width 1 +#define reg_pinmux_rw_iop_pa___pa10___bit 10 +#define reg_pinmux_rw_iop_pa___pa11___lsb 11 +#define reg_pinmux_rw_iop_pa___pa11___width 1 +#define reg_pinmux_rw_iop_pa___pa11___bit 11 +#define reg_pinmux_rw_iop_pa___pa12___lsb 12 +#define reg_pinmux_rw_iop_pa___pa12___width 1 +#define reg_pinmux_rw_iop_pa___pa12___bit 12 +#define reg_pinmux_rw_iop_pa___pa13___lsb 13 +#define reg_pinmux_rw_iop_pa___pa13___width 1 +#define reg_pinmux_rw_iop_pa___pa13___bit 13 +#define reg_pinmux_rw_iop_pa___pa14___lsb 14 +#define reg_pinmux_rw_iop_pa___pa14___width 1 +#define reg_pinmux_rw_iop_pa___pa14___bit 14 +#define reg_pinmux_rw_iop_pa___pa15___lsb 15 +#define reg_pinmux_rw_iop_pa___pa15___width 1 +#define reg_pinmux_rw_iop_pa___pa15___bit 15 +#define reg_pinmux_rw_iop_pa___pa16___lsb 16 +#define reg_pinmux_rw_iop_pa___pa16___width 1 +#define reg_pinmux_rw_iop_pa___pa16___bit 16 +#define reg_pinmux_rw_iop_pa___pa17___lsb 17 +#define reg_pinmux_rw_iop_pa___pa17___width 1 +#define reg_pinmux_rw_iop_pa___pa17___bit 17 +#define reg_pinmux_rw_iop_pa___pa18___lsb 18 +#define reg_pinmux_rw_iop_pa___pa18___width 1 +#define reg_pinmux_rw_iop_pa___pa18___bit 18 +#define reg_pinmux_rw_iop_pa___pa19___lsb 19 +#define reg_pinmux_rw_iop_pa___pa19___width 1 +#define reg_pinmux_rw_iop_pa___pa19___bit 19 +#define reg_pinmux_rw_iop_pa___pa20___lsb 20 +#define reg_pinmux_rw_iop_pa___pa20___width 1 +#define reg_pinmux_rw_iop_pa___pa20___bit 20 +#define reg_pinmux_rw_iop_pa___pa21___lsb 21 +#define reg_pinmux_rw_iop_pa___pa21___width 1 +#define reg_pinmux_rw_iop_pa___pa21___bit 21 +#define reg_pinmux_rw_iop_pa___pa22___lsb 22 +#define reg_pinmux_rw_iop_pa___pa22___width 1 +#define reg_pinmux_rw_iop_pa___pa22___bit 22 +#define reg_pinmux_rw_iop_pa___pa23___lsb 23 +#define reg_pinmux_rw_iop_pa___pa23___width 1 +#define reg_pinmux_rw_iop_pa___pa23___bit 23 +#define reg_pinmux_rw_iop_pa___pa24___lsb 24 +#define reg_pinmux_rw_iop_pa___pa24___width 1 +#define reg_pinmux_rw_iop_pa___pa24___bit 24 +#define reg_pinmux_rw_iop_pa___pa25___lsb 25 +#define reg_pinmux_rw_iop_pa___pa25___width 1 +#define reg_pinmux_rw_iop_pa___pa25___bit 25 +#define reg_pinmux_rw_iop_pa___pa26___lsb 26 +#define reg_pinmux_rw_iop_pa___pa26___width 1 +#define reg_pinmux_rw_iop_pa___pa26___bit 26 +#define reg_pinmux_rw_iop_pa___pa27___lsb 27 +#define reg_pinmux_rw_iop_pa___pa27___width 1 +#define reg_pinmux_rw_iop_pa___pa27___bit 27 +#define reg_pinmux_rw_iop_pa___pa28___lsb 28 +#define reg_pinmux_rw_iop_pa___pa28___width 1 +#define reg_pinmux_rw_iop_pa___pa28___bit 28 +#define reg_pinmux_rw_iop_pa___pa29___lsb 29 +#define reg_pinmux_rw_iop_pa___pa29___width 1 +#define reg_pinmux_rw_iop_pa___pa29___bit 29 +#define reg_pinmux_rw_iop_pa___pa30___lsb 30 +#define reg_pinmux_rw_iop_pa___pa30___width 1 +#define reg_pinmux_rw_iop_pa___pa30___bit 30 +#define reg_pinmux_rw_iop_pa___pa31___lsb 31 +#define reg_pinmux_rw_iop_pa___pa31___width 1 +#define reg_pinmux_rw_iop_pa___pa31___bit 31 +#define reg_pinmux_rw_iop_pa_offset 16 + +/* Register rw_iop_pb, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pb___pb0___lsb 0 +#define reg_pinmux_rw_iop_pb___pb0___width 1 +#define reg_pinmux_rw_iop_pb___pb0___bit 0 +#define reg_pinmux_rw_iop_pb___pb1___lsb 1 +#define reg_pinmux_rw_iop_pb___pb1___width 1 +#define reg_pinmux_rw_iop_pb___pb1___bit 1 +#define reg_pinmux_rw_iop_pb___pb2___lsb 2 +#define reg_pinmux_rw_iop_pb___pb2___width 1 +#define reg_pinmux_rw_iop_pb___pb2___bit 2 +#define reg_pinmux_rw_iop_pb___pb3___lsb 3 +#define reg_pinmux_rw_iop_pb___pb3___width 1 +#define reg_pinmux_rw_iop_pb___pb3___bit 3 +#define reg_pinmux_rw_iop_pb___pb4___lsb 4 +#define reg_pinmux_rw_iop_pb___pb4___width 1 +#define reg_pinmux_rw_iop_pb___pb4___bit 4 +#define reg_pinmux_rw_iop_pb___pb5___lsb 5 +#define reg_pinmux_rw_iop_pb___pb5___width 1 +#define reg_pinmux_rw_iop_pb___pb5___bit 5 +#define reg_pinmux_rw_iop_pb___pb6___lsb 6 +#define reg_pinmux_rw_iop_pb___pb6___width 1 +#define reg_pinmux_rw_iop_pb___pb6___bit 6 +#define reg_pinmux_rw_iop_pb___pb7___lsb 7 +#define reg_pinmux_rw_iop_pb___pb7___width 1 +#define reg_pinmux_rw_iop_pb___pb7___bit 7 +#define reg_pinmux_rw_iop_pb_offset 20 + +/* Register rw_iop_pio, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pio___d0___lsb 0 +#define reg_pinmux_rw_iop_pio___d0___width 1 +#define reg_pinmux_rw_iop_pio___d0___bit 0 +#define reg_pinmux_rw_iop_pio___d1___lsb 1 +#define reg_pinmux_rw_iop_pio___d1___width 1 +#define reg_pinmux_rw_iop_pio___d1___bit 1 +#define reg_pinmux_rw_iop_pio___d2___lsb 2 +#define reg_pinmux_rw_iop_pio___d2___width 1 +#define reg_pinmux_rw_iop_pio___d2___bit 2 +#define reg_pinmux_rw_iop_pio___d3___lsb 3 +#define reg_pinmux_rw_iop_pio___d3___width 1 +#define reg_pinmux_rw_iop_pio___d3___bit 3 +#define reg_pinmux_rw_iop_pio___d4___lsb 4 +#define reg_pinmux_rw_iop_pio___d4___width 1 +#define reg_pinmux_rw_iop_pio___d4___bit 4 +#define reg_pinmux_rw_iop_pio___d5___lsb 5 +#define reg_pinmux_rw_iop_pio___d5___width 1 +#define reg_pinmux_rw_iop_pio___d5___bit 5 +#define reg_pinmux_rw_iop_pio___d6___lsb 6 +#define reg_pinmux_rw_iop_pio___d6___width 1 +#define reg_pinmux_rw_iop_pio___d6___bit 6 +#define reg_pinmux_rw_iop_pio___d7___lsb 7 +#define reg_pinmux_rw_iop_pio___d7___width 1 +#define reg_pinmux_rw_iop_pio___d7___bit 7 +#define reg_pinmux_rw_iop_pio___rd_n___lsb 8 +#define reg_pinmux_rw_iop_pio___rd_n___width 1 +#define reg_pinmux_rw_iop_pio___rd_n___bit 8 +#define reg_pinmux_rw_iop_pio___wr_n___lsb 9 +#define reg_pinmux_rw_iop_pio___wr_n___width 1 +#define reg_pinmux_rw_iop_pio___wr_n___bit 9 +#define reg_pinmux_rw_iop_pio___a0___lsb 10 +#define reg_pinmux_rw_iop_pio___a0___width 1 +#define reg_pinmux_rw_iop_pio___a0___bit 10 +#define reg_pinmux_rw_iop_pio___a1___lsb 11 +#define reg_pinmux_rw_iop_pio___a1___width 1 +#define reg_pinmux_rw_iop_pio___a1___bit 11 +#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 +#define reg_pinmux_rw_iop_pio___ce0_n___width 1 +#define reg_pinmux_rw_iop_pio___ce0_n___bit 12 +#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 +#define reg_pinmux_rw_iop_pio___ce1_n___width 1 +#define reg_pinmux_rw_iop_pio___ce1_n___bit 13 +#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 +#define reg_pinmux_rw_iop_pio___ce2_n___width 1 +#define reg_pinmux_rw_iop_pio___ce2_n___bit 14 +#define reg_pinmux_rw_iop_pio___rdy___lsb 15 +#define reg_pinmux_rw_iop_pio___rdy___width 1 +#define reg_pinmux_rw_iop_pio___rdy___bit 15 +#define reg_pinmux_rw_iop_pio_offset 24 + +/* Register rw_iop_usb, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_usb___usb0___lsb 0 +#define reg_pinmux_rw_iop_usb___usb0___width 1 +#define reg_pinmux_rw_iop_usb___usb0___bit 0 +#define reg_pinmux_rw_iop_usb_offset 28 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_gio_pa_default 0x00000000 +#define regk_pinmux_rw_gio_pb_default 0x00000000 +#define regk_pinmux_rw_gio_pc_default 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_iop_pa_default 0x00000000 +#define regk_pinmux_rw_iop_pb_default 0x00000000 +#define regk_pinmux_rw_iop_pio_default 0x00000000 +#define regk_pinmux_rw_iop_usb_default 0x00000001 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h new file mode 100644 index 000000000000..3907ef4921c8 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h @@ -0,0 +1,337 @@ +#ifndef __pio_defs_asm_h +#define __pio_defs_asm_h + +/* + * This file is autogenerated from + * file: pio.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_data, scope pio, type rw */ +#define reg_pio_rw_data_offset 64 + +/* Register rw_io_access0, scope pio, type rw */ +#define reg_pio_rw_io_access0___data___lsb 0 +#define reg_pio_rw_io_access0___data___width 8 +#define reg_pio_rw_io_access0_offset 0 + +/* Register rw_io_access1, scope pio, type rw */ +#define reg_pio_rw_io_access1___data___lsb 0 +#define reg_pio_rw_io_access1___data___width 8 +#define reg_pio_rw_io_access1_offset 4 + +/* Register rw_io_access2, scope pio, type rw */ +#define reg_pio_rw_io_access2___data___lsb 0 +#define reg_pio_rw_io_access2___data___width 8 +#define reg_pio_rw_io_access2_offset 8 + +/* Register rw_io_access3, scope pio, type rw */ +#define reg_pio_rw_io_access3___data___lsb 0 +#define reg_pio_rw_io_access3___data___width 8 +#define reg_pio_rw_io_access3_offset 12 + +/* Register rw_io_access4, scope pio, type rw */ +#define reg_pio_rw_io_access4___data___lsb 0 +#define reg_pio_rw_io_access4___data___width 8 +#define reg_pio_rw_io_access4_offset 16 + +/* Register rw_io_access5, scope pio, type rw */ +#define reg_pio_rw_io_access5___data___lsb 0 +#define reg_pio_rw_io_access5___data___width 8 +#define reg_pio_rw_io_access5_offset 20 + +/* Register rw_io_access6, scope pio, type rw */ +#define reg_pio_rw_io_access6___data___lsb 0 +#define reg_pio_rw_io_access6___data___width 8 +#define reg_pio_rw_io_access6_offset 24 + +/* Register rw_io_access7, scope pio, type rw */ +#define reg_pio_rw_io_access7___data___lsb 0 +#define reg_pio_rw_io_access7___data___width 8 +#define reg_pio_rw_io_access7_offset 28 + +/* Register rw_io_access8, scope pio, type rw */ +#define reg_pio_rw_io_access8___data___lsb 0 +#define reg_pio_rw_io_access8___data___width 8 +#define reg_pio_rw_io_access8_offset 32 + +/* Register rw_io_access9, scope pio, type rw */ +#define reg_pio_rw_io_access9___data___lsb 0 +#define reg_pio_rw_io_access9___data___width 8 +#define reg_pio_rw_io_access9_offset 36 + +/* Register rw_io_access10, scope pio, type rw */ +#define reg_pio_rw_io_access10___data___lsb 0 +#define reg_pio_rw_io_access10___data___width 8 +#define reg_pio_rw_io_access10_offset 40 + +/* Register rw_io_access11, scope pio, type rw */ +#define reg_pio_rw_io_access11___data___lsb 0 +#define reg_pio_rw_io_access11___data___width 8 +#define reg_pio_rw_io_access11_offset 44 + +/* Register rw_io_access12, scope pio, type rw */ +#define reg_pio_rw_io_access12___data___lsb 0 +#define reg_pio_rw_io_access12___data___width 8 +#define reg_pio_rw_io_access12_offset 48 + +/* Register rw_io_access13, scope pio, type rw */ +#define reg_pio_rw_io_access13___data___lsb 0 +#define reg_pio_rw_io_access13___data___width 8 +#define reg_pio_rw_io_access13_offset 52 + +/* Register rw_io_access14, scope pio, type rw */ +#define reg_pio_rw_io_access14___data___lsb 0 +#define reg_pio_rw_io_access14___data___width 8 +#define reg_pio_rw_io_access14_offset 56 + +/* Register rw_io_access15, scope pio, type rw */ +#define reg_pio_rw_io_access15___data___lsb 0 +#define reg_pio_rw_io_access15___data___width 8 +#define reg_pio_rw_io_access15_offset 60 + +/* Register rw_ce0_cfg, scope pio, type rw */ +#define reg_pio_rw_ce0_cfg___lw___lsb 0 +#define reg_pio_rw_ce0_cfg___lw___width 6 +#define reg_pio_rw_ce0_cfg___ew___lsb 6 +#define reg_pio_rw_ce0_cfg___ew___width 3 +#define reg_pio_rw_ce0_cfg___zw___lsb 9 +#define reg_pio_rw_ce0_cfg___zw___width 3 +#define reg_pio_rw_ce0_cfg___aw___lsb 12 +#define reg_pio_rw_ce0_cfg___aw___width 2 +#define reg_pio_rw_ce0_cfg___mode___lsb 14 +#define reg_pio_rw_ce0_cfg___mode___width 2 +#define reg_pio_rw_ce0_cfg_offset 68 + +/* Register rw_ce1_cfg, scope pio, type rw */ +#define reg_pio_rw_ce1_cfg___lw___lsb 0 +#define reg_pio_rw_ce1_cfg___lw___width 6 +#define reg_pio_rw_ce1_cfg___ew___lsb 6 +#define reg_pio_rw_ce1_cfg___ew___width 3 +#define reg_pio_rw_ce1_cfg___zw___lsb 9 +#define reg_pio_rw_ce1_cfg___zw___width 3 +#define reg_pio_rw_ce1_cfg___aw___lsb 12 +#define reg_pio_rw_ce1_cfg___aw___width 2 +#define reg_pio_rw_ce1_cfg___mode___lsb 14 +#define reg_pio_rw_ce1_cfg___mode___width 2 +#define reg_pio_rw_ce1_cfg_offset 72 + +/* Register rw_ce2_cfg, scope pio, type rw */ +#define reg_pio_rw_ce2_cfg___lw___lsb 0 +#define reg_pio_rw_ce2_cfg___lw___width 6 +#define reg_pio_rw_ce2_cfg___ew___lsb 6 +#define reg_pio_rw_ce2_cfg___ew___width 3 +#define reg_pio_rw_ce2_cfg___zw___lsb 9 +#define reg_pio_rw_ce2_cfg___zw___width 3 +#define reg_pio_rw_ce2_cfg___aw___lsb 12 +#define reg_pio_rw_ce2_cfg___aw___width 2 +#define reg_pio_rw_ce2_cfg___mode___lsb 14 +#define reg_pio_rw_ce2_cfg___mode___width 2 +#define reg_pio_rw_ce2_cfg_offset 76 + +/* Register rw_dout, scope pio, type rw */ +#define reg_pio_rw_dout___data___lsb 0 +#define reg_pio_rw_dout___data___width 8 +#define reg_pio_rw_dout___rd_n___lsb 8 +#define reg_pio_rw_dout___rd_n___width 1 +#define reg_pio_rw_dout___rd_n___bit 8 +#define reg_pio_rw_dout___wr_n___lsb 9 +#define reg_pio_rw_dout___wr_n___width 1 +#define reg_pio_rw_dout___wr_n___bit 9 +#define reg_pio_rw_dout___a0___lsb 10 +#define reg_pio_rw_dout___a0___width 1 +#define reg_pio_rw_dout___a0___bit 10 +#define reg_pio_rw_dout___a1___lsb 11 +#define reg_pio_rw_dout___a1___width 1 +#define reg_pio_rw_dout___a1___bit 11 +#define reg_pio_rw_dout___ce0_n___lsb 12 +#define reg_pio_rw_dout___ce0_n___width 1 +#define reg_pio_rw_dout___ce0_n___bit 12 +#define reg_pio_rw_dout___ce1_n___lsb 13 +#define reg_pio_rw_dout___ce1_n___width 1 +#define reg_pio_rw_dout___ce1_n___bit 13 +#define reg_pio_rw_dout___ce2_n___lsb 14 +#define reg_pio_rw_dout___ce2_n___width 1 +#define reg_pio_rw_dout___ce2_n___bit 14 +#define reg_pio_rw_dout___rdy___lsb 15 +#define reg_pio_rw_dout___rdy___width 1 +#define reg_pio_rw_dout___rdy___bit 15 +#define reg_pio_rw_dout_offset 80 + +/* Register rw_oe, scope pio, type rw */ +#define reg_pio_rw_oe___data___lsb 0 +#define reg_pio_rw_oe___data___width 8 +#define reg_pio_rw_oe___rd_n___lsb 8 +#define reg_pio_rw_oe___rd_n___width 1 +#define reg_pio_rw_oe___rd_n___bit 8 +#define reg_pio_rw_oe___wr_n___lsb 9 +#define reg_pio_rw_oe___wr_n___width 1 +#define reg_pio_rw_oe___wr_n___bit 9 +#define reg_pio_rw_oe___a0___lsb 10 +#define reg_pio_rw_oe___a0___width 1 +#define reg_pio_rw_oe___a0___bit 10 +#define reg_pio_rw_oe___a1___lsb 11 +#define reg_pio_rw_oe___a1___width 1 +#define reg_pio_rw_oe___a1___bit 11 +#define reg_pio_rw_oe___ce0_n___lsb 12 +#define reg_pio_rw_oe___ce0_n___width 1 +#define reg_pio_rw_oe___ce0_n___bit 12 +#define reg_pio_rw_oe___ce1_n___lsb 13 +#define reg_pio_rw_oe___ce1_n___width 1 +#define reg_pio_rw_oe___ce1_n___bit 13 +#define reg_pio_rw_oe___ce2_n___lsb 14 +#define reg_pio_rw_oe___ce2_n___width 1 +#define reg_pio_rw_oe___ce2_n___bit 14 +#define reg_pio_rw_oe___rdy___lsb 15 +#define reg_pio_rw_oe___rdy___width 1 +#define reg_pio_rw_oe___rdy___bit 15 +#define reg_pio_rw_oe_offset 84 + +/* Register rw_man_ctrl, scope pio, type rw */ +#define reg_pio_rw_man_ctrl___data___lsb 0 +#define reg_pio_rw_man_ctrl___data___width 8 +#define reg_pio_rw_man_ctrl___rd_n___lsb 8 +#define reg_pio_rw_man_ctrl___rd_n___width 1 +#define reg_pio_rw_man_ctrl___rd_n___bit 8 +#define reg_pio_rw_man_ctrl___wr_n___lsb 9 +#define reg_pio_rw_man_ctrl___wr_n___width 1 +#define reg_pio_rw_man_ctrl___wr_n___bit 9 +#define reg_pio_rw_man_ctrl___a0___lsb 10 +#define reg_pio_rw_man_ctrl___a0___width 1 +#define reg_pio_rw_man_ctrl___a0___bit 10 +#define reg_pio_rw_man_ctrl___a1___lsb 11 +#define reg_pio_rw_man_ctrl___a1___width 1 +#define reg_pio_rw_man_ctrl___a1___bit 11 +#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 +#define reg_pio_rw_man_ctrl___ce0_n___width 1 +#define reg_pio_rw_man_ctrl___ce0_n___bit 12 +#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 +#define reg_pio_rw_man_ctrl___ce1_n___width 1 +#define reg_pio_rw_man_ctrl___ce1_n___bit 13 +#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 +#define reg_pio_rw_man_ctrl___ce2_n___width 1 +#define reg_pio_rw_man_ctrl___ce2_n___bit 14 +#define reg_pio_rw_man_ctrl___rdy___lsb 15 +#define reg_pio_rw_man_ctrl___rdy___width 1 +#define reg_pio_rw_man_ctrl___rdy___bit 15 +#define reg_pio_rw_man_ctrl_offset 88 + +/* Register r_din, scope pio, type r */ +#define reg_pio_r_din___data___lsb 0 +#define reg_pio_r_din___data___width 8 +#define reg_pio_r_din___rd_n___lsb 8 +#define reg_pio_r_din___rd_n___width 1 +#define reg_pio_r_din___rd_n___bit 8 +#define reg_pio_r_din___wr_n___lsb 9 +#define reg_pio_r_din___wr_n___width 1 +#define reg_pio_r_din___wr_n___bit 9 +#define reg_pio_r_din___a0___lsb 10 +#define reg_pio_r_din___a0___width 1 +#define reg_pio_r_din___a0___bit 10 +#define reg_pio_r_din___a1___lsb 11 +#define reg_pio_r_din___a1___width 1 +#define reg_pio_r_din___a1___bit 11 +#define reg_pio_r_din___ce0_n___lsb 12 +#define reg_pio_r_din___ce0_n___width 1 +#define reg_pio_r_din___ce0_n___bit 12 +#define reg_pio_r_din___ce1_n___lsb 13 +#define reg_pio_r_din___ce1_n___width 1 +#define reg_pio_r_din___ce1_n___bit 13 +#define reg_pio_r_din___ce2_n___lsb 14 +#define reg_pio_r_din___ce2_n___width 1 +#define reg_pio_r_din___ce2_n___bit 14 +#define reg_pio_r_din___rdy___lsb 15 +#define reg_pio_r_din___rdy___width 1 +#define reg_pio_r_din___rdy___bit 15 +#define reg_pio_r_din_offset 92 + +/* Register r_stat, scope pio, type r */ +#define reg_pio_r_stat___busy___lsb 0 +#define reg_pio_r_stat___busy___width 1 +#define reg_pio_r_stat___busy___bit 0 +#define reg_pio_r_stat_offset 96 + +/* Register rw_intr_mask, scope pio, type rw */ +#define reg_pio_rw_intr_mask___rdy___lsb 0 +#define reg_pio_rw_intr_mask___rdy___width 1 +#define reg_pio_rw_intr_mask___rdy___bit 0 +#define reg_pio_rw_intr_mask_offset 100 + +/* Register rw_ack_intr, scope pio, type rw */ +#define reg_pio_rw_ack_intr___rdy___lsb 0 +#define reg_pio_rw_ack_intr___rdy___width 1 +#define reg_pio_rw_ack_intr___rdy___bit 0 +#define reg_pio_rw_ack_intr_offset 104 + +/* Register r_intr, scope pio, type r */ +#define reg_pio_r_intr___rdy___lsb 0 +#define reg_pio_r_intr___rdy___width 1 +#define reg_pio_r_intr___rdy___bit 0 +#define reg_pio_r_intr_offset 108 + +/* Register r_masked_intr, scope pio, type r */ +#define reg_pio_r_masked_intr___rdy___lsb 0 +#define reg_pio_r_masked_intr___rdy___width 1 +#define reg_pio_r_masked_intr___rdy___bit 0 +#define reg_pio_r_masked_intr_offset 112 + + +/* Constants */ +#define regk_pio_a2 0x00000003 +#define regk_pio_no 0x00000000 +#define regk_pio_normal 0x00000000 +#define regk_pio_rd 0x00000001 +#define regk_pio_rw_ce0_cfg_default 0x00000000 +#define regk_pio_rw_ce1_cfg_default 0x00000000 +#define regk_pio_rw_ce2_cfg_default 0x00000000 +#define regk_pio_rw_intr_mask_default 0x00000000 +#define regk_pio_rw_man_ctrl_default 0x00000000 +#define regk_pio_rw_oe_default 0x00000000 +#define regk_pio_wr 0x00000002 +#define regk_pio_wr_ce2 0x00000003 +#define regk_pio_yes 0x00000001 +#define regk_pio_yes_all 0x000000ff +#endif /* __pio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000000..89439e9610e2 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h @@ -0,0 +1,99 @@ +#ifndef __reg_map_asm_h +#define __reg_map_asm_h + +/* + * This file is autogenerated from + * file: reg.rmap + * + * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_ccd 0xb0000000 +#define regi_ccd_top 0xb0000000 +#define regi_ccd_dp 0xb0000400 +#define regi_ccd_stat 0xb0000800 +#define regi_ccd_tg 0xb0001000 +#define regi_cfg 0xb0002000 +#define regi_clkgen 0xb0004000 +#define regi_ddr2_ctrl 0xb0006000 +#define regi_dma0 0xb0008000 +#define regi_dma1 0xb000a000 +#define regi_dma11 0xb000c000 +#define regi_dma2 0xb000e000 +#define regi_dma3 0xb0010000 +#define regi_dma4 0xb0012000 +#define regi_dma5 0xb0014000 +#define regi_dma6 0xb0016000 +#define regi_dma7 0xb0018000 +#define regi_dma9 0xb001a000 +#define regi_eth 0xb001c000 +#define regi_gio 0xb0020000 +#define regi_h264 0xb0022000 +#define regi_hist 0xb0026000 +#define regi_iop 0xb0028000 +#define regi_iop_version 0xb0028000 +#define regi_iop_fifo_in_extra 0xb0028040 +#define regi_iop_fifo_out_extra 0xb0028080 +#define regi_iop_trigger_grp0 0xb00280c0 +#define regi_iop_trigger_grp1 0xb0028100 +#define regi_iop_trigger_grp2 0xb0028140 +#define regi_iop_trigger_grp3 0xb0028180 +#define regi_iop_trigger_grp4 0xb00281c0 +#define regi_iop_trigger_grp5 0xb0028200 +#define regi_iop_trigger_grp6 0xb0028240 +#define regi_iop_trigger_grp7 0xb0028280 +#define regi_iop_crc_par 0xb0028300 +#define regi_iop_dmc_in 0xb0028380 +#define regi_iop_dmc_out 0xb0028400 +#define regi_iop_fifo_in 0xb0028480 +#define regi_iop_fifo_out 0xb0028500 +#define regi_iop_scrc_in 0xb0028580 +#define regi_iop_scrc_out 0xb0028600 +#define regi_iop_timer_grp0 0xb0028680 +#define regi_iop_timer_grp1 0xb0028700 +#define regi_iop_sap_in 0xb0028800 +#define regi_iop_sap_out 0xb0028900 +#define regi_iop_spu 0xb0028a00 +#define regi_iop_sw_cfg 0xb0028b00 +#define regi_iop_sw_cpu 0xb0028c00 +#define regi_iop_sw_mpu 0xb0028d00 +#define regi_iop_sw_spu 0xb0028e00 +#define regi_iop_mpu 0xb0029000 +#define regi_irq 0xb002a000 +#define regi_jpeg 0xb002c000 +#define regi_l2cache 0xb0030000 +#define regi_marb_bar 0xb0032000 +#define regi_marb_bar_bp0 0xb0032140 +#define regi_marb_bar_bp1 0xb0032180 +#define regi_marb_bar_bp2 0xb00321c0 +#define regi_marb_bar_bp3 0xb0032200 +#define regi_marb_foo 0xb0034000 +#define regi_marb_foo_bp0 0xb0034280 +#define regi_marb_foo_bp1 0xb00342c0 +#define regi_marb_foo_bp2 0xb0034300 +#define regi_marb_foo_bp3 0xb0034340 +#define regi_pinmux 0xb0038000 +#define regi_pio 0xb0036000 +#define regi_sclr 0xb003a000 +#define regi_sclr_fifo 0xb003c000 +#define regi_ser0 0xb003e000 +#define regi_ser1 0xb0040000 +#define regi_ser2 0xb0042000 +#define regi_ser3 0xb0044000 +#define regi_ser4 0xb0046000 +#define regi_sser 0xb0048000 +#define regi_strcop 0xb004a000 +#define regi_strdma0 0xb004e000 +#define regi_strdma1 0xb0050000 +#define regi_strdma2 0xb0052000 +#define regi_strdma3 0xb0054000 +#define regi_strdma5 0xb0056000 +#define regi_strmux 0xb004c000 +#define regi_timer0 0xb0058000 +#define regi_timer1 0xb005a000 +#define regi_trace 0xb005c000 +#define regi_vin 0xb005e000 +#define regi_vout 0xb0060000 +#endif /* __reg_map_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000000..b129e826fc34 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,228 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: timer.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_f90 0x00000003 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_vclk 0x00000002 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h new file mode 100644 index 000000000000..c1e9ba93b3a3 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h @@ -0,0 +1,159 @@ +#ifndef __clkgen_defs_h +#define __clkgen_defs_h + +/* + * This file is autogenerated from + * file: clkgen.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope clkgen */ + +/* Register r_bootsel, scope clkgen, type r */ +typedef struct { + unsigned int boot_mode : 5; + unsigned int intern_main_clk : 1; + unsigned int extern_usb2_clk : 1; + unsigned int dummy1 : 25; +} reg_clkgen_r_bootsel; +#define REG_RD_ADDR_clkgen_r_bootsel 0 + +/* Register rw_clk_ctrl, scope clkgen, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop_usb : 1; + unsigned int vin : 1; + unsigned int sclr : 1; + unsigned int h264 : 1; + unsigned int ddr2 : 1; + unsigned int vout_hist : 1; + unsigned int eth : 1; + unsigned int ccd_tg_200 : 1; + unsigned int dma0_1_eth : 1; + unsigned int ccd_tg_100 : 1; + unsigned int jpeg : 1; + unsigned int sser_ser_dma6_7 : 1; + unsigned int strdma0_2_video : 1; + unsigned int dma2_3_strcop : 1; + unsigned int dma4_5_iop : 1; + unsigned int dma9_11 : 1; + unsigned int memarb_bar_ddr : 1; + unsigned int sclr_h264 : 1; + unsigned int dummy1 : 12; +} reg_clkgen_rw_clk_ctrl; +#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 +#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 + + +/* Constants */ +enum { + regk_clkgen_eth1000_rx = 0x0000000c, + regk_clkgen_eth1000_tx = 0x0000000e, + regk_clkgen_eth100_rx = 0x0000001d, + regk_clkgen_eth100_rx_half = 0x0000001c, + regk_clkgen_eth100_tx = 0x0000001f, + regk_clkgen_eth100_tx_half = 0x0000001e, + regk_clkgen_nand_3_2 = 0x00000000, + regk_clkgen_nand_3_2_0x30 = 0x00000002, + regk_clkgen_nand_3_2_0x30_pll = 0x00000012, + regk_clkgen_nand_3_2_pll = 0x00000010, + regk_clkgen_nand_3_3 = 0x00000001, + regk_clkgen_nand_3_3_0x30 = 0x00000003, + regk_clkgen_nand_3_3_0x30_pll = 0x00000013, + regk_clkgen_nand_3_3_pll = 0x00000011, + regk_clkgen_nand_4_2 = 0x00000004, + regk_clkgen_nand_4_2_0x30 = 0x00000006, + regk_clkgen_nand_4_2_0x30_pll = 0x00000016, + regk_clkgen_nand_4_2_pll = 0x00000014, + regk_clkgen_nand_4_3 = 0x00000005, + regk_clkgen_nand_4_3_0x30 = 0x00000007, + regk_clkgen_nand_4_3_0x30_pll = 0x00000017, + regk_clkgen_nand_4_3_pll = 0x00000015, + regk_clkgen_nand_5_2 = 0x00000008, + regk_clkgen_nand_5_2_0x30 = 0x0000000a, + regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, + regk_clkgen_nand_5_2_pll = 0x00000018, + regk_clkgen_nand_5_3 = 0x00000009, + regk_clkgen_nand_5_3_0x30 = 0x0000000b, + regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, + regk_clkgen_nand_5_3_pll = 0x00000019, + regk_clkgen_no = 0x00000000, + regk_clkgen_rw_clk_ctrl_default = 0x00000002, + regk_clkgen_ser = 0x0000000d, + regk_clkgen_ser_pll = 0x0000000f, + regk_clkgen_yes = 0x00000001 +}; +#endif /* __clkgen_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h new file mode 100644 index 000000000000..0f30e8bf946d --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h @@ -0,0 +1,281 @@ +#ifndef __ddr2_defs_h +#define __ddr2_defs_h + +/* + * This file is autogenerated from + * file: ddr2.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ddr2 */ + +/* Register rw_cfg, scope ddr2, type rw */ +typedef struct { + unsigned int col_width : 4; + unsigned int nr_banks : 1; + unsigned int bw : 1; + unsigned int nr_ref : 4; + unsigned int ref_interval : 11; + unsigned int odt_ctrl : 2; + unsigned int odt_mem : 1; + unsigned int imp_strength : 1; + unsigned int auto_imp_cal : 1; + unsigned int imp_cal_override : 1; + unsigned int dll_override : 1; + unsigned int dummy1 : 4; +} reg_ddr2_rw_cfg; +#define REG_RD_ADDR_ddr2_rw_cfg 0 +#define REG_WR_ADDR_ddr2_rw_cfg 0 + +/* Register rw_timing, scope ddr2, type rw */ +typedef struct { + unsigned int wr : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int ras : 4; + unsigned int rfc : 7; + unsigned int rc : 5; + unsigned int rtp : 2; + unsigned int rtw : 3; + unsigned int wtr : 2; +} reg_ddr2_rw_timing; +#define REG_RD_ADDR_ddr2_rw_timing 4 +#define REG_WR_ADDR_ddr2_rw_timing 4 + +/* Register rw_latency, scope ddr2, type rw */ +typedef struct { + unsigned int cas : 3; + unsigned int additive : 3; + unsigned int dummy1 : 26; +} reg_ddr2_rw_latency; +#define REG_RD_ADDR_ddr2_rw_latency 8 +#define REG_WR_ADDR_ddr2_rw_latency 8 + +/* Register rw_phy_cfg, scope ddr2, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_ddr2_rw_phy_cfg; +#define REG_RD_ADDR_ddr2_rw_phy_cfg 12 +#define REG_WR_ADDR_ddr2_rw_phy_cfg 12 + +/* Register rw_phy_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int rst : 1; + unsigned int cal_rst : 1; + unsigned int cal_start : 1; + unsigned int dummy1 : 29; +} reg_ddr2_rw_phy_ctrl; +#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 +#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 + +/* Register rw_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int mrs_data : 16; + unsigned int cmd : 8; + unsigned int dummy1 : 8; +} reg_ddr2_rw_ctrl; +#define REG_RD_ADDR_ddr2_rw_ctrl 20 +#define REG_WR_ADDR_ddr2_rw_ctrl 20 + +/* Register rw_pwr_down, scope ddr2, type rw */ +typedef struct { + unsigned int self_ref : 2; + unsigned int phy_en : 1; + unsigned int dummy1 : 29; +} reg_ddr2_rw_pwr_down; +#define REG_RD_ADDR_ddr2_rw_pwr_down 24 +#define REG_WR_ADDR_ddr2_rw_pwr_down 24 + +/* Register r_stat, scope ddr2, type r */ +typedef struct { + unsigned int dll_lock : 1; + unsigned int dll_delay_code : 7; + unsigned int imp_cal_done : 1; + unsigned int imp_cal_fault : 1; + unsigned int cal_imp_pu : 4; + unsigned int cal_imp_pd : 4; + unsigned int dummy1 : 14; +} reg_ddr2_r_stat; +#define REG_RD_ADDR_ddr2_r_stat 28 + +/* Register rw_imp_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int imp_pu : 4; + unsigned int imp_pd : 4; + unsigned int dummy1 : 24; +} reg_ddr2_rw_imp_ctrl; +#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 +#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 + +#define STRIDE_ddr2_rw_dll_ctrl 4 +/* Register rw_dll_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int mode : 1; + unsigned int clk_delay : 7; + unsigned int dummy1 : 24; +} reg_ddr2_rw_dll_ctrl; +#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 +#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 + +#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 +/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int dqs90_delay : 7; + unsigned int dqs180_delay : 7; + unsigned int dqs270_delay : 7; + unsigned int dqs360_delay : 7; + unsigned int dummy1 : 4; +} reg_ddr2_rw_dqs_dll_ctrl; +#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 +#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 + + +/* Constants */ +enum { + regk_ddr2_al0 = 0x00000000, + regk_ddr2_al1 = 0x00000008, + regk_ddr2_al2 = 0x00000010, + regk_ddr2_al3 = 0x00000018, + regk_ddr2_al4 = 0x00000020, + regk_ddr2_auto = 0x00000003, + regk_ddr2_bank4 = 0x00000000, + regk_ddr2_bank8 = 0x00000001, + regk_ddr2_bl4 = 0x00000002, + regk_ddr2_bl8 = 0x00000003, + regk_ddr2_bt_il = 0x00000008, + regk_ddr2_bt_seq = 0x00000000, + regk_ddr2_bw16 = 0x00000001, + regk_ddr2_bw32 = 0x00000000, + regk_ddr2_cas2 = 0x00000020, + regk_ddr2_cas3 = 0x00000030, + regk_ddr2_cas4 = 0x00000040, + regk_ddr2_cas5 = 0x00000050, + regk_ddr2_deselect = 0x000000c0, + regk_ddr2_dic_weak = 0x00000002, + regk_ddr2_direct = 0x00000001, + regk_ddr2_dis = 0x00000000, + regk_ddr2_dll_dis = 0x00000001, + regk_ddr2_dll_en = 0x00000000, + regk_ddr2_dll_rst = 0x00000100, + regk_ddr2_emrs = 0x00000081, + regk_ddr2_emrs2 = 0x00000082, + regk_ddr2_emrs3 = 0x00000083, + regk_ddr2_full = 0x00000001, + regk_ddr2_hi_ref_rate = 0x00000080, + regk_ddr2_mrs = 0x00000080, + regk_ddr2_no = 0x00000000, + regk_ddr2_nop = 0x000000b8, + regk_ddr2_ocd_adj = 0x00000200, + regk_ddr2_ocd_default = 0x00000380, + regk_ddr2_ocd_drive0 = 0x00000100, + regk_ddr2_ocd_drive1 = 0x00000080, + regk_ddr2_ocd_exit = 0x00000000, + regk_ddr2_odt_dis = 0x00000000, + regk_ddr2_offs = 0x00000000, + regk_ddr2_pre = 0x00000090, + regk_ddr2_pre_all = 0x00000400, + regk_ddr2_pwr_down_fast = 0x00000000, + regk_ddr2_pwr_down_slow = 0x00001000, + regk_ddr2_ref = 0x00000088, + regk_ddr2_rtt150 = 0x00000040, + regk_ddr2_rtt50 = 0x00000044, + regk_ddr2_rtt75 = 0x00000004, + regk_ddr2_rw_cfg_default = 0x00186000, + regk_ddr2_rw_dll_ctrl_default = 0x00000000, + regk_ddr2_rw_dll_ctrl_size = 0x00000004, + regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, + regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, + regk_ddr2_rw_latency_default = 0x00000000, + regk_ddr2_rw_phy_cfg_default = 0x00000000, + regk_ddr2_rw_pwr_down_default = 0x00000000, + regk_ddr2_rw_timing_default = 0x00000000, + regk_ddr2_s1Gb = 0x0000001a, + regk_ddr2_s256Mb = 0x0000000f, + regk_ddr2_s2Gb = 0x00000027, + regk_ddr2_s4Gb = 0x00000042, + regk_ddr2_s512Mb = 0x00000015, + regk_ddr2_temp0_85 = 0x00000618, + regk_ddr2_temp85_95 = 0x0000030c, + regk_ddr2_term150 = 0x00000002, + regk_ddr2_term50 = 0x00000003, + regk_ddr2_term75 = 0x00000001, + regk_ddr2_test = 0x00000080, + regk_ddr2_weak = 0x00000000, + regk_ddr2_wr2 = 0x00000200, + regk_ddr2_wr3 = 0x00000400, + regk_ddr2_yes = 0x00000001 +}; +#endif /* __ddr2_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h new file mode 100644 index 000000000000..5d88e0db23ae --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h @@ -0,0 +1,837 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: gio.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 0 + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 32; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 4 +#define REG_WR_ADDR_gio_rw_pa_dout 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 32; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_pa_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte0_dout; +#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 +#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 + +/* Register rw_pa_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte0_oe; +#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 +#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 + +/* Register rw_pa_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte1_dout; +#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 +#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 + +/* Register rw_pa_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte1_oe; +#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 +#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 + +/* Register rw_pa_byte2_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte2_dout; +#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 +#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 + +/* Register rw_pa_byte2_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte2_oe; +#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 +#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 + +/* Register rw_pa_byte3_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte3_dout; +#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 +#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 + +/* Register rw_pa_byte3_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte3_oe; +#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 +#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 44 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 32; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 48 +#define REG_WR_ADDR_gio_rw_pb_dout 48 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 32; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 52 +#define REG_WR_ADDR_gio_rw_pb_oe 52 + +/* Register rw_pb_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte0_dout; +#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 +#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 + +/* Register rw_pb_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte0_oe; +#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 +#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 + +/* Register rw_pb_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte1_dout; +#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 +#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 + +/* Register rw_pb_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte1_oe; +#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 +#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 + +/* Register rw_pb_byte2_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte2_dout; +#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 +#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 + +/* Register rw_pb_byte2_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte2_oe; +#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 +#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 + +/* Register rw_pb_byte3_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte3_dout; +#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 +#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 + +/* Register rw_pb_byte3_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte3_oe; +#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 +#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 88 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 92 +#define REG_WR_ADDR_gio_rw_pc_dout 92 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 16; + unsigned int dummy1 : 16; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 96 +#define REG_WR_ADDR_gio_rw_pc_oe 96 + +/* Register rw_pc_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte0_dout; +#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 +#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 + +/* Register rw_pc_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte0_oe; +#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 +#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 + +/* Register rw_pc_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte1_dout; +#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 +#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 + +/* Register rw_pc_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte1_oe; +#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 +#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 116 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 3; + unsigned int intr1 : 3; + unsigned int intr2 : 3; + unsigned int intr3 : 3; + unsigned int intr4 : 3; + unsigned int intr5 : 3; + unsigned int intr6 : 3; + unsigned int intr7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 120 +#define REG_WR_ADDR_gio_rw_intr_cfg 120 + +/* Register rw_intr_pins, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 4; + unsigned int intr1 : 4; + unsigned int intr2 : 4; + unsigned int intr3 : 4; + unsigned int intr4 : 4; + unsigned int intr5 : 4; + unsigned int intr6 : 4; + unsigned int intr7 : 4; +} reg_gio_rw_intr_pins; +#define REG_RD_ADDR_gio_rw_intr_pins 124 +#define REG_WR_ADDR_gio_rw_intr_pins 124 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 128 +#define REG_WR_ADDR_gio_rw_intr_mask 128 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 132 +#define REG_WR_ADDR_gio_rw_ack_intr 132 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 136 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 140 + +/* Register rw_i2c0_start, scope gio, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_gio_rw_i2c0_start; +#define REG_RD_ADDR_gio_rw_i2c0_start 144 +#define REG_WR_ADDR_gio_rw_i2c0_start 144 + +/* Register rw_i2c0_cfg, scope gio, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int bit_order : 1; + unsigned int scl_io : 1; + unsigned int scl_inv : 1; + unsigned int sda_io : 1; + unsigned int sda_idle : 1; + unsigned int dummy1 : 26; +} reg_gio_rw_i2c0_cfg; +#define REG_RD_ADDR_gio_rw_i2c0_cfg 148 +#define REG_WR_ADDR_gio_rw_i2c0_cfg 148 + +/* Register rw_i2c0_ctrl, scope gio, type rw */ +typedef struct { + unsigned int trf_bits : 6; + unsigned int switch_dir : 6; + unsigned int extra_start : 3; + unsigned int early_end : 1; + unsigned int start_stop : 1; + unsigned int ack_dir0 : 1; + unsigned int ack_dir1 : 1; + unsigned int ack_dir2 : 1; + unsigned int ack_dir3 : 1; + unsigned int ack_dir4 : 1; + unsigned int ack_dir5 : 1; + unsigned int ack_bit : 1; + unsigned int start_bit : 1; + unsigned int freq : 2; + unsigned int dummy1 : 5; +} reg_gio_rw_i2c0_ctrl; +#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 +#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 + +/* Register rw_i2c0_data, scope gio, type rw */ +typedef struct { + unsigned int data0 : 8; + unsigned int data1 : 8; + unsigned int data2 : 8; + unsigned int data3 : 8; +} reg_gio_rw_i2c0_data; +#define REG_RD_ADDR_gio_rw_i2c0_data 156 +#define REG_WR_ADDR_gio_rw_i2c0_data 156 + +/* Register rw_i2c0_data2, scope gio, type rw */ +typedef struct { + unsigned int data4 : 8; + unsigned int data5 : 8; + unsigned int start_val : 6; + unsigned int ack_val : 6; + unsigned int dummy1 : 4; +} reg_gio_rw_i2c0_data2; +#define REG_RD_ADDR_gio_rw_i2c0_data2 160 +#define REG_WR_ADDR_gio_rw_i2c0_data2 160 + +/* Register rw_i2c1_start, scope gio, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_gio_rw_i2c1_start; +#define REG_RD_ADDR_gio_rw_i2c1_start 164 +#define REG_WR_ADDR_gio_rw_i2c1_start 164 + +/* Register rw_i2c1_cfg, scope gio, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int bit_order : 1; + unsigned int scl_io : 1; + unsigned int scl_inv : 1; + unsigned int sda0_io : 1; + unsigned int sda0_idle : 1; + unsigned int sda1_io : 1; + unsigned int sda1_idle : 1; + unsigned int sda2_io : 1; + unsigned int sda2_idle : 1; + unsigned int sda3_io : 1; + unsigned int sda3_idle : 1; + unsigned int sda_sel : 2; + unsigned int sen_idle : 1; + unsigned int sen_inv : 1; + unsigned int sen_sel : 2; + unsigned int dummy1 : 14; +} reg_gio_rw_i2c1_cfg; +#define REG_RD_ADDR_gio_rw_i2c1_cfg 168 +#define REG_WR_ADDR_gio_rw_i2c1_cfg 168 + +/* Register rw_i2c1_ctrl, scope gio, type rw */ +typedef struct { + unsigned int trf_bits : 6; + unsigned int switch_dir : 6; + unsigned int extra_start : 3; + unsigned int early_end : 1; + unsigned int start_stop : 1; + unsigned int ack_dir0 : 1; + unsigned int ack_dir1 : 1; + unsigned int ack_dir2 : 1; + unsigned int ack_dir3 : 1; + unsigned int ack_dir4 : 1; + unsigned int ack_dir5 : 1; + unsigned int ack_bit : 1; + unsigned int start_bit : 1; + unsigned int freq : 2; + unsigned int dummy1 : 5; +} reg_gio_rw_i2c1_ctrl; +#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 +#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 + +/* Register rw_i2c1_data, scope gio, type rw */ +typedef struct { + unsigned int data0 : 8; + unsigned int data1 : 8; + unsigned int data2 : 8; + unsigned int data3 : 8; +} reg_gio_rw_i2c1_data; +#define REG_RD_ADDR_gio_rw_i2c1_data 176 +#define REG_WR_ADDR_gio_rw_i2c1_data 176 + +/* Register rw_i2c1_data2, scope gio, type rw */ +typedef struct { + unsigned int data4 : 8; + unsigned int data5 : 8; + unsigned int start_val : 6; + unsigned int ack_val : 6; + unsigned int dummy1 : 4; +} reg_gio_rw_i2c1_data2; +#define REG_RD_ADDR_gio_rw_i2c1_data2 180 +#define REG_WR_ADDR_gio_rw_i2c1_data2 180 + +/* Register r_ppwm_stat, scope gio, type r */ +typedef struct { + unsigned int freq : 2; + unsigned int dummy1 : 30; +} reg_gio_r_ppwm_stat; +#define REG_RD_ADDR_gio_r_ppwm_stat 184 + +/* Register rw_ppwm_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_ppwm_data; +#define REG_RD_ADDR_gio_rw_ppwm_data 188 +#define REG_WR_ADDR_gio_rw_ppwm_data 188 + +/* Register rw_pwm0_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm0_ctrl; +#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 +#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 + +/* Register rw_pwm0_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm0_var; +#define REG_RD_ADDR_gio_rw_pwm0_var 196 +#define REG_WR_ADDR_gio_rw_pwm0_var 196 + +/* Register rw_pwm0_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm0_data; +#define REG_RD_ADDR_gio_rw_pwm0_data 200 +#define REG_WR_ADDR_gio_rw_pwm0_data 200 + +/* Register rw_pwm1_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm1_ctrl; +#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 +#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 + +/* Register rw_pwm1_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm1_var; +#define REG_RD_ADDR_gio_rw_pwm1_var 208 +#define REG_WR_ADDR_gio_rw_pwm1_var 208 + +/* Register rw_pwm1_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm1_data; +#define REG_RD_ADDR_gio_rw_pwm1_data 212 +#define REG_WR_ADDR_gio_rw_pwm1_data 212 + +/* Register rw_pwm2_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm2_ctrl; +#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 +#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 + +/* Register rw_pwm2_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm2_var; +#define REG_RD_ADDR_gio_rw_pwm2_var 220 +#define REG_WR_ADDR_gio_rw_pwm2_var 220 + +/* Register rw_pwm2_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm2_data; +#define REG_RD_ADDR_gio_rw_pwm2_data 224 +#define REG_WR_ADDR_gio_rw_pwm2_data 224 + +/* Register rw_pwm_in_cfg, scope gio, type rw */ +typedef struct { + unsigned int pin : 3; + unsigned int dummy1 : 29; +} reg_gio_rw_pwm_in_cfg; +#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 +#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 + +/* Register r_pwm_in_lo, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_lo; +#define REG_RD_ADDR_gio_r_pwm_in_lo 232 + +/* Register r_pwm_in_hi, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_hi; +#define REG_RD_ADDR_gio_r_pwm_in_hi 236 + +/* Register r_pwm_in_cnt, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_cnt; +#define REG_RD_ADDR_gio_r_pwm_in_cnt 240 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_f100k = 0x00000000, + regk_gio_f1562 = 0x00000000, + regk_gio_f195 = 0x00000003, + regk_gio_f1m = 0x00000002, + regk_gio_f390 = 0x00000002, + regk_gio_f400k = 0x00000001, + regk_gio_f5m = 0x00000003, + regk_gio_f781 = 0x00000001, + regk_gio_hi = 0x00000001, + regk_gio_in = 0x00000000, + regk_gio_intr_pa0 = 0x00000000, + regk_gio_intr_pa1 = 0x00000000, + regk_gio_intr_pa10 = 0x00000001, + regk_gio_intr_pa11 = 0x00000001, + regk_gio_intr_pa12 = 0x00000001, + regk_gio_intr_pa13 = 0x00000001, + regk_gio_intr_pa14 = 0x00000001, + regk_gio_intr_pa15 = 0x00000001, + regk_gio_intr_pa16 = 0x00000002, + regk_gio_intr_pa17 = 0x00000002, + regk_gio_intr_pa18 = 0x00000002, + regk_gio_intr_pa19 = 0x00000002, + regk_gio_intr_pa2 = 0x00000000, + regk_gio_intr_pa20 = 0x00000002, + regk_gio_intr_pa21 = 0x00000002, + regk_gio_intr_pa22 = 0x00000002, + regk_gio_intr_pa23 = 0x00000002, + regk_gio_intr_pa24 = 0x00000003, + regk_gio_intr_pa25 = 0x00000003, + regk_gio_intr_pa26 = 0x00000003, + regk_gio_intr_pa27 = 0x00000003, + regk_gio_intr_pa28 = 0x00000003, + regk_gio_intr_pa29 = 0x00000003, + regk_gio_intr_pa3 = 0x00000000, + regk_gio_intr_pa30 = 0x00000003, + regk_gio_intr_pa31 = 0x00000003, + regk_gio_intr_pa4 = 0x00000000, + regk_gio_intr_pa5 = 0x00000000, + regk_gio_intr_pa6 = 0x00000000, + regk_gio_intr_pa7 = 0x00000000, + regk_gio_intr_pa8 = 0x00000001, + regk_gio_intr_pa9 = 0x00000001, + regk_gio_intr_pb0 = 0x00000004, + regk_gio_intr_pb1 = 0x00000004, + regk_gio_intr_pb10 = 0x00000005, + regk_gio_intr_pb11 = 0x00000005, + regk_gio_intr_pb12 = 0x00000005, + regk_gio_intr_pb13 = 0x00000005, + regk_gio_intr_pb14 = 0x00000005, + regk_gio_intr_pb15 = 0x00000005, + regk_gio_intr_pb16 = 0x00000006, + regk_gio_intr_pb17 = 0x00000006, + regk_gio_intr_pb18 = 0x00000006, + regk_gio_intr_pb19 = 0x00000006, + regk_gio_intr_pb2 = 0x00000004, + regk_gio_intr_pb20 = 0x00000006, + regk_gio_intr_pb21 = 0x00000006, + regk_gio_intr_pb22 = 0x00000006, + regk_gio_intr_pb23 = 0x00000006, + regk_gio_intr_pb24 = 0x00000007, + regk_gio_intr_pb25 = 0x00000007, + regk_gio_intr_pb26 = 0x00000007, + regk_gio_intr_pb27 = 0x00000007, + regk_gio_intr_pb28 = 0x00000007, + regk_gio_intr_pb29 = 0x00000007, + regk_gio_intr_pb3 = 0x00000004, + regk_gio_intr_pb30 = 0x00000007, + regk_gio_intr_pb31 = 0x00000007, + regk_gio_intr_pb4 = 0x00000004, + regk_gio_intr_pb5 = 0x00000004, + regk_gio_intr_pb6 = 0x00000004, + regk_gio_intr_pb7 = 0x00000004, + regk_gio_intr_pb8 = 0x00000005, + regk_gio_intr_pb9 = 0x00000005, + regk_gio_intr_pc0 = 0x00000008, + regk_gio_intr_pc1 = 0x00000008, + regk_gio_intr_pc10 = 0x00000009, + regk_gio_intr_pc11 = 0x00000009, + regk_gio_intr_pc12 = 0x00000009, + regk_gio_intr_pc13 = 0x00000009, + regk_gio_intr_pc14 = 0x00000009, + regk_gio_intr_pc15 = 0x00000009, + regk_gio_intr_pc2 = 0x00000008, + regk_gio_intr_pc3 = 0x00000008, + regk_gio_intr_pc4 = 0x00000008, + regk_gio_intr_pc5 = 0x00000008, + regk_gio_intr_pc6 = 0x00000008, + regk_gio_intr_pc7 = 0x00000008, + regk_gio_intr_pc8 = 0x00000009, + regk_gio_intr_pc9 = 0x00000009, + regk_gio_intr_pd0 = 0x0000000c, + regk_gio_intr_pd1 = 0x0000000c, + regk_gio_intr_pd10 = 0x0000000d, + regk_gio_intr_pd11 = 0x0000000d, + regk_gio_intr_pd12 = 0x0000000d, + regk_gio_intr_pd13 = 0x0000000d, + regk_gio_intr_pd14 = 0x0000000d, + regk_gio_intr_pd15 = 0x0000000d, + regk_gio_intr_pd16 = 0x0000000e, + regk_gio_intr_pd17 = 0x0000000e, + regk_gio_intr_pd18 = 0x0000000e, + regk_gio_intr_pd19 = 0x0000000e, + regk_gio_intr_pd2 = 0x0000000c, + regk_gio_intr_pd20 = 0x0000000e, + regk_gio_intr_pd21 = 0x0000000e, + regk_gio_intr_pd22 = 0x0000000e, + regk_gio_intr_pd23 = 0x0000000e, + regk_gio_intr_pd24 = 0x0000000f, + regk_gio_intr_pd25 = 0x0000000f, + regk_gio_intr_pd26 = 0x0000000f, + regk_gio_intr_pd27 = 0x0000000f, + regk_gio_intr_pd28 = 0x0000000f, + regk_gio_intr_pd29 = 0x0000000f, + regk_gio_intr_pd3 = 0x0000000c, + regk_gio_intr_pd30 = 0x0000000f, + regk_gio_intr_pd31 = 0x0000000f, + regk_gio_intr_pd4 = 0x0000000c, + regk_gio_intr_pd5 = 0x0000000c, + regk_gio_intr_pd6 = 0x0000000c, + regk_gio_intr_pd7 = 0x0000000c, + regk_gio_intr_pd8 = 0x0000000d, + regk_gio_intr_pd9 = 0x0000000d, + regk_gio_lo = 0x00000002, + regk_gio_lsb = 0x00000000, + regk_gio_msb = 0x00000001, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_no_switch = 0x0000003f, + regk_gio_none = 0x00000007, + regk_gio_off = 0x00000000, + regk_gio_opendrain = 0x00000000, + regk_gio_out = 0x00000001, + regk_gio_posedge = 0x00000005, + regk_gio_pwm_hfp = 0x00000002, + regk_gio_pwm_pa0 = 0x00000001, + regk_gio_pwm_pa19 = 0x00000004, + regk_gio_pwm_pa6 = 0x00000002, + regk_gio_pwm_pa7 = 0x00000003, + regk_gio_pwm_pb26 = 0x00000005, + regk_gio_pwm_pd23 = 0x00000006, + regk_gio_pwm_pd31 = 0x00000007, + regk_gio_pwm_std = 0x00000001, + regk_gio_pwm_var = 0x00000003, + regk_gio_rw_i2c0_cfg_default = 0x00000020, + regk_gio_rw_i2c0_ctrl_default = 0x00010000, + regk_gio_rw_i2c0_start_default = 0x00000000, + regk_gio_rw_i2c1_cfg_default = 0x00000aa0, + regk_gio_rw_i2c1_ctrl_default = 0x00010000, + regk_gio_rw_i2c1_start_default = 0x00000000, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_ppwm_data_default = 0x00000000, + regk_gio_rw_pwm0_ctrl_default = 0x00000000, + regk_gio_rw_pwm1_ctrl_default = 0x00000000, + regk_gio_rw_pwm2_ctrl_default = 0x00000000, + regk_gio_rw_pwm_in_cfg_default = 0x00000000, + regk_gio_sda0 = 0x00000000, + regk_gio_sda1 = 0x00000001, + regk_gio_sda2 = 0x00000002, + regk_gio_sda3 = 0x00000003, + regk_gio_sen = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h new file mode 100644 index 000000000000..bea699aa480e --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h @@ -0,0 +1,46 @@ +/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr + from intr_vect.r */ + +#ifndef _INTR_VECT_R +#define _INTR_VECT_R +#define TIMER0_INTR_VECT 0x31 +#define TIMER1_INTR_VECT 0x32 +#define DMA0_INTR_VECT 0x33 +#define DMA1_INTR_VECT 0x34 +#define DMA2_INTR_VECT 0x35 +#define DMA3_INTR_VECT 0x36 +#define DMA4_INTR_VECT 0x37 +#define DMA5_INTR_VECT 0x38 +#define DMA6_INTR_VECT 0x39 +#define DMA7_INTR_VECT 0x3a +#define DMA9_INTR_VECT 0x3b +#define DMA11_INTR_VECT 0x3c +#define GIO_INTR_VECT 0x3d +#define IOP0_INTR_VECT 0x3e +#define IOP1_INTR_VECT 0x3f +#define SER0_INTR_VECT 0x40 +#define SER1_INTR_VECT 0x41 +#define SER2_INTR_VECT 0x42 +#define SER3_INTR_VECT 0x43 +#define SER4_INTR_VECT 0x44 +#define SSER_INTR_VECT 0x45 +#define STRDMA0_INTR_VECT 0x46 +#define STRDMA1_INTR_VECT 0x47 +#define STRDMA2_INTR_VECT 0x48 +#define STRDMA3_INTR_VECT 0x49 +#define STRDMA5_INTR_VECT 0x4a +#define VIN_INTR_VECT 0x4b +#define VOUT_INTR_VECT 0x4c +#define JPEG_INTR_VECT 0x4d +#define H264_INTR_VECT 0x4e +#define HISTO_INTR_VECT 0x4f +#define CCD_INTR_VECT 0x50 +#define ETH_INTR_VECT 0x51 +#define MEMARB_BAR_INTR_VECT 0x52 +#define MEMARB_FOO_INTR_VECT 0x53 +#define PIO_INTR_VECT 0x54 +#define SCLR_INTR_VECT 0x55 +#define SCLR_FIFO_INTR_VECT 0x56 +#define IPI_INTR_VECT 0x57 +#define NBR_INTR_VECT 0x58 +#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h new file mode 100644 index 000000000000..b820f6347c74 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h @@ -0,0 +1,341 @@ +#ifndef __intr_vect_defs_h +#define __intr_vect_defs_h + +/* + * This file is autogenerated from + * file: intr_vect.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope intr_vect */ + + +#define STRIDE_intr_vect_rw_mask 4 +/* Register rw_mask0, scope intr_vect, type rw */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_rw_mask0; +#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 +#define REG_RD_ADDR_intr_vect_rw_mask 0 +#define REG_WR_ADDR_intr_vect_rw_mask 0 +#define REG_RD_ADDR_intr_vect_rw_mask0 0 +#define REG_WR_ADDR_intr_vect_rw_mask0 0 + +#define STRIDE_intr_vect_r_vect 4 +/* Register r_vect0, scope intr_vect, type r */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_r_vect0; +#define reg_intr_vect_r_vect reg_intr_vect_r_vect0 +#define REG_RD_ADDR_intr_vect_r_vect 8 +#define REG_RD_ADDR_intr_vect_r_vect0 8 + +#define STRIDE_intr_vect_r_masked_vect 4 +/* Register r_masked_vect0, scope intr_vect, type r */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_r_masked_vect0; +#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 +#define REG_RD_ADDR_intr_vect_r_masked_vect0 16 +#define REG_RD_ADDR_intr_vect_r_masked_vect 16 + +#define STRIDE_intr_vect_rw_xmask 4 +/* Register rw_xmask0, scope intr_vect, type rw */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_rw_xmask0; +#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 +#define REG_RD_ADDR_intr_vect_rw_xmask0 24 +#define REG_WR_ADDR_intr_vect_rw_xmask0 24 +#define REG_RD_ADDR_intr_vect_rw_xmask 24 +#define REG_WR_ADDR_intr_vect_rw_xmask 24 + +/* Register rw_mask1, scope intr_vect, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_rw_mask1; +#define REG_RD_ADDR_intr_vect_rw_mask1 4 +#define REG_WR_ADDR_intr_vect_rw_mask1 4 + +/* Register r_vect1, scope intr_vect, type r */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_r_vect1; +#define REG_RD_ADDR_intr_vect_r_vect1 12 + +/* Register r_masked_vect1, scope intr_vect, type r */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_r_masked_vect1; +#define REG_RD_ADDR_intr_vect_r_masked_vect1 20 + +/* Register rw_xmask1, scope intr_vect, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_rw_xmask1; +#define REG_RD_ADDR_intr_vect_rw_xmask1 28 +#define REG_WR_ADDR_intr_vect_rw_xmask1 28 + +/* Register rw_xmask_ctrl, scope intr_vect, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_rw_xmask_ctrl; +#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 +#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 + +/* Register r_nmi, scope intr_vect, type r */ +typedef struct { + unsigned int watchdog0 : 1; + unsigned int watchdog1 : 1; + unsigned int dummy1 : 30; +} reg_intr_vect_r_nmi; +#define REG_RD_ADDR_intr_vect_r_nmi 64 + +/* Register r_guru, scope intr_vect, type r */ +typedef struct { + unsigned int jtag : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_r_guru; +#define REG_RD_ADDR_intr_vect_r_guru 68 + + +/* Register rw_ipi, scope intr_vect, type rw */ +typedef struct +{ + unsigned int vector; +} reg_intr_vect_rw_ipi; +#define REG_RD_ADDR_intr_vect_rw_ipi 72 +#define REG_WR_ADDR_intr_vect_rw_ipi 72 + +/* Constants */ +enum { + regk_intr_vect_no = 0x00000000, + regk_intr_vect_rw_mask0_default = 0x00000000, + regk_intr_vect_rw_mask1_default = 0x00000000, + regk_intr_vect_rw_xmask0_default = 0x00000000, + regk_intr_vect_rw_xmask1_default = 0x00000000, + regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, + regk_intr_vect_yes = 0x00000001 +}; +#endif /* __intr_vect_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 000000000000..d75a74e90458 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h @@ -0,0 +1,31 @@ +/* Autogenerated Changes here will be lost! + * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg + */ +#define iop_version 0 +#define iop_fifo_in_extra 64 +#define iop_fifo_out_extra 128 +#define iop_trigger_grp0 192 +#define iop_trigger_grp1 256 +#define iop_trigger_grp2 320 +#define iop_trigger_grp3 384 +#define iop_trigger_grp4 448 +#define iop_trigger_grp5 512 +#define iop_trigger_grp6 576 +#define iop_trigger_grp7 640 +#define iop_crc_par 768 +#define iop_dmc_in 896 +#define iop_dmc_out 1024 +#define iop_fifo_in 1152 +#define iop_fifo_out 1280 +#define iop_scrc_in 1408 +#define iop_scrc_out 1536 +#define iop_timer_grp0 1664 +#define iop_timer_grp1 1792 +#define iop_sap_in 2048 +#define iop_sap_out 2304 +#define iop_spu 2560 +#define iop_sw_cfg 2816 +#define iop_sw_cpu 3072 +#define iop_sw_mpu 3328 +#define iop_sw_spu 3584 +#define iop_mpu 4096 diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 000000000000..7f90b5a0460d --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h @@ -0,0 +1,109 @@ +#ifndef __iop_sap_in_defs_asm_h +#define __iop_sap_in_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sap_in.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_sap_in_rw_bus_byte 4 +/* Register rw_bus_byte, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 +#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 +#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 +#define reg_iop_sap_in_rw_bus_byte___delay___width 2 +#define reg_iop_sap_in_rw_bus_byte_offset 0 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_gio___sync_sel___width 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_gio___sync_edge___width 2 +#define reg_iop_sap_in_rw_gio___delay___lsb 7 +#define reg_iop_sap_in_rw_gio___delay___width 2 +#define reg_iop_sap_in_rw_gio___logic___lsb 9 +#define reg_iop_sap_in_rw_gio___logic___width 2 +#define reg_iop_sap_in_rw_gio_offset 16 + + +/* Constants */ +#define regk_iop_sap_in_and 0x00000002 +#define regk_iop_sap_in_ext_clk200 0x00000003 +#define regk_iop_sap_in_gio0 0x00000000 +#define regk_iop_sap_in_gio12 0x00000003 +#define regk_iop_sap_in_gio16 0x00000004 +#define regk_iop_sap_in_gio20 0x00000005 +#define regk_iop_sap_in_gio24 0x00000006 +#define regk_iop_sap_in_gio28 0x00000007 +#define regk_iop_sap_in_gio4 0x00000001 +#define regk_iop_sap_in_gio8 0x00000002 +#define regk_iop_sap_in_inv 0x00000001 +#define regk_iop_sap_in_neg 0x00000002 +#define regk_iop_sap_in_no 0x00000000 +#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 +#define regk_iop_sap_in_none 0x00000000 +#define regk_iop_sap_in_one 0x00000001 +#define regk_iop_sap_in_or 0x00000003 +#define regk_iop_sap_in_pos 0x00000001 +#define regk_iop_sap_in_pos_neg 0x00000003 +#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 +#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 +#define regk_iop_sap_in_rw_gio_default 0x00000000 +#define regk_iop_sap_in_rw_gio_size 0x00000020 +#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 +#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 +#define regk_iop_sap_in_tmr_clk200 0x00000001 +#define regk_iop_sap_in_two 0x00000002 +#define regk_iop_sap_in_two_clk200 0x00000000 +#endif /* __iop_sap_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 000000000000..399bd656406b --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __iop_sap_out_defs_asm_h +#define __iop_sap_out_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sap_out.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 +#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated_offset 0 + +/* Register rw_bus, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 +#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 +#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 +#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 +#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 +#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 +#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 +#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 +#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 +#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 +#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 +#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 +#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 +#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 +#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 +#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 +#define reg_iop_sap_out_rw_bus_offset 4 + +/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 + +/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 +#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 +#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 +#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 +#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 +#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 +#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 +#define reg_iop_sap_out_rw_gio___out_delay___width 1 +#define reg_iop_sap_out_rw_gio___out_delay___bit 7 +#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 +#define reg_iop_sap_out_rw_gio___out_logic___width 2 +#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 +#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 +#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 +#define reg_iop_sap_out_rw_gio___oe_delay___width 1 +#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 +#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 +#define reg_iop_sap_out_rw_gio___oe_logic___width 2 +#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 +#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 +#define reg_iop_sap_out_rw_gio_offset 16 + + +/* Constants */ +#define regk_iop_sap_out_always 0x00000001 +#define regk_iop_sap_out_and 0x00000002 +#define regk_iop_sap_out_clk0 0x00000000 +#define regk_iop_sap_out_clk1 0x00000001 +#define regk_iop_sap_out_clk12 0x00000004 +#define regk_iop_sap_out_clk200 0x00000000 +#define regk_iop_sap_out_ext 0x00000002 +#define regk_iop_sap_out_gated 0x00000003 +#define regk_iop_sap_out_gio0 0x00000000 +#define regk_iop_sap_out_gio1 0x00000000 +#define regk_iop_sap_out_gio16 0x00000002 +#define regk_iop_sap_out_gio17 0x00000002 +#define regk_iop_sap_out_gio24 0x00000003 +#define regk_iop_sap_out_gio25 0x00000003 +#define regk_iop_sap_out_gio8 0x00000001 +#define regk_iop_sap_out_gio9 0x00000001 +#define regk_iop_sap_out_gio_out10 0x00000005 +#define regk_iop_sap_out_gio_out18 0x00000006 +#define regk_iop_sap_out_gio_out2 0x00000004 +#define regk_iop_sap_out_gio_out26 0x00000007 +#define regk_iop_sap_out_inv 0x00000001 +#define regk_iop_sap_out_nand 0x00000003 +#define regk_iop_sap_out_no 0x00000000 +#define regk_iop_sap_out_none 0x00000000 +#define regk_iop_sap_out_one 0x00000001 +#define regk_iop_sap_out_rw_bus_default 0x00000000 +#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 +#define regk_iop_sap_out_rw_gio_default 0x00000000 +#define regk_iop_sap_out_rw_gio_size 0x00000020 +#define regk_iop_sap_out_spu_gio6 0x00000002 +#define regk_iop_sap_out_spu_gio7 0x00000003 +#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 +#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 +#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 +#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 +#define regk_iop_sap_out_tmr200 0x00000001 +#define regk_iop_sap_out_yes 0x00000001 +#endif /* __iop_sap_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 000000000000..3b3949b51a66 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h @@ -0,0 +1,739 @@ +#ifndef __iop_sw_cfg_defs_asm_h +#define __iop_sw_cfg_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_cfg.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 + +/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 + +/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 + +/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 + +/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 + +/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 + +/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 + +/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 + +/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 + +/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 +#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 +#define reg_iop_sw_cfg_rw_spu_owner_offset 44 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 + +/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus_mask_offset 88 + +/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_mask_offset 96 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 +#define reg_iop_sw_cfg_rw_pinmapping_offset 104 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 + +/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 +#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 + +/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 +#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 + + +/* Constants */ +#define regk_iop_sw_cfg_a 0x00000001 +#define regk_iop_sw_cfg_b 0x00000002 +#define regk_iop_sw_cfg_bus 0x00000000 +#define regk_iop_sw_cfg_bus_rot16 0x00000002 +#define regk_iop_sw_cfg_bus_rot24 0x00000003 +#define regk_iop_sw_cfg_bus_rot8 0x00000001 +#define regk_iop_sw_cfg_clk12 0x00000000 +#define regk_iop_sw_cfg_cpu 0x00000000 +#define regk_iop_sw_cfg_gated_clk0 0x0000000e +#define regk_iop_sw_cfg_gated_clk1 0x0000000f +#define regk_iop_sw_cfg_gio0 0x00000004 +#define regk_iop_sw_cfg_gio1 0x00000001 +#define regk_iop_sw_cfg_gio2 0x00000005 +#define regk_iop_sw_cfg_gio3 0x00000002 +#define regk_iop_sw_cfg_gio4 0x00000006 +#define regk_iop_sw_cfg_gio5 0x00000003 +#define regk_iop_sw_cfg_gio6 0x00000007 +#define regk_iop_sw_cfg_gio7 0x00000004 +#define regk_iop_sw_cfg_gio_in18 0x00000002 +#define regk_iop_sw_cfg_gio_in19 0x00000003 +#define regk_iop_sw_cfg_gio_in20 0x00000004 +#define regk_iop_sw_cfg_gio_in21 0x00000005 +#define regk_iop_sw_cfg_gio_in26 0x00000006 +#define regk_iop_sw_cfg_gio_in27 0x00000007 +#define regk_iop_sw_cfg_gio_in4 0x00000000 +#define regk_iop_sw_cfg_gio_in5 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 +#define regk_iop_sw_cfg_mpu 0x00000001 +#define regk_iop_sw_cfg_none 0x00000000 +#define regk_iop_sw_cfg_pdp_out 0x00000001 +#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 +#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 +#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 +#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 +#define regk_iop_sw_cfg_sdp_out 0x00000004 +#define regk_iop_sw_cfg_size16 0x00000002 +#define regk_iop_sw_cfg_size24 0x00000003 +#define regk_iop_sw_cfg_size32 0x00000004 +#define regk_iop_sw_cfg_size8 0x00000001 +#define regk_iop_sw_cfg_spu 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 +#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 +#define regk_iop_sw_cfg_spu_g0 0x00000007 +#define regk_iop_sw_cfg_spu_g1 0x00000007 +#define regk_iop_sw_cfg_spu_g2 0x00000007 +#define regk_iop_sw_cfg_spu_g3 0x00000007 +#define regk_iop_sw_cfg_spu_g4 0x00000007 +#define regk_iop_sw_cfg_spu_g5 0x00000007 +#define regk_iop_sw_cfg_spu_g6 0x00000007 +#define regk_iop_sw_cfg_spu_g7 0x00000007 +#define regk_iop_sw_cfg_spu_gio0 0x00000000 +#define regk_iop_sw_cfg_spu_gio1 0x00000001 +#define regk_iop_sw_cfg_spu_gio5 0x00000005 +#define regk_iop_sw_cfg_spu_gio6 0x00000006 +#define regk_iop_sw_cfg_spu_gio7 0x00000007 +#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu_gioout0 0x00000000 +#define regk_iop_sw_cfg_spu_gioout1 0x00000000 +#define regk_iop_sw_cfg_spu_gioout10 0x00000007 +#define regk_iop_sw_cfg_spu_gioout11 0x00000007 +#define regk_iop_sw_cfg_spu_gioout12 0x00000007 +#define regk_iop_sw_cfg_spu_gioout13 0x00000007 +#define regk_iop_sw_cfg_spu_gioout14 0x00000007 +#define regk_iop_sw_cfg_spu_gioout15 0x00000007 +#define regk_iop_sw_cfg_spu_gioout16 0x00000007 +#define regk_iop_sw_cfg_spu_gioout17 0x00000007 +#define regk_iop_sw_cfg_spu_gioout18 0x00000007 +#define regk_iop_sw_cfg_spu_gioout19 0x00000007 +#define regk_iop_sw_cfg_spu_gioout2 0x00000001 +#define regk_iop_sw_cfg_spu_gioout20 0x00000007 +#define regk_iop_sw_cfg_spu_gioout21 0x00000007 +#define regk_iop_sw_cfg_spu_gioout22 0x00000007 +#define regk_iop_sw_cfg_spu_gioout23 0x00000007 +#define regk_iop_sw_cfg_spu_gioout24 0x00000007 +#define regk_iop_sw_cfg_spu_gioout25 0x00000007 +#define regk_iop_sw_cfg_spu_gioout26 0x00000007 +#define regk_iop_sw_cfg_spu_gioout27 0x00000007 +#define regk_iop_sw_cfg_spu_gioout28 0x00000007 +#define regk_iop_sw_cfg_spu_gioout29 0x00000007 +#define regk_iop_sw_cfg_spu_gioout3 0x00000001 +#define regk_iop_sw_cfg_spu_gioout30 0x00000007 +#define regk_iop_sw_cfg_spu_gioout31 0x00000007 +#define regk_iop_sw_cfg_spu_gioout4 0x00000002 +#define regk_iop_sw_cfg_spu_gioout5 0x00000002 +#define regk_iop_sw_cfg_spu_gioout6 0x00000003 +#define regk_iop_sw_cfg_spu_gioout7 0x00000003 +#define regk_iop_sw_cfg_spu_gioout8 0x00000007 +#define regk_iop_sw_cfg_spu_gioout9 0x00000007 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 +#define regk_iop_sw_cfg_timer_grp0 0x00000000 +#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 +#define regk_iop_sw_cfg_timer_grp1 0x00000000 +#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 +#define regk_iop_sw_cfg_trig0_0 0x00000000 +#define regk_iop_sw_cfg_trig0_1 0x00000000 +#define regk_iop_sw_cfg_trig0_2 0x00000000 +#define regk_iop_sw_cfg_trig0_3 0x00000000 +#define regk_iop_sw_cfg_trig1_0 0x00000000 +#define regk_iop_sw_cfg_trig1_1 0x00000000 +#define regk_iop_sw_cfg_trig1_2 0x00000000 +#define regk_iop_sw_cfg_trig1_3 0x00000000 +#define regk_iop_sw_cfg_trig2_0 0x00000001 +#define regk_iop_sw_cfg_trig2_1 0x00000001 +#define regk_iop_sw_cfg_trig2_2 0x00000001 +#define regk_iop_sw_cfg_trig2_3 0x00000001 +#define regk_iop_sw_cfg_trig3_0 0x00000001 +#define regk_iop_sw_cfg_trig3_1 0x00000001 +#define regk_iop_sw_cfg_trig3_2 0x00000001 +#define regk_iop_sw_cfg_trig3_3 0x00000001 +#define regk_iop_sw_cfg_trig4_0 0x00000002 +#define regk_iop_sw_cfg_trig4_1 0x00000002 +#define regk_iop_sw_cfg_trig4_2 0x00000002 +#define regk_iop_sw_cfg_trig4_3 0x00000002 +#define regk_iop_sw_cfg_trig5_0 0x00000002 +#define regk_iop_sw_cfg_trig5_1 0x00000002 +#define regk_iop_sw_cfg_trig5_2 0x00000002 +#define regk_iop_sw_cfg_trig5_3 0x00000002 +#define regk_iop_sw_cfg_trig6_0 0x00000003 +#define regk_iop_sw_cfg_trig6_1 0x00000003 +#define regk_iop_sw_cfg_trig6_2 0x00000003 +#define regk_iop_sw_cfg_trig6_3 0x00000003 +#define regk_iop_sw_cfg_trig7_0 0x00000003 +#define regk_iop_sw_cfg_trig7_1 0x00000003 +#define regk_iop_sw_cfg_trig7_2 0x00000003 +#define regk_iop_sw_cfg_trig7_3 0x00000003 +#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 000000000000..3f4fe1b31815 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h @@ -0,0 +1,950 @@ +#ifndef __iop_sw_cpu_defs_asm_h +#define __iop_sw_cpu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_cpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_mpu_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mpu_trace_offset 0 + +/* Register r_spu_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_spu_trace_offset 4 + +/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_cpu_rw_mc_data___val___width 32 +#define reg_iop_sw_cpu_rw_mc_data_offset 16 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_addr_offset 20 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +#define reg_iop_sw_cpu_rs_mc_data_offset 24 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_data_offset 28 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_cpu_r_mc_stat_offset 32 + +/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 + +/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 + +/* Register r_bus_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus_in_offset 52 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_gio_in_offset 72 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 +#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_r_intr0_offset 84 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_r_masked_intr0_offset 88 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 +#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 +#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 +#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 +#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 +#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 +#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 +#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 +#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 +#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 +#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_intr1_offset 100 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_masked_intr1_offset 104 + + +/* Constants */ +#define regk_iop_sw_cpu_copy 0x00000000 +#define regk_iop_sw_cpu_no 0x00000000 +#define regk_iop_sw_cpu_rd 0x00000002 +#define regk_iop_sw_cpu_reg_copy 0x00000001 +#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 +#define regk_iop_sw_cpu_wr 0x00000003 +#define regk_iop_sw_cpu_yes 0x00000001 +#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 000000000000..ffcc83b22d21 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h @@ -0,0 +1,1086 @@ +#ifndef __iop_sw_mpu_defs_asm_h +#define __iop_sw_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_mpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 +#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 + +/* Register r_spu_trace, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_spu_trace_offset 4 + +/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_mpu_rw_mc_data___val___width 32 +#define reg_iop_sw_mpu_rw_mc_data_offset 16 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_addr_offset 20 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +#define reg_iop_sw_mpu_rs_mc_data_offset 24 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_data_offset 28 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_mpu_r_mc_stat_offset 32 + +/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 + +/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 + +/* Register r_bus_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus_in_offset 52 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_gio_in_offset 72 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_r_cpu_intr_offset 80 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp0_offset 92 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp1_offset 108 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp2_offset 124 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp3_offset 140 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 + + +/* Constants */ +#define regk_iop_sw_mpu_copy 0x00000000 +#define regk_iop_sw_mpu_cpu 0x00000000 +#define regk_iop_sw_mpu_mpu 0x00000001 +#define regk_iop_sw_mpu_no 0x00000000 +#define regk_iop_sw_mpu_nop 0x00000000 +#define regk_iop_sw_mpu_rd 0x00000002 +#define regk_iop_sw_mpu_reg_copy 0x00000001 +#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 +#define regk_iop_sw_mpu_set 0x00000001 +#define regk_iop_sw_mpu_spu 0x00000002 +#define regk_iop_sw_mpu_wr 0x00000003 +#define regk_iop_sw_mpu_yes 0x00000001 +#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 000000000000..67a745338087 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h @@ -0,0 +1,523 @@ +#ifndef __iop_sw_spu_defs_asm_h +#define __iop_sw_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_spu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_mpu_trace, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_trace_offset 0 + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_spu_rw_mc_data___val___width 32 +#define reg_iop_sw_spu_rw_mc_data_offset 8 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_addr_offset 12 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +#define reg_iop_sw_spu_rs_mc_data_offset 16 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_data_offset 20 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_spu_r_mc_stat_offset 24 + +/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 + +/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 + +/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 + +/* Register r_bus_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus_in_offset 44 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_gio_in_offset 64 + +/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 + +/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 + +/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 + +/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_cpu_intr_offset 116 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_cpu_intr_offset 120 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 +#define reg_iop_sw_spu_r_hw_intr_offset 124 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_mpu_intr_offset 128 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_mpu_intr_offset 132 + + +/* Constants */ +#define regk_iop_sw_spu_copy 0x00000000 +#define regk_iop_sw_spu_no 0x00000000 +#define regk_iop_sw_spu_nop 0x00000000 +#define regk_iop_sw_spu_rd 0x00000002 +#define regk_iop_sw_spu_reg_copy 0x00000001 +#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_spu_set 0x00000001 +#define regk_iop_sw_spu_wr 0x00000003 +#define regk_iop_sw_spu_yes 0x00000001 +#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 000000000000..4ad671202af0 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h @@ -0,0 +1,61 @@ +#ifndef __iop_version_defs_asm_h +#define __iop_version_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_version.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_version, scope iop_version, type r */ +#define reg_iop_version_r_version___nr___lsb 0 +#define reg_iop_version_r_version___nr___width 8 +#define reg_iop_version_r_version_offset 0 + + +/* Constants */ +#define regk_iop_version_v2_0 0x00000002 +#endif /* __iop_version_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h new file mode 100644 index 000000000000..af3196c60a46 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h @@ -0,0 +1,31 @@ +/* Autogenerated Changes here will be lost! + * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg + */ +#define regi_iop_version (regi_iop + 0) +#define regi_iop_fifo_in_extra (regi_iop + 64) +#define regi_iop_fifo_out_extra (regi_iop + 128) +#define regi_iop_trigger_grp0 (regi_iop + 192) +#define regi_iop_trigger_grp1 (regi_iop + 256) +#define regi_iop_trigger_grp2 (regi_iop + 320) +#define regi_iop_trigger_grp3 (regi_iop + 384) +#define regi_iop_trigger_grp4 (regi_iop + 448) +#define regi_iop_trigger_grp5 (regi_iop + 512) +#define regi_iop_trigger_grp6 (regi_iop + 576) +#define regi_iop_trigger_grp7 (regi_iop + 640) +#define regi_iop_crc_par (regi_iop + 768) +#define regi_iop_dmc_in (regi_iop + 896) +#define regi_iop_dmc_out (regi_iop + 1024) +#define regi_iop_fifo_in (regi_iop + 1152) +#define regi_iop_fifo_out (regi_iop + 1280) +#define regi_iop_scrc_in (regi_iop + 1408) +#define regi_iop_scrc_out (regi_iop + 1536) +#define regi_iop_timer_grp0 (regi_iop + 1664) +#define regi_iop_timer_grp1 (regi_iop + 1792) +#define regi_iop_sap_in (regi_iop + 2048) +#define regi_iop_sap_out (regi_iop + 2304) +#define regi_iop_spu (regi_iop + 2560) +#define regi_iop_sw_cfg (regi_iop + 2816) +#define regi_iop_sw_cpu (regi_iop + 3072) +#define regi_iop_sw_mpu (regi_iop + 3328) +#define regi_iop_sw_spu (regi_iop + 3584) +#define regi_iop_mpu (regi_iop + 4096) diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 000000000000..51dde016c03a --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h @@ -0,0 +1,141 @@ +#ifndef __iop_sap_in_defs_h +#define __iop_sap_in_defs_h + +/* + * This file is autogenerated from + * file: iop_sap_in.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_in */ + +#define STRIDE_iop_sap_in_rw_bus_byte 4 +/* Register rw_bus_byte, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 2; + unsigned int dummy1 : 23; +} reg_iop_sap_in_rw_bus_byte; +#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 +#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 2; + unsigned int logic : 2; + unsigned int dummy1 : 21; +} reg_iop_sap_in_rw_gio; +#define REG_RD_ADDR_iop_sap_in_rw_gio 16 +#define REG_WR_ADDR_iop_sap_in_rw_gio 16 + + +/* Constants */ +enum { + regk_iop_sap_in_and = 0x00000002, + regk_iop_sap_in_ext_clk200 = 0x00000003, + regk_iop_sap_in_gio0 = 0x00000000, + regk_iop_sap_in_gio12 = 0x00000003, + regk_iop_sap_in_gio16 = 0x00000004, + regk_iop_sap_in_gio20 = 0x00000005, + regk_iop_sap_in_gio24 = 0x00000006, + regk_iop_sap_in_gio28 = 0x00000007, + regk_iop_sap_in_gio4 = 0x00000001, + regk_iop_sap_in_gio8 = 0x00000002, + regk_iop_sap_in_inv = 0x00000001, + regk_iop_sap_in_neg = 0x00000002, + regk_iop_sap_in_no = 0x00000000, + regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, + regk_iop_sap_in_none = 0x00000000, + regk_iop_sap_in_one = 0x00000001, + regk_iop_sap_in_or = 0x00000003, + regk_iop_sap_in_pos = 0x00000001, + regk_iop_sap_in_pos_neg = 0x00000003, + regk_iop_sap_in_rw_bus_byte_default = 0x00000000, + regk_iop_sap_in_rw_bus_byte_size = 0x00000004, + regk_iop_sap_in_rw_gio_default = 0x00000000, + regk_iop_sap_in_rw_gio_size = 0x00000020, + regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, + regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, + regk_iop_sap_in_tmr_clk200 = 0x00000001, + regk_iop_sap_in_two = 0x00000002, + regk_iop_sap_in_two_clk200 = 0x00000000 +}; +#endif /* __iop_sap_in_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 000000000000..5af88baa2ac1 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h @@ -0,0 +1,231 @@ +#ifndef __iop_sap_out_defs_h +#define __iop_sap_out_defs_h + +/* + * This file is autogenerated from + * file: iop_sap_out.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_out */ + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +typedef struct { + unsigned int clk0_src : 2; + unsigned int clk0_gate_src : 2; + unsigned int clk0_force_src : 3; + unsigned int clk1_src : 2; + unsigned int clk1_gate_src : 2; + unsigned int clk1_force_src : 3; + unsigned int dummy1 : 18; +} reg_iop_sap_out_rw_gen_gated; +#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 +#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 + +/* Register rw_bus, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 2; + unsigned int byte0_clk_ext : 2; + unsigned int byte0_gated_clk : 1; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_delay : 1; + unsigned int byte1_clk_sel : 2; + unsigned int byte1_clk_ext : 2; + unsigned int byte1_gated_clk : 1; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_delay : 1; + unsigned int byte2_clk_sel : 2; + unsigned int byte2_clk_ext : 2; + unsigned int byte2_gated_clk : 1; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_delay : 1; + unsigned int byte3_clk_sel : 2; + unsigned int byte3_clk_ext : 2; + unsigned int byte3_gated_clk : 1; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_delay : 1; + unsigned int dummy1 : 4; +} reg_iop_sap_out_rw_bus; +#define REG_RD_ADDR_iop_sap_out_rw_bus 4 +#define REG_WR_ADDR_iop_sap_out_rw_bus 4 + +/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 2; + unsigned int byte0_clk_ext : 2; + unsigned int byte0_gated_clk : 1; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_delay : 1; + unsigned int byte0_logic : 2; + unsigned int byte0_logic_src : 2; + unsigned int byte1_clk_sel : 2; + unsigned int byte1_clk_ext : 2; + unsigned int byte1_gated_clk : 1; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_delay : 1; + unsigned int byte1_logic : 2; + unsigned int byte1_logic_src : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 +#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 + +/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 2; + unsigned int byte2_clk_ext : 2; + unsigned int byte2_gated_clk : 1; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_delay : 1; + unsigned int byte2_logic : 2; + unsigned int byte2_logic_src : 2; + unsigned int byte3_clk_sel : 2; + unsigned int byte3_clk_ext : 2; + unsigned int byte3_gated_clk : 1; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_delay : 1; + unsigned int byte3_logic : 2; + unsigned int byte3_logic_src : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 +#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +typedef struct { + unsigned int out_clk_sel : 3; + unsigned int out_clk_ext : 2; + unsigned int out_gated_clk : 1; + unsigned int out_clk_inv : 1; + unsigned int out_delay : 1; + unsigned int out_logic : 2; + unsigned int out_logic_src : 2; + unsigned int oe_clk_sel : 3; + unsigned int oe_clk_ext : 2; + unsigned int oe_gated_clk : 1; + unsigned int oe_clk_inv : 1; + unsigned int oe_delay : 1; + unsigned int oe_logic : 2; + unsigned int oe_logic_src : 2; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_gio; +#define REG_RD_ADDR_iop_sap_out_rw_gio 16 +#define REG_WR_ADDR_iop_sap_out_rw_gio 16 + + +/* Constants */ +enum { + regk_iop_sap_out_always = 0x00000001, + regk_iop_sap_out_and = 0x00000002, + regk_iop_sap_out_clk0 = 0x00000000, + regk_iop_sap_out_clk1 = 0x00000001, + regk_iop_sap_out_clk12 = 0x00000004, + regk_iop_sap_out_clk200 = 0x00000000, + regk_iop_sap_out_ext = 0x00000002, + regk_iop_sap_out_gated = 0x00000003, + regk_iop_sap_out_gio0 = 0x00000000, + regk_iop_sap_out_gio1 = 0x00000000, + regk_iop_sap_out_gio16 = 0x00000002, + regk_iop_sap_out_gio17 = 0x00000002, + regk_iop_sap_out_gio24 = 0x00000003, + regk_iop_sap_out_gio25 = 0x00000003, + regk_iop_sap_out_gio8 = 0x00000001, + regk_iop_sap_out_gio9 = 0x00000001, + regk_iop_sap_out_gio_out10 = 0x00000005, + regk_iop_sap_out_gio_out18 = 0x00000006, + regk_iop_sap_out_gio_out2 = 0x00000004, + regk_iop_sap_out_gio_out26 = 0x00000007, + regk_iop_sap_out_inv = 0x00000001, + regk_iop_sap_out_nand = 0x00000003, + regk_iop_sap_out_no = 0x00000000, + regk_iop_sap_out_none = 0x00000000, + regk_iop_sap_out_one = 0x00000001, + regk_iop_sap_out_rw_bus_default = 0x00000000, + regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_gen_gated_default = 0x00000000, + regk_iop_sap_out_rw_gio_default = 0x00000000, + regk_iop_sap_out_rw_gio_size = 0x00000020, + regk_iop_sap_out_spu_gio6 = 0x00000002, + regk_iop_sap_out_spu_gio7 = 0x00000003, + regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, + regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, + regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, + regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, + regk_iop_sap_out_tmr200 = 0x00000001, + regk_iop_sap_out_yes = 0x00000001 +}; +#endif /* __iop_sap_out_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 000000000000..98ac95275a1c --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h @@ -0,0 +1,725 @@ +#ifndef __iop_sw_cfg_defs_h +#define __iop_sw_cfg_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_cfg.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cfg */ + +/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 + +/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 + +/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 + +/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 + +/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 + +/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 + +/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 + +/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 + +/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 + +/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 1; + unsigned int dummy1 : 31; +} reg_iop_sw_cfg_rw_spu_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp4_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp5_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp6_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp7_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 + +/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 + +/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus_byte0 : 2; + unsigned int bus_byte1 : 2; + unsigned int bus_byte2 : 2; + unsigned int bus_byte3 : 2; + unsigned int gio3_0 : 2; + unsigned int gio7_4 : 2; + unsigned int gio11_8 : 2; + unsigned int gio15_12 : 2; + unsigned int gio19_16 : 2; + unsigned int gio23_20 : 2; + unsigned int gio27_24 : 2; + unsigned int gio31_28 : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_pinmapping; +#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 +#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus_lo : 2; + unsigned int bus_hi : 2; + unsigned int bus_lo_oe : 2; + unsigned int bus_hi_oe : 2; + unsigned int dummy1 : 24; +} reg_iop_sw_cfg_rw_bus_out_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio0 : 3; + unsigned int gio0_oe : 1; + unsigned int gio1 : 3; + unsigned int gio1_oe : 1; + unsigned int gio2 : 3; + unsigned int gio2_oe : 1; + unsigned int gio3 : 3; + unsigned int gio3_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio4 : 3; + unsigned int gio4_oe : 1; + unsigned int gio5 : 3; + unsigned int gio5_oe : 1; + unsigned int gio6 : 3; + unsigned int gio6_oe : 1; + unsigned int gio7 : 3; + unsigned int gio7_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio8 : 3; + unsigned int gio8_oe : 1; + unsigned int gio9 : 3; + unsigned int gio9_oe : 1; + unsigned int gio10 : 3; + unsigned int gio10_oe : 1; + unsigned int gio11 : 3; + unsigned int gio11_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio12 : 3; + unsigned int gio12_oe : 1; + unsigned int gio13 : 3; + unsigned int gio13_oe : 1; + unsigned int gio14 : 3; + unsigned int gio14_oe : 1; + unsigned int gio15 : 3; + unsigned int gio15_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio16 : 3; + unsigned int gio16_oe : 1; + unsigned int gio17 : 3; + unsigned int gio17_oe : 1; + unsigned int gio18 : 3; + unsigned int gio18_oe : 1; + unsigned int gio19 : 3; + unsigned int gio19_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio20 : 3; + unsigned int gio20_oe : 1; + unsigned int gio21 : 3; + unsigned int gio21_oe : 1; + unsigned int gio22 : 3; + unsigned int gio22_oe : 1; + unsigned int gio23 : 3; + unsigned int gio23_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio24 : 3; + unsigned int gio24_oe : 1; + unsigned int gio25 : 3; + unsigned int gio25_oe : 1; + unsigned int gio26 : 3; + unsigned int gio26_oe : 1; + unsigned int gio27 : 3; + unsigned int gio27_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio28 : 3; + unsigned int gio28_oe : 1; + unsigned int gio29 : 3; + unsigned int gio29_oe : 1; + unsigned int gio30 : 3; + unsigned int gio30_oe : 1; + unsigned int gio31 : 3; + unsigned int gio31_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 + +/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 1; + unsigned int bus1_in : 1; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 2; + unsigned int tmr1_en : 2; + unsigned int tmr2_en : 2; + unsigned int tmr3_en : 2; + unsigned int tmr0_dis : 2; + unsigned int tmr1_dis : 2; + unsigned int tmr2_dis : 2; + unsigned int tmr3_dis : 2; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_timer_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 2; + unsigned int tmr1_en : 2; + unsigned int tmr2_en : 2; + unsigned int tmr3_en : 2; + unsigned int tmr0_dis : 2; + unsigned int tmr1_dis : 2; + unsigned int tmr2_dis : 2; + unsigned int tmr3_dis : 2; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_timer_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int grp0_dis : 1; + unsigned int grp0_en : 1; + unsigned int grp1_dis : 1; + unsigned int grp1_en : 1; + unsigned int grp2_dis : 1; + unsigned int grp2_en : 1; + unsigned int grp3_dis : 1; + unsigned int grp3_en : 1; + unsigned int grp4_dis : 1; + unsigned int grp4_en : 1; + unsigned int grp5_dis : 1; + unsigned int grp5_en : 1; + unsigned int grp6_dis : 1; + unsigned int grp6_en : 1; + unsigned int grp7_dis : 1; + unsigned int grp7_en : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_trigger_grps_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 + +/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int out_strb : 4; + unsigned int in_src : 2; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int dummy1 : 17; +} reg_iop_sw_cfg_rw_pdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int sdp_out_strb : 3; + unsigned int sdp_in_data : 3; + unsigned int sdp_in_last : 2; + unsigned int sdp_in_strb : 3; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_sdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 +#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 + + +/* Constants */ +enum { + regk_iop_sw_cfg_a = 0x00000001, + regk_iop_sw_cfg_b = 0x00000002, + regk_iop_sw_cfg_bus = 0x00000000, + regk_iop_sw_cfg_bus_rot16 = 0x00000002, + regk_iop_sw_cfg_bus_rot24 = 0x00000003, + regk_iop_sw_cfg_bus_rot8 = 0x00000001, + regk_iop_sw_cfg_clk12 = 0x00000000, + regk_iop_sw_cfg_cpu = 0x00000000, + regk_iop_sw_cfg_gated_clk0 = 0x0000000e, + regk_iop_sw_cfg_gated_clk1 = 0x0000000f, + regk_iop_sw_cfg_gio0 = 0x00000004, + regk_iop_sw_cfg_gio1 = 0x00000001, + regk_iop_sw_cfg_gio2 = 0x00000005, + regk_iop_sw_cfg_gio3 = 0x00000002, + regk_iop_sw_cfg_gio4 = 0x00000006, + regk_iop_sw_cfg_gio5 = 0x00000003, + regk_iop_sw_cfg_gio6 = 0x00000007, + regk_iop_sw_cfg_gio7 = 0x00000004, + regk_iop_sw_cfg_gio_in18 = 0x00000002, + regk_iop_sw_cfg_gio_in19 = 0x00000003, + regk_iop_sw_cfg_gio_in20 = 0x00000004, + regk_iop_sw_cfg_gio_in21 = 0x00000005, + regk_iop_sw_cfg_gio_in26 = 0x00000006, + regk_iop_sw_cfg_gio_in27 = 0x00000007, + regk_iop_sw_cfg_gio_in4 = 0x00000000, + regk_iop_sw_cfg_gio_in5 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, + regk_iop_sw_cfg_mpu = 0x00000001, + regk_iop_sw_cfg_none = 0x00000000, + regk_iop_sw_cfg_pdp_out = 0x00000001, + regk_iop_sw_cfg_pdp_out_hi = 0x00000001, + regk_iop_sw_cfg_pdp_out_lo = 0x00000000, + regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, + regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, + regk_iop_sw_cfg_sdp_out = 0x00000004, + regk_iop_sw_cfg_size16 = 0x00000002, + regk_iop_sw_cfg_size24 = 0x00000003, + regk_iop_sw_cfg_size32 = 0x00000004, + regk_iop_sw_cfg_size8 = 0x00000001, + regk_iop_sw_cfg_spu = 0x00000002, + regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, + regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, + regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, + regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, + regk_iop_sw_cfg_spu_g0 = 0x00000007, + regk_iop_sw_cfg_spu_g1 = 0x00000007, + regk_iop_sw_cfg_spu_g2 = 0x00000007, + regk_iop_sw_cfg_spu_g3 = 0x00000007, + regk_iop_sw_cfg_spu_g4 = 0x00000007, + regk_iop_sw_cfg_spu_g5 = 0x00000007, + regk_iop_sw_cfg_spu_g6 = 0x00000007, + regk_iop_sw_cfg_spu_g7 = 0x00000007, + regk_iop_sw_cfg_spu_gio0 = 0x00000000, + regk_iop_sw_cfg_spu_gio1 = 0x00000001, + regk_iop_sw_cfg_spu_gio5 = 0x00000005, + regk_iop_sw_cfg_spu_gio6 = 0x00000006, + regk_iop_sw_cfg_spu_gio7 = 0x00000007, + regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu_gioout0 = 0x00000000, + regk_iop_sw_cfg_spu_gioout1 = 0x00000000, + regk_iop_sw_cfg_spu_gioout10 = 0x00000007, + regk_iop_sw_cfg_spu_gioout11 = 0x00000007, + regk_iop_sw_cfg_spu_gioout12 = 0x00000007, + regk_iop_sw_cfg_spu_gioout13 = 0x00000007, + regk_iop_sw_cfg_spu_gioout14 = 0x00000007, + regk_iop_sw_cfg_spu_gioout15 = 0x00000007, + regk_iop_sw_cfg_spu_gioout16 = 0x00000007, + regk_iop_sw_cfg_spu_gioout17 = 0x00000007, + regk_iop_sw_cfg_spu_gioout18 = 0x00000007, + regk_iop_sw_cfg_spu_gioout19 = 0x00000007, + regk_iop_sw_cfg_spu_gioout2 = 0x00000001, + regk_iop_sw_cfg_spu_gioout20 = 0x00000007, + regk_iop_sw_cfg_spu_gioout21 = 0x00000007, + regk_iop_sw_cfg_spu_gioout22 = 0x00000007, + regk_iop_sw_cfg_spu_gioout23 = 0x00000007, + regk_iop_sw_cfg_spu_gioout24 = 0x00000007, + regk_iop_sw_cfg_spu_gioout25 = 0x00000007, + regk_iop_sw_cfg_spu_gioout26 = 0x00000007, + regk_iop_sw_cfg_spu_gioout27 = 0x00000007, + regk_iop_sw_cfg_spu_gioout28 = 0x00000007, + regk_iop_sw_cfg_spu_gioout29 = 0x00000007, + regk_iop_sw_cfg_spu_gioout3 = 0x00000001, + regk_iop_sw_cfg_spu_gioout30 = 0x00000007, + regk_iop_sw_cfg_spu_gioout31 = 0x00000007, + regk_iop_sw_cfg_spu_gioout4 = 0x00000002, + regk_iop_sw_cfg_spu_gioout5 = 0x00000002, + regk_iop_sw_cfg_spu_gioout6 = 0x00000003, + regk_iop_sw_cfg_spu_gioout7 = 0x00000003, + regk_iop_sw_cfg_spu_gioout8 = 0x00000007, + regk_iop_sw_cfg_spu_gioout9 = 0x00000007, + regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, + regk_iop_sw_cfg_timer_grp0 = 0x00000000, + regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, + regk_iop_sw_cfg_timer_grp1 = 0x00000000, + regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, + regk_iop_sw_cfg_trig0_0 = 0x00000000, + regk_iop_sw_cfg_trig0_1 = 0x00000000, + regk_iop_sw_cfg_trig0_2 = 0x00000000, + regk_iop_sw_cfg_trig0_3 = 0x00000000, + regk_iop_sw_cfg_trig1_0 = 0x00000000, + regk_iop_sw_cfg_trig1_1 = 0x00000000, + regk_iop_sw_cfg_trig1_2 = 0x00000000, + regk_iop_sw_cfg_trig1_3 = 0x00000000, + regk_iop_sw_cfg_trig2_0 = 0x00000001, + regk_iop_sw_cfg_trig2_1 = 0x00000001, + regk_iop_sw_cfg_trig2_2 = 0x00000001, + regk_iop_sw_cfg_trig2_3 = 0x00000001, + regk_iop_sw_cfg_trig3_0 = 0x00000001, + regk_iop_sw_cfg_trig3_1 = 0x00000001, + regk_iop_sw_cfg_trig3_2 = 0x00000001, + regk_iop_sw_cfg_trig3_3 = 0x00000001, + regk_iop_sw_cfg_trig4_0 = 0x00000002, + regk_iop_sw_cfg_trig4_1 = 0x00000002, + regk_iop_sw_cfg_trig4_2 = 0x00000002, + regk_iop_sw_cfg_trig4_3 = 0x00000002, + regk_iop_sw_cfg_trig5_0 = 0x00000002, + regk_iop_sw_cfg_trig5_1 = 0x00000002, + regk_iop_sw_cfg_trig5_2 = 0x00000002, + regk_iop_sw_cfg_trig5_3 = 0x00000002, + regk_iop_sw_cfg_trig6_0 = 0x00000003, + regk_iop_sw_cfg_trig6_1 = 0x00000003, + regk_iop_sw_cfg_trig6_2 = 0x00000003, + regk_iop_sw_cfg_trig6_3 = 0x00000003, + regk_iop_sw_cfg_trig7_0 = 0x00000003, + regk_iop_sw_cfg_trig7_1 = 0x00000003, + regk_iop_sw_cfg_trig7_2 = 0x00000003, + regk_iop_sw_cfg_trig7_3 = 0x00000003 +}; +#endif /* __iop_sw_cfg_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 000000000000..a16f556370eb --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h @@ -0,0 +1,522 @@ +#ifndef __iop_sw_cpu_defs_h +#define __iop_sw_cpu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_cpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cpu */ + +/* Register r_mpu_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 + +/* Register r_spu_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_spu_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 + +/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_cpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +typedef unsigned int reg_iop_sw_cpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_cpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 + +/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 + +/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 + +/* Register r_bus_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_rw_intr0_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_rw_ack_intr0; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_r_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_r_masked_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_rw_intr1_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr1; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_masked_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 + + +/* Constants */ +enum { + regk_iop_sw_cpu_copy = 0x00000000, + regk_iop_sw_cpu_no = 0x00000000, + regk_iop_sw_cpu_rd = 0x00000002, + regk_iop_sw_cpu_reg_copy = 0x00000001, + regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, + regk_iop_sw_cpu_wr = 0x00000003, + regk_iop_sw_cpu_yes = 0x00000001 +}; +#endif /* __iop_sw_cpu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 000000000000..a2e4e1a33e57 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h @@ -0,0 +1,648 @@ +#ifndef __iop_sw_mpu_defs_h +#define __iop_sw_mpu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_mpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_mpu */ + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_mpu_rw_sw_cfg_owner; +#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 +#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 + +/* Register r_spu_trace, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_spu_trace; +#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 + +/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; +#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_mpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +typedef unsigned int reg_iop_sw_mpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_mpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 + +/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 + +/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 + +/* Register r_bus_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 +#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp0_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr1 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr2 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr3 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp1_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr5 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr6 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr7 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp2_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr9 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr10 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr11 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp3_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr13 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr14 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr15 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 + + +/* Constants */ +enum { + regk_iop_sw_mpu_copy = 0x00000000, + regk_iop_sw_mpu_cpu = 0x00000000, + regk_iop_sw_mpu_mpu = 0x00000001, + regk_iop_sw_mpu_no = 0x00000000, + regk_iop_sw_mpu_nop = 0x00000000, + regk_iop_sw_mpu_rd = 0x00000002, + regk_iop_sw_mpu_reg_copy = 0x00000001, + regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, + regk_iop_sw_mpu_set = 0x00000001, + regk_iop_sw_mpu_spu = 0x00000002, + regk_iop_sw_mpu_wr = 0x00000003, + regk_iop_sw_mpu_yes = 0x00000001 +}; +#endif /* __iop_sw_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 000000000000..c8560b865a1a --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h @@ -0,0 +1,441 @@ +#ifndef __iop_sw_spu_defs_h +#define __iop_sw_spu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_spu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_spu */ + +/* Register r_mpu_trace, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mpu_trace; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_spu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +typedef unsigned int reg_iop_sw_spu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +typedef unsigned int reg_iop_sw_spu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mc_data; +#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_spu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 + +/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 + +/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 + +/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 + +/* Register r_bus_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_gio_in; +#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 + +/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 + +/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 + +/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 + +/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 +#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out : 1; + unsigned int fifo_out_extra : 1; + unsigned int fifo_in : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_out : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_hw_intr; +#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 +#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 + + +/* Constants */ +enum { + regk_iop_sw_spu_copy = 0x00000000, + regk_iop_sw_spu_no = 0x00000000, + regk_iop_sw_spu_nop = 0x00000000, + regk_iop_sw_spu_rd = 0x00000002, + regk_iop_sw_spu_reg_copy = 0x00000001, + regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_spu_set = 0x00000001, + regk_iop_sw_spu_wr = 0x00000003, + regk_iop_sw_spu_yes = 0x00000001 +}; +#endif /* __iop_sw_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h new file mode 100644 index 000000000000..20de425e652b --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h @@ -0,0 +1,96 @@ +#ifndef __iop_version_defs_h +#define __iop_version_defs_h + +/* + * This file is autogenerated from + * file: iop_version.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_version */ + +/* Register r_version, scope iop_version, type r */ +typedef struct { + unsigned int nr : 8; + unsigned int dummy1 : 24; +} reg_iop_version_r_version; +#define REG_RD_ADDR_iop_version_r_version 0 + + +/* Constants */ +enum { + regk_iop_version_v2_0 = 0x00000002 +}; +#endif /* __iop_version_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h new file mode 100644 index 000000000000..243ac3c882cb --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h @@ -0,0 +1,142 @@ +#ifndef __l2cache_defs_h +#define __l2cache_defs_h + +/* + * This file is autogenerated from + * file: l2cache.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope l2cache */ + +/* Register rw_cfg, scope l2cache, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_l2cache_rw_cfg; +#define REG_RD_ADDR_l2cache_rw_cfg 0 +#define REG_WR_ADDR_l2cache_rw_cfg 0 + +/* Register rw_ctrl, scope l2cache, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int cbase : 9; + unsigned int dummy2 : 4; + unsigned int csize : 10; + unsigned int dummy3 : 2; +} reg_l2cache_rw_ctrl; +#define REG_RD_ADDR_l2cache_rw_ctrl 4 +#define REG_WR_ADDR_l2cache_rw_ctrl 4 + +/* Register rw_idxop, scope l2cache, type rw */ +typedef struct { + unsigned int idx : 10; + unsigned int dummy1 : 14; + unsigned int way : 3; + unsigned int dummy2 : 2; + unsigned int cmd : 3; +} reg_l2cache_rw_idxop; +#define REG_RD_ADDR_l2cache_rw_idxop 8 +#define REG_WR_ADDR_l2cache_rw_idxop 8 + +/* Register rw_addrop_addr, scope l2cache, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_l2cache_rw_addrop_addr; +#define REG_RD_ADDR_l2cache_rw_addrop_addr 12 +#define REG_WR_ADDR_l2cache_rw_addrop_addr 12 + +/* Register rw_addrop_ctrl, scope l2cache, type rw */ +typedef struct { + unsigned int size : 16; + unsigned int dummy1 : 13; + unsigned int cmd : 3; +} reg_l2cache_rw_addrop_ctrl; +#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 +#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 + + +/* Constants */ +enum { + regk_l2cache_flush = 0x00000001, + regk_l2cache_no = 0x00000000, + regk_l2cache_rw_addrop_addr_default = 0x00000000, + regk_l2cache_rw_addrop_ctrl_default = 0x00000000, + regk_l2cache_rw_cfg_default = 0x00000000, + regk_l2cache_rw_ctrl_default = 0x00000000, + regk_l2cache_rw_idxop_default = 0x00000000, + regk_l2cache_yes = 0x00000001 +}; +#endif /* __l2cache_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h new file mode 100644 index 000000000000..c0e7628cbf7d --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h @@ -0,0 +1,482 @@ +#ifndef __marb_bar_defs_h +#define __marb_bar_defs_h + +/* + * This file is autogenerated from + * file: marb_bar.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bar */ + +#define STRIDE_marb_bar_rw_ddr2_slots 4 +/* Register rw_ddr2_slots, scope marb_bar, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_ddr2_slots; +#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 +#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 + +/* Register rw_h264_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_h264_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 +#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 + +/* Register rw_h264_wr_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_h264_wr_burst; +#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 +#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 + +/* Register rw_ccd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_ccd_burst; +#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 +#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 + +/* Register rw_vin_wr_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vin_wr_burst; +#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 +#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 + +/* Register rw_vin_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vin_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 +#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 + +/* Register rw_sclr_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_sclr_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 +#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 + +/* Register rw_vout_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vout_burst; +#define REG_RD_ADDR_marb_bar_rw_vout_burst 280 +#define REG_WR_ADDR_marb_bar_rw_vout_burst 280 + +/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_sclr_fifo_burst; +#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 +#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 + +/* Register rw_l2cache_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_l2cache_burst; +#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 +#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 + +/* Register rw_intr_mask, scope marb_bar, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_intr_mask; +#define REG_RD_ADDR_marb_bar_rw_intr_mask 292 +#define REG_WR_ADDR_marb_bar_rw_intr_mask 292 + +/* Register rw_ack_intr, scope marb_bar, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_ack_intr; +#define REG_RD_ADDR_marb_bar_rw_ack_intr 296 +#define REG_WR_ADDR_marb_bar_rw_ack_intr 296 + +/* Register r_intr, scope marb_bar, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_r_intr; +#define REG_RD_ADDR_marb_bar_r_intr 300 + +/* Register r_masked_intr, scope marb_bar, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_r_masked_intr; +#define REG_RD_ADDR_marb_bar_r_masked_intr 304 + +/* Register rw_stop_mask, scope marb_bar, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_rw_stop_mask; +#define REG_RD_ADDR_marb_bar_rw_stop_mask 308 +#define REG_WR_ADDR_marb_bar_rw_stop_mask 308 + +/* Register r_stopped, scope marb_bar, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_r_stopped; +#define REG_RD_ADDR_marb_bar_r_stopped 312 + +/* Register rw_no_snoop, scope marb_bar, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_rw_no_snoop; +#define REG_RD_ADDR_marb_bar_rw_no_snoop 576 +#define REG_WR_ADDR_marb_bar_rw_no_snoop 576 + + +/* Constants */ +enum { + regk_marb_bar_ccd = 0x00000002, + regk_marb_bar_h264_rd = 0x00000000, + regk_marb_bar_h264_wr = 0x00000001, + regk_marb_bar_l2cache = 0x00000008, + regk_marb_bar_no = 0x00000000, + regk_marb_bar_r_stopped_default = 0x00000000, + regk_marb_bar_rw_ccd_burst_default = 0x00000000, + regk_marb_bar_rw_ddr2_slots_default = 0x00000000, + regk_marb_bar_rw_ddr2_slots_size = 0x00000040, + regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, + regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, + regk_marb_bar_rw_intr_mask_default = 0x00000000, + regk_marb_bar_rw_l2cache_burst_default = 0x00000000, + regk_marb_bar_rw_no_snoop_default = 0x00000000, + regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, + regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, + regk_marb_bar_rw_stop_mask_default = 0x00000000, + regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, + regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, + regk_marb_bar_rw_vout_burst_default = 0x00000000, + regk_marb_bar_sclr_fifo = 0x00000007, + regk_marb_bar_sclr_rd = 0x00000005, + regk_marb_bar_vin_rd = 0x00000004, + regk_marb_bar_vin_wr = 0x00000003, + regk_marb_bar_vout = 0x00000006, + regk_marb_bar_yes = 0x00000001 +}; +#endif /* __marb_bar_defs_h */ +#ifndef __marb_bar_bp_defs_h +#define __marb_bar_bp_defs_h + +/* + * This file is autogenerated from + * file: marb_bar.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bar_bp */ + +/* Register rw_first_addr, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bar_bp_rw_op; +#define REG_RD_ADDR_marb_bar_bp_rw_op 8 +#define REG_WR_ADDR_marb_bar_bp_rw_op 8 + +/* Register rw_clients, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_rw_clients; +#define REG_RD_ADDR_marb_bar_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bar_bp_rw_clients 12 + +/* Register rw_options, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bar_bp_rw_options; +#define REG_RD_ADDR_marb_bar_bp_rw_options 16 +#define REG_WR_ADDR_marb_bar_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bar_bp, type r */ +typedef unsigned int reg_marb_bar_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bar_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bar_bp_r_brk_op; +#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bar_bp, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bar_bp, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bar_bp, type r */ +typedef unsigned int reg_marb_bar_bp_r_brk_size; +#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_ack; +#define REG_RD_ADDR_marb_bar_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bar_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bar_bp_no = 0x00000000, + regk_marb_bar_bp_rw_op_default = 0x00000000, + regk_marb_bar_bp_rw_options_default = 0x00000000, + regk_marb_bar_bp_yes = 0x00000001 +}; +#endif /* __marb_bar_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h new file mode 100644 index 000000000000..2baa833f109a --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h @@ -0,0 +1,626 @@ +#ifndef __marb_foo_defs_h +#define __marb_foo_defs_h + +/* + * This file is autogenerated from + * file: marb_foo.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_foo */ + +#define STRIDE_marb_foo_rw_intm_slots 4 +/* Register rw_intm_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_intm_slots; +#define REG_RD_ADDR_marb_foo_rw_intm_slots 0 +#define REG_WR_ADDR_marb_foo_rw_intm_slots 0 + +#define STRIDE_marb_foo_rw_l2_slots 4 +/* Register rw_l2_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_l2_slots; +#define REG_RD_ADDR_marb_foo_rw_l2_slots 256 +#define REG_WR_ADDR_marb_foo_rw_l2_slots 256 + +#define STRIDE_marb_foo_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_regs_slots; +#define REG_RD_ADDR_marb_foo_rw_regs_slots 512 +#define REG_WR_ADDR_marb_foo_rw_regs_slots 512 + +/* Register rw_sclr_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_sclr_burst; +#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 +#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 + +/* Register rw_dma0_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma0_burst; +#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 +#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 + +/* Register rw_dma1_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma1_burst; +#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 +#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 + +/* Register rw_dma2_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma2_burst; +#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 +#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 + +/* Register rw_dma3_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma3_burst; +#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 +#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 + +/* Register rw_dma4_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma4_burst; +#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 +#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 + +/* Register rw_dma5_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma5_burst; +#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 +#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 + +/* Register rw_dma6_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma6_burst; +#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 +#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 + +/* Register rw_dma7_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma7_burst; +#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 +#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 + +/* Register rw_dma9_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma9_burst; +#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 +#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 + +/* Register rw_dma11_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma11_burst; +#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 +#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 + +/* Register rw_cpui_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_cpui_burst; +#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 +#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 + +/* Register rw_cpud_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_cpud_burst; +#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 +#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 + +/* Register rw_iop_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_iop_burst; +#define REG_RD_ADDR_marb_foo_rw_iop_burst 580 +#define REG_WR_ADDR_marb_foo_rw_iop_burst 580 + +/* Register rw_ccdstat_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_ccdstat_burst; +#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 +#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 + +/* Register rw_intr_mask, scope marb_foo, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_intr_mask; +#define REG_RD_ADDR_marb_foo_rw_intr_mask 588 +#define REG_WR_ADDR_marb_foo_rw_intr_mask 588 + +/* Register rw_ack_intr, scope marb_foo, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_ack_intr; +#define REG_RD_ADDR_marb_foo_rw_ack_intr 592 +#define REG_WR_ADDR_marb_foo_rw_ack_intr 592 + +/* Register r_intr, scope marb_foo, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_r_intr; +#define REG_RD_ADDR_marb_foo_r_intr 596 + +/* Register r_masked_intr, scope marb_foo, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_r_masked_intr; +#define REG_RD_ADDR_marb_foo_r_masked_intr 600 + +/* Register rw_stop_mask, scope marb_foo, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_rw_stop_mask; +#define REG_RD_ADDR_marb_foo_rw_stop_mask 604 +#define REG_WR_ADDR_marb_foo_rw_stop_mask 604 + +/* Register r_stopped, scope marb_foo, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_r_stopped; +#define REG_RD_ADDR_marb_foo_r_stopped 608 + +/* Register rw_no_snoop, scope marb_foo, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_rw_no_snoop; +#define REG_RD_ADDR_marb_foo_rw_no_snoop 896 +#define REG_WR_ADDR_marb_foo_rw_no_snoop 896 + +/* Register rw_no_snoop_rq, scope marb_foo, type rw */ +typedef struct { + unsigned int dummy1 : 11; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 19; +} reg_marb_foo_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 +#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 + + +/* Constants */ +enum { + regk_marb_foo_ccdstat = 0x0000000e, + regk_marb_foo_cpud = 0x0000000c, + regk_marb_foo_cpui = 0x0000000b, + regk_marb_foo_dma0 = 0x00000001, + regk_marb_foo_dma1 = 0x00000002, + regk_marb_foo_dma11 = 0x0000000a, + regk_marb_foo_dma2 = 0x00000003, + regk_marb_foo_dma3 = 0x00000004, + regk_marb_foo_dma4 = 0x00000005, + regk_marb_foo_dma5 = 0x00000006, + regk_marb_foo_dma6 = 0x00000007, + regk_marb_foo_dma7 = 0x00000008, + regk_marb_foo_dma9 = 0x00000009, + regk_marb_foo_iop = 0x0000000d, + regk_marb_foo_no = 0x00000000, + regk_marb_foo_r_stopped_default = 0x00000000, + regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, + regk_marb_foo_rw_cpud_burst_default = 0x00000000, + regk_marb_foo_rw_cpui_burst_default = 0x00000000, + regk_marb_foo_rw_dma0_burst_default = 0x00000000, + regk_marb_foo_rw_dma11_burst_default = 0x00000000, + regk_marb_foo_rw_dma1_burst_default = 0x00000000, + regk_marb_foo_rw_dma2_burst_default = 0x00000000, + regk_marb_foo_rw_dma3_burst_default = 0x00000000, + regk_marb_foo_rw_dma4_burst_default = 0x00000000, + regk_marb_foo_rw_dma5_burst_default = 0x00000000, + regk_marb_foo_rw_dma6_burst_default = 0x00000000, + regk_marb_foo_rw_dma7_burst_default = 0x00000000, + regk_marb_foo_rw_dma9_burst_default = 0x00000000, + regk_marb_foo_rw_intm_slots_default = 0x00000000, + regk_marb_foo_rw_intm_slots_size = 0x00000040, + regk_marb_foo_rw_intr_mask_default = 0x00000000, + regk_marb_foo_rw_iop_burst_default = 0x00000000, + regk_marb_foo_rw_l2_slots_default = 0x00000000, + regk_marb_foo_rw_l2_slots_size = 0x00000040, + regk_marb_foo_rw_no_snoop_default = 0x00000000, + regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, + regk_marb_foo_rw_regs_slots_default = 0x00000000, + regk_marb_foo_rw_regs_slots_size = 0x00000004, + regk_marb_foo_rw_sclr_burst_default = 0x00000000, + regk_marb_foo_rw_stop_mask_default = 0x00000000, + regk_marb_foo_sclr = 0x00000000, + regk_marb_foo_yes = 0x00000001 +}; +#endif /* __marb_foo_defs_h */ +#ifndef __marb_foo_bp_defs_h +#define __marb_foo_bp_defs_h + +/* + * This file is autogenerated from + * file: marb_foo.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_foo_bp */ + +/* Register rw_first_addr, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_first_addr; +#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_last_addr; +#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_foo_bp_rw_op; +#define REG_RD_ADDR_marb_foo_bp_rw_op 8 +#define REG_WR_ADDR_marb_foo_bp_rw_op 8 + +/* Register rw_clients, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_rw_clients; +#define REG_RD_ADDR_marb_foo_bp_rw_clients 12 +#define REG_WR_ADDR_marb_foo_bp_rw_clients 12 + +/* Register rw_options, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_foo_bp_rw_options; +#define REG_RD_ADDR_marb_foo_bp_rw_options 16 +#define REG_WR_ADDR_marb_foo_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_foo_bp, type r */ +typedef unsigned int reg_marb_foo_bp_r_brk_addr; +#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_foo_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_foo_bp_r_brk_op; +#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_foo_bp, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_r_brk_clients; +#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_foo_bp, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_foo_bp, type r */ +typedef unsigned int reg_marb_foo_bp_r_brk_size; +#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_ack; +#define REG_RD_ADDR_marb_foo_bp_rw_ack 40 +#define REG_WR_ADDR_marb_foo_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_foo_bp_no = 0x00000000, + regk_marb_foo_bp_rw_op_default = 0x00000000, + regk_marb_foo_bp_rw_options_default = 0x00000000, + regk_marb_foo_bp_yes = 0x00000001 +}; +#endif /* __marb_foo_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h new file mode 100644 index 000000000000..4b96cd2cba8a --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h @@ -0,0 +1,312 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: pinmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int eth_mdio : 1; + unsigned int geth : 1; + unsigned int tg : 1; + unsigned int tg_clk : 1; + unsigned int vout : 1; + unsigned int vout_sync : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int pwm0 : 1; + unsigned int pwm1 : 1; + unsigned int pwm2 : 1; + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int pio : 1; + unsigned int i2c0 : 1; + unsigned int i2c1 : 1; + unsigned int i2c1_sda1 : 1; + unsigned int i2c1_sda2 : 1; + unsigned int i2c1_sda3 : 1; + unsigned int i2c1_sen : 1; + unsigned int dummy1 : 8; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 0 +#define REG_WR_ADDR_pinmux_rw_hwprot 0 + +/* Register rw_gio_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int pa8 : 1; + unsigned int pa9 : 1; + unsigned int pa10 : 1; + unsigned int pa11 : 1; + unsigned int pa12 : 1; + unsigned int pa13 : 1; + unsigned int pa14 : 1; + unsigned int pa15 : 1; + unsigned int pa16 : 1; + unsigned int pa17 : 1; + unsigned int pa18 : 1; + unsigned int pa19 : 1; + unsigned int pa20 : 1; + unsigned int pa21 : 1; + unsigned int pa22 : 1; + unsigned int pa23 : 1; + unsigned int pa24 : 1; + unsigned int pa25 : 1; + unsigned int pa26 : 1; + unsigned int pa27 : 1; + unsigned int pa28 : 1; + unsigned int pa29 : 1; + unsigned int pa30 : 1; + unsigned int pa31 : 1; +} reg_pinmux_rw_gio_pa; +#define REG_RD_ADDR_pinmux_rw_gio_pa 4 +#define REG_WR_ADDR_pinmux_rw_gio_pa 4 + +/* Register rw_gio_pb, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int pb18 : 1; + unsigned int pb19 : 1; + unsigned int pb20 : 1; + unsigned int pb21 : 1; + unsigned int pb22 : 1; + unsigned int pb23 : 1; + unsigned int pb24 : 1; + unsigned int pb25 : 1; + unsigned int pb26 : 1; + unsigned int pb27 : 1; + unsigned int pb28 : 1; + unsigned int pb29 : 1; + unsigned int pb30 : 1; + unsigned int pb31 : 1; +} reg_pinmux_rw_gio_pb; +#define REG_RD_ADDR_pinmux_rw_gio_pb 8 +#define REG_WR_ADDR_pinmux_rw_gio_pb 8 + +/* Register rw_gio_pc, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_gio_pc; +#define REG_RD_ADDR_pinmux_rw_gio_pc 12 +#define REG_WR_ADDR_pinmux_rw_gio_pc 12 + +/* Register rw_iop_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int pa8 : 1; + unsigned int pa9 : 1; + unsigned int pa10 : 1; + unsigned int pa11 : 1; + unsigned int pa12 : 1; + unsigned int pa13 : 1; + unsigned int pa14 : 1; + unsigned int pa15 : 1; + unsigned int pa16 : 1; + unsigned int pa17 : 1; + unsigned int pa18 : 1; + unsigned int pa19 : 1; + unsigned int pa20 : 1; + unsigned int pa21 : 1; + unsigned int pa22 : 1; + unsigned int pa23 : 1; + unsigned int pa24 : 1; + unsigned int pa25 : 1; + unsigned int pa26 : 1; + unsigned int pa27 : 1; + unsigned int pa28 : 1; + unsigned int pa29 : 1; + unsigned int pa30 : 1; + unsigned int pa31 : 1; +} reg_pinmux_rw_iop_pa; +#define REG_RD_ADDR_pinmux_rw_iop_pa 16 +#define REG_WR_ADDR_pinmux_rw_iop_pa 16 + +/* Register rw_iop_pb, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int dummy1 : 24; +} reg_pinmux_rw_iop_pb; +#define REG_RD_ADDR_pinmux_rw_iop_pb 20 +#define REG_WR_ADDR_pinmux_rw_iop_pb 20 + +/* Register rw_iop_pio, scope pinmux, type rw */ +typedef struct { + unsigned int d0 : 1; + unsigned int d1 : 1; + unsigned int d2 : 1; + unsigned int d3 : 1; + unsigned int d4 : 1; + unsigned int d5 : 1; + unsigned int d6 : 1; + unsigned int d7 : 1; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_iop_pio; +#define REG_RD_ADDR_pinmux_rw_iop_pio 24 +#define REG_WR_ADDR_pinmux_rw_iop_pio 24 + +/* Register rw_iop_usb, scope pinmux, type rw */ +typedef struct { + unsigned int usb0 : 1; + unsigned int dummy1 : 31; +} reg_pinmux_rw_iop_usb; +#define REG_RD_ADDR_pinmux_rw_iop_usb 28 +#define REG_WR_ADDR_pinmux_rw_iop_usb 28 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_gio_pa_default = 0x00000000, + regk_pinmux_rw_gio_pb_default = 0x00000000, + regk_pinmux_rw_gio_pc_default = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_iop_pa_default = 0x00000000, + regk_pinmux_rw_iop_pb_default = 0x00000000, + regk_pinmux_rw_iop_pio_default = 0x00000000, + regk_pinmux_rw_iop_usb_default = 0x00000001, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h new file mode 100644 index 000000000000..2d8e4b4cc602 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h @@ -0,0 +1,371 @@ +#ifndef __pio_defs_h +#define __pio_defs_h + +/* + * This file is autogenerated from + * file: pio.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pio */ + +/* Register rw_data, scope pio, type rw */ +typedef unsigned int reg_pio_rw_data; +#define REG_RD_ADDR_pio_rw_data 64 +#define REG_WR_ADDR_pio_rw_data 64 + +/* Register rw_io_access0, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access0; +#define REG_RD_ADDR_pio_rw_io_access0 0 +#define REG_WR_ADDR_pio_rw_io_access0 0 + +/* Register rw_io_access1, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access1; +#define REG_RD_ADDR_pio_rw_io_access1 4 +#define REG_WR_ADDR_pio_rw_io_access1 4 + +/* Register rw_io_access2, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access2; +#define REG_RD_ADDR_pio_rw_io_access2 8 +#define REG_WR_ADDR_pio_rw_io_access2 8 + +/* Register rw_io_access3, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access3; +#define REG_RD_ADDR_pio_rw_io_access3 12 +#define REG_WR_ADDR_pio_rw_io_access3 12 + +/* Register rw_io_access4, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access4; +#define REG_RD_ADDR_pio_rw_io_access4 16 +#define REG_WR_ADDR_pio_rw_io_access4 16 + +/* Register rw_io_access5, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access5; +#define REG_RD_ADDR_pio_rw_io_access5 20 +#define REG_WR_ADDR_pio_rw_io_access5 20 + +/* Register rw_io_access6, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access6; +#define REG_RD_ADDR_pio_rw_io_access6 24 +#define REG_WR_ADDR_pio_rw_io_access6 24 + +/* Register rw_io_access7, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access7; +#define REG_RD_ADDR_pio_rw_io_access7 28 +#define REG_WR_ADDR_pio_rw_io_access7 28 + +/* Register rw_io_access8, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access8; +#define REG_RD_ADDR_pio_rw_io_access8 32 +#define REG_WR_ADDR_pio_rw_io_access8 32 + +/* Register rw_io_access9, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access9; +#define REG_RD_ADDR_pio_rw_io_access9 36 +#define REG_WR_ADDR_pio_rw_io_access9 36 + +/* Register rw_io_access10, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access10; +#define REG_RD_ADDR_pio_rw_io_access10 40 +#define REG_WR_ADDR_pio_rw_io_access10 40 + +/* Register rw_io_access11, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access11; +#define REG_RD_ADDR_pio_rw_io_access11 44 +#define REG_WR_ADDR_pio_rw_io_access11 44 + +/* Register rw_io_access12, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access12; +#define REG_RD_ADDR_pio_rw_io_access12 48 +#define REG_WR_ADDR_pio_rw_io_access12 48 + +/* Register rw_io_access13, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access13; +#define REG_RD_ADDR_pio_rw_io_access13 52 +#define REG_WR_ADDR_pio_rw_io_access13 52 + +/* Register rw_io_access14, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access14; +#define REG_RD_ADDR_pio_rw_io_access14 56 +#define REG_WR_ADDR_pio_rw_io_access14 56 + +/* Register rw_io_access15, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access15; +#define REG_RD_ADDR_pio_rw_io_access15 60 +#define REG_WR_ADDR_pio_rw_io_access15 60 + +/* Register rw_ce0_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce0_cfg; +#define REG_RD_ADDR_pio_rw_ce0_cfg 68 +#define REG_WR_ADDR_pio_rw_ce0_cfg 68 + +/* Register rw_ce1_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce1_cfg; +#define REG_RD_ADDR_pio_rw_ce1_cfg 72 +#define REG_WR_ADDR_pio_rw_ce1_cfg 72 + +/* Register rw_ce2_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce2_cfg; +#define REG_RD_ADDR_pio_rw_ce2_cfg 76 +#define REG_WR_ADDR_pio_rw_ce2_cfg 76 + +/* Register rw_dout, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_dout; +#define REG_RD_ADDR_pio_rw_dout 80 +#define REG_WR_ADDR_pio_rw_dout 80 + +/* Register rw_oe, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_oe; +#define REG_RD_ADDR_pio_rw_oe 84 +#define REG_WR_ADDR_pio_rw_oe 84 + +/* Register rw_man_ctrl, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_man_ctrl; +#define REG_RD_ADDR_pio_rw_man_ctrl 88 +#define REG_WR_ADDR_pio_rw_man_ctrl 88 + +/* Register r_din, scope pio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_r_din; +#define REG_RD_ADDR_pio_r_din 92 + +/* Register r_stat, scope pio, type r */ +typedef struct { + unsigned int busy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_stat; +#define REG_RD_ADDR_pio_r_stat 96 + +/* Register rw_intr_mask, scope pio, type rw */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_rw_intr_mask; +#define REG_RD_ADDR_pio_rw_intr_mask 100 +#define REG_WR_ADDR_pio_rw_intr_mask 100 + +/* Register rw_ack_intr, scope pio, type rw */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_rw_ack_intr; +#define REG_RD_ADDR_pio_rw_ack_intr 104 +#define REG_WR_ADDR_pio_rw_ack_intr 104 + +/* Register r_intr, scope pio, type r */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_intr; +#define REG_RD_ADDR_pio_r_intr 108 + +/* Register r_masked_intr, scope pio, type r */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_masked_intr; +#define REG_RD_ADDR_pio_r_masked_intr 112 + + +/* Constants */ +enum { + regk_pio_a2 = 0x00000003, + regk_pio_no = 0x00000000, + regk_pio_normal = 0x00000000, + regk_pio_rd = 0x00000001, + regk_pio_rw_ce0_cfg_default = 0x00000000, + regk_pio_rw_ce1_cfg_default = 0x00000000, + regk_pio_rw_ce2_cfg_default = 0x00000000, + regk_pio_rw_intr_mask_default = 0x00000000, + regk_pio_rw_man_ctrl_default = 0x00000000, + regk_pio_rw_oe_default = 0x00000000, + regk_pio_wr = 0x00000002, + regk_pio_wr_ce2 = 0x00000003, + regk_pio_yes = 0x00000001, + regk_pio_yes_all = 0x000000ff +}; +#endif /* __pio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h new file mode 100644 index 000000000000..36e59d6e96b6 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h @@ -0,0 +1,103 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: reg.rmap + * + * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +typedef enum { + regi_ccd = 0xb0000000, + regi_ccd_top = 0xb0000000, + regi_ccd_dp = 0xb0000400, + regi_ccd_stat = 0xb0000800, + regi_ccd_tg = 0xb0001000, + regi_cfg = 0xb0002000, + regi_clkgen = 0xb0004000, + regi_ddr2_ctrl = 0xb0006000, + regi_dma0 = 0xb0008000, + regi_dma1 = 0xb000a000, + regi_dma11 = 0xb000c000, + regi_dma2 = 0xb000e000, + regi_dma3 = 0xb0010000, + regi_dma4 = 0xb0012000, + regi_dma5 = 0xb0014000, + regi_dma6 = 0xb0016000, + regi_dma7 = 0xb0018000, + regi_dma9 = 0xb001a000, + regi_eth = 0xb001c000, + regi_gio = 0xb0020000, + regi_h264 = 0xb0022000, + regi_hist = 0xb0026000, + regi_iop = 0xb0028000, + regi_iop_version = 0xb0028000, + regi_iop_fifo_in_extra = 0xb0028040, + regi_iop_fifo_out_extra = 0xb0028080, + regi_iop_trigger_grp0 = 0xb00280c0, + regi_iop_trigger_grp1 = 0xb0028100, + regi_iop_trigger_grp2 = 0xb0028140, + regi_iop_trigger_grp3 = 0xb0028180, + regi_iop_trigger_grp4 = 0xb00281c0, + regi_iop_trigger_grp5 = 0xb0028200, + regi_iop_trigger_grp6 = 0xb0028240, + regi_iop_trigger_grp7 = 0xb0028280, + regi_iop_crc_par = 0xb0028300, + regi_iop_dmc_in = 0xb0028380, + regi_iop_dmc_out = 0xb0028400, + regi_iop_fifo_in = 0xb0028480, + regi_iop_fifo_out = 0xb0028500, + regi_iop_scrc_in = 0xb0028580, + regi_iop_scrc_out = 0xb0028600, + regi_iop_timer_grp0 = 0xb0028680, + regi_iop_timer_grp1 = 0xb0028700, + regi_iop_sap_in = 0xb0028800, + regi_iop_sap_out = 0xb0028900, + regi_iop_spu = 0xb0028a00, + regi_iop_sw_cfg = 0xb0028b00, + regi_iop_sw_cpu = 0xb0028c00, + regi_iop_sw_mpu = 0xb0028d00, + regi_iop_sw_spu = 0xb0028e00, + regi_iop_mpu = 0xb0029000, + regi_irq = 0xb002a000, + regi_irq2 = 0xb006a000, + regi_jpeg = 0xb002c000, + regi_l2cache = 0xb0030000, + regi_marb_bar = 0xb0032000, + regi_marb_bar_bp0 = 0xb0032140, + regi_marb_bar_bp1 = 0xb0032180, + regi_marb_bar_bp2 = 0xb00321c0, + regi_marb_bar_bp3 = 0xb0032200, + regi_marb_foo = 0xb0034000, + regi_marb_foo_bp0 = 0xb0034280, + regi_marb_foo_bp1 = 0xb00342c0, + regi_marb_foo_bp2 = 0xb0034300, + regi_marb_foo_bp3 = 0xb0034340, + regi_pinmux = 0xb0038000, + regi_pio = 0xb0036000, + regi_sclr = 0xb003a000, + regi_sclr_fifo = 0xb003c000, + regi_ser0 = 0xb003e000, + regi_ser1 = 0xb0040000, + regi_ser2 = 0xb0042000, + regi_ser3 = 0xb0044000, + regi_ser4 = 0xb0046000, + regi_sser = 0xb0048000, + regi_strcop = 0xb004a000, + regi_strdma0 = 0xb004e000, + regi_strdma1 = 0xb0050000, + regi_strdma2 = 0xb0052000, + regi_strdma3 = 0xb0054000, + regi_strdma5 = 0xb0056000, + regi_strmux = 0xb004c000, + regi_timer0 = 0xb0058000, + regi_timer1 = 0xb005a000, + regi_timer2 = 0xb006e000, + regi_trace = 0xb005c000, + regi_vin = 0xb005e000, + regi_vout = 0xb0060000 +} reg_scope_instances; +#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h new file mode 100644 index 000000000000..14f718a4ecc3 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h @@ -0,0 +1,120 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: strmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 2; + unsigned int dma1 : 2; + unsigned int dma2 : 2; + unsigned int dma3 : 2; + unsigned int dma4 : 2; + unsigned int dma5 : 2; + unsigned int dma6 : 2; + unsigned int dma7 : 2; + unsigned int dummy1 : 2; + unsigned int dma9 : 2; + unsigned int dummy2 : 2; + unsigned int dma11 : 2; + unsigned int dummy3 : 8; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_eth = 0x00000001, + regk_strmux_h264 = 0x00000001, + regk_strmux_iop = 0x00000001, + regk_strmux_jpeg = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000002, + regk_strmux_ser3 = 0x00000002, + regk_strmux_ser4 = 0x00000002, + regk_strmux_sser = 0x00000001, + regk_strmux_strcop = 0x00000001 +}; +#endif /* __strmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h new file mode 100644 index 000000000000..2c33e097d60a --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h @@ -0,0 +1,265 @@ +#ifndef __timer_defs_h +#define __timer_defs_h + +/* + * This file is autogenerated from + * file: timer.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope timer */ + +/* Register rw_tmr0_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr0_div; +#define REG_RD_ADDR_timer_rw_tmr0_div 0 +#define REG_WR_ADDR_timer_rw_tmr0_div 0 + +/* Register r_tmr0_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr0_data; +#define REG_RD_ADDR_timer_r_tmr0_data 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr0_ctrl; +#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 +#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr1_div; +#define REG_RD_ADDR_timer_rw_tmr1_div 16 +#define REG_WR_ADDR_timer_rw_tmr1_div 16 + +/* Register r_tmr1_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr1_data; +#define REG_RD_ADDR_timer_r_tmr1_data 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr1_ctrl; +#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 +#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 + +/* Register rs_cnt_data, scope timer, type rs */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_rs_cnt_data; +#define REG_RD_ADDR_timer_rs_cnt_data 32 + +/* Register r_cnt_data, scope timer, type r */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_r_cnt_data; +#define REG_RD_ADDR_timer_r_cnt_data 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +typedef struct { + unsigned int clk : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_cnt_cfg; +#define REG_RD_ADDR_timer_rw_cnt_cfg 40 +#define REG_WR_ADDR_timer_rw_cnt_cfg 40 + +/* Register rw_trig, scope timer, type rw */ +typedef unsigned int reg_timer_rw_trig; +#define REG_RD_ADDR_timer_rw_trig 48 +#define REG_WR_ADDR_timer_rw_trig 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_trig_cfg; +#define REG_RD_ADDR_timer_rw_trig_cfg 52 +#define REG_WR_ADDR_timer_rw_trig_cfg 52 + +/* Register r_time, scope timer, type r */ +typedef unsigned int reg_timer_r_time; +#define REG_RD_ADDR_timer_r_time 56 + +/* Register rw_out, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_out; +#define REG_RD_ADDR_timer_rw_out 60 +#define REG_WR_ADDR_timer_rw_out 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int key : 7; + unsigned int dummy1 : 16; +} reg_timer_rw_wd_ctrl; +#define REG_RD_ADDR_timer_rw_wd_ctrl 64 +#define REG_WR_ADDR_timer_rw_wd_ctrl 64 + +/* Register r_wd_stat, scope timer, type r */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int dummy1 : 23; +} reg_timer_r_wd_stat; +#define REG_RD_ADDR_timer_r_wd_stat 68 + +/* Register rw_intr_mask, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_intr_mask; +#define REG_RD_ADDR_timer_rw_intr_mask 72 +#define REG_WR_ADDR_timer_rw_intr_mask 72 + +/* Register rw_ack_intr, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_ack_intr; +#define REG_RD_ADDR_timer_rw_ack_intr 76 +#define REG_WR_ADDR_timer_rw_ack_intr 76 + +/* Register r_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_intr; +#define REG_RD_ADDR_timer_r_intr 80 + +/* Register r_masked_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_masked_intr; +#define REG_RD_ADDR_timer_r_masked_intr 84 + +/* Register rw_test, scope timer, type rw */ +typedef struct { + unsigned int dis : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_timer_rw_test; +#define REG_RD_ADDR_timer_rw_test 88 +#define REG_WR_ADDR_timer_rw_test 88 + + +/* Constants */ +enum { + regk_timer_ext = 0x00000001, + regk_timer_f100 = 0x00000007, + regk_timer_f29_493 = 0x00000004, + regk_timer_f32 = 0x00000005, + regk_timer_f32_768 = 0x00000006, + regk_timer_f90 = 0x00000003, + regk_timer_hold = 0x00000001, + regk_timer_ld = 0x00000000, + regk_timer_no = 0x00000000, + regk_timer_off = 0x00000000, + regk_timer_run = 0x00000002, + regk_timer_rw_cnt_cfg_default = 0x00000000, + regk_timer_rw_intr_mask_default = 0x00000000, + regk_timer_rw_out_default = 0x00000000, + regk_timer_rw_test_default = 0x00000000, + regk_timer_rw_tmr0_ctrl_default = 0x00000000, + regk_timer_rw_tmr1_ctrl_default = 0x00000000, + regk_timer_rw_trig_cfg_default = 0x00000000, + regk_timer_start = 0x00000001, + regk_timer_stop = 0x00000000, + regk_timer_time = 0x00000001, + regk_timer_tmr0 = 0x00000002, + regk_timer_tmr1 = 0x00000003, + regk_timer_vclk = 0x00000002, + regk_timer_yes = 0x00000001 +}; +#endif /* __timer_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h b/arch/cris/include/arch-v32/mach-a3/mach/memmap.h new file mode 100644 index 000000000000..7e15c9eb4e49 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/memmap.h @@ -0,0 +1,10 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_INTMEM_START (0x38000000) +#define MEM_INTMEM_SIZE (0x00018000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h b/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h new file mode 100644 index 000000000000..db42a7254584 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h @@ -0,0 +1,45 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_A 0 +#define PORT_B 1 +#define PORT_C 2 + +enum pin_mode { + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function { + pinmux_eth, + pinmux_geth, + pinmux_tg_ccd, + pinmux_tg_cmos, + pinmux_vout, + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_ser4, + pinmux_sser, + pinmux_pio, + pinmux_pwm0, + pinmux_pwm1, + pinmux_pwm2, + pinmux_i2c0, + pinmux_i2c1, + pinmux_i2c1_3wire, + pinmux_i2c1_sda1, + pinmux_i2c1_sda2, + pinmux_i2c1_sda3, +}; + +int crisv32_pinmux_init(void); +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); +void crisv32_pinmux_dump(void); + +#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc new file mode 100644 index 000000000000..2f23e5e16f4a --- /dev/null +++ b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc @@ -0,0 +1,60 @@ +#include +#include +#include +#include +#include + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d 0xFFFFFFFF, $r0 + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 + move.d $r0, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 + move.d $r1, [$r0] + .endm diff --git a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h b/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h new file mode 100644 index 000000000000..a2e0ec8faa7d --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h @@ -0,0 +1,28 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum { + arbiter_all_dmas = 0x3ff, + arbiter_cpu = 0xc00, + arbiter_all_clients = 0x3fff +}; + +enum { + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback * cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 000000000000..0a409c92837e --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h @@ -0,0 +1,319 @@ +#ifndef __bif_core_defs_asm_h +#define __bif_core_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp1_cfg___lw___width 6 +#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp1_cfg___ew___width 3 +#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp1_cfg___zw___width 3 +#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp1_cfg___aw___width 2 +#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp1_cfg___dw___width 2 +#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp1_cfg___ewb___width 2 +#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp1_cfg___bw___width 1 +#define reg_bif_core_rw_grp1_cfg___bw___bit 18 +#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp1_cfg___mode___width 1 +#define reg_bif_core_rw_grp1_cfg___mode___bit 21 +#define reg_bif_core_rw_grp1_cfg_offset 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp2_cfg___lw___width 6 +#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp2_cfg___ew___width 3 +#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp2_cfg___zw___width 3 +#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp2_cfg___aw___width 2 +#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp2_cfg___dw___width 2 +#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp2_cfg___ewb___width 2 +#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp2_cfg___bw___width 1 +#define reg_bif_core_rw_grp2_cfg___bw___bit 18 +#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp2_cfg___mode___width 1 +#define reg_bif_core_rw_grp2_cfg___mode___bit 21 +#define reg_bif_core_rw_grp2_cfg_offset 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp3_cfg___lw___width 6 +#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp3_cfg___ew___width 3 +#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp3_cfg___zw___width 3 +#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp3_cfg___aw___width 2 +#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp3_cfg___dw___width 2 +#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp3_cfg___ewb___width 2 +#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp3_cfg___bw___width 1 +#define reg_bif_core_rw_grp3_cfg___bw___bit 18 +#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp3_cfg___mode___width 1 +#define reg_bif_core_rw_grp3_cfg___mode___bit 21 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 +#define reg_bif_core_rw_grp3_cfg_offset 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp4_cfg___lw___width 6 +#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp4_cfg___ew___width 3 +#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp4_cfg___zw___width 3 +#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp4_cfg___aw___width 2 +#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp4_cfg___dw___width 2 +#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp4_cfg___ewb___width 2 +#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp4_cfg___bw___width 1 +#define reg_bif_core_rw_grp4_cfg___bw___bit 18 +#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp4_cfg___mode___width 1 +#define reg_bif_core_rw_grp4_cfg___mode___bit 21 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 +#define reg_bif_core_rw_grp4_cfg_offset 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_timing___cl___lsb 0 +#define reg_bif_core_rw_sdram_timing___cl___width 3 +#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 +#define reg_bif_core_rw_sdram_timing___rcd___width 3 +#define reg_bif_core_rw_sdram_timing___rp___lsb 6 +#define reg_bif_core_rw_sdram_timing___rp___width 3 +#define reg_bif_core_rw_sdram_timing___rc___lsb 9 +#define reg_bif_core_rw_sdram_timing___rc___width 2 +#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 +#define reg_bif_core_rw_sdram_timing___dpl___width 2 +#define reg_bif_core_rw_sdram_timing___pde___lsb 13 +#define reg_bif_core_rw_sdram_timing___pde___width 1 +#define reg_bif_core_rw_sdram_timing___pde___bit 13 +#define reg_bif_core_rw_sdram_timing___ref___lsb 14 +#define reg_bif_core_rw_sdram_timing___ref___width 2 +#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 +#define reg_bif_core_rw_sdram_timing___cpd___width 1 +#define reg_bif_core_rw_sdram_timing___cpd___bit 16 +#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 +#define reg_bif_core_rw_sdram_timing___sdcke___width 1 +#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 +#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 +#define reg_bif_core_rw_sdram_timing___sdclk___width 1 +#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 +#define reg_bif_core_rw_sdram_timing_offset 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 +#define reg_bif_core_rw_sdram_cmd___cmd___width 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 +#define reg_bif_core_rw_sdram_cmd_offset 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 +#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_rs_sdram_ref_stat_offset 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_r_sdram_ref_stat___ok___width 1 +#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_r_sdram_ref_stat_offset 36 + + +/* Constants */ +#define regk_bif_core_bank2 0x00000000 +#define regk_bif_core_bank4 0x00000001 +#define regk_bif_core_bit10 0x0000000a +#define regk_bif_core_bit11 0x0000000b +#define regk_bif_core_bit12 0x0000000c +#define regk_bif_core_bit13 0x0000000d +#define regk_bif_core_bit14 0x0000000e +#define regk_bif_core_bit15 0x0000000f +#define regk_bif_core_bit16 0x00000010 +#define regk_bif_core_bit17 0x00000011 +#define regk_bif_core_bit18 0x00000012 +#define regk_bif_core_bit19 0x00000013 +#define regk_bif_core_bit20 0x00000014 +#define regk_bif_core_bit21 0x00000015 +#define regk_bif_core_bit22 0x00000016 +#define regk_bif_core_bit23 0x00000017 +#define regk_bif_core_bit24 0x00000018 +#define regk_bif_core_bit25 0x00000019 +#define regk_bif_core_bit26 0x0000001a +#define regk_bif_core_bit27 0x0000001b +#define regk_bif_core_bit28 0x0000001c +#define regk_bif_core_bit29 0x0000001d +#define regk_bif_core_bit9 0x00000009 +#define regk_bif_core_bw16 0x00000001 +#define regk_bif_core_bw32 0x00000000 +#define regk_bif_core_bwe 0x00000000 +#define regk_bif_core_cwe 0x00000001 +#define regk_bif_core_e15us 0x00000001 +#define regk_bif_core_e7800ns 0x00000002 +#define regk_bif_core_grp0 0x00000000 +#define regk_bif_core_grp1 0x00000001 +#define regk_bif_core_mrs 0x00000003 +#define regk_bif_core_no 0x00000000 +#define regk_bif_core_none 0x00000000 +#define regk_bif_core_nop 0x00000000 +#define regk_bif_core_off 0x00000000 +#define regk_bif_core_pre 0x00000002 +#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rd 0x00000002 +#define regk_bif_core_ref 0x00000001 +#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rw_grp1_cfg_default 0x000006cf +#define regk_bif_core_rw_grp2_cfg_default 0x000006cf +#define regk_bif_core_rw_grp3_cfg_default 0x000006cf +#define regk_bif_core_rw_grp4_cfg_default 0x000006cf +#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 +#define regk_bif_core_slf 0x00000004 +#define regk_bif_core_wr 0x00000001 +#define regk_bif_core_yes 0x00000001 +#endif /* __bif_core_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h new file mode 100644 index 000000000000..a9908dfc2937 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h @@ -0,0 +1,131 @@ +#ifndef __config_defs_asm_h +#define __config_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r + * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope config, type r */ +#define reg_config_r_bootsel___boot_mode___lsb 0 +#define reg_config_r_bootsel___boot_mode___width 3 +#define reg_config_r_bootsel___full_duplex___lsb 3 +#define reg_config_r_bootsel___full_duplex___width 1 +#define reg_config_r_bootsel___full_duplex___bit 3 +#define reg_config_r_bootsel___user___lsb 4 +#define reg_config_r_bootsel___user___width 1 +#define reg_config_r_bootsel___user___bit 4 +#define reg_config_r_bootsel___pll___lsb 5 +#define reg_config_r_bootsel___pll___width 1 +#define reg_config_r_bootsel___pll___bit 5 +#define reg_config_r_bootsel___flash_bw___lsb 6 +#define reg_config_r_bootsel___flash_bw___width 1 +#define reg_config_r_bootsel___flash_bw___bit 6 +#define reg_config_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +#define reg_config_rw_clk_ctrl___pll___lsb 0 +#define reg_config_rw_clk_ctrl___pll___width 1 +#define reg_config_rw_clk_ctrl___pll___bit 0 +#define reg_config_rw_clk_ctrl___cpu___lsb 1 +#define reg_config_rw_clk_ctrl___cpu___width 1 +#define reg_config_rw_clk_ctrl___cpu___bit 1 +#define reg_config_rw_clk_ctrl___iop___lsb 2 +#define reg_config_rw_clk_ctrl___iop___width 1 +#define reg_config_rw_clk_ctrl___iop___bit 2 +#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 +#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 +#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 +#define reg_config_rw_clk_ctrl___dma23___lsb 4 +#define reg_config_rw_clk_ctrl___dma23___width 1 +#define reg_config_rw_clk_ctrl___dma23___bit 4 +#define reg_config_rw_clk_ctrl___dma45___lsb 5 +#define reg_config_rw_clk_ctrl___dma45___width 1 +#define reg_config_rw_clk_ctrl___dma45___bit 5 +#define reg_config_rw_clk_ctrl___dma67___lsb 6 +#define reg_config_rw_clk_ctrl___dma67___width 1 +#define reg_config_rw_clk_ctrl___dma67___bit 6 +#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 +#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 +#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 +#define reg_config_rw_clk_ctrl___bif___lsb 8 +#define reg_config_rw_clk_ctrl___bif___width 1 +#define reg_config_rw_clk_ctrl___bif___bit 8 +#define reg_config_rw_clk_ctrl___fix_io___lsb 9 +#define reg_config_rw_clk_ctrl___fix_io___width 1 +#define reg_config_rw_clk_ctrl___fix_io___bit 9 +#define reg_config_rw_clk_ctrl_offset 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 +#define reg_config_rw_pad_ctrl___usb_susp___width 1 +#define reg_config_rw_pad_ctrl___usb_susp___bit 0 +#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 +#define reg_config_rw_pad_ctrl___phyrst_n___width 1 +#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 +#define reg_config_rw_pad_ctrl_offset 8 + + +/* Constants */ +#define regk_config_bw16 0x00000000 +#define regk_config_bw32 0x00000001 +#define regk_config_master 0x00000005 +#define regk_config_nand 0x00000003 +#define regk_config_net_rx 0x00000001 +#define regk_config_net_tx_rx 0x00000002 +#define regk_config_no 0x00000000 +#define regk_config_none 0x00000007 +#define regk_config_nor 0x00000000 +#define regk_config_rw_clk_ctrl_default 0x00000002 +#define regk_config_rw_pad_ctrl_default 0x00000000 +#define regk_config_ser 0x00000004 +#define regk_config_slave 0x00000006 +#define regk_config_yes 0x00000001 +#endif /* __config_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000000..be4c63936d90 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 8 +#define reg_gio_rw_pa_dout_offset 0 + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 8 +#define reg_gio_r_pa_din_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 8 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___pa0___lsb 0 +#define reg_gio_rw_intr_cfg___pa0___width 3 +#define reg_gio_rw_intr_cfg___pa1___lsb 3 +#define reg_gio_rw_intr_cfg___pa1___width 3 +#define reg_gio_rw_intr_cfg___pa2___lsb 6 +#define reg_gio_rw_intr_cfg___pa2___width 3 +#define reg_gio_rw_intr_cfg___pa3___lsb 9 +#define reg_gio_rw_intr_cfg___pa3___width 3 +#define reg_gio_rw_intr_cfg___pa4___lsb 12 +#define reg_gio_rw_intr_cfg___pa4___width 3 +#define reg_gio_rw_intr_cfg___pa5___lsb 15 +#define reg_gio_rw_intr_cfg___pa5___width 3 +#define reg_gio_rw_intr_cfg___pa6___lsb 18 +#define reg_gio_rw_intr_cfg___pa6___width 3 +#define reg_gio_rw_intr_cfg___pa7___lsb 21 +#define reg_gio_rw_intr_cfg___pa7___width 3 +#define reg_gio_rw_intr_cfg_offset 12 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___pa0___lsb 0 +#define reg_gio_rw_intr_mask___pa0___width 1 +#define reg_gio_rw_intr_mask___pa0___bit 0 +#define reg_gio_rw_intr_mask___pa1___lsb 1 +#define reg_gio_rw_intr_mask___pa1___width 1 +#define reg_gio_rw_intr_mask___pa1___bit 1 +#define reg_gio_rw_intr_mask___pa2___lsb 2 +#define reg_gio_rw_intr_mask___pa2___width 1 +#define reg_gio_rw_intr_mask___pa2___bit 2 +#define reg_gio_rw_intr_mask___pa3___lsb 3 +#define reg_gio_rw_intr_mask___pa3___width 1 +#define reg_gio_rw_intr_mask___pa3___bit 3 +#define reg_gio_rw_intr_mask___pa4___lsb 4 +#define reg_gio_rw_intr_mask___pa4___width 1 +#define reg_gio_rw_intr_mask___pa4___bit 4 +#define reg_gio_rw_intr_mask___pa5___lsb 5 +#define reg_gio_rw_intr_mask___pa5___width 1 +#define reg_gio_rw_intr_mask___pa5___bit 5 +#define reg_gio_rw_intr_mask___pa6___lsb 6 +#define reg_gio_rw_intr_mask___pa6___width 1 +#define reg_gio_rw_intr_mask___pa6___bit 6 +#define reg_gio_rw_intr_mask___pa7___lsb 7 +#define reg_gio_rw_intr_mask___pa7___width 1 +#define reg_gio_rw_intr_mask___pa7___bit 7 +#define reg_gio_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___pa0___lsb 0 +#define reg_gio_rw_ack_intr___pa0___width 1 +#define reg_gio_rw_ack_intr___pa0___bit 0 +#define reg_gio_rw_ack_intr___pa1___lsb 1 +#define reg_gio_rw_ack_intr___pa1___width 1 +#define reg_gio_rw_ack_intr___pa1___bit 1 +#define reg_gio_rw_ack_intr___pa2___lsb 2 +#define reg_gio_rw_ack_intr___pa2___width 1 +#define reg_gio_rw_ack_intr___pa2___bit 2 +#define reg_gio_rw_ack_intr___pa3___lsb 3 +#define reg_gio_rw_ack_intr___pa3___width 1 +#define reg_gio_rw_ack_intr___pa3___bit 3 +#define reg_gio_rw_ack_intr___pa4___lsb 4 +#define reg_gio_rw_ack_intr___pa4___width 1 +#define reg_gio_rw_ack_intr___pa4___bit 4 +#define reg_gio_rw_ack_intr___pa5___lsb 5 +#define reg_gio_rw_ack_intr___pa5___width 1 +#define reg_gio_rw_ack_intr___pa5___bit 5 +#define reg_gio_rw_ack_intr___pa6___lsb 6 +#define reg_gio_rw_ack_intr___pa6___width 1 +#define reg_gio_rw_ack_intr___pa6___bit 6 +#define reg_gio_rw_ack_intr___pa7___lsb 7 +#define reg_gio_rw_ack_intr___pa7___width 1 +#define reg_gio_rw_ack_intr___pa7___bit 7 +#define reg_gio_rw_ack_intr_offset 20 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___pa0___lsb 0 +#define reg_gio_r_intr___pa0___width 1 +#define reg_gio_r_intr___pa0___bit 0 +#define reg_gio_r_intr___pa1___lsb 1 +#define reg_gio_r_intr___pa1___width 1 +#define reg_gio_r_intr___pa1___bit 1 +#define reg_gio_r_intr___pa2___lsb 2 +#define reg_gio_r_intr___pa2___width 1 +#define reg_gio_r_intr___pa2___bit 2 +#define reg_gio_r_intr___pa3___lsb 3 +#define reg_gio_r_intr___pa3___width 1 +#define reg_gio_r_intr___pa3___bit 3 +#define reg_gio_r_intr___pa4___lsb 4 +#define reg_gio_r_intr___pa4___width 1 +#define reg_gio_r_intr___pa4___bit 4 +#define reg_gio_r_intr___pa5___lsb 5 +#define reg_gio_r_intr___pa5___width 1 +#define reg_gio_r_intr___pa5___bit 5 +#define reg_gio_r_intr___pa6___lsb 6 +#define reg_gio_r_intr___pa6___width 1 +#define reg_gio_r_intr___pa6___bit 6 +#define reg_gio_r_intr___pa7___lsb 7 +#define reg_gio_r_intr___pa7___width 1 +#define reg_gio_r_intr___pa7___bit 7 +#define reg_gio_r_intr_offset 24 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___pa0___lsb 0 +#define reg_gio_r_masked_intr___pa0___width 1 +#define reg_gio_r_masked_intr___pa0___bit 0 +#define reg_gio_r_masked_intr___pa1___lsb 1 +#define reg_gio_r_masked_intr___pa1___width 1 +#define reg_gio_r_masked_intr___pa1___bit 1 +#define reg_gio_r_masked_intr___pa2___lsb 2 +#define reg_gio_r_masked_intr___pa2___width 1 +#define reg_gio_r_masked_intr___pa2___bit 2 +#define reg_gio_r_masked_intr___pa3___lsb 3 +#define reg_gio_r_masked_intr___pa3___width 1 +#define reg_gio_r_masked_intr___pa3___bit 3 +#define reg_gio_r_masked_intr___pa4___lsb 4 +#define reg_gio_r_masked_intr___pa4___width 1 +#define reg_gio_r_masked_intr___pa4___bit 4 +#define reg_gio_r_masked_intr___pa5___lsb 5 +#define reg_gio_r_masked_intr___pa5___width 1 +#define reg_gio_r_masked_intr___pa5___bit 5 +#define reg_gio_r_masked_intr___pa6___lsb 6 +#define reg_gio_r_masked_intr___pa6___width 1 +#define reg_gio_r_masked_intr___pa6___bit 6 +#define reg_gio_r_masked_intr___pa7___lsb 7 +#define reg_gio_r_masked_intr___pa7___width 1 +#define reg_gio_r_masked_intr___pa7___bit 7 +#define reg_gio_r_masked_intr_offset 28 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 18 +#define reg_gio_rw_pb_dout_offset 32 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 18 +#define reg_gio_r_pb_din_offset 36 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 18 +#define reg_gio_rw_pb_oe_offset 40 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 18 +#define reg_gio_rw_pc_dout_offset 48 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 18 +#define reg_gio_r_pc_din_offset 52 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 18 +#define reg_gio_rw_pc_oe_offset 56 + +/* Register rw_pd_dout, scope gio, type rw */ +#define reg_gio_rw_pd_dout___data___lsb 0 +#define reg_gio_rw_pd_dout___data___width 18 +#define reg_gio_rw_pd_dout_offset 64 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 18 +#define reg_gio_r_pd_din_offset 68 + +/* Register rw_pd_oe, scope gio, type rw */ +#define reg_gio_rw_pd_oe___oe___lsb 0 +#define reg_gio_rw_pd_oe___oe___width 18 +#define reg_gio_rw_pd_oe_offset 72 + +/* Register rw_pe_dout, scope gio, type rw */ +#define reg_gio_rw_pe_dout___data___lsb 0 +#define reg_gio_rw_pe_dout___data___width 18 +#define reg_gio_rw_pe_dout_offset 80 + +/* Register r_pe_din, scope gio, type r */ +#define reg_gio_r_pe_din___data___lsb 0 +#define reg_gio_r_pe_din___data___width 18 +#define reg_gio_r_pe_din_offset 84 + +/* Register rw_pe_oe, scope gio, type rw */ +#define reg_gio_rw_pe_oe___oe___lsb 0 +#define reg_gio_rw_pe_oe___oe___width 18 +#define reg_gio_rw_pe_oe_offset 88 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_hi 0x00000001 +#define regk_gio_lo 0x00000002 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_off 0x00000000 +#define regk_gio_posedge 0x00000005 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_pd_oe_default 0x00000000 +#define regk_gio_rw_pe_oe_default 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000000..30cf5a936b64 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,632 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_pa___pa0___lsb 0 +#define reg_pinmux_rw_pa___pa0___width 1 +#define reg_pinmux_rw_pa___pa0___bit 0 +#define reg_pinmux_rw_pa___pa1___lsb 1 +#define reg_pinmux_rw_pa___pa1___width 1 +#define reg_pinmux_rw_pa___pa1___bit 1 +#define reg_pinmux_rw_pa___pa2___lsb 2 +#define reg_pinmux_rw_pa___pa2___width 1 +#define reg_pinmux_rw_pa___pa2___bit 2 +#define reg_pinmux_rw_pa___pa3___lsb 3 +#define reg_pinmux_rw_pa___pa3___width 1 +#define reg_pinmux_rw_pa___pa3___bit 3 +#define reg_pinmux_rw_pa___pa4___lsb 4 +#define reg_pinmux_rw_pa___pa4___width 1 +#define reg_pinmux_rw_pa___pa4___bit 4 +#define reg_pinmux_rw_pa___pa5___lsb 5 +#define reg_pinmux_rw_pa___pa5___width 1 +#define reg_pinmux_rw_pa___pa5___bit 5 +#define reg_pinmux_rw_pa___pa6___lsb 6 +#define reg_pinmux_rw_pa___pa6___width 1 +#define reg_pinmux_rw_pa___pa6___bit 6 +#define reg_pinmux_rw_pa___pa7___lsb 7 +#define reg_pinmux_rw_pa___pa7___width 1 +#define reg_pinmux_rw_pa___pa7___bit 7 +#define reg_pinmux_rw_pa___csp2_n___lsb 8 +#define reg_pinmux_rw_pa___csp2_n___width 1 +#define reg_pinmux_rw_pa___csp2_n___bit 8 +#define reg_pinmux_rw_pa___csp3_n___lsb 9 +#define reg_pinmux_rw_pa___csp3_n___width 1 +#define reg_pinmux_rw_pa___csp3_n___bit 9 +#define reg_pinmux_rw_pa___csp5_n___lsb 10 +#define reg_pinmux_rw_pa___csp5_n___width 1 +#define reg_pinmux_rw_pa___csp5_n___bit 10 +#define reg_pinmux_rw_pa___csp6_n___lsb 11 +#define reg_pinmux_rw_pa___csp6_n___width 1 +#define reg_pinmux_rw_pa___csp6_n___bit 11 +#define reg_pinmux_rw_pa___hsh4___lsb 12 +#define reg_pinmux_rw_pa___hsh4___width 1 +#define reg_pinmux_rw_pa___hsh4___bit 12 +#define reg_pinmux_rw_pa___hsh5___lsb 13 +#define reg_pinmux_rw_pa___hsh5___width 1 +#define reg_pinmux_rw_pa___hsh5___bit 13 +#define reg_pinmux_rw_pa___hsh6___lsb 14 +#define reg_pinmux_rw_pa___hsh6___width 1 +#define reg_pinmux_rw_pa___hsh6___bit 14 +#define reg_pinmux_rw_pa___hsh7___lsb 15 +#define reg_pinmux_rw_pa___hsh7___width 1 +#define reg_pinmux_rw_pa___hsh7___bit 15 +#define reg_pinmux_rw_pa_offset 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___ser1___lsb 0 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 0 +#define reg_pinmux_rw_hwprot___ser2___lsb 1 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 1 +#define reg_pinmux_rw_hwprot___ser3___lsb 2 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 2 +#define reg_pinmux_rw_hwprot___sser0___lsb 3 +#define reg_pinmux_rw_hwprot___sser0___width 1 +#define reg_pinmux_rw_hwprot___sser0___bit 3 +#define reg_pinmux_rw_hwprot___sser1___lsb 4 +#define reg_pinmux_rw_hwprot___sser1___width 1 +#define reg_pinmux_rw_hwprot___sser1___bit 4 +#define reg_pinmux_rw_hwprot___ata0___lsb 5 +#define reg_pinmux_rw_hwprot___ata0___width 1 +#define reg_pinmux_rw_hwprot___ata0___bit 5 +#define reg_pinmux_rw_hwprot___ata1___lsb 6 +#define reg_pinmux_rw_hwprot___ata1___width 1 +#define reg_pinmux_rw_hwprot___ata1___bit 6 +#define reg_pinmux_rw_hwprot___ata2___lsb 7 +#define reg_pinmux_rw_hwprot___ata2___width 1 +#define reg_pinmux_rw_hwprot___ata2___bit 7 +#define reg_pinmux_rw_hwprot___ata3___lsb 8 +#define reg_pinmux_rw_hwprot___ata3___width 1 +#define reg_pinmux_rw_hwprot___ata3___bit 8 +#define reg_pinmux_rw_hwprot___ata___lsb 9 +#define reg_pinmux_rw_hwprot___ata___width 1 +#define reg_pinmux_rw_hwprot___ata___bit 9 +#define reg_pinmux_rw_hwprot___eth1___lsb 10 +#define reg_pinmux_rw_hwprot___eth1___width 1 +#define reg_pinmux_rw_hwprot___eth1___bit 10 +#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 +#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 +#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 +#define reg_pinmux_rw_hwprot___timer___lsb 12 +#define reg_pinmux_rw_hwprot___timer___width 1 +#define reg_pinmux_rw_hwprot___timer___bit 12 +#define reg_pinmux_rw_hwprot___p21___lsb 13 +#define reg_pinmux_rw_hwprot___p21___width 1 +#define reg_pinmux_rw_hwprot___p21___bit 13 +#define reg_pinmux_rw_hwprot_offset 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_gio___pb0___lsb 0 +#define reg_pinmux_rw_pb_gio___pb0___width 1 +#define reg_pinmux_rw_pb_gio___pb0___bit 0 +#define reg_pinmux_rw_pb_gio___pb1___lsb 1 +#define reg_pinmux_rw_pb_gio___pb1___width 1 +#define reg_pinmux_rw_pb_gio___pb1___bit 1 +#define reg_pinmux_rw_pb_gio___pb2___lsb 2 +#define reg_pinmux_rw_pb_gio___pb2___width 1 +#define reg_pinmux_rw_pb_gio___pb2___bit 2 +#define reg_pinmux_rw_pb_gio___pb3___lsb 3 +#define reg_pinmux_rw_pb_gio___pb3___width 1 +#define reg_pinmux_rw_pb_gio___pb3___bit 3 +#define reg_pinmux_rw_pb_gio___pb4___lsb 4 +#define reg_pinmux_rw_pb_gio___pb4___width 1 +#define reg_pinmux_rw_pb_gio___pb4___bit 4 +#define reg_pinmux_rw_pb_gio___pb5___lsb 5 +#define reg_pinmux_rw_pb_gio___pb5___width 1 +#define reg_pinmux_rw_pb_gio___pb5___bit 5 +#define reg_pinmux_rw_pb_gio___pb6___lsb 6 +#define reg_pinmux_rw_pb_gio___pb6___width 1 +#define reg_pinmux_rw_pb_gio___pb6___bit 6 +#define reg_pinmux_rw_pb_gio___pb7___lsb 7 +#define reg_pinmux_rw_pb_gio___pb7___width 1 +#define reg_pinmux_rw_pb_gio___pb7___bit 7 +#define reg_pinmux_rw_pb_gio___pb8___lsb 8 +#define reg_pinmux_rw_pb_gio___pb8___width 1 +#define reg_pinmux_rw_pb_gio___pb8___bit 8 +#define reg_pinmux_rw_pb_gio___pb9___lsb 9 +#define reg_pinmux_rw_pb_gio___pb9___width 1 +#define reg_pinmux_rw_pb_gio___pb9___bit 9 +#define reg_pinmux_rw_pb_gio___pb10___lsb 10 +#define reg_pinmux_rw_pb_gio___pb10___width 1 +#define reg_pinmux_rw_pb_gio___pb10___bit 10 +#define reg_pinmux_rw_pb_gio___pb11___lsb 11 +#define reg_pinmux_rw_pb_gio___pb11___width 1 +#define reg_pinmux_rw_pb_gio___pb11___bit 11 +#define reg_pinmux_rw_pb_gio___pb12___lsb 12 +#define reg_pinmux_rw_pb_gio___pb12___width 1 +#define reg_pinmux_rw_pb_gio___pb12___bit 12 +#define reg_pinmux_rw_pb_gio___pb13___lsb 13 +#define reg_pinmux_rw_pb_gio___pb13___width 1 +#define reg_pinmux_rw_pb_gio___pb13___bit 13 +#define reg_pinmux_rw_pb_gio___pb14___lsb 14 +#define reg_pinmux_rw_pb_gio___pb14___width 1 +#define reg_pinmux_rw_pb_gio___pb14___bit 14 +#define reg_pinmux_rw_pb_gio___pb15___lsb 15 +#define reg_pinmux_rw_pb_gio___pb15___width 1 +#define reg_pinmux_rw_pb_gio___pb15___bit 15 +#define reg_pinmux_rw_pb_gio___pb16___lsb 16 +#define reg_pinmux_rw_pb_gio___pb16___width 1 +#define reg_pinmux_rw_pb_gio___pb16___bit 16 +#define reg_pinmux_rw_pb_gio___pb17___lsb 17 +#define reg_pinmux_rw_pb_gio___pb17___width 1 +#define reg_pinmux_rw_pb_gio___pb17___bit 17 +#define reg_pinmux_rw_pb_gio_offset 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_iop___pb0___lsb 0 +#define reg_pinmux_rw_pb_iop___pb0___width 1 +#define reg_pinmux_rw_pb_iop___pb0___bit 0 +#define reg_pinmux_rw_pb_iop___pb1___lsb 1 +#define reg_pinmux_rw_pb_iop___pb1___width 1 +#define reg_pinmux_rw_pb_iop___pb1___bit 1 +#define reg_pinmux_rw_pb_iop___pb2___lsb 2 +#define reg_pinmux_rw_pb_iop___pb2___width 1 +#define reg_pinmux_rw_pb_iop___pb2___bit 2 +#define reg_pinmux_rw_pb_iop___pb3___lsb 3 +#define reg_pinmux_rw_pb_iop___pb3___width 1 +#define reg_pinmux_rw_pb_iop___pb3___bit 3 +#define reg_pinmux_rw_pb_iop___pb4___lsb 4 +#define reg_pinmux_rw_pb_iop___pb4___width 1 +#define reg_pinmux_rw_pb_iop___pb4___bit 4 +#define reg_pinmux_rw_pb_iop___pb5___lsb 5 +#define reg_pinmux_rw_pb_iop___pb5___width 1 +#define reg_pinmux_rw_pb_iop___pb5___bit 5 +#define reg_pinmux_rw_pb_iop___pb6___lsb 6 +#define reg_pinmux_rw_pb_iop___pb6___width 1 +#define reg_pinmux_rw_pb_iop___pb6___bit 6 +#define reg_pinmux_rw_pb_iop___pb7___lsb 7 +#define reg_pinmux_rw_pb_iop___pb7___width 1 +#define reg_pinmux_rw_pb_iop___pb7___bit 7 +#define reg_pinmux_rw_pb_iop___pb8___lsb 8 +#define reg_pinmux_rw_pb_iop___pb8___width 1 +#define reg_pinmux_rw_pb_iop___pb8___bit 8 +#define reg_pinmux_rw_pb_iop___pb9___lsb 9 +#define reg_pinmux_rw_pb_iop___pb9___width 1 +#define reg_pinmux_rw_pb_iop___pb9___bit 9 +#define reg_pinmux_rw_pb_iop___pb10___lsb 10 +#define reg_pinmux_rw_pb_iop___pb10___width 1 +#define reg_pinmux_rw_pb_iop___pb10___bit 10 +#define reg_pinmux_rw_pb_iop___pb11___lsb 11 +#define reg_pinmux_rw_pb_iop___pb11___width 1 +#define reg_pinmux_rw_pb_iop___pb11___bit 11 +#define reg_pinmux_rw_pb_iop___pb12___lsb 12 +#define reg_pinmux_rw_pb_iop___pb12___width 1 +#define reg_pinmux_rw_pb_iop___pb12___bit 12 +#define reg_pinmux_rw_pb_iop___pb13___lsb 13 +#define reg_pinmux_rw_pb_iop___pb13___width 1 +#define reg_pinmux_rw_pb_iop___pb13___bit 13 +#define reg_pinmux_rw_pb_iop___pb14___lsb 14 +#define reg_pinmux_rw_pb_iop___pb14___width 1 +#define reg_pinmux_rw_pb_iop___pb14___bit 14 +#define reg_pinmux_rw_pb_iop___pb15___lsb 15 +#define reg_pinmux_rw_pb_iop___pb15___width 1 +#define reg_pinmux_rw_pb_iop___pb15___bit 15 +#define reg_pinmux_rw_pb_iop___pb16___lsb 16 +#define reg_pinmux_rw_pb_iop___pb16___width 1 +#define reg_pinmux_rw_pb_iop___pb16___bit 16 +#define reg_pinmux_rw_pb_iop___pb17___lsb 17 +#define reg_pinmux_rw_pb_iop___pb17___width 1 +#define reg_pinmux_rw_pb_iop___pb17___bit 17 +#define reg_pinmux_rw_pb_iop_offset 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_gio___pc0___lsb 0 +#define reg_pinmux_rw_pc_gio___pc0___width 1 +#define reg_pinmux_rw_pc_gio___pc0___bit 0 +#define reg_pinmux_rw_pc_gio___pc1___lsb 1 +#define reg_pinmux_rw_pc_gio___pc1___width 1 +#define reg_pinmux_rw_pc_gio___pc1___bit 1 +#define reg_pinmux_rw_pc_gio___pc2___lsb 2 +#define reg_pinmux_rw_pc_gio___pc2___width 1 +#define reg_pinmux_rw_pc_gio___pc2___bit 2 +#define reg_pinmux_rw_pc_gio___pc3___lsb 3 +#define reg_pinmux_rw_pc_gio___pc3___width 1 +#define reg_pinmux_rw_pc_gio___pc3___bit 3 +#define reg_pinmux_rw_pc_gio___pc4___lsb 4 +#define reg_pinmux_rw_pc_gio___pc4___width 1 +#define reg_pinmux_rw_pc_gio___pc4___bit 4 +#define reg_pinmux_rw_pc_gio___pc5___lsb 5 +#define reg_pinmux_rw_pc_gio___pc5___width 1 +#define reg_pinmux_rw_pc_gio___pc5___bit 5 +#define reg_pinmux_rw_pc_gio___pc6___lsb 6 +#define reg_pinmux_rw_pc_gio___pc6___width 1 +#define reg_pinmux_rw_pc_gio___pc6___bit 6 +#define reg_pinmux_rw_pc_gio___pc7___lsb 7 +#define reg_pinmux_rw_pc_gio___pc7___width 1 +#define reg_pinmux_rw_pc_gio___pc7___bit 7 +#define reg_pinmux_rw_pc_gio___pc8___lsb 8 +#define reg_pinmux_rw_pc_gio___pc8___width 1 +#define reg_pinmux_rw_pc_gio___pc8___bit 8 +#define reg_pinmux_rw_pc_gio___pc9___lsb 9 +#define reg_pinmux_rw_pc_gio___pc9___width 1 +#define reg_pinmux_rw_pc_gio___pc9___bit 9 +#define reg_pinmux_rw_pc_gio___pc10___lsb 10 +#define reg_pinmux_rw_pc_gio___pc10___width 1 +#define reg_pinmux_rw_pc_gio___pc10___bit 10 +#define reg_pinmux_rw_pc_gio___pc11___lsb 11 +#define reg_pinmux_rw_pc_gio___pc11___width 1 +#define reg_pinmux_rw_pc_gio___pc11___bit 11 +#define reg_pinmux_rw_pc_gio___pc12___lsb 12 +#define reg_pinmux_rw_pc_gio___pc12___width 1 +#define reg_pinmux_rw_pc_gio___pc12___bit 12 +#define reg_pinmux_rw_pc_gio___pc13___lsb 13 +#define reg_pinmux_rw_pc_gio___pc13___width 1 +#define reg_pinmux_rw_pc_gio___pc13___bit 13 +#define reg_pinmux_rw_pc_gio___pc14___lsb 14 +#define reg_pinmux_rw_pc_gio___pc14___width 1 +#define reg_pinmux_rw_pc_gio___pc14___bit 14 +#define reg_pinmux_rw_pc_gio___pc15___lsb 15 +#define reg_pinmux_rw_pc_gio___pc15___width 1 +#define reg_pinmux_rw_pc_gio___pc15___bit 15 +#define reg_pinmux_rw_pc_gio___pc16___lsb 16 +#define reg_pinmux_rw_pc_gio___pc16___width 1 +#define reg_pinmux_rw_pc_gio___pc16___bit 16 +#define reg_pinmux_rw_pc_gio___pc17___lsb 17 +#define reg_pinmux_rw_pc_gio___pc17___width 1 +#define reg_pinmux_rw_pc_gio___pc17___bit 17 +#define reg_pinmux_rw_pc_gio_offset 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_iop___pc0___lsb 0 +#define reg_pinmux_rw_pc_iop___pc0___width 1 +#define reg_pinmux_rw_pc_iop___pc0___bit 0 +#define reg_pinmux_rw_pc_iop___pc1___lsb 1 +#define reg_pinmux_rw_pc_iop___pc1___width 1 +#define reg_pinmux_rw_pc_iop___pc1___bit 1 +#define reg_pinmux_rw_pc_iop___pc2___lsb 2 +#define reg_pinmux_rw_pc_iop___pc2___width 1 +#define reg_pinmux_rw_pc_iop___pc2___bit 2 +#define reg_pinmux_rw_pc_iop___pc3___lsb 3 +#define reg_pinmux_rw_pc_iop___pc3___width 1 +#define reg_pinmux_rw_pc_iop___pc3___bit 3 +#define reg_pinmux_rw_pc_iop___pc4___lsb 4 +#define reg_pinmux_rw_pc_iop___pc4___width 1 +#define reg_pinmux_rw_pc_iop___pc4___bit 4 +#define reg_pinmux_rw_pc_iop___pc5___lsb 5 +#define reg_pinmux_rw_pc_iop___pc5___width 1 +#define reg_pinmux_rw_pc_iop___pc5___bit 5 +#define reg_pinmux_rw_pc_iop___pc6___lsb 6 +#define reg_pinmux_rw_pc_iop___pc6___width 1 +#define reg_pinmux_rw_pc_iop___pc6___bit 6 +#define reg_pinmux_rw_pc_iop___pc7___lsb 7 +#define reg_pinmux_rw_pc_iop___pc7___width 1 +#define reg_pinmux_rw_pc_iop___pc7___bit 7 +#define reg_pinmux_rw_pc_iop___pc8___lsb 8 +#define reg_pinmux_rw_pc_iop___pc8___width 1 +#define reg_pinmux_rw_pc_iop___pc8___bit 8 +#define reg_pinmux_rw_pc_iop___pc9___lsb 9 +#define reg_pinmux_rw_pc_iop___pc9___width 1 +#define reg_pinmux_rw_pc_iop___pc9___bit 9 +#define reg_pinmux_rw_pc_iop___pc10___lsb 10 +#define reg_pinmux_rw_pc_iop___pc10___width 1 +#define reg_pinmux_rw_pc_iop___pc10___bit 10 +#define reg_pinmux_rw_pc_iop___pc11___lsb 11 +#define reg_pinmux_rw_pc_iop___pc11___width 1 +#define reg_pinmux_rw_pc_iop___pc11___bit 11 +#define reg_pinmux_rw_pc_iop___pc12___lsb 12 +#define reg_pinmux_rw_pc_iop___pc12___width 1 +#define reg_pinmux_rw_pc_iop___pc12___bit 12 +#define reg_pinmux_rw_pc_iop___pc13___lsb 13 +#define reg_pinmux_rw_pc_iop___pc13___width 1 +#define reg_pinmux_rw_pc_iop___pc13___bit 13 +#define reg_pinmux_rw_pc_iop___pc14___lsb 14 +#define reg_pinmux_rw_pc_iop___pc14___width 1 +#define reg_pinmux_rw_pc_iop___pc14___bit 14 +#define reg_pinmux_rw_pc_iop___pc15___lsb 15 +#define reg_pinmux_rw_pc_iop___pc15___width 1 +#define reg_pinmux_rw_pc_iop___pc15___bit 15 +#define reg_pinmux_rw_pc_iop___pc16___lsb 16 +#define reg_pinmux_rw_pc_iop___pc16___width 1 +#define reg_pinmux_rw_pc_iop___pc16___bit 16 +#define reg_pinmux_rw_pc_iop___pc17___lsb 17 +#define reg_pinmux_rw_pc_iop___pc17___width 1 +#define reg_pinmux_rw_pc_iop___pc17___bit 17 +#define reg_pinmux_rw_pc_iop_offset 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_gio___pd0___lsb 0 +#define reg_pinmux_rw_pd_gio___pd0___width 1 +#define reg_pinmux_rw_pd_gio___pd0___bit 0 +#define reg_pinmux_rw_pd_gio___pd1___lsb 1 +#define reg_pinmux_rw_pd_gio___pd1___width 1 +#define reg_pinmux_rw_pd_gio___pd1___bit 1 +#define reg_pinmux_rw_pd_gio___pd2___lsb 2 +#define reg_pinmux_rw_pd_gio___pd2___width 1 +#define reg_pinmux_rw_pd_gio___pd2___bit 2 +#define reg_pinmux_rw_pd_gio___pd3___lsb 3 +#define reg_pinmux_rw_pd_gio___pd3___width 1 +#define reg_pinmux_rw_pd_gio___pd3___bit 3 +#define reg_pinmux_rw_pd_gio___pd4___lsb 4 +#define reg_pinmux_rw_pd_gio___pd4___width 1 +#define reg_pinmux_rw_pd_gio___pd4___bit 4 +#define reg_pinmux_rw_pd_gio___pd5___lsb 5 +#define reg_pinmux_rw_pd_gio___pd5___width 1 +#define reg_pinmux_rw_pd_gio___pd5___bit 5 +#define reg_pinmux_rw_pd_gio___pd6___lsb 6 +#define reg_pinmux_rw_pd_gio___pd6___width 1 +#define reg_pinmux_rw_pd_gio___pd6___bit 6 +#define reg_pinmux_rw_pd_gio___pd7___lsb 7 +#define reg_pinmux_rw_pd_gio___pd7___width 1 +#define reg_pinmux_rw_pd_gio___pd7___bit 7 +#define reg_pinmux_rw_pd_gio___pd8___lsb 8 +#define reg_pinmux_rw_pd_gio___pd8___width 1 +#define reg_pinmux_rw_pd_gio___pd8___bit 8 +#define reg_pinmux_rw_pd_gio___pd9___lsb 9 +#define reg_pinmux_rw_pd_gio___pd9___width 1 +#define reg_pinmux_rw_pd_gio___pd9___bit 9 +#define reg_pinmux_rw_pd_gio___pd10___lsb 10 +#define reg_pinmux_rw_pd_gio___pd10___width 1 +#define reg_pinmux_rw_pd_gio___pd10___bit 10 +#define reg_pinmux_rw_pd_gio___pd11___lsb 11 +#define reg_pinmux_rw_pd_gio___pd11___width 1 +#define reg_pinmux_rw_pd_gio___pd11___bit 11 +#define reg_pinmux_rw_pd_gio___pd12___lsb 12 +#define reg_pinmux_rw_pd_gio___pd12___width 1 +#define reg_pinmux_rw_pd_gio___pd12___bit 12 +#define reg_pinmux_rw_pd_gio___pd13___lsb 13 +#define reg_pinmux_rw_pd_gio___pd13___width 1 +#define reg_pinmux_rw_pd_gio___pd13___bit 13 +#define reg_pinmux_rw_pd_gio___pd14___lsb 14 +#define reg_pinmux_rw_pd_gio___pd14___width 1 +#define reg_pinmux_rw_pd_gio___pd14___bit 14 +#define reg_pinmux_rw_pd_gio___pd15___lsb 15 +#define reg_pinmux_rw_pd_gio___pd15___width 1 +#define reg_pinmux_rw_pd_gio___pd15___bit 15 +#define reg_pinmux_rw_pd_gio___pd16___lsb 16 +#define reg_pinmux_rw_pd_gio___pd16___width 1 +#define reg_pinmux_rw_pd_gio___pd16___bit 16 +#define reg_pinmux_rw_pd_gio___pd17___lsb 17 +#define reg_pinmux_rw_pd_gio___pd17___width 1 +#define reg_pinmux_rw_pd_gio___pd17___bit 17 +#define reg_pinmux_rw_pd_gio_offset 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_iop___pd0___lsb 0 +#define reg_pinmux_rw_pd_iop___pd0___width 1 +#define reg_pinmux_rw_pd_iop___pd0___bit 0 +#define reg_pinmux_rw_pd_iop___pd1___lsb 1 +#define reg_pinmux_rw_pd_iop___pd1___width 1 +#define reg_pinmux_rw_pd_iop___pd1___bit 1 +#define reg_pinmux_rw_pd_iop___pd2___lsb 2 +#define reg_pinmux_rw_pd_iop___pd2___width 1 +#define reg_pinmux_rw_pd_iop___pd2___bit 2 +#define reg_pinmux_rw_pd_iop___pd3___lsb 3 +#define reg_pinmux_rw_pd_iop___pd3___width 1 +#define reg_pinmux_rw_pd_iop___pd3___bit 3 +#define reg_pinmux_rw_pd_iop___pd4___lsb 4 +#define reg_pinmux_rw_pd_iop___pd4___width 1 +#define reg_pinmux_rw_pd_iop___pd4___bit 4 +#define reg_pinmux_rw_pd_iop___pd5___lsb 5 +#define reg_pinmux_rw_pd_iop___pd5___width 1 +#define reg_pinmux_rw_pd_iop___pd5___bit 5 +#define reg_pinmux_rw_pd_iop___pd6___lsb 6 +#define reg_pinmux_rw_pd_iop___pd6___width 1 +#define reg_pinmux_rw_pd_iop___pd6___bit 6 +#define reg_pinmux_rw_pd_iop___pd7___lsb 7 +#define reg_pinmux_rw_pd_iop___pd7___width 1 +#define reg_pinmux_rw_pd_iop___pd7___bit 7 +#define reg_pinmux_rw_pd_iop___pd8___lsb 8 +#define reg_pinmux_rw_pd_iop___pd8___width 1 +#define reg_pinmux_rw_pd_iop___pd8___bit 8 +#define reg_pinmux_rw_pd_iop___pd9___lsb 9 +#define reg_pinmux_rw_pd_iop___pd9___width 1 +#define reg_pinmux_rw_pd_iop___pd9___bit 9 +#define reg_pinmux_rw_pd_iop___pd10___lsb 10 +#define reg_pinmux_rw_pd_iop___pd10___width 1 +#define reg_pinmux_rw_pd_iop___pd10___bit 10 +#define reg_pinmux_rw_pd_iop___pd11___lsb 11 +#define reg_pinmux_rw_pd_iop___pd11___width 1 +#define reg_pinmux_rw_pd_iop___pd11___bit 11 +#define reg_pinmux_rw_pd_iop___pd12___lsb 12 +#define reg_pinmux_rw_pd_iop___pd12___width 1 +#define reg_pinmux_rw_pd_iop___pd12___bit 12 +#define reg_pinmux_rw_pd_iop___pd13___lsb 13 +#define reg_pinmux_rw_pd_iop___pd13___width 1 +#define reg_pinmux_rw_pd_iop___pd13___bit 13 +#define reg_pinmux_rw_pd_iop___pd14___lsb 14 +#define reg_pinmux_rw_pd_iop___pd14___width 1 +#define reg_pinmux_rw_pd_iop___pd14___bit 14 +#define reg_pinmux_rw_pd_iop___pd15___lsb 15 +#define reg_pinmux_rw_pd_iop___pd15___width 1 +#define reg_pinmux_rw_pd_iop___pd15___bit 15 +#define reg_pinmux_rw_pd_iop___pd16___lsb 16 +#define reg_pinmux_rw_pd_iop___pd16___width 1 +#define reg_pinmux_rw_pd_iop___pd16___bit 16 +#define reg_pinmux_rw_pd_iop___pd17___lsb 17 +#define reg_pinmux_rw_pd_iop___pd17___width 1 +#define reg_pinmux_rw_pd_iop___pd17___bit 17 +#define reg_pinmux_rw_pd_iop_offset 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_gio___pe0___lsb 0 +#define reg_pinmux_rw_pe_gio___pe0___width 1 +#define reg_pinmux_rw_pe_gio___pe0___bit 0 +#define reg_pinmux_rw_pe_gio___pe1___lsb 1 +#define reg_pinmux_rw_pe_gio___pe1___width 1 +#define reg_pinmux_rw_pe_gio___pe1___bit 1 +#define reg_pinmux_rw_pe_gio___pe2___lsb 2 +#define reg_pinmux_rw_pe_gio___pe2___width 1 +#define reg_pinmux_rw_pe_gio___pe2___bit 2 +#define reg_pinmux_rw_pe_gio___pe3___lsb 3 +#define reg_pinmux_rw_pe_gio___pe3___width 1 +#define reg_pinmux_rw_pe_gio___pe3___bit 3 +#define reg_pinmux_rw_pe_gio___pe4___lsb 4 +#define reg_pinmux_rw_pe_gio___pe4___width 1 +#define reg_pinmux_rw_pe_gio___pe4___bit 4 +#define reg_pinmux_rw_pe_gio___pe5___lsb 5 +#define reg_pinmux_rw_pe_gio___pe5___width 1 +#define reg_pinmux_rw_pe_gio___pe5___bit 5 +#define reg_pinmux_rw_pe_gio___pe6___lsb 6 +#define reg_pinmux_rw_pe_gio___pe6___width 1 +#define reg_pinmux_rw_pe_gio___pe6___bit 6 +#define reg_pinmux_rw_pe_gio___pe7___lsb 7 +#define reg_pinmux_rw_pe_gio___pe7___width 1 +#define reg_pinmux_rw_pe_gio___pe7___bit 7 +#define reg_pinmux_rw_pe_gio___pe8___lsb 8 +#define reg_pinmux_rw_pe_gio___pe8___width 1 +#define reg_pinmux_rw_pe_gio___pe8___bit 8 +#define reg_pinmux_rw_pe_gio___pe9___lsb 9 +#define reg_pinmux_rw_pe_gio___pe9___width 1 +#define reg_pinmux_rw_pe_gio___pe9___bit 9 +#define reg_pinmux_rw_pe_gio___pe10___lsb 10 +#define reg_pinmux_rw_pe_gio___pe10___width 1 +#define reg_pinmux_rw_pe_gio___pe10___bit 10 +#define reg_pinmux_rw_pe_gio___pe11___lsb 11 +#define reg_pinmux_rw_pe_gio___pe11___width 1 +#define reg_pinmux_rw_pe_gio___pe11___bit 11 +#define reg_pinmux_rw_pe_gio___pe12___lsb 12 +#define reg_pinmux_rw_pe_gio___pe12___width 1 +#define reg_pinmux_rw_pe_gio___pe12___bit 12 +#define reg_pinmux_rw_pe_gio___pe13___lsb 13 +#define reg_pinmux_rw_pe_gio___pe13___width 1 +#define reg_pinmux_rw_pe_gio___pe13___bit 13 +#define reg_pinmux_rw_pe_gio___pe14___lsb 14 +#define reg_pinmux_rw_pe_gio___pe14___width 1 +#define reg_pinmux_rw_pe_gio___pe14___bit 14 +#define reg_pinmux_rw_pe_gio___pe15___lsb 15 +#define reg_pinmux_rw_pe_gio___pe15___width 1 +#define reg_pinmux_rw_pe_gio___pe15___bit 15 +#define reg_pinmux_rw_pe_gio___pe16___lsb 16 +#define reg_pinmux_rw_pe_gio___pe16___width 1 +#define reg_pinmux_rw_pe_gio___pe16___bit 16 +#define reg_pinmux_rw_pe_gio___pe17___lsb 17 +#define reg_pinmux_rw_pe_gio___pe17___width 1 +#define reg_pinmux_rw_pe_gio___pe17___bit 17 +#define reg_pinmux_rw_pe_gio_offset 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_iop___pe0___lsb 0 +#define reg_pinmux_rw_pe_iop___pe0___width 1 +#define reg_pinmux_rw_pe_iop___pe0___bit 0 +#define reg_pinmux_rw_pe_iop___pe1___lsb 1 +#define reg_pinmux_rw_pe_iop___pe1___width 1 +#define reg_pinmux_rw_pe_iop___pe1___bit 1 +#define reg_pinmux_rw_pe_iop___pe2___lsb 2 +#define reg_pinmux_rw_pe_iop___pe2___width 1 +#define reg_pinmux_rw_pe_iop___pe2___bit 2 +#define reg_pinmux_rw_pe_iop___pe3___lsb 3 +#define reg_pinmux_rw_pe_iop___pe3___width 1 +#define reg_pinmux_rw_pe_iop___pe3___bit 3 +#define reg_pinmux_rw_pe_iop___pe4___lsb 4 +#define reg_pinmux_rw_pe_iop___pe4___width 1 +#define reg_pinmux_rw_pe_iop___pe4___bit 4 +#define reg_pinmux_rw_pe_iop___pe5___lsb 5 +#define reg_pinmux_rw_pe_iop___pe5___width 1 +#define reg_pinmux_rw_pe_iop___pe5___bit 5 +#define reg_pinmux_rw_pe_iop___pe6___lsb 6 +#define reg_pinmux_rw_pe_iop___pe6___width 1 +#define reg_pinmux_rw_pe_iop___pe6___bit 6 +#define reg_pinmux_rw_pe_iop___pe7___lsb 7 +#define reg_pinmux_rw_pe_iop___pe7___width 1 +#define reg_pinmux_rw_pe_iop___pe7___bit 7 +#define reg_pinmux_rw_pe_iop___pe8___lsb 8 +#define reg_pinmux_rw_pe_iop___pe8___width 1 +#define reg_pinmux_rw_pe_iop___pe8___bit 8 +#define reg_pinmux_rw_pe_iop___pe9___lsb 9 +#define reg_pinmux_rw_pe_iop___pe9___width 1 +#define reg_pinmux_rw_pe_iop___pe9___bit 9 +#define reg_pinmux_rw_pe_iop___pe10___lsb 10 +#define reg_pinmux_rw_pe_iop___pe10___width 1 +#define reg_pinmux_rw_pe_iop___pe10___bit 10 +#define reg_pinmux_rw_pe_iop___pe11___lsb 11 +#define reg_pinmux_rw_pe_iop___pe11___width 1 +#define reg_pinmux_rw_pe_iop___pe11___bit 11 +#define reg_pinmux_rw_pe_iop___pe12___lsb 12 +#define reg_pinmux_rw_pe_iop___pe12___width 1 +#define reg_pinmux_rw_pe_iop___pe12___bit 12 +#define reg_pinmux_rw_pe_iop___pe13___lsb 13 +#define reg_pinmux_rw_pe_iop___pe13___width 1 +#define reg_pinmux_rw_pe_iop___pe13___bit 13 +#define reg_pinmux_rw_pe_iop___pe14___lsb 14 +#define reg_pinmux_rw_pe_iop___pe14___width 1 +#define reg_pinmux_rw_pe_iop___pe14___bit 14 +#define reg_pinmux_rw_pe_iop___pe15___lsb 15 +#define reg_pinmux_rw_pe_iop___pe15___width 1 +#define reg_pinmux_rw_pe_iop___pe15___bit 15 +#define reg_pinmux_rw_pe_iop___pe16___lsb 16 +#define reg_pinmux_rw_pe_iop___pe16___width 1 +#define reg_pinmux_rw_pe_iop___pe16___bit 16 +#define reg_pinmux_rw_pe_iop___pe17___lsb 17 +#define reg_pinmux_rw_pe_iop___pe17___width 1 +#define reg_pinmux_rw_pe_iop___pe17___bit 17 +#define reg_pinmux_rw_pe_iop_offset 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 +#define reg_pinmux_rw_usb_phy___en_usb0___width 1 +#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 +#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 +#define reg_pinmux_rw_usb_phy___en_usb1___width 1 +#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 +#define reg_pinmux_rw_usb_phy_offset 40 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_pa_default 0x00000000 +#define regk_pinmux_rw_pb_gio_default 0x00000000 +#define regk_pinmux_rw_pb_iop_default 0x00000000 +#define regk_pinmux_rw_pc_gio_default 0x00000000 +#define regk_pinmux_rw_pc_iop_default 0x00000000 +#define regk_pinmux_rw_pd_gio_default 0x00000000 +#define regk_pinmux_rw_pd_iop_default 0x00000000 +#define regk_pinmux_rw_pe_gio_default 0x00000000 +#define regk_pinmux_rw_pe_iop_default 0x00000000 +#define regk_pinmux_rw_usb_phy_default 0x00000000 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000000..87517aebd2cb --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h @@ -0,0 +1,96 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_artpec_mod 0xb7044000 +#define regi_ata 0xb0032000 +#define regi_ata_mod 0xb7006000 +#define regi_barber 0xb701a000 +#define regi_bif_core 0xb0014000 +#define regi_bif_dma 0xb0016000 +#define regi_bif_slave 0xb0018000 +#define regi_bif_slave_ext 0xac000000 +#define regi_bus_master 0xb703c000 +#define regi_config 0xb003c000 +#define regi_dma0 0xb0000000 +#define regi_dma1 0xb0002000 +#define regi_dma2 0xb0004000 +#define regi_dma3 0xb0006000 +#define regi_dma4 0xb0008000 +#define regi_dma5 0xb000a000 +#define regi_dma6 0xb000c000 +#define regi_dma7 0xb000e000 +#define regi_dma8 0xb0010000 +#define regi_dma9 0xb0012000 +#define regi_eth0 0xb0034000 +#define regi_eth1 0xb0036000 +#define regi_eth_mod 0xb7004000 +#define regi_eth_mod1 0xb701c000 +#define regi_eth_strmod 0xb7008000 +#define regi_eth_strmod1 0xb7032000 +#define regi_ext_dma 0xb703a000 +#define regi_ext_mem 0xb7046000 +#define regi_gen_io 0xb7016000 +#define regi_gio 0xb001a000 +#define regi_hook 0xb7000000 +#define regi_iop 0xb0020000 +#define regi_irq 0xb001c000 +#define regi_irq_nmi 0xb701e000 +#define regi_marb 0xb003e000 +#define regi_marb_bp0 0xb003e240 +#define regi_marb_bp1 0xb003e280 +#define regi_marb_bp2 0xb003e2c0 +#define regi_marb_bp3 0xb003e300 +#define regi_nand_mod 0xb7014000 +#define regi_p21 0xb002e000 +#define regi_p21_mod 0xb7042000 +#define regi_pci_mod 0xb7010000 +#define regi_pin_test 0xb7018000 +#define regi_pinmux 0xb0038000 +#define regi_sdram_chk 0xb703e000 +#define regi_sdram_mod 0xb7012000 +#define regi_ser0 0xb0026000 +#define regi_ser1 0xb0028000 +#define regi_ser2 0xb002a000 +#define regi_ser3 0xb002c000 +#define regi_ser_mod0 0xb7020000 +#define regi_ser_mod1 0xb7022000 +#define regi_ser_mod2 0xb7024000 +#define regi_ser_mod3 0xb7026000 +#define regi_smif_stat 0xb700e000 +#define regi_sser0 0xb0022000 +#define regi_sser1 0xb0024000 +#define regi_sser_mod0 0xb700a000 +#define regi_sser_mod1 0xb700c000 +#define regi_strcop 0xb0030000 +#define regi_strmux 0xb003a000 +#define regi_strmux_tst 0xb7040000 +#define regi_tap 0xb7002000 +#define regi_timer 0xb001e000 +#define regi_timer_mod 0xb7034000 +#define regi_trace 0xb0040000 +#define regi_usb0 0xb7028000 +#define regi_usb1 0xb702a000 +#define regi_usb2 0xb702c000 +#define regi_usb3 0xb702e000 +#define regi_usb_dev 0xb7030000 +#define regi_utmi_mod0 0xb7036000 +#define regi_utmi_mod1 0xb7038000 +#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000000..e1197194d5c1 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,229 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h new file mode 100644 index 000000000000..44362a62b47c --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h @@ -0,0 +1,284 @@ +#ifndef __bif_core_defs_h +#define __bif_core_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_core */ + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp1_cfg; +#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 +#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp2_cfg; +#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 +#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 2; + unsigned int gated_csp0 : 2; + unsigned int gated_csp1 : 2; + unsigned int gated_csp2 : 2; + unsigned int gated_csp3 : 2; +} reg_bif_core_rw_grp3_cfg; +#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 +#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 4; + unsigned int gated_csp4 : 2; + unsigned int gated_csp5 : 2; + unsigned int gated_csp6 : 2; +} reg_bif_core_rw_grp4_cfg; +#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 +#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int grp_sel : 5; + unsigned int dummy1 : 12; +} reg_bif_core_rw_sdram_cfg_grp0; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int dummy1 : 17; +} reg_bif_core_rw_sdram_cfg_grp1; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +typedef struct { + unsigned int cl : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int rc : 2; + unsigned int dpl : 2; + unsigned int pde : 1; + unsigned int ref : 2; + unsigned int cpd : 1; + unsigned int sdcke : 1; + unsigned int sdclk : 1; + unsigned int dummy1 : 13; +} reg_bif_core_rw_sdram_timing; +#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 +#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +typedef struct { + unsigned int cmd : 3; + unsigned int mrs_data : 15; + unsigned int dummy1 : 14; +} reg_bif_core_rw_sdram_cmd; +#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 +#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_rs_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_r_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 + + +/* Constants */ +enum { + regk_bif_core_bank2 = 0x00000000, + regk_bif_core_bank4 = 0x00000001, + regk_bif_core_bit10 = 0x0000000a, + regk_bif_core_bit11 = 0x0000000b, + regk_bif_core_bit12 = 0x0000000c, + regk_bif_core_bit13 = 0x0000000d, + regk_bif_core_bit14 = 0x0000000e, + regk_bif_core_bit15 = 0x0000000f, + regk_bif_core_bit16 = 0x00000010, + regk_bif_core_bit17 = 0x00000011, + regk_bif_core_bit18 = 0x00000012, + regk_bif_core_bit19 = 0x00000013, + regk_bif_core_bit20 = 0x00000014, + regk_bif_core_bit21 = 0x00000015, + regk_bif_core_bit22 = 0x00000016, + regk_bif_core_bit23 = 0x00000017, + regk_bif_core_bit24 = 0x00000018, + regk_bif_core_bit25 = 0x00000019, + regk_bif_core_bit26 = 0x0000001a, + regk_bif_core_bit27 = 0x0000001b, + regk_bif_core_bit28 = 0x0000001c, + regk_bif_core_bit29 = 0x0000001d, + regk_bif_core_bit9 = 0x00000009, + regk_bif_core_bw16 = 0x00000001, + regk_bif_core_bw32 = 0x00000000, + regk_bif_core_bwe = 0x00000000, + regk_bif_core_cwe = 0x00000001, + regk_bif_core_e15us = 0x00000001, + regk_bif_core_e7800ns = 0x00000002, + regk_bif_core_grp0 = 0x00000000, + regk_bif_core_grp1 = 0x00000001, + regk_bif_core_mrs = 0x00000003, + regk_bif_core_no = 0x00000000, + regk_bif_core_none = 0x00000000, + regk_bif_core_nop = 0x00000000, + regk_bif_core_off = 0x00000000, + regk_bif_core_pre = 0x00000002, + regk_bif_core_r_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rd = 0x00000002, + regk_bif_core_ref = 0x00000001, + regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rw_grp1_cfg_default = 0x000006cf, + regk_bif_core_rw_grp2_cfg_default = 0x000006cf, + regk_bif_core_rw_grp3_cfg_default = 0x000006cf, + regk_bif_core_rw_grp4_cfg_default = 0x000006cf, + regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, + regk_bif_core_slf = 0x00000004, + regk_bif_core_wr = 0x00000001, + regk_bif_core_yes = 0x00000001 +}; +#endif /* __bif_core_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h new file mode 100644 index 000000000000..3cb51a09dba7 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h @@ -0,0 +1,473 @@ +#ifndef __bif_dma_defs_h +#define __bif_dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_dma */ + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch0_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 +#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch0_addr; +#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 +#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch0_start; +#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 +#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch0_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 +#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch0_stat; +#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch1_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 +#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch1_addr; +#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 +#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch1_start; +#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 +#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch1_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 +#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch1_stat; +#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch2_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 +#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch2_addr; +#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 +#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch2_start; +#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 +#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch2_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 +#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch2_stat; +#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch3_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 +#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch3_addr; +#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 +#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch3_start; +#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 +#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch3_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 +#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch3_stat; +#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_intr_mask; +#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 +#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_ack_intr; +#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 +#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 + +/* Register r_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_intr; +#define REG_RD_ADDR_bif_dma_r_intr 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_masked_intr; +#define REG_RD_ADDR_bif_dma_r_masked_intr 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin0_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 +#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin1_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 +#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin2_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 +#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin3_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 +#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin4_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 +#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin5_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 +#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin6_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 +#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin7_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 +#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +typedef struct { + unsigned int pin0 : 1; + unsigned int pin1 : 1; + unsigned int pin2 : 1; + unsigned int pin3 : 1; + unsigned int pin4 : 1; + unsigned int pin5 : 1; + unsigned int pin6 : 1; + unsigned int pin7 : 1; + unsigned int dummy1 : 24; +} reg_bif_dma_r_pin_stat; +#define REG_RD_ADDR_bif_dma_r_pin_stat 192 + + +/* Constants */ +enum { + regk_bif_dma_as_master = 0x00000001, + regk_bif_dma_as_slave = 0x00000001, + regk_bif_dma_burst1 = 0x00000000, + regk_bif_dma_burst8 = 0x00000001, + regk_bif_dma_bw16 = 0x00000001, + regk_bif_dma_bw32 = 0x00000002, + regk_bif_dma_bw8 = 0x00000000, + regk_bif_dma_dack = 0x00000006, + regk_bif_dma_dack_inv = 0x00000007, + regk_bif_dma_force = 0x00000001, + regk_bif_dma_hi = 0x00000003, + regk_bif_dma_inv = 0x00000003, + regk_bif_dma_lo = 0x00000002, + regk_bif_dma_master = 0x00000001, + regk_bif_dma_no = 0x00000000, + regk_bif_dma_norm = 0x00000002, + regk_bif_dma_off = 0x00000000, + regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch0_start_default = 0x00000000, + regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch1_start_default = 0x00000000, + regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch2_start_default = 0x00000000, + regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch3_start_default = 0x00000000, + regk_bif_dma_rw_intr_mask_default = 0x00000000, + regk_bif_dma_rw_pin0_cfg_default = 0x00000000, + regk_bif_dma_rw_pin1_cfg_default = 0x00000000, + regk_bif_dma_rw_pin2_cfg_default = 0x00000000, + regk_bif_dma_rw_pin3_cfg_default = 0x00000000, + regk_bif_dma_rw_pin4_cfg_default = 0x00000000, + regk_bif_dma_rw_pin5_cfg_default = 0x00000000, + regk_bif_dma_rw_pin6_cfg_default = 0x00000000, + regk_bif_dma_rw_pin7_cfg_default = 0x00000000, + regk_bif_dma_slave = 0x00000002, + regk_bif_dma_sreq = 0x00000006, + regk_bif_dma_sreq_inv = 0x00000007, + regk_bif_dma_tc = 0x00000004, + regk_bif_dma_tc_inv = 0x00000005, + regk_bif_dma_yes = 0x00000001 +}; +#endif /* __bif_dma_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h new file mode 100644 index 000000000000..0c434585a3f9 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_h +#define __bif_slave_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_slave */ + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int slave_id : 3; + unsigned int use_slave_id : 1; + unsigned int boot_rdy : 1; + unsigned int loopback : 1; + unsigned int dis : 1; + unsigned int dummy1 : 25; +} reg_bif_slave_rw_slave_cfg; +#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 +#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +typedef struct { + unsigned int ch0_mode : 1; + unsigned int ch1_mode : 1; + unsigned int ch2_mode : 1; + unsigned int ch3_mode : 1; + unsigned int dummy1 : 28; +} reg_bif_slave_r_slave_mode; +#define REG_RD_ADDR_bif_slave_r_slave_mode 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch0_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 +#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch1_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 +#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch2_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 +#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch3_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 +#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int brin_mode : 1; + unsigned int brout_mode : 3; + unsigned int bg_mode : 3; + unsigned int release : 2; + unsigned int acquire : 1; + unsigned int settle_time : 2; + unsigned int dram_ctrl : 1; + unsigned int dummy1 : 19; +} reg_bif_slave_rw_arb_cfg; +#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 +#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +typedef struct { + unsigned int init_mode : 1; + unsigned int mode : 1; + unsigned int brin : 1; + unsigned int brout : 1; + unsigned int bg : 1; + unsigned int dummy1 : 27; +} reg_bif_slave_r_arb_stat; +#define REG_RD_ADDR_bif_slave_r_arb_stat 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_intr_mask; +#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 +#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_ack_intr; +#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 +#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 + +/* Register r_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_intr; +#define REG_RD_ADDR_bif_slave_r_intr 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_masked_intr; +#define REG_RD_ADDR_bif_slave_r_masked_intr 76 + + +/* Constants */ +enum { + regk_bif_slave_active_hi = 0x00000003, + regk_bif_slave_active_lo = 0x00000002, + regk_bif_slave_addr = 0x00000000, + regk_bif_slave_always = 0x00000001, + regk_bif_slave_at_idle = 0x00000002, + regk_bif_slave_burst_end = 0x00000003, + regk_bif_slave_dma = 0x00000001, + regk_bif_slave_hi = 0x00000003, + regk_bif_slave_inv = 0x00000001, + regk_bif_slave_lo = 0x00000002, + regk_bif_slave_local = 0x00000001, + regk_bif_slave_master = 0x00000000, + regk_bif_slave_mode_reg = 0x00000001, + regk_bif_slave_no = 0x00000000, + regk_bif_slave_norm = 0x00000000, + regk_bif_slave_on_access = 0x00000000, + regk_bif_slave_rw_arb_cfg_default = 0x00000000, + regk_bif_slave_rw_ch0_cfg_default = 0x00000000, + regk_bif_slave_rw_ch1_cfg_default = 0x00000000, + regk_bif_slave_rw_ch2_cfg_default = 0x00000000, + regk_bif_slave_rw_ch3_cfg_default = 0x00000000, + regk_bif_slave_rw_intr_mask_default = 0x00000000, + regk_bif_slave_rw_slave_cfg_default = 0x00000000, + regk_bif_slave_shared = 0x00000000, + regk_bif_slave_slave = 0x00000001, + regk_bif_slave_t0ns = 0x00000003, + regk_bif_slave_t10ns = 0x00000002, + regk_bif_slave_t20ns = 0x00000003, + regk_bif_slave_t30ns = 0x00000002, + regk_bif_slave_t40ns = 0x00000001, + regk_bif_slave_t50ns = 0x00000000, + regk_bif_slave_yes = 0x00000001, + regk_bif_slave_z = 0x00000004 +}; +#endif /* __bif_slave_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h new file mode 100644 index 000000000000..abc5f20705f7 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h @@ -0,0 +1,142 @@ +#ifndef __config_defs_h +#define __config_defs_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r + * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope config */ + +/* Register r_bootsel, scope config, type r */ +typedef struct { + unsigned int boot_mode : 3; + unsigned int full_duplex : 1; + unsigned int user : 1; + unsigned int pll : 1; + unsigned int flash_bw : 1; + unsigned int dummy1 : 25; +} reg_config_r_bootsel; +#define REG_RD_ADDR_config_r_bootsel 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop : 1; + unsigned int dma01_eth0 : 1; + unsigned int dma23 : 1; + unsigned int dma45 : 1; + unsigned int dma67 : 1; + unsigned int dma89_strcop : 1; + unsigned int bif : 1; + unsigned int fix_io : 1; + unsigned int dummy1 : 22; +} reg_config_rw_clk_ctrl; +#define REG_RD_ADDR_config_rw_clk_ctrl 4 +#define REG_WR_ADDR_config_rw_clk_ctrl 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +typedef struct { + unsigned int usb_susp : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 30; +} reg_config_rw_pad_ctrl; +#define REG_RD_ADDR_config_rw_pad_ctrl 8 +#define REG_WR_ADDR_config_rw_pad_ctrl 8 + + +/* Constants */ +enum { + regk_config_bw16 = 0x00000000, + regk_config_bw32 = 0x00000001, + regk_config_master = 0x00000005, + regk_config_nand = 0x00000003, + regk_config_net_rx = 0x00000001, + regk_config_net_tx_rx = 0x00000002, + regk_config_no = 0x00000000, + regk_config_none = 0x00000007, + regk_config_nor = 0x00000000, + regk_config_rw_clk_ctrl_default = 0x00000002, + regk_config_rw_pad_ctrl_default = 0x00000000, + regk_config_ser = 0x00000004, + regk_config_slave = 0x00000006, + regk_config_yes = 0x00000001 +}; +#endif /* __config_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h new file mode 100644 index 000000000000..26aa3efcf91b --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h @@ -0,0 +1,295 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 0 +#define REG_WR_ADDR_gio_rw_pa_dout 0 + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 3; + unsigned int pa1 : 3; + unsigned int pa2 : 3; + unsigned int pa3 : 3; + unsigned int pa4 : 3; + unsigned int pa5 : 3; + unsigned int pa6 : 3; + unsigned int pa7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 12 +#define REG_WR_ADDR_gio_rw_intr_cfg 12 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 16 +#define REG_WR_ADDR_gio_rw_intr_mask 16 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 20 +#define REG_WR_ADDR_gio_rw_ack_intr 20 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 24 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 28 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 32 +#define REG_WR_ADDR_gio_rw_pb_dout 32 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 36 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 40 +#define REG_WR_ADDR_gio_rw_pb_oe 40 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 48 +#define REG_WR_ADDR_gio_rw_pc_dout 48 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 52 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 56 +#define REG_WR_ADDR_gio_rw_pc_oe 56 + +/* Register rw_pd_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_dout; +#define REG_RD_ADDR_gio_rw_pd_dout 64 +#define REG_WR_ADDR_gio_rw_pd_dout 64 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 68 + +/* Register rw_pd_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_oe; +#define REG_RD_ADDR_gio_rw_pd_oe 72 +#define REG_WR_ADDR_gio_rw_pd_oe 72 + +/* Register rw_pe_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_dout; +#define REG_RD_ADDR_gio_rw_pe_dout 80 +#define REG_WR_ADDR_gio_rw_pe_dout 80 + +/* Register r_pe_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pe_din; +#define REG_RD_ADDR_gio_r_pe_din 84 + +/* Register rw_pe_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_oe; +#define REG_RD_ADDR_gio_rw_pe_oe 88 +#define REG_WR_ADDR_gio_rw_pe_oe 88 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_hi = 0x00000001, + regk_gio_lo = 0x00000002, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_off = 0x00000000, + regk_gio_posedge = 0x00000005, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_pd_oe_default = 0x00000000, + regk_gio_rw_pe_oe_default = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h new file mode 100644 index 000000000000..bacc2a895c21 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define GIO_INTR_VECT GEN_IO_INTR_VECT +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define TIMER0_INTR_VECT TIMER_INTR_VECT +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e +#define IPI_INTR_VECT 0x4f +#define NBR_INTR_VECT 0x50 +#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h new file mode 100644 index 000000000000..aa65128ae1aa --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h @@ -0,0 +1,228 @@ +#ifndef __intr_vect_defs_h +#define __intr_vect_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * last modfied: Mon Apr 11 16:08:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope intr_vect */ + +#define STRIDE_intr_vect_rw_mask 0 +/* Register rw_mask, scope intr_vect, type rw */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer0 : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_rw_mask; +#define REG_RD_ADDR_intr_vect_rw_mask 0 +#define REG_WR_ADDR_intr_vect_rw_mask 0 + +#define STRIDE_intr_vect_r_vect 0 +/* Register r_vect, scope intr_vect, type r */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_r_vect; +#define REG_RD_ADDR_intr_vect_r_vect 4 + +#define STRIDE_intr_vect_r_masked_vect 0 +/* Register r_masked_vect, scope intr_vect, type r */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_r_masked_vect; +#define REG_RD_ADDR_intr_vect_r_masked_vect 8 + +/* Register r_nmi, scope intr_vect, type r */ +typedef struct { + unsigned int ext : 1; + unsigned int watchdog : 1; + unsigned int dummy1 : 30; +} reg_intr_vect_r_nmi; +#define REG_RD_ADDR_intr_vect_r_nmi 12 + +/* Register r_guru, scope intr_vect, type r */ +typedef struct { + unsigned int jtag : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_r_guru; +#define REG_RD_ADDR_intr_vect_r_guru 16 + +/* Register rw_ipi, scope intr_vect, type rw */ +typedef struct +{ + unsigned int vector; +} reg_intr_vect_rw_ipi; +#define REG_RD_ADDR_intr_vect_rw_ipi 20 +#define REG_WR_ADDR_intr_vect_rw_ipi 20 + +/* Constants */ +enum { + regk_intr_vect_off = 0x00000000, + regk_intr_vect_on = 0x00000001, + regk_intr_vect_rw_mask_default = 0x00000000 +}; +#endif /* __intr_vect_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h new file mode 100644 index 000000000000..dcaaec4620ba --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h @@ -0,0 +1,205 @@ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Fri Nov 7 15:36:04 2003 + * + * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_break_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_addr; +#define REG_RD_ADDR_marb_bp_r_break_addr 20 + +/* Register r_break_op, scope marb_bp, type r */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_break_op; +#define REG_RD_ADDR_marb_bp_r_break_op 24 + +/* Register r_break_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_clients; +#define REG_RD_ADDR_marb_bp_r_break_clients 28 + +/* Register r_break_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_first_client; +#define REG_RD_ADDR_marb_bp_r_break_first_client 32 + +/* Register r_break_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_size; +#define REG_RD_ADDR_marb_bp_r_break_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h new file mode 100644 index 000000000000..254da0854986 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h @@ -0,0 +1,475 @@ +#ifndef __marb_defs_h +#define __marb_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb */ + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_int_slots; +#define REG_RD_ADDR_marb_rw_int_slots 0 +#define REG_WR_ADDR_marb_rw_int_slots 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_ext_slots; +#define REG_RD_ADDR_marb_rw_ext_slots 256 +#define REG_WR_ADDR_marb_rw_ext_slots 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_regs_slots; +#define REG_RD_ADDR_marb_rw_regs_slots 512 +#define REG_WR_ADDR_marb_rw_regs_slots 512 + +/* Register rw_intr_mask, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_intr_mask; +#define REG_RD_ADDR_marb_rw_intr_mask 528 +#define REG_WR_ADDR_marb_rw_intr_mask 528 + +/* Register rw_ack_intr, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_ack_intr; +#define REG_RD_ADDR_marb_rw_ack_intr 532 +#define REG_WR_ADDR_marb_rw_ack_intr 532 + +/* Register r_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_intr; +#define REG_RD_ADDR_marb_r_intr 536 + +/* Register r_masked_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_masked_intr; +#define REG_RD_ADDR_marb_r_masked_intr 540 + +/* Register rw_stop_mask, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_stop_mask; +#define REG_RD_ADDR_marb_rw_stop_mask 544 +#define REG_WR_ADDR_marb_rw_stop_mask 544 + +/* Register r_stopped, scope marb, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_r_stopped; +#define REG_RD_ADDR_marb_r_stopped 548 + +/* Register rw_no_snoop, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_no_snoop; +#define REG_RD_ADDR_marb_rw_no_snoop 832 +#define REG_WR_ADDR_marb_rw_no_snoop 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +typedef struct { + unsigned int dummy1 : 10; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 20; +} reg_marb_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 +#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 + + +/* Constants */ +enum { + regk_marb_cpud = 0x0000000b, + regk_marb_cpui = 0x0000000a, + regk_marb_dma0 = 0x00000000, + regk_marb_dma1 = 0x00000001, + regk_marb_dma2 = 0x00000002, + regk_marb_dma3 = 0x00000003, + regk_marb_dma4 = 0x00000004, + regk_marb_dma5 = 0x00000005, + regk_marb_dma6 = 0x00000006, + regk_marb_dma7 = 0x00000007, + regk_marb_dma8 = 0x00000008, + regk_marb_dma9 = 0x00000009, + regk_marb_iop = 0x0000000c, + regk_marb_no = 0x00000000, + regk_marb_r_stopped_default = 0x00000000, + regk_marb_rw_ext_slots_default = 0x00000000, + regk_marb_rw_ext_slots_size = 0x00000040, + regk_marb_rw_int_slots_default = 0x00000000, + regk_marb_rw_int_slots_size = 0x00000040, + regk_marb_rw_intr_mask_default = 0x00000000, + regk_marb_rw_no_snoop_default = 0x00000000, + regk_marb_rw_no_snoop_rq_default = 0x00000000, + regk_marb_rw_regs_slots_default = 0x00000000, + regk_marb_rw_regs_slots_size = 0x00000004, + regk_marb_rw_stop_mask_default = 0x00000000, + regk_marb_slave = 0x0000000d, + regk_marb_yes = 0x00000001 +}; +#endif /* __marb_defs_h */ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_brk_op; +#define REG_RD_ADDR_marb_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_size; +#define REG_RD_ADDR_marb_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h new file mode 100644 index 000000000000..751eab5f191c --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h @@ -0,0 +1,357 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int csp2_n : 1; + unsigned int csp3_n : 1; + unsigned int csp5_n : 1; + unsigned int csp6_n : 1; + unsigned int hsh4 : 1; + unsigned int hsh5 : 1; + unsigned int hsh6 : 1; + unsigned int hsh7 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_pa; +#define REG_RD_ADDR_pinmux_rw_pa 0 +#define REG_WR_ADDR_pinmux_rw_pa 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ata0 : 1; + unsigned int ata1 : 1; + unsigned int ata2 : 1; + unsigned int ata3 : 1; + unsigned int ata : 1; + unsigned int eth1 : 1; + unsigned int eth1_mgm : 1; + unsigned int timer : 1; + unsigned int p21 : 1; + unsigned int dummy1 : 18; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 4 +#define REG_WR_ADDR_pinmux_rw_hwprot 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_gio; +#define REG_RD_ADDR_pinmux_rw_pb_gio 8 +#define REG_WR_ADDR_pinmux_rw_pb_gio 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_iop; +#define REG_RD_ADDR_pinmux_rw_pb_iop 12 +#define REG_WR_ADDR_pinmux_rw_pb_iop 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_gio; +#define REG_RD_ADDR_pinmux_rw_pc_gio 16 +#define REG_WR_ADDR_pinmux_rw_pc_gio 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_iop; +#define REG_RD_ADDR_pinmux_rw_pc_iop 20 +#define REG_WR_ADDR_pinmux_rw_pc_iop 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_gio; +#define REG_RD_ADDR_pinmux_rw_pd_gio 24 +#define REG_WR_ADDR_pinmux_rw_pd_gio 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_iop; +#define REG_RD_ADDR_pinmux_rw_pd_iop 28 +#define REG_WR_ADDR_pinmux_rw_pd_iop 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_gio; +#define REG_RD_ADDR_pinmux_rw_pe_gio 32 +#define REG_WR_ADDR_pinmux_rw_pe_gio 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_iop; +#define REG_RD_ADDR_pinmux_rw_pe_iop 36 +#define REG_WR_ADDR_pinmux_rw_pe_iop 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +typedef struct { + unsigned int en_usb0 : 1; + unsigned int en_usb1 : 1; + unsigned int dummy1 : 30; +} reg_pinmux_rw_usb_phy; +#define REG_RD_ADDR_pinmux_rw_usb_phy 40 +#define REG_WR_ADDR_pinmux_rw_usb_phy 40 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_pa_default = 0x00000000, + regk_pinmux_rw_pb_gio_default = 0x00000000, + regk_pinmux_rw_pb_iop_default = 0x00000000, + regk_pinmux_rw_pc_gio_default = 0x00000000, + regk_pinmux_rw_pc_iop_default = 0x00000000, + regk_pinmux_rw_pd_gio_default = 0x00000000, + regk_pinmux_rw_pd_iop_default = 0x00000000, + regk_pinmux_rw_pe_gio_default = 0x00000000, + regk_pinmux_rw_pe_iop_default = 0x00000000, + regk_pinmux_rw_usb_phy_default = 0x00000000, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h new file mode 100644 index 000000000000..4146973a58b3 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h @@ -0,0 +1,104 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +typedef enum { + regi_ata = 0xb0032000, + regi_bif_core = 0xb0014000, + regi_bif_dma = 0xb0016000, + regi_bif_slave = 0xb0018000, + regi_config = 0xb003c000, + regi_dma0 = 0xb0000000, + regi_dma1 = 0xb0002000, + regi_dma2 = 0xb0004000, + regi_dma3 = 0xb0006000, + regi_dma4 = 0xb0008000, + regi_dma5 = 0xb000a000, + regi_dma6 = 0xb000c000, + regi_dma7 = 0xb000e000, + regi_dma8 = 0xb0010000, + regi_dma9 = 0xb0012000, + regi_eth0 = 0xb0034000, + regi_eth1 = 0xb0036000, + regi_gio = 0xb001a000, + regi_iop = 0xb0020000, + regi_iop_version = 0xb0020000, + regi_iop_fifo_in0_extra = 0xb0020040, + regi_iop_fifo_in1_extra = 0xb0020080, + regi_iop_fifo_out0_extra = 0xb00200c0, + regi_iop_fifo_out1_extra = 0xb0020100, + regi_iop_trigger_grp0 = 0xb0020140, + regi_iop_trigger_grp1 = 0xb0020180, + regi_iop_trigger_grp2 = 0xb00201c0, + regi_iop_trigger_grp3 = 0xb0020200, + regi_iop_trigger_grp4 = 0xb0020240, + regi_iop_trigger_grp5 = 0xb0020280, + regi_iop_trigger_grp6 = 0xb00202c0, + regi_iop_trigger_grp7 = 0xb0020300, + regi_iop_crc_par0 = 0xb0020380, + regi_iop_crc_par1 = 0xb0020400, + regi_iop_dmc_in0 = 0xb0020480, + regi_iop_dmc_in1 = 0xb0020500, + regi_iop_dmc_out0 = 0xb0020580, + regi_iop_dmc_out1 = 0xb0020600, + regi_iop_fifo_in0 = 0xb0020680, + regi_iop_fifo_in1 = 0xb0020700, + regi_iop_fifo_out0 = 0xb0020780, + regi_iop_fifo_out1 = 0xb0020800, + regi_iop_scrc_in0 = 0xb0020880, + regi_iop_scrc_in1 = 0xb0020900, + regi_iop_scrc_out0 = 0xb0020980, + regi_iop_scrc_out1 = 0xb0020a00, + regi_iop_timer_grp0 = 0xb0020a80, + regi_iop_timer_grp1 = 0xb0020b00, + regi_iop_timer_grp2 = 0xb0020b80, + regi_iop_timer_grp3 = 0xb0020c00, + regi_iop_sap_in = 0xb0020d00, + regi_iop_sap_out = 0xb0020e00, + regi_iop_spu0 = 0xb0020f00, + regi_iop_spu1 = 0xb0021000, + regi_iop_sw_cfg = 0xb0021100, + regi_iop_sw_cpu = 0xb0021200, + regi_iop_sw_mpu = 0xb0021300, + regi_iop_sw_spu0 = 0xb0021400, + regi_iop_sw_spu1 = 0xb0021500, + regi_iop_mpu = 0xb0021600, + regi_irq = 0xb001c000, + regi_irq2 = 0xb005c000, + regi_marb = 0xb003e000, + regi_marb_bp0 = 0xb003e240, + regi_marb_bp1 = 0xb003e280, + regi_marb_bp2 = 0xb003e2c0, + regi_marb_bp3 = 0xb003e300, + regi_pinmux = 0xb0038000, + regi_ser0 = 0xb0026000, + regi_ser1 = 0xb0028000, + regi_ser2 = 0xb002a000, + regi_ser3 = 0xb002c000, + regi_sser0 = 0xb0022000, + regi_sser1 = 0xb0024000, + regi_strcop = 0xb0030000, + regi_strmux = 0xb003a000, + regi_timer = 0xb001e000, + regi_timer0 = 0xb001e000, + regi_timer2 = 0xb005e000, + regi_trace = 0xb0040000, +} reg_scope_instances; +#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h new file mode 100644 index 000000000000..cbfaa867829e --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h @@ -0,0 +1,127 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 3; + unsigned int dma1 : 3; + unsigned int dma2 : 3; + unsigned int dma3 : 3; + unsigned int dma4 : 3; + unsigned int dma5 : 3; + unsigned int dma6 : 3; + unsigned int dma7 : 3; + unsigned int dma8 : 3; + unsigned int dma9 : 3; + unsigned int dummy1 : 2; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_ata = 0x00000003, + regk_strmux_eth0 = 0x00000001, + regk_strmux_eth1 = 0x00000004, + regk_strmux_ext0 = 0x00000001, + regk_strmux_ext1 = 0x00000001, + regk_strmux_ext2 = 0x00000001, + regk_strmux_ext3 = 0x00000001, + regk_strmux_iop0 = 0x00000002, + regk_strmux_iop1 = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_p21 = 0x00000004, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000004, + regk_strmux_ser3 = 0x00000003, + regk_strmux_sser0 = 0x00000003, + regk_strmux_sser1 = 0x00000003, + regk_strmux_strcop = 0x00000002 +}; +#endif /* __strmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h new file mode 100644 index 000000000000..76bcc591921d --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h @@ -0,0 +1,266 @@ +#ifndef __timer_defs_h +#define __timer_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope timer */ + +/* Register rw_tmr0_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr0_div; +#define REG_RD_ADDR_timer_rw_tmr0_div 0 +#define REG_WR_ADDR_timer_rw_tmr0_div 0 + +/* Register r_tmr0_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr0_data; +#define REG_RD_ADDR_timer_r_tmr0_data 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr0_ctrl; +#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 +#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr1_div; +#define REG_RD_ADDR_timer_rw_tmr1_div 16 +#define REG_WR_ADDR_timer_rw_tmr1_div 16 + +/* Register r_tmr1_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr1_data; +#define REG_RD_ADDR_timer_r_tmr1_data 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr1_ctrl; +#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 +#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 + +/* Register rs_cnt_data, scope timer, type rs */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_rs_cnt_data; +#define REG_RD_ADDR_timer_rs_cnt_data 32 + +/* Register r_cnt_data, scope timer, type r */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_r_cnt_data; +#define REG_RD_ADDR_timer_r_cnt_data 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +typedef struct { + unsigned int clk : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_cnt_cfg; +#define REG_RD_ADDR_timer_rw_cnt_cfg 40 +#define REG_WR_ADDR_timer_rw_cnt_cfg 40 + +/* Register rw_trig, scope timer, type rw */ +typedef unsigned int reg_timer_rw_trig; +#define REG_RD_ADDR_timer_rw_trig 48 +#define REG_WR_ADDR_timer_rw_trig 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_trig_cfg; +#define REG_RD_ADDR_timer_rw_trig_cfg 52 +#define REG_WR_ADDR_timer_rw_trig_cfg 52 + +/* Register r_time, scope timer, type r */ +typedef unsigned int reg_timer_r_time; +#define REG_RD_ADDR_timer_r_time 56 + +/* Register rw_out, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_out; +#define REG_RD_ADDR_timer_rw_out 60 +#define REG_WR_ADDR_timer_rw_out 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int key : 7; + unsigned int dummy1 : 16; +} reg_timer_rw_wd_ctrl; +#define REG_RD_ADDR_timer_rw_wd_ctrl 64 +#define REG_WR_ADDR_timer_rw_wd_ctrl 64 + +/* Register r_wd_stat, scope timer, type r */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int dummy1 : 23; +} reg_timer_r_wd_stat; +#define REG_RD_ADDR_timer_r_wd_stat 68 + +/* Register rw_intr_mask, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_intr_mask; +#define REG_RD_ADDR_timer_rw_intr_mask 72 +#define REG_WR_ADDR_timer_rw_intr_mask 72 + +/* Register rw_ack_intr, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_ack_intr; +#define REG_RD_ADDR_timer_rw_ack_intr 76 +#define REG_WR_ADDR_timer_rw_ack_intr 76 + +/* Register r_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_intr; +#define REG_RD_ADDR_timer_r_intr 80 + +/* Register r_masked_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_masked_intr; +#define REG_RD_ADDR_timer_r_masked_intr 84 + +/* Register rw_test, scope timer, type rw */ +typedef struct { + unsigned int dis : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_timer_rw_test; +#define REG_RD_ADDR_timer_rw_test 88 +#define REG_WR_ADDR_timer_rw_test 88 + + +/* Constants */ +enum { + regk_timer_ext = 0x00000001, + regk_timer_f100 = 0x00000007, + regk_timer_f29_493 = 0x00000004, + regk_timer_f32 = 0x00000005, + regk_timer_f32_768 = 0x00000006, + regk_timer_hold = 0x00000001, + regk_timer_ld = 0x00000000, + regk_timer_no = 0x00000000, + regk_timer_off = 0x00000000, + regk_timer_run = 0x00000002, + regk_timer_rw_cnt_cfg_default = 0x00000000, + regk_timer_rw_intr_mask_default = 0x00000000, + regk_timer_rw_out_default = 0x00000000, + regk_timer_rw_test_default = 0x00000000, + regk_timer_rw_tmr0_ctrl_default = 0x00000000, + regk_timer_rw_tmr1_ctrl_default = 0x00000000, + regk_timer_rw_trig_cfg_default = 0x00000000, + regk_timer_start = 0x00000001, + regk_timer_stop = 0x00000000, + regk_timer_time = 0x00000001, + regk_timer_tmr0 = 0x00000002, + regk_timer_tmr1 = 0x00000003, + regk_timer_yes = 0x00000001 +}; +#endif /* __timer_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h b/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h new file mode 100644 index 000000000000..c2b3036779df --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h @@ -0,0 +1,38 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_B 0 +#define PORT_C 1 +#define PORT_D 2 +#define PORT_E 3 + +enum pin_mode { + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function { + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_sser0, + pinmux_sser1, + pinmux_ata0, + pinmux_ata1, + pinmux_ata2, + pinmux_ata3, + pinmux_ata, + pinmux_eth1, + pinmux_timer +}; + +int crisv32_pinmux_init(void); +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); +void crisv32_pinmux_dump(void); + +#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc new file mode 100644 index 000000000000..4a10ccbd6cc1 --- /dev/null +++ b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc @@ -0,0 +1,77 @@ +#include +#include +#include +#include + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 + move.d $r0, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(config, rw_clk_ctrl, bif, yes) | \ + REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + ;; Set up waitstates etc + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 + move.d $r1, [$r0] +#ifdef CONFIG_ETRAX_VCS_SIM + ;; Set up minimal flash waitstates + move.d 0, $r10 + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 + move.d $r10, [$r11] +#endif + .endm diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild new file mode 100644 index 000000000000..d5b631935ec8 --- /dev/null +++ b/arch/cris/include/asm/Kbuild @@ -0,0 +1,11 @@ +include include/asm-generic/Kbuild.asm + +header-y += arch-v10/ +header-y += arch-v32/ + +header-y += ethernet.h +header-y += rtc.h +header-y += sync_serial.h + +unifdef-y += etraxgpio.h +unifdef-y += rs485.h diff --git a/arch/cris/include/asm/atomic.h b/arch/cris/include/asm/atomic.h new file mode 100644 index 000000000000..f71ea686a2ea --- /dev/null +++ b/arch/cris/include/asm/atomic.h @@ -0,0 +1,164 @@ +/* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */ + +#ifndef __ASM_CRIS_ATOMIC__ +#define __ASM_CRIS_ATOMIC__ + +#include + +#include +#include + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) (((v)->counter) = (i)) + +/* These should be written in asm but we do it in C for now. */ + +static inline void atomic_add(int i, volatile atomic_t *v) +{ + unsigned long flags; + cris_atomic_save(v, flags); + v->counter += i; + cris_atomic_restore(v, flags); +} + +static inline void atomic_sub(int i, volatile atomic_t *v) +{ + unsigned long flags; + cris_atomic_save(v, flags); + v->counter -= i; + cris_atomic_restore(v, flags); +} + +static inline int atomic_add_return(int i, volatile atomic_t *v) +{ + unsigned long flags; + int retval; + cris_atomic_save(v, flags); + retval = (v->counter += i); + cris_atomic_restore(v, flags); + return retval; +} + +#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) + +static inline int atomic_sub_return(int i, volatile atomic_t *v) +{ + unsigned long flags; + int retval; + cris_atomic_save(v, flags); + retval = (v->counter -= i); + cris_atomic_restore(v, flags); + return retval; +} + +static inline int atomic_sub_and_test(int i, volatile atomic_t *v) +{ + int retval; + unsigned long flags; + cris_atomic_save(v, flags); + retval = (v->counter -= i) == 0; + cris_atomic_restore(v, flags); + return retval; +} + +static inline void atomic_inc(volatile atomic_t *v) +{ + unsigned long flags; + cris_atomic_save(v, flags); + (v->counter)++; + cris_atomic_restore(v, flags); +} + +static inline void atomic_dec(volatile atomic_t *v) +{ + unsigned long flags; + cris_atomic_save(v, flags); + (v->counter)--; + cris_atomic_restore(v, flags); +} + +static inline int atomic_inc_return(volatile atomic_t *v) +{ + unsigned long flags; + int retval; + cris_atomic_save(v, flags); + retval = ++(v->counter); + cris_atomic_restore(v, flags); + return retval; +} + +static inline int atomic_dec_return(volatile atomic_t *v) +{ + unsigned long flags; + int retval; + cris_atomic_save(v, flags); + retval = --(v->counter); + cris_atomic_restore(v, flags); + return retval; +} +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + int retval; + unsigned long flags; + cris_atomic_save(v, flags); + retval = --(v->counter) == 0; + cris_atomic_restore(v, flags); + return retval; +} + +static inline int atomic_inc_and_test(volatile atomic_t *v) +{ + int retval; + unsigned long flags; + cris_atomic_save(v, flags); + retval = ++(v->counter) == 0; + cris_atomic_restore(v, flags); + return retval; +} + +static inline int atomic_cmpxchg(atomic_t *v, int old, int new) +{ + int ret; + unsigned long flags; + + cris_atomic_save(v, flags); + ret = v->counter; + if (likely(ret == old)) + v->counter = new; + cris_atomic_restore(v, flags); + return ret; +} + +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int ret; + unsigned long flags; + + cris_atomic_save(v, flags); + ret = v->counter; + if (ret != u) + v->counter += a; + cris_atomic_restore(v, flags); + return ret != u; +} +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +/* Atomic operations are already serializing */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#include +#endif diff --git a/arch/cris/include/asm/auxvec.h b/arch/cris/include/asm/auxvec.h new file mode 100644 index 000000000000..cb30b01bf19f --- /dev/null +++ b/arch/cris/include/asm/auxvec.h @@ -0,0 +1,4 @@ +#ifndef __ASMCRIS_AUXVEC_H +#define __ASMCRIS_AUXVEC_H + +#endif diff --git a/arch/cris/include/asm/axisflashmap.h b/arch/cris/include/asm/axisflashmap.h new file mode 100644 index 000000000000..015ca5445ddd --- /dev/null +++ b/arch/cris/include/asm/axisflashmap.h @@ -0,0 +1,61 @@ +#ifndef __ASM_AXISFLASHMAP_H +#define __ASM_AXISFLASHMAP_H + +/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC + * as start, it ends with 0xFFFFFFFF */ +#define FLASH_BOOT_MAGIC 0xbeefcace +#define BOOTPARAM_OFFSET 0xc000 +/* apps/bootblocktool is used to read and write the parameters, + * and it has nothing to do with the partition table. + */ + +#define PARTITION_TABLE_OFFSET 10 +#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ + +/* The partitiontable_head is located at offset +10: */ +struct partitiontable_head { + __u16 magic; /* PARTITION_TABLE_MAGIC */ + __u16 size; /* Length of ptable block (entries + end marker) */ + __u32 checksum; /* simple longword sum, over entries + end marker */ +}; + +/* And followed by partition table entries */ +struct partitiontable_entry { + __u32 offset; /* relative to the sector the ptable is in */ + __u32 size; /* in bytes */ + __u32 checksum; /* simple longword sum */ + __u16 type; /* see type codes below */ + __u16 flags; /* bit 0: ro/rw = 1/0 */ + __u32 future0; /* 16 bytes reserved for future use */ + __u32 future1; + __u32 future2; + __u32 future3; +}; +/* ended by an end marker: */ +#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF +#define PARTITIONTABLE_END_MARKER_SIZE 4 + +#define PARTITIONTABLE_END_PAD 10 + +/* Complete structure for whole partition table */ +/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting + * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. + */ +struct partitiontable { + __u8 skip[PARTITION_TABLE_OFFSET]; + struct partitiontable_head head; + struct partitiontable_entry entries[]; +}; + +#define PARTITION_TYPE_PARAM 0x0001 +#define PARTITION_TYPE_KERNEL 0x0002 +#define PARTITION_TYPE_JFFS 0x0003 +#define PARTITION_TYPE_JFFS2 0x0000 + +#define PARTITION_FLAGS_READONLY_MASK 0x0001 +#define PARTITION_FLAGS_READONLY 0x0001 + +/* The master mtd for the entire flash. */ +extern struct mtd_info *axisflash_mtd; + +#endif diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h new file mode 100644 index 000000000000..c0e62f811e09 --- /dev/null +++ b/arch/cris/include/asm/bitops.h @@ -0,0 +1,166 @@ +/* asm/bitops.h for Linux/CRIS + * + * TODO: asm versions if speed is needed + * + * All bit operations return 0 if the bit was cleared before the + * operation and != 0 if it was not. + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + */ + +#ifndef _CRIS_BITOPS_H +#define _CRIS_BITOPS_H + +/* Currently this is unsuitable for consumption outside the kernel. */ +#ifdef __KERNEL__ + +#ifndef _LINUX_BITOPS_H +#error only can be included directly +#endif + +#include +#include +#include +#include + +/* + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ + +#define set_bit(nr, addr) (void)test_and_set_bit(nr, addr) + +/* + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ + +#define clear_bit(nr, addr) (void)test_and_clear_bit(nr, addr) + +/* + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ + +#define change_bit(nr, addr) (void)test_and_change_bit(nr, addr) + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ + +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned int mask, retval; + unsigned long flags; + unsigned int *adr = (unsigned int *)addr; + + adr += nr >> 5; + mask = 1 << (nr & 0x1f); + cris_atomic_save(addr, flags); + retval = (mask & *adr) != 0; + *adr |= mask; + cris_atomic_restore(addr, flags); + return retval; +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ + +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned int mask, retval; + unsigned long flags; + unsigned int *adr = (unsigned int *)addr; + + adr += nr >> 5; + mask = 1 << (nr & 0x1f); + cris_atomic_save(addr, flags); + retval = (mask & *adr) != 0; + *adr &= ~mask; + cris_atomic_restore(addr, flags); + return retval; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ + +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned int mask, retval; + unsigned long flags; + unsigned int *adr = (unsigned int *)addr; + adr += nr >> 5; + mask = 1 << (nr & 0x1f); + cris_atomic_save(addr, flags); + retval = (mask & *adr) != 0; + *adr ^= mask; + cris_atomic_restore(addr, flags); + return retval; +} + +#include + +/* + * Since we define it "external", it collides with the built-in + * definition, which doesn't have the same semantics. We don't want to + * use -fno-builtin, so just hide the name ffs. + */ +#define ffs kernel_ffs + +#include +#include +#include +#include +#include + +#include + +#define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) +#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) + +#include +#include + +#endif /* __KERNEL__ */ + +#endif /* _CRIS_BITOPS_H */ diff --git a/arch/cris/include/asm/bug.h b/arch/cris/include/asm/bug.h new file mode 100644 index 000000000000..3b3958963801 --- /dev/null +++ b/arch/cris/include/asm/bug.h @@ -0,0 +1,4 @@ +#ifndef _CRIS_BUG_H +#define _CRIS_BUG_H +#include +#endif diff --git a/arch/cris/include/asm/bugs.h b/arch/cris/include/asm/bugs.h new file mode 100644 index 000000000000..c5907aac1007 --- /dev/null +++ b/arch/cris/include/asm/bugs.h @@ -0,0 +1,21 @@ +/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ + * + * include/asm-cris/bugs.h + * + * Copyright (C) 2001 Axis Communications AB + */ + +/* + * This is included by init/main.c to check for architecture-dependent bugs. + * + * Needs: + * void check_bugs(void); + */ + +static void check_bugs(void) +{ +} + + + + diff --git a/arch/cris/include/asm/byteorder.h b/arch/cris/include/asm/byteorder.h new file mode 100644 index 000000000000..cc8e418cfd14 --- /dev/null +++ b/arch/cris/include/asm/byteorder.h @@ -0,0 +1,27 @@ +#ifndef _CRIS_BYTEORDER_H +#define _CRIS_BYTEORDER_H + +#ifdef __GNUC__ + +#ifdef __KERNEL__ +#include + +/* defines are necessary because the other files detect the presence + * of a defined __arch_swab32, not an inline + */ +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) +#endif /* __KERNEL__ */ + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#include + +#endif + + diff --git a/arch/cris/include/asm/cache.h b/arch/cris/include/asm/cache.h new file mode 100644 index 000000000000..a692b9fba8b9 --- /dev/null +++ b/arch/cris/include/asm/cache.h @@ -0,0 +1,6 @@ +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +#include + +#endif /* _ASM_CACHE_H */ diff --git a/arch/cris/include/asm/cacheflush.h b/arch/cris/include/asm/cacheflush.h new file mode 100644 index 000000000000..cf60e3f69f8d --- /dev/null +++ b/arch/cris/include/asm/cacheflush.h @@ -0,0 +1,31 @@ +#ifndef _CRIS_CACHEFLUSH_H +#define _CRIS_CACHEFLUSH_H + +/* Keep includes the same across arches. */ +#include + +/* The cache doesn't need to be flushed when TLB entries change because + * the cache is mapped to physical memory, not virtual memory + */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define flush_cache_vmap(start, end) do { } while (0) +#define flush_cache_vunmap(start, end) do { } while (0) + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) + +int change_page_attr(struct page *page, int numpages, pgprot_t prot); + +#endif /* _CRIS_CACHEFLUSH_H */ diff --git a/arch/cris/include/asm/checksum.h b/arch/cris/include/asm/checksum.h new file mode 100644 index 000000000000..75dcb77d6cb0 --- /dev/null +++ b/arch/cris/include/asm/checksum.h @@ -0,0 +1,83 @@ +/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ + +#ifndef _CRIS_CHECKSUM_H +#define _CRIS_CHECKSUM_H + +#include + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +__wsum csum_partial_copy_nocheck(const void *src, void *dst, + int len, __wsum sum); + +/* + * Fold a partial checksum into a word + */ + +static inline __sum16 csum_fold(__wsum csum) +{ + u32 sum = (__force u32)csum; + sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ + sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ + return (__force __sum16)~sum; +} + +extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, + int *errptr); + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + * + */ + +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + return csum_fold(csum_partial(iph, ihl * 4, 0)); +} + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ + +static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, + unsigned short len, + unsigned short proto, + __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +static inline __sum16 ip_compute_csum(const void *buff, int len) +{ + return csum_fold (csum_partial(buff, len, 0)); +} + +#endif diff --git a/arch/cris/include/asm/cputime.h b/arch/cris/include/asm/cputime.h new file mode 100644 index 000000000000..4446a65656fa --- /dev/null +++ b/arch/cris/include/asm/cputime.h @@ -0,0 +1,6 @@ +#ifndef __CRIS_CPUTIME_H +#define __CRIS_CPUTIME_H + +#include + +#endif /* __CRIS_CPUTIME_H */ diff --git a/arch/cris/include/asm/current.h b/arch/cris/include/asm/current.h new file mode 100644 index 000000000000..5f5c0efd00be --- /dev/null +++ b/arch/cris/include/asm/current.h @@ -0,0 +1,15 @@ +#ifndef _CRIS_CURRENT_H +#define _CRIS_CURRENT_H + +#include + +struct task_struct; + +static inline struct task_struct * get_current(void) +{ + return current_thread_info()->task; +} + +#define current get_current() + +#endif /* !(_CRIS_CURRENT_H) */ diff --git a/arch/cris/include/asm/delay.h b/arch/cris/include/asm/delay.h new file mode 100644 index 000000000000..75ec581bfead --- /dev/null +++ b/arch/cris/include/asm/delay.h @@ -0,0 +1,27 @@ +#ifndef _CRIS_DELAY_H +#define _CRIS_DELAY_H + +/* + * Copyright (C) 1998-2002 Axis Communications AB + * + * Delay routines, using a pre-computed "loops_per_second" value. + */ + +#include + +/* Use only for very small delays ( < 1 msec). */ + +extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ + +/* May be defined by arch/delay.h. */ +#ifndef udelay +static inline void udelay(unsigned long usecs) +{ + __delay(usecs * loops_per_usec); +} +#endif + +#endif /* defined(_CRIS_DELAY_H) */ + + + diff --git a/arch/cris/include/asm/device.h b/arch/cris/include/asm/device.h new file mode 100644 index 000000000000..d8f9872b0e2d --- /dev/null +++ b/arch/cris/include/asm/device.h @@ -0,0 +1,7 @@ +/* + * Arch specific extensions to struct device + * + * This file is released under the GPLv2 + */ +#include + diff --git a/arch/cris/include/asm/div64.h b/arch/cris/include/asm/div64.h new file mode 100644 index 000000000000..6cd978cefb28 --- /dev/null +++ b/arch/cris/include/asm/div64.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/dma-mapping.h b/arch/cris/include/asm/dma-mapping.h new file mode 100644 index 000000000000..da8ef8e8f842 --- /dev/null +++ b/arch/cris/include/asm/dma-mapping.h @@ -0,0 +1,170 @@ +/* DMA mapping. Nothing tricky here, just virt_to_phys */ + +#ifndef _ASM_CRIS_DMA_MAPPING_H +#define _ASM_CRIS_DMA_MAPPING_H + +#include +#include + +#include +#include +#include + +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) + +#ifdef CONFIG_PCI +#include + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag); + +void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); +#else +static inline void * +dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t flag) +{ + BUG(); + return NULL; +} + +static inline void +dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle) +{ + BUG(); +} +#endif +static inline dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + return virt_to_phys(ptr); +} + +static inline void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + printk("Map sg\n"); + return nents; +} + +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, unsigned long offset, + size_t size, enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + return page_to_phys(page) + offset; +} + +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + + +static inline void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +static inline void +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ +} + +static inline int +dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return 0; +} + +static inline int +dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if(mask < 0x00ffffff) + return 0; + + return 1; +} + +static inline int +dma_set_mask(struct device *dev, u64 mask) +{ + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + + return 0; +} + +static inline int +dma_get_cache_alignment(void) +{ + return (1 << INTERNODE_CACHE_SHIFT); +} + +#define dma_is_consistent(d, h) (1) + +static inline void +dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) +{ +} + + +#endif diff --git a/arch/cris/include/asm/dma.h b/arch/cris/include/asm/dma.h new file mode 100644 index 000000000000..30fd715fa589 --- /dev/null +++ b/arch/cris/include/asm/dma.h @@ -0,0 +1,21 @@ +/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ + +#ifndef _ASM_DMA_H +#define _ASM_DMA_H + +#include + +/* it's useless on the Etrax, but unfortunately needed by the new + bootmem allocator (but this should do it for this) */ + +#define MAX_DMA_ADDRESS PAGE_OFFSET + +/* From PCI */ + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + +#endif /* _ASM_DMA_H */ diff --git a/arch/cris/include/asm/elf.h b/arch/cris/include/asm/elf.h new file mode 100644 index 000000000000..0f51b10b9f4f --- /dev/null +++ b/arch/cris/include/asm/elf.h @@ -0,0 +1,93 @@ +#ifndef __ASMCRIS_ELF_H +#define __ASMCRIS_ELF_H + +/* + * ELF register definitions.. + */ + +#include + +#define R_CRIS_NONE 0 +#define R_CRIS_8 1 +#define R_CRIS_16 2 +#define R_CRIS_32 3 +#define R_CRIS_8_PCREL 4 +#define R_CRIS_16_PCREL 5 +#define R_CRIS_32_PCREL 6 +#define R_CRIS_GNU_VTINHERIT 7 +#define R_CRIS_GNU_VTENTRY 8 +#define R_CRIS_COPY 9 +#define R_CRIS_GLOB_DAT 10 +#define R_CRIS_JUMP_SLOT 11 +#define R_CRIS_RELATIVE 12 +#define R_CRIS_16_GOT 13 +#define R_CRIS_32_GOT 14 +#define R_CRIS_16_GOTPLT 15 +#define R_CRIS_32_GOTPLT 16 +#define R_CRIS_32_GOTREL 17 +#define R_CRIS_32_PLT_GOTREL 18 +#define R_CRIS_32_PLT_PCREL 19 + +typedef unsigned long elf_greg_t; + +/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is + thus exposed to user-space. */ +#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* A placeholder; CRIS does not have any fp regs. */ +typedef unsigned long elf_fpregset_t; + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_CRIS + +#include + +/* The master for these definitions is {binutils}/include/elf/cris.h: */ +/* User symbols in this file have a leading underscore. */ +#define EF_CRIS_UNDERSCORE 0x00000001 + +/* This is a mask for different incompatible machine variants. */ +#define EF_CRIS_VARIANT_MASK 0x0000000e + +/* Variant 0; may contain v0..10 object. */ +#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 + +/* Variant 1; contains v32 object. */ +#define EF_CRIS_VARIANT_V32 0x00000002 + +/* Variant 2; contains object compatible with v32 and v10. */ +#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 +/* End of excerpt from {binutils}/include/elf/cris.h. */ + +#define USE_ELF_CORE_DUMP + +#define ELF_EXEC_PAGESIZE 8192 + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + +/* This yields a mask that user programs can use to figure out what + instruction set this CPU supports. This could be done in user space, + but it's not easy, and we've already done it here. */ + +#define ELF_HWCAP (0) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. +*/ + +#define ELF_PLATFORM (NULL) + +#define SET_PERSONALITY(ex) set_personality(PER_LINUX) + +#endif diff --git a/arch/cris/include/asm/emergency-restart.h b/arch/cris/include/asm/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/arch/cris/include/asm/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/cris/include/asm/errno.h b/arch/cris/include/asm/errno.h new file mode 100644 index 000000000000..2bf5eb5fa773 --- /dev/null +++ b/arch/cris/include/asm/errno.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_ERRNO_H +#define _CRIS_ERRNO_H + +#include + +#endif diff --git a/arch/cris/include/asm/eshlibld.h b/arch/cris/include/asm/eshlibld.h new file mode 100644 index 000000000000..10ce36cf79a9 --- /dev/null +++ b/arch/cris/include/asm/eshlibld.h @@ -0,0 +1,113 @@ +/*!************************************************************************** +*! +*! FILE NAME : eshlibld.h +*! +*! DESCRIPTION: Prototypes for exported shared library functions +*! +*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit +*! (EXPORTED) +*! +*!--------------------------------------------------------------------------- +*! +*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN +*! +*!**************************************************************************/ +/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ + +#ifndef _cris_relocate_h +#define _cris_relocate_h + +/* Please note that this file is also compiled into the xsim simulator. + Try to avoid breaking its double use (only works on a little-endian + 32-bit machine such as the i386 anyway). + + Use __KERNEL__ when you're about to use kernel functions, + (which you should not do here anyway, since this file is + used by glibc). + Use defined(__KERNEL__) || defined(__elinux__) when doing + things that only makes sense on an elinux system. + Use __CRIS__ when you're about to do (really) CRIS-specific code. +*/ + +/* We have dependencies all over the place for the host system + for xsim being a linux system, so let's not pretend anything + else with #ifdef:s here until fixed. */ +#include + +/* Maybe do sanity checking if file input. */ +#undef SANITYCHECK_RELOC + +/* Maybe output debug messages. */ +#undef RELOC_DEBUG + +/* Maybe we want to share core as well as disk space. + Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is + assumed that we want to share code when debugging (exposes more + trouble). */ +#ifndef SHARE_LIB_CORE +# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ + && !defined(CONFIG_SHARE_SHLIB_CORE) +# define SHARE_LIB_CORE 0 +# else +# define SHARE_LIB_CORE 1 +# endif /* __KERNEL__ etc */ +#endif /* SHARE_LIB_CORE */ + + +/* Main exported function; supposed to be called when the program a.out + has been read in. */ +extern int +perform_cris_aout_relocations(unsigned long text, unsigned long tlength, + unsigned long data, unsigned long dlength, + unsigned long baddr, unsigned long blength, + + /* These may be zero when there's "perfect" + position-independent code. */ + unsigned char *trel, unsigned long tsrel, + unsigned long dsrel, + + /* These will be zero at a first try, to see + if code is statically linked. Else a + second try, with the symbol table and + string table nonzero should be done. */ + unsigned char *symbols, unsigned long symlength, + unsigned char *strings, unsigned long stringlength, + + /* These will only be used when symbol table + information is present. */ + char **env, int envc, + int euid, int is_suid); + + +#ifdef RELOC_DEBUG +/* Task-specific debug stuff. */ +struct task_reloc_debug { + struct memdebug *alloclast; + unsigned long alloc_total; + unsigned long export_total; +}; +#endif /* RELOC_DEBUG */ + +#if SHARE_LIB_CORE + +/* When code (and some very specific data) is shared and not just + dynamically linked, we need to export hooks for exec beginning and + end. */ + +struct shlibdep; + +extern void +shlibmod_exit(struct shlibdep **deps); + +/* Returns 0 if failure, nonzero for ok. */ +extern int +shlibmod_fork(struct shlibdep **deps); + +#else /* ! SHARE_LIB_CORE */ +# define shlibmod_exit(x) +# define shlibmod_fork(x) 1 +#endif /* ! SHARE_LIB_CORE */ + +#endif _cris_relocate_h +/********************** END OF FILE eshlibld.h *****************************/ + diff --git a/arch/cris/include/asm/ethernet.h b/arch/cris/include/asm/ethernet.h new file mode 100644 index 000000000000..4d58652c3a49 --- /dev/null +++ b/arch/cris/include/asm/ethernet.h @@ -0,0 +1,21 @@ +/* + * ioctl defines for ethernet driver + * + * Copyright (c) 2001 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef _CRIS_ETHERNET_H +#define _CRIS_ETHERNET_H +#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ +#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ +#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ +#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ +#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ +#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ +#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ +#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ +#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 +#endif /* _CRIS_ETHERNET_H */ diff --git a/arch/cris/include/asm/etraxgpio.h b/arch/cris/include/asm/etraxgpio.h new file mode 100644 index 000000000000..38f1c8e1770c --- /dev/null +++ b/arch/cris/include/asm/etraxgpio.h @@ -0,0 +1,179 @@ +/* + * The following devices are accessable using this driver using + * GPIO_MAJOR (120) and a couple of minor numbers. + * + * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/gpiog minor 3 + * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG + * g1-g7 and g25-g31 is both input and outputs but on different pins + * Also note that some bits change pins depending on what interfaces + * are enabled. + * + * For ETRAX FS (CONFIG_ETRAXFS): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction + * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * + * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/pwm0 minor 16, PWM channel 0 on PA30 + * /dev/pwm1 minor 17, PWM channel 1 on PA31 + * /dev/pwm2 minor 18, PWM channel 2 on PB26 + * + */ +#ifndef _ASM_ETRAXGPIO_H +#define _ASM_ETRAXGPIO_H + +/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ +#ifdef CONFIG_ETRAX_ARCH_V10 +#define ETRAXGPIO_IOCTYPE 43 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_G 3 +#define GPIO_MINOR_LAST 3 +#endif + +#ifdef CONFIG_ETRAXFS +#define ETRAXGPIO_IOCTYPE 43 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#define GPIO_MINOR_E 5 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 5 +#endif +#endif + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#define ETRAXGPIO_IOCTYPE 43 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 4 +#endif +#define GPIO_MINOR_PWM0 16 +#define GPIO_MINOR_PWM1 17 +#define GPIO_MINOR_PWM2 18 +#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 +#endif + +/* supported ioctl _IOC_NR's */ + +#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ +#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ +#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ + +/* the alarm is waited for by select() */ + +#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ +#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ +#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ + +/* LED ioctl */ +#define IO_LEDACTIVE_SET 0x7 /* set active led + * 0=off, 1=green, 2=red, 3=yellow */ + +/* GPIO direction ioctl's */ +#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ +#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, + returns mask with current inputs (obsolete) */ +#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, + returns mask with current outputs (obsolete)*/ + +/* LED ioctl extended */ +#define IO_LED_SETBIT 0xB +#define IO_LED_CLRBIT 0xC + +/* SHUTDOWN ioctl */ +#define IO_SHUTDOWN 0xD +#define IO_GET_PWR_BT 0xE + +/* Bit toggling in driver settings */ +/* bit set in low byte0 is CLK mask (0x00FF), + bit set in byte1 is DATA mask (0xFF00) + msb, data_mask[7:0] , clk_mask[7:0] + */ +#define IO_CFG_WRITE_MODE 0xF +#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ + ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) + +/* The following 4 ioctl's take a pointer as argument and handles + * 32 bit ports (port G) properly. + * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT + */ +#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ +#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ +#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, + * *arg updated with current input pins. + */ +#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, + * *arg updated with current output pins. + */ + +/* The following ioctl's are applicable to the PWM channels only */ + +#define IO_PWM_SET_MODE 0x20 + +enum io_pwm_mode { + PWM_OFF = 0, /* disabled, deallocated */ + PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ + PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ + PWM_VARFREQ = 3 /* individually configurable high/low periods */ +}; + +struct io_pwm_set_mode { + enum io_pwm_mode mode; +}; + +/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns + * from 10ns (value = 0) to 81920ns (value = 8191) + * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to + * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty + * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) + */ +#define IO_PWM_SET_PERIOD 0x21 + +struct io_pwm_set_period { + unsigned int lo; /* 0..8191 */ + unsigned int hi; /* 0..8191 */ +}; + +/* Only for modes PWM_STANDARD and PWM_FAST. + * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from + * 0 (value = 0) to 255/256 (value = 255). + * For PWM_FAST, set duty cycle of PWM output signal from + * 0% (value = 0) to 100% (value = 255). Output signal in this mode + * is a 10ns pulse surrounded by a high or low level depending on duty + * cycle (except for 0% and 100% which result in a constant output). + * Resulting output frequency varies from 50 MHz at 50% duty cycle, + * down to 390 kHz at min/max duty cycle. + */ +#define IO_PWM_SET_DUTY 0x22 + +struct io_pwm_set_duty { + int duty; /* 0..255 */ +}; + +#endif diff --git a/arch/cris/include/asm/etraxi2c.h b/arch/cris/include/asm/etraxi2c.h new file mode 100644 index 000000000000..e369a7620893 --- /dev/null +++ b/arch/cris/include/asm/etraxi2c.h @@ -0,0 +1,36 @@ +/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ + +#ifndef _LINUX_ETRAXI2C_H +#define _LINUX_ETRAXI2C_H + +/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ + +#define ETRAXI2C_IOCTYPE 44 + +/* supported ioctl _IOC_NR's */ + +/* in write operations, the argument contains both i2c + * slave, register and value. + */ + +#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) +#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) + +#define I2C_ARGSLAVE(arg) ((arg) >> 16) +#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) +#define I2C_ARGVALUE(arg) ((arg) & 0xff) + +#define I2C_WRITEREG 0x1 /* write to an i2c register */ +#define I2C_READREG 0x2 /* read from an i2c register */ + +/* +EXAMPLE usage: + + i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); + ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); + + i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); + val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); + +*/ +#endif diff --git a/arch/cris/include/asm/fasttimer.h b/arch/cris/include/asm/fasttimer.h new file mode 100644 index 000000000000..8f8a8d6c9653 --- /dev/null +++ b/arch/cris/include/asm/fasttimer.h @@ -0,0 +1,47 @@ +/* + * linux/include/asm-cris/fasttimer.h + * + * Fast timers for ETRAX100LX + * Copyright (C) 2000-2007 Axis Communications AB + */ +#include /* struct timeval */ +#include + +#ifdef CONFIG_ETRAX_FAST_TIMER + +typedef void fast_timer_function_type(unsigned long); + +struct fasttime_t { + unsigned long tv_jiff; /* jiffies */ + unsigned long tv_usec; /* microseconds */ +}; + +struct fast_timer{ /* Close to timer_list */ + struct fast_timer *next; + struct fast_timer *prev; + struct fasttime_t tv_set; + struct fasttime_t tv_expires; + unsigned long delay_us; + fast_timer_function_type *function; + unsigned long data; + const char *name; +}; + +extern struct fast_timer *fast_timer_list; + +void start_one_shot_timer(struct fast_timer *t, + fast_timer_function_type *function, + unsigned long data, + unsigned long delay_us, + const char *name); + +int del_fast_timer(struct fast_timer * t); +/* return 1 if deleted */ + + +void schedule_usleep(unsigned long us); + + +int fast_timer_init(void); + +#endif diff --git a/arch/cris/include/asm/fb.h b/arch/cris/include/asm/fb.h new file mode 100644 index 000000000000..c7df38030992 --- /dev/null +++ b/arch/cris/include/asm/fb.h @@ -0,0 +1,12 @@ +#ifndef _ASM_FB_H_ +#define _ASM_FB_H_ +#include + +#define fb_pgprotect(...) do {} while (0) + +static inline int fb_is_primary_device(struct fb_info *info) +{ + return 0; +} + +#endif /* _ASM_FB_H_ */ diff --git a/arch/cris/include/asm/fcntl.h b/arch/cris/include/asm/fcntl.h new file mode 100644 index 000000000000..46ab12db5739 --- /dev/null +++ b/arch/cris/include/asm/fcntl.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/futex.h b/arch/cris/include/asm/futex.h new file mode 100644 index 000000000000..6a332a9f099c --- /dev/null +++ b/arch/cris/include/asm/futex.h @@ -0,0 +1,6 @@ +#ifndef _ASM_FUTEX_H +#define _ASM_FUTEX_H + +#include + +#endif diff --git a/arch/cris/include/asm/hardirq.h b/arch/cris/include/asm/hardirq.h new file mode 100644 index 000000000000..74178adeb1cd --- /dev/null +++ b/arch/cris/include/asm/hardirq.h @@ -0,0 +1,27 @@ +#ifndef __ASM_HARDIRQ_H +#define __ASM_HARDIRQ_H + +#include +#include +#include + +typedef struct { + unsigned int __softirq_pending; +} ____cacheline_aligned irq_cpustat_t; + +#include /* Standard mappings for irq_cpustat_t above */ + +void ack_bad_irq(unsigned int irq); + +#define HARDIRQ_BITS 8 + +/* + * The hardirq mask has to be large enough to have + * space for potentially all IRQ sources in the system + * nesting on a single CPU: + */ +#if (1 << HARDIRQ_BITS) < NR_IRQS +# error HARDIRQ_BITS is too low! +#endif + +#endif /* __ASM_HARDIRQ_H */ diff --git a/arch/cris/include/asm/hw_irq.h b/arch/cris/include/asm/hw_irq.h new file mode 100644 index 000000000000..298066020af2 --- /dev/null +++ b/arch/cris/include/asm/hw_irq.h @@ -0,0 +1,5 @@ +#ifndef _ASM_HW_IRQ_H +#define _ASM_HW_IRQ_H + +#endif + diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h new file mode 100644 index 000000000000..32567bc2a421 --- /dev/null +++ b/arch/cris/include/asm/io.h @@ -0,0 +1,154 @@ +#ifndef _ASM_CRIS_IO_H +#define _ASM_CRIS_IO_H + +#include /* for __va, __pa */ +#include +#include + +struct cris_io_operations +{ + u32 (*read_mem)(void *addr, int size); + void (*write_mem)(u32 val, int size, void *addr); + u32 (*read_io)(u32 port, void *addr, int size, int count); + void (*write_io)(u32 port, void *addr, int size, int count); +}; + +#ifdef CONFIG_PCI +extern struct cris_io_operations *cris_iops; +#else +#define cris_iops ((struct cris_io_operations*)NULL) +#endif + +/* + * Change virtual addresses to physical addresses and vv. + */ + +static inline unsigned long virt_to_phys(volatile void * address) +{ + return __pa(address); +} + +static inline void * phys_to_virt(unsigned long address) +{ + return __va(address); +} + +extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); +extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); + +static inline void __iomem * ioremap (unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size, 0); +} + +extern void iounmap(volatile void * __iomem addr); + +extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); + +/* + * IO bus memory addresses are also 1:1 with the physical address + */ +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the CRIS architecture, we just read/write the + * memory location directly. + */ +#ifdef CONFIG_PCI +#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) +#else +#define PCI_SPACE(x) 0 +#endif +static inline unsigned char readb(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 1); + else + return *(volatile unsigned char __force *) addr; +} +static inline unsigned short readw(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 2); + else + return *(volatile unsigned short __force *) addr; +} +static inline unsigned int readl(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 4); + else + return *(volatile unsigned int __force *) addr; +} +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +static inline void writeb(unsigned char b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 1, (void*)addr); + else + *(volatile unsigned char __force *) addr = b; +} +static inline void writew(unsigned short b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 2, (void*)addr); + else + *(volatile unsigned short __force *) addr = b; +} +static inline void writel(unsigned int b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 4, (void*)addr); + else + *(volatile unsigned int __force *) addr = b; +} +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define mmiowb() + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + + +/* I/O port access. Normally there is no I/O space on CRIS but when + * Cardbus/PCI is enabled the request is passed through the bridge. + */ + +#define IO_SPACE_LIMIT 0xffff +#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) +#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) +#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) +#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) +#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) +#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) +#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1) +#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1) +#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1) +#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count) +#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count) +#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count) + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem + * access + */ +#define xlate_dev_mem_ptr(p) __va(p) + +/* + * Convert a virtual cached pointer to an uncached pointer + */ +#define xlate_dev_kmem_ptr(p) p + +#endif diff --git a/arch/cris/include/asm/ioctl.h b/arch/cris/include/asm/ioctl.h new file mode 100644 index 000000000000..b279fe06dfe5 --- /dev/null +++ b/arch/cris/include/asm/ioctl.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/ioctls.h b/arch/cris/include/asm/ioctls.h new file mode 100644 index 000000000000..4f4e52531fa0 --- /dev/null +++ b/arch/cris/include/asm/ioctls.h @@ -0,0 +1,91 @@ +#ifndef __ARCH_CRIS_IOCTLS_H__ +#define __ARCH_CRIS_IOCTLS_H__ + +/* verbatim copy of asm-i386/ioctls.h */ + +#include + +/* 0x54 is just a magic number to make these relatively unique ('T') */ + +#define TCGETS 0x5401 +#define TCSETS 0x5402 +#define TCSETSW 0x5403 +#define TCSETSF 0x5404 +#define TCGETA 0x5405 +#define TCSETA 0x5406 +#define TCSETAW 0x5407 +#define TCSETAF 0x5408 +#define TCSBRK 0x5409 +#define TCXONC 0x540A +#define TCFLSH 0x540B +#define TIOCEXCL 0x540C +#define TIOCNXCL 0x540D +#define TIOCSCTTY 0x540E +#define TIOCGPGRP 0x540F +#define TIOCSPGRP 0x5410 +#define TIOCOUTQ 0x5411 +#define TIOCSTI 0x5412 +#define TIOCGWINSZ 0x5413 +#define TIOCSWINSZ 0x5414 +#define TIOCMGET 0x5415 +#define TIOCMBIS 0x5416 +#define TIOCMBIC 0x5417 +#define TIOCMSET 0x5418 +#define TIOCGSOFTCAR 0x5419 +#define TIOCSSOFTCAR 0x541A +#define FIONREAD 0x541B +#define TIOCINQ FIONREAD +#define TIOCLINUX 0x541C +#define TIOCCONS 0x541D +#define TIOCGSERIAL 0x541E +#define TIOCSSERIAL 0x541F +#define TIOCPKT 0x5420 +#define FIONBIO 0x5421 +#define TIOCNOTTY 0x5422 +#define TIOCSETD 0x5423 +#define TIOCGETD 0x5424 +#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ +#define TIOCSBRK 0x5427 /* BSD compatibility */ +#define TIOCCBRK 0x5428 /* BSD compatibility */ +#define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) +#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ + +#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ +#define FIOCLEX 0x5451 +#define FIOASYNC 0x5452 +#define TIOCSERCONFIG 0x5453 +#define TIOCSERGWILD 0x5454 +#define TIOCSERSWILD 0x5455 +#define TIOCGLCKTRMIOS 0x5456 +#define TIOCSLCKTRMIOS 0x5457 +#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ +#define TIOCSERGETLSR 0x5459 /* Get line status register */ +#define TIOCSERGETMULTI 0x545A /* Get multiport config */ +#define TIOCSERSETMULTI 0x545B /* Set multiport config */ + +#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ +#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ +#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ +#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ +#define FIOQSIZE 0x5460 + +#define TIOCSERSETRS485 0x5461 /* enable rs-485 */ +#define TIOCSERWRRS485 0x5462 /* write rs-485 */ + +/* Used for packet mode */ +#define TIOCPKT_DATA 0 +#define TIOCPKT_FLUSHREAD 1 +#define TIOCPKT_FLUSHWRITE 2 +#define TIOCPKT_STOP 4 +#define TIOCPKT_START 8 +#define TIOCPKT_NOSTOP 16 +#define TIOCPKT_DOSTOP 32 + +#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ + +#endif diff --git a/arch/cris/include/asm/ipcbuf.h b/arch/cris/include/asm/ipcbuf.h new file mode 100644 index 000000000000..8b0c18b02844 --- /dev/null +++ b/arch/cris/include/asm/ipcbuf.h @@ -0,0 +1,29 @@ +#ifndef __CRIS_IPCBUF_H__ +#define __CRIS_IPCBUF_H__ + +/* + * The user_ipc_perm structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 32-bit mode_t and seq + * - 2 miscellaneous 32-bit values + */ + +struct ipc64_perm +{ + __kernel_key_t key; + __kernel_uid32_t uid; + __kernel_gid32_t gid; + __kernel_uid32_t cuid; + __kernel_gid32_t cgid; + __kernel_mode_t mode; + unsigned short __pad1; + unsigned short seq; + unsigned short __pad2; + unsigned long __unused1; + unsigned long __unused2; +}; + +#endif /* __CRIS_IPCBUF_H__ */ diff --git a/arch/cris/include/asm/irq.h b/arch/cris/include/asm/irq.h new file mode 100644 index 000000000000..ce0fcf540d62 --- /dev/null +++ b/arch/cris/include/asm/irq.h @@ -0,0 +1,13 @@ +#ifndef _ASM_IRQ_H +#define _ASM_IRQ_H + +#include + +static inline int irq_canonicalize(int irq) +{ + return irq; +} + +#endif /* _ASM_IRQ_H */ + + diff --git a/arch/cris/include/asm/irq_regs.h b/arch/cris/include/asm/irq_regs.h new file mode 100644 index 000000000000..3dd9c0b70270 --- /dev/null +++ b/arch/cris/include/asm/irq_regs.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/kdebug.h b/arch/cris/include/asm/kdebug.h new file mode 100644 index 000000000000..6ece1b037665 --- /dev/null +++ b/arch/cris/include/asm/kdebug.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/kmap_types.h b/arch/cris/include/asm/kmap_types.h new file mode 100644 index 000000000000..492988cb9077 --- /dev/null +++ b/arch/cris/include/asm/kmap_types.h @@ -0,0 +1,25 @@ +#ifndef _ASM_KMAP_TYPES_H +#define _ASM_KMAP_TYPES_H + +/* Dummy header just to define km_type. None of this + * is actually used on cris. + */ + +enum km_type { + KM_BOUNCE_READ, + KM_SKB_SUNRPC_DATA, + KM_SKB_DATA_SOFTIRQ, + KM_USER0, + KM_USER1, + KM_BIO_SRC_IRQ, + KM_BIO_DST_IRQ, + KM_PTE0, + KM_PTE1, + KM_IRQ0, + KM_IRQ1, + KM_SOFTIRQ0, + KM_SOFTIRQ1, + KM_TYPE_NR +}; + +#endif diff --git a/arch/cris/include/asm/linkage.h b/arch/cris/include/asm/linkage.h new file mode 100644 index 000000000000..291c2d01c44f --- /dev/null +++ b/arch/cris/include/asm/linkage.h @@ -0,0 +1,6 @@ +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +/* Nothing to see here... */ + +#endif diff --git a/arch/cris/include/asm/local.h b/arch/cris/include/asm/local.h new file mode 100644 index 000000000000..c11c530f74d0 --- /dev/null +++ b/arch/cris/include/asm/local.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/mman.h b/arch/cris/include/asm/mman.h new file mode 100644 index 000000000000..1c35e1b66b46 --- /dev/null +++ b/arch/cris/include/asm/mman.h @@ -0,0 +1,19 @@ +#ifndef __CRIS_MMAN_H__ +#define __CRIS_MMAN_H__ + +/* verbatim copy of asm-i386/ version */ + +#include + +#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ +#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ +#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ +#define MAP_LOCKED 0x2000 /* pages are locked */ +#define MAP_NORESERVE 0x4000 /* don't check for reservations */ +#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ +#define MAP_NONBLOCK 0x10000 /* do not block on IO */ + +#define MCL_CURRENT 1 /* lock all current mappings */ +#define MCL_FUTURE 2 /* lock all future mappings */ + +#endif /* __CRIS_MMAN_H__ */ diff --git a/arch/cris/include/asm/mmu.h b/arch/cris/include/asm/mmu.h new file mode 100644 index 000000000000..e06ea94ecffd --- /dev/null +++ b/arch/cris/include/asm/mmu.h @@ -0,0 +1,10 @@ +/* + * CRIS MMU constants and PTE layout + */ + +#ifndef _CRIS_MMU_H +#define _CRIS_MMU_H + +#include + +#endif diff --git a/arch/cris/include/asm/mmu_context.h b/arch/cris/include/asm/mmu_context.h new file mode 100644 index 000000000000..72ba08dcfd18 --- /dev/null +++ b/arch/cris/include/asm/mmu_context.h @@ -0,0 +1,26 @@ +#ifndef __CRIS_MMU_CONTEXT_H +#define __CRIS_MMU_CONTEXT_H + +#include + +extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); +extern void get_mmu_context(struct mm_struct *mm); +extern void destroy_context(struct mm_struct *mm); +extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk); + +#define deactivate_mm(tsk,mm) do { } while (0) + +#define activate_mm(prev,next) switch_mm((prev),(next),NULL) + +/* current active pgd - this is similar to other processors pgd + * registers like cr3 on the i386 + */ + +extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */ + +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ +} + +#endif diff --git a/arch/cris/include/asm/module.h b/arch/cris/include/asm/module.h new file mode 100644 index 000000000000..7ee72311bd78 --- /dev/null +++ b/arch/cris/include/asm/module.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_MODULE_H +#define _ASM_CRIS_MODULE_H +/* cris is simple */ +struct mod_arch_specific { }; + +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Ehdr Elf32_Ehdr +#endif /* _ASM_CRIS_MODULE_H */ diff --git a/arch/cris/include/asm/msgbuf.h b/arch/cris/include/asm/msgbuf.h new file mode 100644 index 000000000000..ada63df1d574 --- /dev/null +++ b/arch/cris/include/asm/msgbuf.h @@ -0,0 +1,33 @@ +#ifndef _CRIS_MSGBUF_H +#define _CRIS_MSGBUF_H + +/* verbatim copy of asm-i386 version */ + +/* + * The msqid64_ds structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct msqid64_ds { + struct ipc64_perm msg_perm; + __kernel_time_t msg_stime; /* last msgsnd time */ + unsigned long __unused1; + __kernel_time_t msg_rtime; /* last msgrcv time */ + unsigned long __unused2; + __kernel_time_t msg_ctime; /* last change time */ + unsigned long __unused3; + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* _CRIS_MSGBUF_H */ diff --git a/arch/cris/include/asm/mutex.h b/arch/cris/include/asm/mutex.h new file mode 100644 index 000000000000..458c1f7fbc18 --- /dev/null +++ b/arch/cris/include/asm/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include diff --git a/arch/cris/include/asm/page.h b/arch/cris/include/asm/page.h new file mode 100644 index 000000000000..f3fdbd09c34c --- /dev/null +++ b/arch/cris/include/asm/page.h @@ -0,0 +1,74 @@ +#ifndef _CRIS_PAGE_H +#define _CRIS_PAGE_H + +#include +#include + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 13 +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) + +#define clear_user_page(page, vaddr, pg) clear_page(page) +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) + +#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ + alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) +#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE + +/* + * These are used to make use of C type-checking.. + */ +#ifndef __ASSEMBLY__ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; +#endif + +#define pte_val(x) ((x).pte) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ +/* for that before indexing into the page table starting at mem_map */ +#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) +#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) + +/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so + * we can let the map start there. notice that we subtract PAGE_OFFSET because + * we start our mem_map there - in other ports they map mem_map physically and + * use __pa instead. in our system both the physical and virtual address of DRAM + * is too high to let mem_map start at 0, so we do it this way instead (similar + * to arm and m68k I think) + */ + +#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) +#define VALID_PAGE(page) (((page) - mem_map) < max_mapnr) +#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) + +/* convert a page (based on mem_map and forward) to a physical address + * do this by figuring out the virtual address and then use __pa + */ + +#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) + +#ifndef __ASSEMBLY__ + +#endif /* __ASSEMBLY__ */ + +#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#include +#include + +#endif /* _CRIS_PAGE_H */ + diff --git a/arch/cris/include/asm/param.h b/arch/cris/include/asm/param.h new file mode 100644 index 000000000000..0e47994e40be --- /dev/null +++ b/arch/cris/include/asm/param.h @@ -0,0 +1,23 @@ +#ifndef _ASMCRIS_PARAM_H +#define _ASMCRIS_PARAM_H + +/* Currently we assume that HZ=100 is good for CRIS. */ +#ifdef __KERNEL__ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ +# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ +# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ +#endif + +#ifndef HZ +#define HZ 100 +#endif + +#define EXEC_PAGESIZE 8192 + +#ifndef NOGROUP +#define NOGROUP (-1) +#endif + +#define MAXHOSTNAMELEN 64 /* max length of hostname */ + +#endif diff --git a/arch/cris/include/asm/pci.h b/arch/cris/include/asm/pci.h new file mode 100644 index 000000000000..730ce40fdd0f --- /dev/null +++ b/arch/cris/include/asm/pci.h @@ -0,0 +1,68 @@ +#ifndef __ASM_CRIS_PCI_H +#define __ASM_CRIS_PCI_H + + +#ifdef __KERNEL__ +#include /* for struct page */ + +/* Can be used to override the logic in pci_scan_bus for skipping + already-configured bus numbers - to be used for buggy BIOSes + or architectures with incomplete PCI setup by the loader */ + +#define pcibios_assign_all_busses(void) 1 + +extern unsigned long pci_mem_start; +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0x10000000 + +#define PCIBIOS_MIN_CARDBUS_IO 0x4000 + +void pcibios_config_init(void); +struct pci_bus * pcibios_scan_root(int bus); +int pcibios_assign_resources(void); + +void pcibios_set_master(struct pci_dev *dev); +void pcibios_penalize_isa_irq(int irq); +struct irq_routing_table *pcibios_get_irq_routing_table(void); +int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); + +/* Dynamic DMA mapping stuff. + * i386 has everything mapped statically. + */ + +#include +#include +#include +#include +#include + +struct pci_dev; + +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (1) + +/* pci_unmap_{page,single} is a nop so... */ +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) +#define pci_unmap_addr(PTR, ADDR_NAME) (0) +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) +#define pci_unmap_len(PTR, LEN_NAME) (0) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) + +#define HAVE_PCI_MMAP +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + + +#endif /* __KERNEL__ */ + +/* implement the pci_ DMA API in terms of the generic device dma_ one */ +#include + +/* generic pci stuff */ +#include + +#endif /* __ASM_CRIS_PCI_H */ diff --git a/arch/cris/include/asm/percpu.h b/arch/cris/include/asm/percpu.h new file mode 100644 index 000000000000..6db9b43cf80a --- /dev/null +++ b/arch/cris/include/asm/percpu.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_PERCPU_H +#define _CRIS_PERCPU_H + +#include + +#endif /* _CRIS_PERCPU_H */ diff --git a/arch/cris/include/asm/pgalloc.h b/arch/cris/include/asm/pgalloc.h new file mode 100644 index 000000000000..a1ba761d0573 --- /dev/null +++ b/arch/cris/include/asm/pgalloc.h @@ -0,0 +1,58 @@ +#ifndef _CRIS_PGALLOC_H +#define _CRIS_PGALLOC_H + +#include +#include + +#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) +#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) +#define pmd_pgtable(pmd) pmd_page(pmd) + +/* + * Allocate and free page tables. + */ + +static inline pgd_t *pgd_alloc (struct mm_struct *mm) +{ + return (pgd_t *)get_zeroed_page(GFP_KERNEL); +} + +static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) +{ + free_page((unsigned long)pgd); +} + +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) +{ + pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); + return pte; +} + +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) +{ + struct page *pte; + pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); + pgtable_page_ctor(pte); + return pte; +} + +static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + free_page((unsigned long)pte); +} + +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) +{ + pgtable_page_dtor(pte); + __free_page(pte); +} + +#define __pte_free_tlb(tlb,pte) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) + +#define check_pgt_cache() do { } while (0) + +#endif diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h new file mode 100644 index 000000000000..50aa974aa834 --- /dev/null +++ b/arch/cris/include/asm/pgtable.h @@ -0,0 +1,299 @@ +/* + * CRIS pgtable.h - macros and functions to manipulate page tables. + */ + +#ifndef _CRIS_PGTABLE_H +#define _CRIS_PGTABLE_H + +#include +#include + +#ifndef __ASSEMBLY__ +#include +#include +#endif +#include + +/* + * The Linux memory management assumes a three-level page table setup. On + * CRIS, we use that, but "fold" the mid level into the top-level page + * table. Since the MMU TLB is software loaded through an interrupt, it + * supports any page table structure, so we could have used a three-level + * setup, but for the amounts of memory we normally use, a two-level is + * probably more efficient. + * + * This file contains the functions and defines necessary to modify and use + * the CRIS page table tree. + */ +#ifndef __ASSEMBLY__ +extern void paging_init(void); +#endif + +/* Certain architectures need to do special things when pte's + * within a page table are directly modified. Thus, the following + * hook is made available. + */ +#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) +#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) + +/* + * (pmds are folded into pgds so this doesn't get actually called, + * but the define is needed for a generic inline function.) + */ +#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) +#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) + +/* PGDIR_SHIFT determines the size of the area a second-level page table can + * map. It is equal to the page size times the number of PTE's that fit in + * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. + */ + +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * entries per page directory level: we use a two-level, so + * we don't really have any PMD directory physically. + * pointers are 4 bytes so we can use the page size and + * divide it by 4 (shift by 2). + */ +#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) +#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) + +/* calculate how many PGD entries a user-level program can use + * the first mappable virtual address is 0 + * (TASK_SIZE is the maximum virtual address space) + */ + +#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) +#define FIRST_USER_ADDRESS 0 + +/* zero page used for uninitialized stuff */ +#ifndef __ASSEMBLY__ +extern unsigned long empty_zero_page; +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) +#endif + +/* number of bits that fit into a memory pointer */ +#define BITS_PER_PTR (8*sizeof(unsigned long)) + +/* to align the pointer to a pointer address */ +#define PTR_MASK (~(sizeof(void*)-1)) + +/* sizeof(void*)==1<>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) + +/* to set the page-dir */ +#define SET_PAGE_DIR(tsk,pgdir) + +#define pte_none(x) (!pte_val(x)) +#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) +#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) + +#define pmd_none(x) (!pmd_val(x)) +/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad + * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. + */ +#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) +#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) +#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) + +#ifndef __ASSEMBLY__ + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not.. + */ + +static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } +static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } +static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } +static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } +static inline int pte_special(pte_t pte) { return 0; } + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); + return pte; +} + +static inline pte_t pte_mkclean(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); + return pte; +} + +static inline pte_t pte_mkold(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); + return pte; +} + +static inline pte_t pte_mkwrite(pte_t pte) +{ + pte_val(pte) |= _PAGE_WRITE; + if (pte_val(pte) & _PAGE_MODIFIED) + pte_val(pte) |= _PAGE_SILENT_WRITE; + return pte; +} + +static inline pte_t pte_mkdirty(pte_t pte) +{ + pte_val(pte) |= _PAGE_MODIFIED; + if (pte_val(pte) & _PAGE_WRITE) + pte_val(pte) |= _PAGE_SILENT_WRITE; + return pte; +} + +static inline pte_t pte_mkyoung(pte_t pte) +{ + pte_val(pte) |= _PAGE_ACCESSED; + if (pte_val(pte) & _PAGE_READ) + { + pte_val(pte) |= _PAGE_SILENT_READ; + if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == + (_PAGE_WRITE | _PAGE_MODIFIED)) + pte_val(pte) |= _PAGE_SILENT_WRITE; + } + return pte; +} +static inline pte_t pte_mkspecial(pte_t pte) { return pte; } + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ + +/* What actually goes as arguments to the various functions is less than + * obvious, but a rule of thumb is that struct page's goes as struct page *, + * really physical DRAM addresses are unsigned long's, and DRAM "virtual" + * addresses (the 0xc0xxxxxx's) goes as void *'s. + */ + +static inline pte_t __mk_pte(void * page, pgprot_t pgprot) +{ + pte_t pte; + /* the PTE needs a physical address */ + pte_val(pte) = __pa(page) | pgprot_val(pgprot); + return pte; +} + +#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) + +#define mk_pte_phys(physpage, pgprot) \ +({ \ + pte_t __pte; \ + \ + pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ + __pte; \ +}) + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } + + +/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval + * __pte_page(pte_val) refers to the "virtual" DRAM interval + * pte_pagenr refers to the page-number counted starting from the virtual DRAM start + */ + +static inline unsigned long __pte_page(pte_t pte) +{ + /* the PTE contains a physical address */ + return (unsigned long)__va(pte_val(pte) & PAGE_MASK); +} + +#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) + +/* permanent address of a page */ + +#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) +#define pte_page(pte) (mem_map+pte_pagenr(pte)) + +/* only the pte's themselves need to point to physical DRAM (see above) + * the pagetable links are purely handled within the kernel SW and thus + * don't need the __pa and __va transformations. + */ + +static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) +{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } + +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) +#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) + +/* to find an entry in a page-table-directory. */ +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) + +/* to find an entry in a page-table-directory */ +static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address) +{ + return mm->pgd + pgd_index(address); +} + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* Find an entry in the third-level page table.. */ +#define __pte_offset(address) \ + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) +#define pte_offset_map(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) + +#define pte_unmap(pte) do { } while (0) +#define pte_unmap_nested(pte) do { } while (0) +#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) + +#define pte_ERROR(e) \ + printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) +#define pgd_ERROR(e) \ + printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) + + +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ + +/* + * CRIS doesn't have any external MMU info: the kernel page + * tables contain all the necessary information. + * + * Actually I am not sure on what this could be used for. + */ +static inline void update_mmu_cache(struct vm_area_struct * vma, + unsigned long address, pte_t pte) +{ +} + +/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ +/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ + +#define __swp_type(x) (((x).val >> 5) & 0x7f) +#define __swp_offset(x) ((x).val >> 12) +#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +#define kern_addr_valid(addr) (1) + +#include + +/* + * No page table caches to initialise + */ +#define pgtable_cache_init() do { } while (0) + +#define pte_to_pgoff(x) (pte_val(x) >> 6) +#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) + +typedef pte_t *pte_addr_t; + +#endif /* __ASSEMBLY__ */ +#endif /* _CRIS_PGTABLE_H */ diff --git a/arch/cris/include/asm/poll.h b/arch/cris/include/asm/poll.h new file mode 100644 index 000000000000..c98509d3149e --- /dev/null +++ b/arch/cris/include/asm/poll.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/posix_types.h b/arch/cris/include/asm/posix_types.h new file mode 100644 index 000000000000..ce3fb25a460b --- /dev/null +++ b/arch/cris/include/asm/posix_types.h @@ -0,0 +1,66 @@ +/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ +/* I guess we should write these in assembler because they are used often. */ + +#ifndef __ARCH_CRIS_POSIX_TYPES_H +#define __ARCH_CRIS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef __SIZE_TYPE__ __kernel_size_t; +typedef long __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { + int val[2]; +} __kernel_fsid_t; + +#ifdef __KERNEL__ + +#undef __FD_SET +#define __FD_SET(fd,fdsetp) set_bit(fd, (void *)(fdsetp)) + +#undef __FD_CLR +#define __FD_CLR(fd,fdsetp) clear_bit(fd, (void *)(fdsetp)) + +#undef __FD_ISSET +#define __FD_ISSET(fd,fdsetp) test_bit(fd, (void *)(fdsetp)) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) memset((void *)(fdsetp), 0, __FDSET_LONGS << 2) + +#endif /* __KERNEL__ */ + +#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/arch/cris/include/asm/processor.h b/arch/cris/include/asm/processor.h new file mode 100644 index 000000000000..3f7248f7a1c9 --- /dev/null +++ b/arch/cris/include/asm/processor.h @@ -0,0 +1,75 @@ +/* + * include/asm-cris/processor.h + * + * Copyright (C) 2000, 2001 Axis Communications AB + * + * Authors: Bjorn Wesen Initial version + * + */ + +#ifndef __ASM_CRIS_PROCESSOR_H +#define __ASM_CRIS_PROCESSOR_H + +#include +#include +#include +#include + +struct task_struct; + +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) + +/* THREAD_SIZE is the size of the task_struct/kernel_stack combo. + * normally, the stack is found by doing something like p + THREAD_SIZE + * in CRIS, a page is 8192 bytes, which seems like a sane size + */ + +#define THREAD_SIZE PAGE_SIZE +#define KERNEL_STACK_SIZE PAGE_SIZE + +/* + * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. + * This macro allows us to find those regs for a task. + * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while + * we're in the kernel, won't affect this - only the first user->kernel transition + * registers are reached by this. + */ + +#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) + +/* + * Dito but for the currently running task + */ + +#define task_pt_regs(task) user_regs(task_thread_info(task)) +#define current_regs() task_pt_regs(current) + +static inline void prepare_to_copy(struct task_struct *tsk) +{ +} + +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) + +extern unsigned long thread_saved_pc(struct task_struct *tsk); + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ + /* Nothing needs to be done. */ +} + +#define init_stack (init_thread_union.stack) + +#define cpu_relax() barrier() + +#endif /* __ASM_CRIS_PROCESSOR_H */ diff --git a/arch/cris/include/asm/ptrace.h b/arch/cris/include/asm/ptrace.h new file mode 100644 index 000000000000..6618893bfe8e --- /dev/null +++ b/arch/cris/include/asm/ptrace.h @@ -0,0 +1,16 @@ +#ifndef _CRIS_PTRACE_H +#define _CRIS_PTRACE_H + +#include + +#ifdef __KERNEL__ + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 + +#define profile_pc(regs) instruction_pointer(regs) + +#endif /* __KERNEL__ */ + +#endif /* _CRIS_PTRACE_H */ diff --git a/arch/cris/include/asm/resource.h b/arch/cris/include/asm/resource.h new file mode 100644 index 000000000000..b5d29448de4e --- /dev/null +++ b/arch/cris/include/asm/resource.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_RESOURCE_H +#define _CRIS_RESOURCE_H + +#include + +#endif diff --git a/arch/cris/include/asm/rs485.h b/arch/cris/include/asm/rs485.h new file mode 100644 index 000000000000..c331c51b0c2b --- /dev/null +++ b/arch/cris/include/asm/rs485.h @@ -0,0 +1,20 @@ +/* RS-485 structures */ + +/* RS-485 support */ +/* Used with ioctl() TIOCSERSETRS485 */ +struct rs485_control { + unsigned short rts_on_send; + unsigned short rts_after_sent; + unsigned long delay_rts_before_send; + unsigned short enabled; +#ifdef __KERNEL__ + int disable_serial_loopback; +#endif +}; + +/* Used with ioctl() TIOCSERWRRS485 */ +struct rs485_write { + unsigned short outc_size; + unsigned char *outc; +}; + diff --git a/arch/cris/include/asm/rtc.h b/arch/cris/include/asm/rtc.h new file mode 100644 index 000000000000..17d3019529e1 --- /dev/null +++ b/arch/cris/include/asm/rtc.h @@ -0,0 +1,107 @@ + +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef CONFIG_ETRAX_DS1302 + /* Dallas DS1302 clock/calendar register numbers. */ +# define RTC_SECONDS 0 +# define RTC_MINUTES 1 +# define RTC_HOURS 2 +# define RTC_DAY_OF_MONTH 3 +# define RTC_MONTH 4 +# define RTC_WEEKDAY 5 +# define RTC_YEAR 6 +# define RTC_CONTROL 7 + + /* Bits in CONTROL register. */ +# define RTC_CONTROL_WRITEPROTECT 0x80 +# define RTC_TRICKLECHARGER 8 + + /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ +# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ +# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ +# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ +# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ +# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ +# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ +# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ + +#elif defined(CONFIG_ETRAX_PCF8563) + /* I2C bus slave registers. */ +# define RTC_I2C_READ 0xa3 +# define RTC_I2C_WRITE 0xa2 + + /* Phillips PCF8563 registers. */ +# define RTC_CONTROL1 0x00 /* Control/Status register 1. */ +# define RTC_CONTROL2 0x01 /* Control/Status register 2. */ +# define RTC_CLOCKOUT_FREQ 0x0d /* CLKOUT frequency. */ +# define RTC_TIMER_CONTROL 0x0e /* Timer control. */ +# define RTC_TIMER_CNTDOWN 0x0f /* Timer countdown. */ + + /* BCD encoded clock registers. */ +# define RTC_SECONDS 0x02 +# define RTC_MINUTES 0x03 +# define RTC_HOURS 0x04 +# define RTC_DAY_OF_MONTH 0x05 +# define RTC_WEEKDAY 0x06 /* Not coded in BCD! */ +# define RTC_MONTH 0x07 +# define RTC_YEAR 0x08 +# define RTC_MINUTE_ALARM 0x09 +# define RTC_HOUR_ALARM 0x0a +# define RTC_DAY_ALARM 0x0b +# define RTC_WEEKDAY_ALARM 0x0c + +#endif + +#ifdef CONFIG_ETRAX_DS1302 +extern unsigned char ds1302_readreg(int reg); +extern void ds1302_writereg(int reg, unsigned char val); +extern int ds1302_init(void); +# define CMOS_READ(x) ds1302_readreg(x) +# define CMOS_WRITE(val,reg) ds1302_writereg(reg,val) +# define RTC_INIT() ds1302_init() +#elif defined(CONFIG_ETRAX_PCF8563) +extern unsigned char pcf8563_readreg(int reg); +extern void pcf8563_writereg(int reg, unsigned char val); +extern int pcf8563_init(void); +# define CMOS_READ(x) pcf8563_readreg(x) +# define CMOS_WRITE(val,reg) pcf8563_writereg(reg,val) +# define RTC_INIT() pcf8563_init() +#else + /* No RTC configured so we shouldn't try to access any. */ +# define CMOS_READ(x) 42 +# define CMOS_WRITE(x,y) +# define RTC_INIT() (-1) +#endif + +/* + * The struct used to pass data via the following ioctl. Similar to the + * struct tm in , but it needs to be here so that the kernel + * source is self contained, allowing cross-compiles, etc. etc. + */ +struct rtc_time { + int tm_sec; + int tm_min; + int tm_hour; + int tm_mday; + int tm_mon; + int tm_year; + int tm_wday; + int tm_yday; + int tm_isdst; +}; + +/* ioctl() calls that are permitted to the /dev/rtc interface. */ +#define RTC_MAGIC 'p' +/* Read RTC time. */ +#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) +/* Set RTC time. */ +#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) +#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) +/* Voltage low detector */ +#define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int) +/* Clear voltage low information */ +#define RTC_VL_CLR _IO(RTC_MAGIC, 0x14) +#define RTC_MAX_IOCTL 0x14 + +#endif /* __RTC_H__ */ diff --git a/arch/cris/include/asm/scatterlist.h b/arch/cris/include/asm/scatterlist.h new file mode 100644 index 000000000000..faff53ad1f96 --- /dev/null +++ b/arch/cris/include/asm/scatterlist.h @@ -0,0 +1,23 @@ +#ifndef __ASM_CRIS_SCATTERLIST_H +#define __ASM_CRIS_SCATTERLIST_H + +struct scatterlist { +#ifdef CONFIG_DEBUG_SG + unsigned long sg_magic; +#endif + char * address; /* Location data is to be transferred to */ + unsigned int length; + + /* The following is i386 highmem junk - not used by us */ + unsigned long page_link; + unsigned int offset;/* for highmem, page offset */ + +}; + +#define sg_dma_address(sg) ((sg)->address) +#define sg_dma_len(sg) ((sg)->length) +/* i386 junk */ + +#define ISA_DMA_THRESHOLD (0x1fffffff) + +#endif /* !(__ASM_CRIS_SCATTERLIST_H) */ diff --git a/arch/cris/include/asm/sections.h b/arch/cris/include/asm/sections.h new file mode 100644 index 000000000000..2c998ce8967b --- /dev/null +++ b/arch/cris/include/asm/sections.h @@ -0,0 +1,7 @@ +#ifndef _CRIS_SECTIONS_H +#define _CRIS_SECTIONS_H + +/* nothing to see, move along */ +#include + +#endif diff --git a/arch/cris/include/asm/segment.h b/arch/cris/include/asm/segment.h new file mode 100644 index 000000000000..c067513beaaf --- /dev/null +++ b/arch/cris/include/asm/segment.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SEGMENT_H +#define _ASM_SEGMENT_H + +typedef struct { + unsigned long seg; +} mm_segment_t; + +#endif diff --git a/arch/cris/include/asm/sembuf.h b/arch/cris/include/asm/sembuf.h new file mode 100644 index 000000000000..7fed9843796d --- /dev/null +++ b/arch/cris/include/asm/sembuf.h @@ -0,0 +1,25 @@ +#ifndef _CRIS_SEMBUF_H +#define _CRIS_SEMBUF_H + +/* + * The semid64_ds structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct semid64_ds { + struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ + __kernel_time_t sem_otime; /* last semop time */ + unsigned long __unused1; + __kernel_time_t sem_ctime; /* last change time */ + unsigned long __unused2; + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _CRIS_SEMBUF_H */ diff --git a/arch/cris/include/asm/setup.h b/arch/cris/include/asm/setup.h new file mode 100644 index 000000000000..b90728652d1a --- /dev/null +++ b/arch/cris/include/asm/setup.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_SETUP_H +#define _CRIS_SETUP_H + +#define COMMAND_LINE_SIZE 256 + +#endif diff --git a/arch/cris/include/asm/shmbuf.h b/arch/cris/include/asm/shmbuf.h new file mode 100644 index 000000000000..3239e3f000e8 --- /dev/null +++ b/arch/cris/include/asm/shmbuf.h @@ -0,0 +1,42 @@ +#ifndef _CRIS_SHMBUF_H +#define _CRIS_SHMBUF_H + +/* + * The shmid64_ds structure for CRIS architecture (same as for i386) + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct shmid64_ds { + struct ipc64_perm shm_perm; /* operation perms */ + size_t shm_segsz; /* size of segment (bytes) */ + __kernel_time_t shm_atime; /* last attach time */ + unsigned long __unused1; + __kernel_time_t shm_dtime; /* last detach time */ + unsigned long __unused2; + __kernel_time_t shm_ctime; /* last change time */ + unsigned long __unused3; + __kernel_pid_t shm_cpid; /* pid of creator */ + __kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _CRIS_SHMBUF_H */ diff --git a/arch/cris/include/asm/shmparam.h b/arch/cris/include/asm/shmparam.h new file mode 100644 index 000000000000..d29d12270687 --- /dev/null +++ b/arch/cris/include/asm/shmparam.h @@ -0,0 +1,8 @@ +#ifndef _ASM_CRIS_SHMPARAM_H +#define _ASM_CRIS_SHMPARAM_H + +/* same as asm-i386/ version.. */ + +#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ + +#endif /* _ASM_CRIS_SHMPARAM_H */ diff --git a/arch/cris/include/asm/sigcontext.h b/arch/cris/include/asm/sigcontext.h new file mode 100644 index 000000000000..a1d634e120df --- /dev/null +++ b/arch/cris/include/asm/sigcontext.h @@ -0,0 +1,24 @@ +/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +#ifndef _ASM_CRIS_SIGCONTEXT_H +#define _ASM_CRIS_SIGCONTEXT_H + +#include + +/* This struct is saved by setup_frame in signal.c, to keep the current context while + a signal handler is executed. It's restored by sys_sigreturn. + + To keep things simple, we use pt_regs here even though normally you just specify + the list of regs to save. Then we can use copy_from_user on the entire regs instead + of a bunch of get_user's as well... + +*/ + +struct sigcontext { + struct pt_regs regs; /* needs to be first */ + unsigned long oldmask; + unsigned long usp; /* usp before stacking this gunk on it */ +}; + +#endif + diff --git a/arch/cris/include/asm/siginfo.h b/arch/cris/include/asm/siginfo.h new file mode 100644 index 000000000000..c1cd6d16928b --- /dev/null +++ b/arch/cris/include/asm/siginfo.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_SIGINFO_H +#define _CRIS_SIGINFO_H + +#include + +#endif diff --git a/arch/cris/include/asm/signal.h b/arch/cris/include/asm/signal.h new file mode 100644 index 000000000000..349ae682b568 --- /dev/null +++ b/arch/cris/include/asm/signal.h @@ -0,0 +1,163 @@ +#ifndef _ASM_CRIS_SIGNAL_H +#define _ASM_CRIS_SIGNAL_H + +#include + +/* Avoid too many header ordering problems. */ +struct siginfo; + +#ifdef __KERNEL__ +/* Most things should be clean enough to redefine this at will, if care + is taken to make libc match. */ + +#define _NSIG 64 +#define _NSIG_BPW 32 +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +typedef unsigned long old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX _NSIG + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ + +#define SA_NOCLDSTOP 0x00000001u +#define SA_NOCLDWAIT 0x00000002u +#define SA_SIGINFO 0x00000004u +#define SA_ONSTACK 0x08000000u +#define SA_RESTART 0x10000000u +#define SA_NODEFER 0x40000000u +#define SA_RESETHAND 0x80000000u + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +#define SA_RESTORER 0x04000000 + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#include + +#ifdef __KERNEL__ +struct old_sigaction { + __sighandler_t sa_handler; + old_sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +struct sigaction { + __sighandler_t sa_handler; + unsigned long sa_flags; + void (*sa_restorer)(void); + sigset_t sa_mask; /* mask last for extensibility */ +}; + +struct k_sigaction { + struct sigaction sa; +}; +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + +#ifdef __KERNEL__ +#include + +/* here we could define asm-optimized sigaddset, sigdelset etc. operations. + * if we don't, generic ones are used from linux/signal.h + */ +#define ptrace_signal_deliver(regs, cookie) do { } while (0) + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/cris/include/asm/smp.h b/arch/cris/include/asm/smp.h new file mode 100644 index 000000000000..dba33aba3e95 --- /dev/null +++ b/arch/cris/include/asm/smp.h @@ -0,0 +1,11 @@ +#ifndef __ASM_SMP_H +#define __ASM_SMP_H + +#include + +extern cpumask_t phys_cpu_present_map; +extern cpumask_t cpu_possible_map; + +#define raw_smp_processor_id() (current_thread_info()->cpu) + +#endif diff --git a/arch/cris/include/asm/socket.h b/arch/cris/include/asm/socket.h new file mode 100644 index 000000000000..9df0ca82f5de --- /dev/null +++ b/arch/cris/include/asm/socket.h @@ -0,0 +1,61 @@ +#ifndef _ASM_SOCKET_H +#define _ASM_SOCKET_H + +/* almost the same as asm-i386/socket.h */ + +#include + +/* For setsockoptions(2) */ +#define SOL_SOCKET 1 + +#define SO_DEBUG 1 +#define SO_REUSEADDR 2 +#define SO_TYPE 3 +#define SO_ERROR 4 +#define SO_DONTROUTE 5 +#define SO_BROADCAST 6 +#define SO_SNDBUF 7 +#define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 +#define SO_KEEPALIVE 9 +#define SO_OOBINLINE 10 +#define SO_NO_CHECK 11 +#define SO_PRIORITY 12 +#define SO_LINGER 13 +#define SO_BSDCOMPAT 14 +/* To add :#define SO_REUSEPORT 15 */ +#define SO_PASSCRED 16 +#define SO_PEERCRED 17 +#define SO_RCVLOWAT 18 +#define SO_SNDLOWAT 19 +#define SO_RCVTIMEO 20 +#define SO_SNDTIMEO 21 + +/* Security levels - as per NRL IPv6 - don't actually do anything */ +#define SO_SECURITY_AUTHENTICATION 22 +#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 +#define SO_SECURITY_ENCRYPTION_NETWORK 24 + +#define SO_BINDTODEVICE 25 + +/* Socket filtering */ +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 + +#define SO_PEERNAME 28 +#define SO_TIMESTAMP 29 +#define SCM_TIMESTAMP SO_TIMESTAMP + +#define SO_ACCEPTCONN 30 + +#define SO_PEERSEC 31 +#define SO_PASSSEC 34 +#define SO_TIMESTAMPNS 35 +#define SCM_TIMESTAMPNS SO_TIMESTAMPNS + +#define SO_MARK 36 + +#endif /* _ASM_SOCKET_H */ + + diff --git a/arch/cris/include/asm/sockios.h b/arch/cris/include/asm/sockios.h new file mode 100644 index 000000000000..cfe7bfecf599 --- /dev/null +++ b/arch/cris/include/asm/sockios.h @@ -0,0 +1,13 @@ +#ifndef __ARCH_CRIS_SOCKIOS__ +#define __ARCH_CRIS_SOCKIOS__ + +/* Socket-level I/O control calls. */ +#define FIOSETOWN 0x8901 +#define SIOCSPGRP 0x8902 +#define FIOGETOWN 0x8903 +#define SIOCGPGRP 0x8904 +#define SIOCATMARK 0x8905 +#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ +#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ + +#endif diff --git a/arch/cris/include/asm/spinlock.h b/arch/cris/include/asm/spinlock.h new file mode 100644 index 000000000000..ed816b57face --- /dev/null +++ b/arch/cris/include/asm/spinlock.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/stat.h b/arch/cris/include/asm/stat.h new file mode 100644 index 000000000000..9e558cc3c43b --- /dev/null +++ b/arch/cris/include/asm/stat.h @@ -0,0 +1,81 @@ +#ifndef _CRIS_STAT_H +#define _CRIS_STAT_H + +/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in + the kernel if necessary. */ + +struct __old_kernel_stat { + unsigned short st_dev; + unsigned short st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned long st_size; + unsigned long st_atime; + unsigned long st_mtime; + unsigned long st_ctime; +}; + +#define STAT_HAVE_NSEC 1 + +struct stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +struct stat64 { + unsigned long long st_dev; + unsigned char __pad0[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + unsigned long __st_ino; + + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad3[4]; + + long long st_size; + unsigned long st_blksize; + + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ + unsigned long __pad4; /* future possible st_blocks high bits */ + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned long st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ + + unsigned long long st_ino; +}; + +#endif diff --git a/arch/cris/include/asm/statfs.h b/arch/cris/include/asm/statfs.h new file mode 100644 index 000000000000..fdaf921844bc --- /dev/null +++ b/arch/cris/include/asm/statfs.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_STATFS_H +#define _CRIS_STATFS_H + +#include + +#endif diff --git a/arch/cris/include/asm/string.h b/arch/cris/include/asm/string.h new file mode 100644 index 000000000000..691190e99a27 --- /dev/null +++ b/arch/cris/include/asm/string.h @@ -0,0 +1,14 @@ +#ifndef _ASM_CRIS_STRING_H +#define _ASM_CRIS_STRING_H + +/* the optimized memcpy is in arch/cris/lib/string.c */ + +#define __HAVE_ARCH_MEMCPY +extern void *memcpy(void *, const void *, size_t); + +/* New and improved. In arch/cris/lib/memset.c */ + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *, int, size_t); + +#endif diff --git a/arch/cris/include/asm/sync_serial.h b/arch/cris/include/asm/sync_serial.h new file mode 100644 index 000000000000..d87c24df2b38 --- /dev/null +++ b/arch/cris/include/asm/sync_serial.h @@ -0,0 +1,107 @@ +/* + * ioctl defines for synchronous serial port driver + * + * Copyright (c) 2001-2003 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef SYNC_SERIAL_H +#define SYNC_SERIAL_H + +#include + +#define SSP_SPEED _IOR('S', 0, unsigned int) +#define SSP_MODE _IOR('S', 1, unsigned int) +#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) +#define SSP_IPOLARITY _IOR('S', 3, unsigned int) +#define SSP_OPOLARITY _IOR('S', 4, unsigned int) +#define SSP_SPI _IOR('S', 5, unsigned int) +#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) + +/* Values for SSP_SPEED */ +#define SSP150 0 +#define SSP300 1 +#define SSP600 2 +#define SSP1200 3 +#define SSP2400 4 +#define SSP4800 5 +#define SSP9600 6 +#define SSP19200 7 +#define SSP28800 8 +#define SSP57600 9 +#define SSP115200 10 +#define SSP230400 11 +#define SSP460800 12 +#define SSP921600 13 +#define SSP3125000 14 +#define CODEC 15 + +#define FREQ_4MHz 0 +#define FREQ_2MHz 1 +#define FREQ_1MHz 2 +#define FREQ_512kHz 3 +#define FREQ_256kHz 4 +#define FREQ_128kHz 5 +#define FREQ_64kHz 6 +#define FREQ_32kHz 7 + +/* Used by application to set CODEC divider, word rate and frame rate */ +#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28)) + +/* Used by driver to extract speed */ +#define GET_SPEED(x) (x & 0xff) +#define GET_FREQ(x) ((x & 0xff00) >> 8) +#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) +#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) + +/* Values for SSP_MODE */ +#define MASTER_OUTPUT 0 +#define SLAVE_OUTPUT 1 +#define MASTER_INPUT 2 +#define SLAVE_INPUT 3 +#define MASTER_BIDIR 4 +#define SLAVE_BIDIR 5 + +/* Values for SSP_FRAME_SYNC */ +#define NORMAL_SYNC 1 +#define EARLY_SYNC 2 +#define SECOND_WORD_SYNC 0x40000 + +#define BIT_SYNC 4 +#define WORD_SYNC 8 +#define EXTENDED_SYNC 0x10 + +#define SYNC_OFF 0x20 +#define SYNC_ON 0x40 +#define WORD_SIZE_8 0x80 +#define WORD_SIZE_12 0x100 +#define WORD_SIZE_16 0x200 +#define WORD_SIZE_24 0x400 +#define WORD_SIZE_32 0x800 +#define BIT_ORDER_LSB 0x1000 +#define BIT_ORDER_MSB 0x2000 +#define FLOW_CONTROL_ENABLE 0x4000 +#define FLOW_CONTROL_DISABLE 0x8000 +#define CLOCK_GATED 0x10000 +#define CLOCK_NOT_GATED 0x20000 + +/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ +#define CLOCK_NORMAL 1 +#define CLOCK_INVERT 2 +#define CLOCK_INEGEDGE CLOCK_NORMAL +#define CLOCK_IPOSEDGE CLOCK_INVERT +#define FRAME_NORMAL 4 +#define FRAME_INVERT 8 +#define STATUS_NORMAL 0x10 +#define STATUS_INVERT 0x20 + +/* Values for SSP_SPI */ +#define SPI_MASTER 0 +#define SPI_SLAVE 1 + +/* Values for SSP_INBUFCHUNK */ +/* plain integer with the size of DMA chunks */ + +#endif diff --git a/arch/cris/include/asm/system.h b/arch/cris/include/asm/system.h new file mode 100644 index 000000000000..8657b084a922 --- /dev/null +++ b/arch/cris/include/asm/system.h @@ -0,0 +1,88 @@ +#ifndef __ASM_CRIS_SYSTEM_H +#define __ASM_CRIS_SYSTEM_H + +#include + +/* the switch_to macro calls resume, an asm function in entry.S which does the actual + * task switching. + */ + +extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); +#define switch_to(prev,next,last) last = resume(prev,next, \ + (int)&((struct task_struct *)0)->thread) + +#define barrier() __asm__ __volatile__("": : :"memory") +#define mb() barrier() +#define rmb() mb() +#define wmb() mb() +#define read_barrier_depends() do { } while(0) +#define set_mb(var, value) do { var = value; mb(); } while (0) + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) +#endif + +#define iret() + +/* + * disable hlt during certain critical i/o operations + */ +#define HAVE_DISABLE_HLT +void disable_hlt(void); +void enable_hlt(void); + +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + /* since Etrax doesn't have any atomic xchg instructions, we need to disable + irq's (if enabled) and do it with move.d's */ + unsigned long flags,temp; + local_irq_save(flags); /* save flags, including irq enable bit and shut off irqs */ + switch (size) { + case 1: + *((unsigned char *)&temp) = x; + x = *(unsigned char *)ptr; + *(unsigned char *)ptr = *((unsigned char *)&temp); + break; + case 2: + *((unsigned short *)&temp) = x; + x = *(unsigned short *)ptr; + *(unsigned short *)ptr = *((unsigned short *)&temp); + break; + case 4: + temp = x; + x = *(unsigned long *)ptr; + *(unsigned long *)ptr = temp; + break; + } + local_irq_restore(flags); /* restore irq enable bit */ + return x; +} + +#include + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ + (unsigned long)(n), sizeof(*(ptr)))) +#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) + +#ifndef CONFIG_SMP +#include +#endif + +#define arch_align_stack(x) (x) + +void default_idle(void); + +#endif diff --git a/arch/cris/include/asm/termbits.h b/arch/cris/include/asm/termbits.h new file mode 100644 index 000000000000..66e1a7492a0c --- /dev/null +++ b/arch/cris/include/asm/termbits.h @@ -0,0 +1,234 @@ +/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +#ifndef __ARCH_ETRAX100_TERMBITS_H__ +#define __ARCH_ETRAX100_TERMBITS_H__ + +#include + +typedef unsigned char cc_t; +typedef unsigned int speed_t; +typedef unsigned int tcflag_t; + +#define NCCS 19 +struct termios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +struct ktermios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +/* c_cc characters */ +#define VINTR 0 +#define VQUIT 1 +#define VERASE 2 +#define VKILL 3 +#define VEOF 4 +#define VTIME 5 +#define VMIN 6 +#define VSWTC 7 +#define VSTART 8 +#define VSTOP 9 +#define VSUSP 10 +#define VEOL 11 +#define VREPRINT 12 +#define VDISCARD 13 +#define VWERASE 14 +#define VLNEXT 15 +#define VEOL2 16 + +/* c_iflag bits */ +#define IGNBRK 0000001 +#define BRKINT 0000002 +#define IGNPAR 0000004 +#define PARMRK 0000010 +#define INPCK 0000020 +#define ISTRIP 0000040 +#define INLCR 0000100 +#define IGNCR 0000200 +#define ICRNL 0000400 +#define IUCLC 0001000 +#define IXON 0002000 +#define IXANY 0004000 +#define IXOFF 0010000 +#define IMAXBEL 0020000 +#define IUTF8 0040000 + +/* c_oflag bits */ +#define OPOST 0000001 +#define OLCUC 0000002 +#define ONLCR 0000004 +#define OCRNL 0000010 +#define ONOCR 0000020 +#define ONLRET 0000040 +#define OFILL 0000100 +#define OFDEL 0000200 +#define NLDLY 0000400 +#define NL0 0000000 +#define NL1 0000400 +#define CRDLY 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 +#define TABDLY 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 +#define BSDLY 0020000 +#define BS0 0000000 +#define BS1 0020000 +#define VTDLY 0040000 +#define VT0 0000000 +#define VT1 0040000 +#define FFDLY 0100000 +#define FF0 0000000 +#define FF1 0100000 + +/* c_cflag bit meaning */ +/* + * 3 2 1 + * 10 987 654 321 098 765 432 109 876 543 210 + * | | ||| CBAUD + * obaud + * + * ||CSIZE + * + * |CSTOP + * |CREAD + * |CPARENB + * + * |CPARODD + * |HUPCL + * |CLOCAL + * |CBAUDEX + * 10 987 654 321 098 765 432 109 876 543 210 + * | || || CIBAUD, IBSHIFT=16 + * ibaud + * |CMSPAR + * | CRTSCTS + * x x xxx xxx x x xx Free bits + */ + +#define CBAUD 0010017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 +#define EXTA B19200 +#define EXTB B38400 +#define CSIZE 0000060 +#define CS5 0000000 +#define CS6 0000020 +#define CS7 0000040 +#define CS8 0000060 +#define CSTOPB 0000100 +#define CREAD 0000200 +#define PARENB 0000400 +#define PARODD 0001000 +#define HUPCL 0002000 +#define CLOCAL 0004000 +#define CBAUDEX 0010000 +#define BOTHER 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 + +/* Unsupported rates, but needed to avoid compile error. */ +#define B500000 0010005 +#define B576000 0010006 +#define B1000000 0010010 +#define B1152000 0010011 +#define B1500000 0010012 +#define B2000000 0010013 +#define B2500000 0010014 +#define B3000000 0010015 +#define B3500000 0010016 +#define B4000000 0010017 + +/* etrax supports these additional three baud rates */ +#define B921600 0010005 +#define B1843200 0010006 +#define B6250000 0010007 +/* ETRAX FS supports this as well */ +#define B12500000 0010010 +#define CIBAUD 002003600000 /* input baud rate (used in v32) */ +/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX + * shifted left IBSHIFT bits. + */ +#define IBSHIFT 16 +#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ +#define CRTSCTS 020000000000 /* flow control */ + +/* c_lflag bits */ +#define ISIG 0000001 +#define ICANON 0000002 +#define XCASE 0000004 +#define ECHO 0000010 +#define ECHOE 0000020 +#define ECHOK 0000040 +#define ECHONL 0000100 +#define NOFLSH 0000200 +#define TOSTOP 0000400 +#define ECHOCTL 0001000 +#define ECHOPRT 0002000 +#define ECHOKE 0004000 +#define FLUSHO 0010000 +#define PENDIN 0040000 +#define IEXTEN 0100000 + +/* tcflow() and TCXONC use these */ +#define TCOOFF 0 +#define TCOON 1 +#define TCIOFF 2 +#define TCION 3 + +/* tcflush() and TCFLSH use these */ +#define TCIFLUSH 0 +#define TCOFLUSH 1 +#define TCIOFLUSH 2 + +/* tcsetattr uses these */ +#define TCSANOW 0 +#define TCSADRAIN 1 +#define TCSAFLUSH 2 + +#endif diff --git a/arch/cris/include/asm/termios.h b/arch/cris/include/asm/termios.h new file mode 100644 index 000000000000..b0124e6c2e41 --- /dev/null +++ b/arch/cris/include/asm/termios.h @@ -0,0 +1,91 @@ +#ifndef _CRIS_TERMIOS_H +#define _CRIS_TERMIOS_H + +#include +#include +#include + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define NCC 8 +struct termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[NCC]; /* control characters */ +}; + +/* modem lines */ +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ + +#ifdef __KERNEL__ + +/* intr=^C quit=^\ erase=del kill=^U + eof=^D vtime=\0 vmin=\1 sxtc=\0 + start=^Q stop=^S susp=^Z eol=\0 + reprint=^R discard=^U werase=^W lnext=^V + eol2=\0 +*/ +#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" + +/* + * Translate a "termio" structure into a "termios". Ugh. + */ +#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ + unsigned short __tmp; \ + get_user(__tmp,&(termio)->x); \ + *(unsigned short *) &(termios)->x = __tmp; \ +} + +#define user_termio_to_kernel_termios(termios, termio) \ +({ \ + SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ + copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ +}) + +/* + * Translate a "termios" structure into a "termio". Ugh. + */ +#define kernel_termios_to_user_termio(termio, termios) \ +({ \ + put_user((termios)->c_iflag, &(termio)->c_iflag); \ + put_user((termios)->c_oflag, &(termio)->c_oflag); \ + put_user((termios)->c_cflag, &(termio)->c_cflag); \ + put_user((termios)->c_lflag, &(termio)->c_lflag); \ + put_user((termios)->c_line, &(termio)->c_line); \ + copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ +}) + +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) + +#endif /* __KERNEL__ */ + +#endif /* _CRIS_TERMIOS_H */ diff --git a/arch/cris/include/asm/thread_info.h b/arch/cris/include/asm/thread_info.h new file mode 100644 index 000000000000..bc5b2935ca53 --- /dev/null +++ b/arch/cris/include/asm/thread_info.h @@ -0,0 +1,106 @@ +/* thread_info.h: CRIS low-level thread information + * + * Copyright (C) 2002 David Howells (dhowells@redhat.com) + * - Incorporating suggestions made by Linus Torvalds and Dave Miller + * + * CRIS port by Axis Communications + */ + +#ifndef _ASM_THREAD_INFO_H +#define _ASM_THREAD_INFO_H + +#ifdef __KERNEL__ + +#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR + +#ifndef __ASSEMBLY__ +#include +#include +#include +#include +#endif + + +/* + * low level task data that entry.S needs immediate access to + * - this struct should fit entirely inside of one cache line + * - this struct shares the supervisor stack pages + * - if the contents of this structure are changed, the assembly constants must also be changed + */ +#ifndef __ASSEMBLY__ +struct thread_info { + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + unsigned long flags; /* low level flags */ + __u32 cpu; /* current CPU */ + int preempt_count; /* 0 => preemptable, <0 => BUG */ + __u32 tls; /* TLS for this thread */ + + mm_segment_t addr_limit; /* thread address space: + 0-0xBFFFFFFF for user-thead + 0-0xFFFFFFFF for kernel-thread + */ + struct restart_block restart_block; + __u8 supervisor_stack[0]; +}; + +#endif + +#define PREEMPT_ACTIVE 0x10000000 + +/* + * macros/functions for gaining access to the thread information structure + * + * preempt_count needs to be 1 initially, until the scheduler is functional. + */ +#ifndef __ASSEMBLY__ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = 1, \ + .addr_limit = KERNEL_DS, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) + +/* thread information allocation */ +#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) +#define free_thread_info(ti) free_pages((unsigned long) (ti), 1) + +#endif /* !__ASSEMBLY__ */ + +/* + * thread information flags + * - these are process state flags that various assembly files may need to access + * - pending work-to-be-done flags are in LSW + * - other flags in MSW + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ +#define TIF_SIGPENDING 2 /* signal pending */ +#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ +#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ +#define TIF_MEMDIE 17 +#define TIF_FREEZE 18 /* is freezing for suspend */ + +#define _TIF_SYSCALL_TRACE (1< + +/* + * We don't have a cycle-counter.. but we do not support SMP anyway where this is + * used so it does not matter. + */ + +typedef unsigned long long cycles_t; + +static inline cycles_t get_cycles(void) +{ + return 0; +} + +#endif diff --git a/arch/cris/include/asm/tlb.h b/arch/cris/include/asm/tlb.h new file mode 100644 index 000000000000..77384ea2f29d --- /dev/null +++ b/arch/cris/include/asm/tlb.h @@ -0,0 +1,19 @@ +#ifndef _CRIS_TLB_H +#define _CRIS_TLB_H + +#include + +#include + +/* + * cris doesn't need any special per-pte or + * per-vma handling.. + */ +#define tlb_start_vma(tlb, vma) do { } while (0) +#define tlb_end_vma(tlb, vma) do { } while (0) +#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) + +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) +#include + +#endif diff --git a/arch/cris/include/asm/tlbflush.h b/arch/cris/include/asm/tlbflush.h new file mode 100644 index 000000000000..20697e7ef4f2 --- /dev/null +++ b/arch/cris/include/asm/tlbflush.h @@ -0,0 +1,48 @@ +#ifndef _CRIS_TLBFLUSH_H +#define _CRIS_TLBFLUSH_H + +#include +#include +#include +#include + +/* + * TLB flushing (implemented in arch/cris/mm/tlb.c): + * + * - flush_tlb() flushes the current mm struct TLBs + * - flush_tlb_all() flushes all processes TLBs + * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(mm, start, end) flushes a range of pages + * + */ + +extern void __flush_tlb_all(void); +extern void __flush_tlb_mm(struct mm_struct *mm); +extern void __flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr); + +#ifdef CONFIG_SMP +extern void flush_tlb_all(void); +extern void flush_tlb_mm(struct mm_struct *mm); +extern void flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr); +#else +#define flush_tlb_all __flush_tlb_all +#define flush_tlb_mm __flush_tlb_mm +#define flush_tlb_page __flush_tlb_page +#endif + +static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) +{ + flush_tlb_mm(vma->vm_mm); +} + +static inline void flush_tlb(void) +{ + flush_tlb_mm(current->mm); +} + +#define flush_tlb_kernel_range(start, end) flush_tlb_all() + +#endif /* _CRIS_TLBFLUSH_H */ diff --git a/arch/cris/include/asm/topology.h b/arch/cris/include/asm/topology.h new file mode 100644 index 000000000000..2ac613d32a89 --- /dev/null +++ b/arch/cris/include/asm/topology.h @@ -0,0 +1,6 @@ +#ifndef _ASM_CRIS_TOPOLOGY_H +#define _ASM_CRIS_TOPOLOGY_H + +#include + +#endif /* _ASM_CRIS_TOPOLOGY_H */ diff --git a/arch/cris/include/asm/types.h b/arch/cris/include/asm/types.h new file mode 100644 index 000000000000..5790262cbe8a --- /dev/null +++ b/arch/cris/include/asm/types.h @@ -0,0 +1,30 @@ +#ifndef _ETRAX_TYPES_H +#define _ETRAX_TYPES_H + +#include + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + +/* Dma addresses are 32-bits wide, just like our other addresses. */ + +typedef u32 dma_addr_t; +typedef u32 dma64_addr_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/cris/include/asm/uaccess.h b/arch/cris/include/asm/uaccess.h new file mode 100644 index 000000000000..914540801c5e --- /dev/null +++ b/arch/cris/include/asm/uaccess.h @@ -0,0 +1,404 @@ +/* + * Authors: Bjorn Wesen (bjornw@axis.com) + * Hans-Peter Nilsson (hp@axis.com) + */ + +/* Asm:s have been tweaked (within the domain of correctness) to give + satisfactory results for "gcc version 2.96 20000427 (experimental)". + + Check regularly... + + Register $r9 is chosen for temporaries, being a call-clobbered register + first in line to be used (notably for local blocks), not colliding with + parameter registers. */ + +#ifndef _CRIS_UACCESS_H +#define _CRIS_UACCESS_H + +#ifndef __ASSEMBLY__ +#include +#include +#include +#include + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + * + * For historical reasons, these macros are grossly misnamed. + */ + +#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) + +/* addr_limit is the maximum accessible address for the task. we misuse + * the KERNEL_DS and USER_DS values to both assign and compare the + * addr_limit values through the equally misnamed get/set_fs macros. + * (see above) + */ + +#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) +#define USER_DS MAKE_MM_SEG(TASK_SIZE) + +#define get_ds() (KERNEL_DS) +#define get_fs() (current_thread_info()->addr_limit) +#define set_fs(x) (current_thread_info()->addr_limit = (x)) + +#define segment_eq(a,b) ((a).seg == (b).seg) + +#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) +#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size))) +#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size))) +#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size)) + +#include + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry +{ + unsigned long insn, fixup; +}; + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + * + * This gets kind of ugly. We want to return _two_ values in "get_user()" + * and yet we don't want to do any pointers, because that is too much + * of a performance impact. Thus we have a few rather ugly macros here, + * and hide all the ugliness from the user. + * + * The "__xxx" versions of the user access functions are versions that + * do not verify the address space, that must have been done previously + * with a separate "access_ok()" call (this is used when we do multiple + * accesses to the same area of user memory). + * + * As we use the same address space for kernel and user data on + * CRIS, we can just do these as direct assignments. (Of course, the + * exception handling means that it's no longer "just"...) + */ +#define get_user(x,ptr) \ + __get_user_check((x),(ptr),sizeof(*(ptr))) +#define put_user(x,ptr) \ + __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) + +#define __get_user(x,ptr) \ + __get_user_nocheck((x),(ptr),sizeof(*(ptr))) +#define __put_user(x,ptr) \ + __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) + +extern long __put_user_bad(void); + +#define __put_user_size(x,ptr,size,retval) \ +do { \ + retval = 0; \ + switch (size) { \ + case 1: __put_user_asm(x,ptr,retval,"move.b"); break; \ + case 2: __put_user_asm(x,ptr,retval,"move.w"); break; \ + case 4: __put_user_asm(x,ptr,retval,"move.d"); break; \ + case 8: __put_user_asm_64(x,ptr,retval); break; \ + default: __put_user_bad(); \ + } \ +} while (0) + +#define __get_user_size(x,ptr,size,retval) \ +do { \ + retval = 0; \ + switch (size) { \ + case 1: __get_user_asm(x,ptr,retval,"move.b"); break; \ + case 2: __get_user_asm(x,ptr,retval,"move.w"); break; \ + case 4: __get_user_asm(x,ptr,retval,"move.d"); break; \ + case 8: __get_user_asm_64(x,ptr,retval); break; \ + default: (x) = __get_user_bad(); \ + } \ +} while (0) + +#define __put_user_nocheck(x,ptr,size) \ +({ \ + long __pu_err; \ + __put_user_size((x),(ptr),(size),__pu_err); \ + __pu_err; \ +}) + +#define __put_user_check(x,ptr,size) \ +({ \ + long __pu_err = -EFAULT; \ + __typeof__(*(ptr)) *__pu_addr = (ptr); \ + if (access_ok(VERIFY_WRITE,__pu_addr,size)) \ + __put_user_size((x),__pu_addr,(size),__pu_err); \ + __pu_err; \ +}) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct *)(x)) + + + +#define __get_user_nocheck(x,ptr,size) \ +({ \ + long __gu_err, __gu_val; \ + __get_user_size(__gu_val,(ptr),(size),__gu_err); \ + (x) = (__typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x,ptr,size) \ +({ \ + long __gu_err = -EFAULT, __gu_val = 0; \ + const __typeof__(*(ptr)) *__gu_addr = (ptr); \ + if (access_ok(VERIFY_READ,__gu_addr,size)) \ + __get_user_size(__gu_val,__gu_addr,(size),__gu_err); \ + (x) = (__typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +extern long __get_user_bad(void); + +/* More complex functions. Most are inline, but some call functions that + live in lib/usercopy.c */ + +extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __copy_user_zeroing(void *to, const void __user *from, unsigned long n); +extern unsigned long __do_clear_user(void __user *to, unsigned long n); + +static inline unsigned long +__generic_copy_to_user(void __user *to, const void *from, unsigned long n) +{ + if (access_ok(VERIFY_WRITE, to, n)) + return __copy_user(to,from,n); + return n; +} + +static inline unsigned long +__generic_copy_from_user(void *to, const void __user *from, unsigned long n) +{ + if (access_ok(VERIFY_READ, from, n)) + return __copy_user_zeroing(to,from,n); + return n; +} + +static inline unsigned long +__generic_clear_user(void __user *to, unsigned long n) +{ + if (access_ok(VERIFY_WRITE, to, n)) + return __do_clear_user(to,n); + return n; +} + +static inline long +__strncpy_from_user(char *dst, const char __user *src, long count) +{ + return __do_strncpy_from_user(dst, src, count); +} + +static inline long +strncpy_from_user(char *dst, const char __user *src, long count) +{ + long res = -EFAULT; + if (access_ok(VERIFY_READ, src, 1)) + res = __do_strncpy_from_user(dst, src, count); + return res; +} + + +/* Note that these expand awfully if made into switch constructs, so + don't do that. */ + +static inline unsigned long +__constant_copy_from_user(void *to, const void __user *from, unsigned long n) +{ + unsigned long ret = 0; + if (n == 0) + ; + else if (n == 1) + __asm_copy_from_user_1(to, from, ret); + else if (n == 2) + __asm_copy_from_user_2(to, from, ret); + else if (n == 3) + __asm_copy_from_user_3(to, from, ret); + else if (n == 4) + __asm_copy_from_user_4(to, from, ret); + else if (n == 5) + __asm_copy_from_user_5(to, from, ret); + else if (n == 6) + __asm_copy_from_user_6(to, from, ret); + else if (n == 7) + __asm_copy_from_user_7(to, from, ret); + else if (n == 8) + __asm_copy_from_user_8(to, from, ret); + else if (n == 9) + __asm_copy_from_user_9(to, from, ret); + else if (n == 10) + __asm_copy_from_user_10(to, from, ret); + else if (n == 11) + __asm_copy_from_user_11(to, from, ret); + else if (n == 12) + __asm_copy_from_user_12(to, from, ret); + else if (n == 13) + __asm_copy_from_user_13(to, from, ret); + else if (n == 14) + __asm_copy_from_user_14(to, from, ret); + else if (n == 15) + __asm_copy_from_user_15(to, from, ret); + else if (n == 16) + __asm_copy_from_user_16(to, from, ret); + else if (n == 20) + __asm_copy_from_user_20(to, from, ret); + else if (n == 24) + __asm_copy_from_user_24(to, from, ret); + else + ret = __generic_copy_from_user(to, from, n); + + return ret; +} + +/* Ditto, don't make a switch out of this. */ + +static inline unsigned long +__constant_copy_to_user(void __user *to, const void *from, unsigned long n) +{ + unsigned long ret = 0; + if (n == 0) + ; + else if (n == 1) + __asm_copy_to_user_1(to, from, ret); + else if (n == 2) + __asm_copy_to_user_2(to, from, ret); + else if (n == 3) + __asm_copy_to_user_3(to, from, ret); + else if (n == 4) + __asm_copy_to_user_4(to, from, ret); + else if (n == 5) + __asm_copy_to_user_5(to, from, ret); + else if (n == 6) + __asm_copy_to_user_6(to, from, ret); + else if (n == 7) + __asm_copy_to_user_7(to, from, ret); + else if (n == 8) + __asm_copy_to_user_8(to, from, ret); + else if (n == 9) + __asm_copy_to_user_9(to, from, ret); + else if (n == 10) + __asm_copy_to_user_10(to, from, ret); + else if (n == 11) + __asm_copy_to_user_11(to, from, ret); + else if (n == 12) + __asm_copy_to_user_12(to, from, ret); + else if (n == 13) + __asm_copy_to_user_13(to, from, ret); + else if (n == 14) + __asm_copy_to_user_14(to, from, ret); + else if (n == 15) + __asm_copy_to_user_15(to, from, ret); + else if (n == 16) + __asm_copy_to_user_16(to, from, ret); + else if (n == 20) + __asm_copy_to_user_20(to, from, ret); + else if (n == 24) + __asm_copy_to_user_24(to, from, ret); + else + ret = __generic_copy_to_user(to, from, n); + + return ret; +} + +/* No switch, please. */ + +static inline unsigned long +__constant_clear_user(void __user *to, unsigned long n) +{ + unsigned long ret = 0; + if (n == 0) + ; + else if (n == 1) + __asm_clear_1(to, ret); + else if (n == 2) + __asm_clear_2(to, ret); + else if (n == 3) + __asm_clear_3(to, ret); + else if (n == 4) + __asm_clear_4(to, ret); + else if (n == 8) + __asm_clear_8(to, ret); + else if (n == 12) + __asm_clear_12(to, ret); + else if (n == 16) + __asm_clear_16(to, ret); + else if (n == 20) + __asm_clear_20(to, ret); + else if (n == 24) + __asm_clear_24(to, ret); + else + ret = __generic_clear_user(to, n); + + return ret; +} + + +#define clear_user(to, n) \ +(__builtin_constant_p(n) ? \ + __constant_clear_user(to, n) : \ + __generic_clear_user(to, n)) + +#define copy_from_user(to, from, n) \ +(__builtin_constant_p(n) ? \ + __constant_copy_from_user(to, from, n) : \ + __generic_copy_from_user(to, from, n)) + +#define copy_to_user(to, from, n) \ +(__builtin_constant_p(n) ? \ + __constant_copy_to_user(to, from, n) : \ + __generic_copy_to_user(to, from, n)) + +/* We let the __ versions of copy_from/to_user inline, because they're often + * used in fast paths and have only a small space overhead. + */ + +static inline unsigned long +__generic_copy_from_user_nocheck(void *to, const void __user *from, + unsigned long n) +{ + return __copy_user_zeroing(to,from,n); +} + +static inline unsigned long +__generic_copy_to_user_nocheck(void __user *to, const void *from, + unsigned long n) +{ + return __copy_user(to,from,n); +} + +static inline unsigned long +__generic_clear_user_nocheck(void __user *to, unsigned long n) +{ + return __do_clear_user(to,n); +} + +/* without checking */ + +#define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n)) +#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n)) +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user +#define __clear_user(to,n) __generic_clear_user_nocheck((to),(n)) + +#define strlen_user(str) strnlen_user((str), 0x7ffffffe) + +#endif /* __ASSEMBLY__ */ + +#endif /* _CRIS_UACCESS_H */ diff --git a/arch/cris/include/asm/ucontext.h b/arch/cris/include/asm/ucontext.h new file mode 100644 index 000000000000..eed6ad5eb3f2 --- /dev/null +++ b/arch/cris/include/asm/ucontext.h @@ -0,0 +1,12 @@ +#ifndef _ASM_CRIS_UCONTEXT_H +#define _ASM_CRIS_UCONTEXT_H + +struct ucontext { + unsigned long uc_flags; + struct ucontext *uc_link; + stack_t uc_stack; + struct sigcontext uc_mcontext; + sigset_t uc_sigmask; /* mask last for extensibility */ +}; + +#endif /* !_ASM_CRIS_UCONTEXT_H */ diff --git a/arch/cris/include/asm/unaligned.h b/arch/cris/include/asm/unaligned.h new file mode 100644 index 000000000000..7b3f3fec567c --- /dev/null +++ b/arch/cris/include/asm/unaligned.h @@ -0,0 +1,13 @@ +#ifndef _ASM_CRIS_UNALIGNED_H +#define _ASM_CRIS_UNALIGNED_H + +/* + * CRIS can do unaligned accesses itself. + */ +#include +#include + +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le + +#endif /* _ASM_CRIS_UNALIGNED_H */ diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h new file mode 100644 index 000000000000..235d076379d5 --- /dev/null +++ b/arch/cris/include/asm/unistd.h @@ -0,0 +1,374 @@ +#ifndef _ASM_CRIS_UNISTD_H_ +#define _ASM_CRIS_UNISTD_H_ + +/* + * This file contains the system call numbers, and stub macros for libc. + */ + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl 110 +#define __NR_vhangup 111 +#define __NR_idle 112 +#define __NR_vm86 113 +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_modify_ldt 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 + +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_getpmsg 188 /* some people actually want streams */ +#define __NR_putpmsg 189 /* some people actually want streams */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_mincore 218 +#define __NR_madvise 219 +#define __NR_getdents64 220 +#define __NR_fcntl64 221 +/* 223 is unused */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_set_thread_area 243 +#define __NR_get_thread_area 244 +#define __NR_io_setup 245 +#define __NR_io_destroy 246 +#define __NR_io_getevents 247 +#define __NR_io_submit 248 +#define __NR_io_cancel 249 +#define __NR_fadvise64 250 +/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ +#define __NR_exit_group 252 +#define __NR_lookup_dcookie 253 +#define __NR_epoll_create 254 +#define __NR_epoll_ctl 255 +#define __NR_epoll_wait 256 +#define __NR_remap_file_pages 257 +#define __NR_set_tid_address 258 +#define __NR_timer_create 259 +#define __NR_timer_settime (__NR_timer_create+1) +#define __NR_timer_gettime (__NR_timer_create+2) +#define __NR_timer_getoverrun (__NR_timer_create+3) +#define __NR_timer_delete (__NR_timer_create+4) +#define __NR_clock_settime (__NR_timer_create+5) +#define __NR_clock_gettime (__NR_timer_create+6) +#define __NR_clock_getres (__NR_timer_create+7) +#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_statfs64 268 +#define __NR_fstatfs64 269 +#define __NR_tgkill 270 +#define __NR_utimes 271 +#define __NR_fadvise64_64 272 +#define __NR_vserver 273 +#define __NR_mbind 274 +#define __NR_get_mempolicy 275 +#define __NR_set_mempolicy 276 +#define __NR_mq_open 277 +#define __NR_mq_unlink (__NR_mq_open+1) +#define __NR_mq_timedsend (__NR_mq_open+2) +#define __NR_mq_timedreceive (__NR_mq_open+3) +#define __NR_mq_notify (__NR_mq_open+4) +#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_kexec_load 283 +#define __NR_waitid 284 +/* #define __NR_sys_setaltroot 285 */ +#define __NR_add_key 286 +#define __NR_request_key 287 +#define __NR_keyctl 288 +#define __NR_ioprio_set 289 +#define __NR_ioprio_get 290 +#define __NR_inotify_init 291 +#define __NR_inotify_add_watch 292 +#define __NR_inotify_rm_watch 293 +#define __NR_migrate_pages 294 +#define __NR_openat 295 +#define __NR_mkdirat 296 +#define __NR_mknodat 297 +#define __NR_fchownat 298 +#define __NR_futimesat 299 +#define __NR_fstatat64 300 +#define __NR_unlinkat 301 +#define __NR_renameat 302 +#define __NR_linkat 303 +#define __NR_symlinkat 304 +#define __NR_readlinkat 305 +#define __NR_fchmodat 306 +#define __NR_faccessat 307 +#define __NR_pselect6 308 +#define __NR_ppoll 309 +#define __NR_unshare 310 +#define __NR_set_robust_list 311 +#define __NR_get_robust_list 312 +#define __NR_splice 313 +#define __NR_sync_file_range 314 +#define __NR_tee 315 +#define __NR_vmsplice 316 +#define __NR_move_pages 317 +#define __NR_getcpu 318 +#define __NR_epoll_pwait 319 +#define __NR_utimensat 320 +#define __NR_signalfd 321 +#define __NR_timerfd_create 322 +#define __NR_eventfd 323 +#define __NR_fallocate 324 +#define __NR_timerfd_settime 325 +#define __NR_timerfd_gettime 326 + +#ifdef __KERNEL__ + +#define NR_syscalls 327 + +#include + +#define __ARCH_WANT_IPC_PARSE_VERSION +#define __ARCH_WANT_OLD_READDIR +#define __ARCH_WANT_OLD_STAT +#define __ARCH_WANT_STAT64 +#define __ARCH_WANT_SYS_ALARM +#define __ARCH_WANT_SYS_GETHOSTNAME +#define __ARCH_WANT_SYS_PAUSE +#define __ARCH_WANT_SYS_SGETMASK +#define __ARCH_WANT_SYS_SIGNAL +#define __ARCH_WANT_SYS_TIME +#define __ARCH_WANT_SYS_UTIME +#define __ARCH_WANT_SYS_WAITPID +#define __ARCH_WANT_SYS_SOCKETCALL +#define __ARCH_WANT_SYS_FADVISE64 +#define __ARCH_WANT_SYS_GETPGRP +#define __ARCH_WANT_SYS_LLSEEK +#define __ARCH_WANT_SYS_NICE +#define __ARCH_WANT_SYS_OLD_GETRLIMIT +#define __ARCH_WANT_SYS_OLDUMOUNT +#define __ARCH_WANT_SYS_SIGPENDING +#define __ARCH_WANT_SYS_SIGPROCMASK +#define __ARCH_WANT_SYS_RT_SIGACTION +#define __ARCH_WANT_SYS_RT_SIGSUSPEND + +/* + * "Conditional" syscalls + * + * What we want is __attribute__((weak,alias("sys_ni_syscall"))), + * but it doesn't work on all toolchains, so we just do it by hand + */ +#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") + +#endif /* __KERNEL__ */ +#endif /* _ASM_CRIS_UNISTD_H_ */ diff --git a/arch/cris/include/asm/user.h b/arch/cris/include/asm/user.h new file mode 100644 index 000000000000..59147cf43cf6 --- /dev/null +++ b/arch/cris/include/asm/user.h @@ -0,0 +1,52 @@ +#ifndef __ASM_CRIS_USER_H +#define __ASM_CRIS_USER_H + +#include +#include +#include +#include + +/* + * Core file format: The core file is written in such a way that gdb + * can understand it and provide useful information to the user (under + * linux we use the `trad-core' bfd). The file contents are as follows: + * + * upage: 1 page consisting of a user struct that tells gdb + * what is present in the file. Directly after this is a + * copy of the task_struct, which is currently not used by gdb, + * but it may come in handy at some point. All of the registers + * are stored as part of the upage. The upage should always be + * only one page long. + * data: The data segment follows next. We use current->end_text to + * current->brk to pick up all of the user variables, plus any memory + * that may have been sbrk'ed. No attempt is made to determine if a + * page is demand-zero or if a page is totally unused, we just cover + * the entire range. All of the addresses are rounded in such a way + * that an integral number of pages is written. + * stack: We need the stack information in order to get a meaningful + * backtrace. We need to write the data from usp to + * current->start_stack, so we round each of these in order to be able + * to write an integer number of pages. + */ + +struct user { + struct user_regs_struct regs; /* entire machine state */ + size_t u_tsize; /* text size (pages) */ + size_t u_dsize; /* data size (pages) */ + size_t u_ssize; /* stack size (pages) */ + unsigned long start_code; /* text starting address */ + unsigned long start_data; /* data starting address */ + unsigned long start_stack; /* stack starting address */ + long int signal; /* signal causing core dump */ + unsigned long u_ar0; /* help gdb find registers */ + unsigned long magic; /* identifies a core file */ + char u_comm[32]; /* user command name */ +}; + +#define NBPG PAGE_SIZE +#define UPAGES 1 +#define HOST_TEXT_START_ADDR (u.start_code) +#define HOST_DATA_START_ADDR (u.start_data) +#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) + +#endif /* __ASM_CRIS_USER_H */ diff --git a/arch/cris/kernel/asm-offsets.c b/arch/cris/kernel/asm-offsets.c new file mode 100644 index 000000000000..ddd6fbbe75de --- /dev/null +++ b/arch/cris/kernel/asm-offsets.c @@ -0,0 +1,64 @@ +#include +#include +#include + +/* + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + */ + +#define DEFINE(sym, val) \ + asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + +#define BLANK() asm volatile("\n->" : : ) + +#if !defined(CONFIG_ETRAX_ARCH_V10) && !defined(CONFIG_ETRAX_ARCH_V32) +#error One of ARCH v10 and ARCH v32 must be true! +#endif + +int main(void) +{ +#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry)) + ENTRY(orig_r10); + ENTRY(r13); + ENTRY(r12); + ENTRY(r11); + ENTRY(r10); + ENTRY(r9); +#ifdef CONFIG_ETRAX_ARCH_V32 + ENTRY(acr); + ENTRY(srs); +#endif + ENTRY(mof); +#ifdef CONFIG_ETRAX_ARCH_V10 + ENTRY(dccr); +#else + ENTRY(ccs); +#endif + ENTRY(srp); + BLANK(); +#undef ENTRY +#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) + ENTRY(task); + ENTRY(flags); + ENTRY(preempt_count); + BLANK(); +#undef ENTRY +#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry)) + ENTRY(ksp); + ENTRY(usp); +#ifdef CONFIG_ETRAX_ARCH_V10 + ENTRY(dccr); +#else + ENTRY(ccs); +#endif + BLANK(); +#undef ENTRY +#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry)) + ENTRY(pid); + BLANK(); + DEFINE(LCLONE_VM, CLONE_VM); + DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED); + return 0; +} diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S new file mode 100644 index 000000000000..0d2adfc794d4 --- /dev/null +++ b/arch/cris/kernel/vmlinux.lds.S @@ -0,0 +1,151 @@ +/* ld script to make the Linux/CRIS kernel + * Authors: Bjorn Wesen (bjornw@axis.com) + * + * It is VERY DANGEROUS to fiddle around with the symbols in this + * script. It is for example quite vital that all generated sections + * that are used are actually named here, otherwise the linker will + * put them at the end, where the init stuff is which is FREED after + * the kernel has booted. + */ + +#include +#include +#include + +#ifdef CONFIG_ETRAX_VMEM_SIZE +#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE +#else +#define __CONFIG_ETRAX_VMEM_SIZE 0 +#endif + + +jiffies = jiffies_64; +SECTIONS +{ + . = DRAM_VIRTUAL_BASE; + dram_start = .; +#ifdef CONFIG_ETRAX_ARCH_V10 + ibr_start = .; +#else + ebp_start = .; + /* The boot section is only necessary until the VCS top */ + /* level testbench includes both flash and DRAM. */ + .boot : { *(.boot) } +#endif + + /* see head.S and pages reserved at the start */ + . = DRAM_VIRTUAL_BASE + 0x4000; + + _text = .; /* Text and read-only data. */ + text_start = .; /* Lots of aliases. */ + _stext = .; + __stext = .; + .text : { + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + *(.fixup) + *(.text.__*) + } + + _etext = . ; /* End of text section. */ + __etext = .; + + . = ALIGN(4); /* Exception table. */ + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + RODATA + + . = ALIGN (4); + ___data_start = . ; + __Sdata = . ; + .data : { /* Data */ + DATA_DATA + } + __edata = . ; /* End of data section. */ + _edata = . ; + + . = ALIGN(PAGE_SIZE); /* init_task and stack, must be aligned. */ + .data.init_task : { *(.data.init_task) } + + . = ALIGN(PAGE_SIZE); /* Init code and data. */ + __init_begin = .; + .init.text : { + _sinittext = .; + INIT_TEXT + _einittext = .; + } + .init.data : { INIT_DATA } + . = ALIGN(16); + __setup_start = .; + .init.setup : { *(.init.setup) } + __setup_end = .; +#ifdef CONFIG_ETRAX_ARCH_V32 + __start___param = .; + __param : { *(__param) } + __stop___param = .; +#endif + .initcall.init : { + __initcall_start = .; + INITCALLS + __initcall_end = .; + } + + .con_initcall.init : { + __con_initcall_start = .; + *(.con_initcall.init) + __con_initcall_end = .; + } + SECURITY_INIT + +#ifdef CONFIG_ETRAX_ARCH_V10 +#ifdef CONFIG_BLK_DEV_INITRD + .init.ramfs : { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } +#endif +#endif + __vmlinux_end = .; /* Last address of the physical file. */ +#ifdef CONFIG_ETRAX_ARCH_V32 + PERCPU(PAGE_SIZE) + + .init.ramfs : { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } +#endif + + /* + * We fill to the next page, so we can discard all init + * pages without needing to consider what payload might be + * appended to the kernel image. + */ + . = ALIGN(PAGE_SIZE); + + __init_end = .; + + __data_end = . ; /* Move to _edata ? */ + __bss_start = .; /* BSS. */ + .bss : { + *(COMMON) + *(.bss) + } + + . = ALIGN (0x20); + _end = .; + __end = .; + + /* Sections to be discarded */ + /DISCARD/ : { + EXIT_TEXT + EXIT_DATA + *(.exitcall.exit) + } + + dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024; +} diff --git a/arch/cris/mm/ioremap.c b/arch/cris/mm/ioremap.c index 8b0b9348b574..f9ca44bdea20 100644 --- a/arch/cris/mm/ioremap.c +++ b/arch/cris/mm/ioremap.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include /* * Generic mapping function (not visible outside): diff --git a/arch/frv/kernel/sys_frv.c b/arch/frv/kernel/sys_frv.c index 49b2cf2c38f3..baadc97f8627 100644 --- a/arch/frv/kernel/sys_frv.c +++ b/arch/frv/kernel/sys_frv.c @@ -35,22 +35,21 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, int error = -EBADF; struct file * file = NULL; - flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - if (!(flags & MAP_ANONYMOUS)) { - file = fget(fd); - if (!file) - goto out; - } - /* As with sparc32, make sure the shift for mmap2 is constant (12), no matter what PAGE_SIZE we have.... */ /* But unlike sparc32, don't just silently break if we're trying to map something we can't */ - if (pgoff & ((1<<(PAGE_SHIFT-12))-1)) + if (pgoff & ((1 << (PAGE_SHIFT - 12)) - 1)) return -EINVAL; + pgoff >>= PAGE_SHIFT - 12; - pgoff >>= (PAGE_SHIFT - 12); + flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); + if (!(flags & MAP_ANONYMOUS)) { + file = fget(fd); + if (!file) + goto out; + } down_write(¤t->mm->mmap_sem); error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff); diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 27eec71429b0..6bd91ed7cd03 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -148,6 +148,7 @@ config IA64_GENERIC select ACPI_NUMA select SWIOTLB select PCI_MSI + select DMAR help This selects the system type of your hardware. A "generic" kernel will run on any supported IA-64 system. However, if you configure @@ -585,7 +586,7 @@ source "fs/Kconfig.binfmt" endmenu -menu "Power management and ACPI" +menu "Power management and ACPI options" source "kernel/power/Kconfig" @@ -641,6 +642,8 @@ source "net/Kconfig" source "drivers/Kconfig" +source "arch/ia64/hp/sim/Kconfig" + config MSPEC tristate "Memory special operations driver" depends on IA64 @@ -652,6 +655,12 @@ config MSPEC source "fs/Kconfig" +source "arch/ia64/Kconfig.debug" + +source "security/Kconfig" + +source "crypto/Kconfig" + source "arch/ia64/kvm/Kconfig" source "lib/Kconfig" @@ -678,11 +687,3 @@ config IRQ_PER_CPU config IOMMU_HELPER def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB) - -source "arch/ia64/hp/sim/Kconfig" - -source "arch/ia64/Kconfig.debug" - -source "security/Kconfig" - -source "crypto/Kconfig" diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig index e05f9e1d3faa..27eb67604c53 100644 --- a/arch/ia64/configs/generic_defconfig +++ b/arch/ia64/configs/generic_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Mon Aug 4 15:38:01 2008 +# Linux kernel version: 2.6.28-rc7 +# Mon Dec 8 08:12:07 2008 # CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -26,6 +26,7 @@ CONFIG_LOG_BUF_SHIFT=20 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set # CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set # CONFIG_CGROUP_DEVICE is not set CONFIG_CPUSETS=y # CONFIG_GROUP_SCHED is not set @@ -46,7 +47,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -63,7 +63,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -72,15 +74,11 @@ CONFIG_SLUB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set +CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -113,6 +111,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Processor type and features @@ -125,8 +124,6 @@ CONFIG_MMU=y CONFIG_SWIOTLB=y CONFIG_IOMMU_HELPER=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -139,13 +136,16 @@ CONFIG_GENERIC_IOMAP=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_IA64_UNCACHED_ALLOCATOR=y CONFIG_AUDIT_ARCH=y +# CONFIG_PARAVIRT_GUEST is not set CONFIG_IA64_GENERIC=y # CONFIG_IA64_DIG is not set +# CONFIG_IA64_DIG_VTD is not set # CONFIG_IA64_HP_ZX1 is not set # CONFIG_IA64_HP_ZX1_SWIOTLB is not set # CONFIG_IA64_SGI_SN2 is not set # CONFIG_IA64_SGI_UV is not set # CONFIG_IA64_HP_SIM is not set +# CONFIG_IA64_XEN_GUEST is not set # CONFIG_ITANIUM is not set CONFIG_MCKINLEY=y # CONFIG_IA64_PAGE_SIZE_4KB is not set @@ -182,16 +182,17 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_NR_QUICK=1 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_MMU_NOTIFIER=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_DISCONTIGMEM_ENABLE=y @@ -231,12 +232,12 @@ CONFIG_EFI_VARS=y CONFIG_EFI_PCDP=y CONFIG_DMIID=y CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m -# CONFIG_DMAR is not set - # -# Power management and ACPI +# Power management and ACPI options # CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -248,7 +249,6 @@ CONFIG_ACPI_PROC_EVENT=y CONFIG_ACPI_BUTTON=m CONFIG_ACPI_FAN=m CONFIG_ACPI_DOCK=y -# CONFIG_ACPI_BAY is not set CONFIG_ACPI_PROCESSOR=m CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_THERMAL=m @@ -256,9 +256,7 @@ CONFIG_ACPI_NUMA=y # CONFIG_ACPI_CUSTOM_DSDT is not set CONFIG_ACPI_BLACKLIST_YEAR=0 # CONFIG_ACPI_DEBUG is not set -CONFIG_ACPI_EC=y # CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_POWER=y CONFIG_ACPI_SYSTEM=y CONFIG_ACPI_CONTAINER=m @@ -275,7 +273,7 @@ CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y -# CONFIG_PCI_MSI is not set +CONFIG_PCI_MSI=y CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set CONFIG_HOTPLUG_PCI=m @@ -286,6 +284,7 @@ CONFIG_HOTPLUG_PCI_ACPI=m # CONFIG_HOTPLUG_PCI_SHPC is not set # CONFIG_HOTPLUG_PCI_SGI is not set # CONFIG_PCCARD is not set +CONFIG_DMAR=y CONFIG_NET=y # @@ -333,6 +332,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -353,11 +353,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -385,7 +384,7 @@ CONFIG_PROC_EVENTS=y # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_PNP=y -# CONFIG_PNP_DEBUG is not set +# CONFIG_PNP_DEBUG_MESSAGES is not set # # Protocols @@ -419,10 +418,9 @@ CONFIG_SGI_XP=m # CONFIG_HP_ILO is not set CONFIG_SGI_GRU=m # CONFIG_SGI_GRU_DEBUG is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives @@ -430,12 +428,12 @@ CONFIG_BLK_DEV_IDE=y CONFIG_IDE_TIMINGS=y CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=y CONFIG_BLK_DEV_IDESCSI=m # CONFIG_BLK_DEV_IDEACPI is not set # CONFIG_IDE_TASK_IOCTL is not set @@ -705,6 +703,9 @@ CONFIG_TULIP=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -725,11 +726,11 @@ CONFIG_E100=m # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set CONFIG_IGB=y @@ -747,18 +748,22 @@ CONFIG_TIGON3=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -826,9 +831,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -942,15 +949,16 @@ CONFIG_HWMON=y # CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_HWMON_DEBUG_CHIP is not set CONFIG_THERMAL=m # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -959,6 +967,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -1009,6 +1019,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1113,8 +1124,7 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=m -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set # @@ -1122,6 +1132,34 @@ CONFIG_USB_HID=m # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BRIGHT=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DELL=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SUNPLUS=m +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1138,6 +1176,9 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1155,6 +1196,12 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# Enable Host or Gadget support to see Inventra options +# # # USB Device Class drivers @@ -1162,13 +1209,14 @@ CONFIG_USB_UHCI_HCD=m # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# may also be needed; see USB_STORAGE Help for more information +# see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set @@ -1191,7 +1239,6 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -CONFIG_USB_MON=y # # USB port drivers @@ -1204,7 +1251,7 @@ CONFIG_USB_MON=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1222,7 +1269,9 @@ CONFIG_USB_MON=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1246,6 +1295,15 @@ CONFIG_INFINIBAND_IPOIB_DEBUG=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y + +# +# HP Simulator drivers +# +# CONFIG_HP_SIMETH is not set +# CONFIG_HP_SIMSERIAL is not set +# CONFIG_HP_SIMSCSI is not set CONFIG_MSPEC=m # @@ -1260,7 +1318,7 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y @@ -1271,6 +1329,7 @@ CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -1282,8 +1341,8 @@ CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m # CONFIG_FUSE_FS is not set # @@ -1314,6 +1373,7 @@ CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_VMCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1356,6 +1416,7 @@ CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_SUNRPC_XPRT_RDMA=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1433,38 +1494,6 @@ CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m # CONFIG_DLM is not set -CONFIG_HAVE_KVM=y -CONFIG_VIRTUALIZATION=y -# CONFIG_KVM is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=m -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_IRQ_PER_CPU=y - -# -# HP Simulator drivers -# -# CONFIG_HP_SIMETH is not set -# CONFIG_HP_SIMSERIAL is not set -# CONFIG_HP_SIMSCSI is not set # # Kernel hacking @@ -1503,8 +1532,19 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_IA64_GRANULE_16MB=y # CONFIG_IA64_GRANULE_64MB is not set @@ -1519,14 +1559,19 @@ CONFIG_SYSVIPC_COMPAT=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_MANAGER=m # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1599,5 +1644,36 @@ CONFIG_CRYPTO_DES=m # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_HAVE_KVM=y +CONFIG_VIRTUALIZATION=y +# CONFIG_KVM is not set +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_IRQ_PER_CPU=y diff --git a/arch/ia64/hp/common/hwsw_iommu.c b/arch/ia64/hp/common/hwsw_iommu.c index 88b6e6f3fd88..2769dbfd03bf 100644 --- a/arch/ia64/hp/common/hwsw_iommu.c +++ b/arch/ia64/hp/common/hwsw_iommu.c @@ -13,19 +13,12 @@ */ #include +#include #include /* swiotlb declarations & definitions: */ extern int swiotlb_late_init_with_default_size (size_t size); -extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent; -extern ia64_mv_dma_free_coherent swiotlb_free_coherent; -extern ia64_mv_dma_map_single_attrs swiotlb_map_single_attrs; -extern ia64_mv_dma_unmap_single_attrs swiotlb_unmap_single_attrs; -extern ia64_mv_dma_map_sg_attrs swiotlb_map_sg_attrs; -extern ia64_mv_dma_unmap_sg_attrs swiotlb_unmap_sg_attrs; -extern ia64_mv_dma_supported swiotlb_dma_supported; -extern ia64_mv_dma_mapping_error swiotlb_dma_mapping_error; /* hwiommu declarations & definitions: */ diff --git a/arch/ia64/hp/sim/Kconfig b/arch/ia64/hp/sim/Kconfig index f92306bbedb8..8d513a8c5266 100644 --- a/arch/ia64/hp/sim/Kconfig +++ b/arch/ia64/hp/sim/Kconfig @@ -4,6 +4,7 @@ menu "HP Simulator drivers" config HP_SIMETH bool "Simulated Ethernet " + depends on NET config HP_SIMSERIAL bool "Simulated serial driver support" diff --git a/arch/ia64/include/asm/intrinsics.h b/arch/ia64/include/asm/intrinsics.h index 47d686dba1eb..a3e44a5ed497 100644 --- a/arch/ia64/include/asm/intrinsics.h +++ b/arch/ia64/include/asm/intrinsics.h @@ -226,7 +226,7 @@ extern long ia64_cmpxchg_called_with_bad_pointer (void); /************************************************/ #define ia64_ssm IA64_INTRINSIC_MACRO(ssm) #define ia64_rsm IA64_INTRINSIC_MACRO(rsm) -#define ia64_getreg IA64_INTRINSIC_API(getreg) +#define ia64_getreg IA64_INTRINSIC_MACRO(getreg) #define ia64_setreg IA64_INTRINSIC_API(setreg) #define ia64_set_rr IA64_INTRINSIC_API(set_rr) #define ia64_get_rr IA64_INTRINSIC_API(get_rr) diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h index 7f257507cd86..0d9d16e2d949 100644 --- a/arch/ia64/include/asm/io.h +++ b/arch/ia64/include/asm/io.h @@ -434,28 +434,4 @@ extern void memset_io(volatile void __iomem *s, int c, long n); # endif /* __KERNEL__ */ -/* - * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that - * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64). - * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on - * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing - * over BIO-level virtual merging. - */ -extern unsigned long ia64_max_iommu_merge_mask; -#if 1 -#define BIO_VMERGE_BOUNDARY 0 -#else -/* - * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be - * replaced by dma_merge_mask() or something of that sort. Note: the only way - * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets - * expanded into: - * - * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask) - * - * which is precisely what we want. - */ -#define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1) -#endif - #endif /* _ASM_IA64_IO_H */ diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h index 5fb2bb93de3b..0490794fe4aa 100644 --- a/arch/ia64/include/asm/iommu.h +++ b/arch/ia64/include/asm/iommu.h @@ -11,6 +11,5 @@ extern int force_iommu, no_iommu; extern int iommu_detected; extern void iommu_dma_init(void); extern void machvec_init(const char *name); -extern int forbid_dac; #endif diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h index 85db124d37f6..c60d324da540 100644 --- a/arch/ia64/include/asm/kvm_host.h +++ b/arch/ia64/include/asm/kvm_host.h @@ -365,7 +365,8 @@ struct kvm_vcpu_arch { long itc_offset; unsigned long itc_check; unsigned long timer_check; - unsigned long timer_pending; + unsigned int timer_pending; + unsigned int timer_fired; unsigned long vrr[8]; unsigned long ibr[8]; @@ -417,6 +418,9 @@ struct kvm_arch { struct list_head assigned_dev_head; struct dmar_domain *intel_iommu_domain; struct hlist_head irq_ack_notifier_list; + + unsigned long irq_sources_bitmap; + unsigned long irq_states[KVM_IOAPIC_NUM_PINS]; }; union cpuid3_t { diff --git a/arch/ia64/include/asm/machvec.h b/arch/ia64/include/asm/machvec.h index 1ea28bcee33b..59c17e446683 100644 --- a/arch/ia64/include/asm/machvec.h +++ b/arch/ia64/include/asm/machvec.h @@ -11,6 +11,7 @@ #define _ASM_IA64_MACHVEC_H #include +#include /* forward declarations: */ struct device; @@ -297,27 +298,6 @@ extern void machvec_init_from_cmdline(const char *cmdline); # error Unknown configuration. Update arch/ia64/include/asm/machvec.h. # endif /* CONFIG_IA64_GENERIC */ -/* - * Declare default routines which aren't declared anywhere else: - */ -extern ia64_mv_dma_init swiotlb_init; -extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent; -extern ia64_mv_dma_free_coherent swiotlb_free_coherent; -extern ia64_mv_dma_map_single swiotlb_map_single; -extern ia64_mv_dma_map_single_attrs swiotlb_map_single_attrs; -extern ia64_mv_dma_unmap_single swiotlb_unmap_single; -extern ia64_mv_dma_unmap_single_attrs swiotlb_unmap_single_attrs; -extern ia64_mv_dma_map_sg swiotlb_map_sg; -extern ia64_mv_dma_map_sg_attrs swiotlb_map_sg_attrs; -extern ia64_mv_dma_unmap_sg swiotlb_unmap_sg; -extern ia64_mv_dma_unmap_sg_attrs swiotlb_unmap_sg_attrs; -extern ia64_mv_dma_sync_single_for_cpu swiotlb_sync_single_for_cpu; -extern ia64_mv_dma_sync_sg_for_cpu swiotlb_sync_sg_for_cpu; -extern ia64_mv_dma_sync_single_for_device swiotlb_sync_single_for_device; -extern ia64_mv_dma_sync_sg_for_device swiotlb_sync_sg_for_device; -extern ia64_mv_dma_mapping_error swiotlb_dma_mapping_error; -extern ia64_mv_dma_supported swiotlb_dma_supported; - /* * Define default versions so we can extend machvec for new platforms without having * to update the machvec files for all existing platforms. diff --git a/arch/ia64/include/asm/meminit.h b/arch/ia64/include/asm/meminit.h index 6bc96ee54327..c0cea375620a 100644 --- a/arch/ia64/include/asm/meminit.h +++ b/arch/ia64/include/asm/meminit.h @@ -48,7 +48,6 @@ extern int reserve_elfcorehdr(unsigned long *start, unsigned long *end); */ #define GRANULEROUNDDOWN(n) ((n) & ~(IA64_GRANULE_SIZE-1)) #define GRANULEROUNDUP(n) (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1)) -#define ORDERROUNDDOWN(n) ((n) & ~((PAGE_SIZE< #include -#include #include #ifdef CONFIG_DMAR #include -#include #include -#include dma_addr_t bad_dma_address __read_mostly; EXPORT_SYMBOL(bad_dma_address); @@ -89,13 +86,6 @@ int iommu_dma_supported(struct device *dev, u64 mask) { struct dma_mapping_ops *ops = get_dma_ops(dev); -#ifdef CONFIG_PCI - if (mask > 0xffffffff && forbid_dac > 0) { - dev_info(dev, "Disallowing DAC for device\n"); - return 0; - } -#endif - if (ops->dma_supported_op) return ops->dma_supported_op(dev, mask); diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index ada4605d1223..6543a5547c84 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -1995,11 +1995,6 @@ pfm_close(struct inode *inode, struct file *filp) return -EBADF; } - if (filp->f_flags & FASYNC) { - DPRINT(("cleaning up async_queue=%p\n", ctx->ctx_async_queue)); - pfm_do_fasync(-1, filp, ctx, 0); - } - PROTECT_CTX(ctx, flags); state = ctx->ctx_state; diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index ae7911702bf8..865af27c7737 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -359,7 +359,7 @@ reserve_memory (void) } #endif -#ifdef CONFIG_CRASH_KERNEL +#ifdef CONFIG_CRASH_DUMP if (reserve_elfcorehdr(&rsvd_region[n].start, &rsvd_region[n].end) == 0) n++; @@ -561,8 +561,12 @@ setup_arch (char **cmdline_p) #ifdef CONFIG_ACPI /* Initialize the ACPI boot-time table parser */ acpi_table_init(); + early_acpi_boot_init(); # ifdef CONFIG_ACPI_NUMA acpi_numa_init(); +#ifdef CONFIG_ACPI_HOTPLUG_CPU + prefill_possible_map(); +#endif per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? 32 : cpus_weight(early_cpu_possible_map)), additional_cpus > 0 ? additional_cpus : 0); @@ -853,9 +857,6 @@ void __init setup_per_cpu_areas (void) { /* start_kernel() requires this... */ -#ifdef CONFIG_ACPI_HOTPLUG_CPU - prefill_possible_map(); -#endif } /* diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c index 26228e2d01ae..c75b914f2d6b 100644 --- a/arch/ia64/kernel/topology.c +++ b/arch/ia64/kernel/topology.c @@ -53,10 +53,12 @@ int __ref arch_register_cpu(int num) } EXPORT_SYMBOL(arch_register_cpu); -void arch_unregister_cpu(int num) +void __ref arch_unregister_cpu(int num) { unregister_cpu(&sysfs_cpus[num].cpu); +#ifdef CONFIG_ACPI unmap_cpu_from_node(num, cpu_to_node(num)); +#endif } EXPORT_SYMBOL(arch_unregister_cpu); #else diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig index 8e99fed6b3fd..f833a0b4188d 100644 --- a/arch/ia64/kvm/Kconfig +++ b/arch/ia64/kvm/Kconfig @@ -20,6 +20,8 @@ if VIRTUALIZATION config KVM tristate "Kernel-based Virtual Machine (KVM) support" depends on HAVE_KVM && EXPERIMENTAL + # for device assignment: + depends on PCI select PREEMPT_NOTIFIERS select ANON_INODES ---help--- diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile index cf37f8f490c0..92cef66ca268 100644 --- a/arch/ia64/kvm/Makefile +++ b/arch/ia64/kvm/Makefile @@ -29,13 +29,18 @@ define cmd_offsets echo ""; \ echo "#endif" ) > $@ endef + # We use internal rules to avoid the "is up to date" message from make -arch/ia64/kvm/asm-offsets.s: arch/ia64/kvm/asm-offsets.c +arch/ia64/kvm/asm-offsets.s: arch/ia64/kvm/asm-offsets.c \ + $(wildcard $(srctree)/arch/ia64/include/asm/*.h)\ + $(wildcard $(srctree)/include/linux/*.h) $(call if_changed_dep,cc_s_c) $(obj)/$(offsets-file): arch/ia64/kvm/asm-offsets.s $(call cmd,offsets) +FORCE : $(obj)/$(offsets-file) + # # Makefile for Kernel-based Virtual Machine module # @@ -53,8 +58,7 @@ endif kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o obj-$(CONFIG_KVM) += kvm.o -FORCE : $(obj)/$(offsets-file) -EXTRA_CFLAGS_vcpu.o += -mfixed-range=f2-f5,f12-f127 +CFLAGS_vcpu.o += -mfixed-range=f2-f5,f12-f127 kvm-intel-objs = vmm.o vmm_ivt.o trampoline.o vcpu.o optvfault.o mmio.o \ vtlb.o process.o #Add link memcpy and memset to avoid possible structure assignment error diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c index a312c9e9b9ef..af1464f7a6ad 100644 --- a/arch/ia64/kvm/kvm-ia64.c +++ b/arch/ia64/kvm/kvm-ia64.c @@ -385,6 +385,7 @@ static int handle_global_purge(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) struct kvm *kvm = vcpu->kvm; struct call_data call_data; int i; + call_data.ptc_g_data = p->u.ptc_g_data; for (i = 0; i < KVM_MAX_VCPUS; i++) { @@ -418,33 +419,41 @@ int kvm_emulate_halt(struct kvm_vcpu *vcpu) ktime_t kt; long itc_diff; unsigned long vcpu_now_itc; - unsigned long expires; struct hrtimer *p_ht = &vcpu->arch.hlt_timer; unsigned long cyc_per_usec = local_cpu_data->cyc_per_usec; struct vpd *vpd = to_host(vcpu->kvm, vcpu->arch.vpd); - vcpu_now_itc = ia64_getreg(_IA64_REG_AR_ITC) + vcpu->arch.itc_offset; + if (irqchip_in_kernel(vcpu->kvm)) { - if (time_after(vcpu_now_itc, vpd->itm)) { - vcpu->arch.timer_check = 1; - return 1; - } - itc_diff = vpd->itm - vcpu_now_itc; - if (itc_diff < 0) - itc_diff = -itc_diff; + vcpu_now_itc = ia64_getreg(_IA64_REG_AR_ITC) + vcpu->arch.itc_offset; - expires = div64_u64(itc_diff, cyc_per_usec); - kt = ktime_set(0, 1000 * expires); - vcpu->arch.ht_active = 1; - hrtimer_start(p_ht, kt, HRTIMER_MODE_ABS); + if (time_after(vcpu_now_itc, vpd->itm)) { + vcpu->arch.timer_check = 1; + return 1; + } + itc_diff = vpd->itm - vcpu_now_itc; + if (itc_diff < 0) + itc_diff = -itc_diff; + + expires = div64_u64(itc_diff, cyc_per_usec); + kt = ktime_set(0, 1000 * expires); + + down_read(&vcpu->kvm->slots_lock); + vcpu->arch.ht_active = 1; + hrtimer_start(p_ht, kt, HRTIMER_MODE_ABS); - if (irqchip_in_kernel(vcpu->kvm)) { vcpu->arch.mp_state = KVM_MP_STATE_HALTED; kvm_vcpu_block(vcpu); hrtimer_cancel(p_ht); vcpu->arch.ht_active = 0; + if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests)) + if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) + vcpu->arch.mp_state = + KVM_MP_STATE_RUNNABLE; + up_read(&vcpu->kvm->slots_lock); + if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE) return -EINTR; return 1; @@ -484,10 +493,6 @@ static int (*kvm_vti_exit_handlers[])(struct kvm_vcpu *vcpu, static const int kvm_vti_max_exit_handlers = sizeof(kvm_vti_exit_handlers)/sizeof(*kvm_vti_exit_handlers); -static void kvm_prepare_guest_switch(struct kvm_vcpu *vcpu) -{ -} - static uint32_t kvm_get_exit_reason(struct kvm_vcpu *vcpu) { struct exit_ctl_data *p_exit_data; @@ -600,8 +605,6 @@ static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) again: preempt_disable(); - - kvm_prepare_guest_switch(vcpu); local_irq_disable(); if (signal_pending(current)) { @@ -614,7 +617,7 @@ again: vcpu->guest_mode = 1; kvm_guest_enter(); - + down_read(&vcpu->kvm->slots_lock); r = vti_vcpu_run(vcpu, kvm_run); if (r < 0) { local_irq_enable(); @@ -634,9 +637,8 @@ again: * But we need to prevent reordering, hence this barrier(): */ barrier(); - kvm_guest_exit(); - + up_read(&vcpu->kvm->slots_lock); preempt_enable(); r = kvm_handle_exit(kvm_run, vcpu); @@ -671,15 +673,16 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) vcpu_load(vcpu); + if (vcpu->sigset_active) + sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); + if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { kvm_vcpu_block(vcpu); - vcpu_put(vcpu); - return -EAGAIN; + clear_bit(KVM_REQ_UNHALT, &vcpu->requests); + r = -EAGAIN; + goto out; } - if (vcpu->sigset_active) - sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); - if (vcpu->mmio_needed) { memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); kvm_set_mmio_data(vcpu); @@ -687,7 +690,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) vcpu->mmio_needed = 0; } r = __vcpu_run(vcpu, kvm_run); - +out: if (vcpu->sigset_active) sigprocmask(SIG_SETMASK, &sigsaved, NULL); @@ -778,6 +781,9 @@ static void kvm_init_vm(struct kvm *kvm) kvm_build_io_pmt(kvm); INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); + + /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ + set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); } struct kvm *kvm_arch_create_vm(void) @@ -941,9 +947,8 @@ long kvm_arch_vm_ioctl(struct file *filp, goto out; if (irqchip_in_kernel(kvm)) { mutex_lock(&kvm->lock); - kvm_ioapic_set_irq(kvm->arch.vioapic, - irq_event.irq, - irq_event.level); + kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, + irq_event.irq, irq_event.level); mutex_unlock(&kvm->lock); r = 0; } @@ -1123,15 +1128,16 @@ static enum hrtimer_restart hlt_timer_fn(struct hrtimer *data) wait_queue_head_t *q; vcpu = container_of(data, struct kvm_vcpu, arch.hlt_timer); + q = &vcpu->wq; + if (vcpu->arch.mp_state != KVM_MP_STATE_HALTED) goto out; - q = &vcpu->wq; - if (waitqueue_active(q)) { - vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; + if (waitqueue_active(q)) wake_up_interruptible(q); - } + out: + vcpu->arch.timer_fired = 1; vcpu->arch.timer_check = 1; return HRTIMER_NORESTART; } @@ -1700,12 +1706,14 @@ static void vcpu_kick_intr(void *info) void kvm_vcpu_kick(struct kvm_vcpu *vcpu) { int ipi_pcpu = vcpu->cpu; + int cpu = get_cpu(); if (waitqueue_active(&vcpu->wq)) wake_up_interruptible(&vcpu->wq); - if (vcpu->guest_mode) + if (vcpu->guest_mode && cpu != ipi_pcpu) smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0); + put_cpu(); } int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig) @@ -1715,13 +1723,7 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig) if (!test_and_set_bit(vec, &vpd->irr[0])) { vcpu->arch.irq_new_pending = 1; - if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) - kvm_vcpu_kick(vcpu); - else if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) { - vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; - if (waitqueue_active(&vcpu->wq)) - wake_up_interruptible(&vcpu->wq); - } + kvm_vcpu_kick(vcpu); return 1; } return 0; @@ -1791,7 +1793,7 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu) int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) { - return 0; + return vcpu->arch.timer_fired; } gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) diff --git a/arch/ia64/kvm/kvm_fw.c b/arch/ia64/kvm/kvm_fw.c index 0c69d9ec92d4..cb7600bdff9d 100644 --- a/arch/ia64/kvm/kvm_fw.c +++ b/arch/ia64/kvm/kvm_fw.c @@ -286,6 +286,12 @@ static u64 kvm_get_pal_call_index(struct kvm_vcpu *vcpu) return index; } +static void prepare_for_halt(struct kvm_vcpu *vcpu) +{ + vcpu->arch.timer_pending = 1; + vcpu->arch.timer_fired = 0; +} + int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *run) { @@ -304,11 +310,10 @@ int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *run) break; case PAL_HALT_LIGHT: { - vcpu->arch.timer_pending = 1; INIT_PAL_STATUS_SUCCESS(result); + prepare_for_halt(vcpu); if (kvm_highest_pending_irq(vcpu) == -1) ret = kvm_emulate_halt(vcpu); - } break; diff --git a/arch/ia64/kvm/optvfault.S b/arch/ia64/kvm/optvfault.S index 634abad979b5..32254ce9a1bd 100644 --- a/arch/ia64/kvm/optvfault.S +++ b/arch/ia64/kvm/optvfault.S @@ -107,10 +107,10 @@ END(kvm_vps_resume_normal) GLOBAL_ENTRY(kvm_vps_resume_handler) movl r30 = PAL_VPS_RESUME_HANDLER ;; - ld8 r27=[r25] + ld8 r26=[r25] shr r17=r17,IA64_ISR_IR_BIT ;; - dep r27=r17,r27,63,1 // bit 63 of r27 indicate whether enable CFLE + dep r26=r17,r26,63,1 // bit 63 of r26 indicate whether enable CFLE mov pr=r23,-2 br.sptk.many kvm_vps_entry END(kvm_vps_resume_handler) @@ -894,12 +894,15 @@ ENTRY(kvm_resume_to_guest) ;; ld8 r19=[r19] mov b0=r29 - cmp.ne p6,p7 = r0,r0 + mov r27=cr.isr ;; - tbit.z p6,p7 = r19,IA64_PSR_IC_BIT // p1=vpsr.ic + tbit.z p6,p7 = r19,IA64_PSR_IC_BIT // p7=vpsr.ic + shr r27=r27,IA64_ISR_IR_BIT ;; (p6) ld8 r26=[r25] (p7) mov b0=r28 + ;; + (p6) dep r26=r27,r26,63,1 mov pr=r31,-2 br.sptk.many b0 // call pal service ;; diff --git a/arch/ia64/kvm/process.c b/arch/ia64/kvm/process.c index 3417783ae164..800817307b7b 100644 --- a/arch/ia64/kvm/process.c +++ b/arch/ia64/kvm/process.c @@ -713,7 +713,7 @@ void leave_hypervisor_tail(void) if (!(VCPU(v, itv) & (1 << 16))) { vcpu_pend_interrupt(v, VCPU(v, itv) & 0xff); - VMX(v, itc_check) = 0; + VMX(v, itc_check) = 0; } else { v->arch.timer_pending = 1; } diff --git a/arch/ia64/kvm/vcpu.h b/arch/ia64/kvm/vcpu.h index 341e3fee280c..e9b2a4e121c0 100644 --- a/arch/ia64/kvm/vcpu.h +++ b/arch/ia64/kvm/vcpu.h @@ -384,6 +384,10 @@ static inline u64 __gpfn_is_io(u64 gpfn) #define MODE_IND(psr) \ (((psr).it << 2) + ((psr).dt << 1) + (psr).rt) +#ifndef CONFIG_SMP +#define _vmm_raw_spin_lock(x) do {}while(0) +#define _vmm_raw_spin_unlock(x) do {}while(0) +#else #define _vmm_raw_spin_lock(x) \ do { \ __u32 *ia64_spinlock_ptr = (__u32 *) (x); \ @@ -403,6 +407,7 @@ static inline u64 __gpfn_is_io(u64 gpfn) do { barrier(); \ ((spinlock_t *)x)->raw_lock.lock = 0; } \ while (0) +#endif void vmm_spin_lock(spinlock_t *lock); void vmm_spin_unlock(spinlock_t *lock); diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c index d8c5fcd89e5b..d85ba98d9008 100644 --- a/arch/ia64/mm/discontig.c +++ b/arch/ia64/mm/discontig.c @@ -635,7 +635,6 @@ static __init int count_node_pages(unsigned long start, unsigned long len, int n (min(end, __pa(MAX_DMA_ADDRESS)) - start) >>PAGE_SHIFT; #endif start = GRANULEROUNDDOWN(start); - start = ORDERROUNDDOWN(start); end = GRANULEROUNDUP(end); mem_data[node].max_pfn = max(mem_data[node].max_pfn, end >> PAGE_SHIFT); diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c index c3aa851d1ca6..4e1801bad83a 100644 --- a/arch/ia64/sn/kernel/io_init.c +++ b/arch/ia64/sn/kernel/io_init.c @@ -292,7 +292,7 @@ EXPORT_SYMBOL(sn_io_slot_fixup); * sn_pci_controller_fixup() - This routine sets up a bus's resources * consistent with the Linux PCI abstraction layer. */ -static void +static void __init sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus) { s64 status = 0; diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 96c31b4180c3..0c66dbdd1d72 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2000-2008 Silicon Graphics, Inc. All Rights Reserved. */ #include @@ -375,6 +375,7 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) int cpu = nasid_slice_to_cpuid(nasid, slice); #ifdef CONFIG_SMP int cpuphys; + irq_desc_t *desc; #endif pci_dev_get(pci_dev); @@ -391,6 +392,12 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) #ifdef CONFIG_SMP cpuphys = cpu_physical_id(cpu); set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0); + desc = irq_to_desc(sn_irq_info->irq_irq); + /* + * Affinity was set by the PROM, prevent it from + * being reset by the request_irq() path. + */ + desc->status |= IRQ_AFFINITY_SET; #endif } diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c index bb1d24929640..02c5b8a9fb60 100644 --- a/arch/ia64/sn/kernel/setup.c +++ b/arch/ia64/sn/kernel/setup.c @@ -200,7 +200,7 @@ static int __cpuinitdata shub_1_1_found; * Set flag for enabling shub specific wars */ -static inline int __init is_shub_1_1(int nasid) +static inline int __cpuinit is_shub_1_1(int nasid) { unsigned long id; int rev; @@ -212,7 +212,7 @@ static inline int __init is_shub_1_1(int nasid) return rev <= 2; } -static void __init sn_check_for_wars(void) +static void __cpuinit sn_check_for_wars(void) { int cnode; @@ -512,7 +512,6 @@ static void __init sn_init_pdas(char **cmdline_p) for_each_online_node(cnode) { nodepdaindr[cnode] = alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t)); - memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); memset(nodepdaindr[cnode]->phys_cpuid, -1, sizeof(nodepdaindr[cnode]->phys_cpuid)); spin_lock_init(&nodepdaindr[cnode]->ptc_lock); @@ -521,11 +520,9 @@ static void __init sn_init_pdas(char **cmdline_p) /* * Allocate & initialize nodepda for TIOs. For now, put them on node 0. */ - for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) { + for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) nodepdaindr[cnode] = alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t)); - memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); - } /* * Now copy the array of nodepda pointers to each nodepda. diff --git a/arch/ia64/uv/kernel/setup.c b/arch/ia64/uv/kernel/setup.c index cf5f28ae96c4..7a5ae633198b 100644 --- a/arch/ia64/uv/kernel/setup.c +++ b/arch/ia64/uv/kernel/setup.c @@ -19,6 +19,12 @@ EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); #ifdef CONFIG_IA64_SGI_UV int sn_prom_type; +long sn_partition_id; +EXPORT_SYMBOL(sn_partition_id); +long sn_coherency_id; +EXPORT_SYMBOL_GPL(sn_coherency_id); +long sn_region_size; +EXPORT_SYMBOL(sn_region_size); #endif struct redir_addr { diff --git a/arch/ia64/xen/hypercall.S b/arch/ia64/xen/hypercall.S index d4ff0b9e79f1..45e02bb64a92 100644 --- a/arch/ia64/xen/hypercall.S +++ b/arch/ia64/xen/hypercall.S @@ -58,7 +58,7 @@ __HCALL2(xen_set_rr, HYPERPRIVOP_SET_RR) __HCALL2(xen_set_kr, HYPERPRIVOP_SET_KR) #ifdef CONFIG_IA32_SUPPORT -__HCALL1(xen_get_eflag, HYPERPRIVOP_GET_EFLAG) +__HCALL0(xen_get_eflag, HYPERPRIVOP_GET_EFLAG) __HCALL1(xen_set_eflag, HYPERPRIVOP_SET_EFLAG) // refer SDM vol1 3.1.8 #endif /* CONFIG_IA32_SUPPORT */ diff --git a/arch/m32r/kernel/head.S b/arch/m32r/kernel/head.S index 40180778a5c7..90916067b9c1 100644 --- a/arch/m32r/kernel/head.S +++ b/arch/m32r/kernel/head.S @@ -23,7 +23,7 @@ __INITDATA /* * References to members of the boot_cpu_data structure. */ - .text +.section .text.head, "ax" .global start_kernel .global __bss_start .global _end @@ -133,7 +133,6 @@ loop1: /* * AP startup routine */ - .text .global eit_vector ENTRY(startup_AP) ;; setup EVB @@ -230,6 +229,7 @@ ENTRY(startup_AP) nop #endif /* CONFIG_SMP */ + .text ENTRY(stack_start) .long init_thread_union+8192 .long __KERNEL_DS diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S index 15a6f36c06db..9db05df20c0e 100644 --- a/arch/m32r/kernel/vmlinux.lds.S +++ b/arch/m32r/kernel/vmlinux.lds.S @@ -27,6 +27,7 @@ SECTIONS _text = .; /* Text and read-only data */ .boot : { *(.boot) } = 0 .text : { + *(.text.head) TEXT_TEXT SCHED_TEXT LOCK_TEXT diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig index 8bd61a640fc9..23597beb66c1 100644 --- a/arch/m68k/configs/amiga_defconfig +++ b/arch/m68k/configs/amiga_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:00 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:42 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set CONFIG_AMIGA=y # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -148,19 +138,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_ZORRO=y @@ -212,7 +204,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -262,13 +253,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -282,19 +274,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -302,20 +297,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -323,8 +318,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -337,9 +332,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -351,16 +346,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -387,6 +382,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -410,19 +406,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -470,21 +455,20 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # -CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=m # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -609,8 +593,12 @@ CONFIG_APNE=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_CS89x0 is not set # CONFIG_NET_POCKET is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -763,11 +751,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -777,6 +765,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -802,6 +791,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -829,6 +819,8 @@ CONFIG_FB_FM2=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -852,12 +844,19 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_DMASOUND_PAULA=m CONFIG_DMASOUND=m CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -867,6 +866,8 @@ CONFIG_HIDRAW=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -883,8 +884,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -895,6 +897,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -906,6 +909,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -944,6 +948,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -986,6 +991,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1059,7 +1065,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -1067,6 +1079,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -1077,10 +1090,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1154,14 +1169,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig index c41b854c0284..935108d115a0 100644 --- a/arch/m68k/configs/apollo_defconfig +++ b/arch/m68k/configs/apollo_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:01 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:43 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -148,19 +138,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_HEARTBEAT=y @@ -210,7 +202,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -260,13 +251,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -280,19 +272,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -300,20 +295,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -321,8 +316,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -335,9 +330,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -349,16 +344,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -385,6 +380,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -408,19 +404,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -458,6 +443,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -540,6 +526,9 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -609,6 +598,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -663,11 +653,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -677,6 +667,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -702,6 +693,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y # CONFIG_FB_CFB_COPYAREA is not set CONFIG_FB_CFB_IMAGEBLIT=y @@ -724,6 +716,8 @@ CONFIG_FB_APOLLO=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -750,6 +744,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -758,6 +758,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -773,8 +775,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -785,6 +788,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -796,6 +800,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -834,6 +839,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -877,6 +883,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -949,7 +956,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -957,6 +970,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -967,10 +981,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1044,14 +1060,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig index 654c5acb9e86..a594a1d47b62 100644 --- a/arch/m68k/configs/atari_defconfig +++ b/arch/m68k/configs/atari_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:02 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:44 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set CONFIG_ATARI=y # CONFIG_MAC is not set @@ -148,19 +138,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_STRAM_PROC=y @@ -208,7 +200,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -258,13 +249,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -278,19 +270,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -298,20 +293,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -319,8 +314,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -333,9 +328,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -347,16 +342,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -383,6 +378,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -406,19 +402,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -462,21 +447,20 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # -CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=m # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -565,12 +549,15 @@ CONFIG_EQUALIZER=m CONFIG_VETH=m # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y CONFIG_ATARILANCE=m # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NET_POCKET is not set # CONFIG_NETDEV_1000 is not set @@ -644,6 +631,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set CONFIG_MOUSE_ATARI=m @@ -706,11 +694,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -720,6 +708,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -745,6 +734,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -768,6 +758,8 @@ CONFIG_FB_ATARI=y # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_ATY is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -790,12 +782,19 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_DMASOUND_ATARI=m CONFIG_DMASOUND=m CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -805,6 +804,8 @@ CONFIG_HIDRAW=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -821,10 +822,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4DEV_FS=y -# CONFIG_EXT4DEV_FS_XATTR is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y -CONFIG_JBD2=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -835,6 +835,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -846,6 +847,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -884,6 +886,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -925,6 +928,7 @@ CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -998,7 +1002,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -1006,6 +1016,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -1016,10 +1027,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1093,14 +1106,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig index 2e44af0fe54a..d3d9814a91de 100644 --- a/arch/m68k/configs/bvme6000_defconfig +++ b/arch/m68k/configs/bvme6000_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:03 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:45 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -151,19 +141,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_PROC_HARDWARE=y @@ -212,7 +204,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -262,13 +253,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -282,19 +274,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -302,20 +297,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -323,8 +318,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -337,9 +332,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -351,16 +346,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -387,6 +382,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -410,19 +406,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -460,6 +445,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -545,6 +531,9 @@ CONFIG_BVME6000_NET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -614,6 +603,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -668,11 +658,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -682,6 +672,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -721,6 +712,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -729,6 +726,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -744,8 +743,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -756,6 +756,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -767,6 +768,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -805,6 +807,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -848,6 +851,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -921,7 +925,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -929,6 +939,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -939,10 +950,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1016,14 +1029,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=m -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig index 3570fc89b089..5556ef088d04 100644 --- a/arch/m68k/configs/hp300_defconfig +++ b/arch/m68k/configs/hp300_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:04 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:46 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -149,19 +139,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_HEARTBEAT=y @@ -211,7 +203,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -261,13 +252,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -281,19 +273,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -301,20 +296,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -322,8 +317,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -336,9 +331,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -350,16 +345,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -386,6 +381,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -409,19 +405,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -459,6 +444,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -542,6 +528,9 @@ CONFIG_HPLANCE=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -613,6 +602,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -673,11 +663,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -687,6 +677,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -712,6 +703,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set # CONFIG_FB_CFB_FILLRECT is not set # CONFIG_FB_CFB_COPYAREA is not set CONFIG_FB_CFB_IMAGEBLIT=y @@ -734,6 +726,8 @@ CONFIG_FB_HP300=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -760,6 +754,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -768,6 +768,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -781,8 +783,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -793,6 +796,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -804,6 +808,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -842,6 +847,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -885,6 +891,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -957,7 +964,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -965,6 +978,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -975,10 +989,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1052,14 +1068,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig index db6e8822594a..c6de25724a25 100644 --- a/arch/m68k/configs/mac_defconfig +++ b/arch/m68k/configs/mac_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:06 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:47 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set CONFIG_MAC=y @@ -150,19 +140,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_HEARTBEAT is not set @@ -209,7 +201,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -259,13 +250,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -279,19 +271,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -299,20 +294,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -320,8 +315,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -334,9 +329,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -348,16 +343,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -384,6 +379,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -410,19 +406,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -460,21 +445,20 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # -CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=m # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -581,6 +565,9 @@ CONFIG_MACMACE=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -650,6 +637,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -706,11 +694,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -720,6 +708,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -745,6 +734,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -768,6 +758,8 @@ CONFIG_FB_MAC=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -796,6 +788,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -804,6 +802,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -820,8 +820,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -832,6 +833,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -843,6 +845,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -881,6 +884,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -923,6 +927,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -996,7 +1001,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -1004,6 +1015,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -1014,10 +1026,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1091,14 +1105,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig index 1a806102b999..70693588031e 100644 --- a/arch/m68k/configs/multi_defconfig +++ b/arch/m68k/configs/multi_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:07 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:48 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set CONFIG_AMIGA=y CONFIG_ATARI=y CONFIG_MAC=y @@ -154,19 +144,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_ZORRO=y @@ -222,7 +214,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -272,13 +263,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -292,19 +284,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -312,20 +307,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -333,8 +328,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -347,9 +342,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -361,16 +356,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -397,6 +392,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -424,19 +420,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -486,21 +471,20 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # -CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=m # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -629,7 +613,7 @@ CONFIG_VETH=m # CONFIG_ARCNET is not set # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y CONFIG_ARIADNE=m CONFIG_A2065=m CONFIG_HYDRA=m @@ -657,8 +641,12 @@ CONFIG_NE2000=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_CS89x0 is not set # CONFIG_NET_POCKET is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -735,6 +723,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_INPORT is not set @@ -832,11 +821,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -846,6 +835,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -871,6 +861,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -905,6 +896,8 @@ CONFIG_FB_HP300=y # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_ATY is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -930,6 +923,7 @@ CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_LOGO_MAC_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_DMASOUND_ATARI=m CONFIG_DMASOUND_PAULA=m CONFIG_DMASOUND_Q40=m @@ -938,6 +932,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -947,6 +947,8 @@ CONFIG_HIDRAW=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -973,10 +975,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4DEV_FS=y -# CONFIG_EXT4DEV_FS_XATTR is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y -CONFIG_JBD2=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -987,6 +988,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -998,6 +1000,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1036,6 +1039,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1079,6 +1083,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1156,7 +1161,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -1164,6 +1175,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -1174,10 +1186,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1251,14 +1265,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig index cacb5aef6a37..52d42715bd0b 100644 --- a/arch/m68k/configs/mvme147_defconfig +++ b/arch/m68k/configs/mvme147_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:08 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:50 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -151,19 +141,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_PROC_HARDWARE=y @@ -212,7 +204,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -262,13 +253,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -282,19 +274,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -302,20 +297,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -323,8 +318,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -337,9 +332,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -351,16 +346,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -387,6 +382,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -410,19 +406,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -460,6 +445,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -544,6 +530,9 @@ CONFIG_MVME147_NET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -613,6 +602,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -667,11 +657,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -681,6 +671,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -720,6 +711,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -728,6 +725,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -743,8 +742,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -755,6 +755,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -766,6 +767,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -804,6 +806,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -847,6 +850,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -920,7 +924,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -928,6 +938,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -938,10 +949,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1015,14 +1028,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig index a183e25e348d..3403ed2eda79 100644 --- a/arch/m68k/configs/mvme16x_defconfig +++ b/arch/m68k/configs/mvme16x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:09 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:51 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -151,19 +141,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_PROC_HARDWARE=y @@ -212,7 +204,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -262,13 +253,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -282,19 +274,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -302,20 +297,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -323,8 +318,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -337,9 +332,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -351,16 +346,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -387,6 +382,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -410,19 +406,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -460,6 +445,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -545,6 +531,9 @@ CONFIG_MVME16x_NET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -614,6 +603,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -668,11 +658,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -682,6 +672,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -721,6 +712,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -729,6 +726,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -745,8 +744,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -757,6 +757,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -768,6 +769,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -806,6 +808,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -849,6 +852,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -922,7 +926,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -930,6 +940,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -940,10 +951,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1017,14 +1030,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig index 72eaff0776b8..3459c594194b 100644 --- a/arch/m68k/configs/q40_defconfig +++ b/arch/m68k/configs/q40_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:10 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:52 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -148,19 +138,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_HEARTBEAT=y @@ -209,7 +201,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -259,13 +250,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -279,19 +271,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -299,20 +294,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -320,8 +315,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -334,9 +329,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -348,16 +343,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -384,6 +379,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -407,19 +403,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -458,21 +443,20 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # -CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=m # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -585,8 +569,12 @@ CONFIG_NE2000=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_CS89x0 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -656,6 +644,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_INPORT is not set @@ -717,11 +706,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -731,6 +720,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -756,6 +746,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -778,6 +769,8 @@ CONFIG_FB_Q40=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -800,12 +793,19 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_DMASOUND_Q40=m CONFIG_DMASOUND=m CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -814,6 +814,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -827,8 +829,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -839,6 +842,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -850,6 +854,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -888,6 +893,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -930,6 +936,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1002,7 +1009,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -1010,6 +1023,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -1020,10 +1034,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1097,14 +1113,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig index cb62b96d766e..f404917429fa 100644 --- a/arch/m68k/configs/sun3_defconfig +++ b/arch/m68k/configs/sun3_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:11 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:53 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y CONFIG_NO_DMA=y -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,10 +105,19 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # +# CONFIG_AMIGA is not set +# CONFIG_ATARI is not set +# CONFIG_MAC is not set +# CONFIG_APOLLO is not set +# CONFIG_VME is not set +# CONFIG_HP300 is not set +# CONFIG_SUN3X is not set +# CONFIG_Q40 is not set CONFIG_SUN3=y # @@ -137,19 +136,21 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_PROC_HARDWARE=y @@ -198,7 +199,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -248,13 +248,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -268,19 +269,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -288,20 +292,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -309,8 +313,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -323,9 +327,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -337,16 +341,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -373,6 +377,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -396,19 +401,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -446,6 +440,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -531,6 +526,9 @@ CONFIG_SUN3_82586=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -599,6 +597,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -654,10 +653,6 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set -# -# Sonics Silicon Backplane -# - # # Multifunction device drivers # @@ -665,6 +660,7 @@ CONFIG_GEN_RTC_X=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -690,6 +686,7 @@ CONFIG_GEN_RTC_X=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set # CONFIG_FB_CFB_FILLRECT is not set # CONFIG_FB_CFB_COPYAREA is not set # CONFIG_FB_CFB_IMAGEBLIT is not set @@ -711,6 +708,8 @@ CONFIG_FB=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -737,6 +736,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -744,6 +749,8 @@ CONFIG_HIDRAW=y # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -757,8 +764,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -769,6 +777,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -780,6 +789,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -818,6 +828,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -861,6 +872,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -934,7 +946,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -942,6 +960,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -952,10 +971,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1029,14 +1050,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig index 04b4363a7050..4d8a1e84e39f 100644 --- a/arch/m68k/configs/sun3x_defconfig +++ b/arch/m68k/configs/sun3x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc6 -# Wed Sep 10 09:02:12 2008 +# Linux kernel version: 2.6.28-rc7 +# Tue Dec 2 20:27:54 2008 # CONFIG_M68K=y CONFIG_MMU=y @@ -14,7 +14,6 @@ CONFIG_TIME_LOW_RES=y CONFIG_GENERIC_IOMAP=y CONFIG_NO_IOPORT=y # CONFIG_NO_DMA is not set -CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -67,22 +66,13 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set -# CONFIG_HAVE_OPROFILE is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,11 +105,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform dependent setup # -# CONFIG_SUN3 is not set # CONFIG_AMIGA is not set # CONFIG_ATARI is not set # CONFIG_MAC is not set @@ -148,19 +138,21 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # General setup # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m CONFIG_PROC_HARDWARE=y @@ -209,7 +201,6 @@ CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -259,13 +250,14 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -279,19 +271,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -299,20 +294,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -320,8 +315,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -334,9 +329,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -348,16 +343,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -384,6 +379,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -407,19 +403,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -457,6 +442,7 @@ CONFIG_ATA_OVER_ETH=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -541,6 +527,9 @@ CONFIG_SUN3LANCE=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -610,6 +599,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -664,11 +654,11 @@ CONFIG_GEN_RTC_X=y # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -678,6 +668,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -703,6 +694,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set # CONFIG_FB_CFB_FILLRECT is not set # CONFIG_FB_CFB_COPYAREA is not set # CONFIG_FB_CFB_IMAGEBLIT is not set @@ -724,6 +716,8 @@ CONFIG_FB=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -750,6 +744,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -758,6 +758,8 @@ CONFIG_HIDRAW=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Character devices @@ -771,8 +773,9 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y +CONFIG_JBD2=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -783,6 +786,7 @@ CONFIG_JFS_FS=m # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -794,6 +798,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m # CONFIG_OCFS2_FS_STATS is not set # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -832,6 +837,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -875,6 +881,7 @@ CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -948,7 +955,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set # @@ -956,6 +969,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -966,10 +980,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1043,14 +1059,17 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=y diff --git a/arch/m68k/kernel/ints.c b/arch/m68k/kernel/ints.c index 7e8a0d394e61..761ee0440c99 100644 --- a/arch/m68k/kernel/ints.c +++ b/arch/m68k/kernel/ints.c @@ -133,7 +133,7 @@ void __init m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt, { int i; - BUG_ON(IRQ_USER + cnt >= NR_IRQS); + BUG_ON(IRQ_USER + cnt > NR_IRQS); m68k_first_user_vec = vec; for (i = 0; i < cnt; i++) irq_controller[IRQ_USER + i] = &user_irq_controller; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5f149b030c0f..f4af967a6b30 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -238,21 +238,8 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MARKEINS - bool "NEC EMMA2RH Mark-eins" - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SWAP_IO_SPACE - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_CPU_R5000 - help - This enables support for the R5432-based NEC Mark-eins - boards with R5500 CPU. +config MACH_EMMA + bool "NEC EMMA series based machines" config MACH_VR41XX bool "NEC VR4100 series based machines" @@ -261,6 +248,19 @@ config MACH_VR41XX select SYS_HAS_CPU_VR41XX select GENERIC_HARDIRQS_NO__DO_IRQ +config NXP_STB220 + bool "NXP STB220 board" + select SOC_PNX833X + help + Support for NXP Semiconductors STB220 Development Board. + +config NXP_STB225 + bool "NXP 225 board" + select SOC_PNX833X + select SOC_PNX8335 + help + Support for NXP Semiconductors STB225 Development Board. + config PNX8550_JBS bool "NXP PNX8550 based JBS board" select PNX8550 @@ -327,7 +327,6 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN - select SGI_HAS_DS1286 select SGI_HAS_I8042 select SGI_HAS_INDYDOG select SGI_HAS_HAL2 @@ -382,7 +381,6 @@ config SGI_IP28 select HW_HAS_EISA select I8253 select I8259 - select SGI_HAS_DS1286 select SGI_HAS_I8042 select SGI_HAS_INDYDOG select SGI_HAS_HAL2 @@ -601,6 +599,7 @@ endchoice source "arch/mips/alchemy/Kconfig" source "arch/mips/basler/excite/Kconfig" +source "arch/mips/emma/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" @@ -849,6 +848,24 @@ config MIPS_RM9122 bool select SERIAL_RM9000 +config SOC_PNX833X + bool + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select DMA_NONCOHERENT + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_GPIO + select CPU_MIPSR2_IRQ_VI + +config SOC_PNX8335 + bool + select SOC_PNX833X + config PNX8550 bool select SOC_PNX8550 @@ -874,9 +891,6 @@ config EMMA2RH config SERIAL_RM9000 bool -config SGI_HAS_DS1286 - bool - config SGI_HAS_INDYDOG bool @@ -1092,6 +1106,16 @@ config CPU_R5432 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL +config CPU_R5500 + bool "R5500" + depends on SYS_HAS_CPU_R5500 + select CPU_HAS_LLSC + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + help + NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV + instruction set. + config CPU_R6000 bool "R6000" depends on EXPERIMENTAL @@ -1202,6 +1226,9 @@ config SYS_HAS_CPU_R5000 config SYS_HAS_CPU_R5432 bool +config SYS_HAS_CPU_R5500 + bool + config SYS_HAS_CPU_R6000 bool diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 765c8e287d2b..364ca8938807 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -48,7 +48,7 @@ config RUNTIME_DEBUG help If you say Y here, some debugging macros will do run-time checking. If you say N here, those macros will mostly turn to no-ops. See - include/asm-mips/debug.h for debuging macros. + arch/mips/include/asm/debug.h for debugging macros. If unsure, say N. endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7f39fd8a91fe..28c55f608913 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -131,6 +131,8 @@ cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_ cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \ -Wa,--trap +cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \ + -Wa,--trap cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ -Wa,--trap cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ @@ -381,6 +383,14 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 # load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 +# NXP STB225 +core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/ +cflags-$(CONFIG_SOC_PNX833X) += -Iarch/mips/include/asm/mach-pnx833x +libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB220) += 0xffffffff80001000 +libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB225) += 0xffffffff80001000 + # # Common NXP PNX8550 # @@ -399,14 +409,17 @@ load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 -# NEC EMMA2RH boards # -core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ -cflags-$(CONFIG_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh +# Common NEC EMMAXXX +# +core-$(CONFIG_SOC_EMMA) += arch/mips/emma/common/ +cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh +# # NEC EMMA2RH Mark-eins -core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/ -load-$(CONFIG_MARKEINS) += 0xffffffff88100000 +# +core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/ +load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000 # # SGI IP22 (Indy/Indigo2) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index dc8a67efac28..5c76c6448e04 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -17,6 +17,8 @@ #include #include +#include +#include #define PORT(_base, _irq) \ { \ @@ -163,24 +165,6 @@ static struct resource au1xxx_usb_gdt_resources[] = { }, }; -static struct resource au1xxx_mmc_resources[] = { - [0] = { - .start = SD0_PHYS_ADDR, - .end = SD0_PHYS_ADDR + 0x7ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SD1_PHYS_ADDR, - .end = SD1_PHYS_ADDR + 0x7ffff, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - } -}; - static u64 udc_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_gdt_device = { @@ -249,16 +233,79 @@ static struct platform_device au1200_lcd_device = { static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; -static struct platform_device au1xxx_mmc_device = { +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; + +static struct resource au1200_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device au1200_mmc0_device = { .name = "au1xxx-mmc", .id = 0, .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[0], }, - .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), - .resource = au1xxx_mmc_resources, + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), + .resource = au1200_mmc0_resources, }; + +#ifndef CONFIG_MIPS_DB1200 +static struct resource au1200_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device au1200_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_resources), + .resource = au1200_mmc1_resources, +}; +#endif /* #ifndef CONFIG_MIPS_DB1200 */ #endif /* #ifdef CONFIG_SOC_AU1200 */ static struct platform_device au1x00_pcmcia_device = { @@ -296,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xxx_usb_gdt_device, &au1xxx_usb_otg_device, &au1200_lcd_device, - &au1xxx_mmc_device, + &au1200_mmc0_device, +#ifndef CONFIG_MIPS_DB1200 + &au1200_mmc1_device, +#endif #endif #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/pb1200/platform.c index f8fb0aeac571..95303297c534 100644 --- a/arch/mips/alchemy/pb1200/platform.c +++ b/arch/mips/alchemy/pb1200/platform.c @@ -20,9 +20,90 @@ #include #include +#include #include #include +#include + +static int mmc_activity; + +static void pb1200mmc0_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD0PWR; + else + bcsr->board &= ~BCSR_BOARD_SD0PWR; + + au_sync_delay(1); +} + +static int pb1200mmc0_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; +} + +static int pb1200mmc0_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; +} + +static void pb1200_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev pb1200mmc_led = { + .brightness_set = pb1200_mmcled_set, +}; + +#ifndef CONFIG_MIPS_DB1200 +static void pb1200mmc1_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD1PWR; + else + bcsr->board &= ~BCSR_BOARD_SD1PWR; + + au_sync_delay(1); +} + +static int pb1200mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; +} + +static int pb1200mmc1_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; +} +#endif + +const struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = pb1200mmc0_set_power, + .card_inserted = pb1200mmc0_card_inserted, + .card_readonly = pb1200mmc0_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#ifndef CONFIG_MIPS_DB1200 + [1] = { + .set_power = pb1200mmc1_set_power, + .card_inserted = pb1200mmc1_card_inserted, + .card_readonly = pb1200mmc1_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#endif +}; static struct resource ide_resources[] = { [0] = { diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 620980081a30..b6698a232ae9 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -1,63 +1,78 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22-rc4 -# Mon Jun 11 00:23:51 2007 +# Linux kernel version: 2.6.28-rc6 +# Fri Nov 28 17:53:48 2008 # CONFIG_MIPS=y # # Machine selection # -CONFIG_LEMOTE_FULONG=y # CONFIG_MACH_ALCHEMY is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +CONFIG_LEMOTE_FULONG=y # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set +# CONFIG_MACH_EMMA is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_I8259=y # CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection @@ -75,6 +90,7 @@ CONFIG_CPU_LOONGSON2=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -101,7 +117,6 @@ CONFIG_BOARD_SCACHE=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_CPU_HAS_WB=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y @@ -109,6 +124,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -117,9 +133,17 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -133,37 +157,40 @@ CONFIG_HZ=250 CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="lm32" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +CONFIG_USER_NS=y +CONFIG_PID_NS=y # CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y @@ -175,6 +202,8 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -183,29 +212,33 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y - -# -# Block layer -# CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLOCK_COMPAT=y # # IO Schedulers @@ -219,19 +252,19 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y CONFIG_ISA=y CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -239,8 +272,9 @@ CONFIG_MMU=y # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y -# CONFIG_BUILD_ELF64 is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y @@ -251,14 +285,12 @@ CONFIG_BINFMT_ELF32=y # # Power management options # +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y CONFIG_NET=y # @@ -271,6 +303,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -294,18 +327,17 @@ CONFIG_INET_TUNNEL=m # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration @@ -313,53 +345,59 @@ CONFIG_NETFILTER=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m -# CONFIG_NF_CONNTRACK_ENABLED is not set # CONFIG_NF_CONNTRACK is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m # CONFIG_NETFILTER_XT_TARGET_DSCP is not set CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_DCCP=m # CONFIG_NETFILTER_XT_MATCH_DSCP is not set CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m -# CONFIG_NETFILTER_XT_MATCH_POLICY is not set CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m @@ -371,6 +409,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -380,10 +419,6 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set CONFIG_NET_CLS_ROUTE=y @@ -392,23 +427,25 @@ CONFIG_NET_CLS_ROUTE=y # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +CONFIG_PHONET=m +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_MAC80211 is not set CONFIG_IEEE80211=m # CONFIG_IEEE80211_DEBUG is not set CONFIG_IEEE80211_CRYPT_WEP=m # CONFIG_IEEE80211_CRYPT_CCMP is not set # CONFIG_IEEE80211_CRYPT_TKIP is not set -# CONFIG_IEEE80211_SOFTMAC is not set # CONFIG_RFKILL is not set +CONFIG_NET_9P=m +# CONFIG_NET_9P_DEBUG is not set # # Device Drivers @@ -417,14 +454,13 @@ CONFIG_IEEE80211_CRYPT_WEP=m # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set CONFIG_MTD=m # CONFIG_MTD_DEBUG is not set @@ -443,6 +479,7 @@ CONFIG_MTD_BLOCK=m # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -482,6 +519,7 @@ CONFIG_MTD_PHYSMAP=m CONFIG_MTD_PHYSMAP_START=0x1fc00000 CONFIG_MTD_PHYSMAP_LEN=0x80000 CONFIG_MTD_PHYSMAP_BANKWIDTH=1 +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -506,21 +544,9 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# # CONFIG_PNP is not set -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -534,32 +560,28 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m - -# -# Misc devices -# -# CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_BLINK is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # +CONFIG_IDE_TIMINGS=y +CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set CONFIG_BLK_DEV_IDESCSI=y CONFIG_IDE_TASK_IOCTL=y CONFIG_IDE_PROC_FS=y @@ -568,24 +590,25 @@ CONFIG_IDE_PROC_FS=y # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_SHARE_IRQ=y CONFIG_IDEPCI_PCIBUS_ORDER=y # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_ONLYDISK is not set # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_BLK_DEV_AMD74XX is not set # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set @@ -601,17 +624,28 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y # CONFIG_BLK_DEV_TRM290 is not set CONFIG_BLK_DEV_VIA82CXXX=y # CONFIG_BLK_DEV_TC86C001 is not set -# CONFIG_IDE_ARM is not set -# CONFIG_IDE_CHIPSETS is not set + +# +# Other IDE chipsets support +# + +# +# Note: most of these also require special kernel boot parameters +# +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_UMC8672 is not set CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y @@ -644,88 +678,30 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# -# CONFIG_ISCSI_TCP is not set -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set - -# -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support # -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set # -# I2O device support +# Enable only one of the two stacks, unless you know what you are doing # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set # CONFIG_I2O is not set - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +CONFIG_MACVLAN=m # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +CONFIG_VETH=m # CONFIG_ARCNET is not set CONFIG_PHYLIB=m @@ -740,29 +716,32 @@ CONFIG_CICADA_PHY=m # CONFIG_VITESSE_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_SMC is not set +# CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_NET_VENDOR_RACAL is not set - -# -# Tulip family network device support -# # CONFIG_NET_TULIP is not set # CONFIG_AT1700 is not set # CONFIG_DEPCA is not set # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -773,7 +752,6 @@ CONFIG_NET_PCI=y # CONFIG_FORCEDETH is not set # CONFIG_CS89x0 is not set # CONFIG_TC35815 is not set -# CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set @@ -785,15 +763,21 @@ CONFIG_8139TOO=y # CONFIG_8139TOO_TUNE_TWISTER is not set # CONFIG_8139TOO_8129 is not set # CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -801,20 +785,29 @@ CONFIG_NETDEV_1000=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set # CONFIG_TR is not set # @@ -822,6 +815,7 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -830,7 +824,6 @@ CONFIG_NETDEV_10000=y # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET_MII is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set @@ -844,25 +837,17 @@ CONFIG_PPP_DEFLATE=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m CONFIG_SLIP=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLHC=m CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y CONFIG_NET_FC=y -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -870,6 +855,7 @@ CONFIG_NET_FC=y # CONFIG_INPUT=y CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -879,7 +865,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -900,9 +885,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=y # CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_INPORT is not set # CONFIG_MOUSE_LOGIBM is not set # CONFIG_MOUSE_PC110PAD is not set @@ -927,10 +914,13 @@ CONFIG_SERIO_LIBPS2=y # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -951,105 +941,152 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=y -CONFIG_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y # -# I2C Algorithms +# I2C Hardware Bus support # -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set # -# I2C Hardware Bus support +# PC SMBus host controller drivers # # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_ELEKTOR is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_VIA is not set CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_ELEKTOR is not set # CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # -# Dallas's 1-wire bus +# Sonics Silicon Backplane # -# CONFIG_W1 is not set -# CONFIG_HWMON is not set +# CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_VIDEO_V4L2=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_CUSTOMIZE=y +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DMA_CONTIG=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_HELPER_CHIPS_AUTO=y # CONFIG_VIDEO_VIVI is not set # CONFIG_VIDEO_BT848 is not set @@ -1058,17 +1095,46 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y # CONFIG_VIDEO_CPIA2 is not set # CONFIG_VIDEO_SAA5246A is not set # CONFIG_VIDEO_SAA5249 is not set -# CONFIG_TUNER_3036 is not set # CONFIG_VIDEO_STRADIS is not set # CONFIG_VIDEO_SAA7134 is not set # CONFIG_VIDEO_MXB is not set -# CONFIG_VIDEO_DPC is not set # CONFIG_VIDEO_HEXIUM_ORION is not set # CONFIG_VIDEO_HEXIUM_GEMINI is not set # CONFIG_VIDEO_CX88 is not set # CONFIG_VIDEO_IVTV is not set # CONFIG_VIDEO_CAFE_CCIC is not set +CONFIG_SOC_CAMERA=m +CONFIG_SOC_CAMERA_MT9M001=m +CONFIG_SOC_CAMERA_MT9M111=m +CONFIG_SOC_CAMERA_MT9V022=m +CONFIG_SOC_CAMERA_PLATFORM=m +CONFIG_VIDEO_SH_MOBILE_CEU=m CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_ZC3XX=m # CONFIG_VIDEO_PVRUSB2 is not set # CONFIG_VIDEO_EM28XX is not set # CONFIG_VIDEO_USBVISION is not set @@ -1079,7 +1145,6 @@ CONFIG_USB_KONICAWC=m CONFIG_USB_QUICKCAM_MESSENGER=m CONFIG_USB_ET61X251=m # CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_W9968CF is not set CONFIG_USB_OV511=m CONFIG_USB_SE401=m CONFIG_USB_SN9C102=m @@ -1088,6 +1153,8 @@ CONFIG_USB_ZC0301=m CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set # CONFIG_USB_ZR364XX is not set +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m CONFIG_RADIO_ADAPTERS=y # CONFIG_RADIO_CADET is not set # CONFIG_RADIO_RTRACK is not set @@ -1104,33 +1171,30 @@ CONFIG_RADIO_ADAPTERS=y # CONFIG_RADIO_TYPHOON is not set # CONFIG_RADIO_ZOLTRIX is not set # CONFIG_USB_DSBR is not set -# CONFIG_DVB_CORE is not set +CONFIG_USB_SI470X=m +CONFIG_USB_MR800=m CONFIG_DAB=y # CONFIG_USB_DABUSB is not set # # Graphics support # -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_LCD_CLASS_DEVICE=m - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_DRM is not set # CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set -CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set CONFIG_FB_BACKLIGHT=y @@ -1158,16 +1222,30 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_SMIVGX is not set # CONFIG_FB_VT8623 is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_CORGI is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support @@ -1176,20 +1254,14 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y # CONFIG_LOGO is not set - -# -# Sound -# CONFIG_SOUND=y - -# -# Advanced Linux Sound Architecture -# +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1201,28 +1273,22 @@ CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_RTCTIMER=m -CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# +CONFIG_SND_VMASTER=y CONFIG_SND_MPU401_UART=m CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_VIRMIDI is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set - -# -# PCI devices -# +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set # CONFIG_SND_ALS300 is not set # CONFIG_SND_ALI5451 is not set @@ -1231,10 +1297,12 @@ CONFIG_SND_AC97_CODEC=m # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set # CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set # CONFIG_SND_CA0106 is not set # CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set # CONFIG_SND_CS4281 is not set # CONFIG_SND_CS46XX is not set # CONFIG_SND_DARLA20 is not set @@ -1259,6 +1327,7 @@ CONFIG_SND_AC97_CODEC=m # CONFIG_SND_HDA_INTEL is not set # CONFIG_SND_HDSP is not set # CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set # CONFIG_SND_ICE1712 is not set # CONFIG_SND_ICE1724 is not set # CONFIG_SND_INTEL8X0 is not set @@ -1276,43 +1345,26 @@ CONFIG_SND_AC97_CODEC=m # CONFIG_SND_TRIDENT is not set CONFIG_SND_VIA82XX=m # CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set -# CONFIG_SND_AC97_POWER_SAVE is not set - -# -# ALSA MIPS devices -# - -# -# USB devices -# +CONFIG_SND_MIPS=y +CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set # CONFIG_SND_USB_CAIAQ is not set - -# -# System on Chip audio support -# # CONFIG_SND_SOC is not set - -# -# Open Sound System -# # CONFIG_SOUND_PRIME is not set CONFIG_AC97_BUS=m - -# -# HID Devices -# +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y # # USB Input Devices # CONFIG_USB_HID=m -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y # @@ -1322,13 +1374,39 @@ CONFIG_USB_HIDDEV=y # CONFIG_USB_MOUSE is not set # -# USB support -# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BRIGHT=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DELL=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_LOGITECH=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SUNPLUS=m +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_ZEROPLUS_FF=m +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # # Miscellaneous USB options @@ -1338,35 +1416,46 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set +CONFIG_USB_OTG_WHITELIST=y +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +CONFIG_USB_WUSB_CBAF=m +# CONFIG_USB_WUSB_CBAF_DEBUG is not set # # USB Host Controller Drivers # +CONFIG_USB_C67X00_HCD=m CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_SPLIT_ISO=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set # CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_ISP1760_HCD=m CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set +CONFIG_USB_R8A66597_HCD=m +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers # CONFIG_USB_ACM=y CONFIG_USB_PRINTER=y +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# may also be needed; see USB_STORAGE Help for more information +# see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set @@ -1379,7 +1468,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set +CONFIG_USB_STORAGE_ONETOUCH=y # CONFIG_USB_STORAGE_KARMA is not set +CONFIG_USB_STORAGE_CYPRESS_ATACB=y CONFIG_USB_LIBUSUAL=y # @@ -1387,15 +1478,10 @@ CONFIG_USB_LIBUSUAL=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers # - -# -# USB Serial Converter support -# # CONFIG_USB_SERIAL is not set # @@ -1404,7 +1490,7 @@ CONFIG_USB_LIBUSUAL=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +CONFIG_USB_SEVSEG=m # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1421,56 +1507,75 @@ CONFIG_USB_LIBUSUAL=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# - -# -# USB Gadget Support -# +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_VST=m # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set - -# -# LED devices -# +# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=m # -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# RTC interfaces # +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set # -# Real Time Clock +# I2C RTC drivers # -# CONFIG_RTC_CLASS is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # -# DMA Engine support +# SPI RTC drivers # -# CONFIG_DMA_ENGINE is not set # -# DMA Clients +# Platform RTC drivers # +CONFIG_RTC_DRV_CMOS=m +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# DMA Devices +# on-CPU RTC drivers # +# CONFIG_DMADEVICES is not set +CONFIG_UIO=m +CONFIG_UIO_CIF=m +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -1478,27 +1583,31 @@ CONFIG_USB_LIBUSUAL=y CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=m +CONFIG_EXT4DEV_COMPAT=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_XIP=y CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=m +CONFIG_FS_MBCACHE=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_REISERFS_FS_XATTR is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=y @@ -1530,11 +1639,11 @@ CONFIG_NTFS_RW=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -1550,25 +1659,23 @@ CONFIG_RAMFS=y # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +CONFIG_OMFS_FS=m # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -CONFIG_NFS_DIRECTIO=y CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y -CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m @@ -1576,7 +1683,7 @@ CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1616,10 +1723,6 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" # CONFIG_NLS_CODEPAGE_437 is not set @@ -1660,30 +1763,31 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set CONFIG_NLS_UTF8=y - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set -# -# Profiling support -# -CONFIG_PROFILING=y -CONFIG_OPROFILE=m - # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y # CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +CONFIG_DYNAMIC_PRINTK_DEBUG=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -1691,64 +1795,113 @@ CONFIG_CMDLINE="" # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y +CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=m +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA1=m # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=m -# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=m -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_LZO=m # -# Hardware crypto devices +# Random Number Generation # +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y +CONFIG_CRC7=m # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index cc8e6bf2b245..115822876417 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -1,30 +1,34 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.23-rc2 -# Tue Aug 7 12:39:49 2007 +# Linux kernel version: 2.6.28-rc6 +# Fri Nov 28 15:41:33 2008 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y # CONFIG_MACH_ALCHEMY is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_MACH_EMMA is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set @@ -35,34 +39,49 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARC=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +CONFIG_I8259=y # CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y +CONFIG_SGI_HAS_INDYDOG=y +CONFIG_SGI_HAS_HAL2=y +CONFIG_SGI_HAS_SEEQ=y +CONFIG_SGI_HAS_WD93=y +CONFIG_SGI_HAS_ZILOG=y +CONFIG_SGI_HAS_I8042=y +CONFIG_DEFAULT_SGI_PARTITION=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_L1_CACHE_SHIFT=7 CONFIG_ARC_CONSOLE=y CONFIG_ARC_PROMLIB=y @@ -82,6 +101,7 @@ CONFIG_ARC_PROMLIB=y # CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -115,18 +135,24 @@ CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -159,13 +185,20 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y # CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y @@ -177,6 +210,8 @@ CONFIG_KALLSYMS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -185,14 +220,21 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y @@ -203,6 +245,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -216,6 +259,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -224,29 +269,24 @@ CONFIG_HW_HAS_EISA=y # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_EISA is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# +CONFIG_I8253=y # # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set # CONFIG_SUSPEND is not set - -# -# Networking -# CONFIG_NET=y # @@ -259,6 +299,8 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -282,42 +324,13 @@ CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -334,12 +347,16 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration @@ -347,12 +364,12 @@ CONFIG_NETFILTER=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=m CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m CONFIG_NF_CT_PROTO_UDPLITE=m @@ -366,18 +383,22 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m @@ -386,39 +407,75 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT=y CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -426,11 +483,13 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_TFTP=m @@ -439,32 +498,30 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration (EXPERIMENTAL) +# IPv6: Netfilter Configuration # CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_OWNER=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -479,6 +536,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -488,12 +546,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y # # Queueing/Scheduling @@ -502,7 +555,7 @@ CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RR=m +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -526,6 +579,7 @@ CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m # CONFIG_NET_EMATCH is not set CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y @@ -533,35 +587,28 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m -CONFIG_NET_CLS_POLICE=y +CONFIG_NET_ACT_SKBEDIT=m # CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +CONFIG_PHONET=m CONFIG_FIB_RULES=y - -# -# Wireless -# -CONFIG_CFG80211=m +# CONFIG_WIRELESS is not set CONFIG_WIRELESS_EXT=y -CONFIG_MAC80211=m -# CONFIG_MAC80211_DEBUG is not set CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=m # CONFIG_NET_9P is not set @@ -588,7 +635,9 @@ CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -628,20 +677,22 @@ CONFIG_SCSI_SPI_ATTRS=m # CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=m # CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=m CONFIG_SGIWD93_SCSI=y # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_IFB is not set CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_MACVLAN=m CONFIG_EQUALIZER=m CONFIG_TUN=m +CONFIG_VETH=m CONFIG_PHYLIB=m # @@ -656,11 +707,21 @@ CONFIG_CICADA_PHY=m # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set -# CONFIG_FIXED_PHY is not set +CONFIG_REALTEK_PHY=m +CONFIG_MDIO_BITBANG=m CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=m # CONFIG_AX88796 is not set +CONFIG_SMC91X=m # CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set CONFIG_SGISEEQ=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -672,12 +733,12 @@ CONFIG_WLAN_PRE80211=y CONFIG_STRIP=m CONFIG_WLAN_80211=y # CONFIG_LIBERTAS is not set +# CONFIG_IWLWIFI_LEDS is not set CONFIG_HOSTAP=m # CONFIG_HOSTAP_FIRMWARE is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -699,7 +760,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -720,6 +780,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y # CONFIG_MOUSE_PS2_SYNAPTICS is not set # CONFIG_MOUSE_PS2_LIFEBOOK is not set CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_VSXXXAA is not set @@ -742,9 +803,11 @@ CONFIG_SERIO_RAW=m # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -761,6 +824,17 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=m CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -769,48 +843,50 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_INDYDOG=m -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -CONFIG_SGI_DS1286=m -# CONFIG_R3964 is not set -CONFIG_RAW_DRIVER=m -CONFIG_MAX_RAW_DEVS=256 -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set +CONFIG_SSB_POSSIBLE=y # -# SPI support +# Sonics Silicon Backplane # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set +# CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# # CONFIG_DAB is not set # # Graphics support # +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set # # Console display driver support @@ -824,48 +900,77 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SGI_CLUT224=y - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y +CONFIG_HID_PID=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# Enable Host or Gadget support to see Inventra options # # -# USB Gadget Support +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set -# CONFIG_RTC_CLASS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # -# DMA Engine support +# RTC interfaces # -# CONFIG_DMA_ENGINE is not set +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set # -# DMA Clients +# SPI RTC drivers # # -# DMA Devices +# Platform RTC drivers # +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_DRV_DS1286=y +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# Userspace I/O +# on-CPU RTC drivers # +# CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -877,29 +982,33 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=m +CONFIG_EXT4DEV_COMPAT=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=m CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set -# CONFIG_GFS2_FS is not set +# CONFIG_XFS_DEBUG is not set # CONFIG_OCFS2_FS is not set -CONFIG_MINIX_FS=m -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m @@ -930,11 +1039,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m # @@ -950,27 +1059,25 @@ CONFIG_CONFIGFS_FS=m CONFIG_EFS_FS=m # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set CONFIG_UFS_FS=m # CONFIG_UFS_FS_WRITE is not set # CONFIG_UFS_DEBUG is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set -CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m @@ -978,7 +1085,7 @@ CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -987,12 +1094,12 @@ CONFIG_SMB_NLS_REMOTE="cp437" CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +CONFIG_CIFS_UPCALL=y # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_EXPERIMENTAL is not set # CONFIG_NCP_FS is not set CONFIG_CODA_FS=m -# CONFIG_CODA_FS_OLD_API is not set # CONFIG_AFS_FS is not set # @@ -1016,10 +1123,6 @@ CONFIG_SGI_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m @@ -1060,30 +1163,32 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# CONFIG_DLM=m # CONFIG_DLM_DEBUG is not set -# -# Profiling support -# -# CONFIG_PROFILING is not set - # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set + +# +# Tracers +# +CONFIG_DYNAMIC_PRINTK_DEBUG=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -1092,46 +1197,97 @@ CONFIG_CMDLINE="" CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ABLKCIPHER=m -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m # CONFIG_CRYPTO_HW is not set # @@ -1140,12 +1296,15 @@ CONFIG_CRYPTO_CAMELLIA=m CONFIG_BITREVERSE=m # CONFIG_CRC_CCITT is not set CONFIG_CRC16=m -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC_T10DIF=m +CONFIG_CRC_ITU_T=m CONFIG_CRC32=m # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 831d3e5a1ea6..34ea319be94c 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -701,7 +701,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=m # CONFIG_RTC is not set -CONFIG_SGI_IP27_RTC=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_DRM is not set diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 822b01f643e3..70a744e9a8c5 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -70,7 +70,6 @@ CONFIG_CPU_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y -CONFIG_SGI_HAS_DS1286=y CONFIG_SGI_HAS_INDYDOG=y CONFIG_SGI_HAS_SEEQ=y CONFIG_SGI_HAS_WD93=y @@ -585,7 +584,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set -CONFIG_SGI_DS1286=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index fe4699df9626..de4c7a0a96dd 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -1,71 +1,71 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:33 2007 +# Linux kernel version: 2.6.28-rc7 +# Wed Dec 10 14:39:08 2008 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MACH_ALCHEMY is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_MACH_EMMA is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set CONFIG_SGI_IP32=y -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARC=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -75,6 +75,7 @@ CONFIG_ARC_PROMLIB=y # # CPU selection # +# CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -87,6 +88,7 @@ CONFIG_ARC_PROMLIB=y # CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -116,65 +118,73 @@ CONFIG_RM7000_CPU_SCACHE=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_RESOURCES_64BIT=y -CONFIG_ZONE_DMA_FLAG=1 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set +CONFIG_HZ_250=y # CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y +# CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set +CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set +CONFIG_AUDIT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y @@ -184,27 +194,43 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLOCK_COMPAT=y # # IO Schedulers @@ -213,59 +239,50 @@ CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_LEGACY is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# # CONFIG_HOTPLUG_PCI is not set # # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y -# CONFIG_BUILD_ELF64 is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_MIPS32_O32=y -# CONFIG_MIPS32_N32 is not set +CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # # Power management options # -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y @@ -273,56 +290,83 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=y # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set +CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +# CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_DEFAULT_BIC is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_HTCP is not set +# CONFIG_DEFAULT_VEGAS is not set +# CONFIG_DEFAULT_WESTWOOD is not set +# CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set CONFIG_NETWORK_SECMARK=y # CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -332,10 +376,6 @@ CONFIG_NETWORK_SECMARK=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -343,15 +383,14 @@ CONFIG_NETWORK_SECMARK=y # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -360,60 +399,40 @@ CONFIG_WIRELESS_EXT=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# # CONFIG_MTD is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# Misc devices -# +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set CONFIG_SGI_IOC4=y # CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -421,19 +440,20 @@ CONFIG_SGI_IOC4=y # CONFIG_RAID_ATTRS=y CONFIG_SCSI=y +CONFIG_SCSI_DMA=y CONFIG_SCSI_TGT=y -CONFIG_SCSI_NETLINK=y +# CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -CONFIG_CHR_DEV_OSST=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SG=m # CONFIG_CHR_DEV_SCH is not set # @@ -443,35 +463,36 @@ CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SCSI_FC_ATTRS=y +# CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set CONFIG_SCSI_SAS_ATTRS=y CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SCSI_SAS_HOST_SMP=y # CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set CONFIG_SCSI_AIC7XXX=y -CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 CONFIG_AIC7XXX_RESET_DELAY_MS=15000 CONFIG_AIC7XXX_DEBUG_ENABLE=y CONFIG_AIC7XXX_DEBUG_MASK=0 CONFIG_AIC7XXX_REG_PRETTY_PRINT=y # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set -CONFIG_SCSI_AIC94XX=y -# CONFIG_AIC94XX_DEBUG is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set @@ -482,6 +503,7 @@ CONFIG_SCSI_AIC94XX=y # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_QLOGIC_1280 is not set @@ -492,147 +514,81 @@ CONFIG_SCSI_AIC94XX=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# # CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support # -# CONFIG_IEEE1394 is not set # -# I2O device support +# Enable only one of the two stacks, unless you know what you are doing # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set # CONFIG_I2O is not set - -# -# Network device support -# CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set +CONFIG_DUMMY=m +CONFIG_BONDING=m +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# ARCnet devices -# +# CONFIG_VETH is not set # CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -# CONFIG_BROADCOM_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y +# CONFIG_AX88796 is not set CONFIG_SGI_O2MACE_ETH=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set # CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +CONFIG_TULIP_MMIO=y +# CONFIG_TULIP_NAPI is not set +# CONFIG_DE4X5 is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_DM9102 is not set +# CONFIG_ULI526X is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_QLA3XXX=y -# CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3=y -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -CONFIG_NETXEN_NIC=y - -# -# Token Ring devices -# +# CONFIG_B44 is not set +# CONFIG_ATL2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -640,6 +596,7 @@ CONFIG_NETXEN_NIC=y # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -649,16 +606,32 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set +CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -669,8 +642,8 @@ CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_MACEPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set +CONFIG_SERIO_MACEPS2=y +CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=y # CONFIG_GAMEPORT is not set @@ -678,10 +651,13 @@ CONFIG_SERIO_RAW=y # Character devices # CONFIG_VT=y +# CONFIG_CONSOLE_TRANSLATIONS is not set CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -702,192 +678,304 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set +CONFIG_HW_RANDOM=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set # -# I2C support +# Watchdog Device Drivers # -# CONFIG_I2C is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set # -# SPI support +# PCI-based Watchdog Cards # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set +CONFIG_SSB_POSSIBLE=y # -# Dallas's 1-wire bus +# Sonics Silicon Backplane # -# CONFIG_W1 is not set +# CONFIG_SSB is not set # -# Hardware Monitoring support +# Multifunction device drivers # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # -# CONFIG_VIDEO_DEV is not set # -# Digital Video Broadcasting Devices +# Multimedia core support # -# CONFIG_DVB is not set +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=m # -# Graphics support +# Multimedia drivers # -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_VIVI=m +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_STRADIS is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_GEMTEK_PCI is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_MAESTRO is not set +CONFIG_DAB=y # -# Console display driver support +# Graphics support # -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +CONFIG_FB_GBE=y +CONFIG_FB_GBE_MEM=4 +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Sound +# Display device support # -# CONFIG_SOUND is not set +# CONFIG_DISPLAY_SUPPORT is not set # -# HID Devices +# Console display driver support # +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_SGI_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set # -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support +# Special HID drivers # +CONFIG_HID_COMPAT=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set - -# -# LED devices -# +# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_DEBUG is not set # -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# RTC interfaces # +# CONFIG_RTC_INTF_SYSFS is not set +# CONFIG_RTC_INTF_PROC is not set +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# Real Time Clock +# SPI RTC drivers # -# CONFIG_RTC_CLASS is not set # -# DMA Engine support +# Platform RTC drivers # -# CONFIG_DMA_ENGINE is not set +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization +# on-CPU RTC drivers # +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems # CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m CONFIG_GENERIC_ACL=y # # CD-ROM/DVD Filesystems # -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set # @@ -896,11 +984,11 @@ CONFIG_GENERIC_ACL=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=y # @@ -916,33 +1004,42 @@ CONFIG_CONFIGFS_FS=y # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -953,45 +1050,83 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Distributed Lock Manager -# -CONFIG_DLM=y -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -1000,51 +1135,99 @@ CONFIG_CMDLINE="" CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_NULL=y + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_PCBC=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y -CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_WP512=y + +# +# Ciphers +# CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y CONFIG_CRYPTO_CAST5=y CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=y CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CAMELLIA=y +# CONFIG_CRYPTO_LZO is not set # -# Hardware crypto devices +# Random Number Generation # +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set # # Library routines @@ -1052,10 +1235,15 @@ CONFIG_CRYPTO_CAMELLIA=y CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y +CONFIG_AUDIT_GENERIC=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 74daa0cf87e6..1ecdd3b65dc7 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.23-rc2 -# Tue Aug 7 12:59:29 2007 +# Linux kernel version: 2.6.28-rc6 +# Mon Dec 1 08:08:19 2008 # CONFIG_MIPS=y @@ -11,20 +11,25 @@ CONFIG_MIPS=y CONFIG_ZONE_DMA=y # CONFIG_MACH_ALCHEMY is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_MACH_EMMA is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set @@ -35,13 +40,14 @@ CONFIG_MIPS_MALTA=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y @@ -51,21 +57,26 @@ CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_BOOT_RAW=y CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_GENERIC_ISA_DMA=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_I8259=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y # CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y +CONFIG_IRQ_GIC=y +CONFIG_MIPS_BOARDS_GEN=y CONFIG_PCI_GT64XXX_PCI0=y CONFIG_SWAP_IO_SPACE=y CONFIG_BOOT_ELF32=y @@ -74,10 +85,6 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y @@ -91,6 +98,7 @@ CONFIG_CPU_MIPS32_R2=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -108,6 +116,7 @@ CONFIG_CPU_MIPSR2=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -125,6 +134,8 @@ CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_SMP=y # CONFIG_MIPS_MT_SMTC is not set CONFIG_MIPS_MT=y +# CONFIG_SCHED_SMT is not set +CONFIG_SYS_SUPPORTS_SCHED_SMT=y CONFIG_SYS_SUPPORTS_MULTITHREADING=y CONFIG_MIPS_MT_FPAFF=y # CONFIG_MIPS_VPE_LOADER is not set @@ -132,7 +143,6 @@ CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_SMARTMIPS is not set CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_SRS=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y @@ -140,22 +150,30 @@ CONFIG_IRQ_PER_CPU=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_SMARTMIPS=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_SMP=y +CONFIG_SMP_UP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS_DEFAULT_2=y CONFIG_NR_CPUS=2 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set CONFIG_HZ_100=y # CONFIG_HZ_128 is not set @@ -168,7 +186,6 @@ CONFIG_HZ=100 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -CONFIG_PREEMPT_BKL=y # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y @@ -189,13 +206,19 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_CPUSETS is not set +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +CONFIG_PID_NS=y # CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y @@ -207,6 +230,8 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -215,14 +240,23 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y @@ -234,6 +268,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -247,19 +282,19 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y CONFIG_MMU=y CONFIG_I8253=y - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -267,6 +302,8 @@ CONFIG_I8253=y # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y @@ -274,12 +311,7 @@ CONFIG_TRAD_SIGNALS=y # Power management options # CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set - -# -# Networking -# CONFIG_NET=y # @@ -292,6 +324,8 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -323,42 +357,13 @@ CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=m CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -375,11 +380,15 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m # CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y # @@ -388,12 +397,12 @@ CONFIG_BRIDGE_NETFILTER=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=m CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m CONFIG_NF_CT_PROTO_UDPLITE=m @@ -407,18 +416,22 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m -# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m @@ -427,40 +440,76 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m # CONFIG_NETFILTER_XT_MATCH_DSCP is not set CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -468,11 +517,13 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_TFTP=m @@ -481,40 +532,34 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration (EXPERIMENTAL) +# IPv6: Netfilter Configuration # CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_OWNER=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -523,6 +568,7 @@ CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m @@ -535,6 +581,7 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=m # CONFIG_SCTP_DBG_MSG is not set @@ -544,8 +591,12 @@ CONFIG_IP_SCTP=m CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set +CONFIG_STP=m +CONFIG_GARP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set @@ -559,12 +610,7 @@ CONFIG_IPDDP_DECAP=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y # # Queueing/Scheduling @@ -573,7 +619,7 @@ CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RR=m +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -597,6 +643,7 @@ CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m # CONFIG_NET_EMATCH is not set CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y @@ -604,37 +651,51 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m -CONFIG_NET_CLS_POLICE=y +CONFIG_NET_ACT_SKBEDIT=m CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +CONFIG_PHONET=m CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y CONFIG_CFG80211=m +CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_MAC80211=m -# CONFIG_MAC80211_DEBUG is not set + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT="pid" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_IEEE80211=m # CONFIG_IEEE80211_DEBUG is not set CONFIG_IEEE80211_CRYPT_WEP=m CONFIG_IEEE80211_CRYPT_CCMP=m CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=m +CONFIG_RFKILL_LEDS=y # CONFIG_NET_9P is not set # @@ -644,9 +705,12 @@ CONFIG_RFKILL_INPUT=m # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m CONFIG_MTD=y @@ -655,6 +719,7 @@ CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -667,6 +732,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +CONFIG_MTD_OOPS=m # # RAM/ROM/Flash chip drivers @@ -701,6 +767,7 @@ CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_START=0x0 CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -748,25 +815,26 @@ CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -775,24 +843,25 @@ CONFIG_IDE_PROC_FS=y # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDEPCI_SHARE_IRQ is not set CONFIG_IDEPCI_PCIBUS_ORDER=y # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_ONLYDISK is not set # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_BLK_DEV_AMD74XX is not set # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set @@ -808,10 +877,7 @@ CONFIG_BLK_DEV_IT8213=m # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set CONFIG_BLK_DEV_TC86C001=m -# CONFIG_IDE_ARM is not set CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support @@ -848,8 +914,10 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_FC_ATTRS=m +# CONFIG_SCSI_FC_TGT_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=m # CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=m CONFIG_BLK_DEV_3W_XXXX_RAID=m @@ -866,6 +934,7 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set @@ -876,6 +945,7 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_QLOGIC_1280 is not set @@ -887,6 +957,7 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m @@ -905,32 +976,28 @@ CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_EMC=m -CONFIG_DM_MULTIPATH_RDAC=m # CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set # -# Fusion MPT device support +# IEEE 1394 (FireWire) support # -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # -# IEEE 1394 (FireWire) support +# Enable only one of the two stacks, unless you know what you are doing # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -CONFIG_NETDEVICES_MULTIQUEUE=y CONFIG_IFB=m CONFIG_DUMMY=m CONFIG_BONDING=m CONFIG_MACVLAN=m CONFIG_EQUALIZER=m CONFIG_TUN=m +CONFIG_VETH=m # CONFIG_ARCNET is not set CONFIG_PHYLIB=m @@ -946,26 +1013,34 @@ CONFIG_VITESSE_PHY=m CONFIG_SMSC_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_ICPLUS_PHY=m -# CONFIG_FIXED_PHY is not set +CONFIG_REALTEK_PHY=m +CONFIG_MDIO_BITBANG=m CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_AX88796=m +# CONFIG_AX88796_93CX6 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y -# CONFIG_PCNET32_NAPI is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set CONFIG_TC35815=m -# CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set @@ -973,16 +1048,21 @@ CONFIG_TC35815=m # CONFIG_NE2K_PCI is not set # CONFIG_8139CP is not set # CONFIG_8139TOO is not set +# CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -995,14 +1075,24 @@ CONFIG_NETDEV_1000=y # CONFIG_BNX2 is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set CONFIG_CHELSIO_T3=m +# CONFIG_ENIC is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set CONFIG_NETXEN_NIC=m +# CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set # CONFIG_TR is not set # @@ -1022,6 +1112,7 @@ CONFIG_IPW2200_QOS=y # CONFIG_IPW2200_DEBUG is not set CONFIG_LIBERTAS=m # CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set CONFIG_HERMES=m CONFIG_PLX_HERMES=m CONFIG_TMD_HERMES=m @@ -1030,25 +1121,30 @@ CONFIG_PCI_HERMES=m CONFIG_ATMEL=m CONFIG_PCI_ATMEL=m CONFIG_PRISM54=m +# CONFIG_RTL8180 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH9K is not set +# CONFIG_IWLCORE is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_IWLAGN is not set +# CONFIG_IWL3945 is not set CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m -CONFIG_BCM43XX=m -CONFIG_BCM43XX_DEBUG=y -CONFIG_BCM43XX_DMA=y -CONFIG_BCM43XX_PIO=y -CONFIG_BCM43XX_DMA_AND_PIO_MODE=y -# CONFIG_BCM43XX_DMA_MODE is not set -# CONFIG_BCM43XX_PIO_MODE is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_RT2X00 is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -1070,7 +1166,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -1099,10 +1194,13 @@ CONFIG_SERIO_SERPORT=y # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -1124,101 +1222,165 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=m -CONFIG_RTC=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# # CONFIG_DAB is not set # # Graphics support # +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=m # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# Enable Host or Gadget support to see Inventra options # # -# USB Gadget Support +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set -# CONFIG_NEW_LEDS is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # -# DMA Engine support +# RTC interfaces # -# CONFIG_DMA_ENGINE is not set +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# DMA Clients +# SPI RTC drivers # # -# DMA Devices +# Platform RTC drivers # +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# Userspace I/O +# on-CPU RTC drivers # +# CONFIG_DMADEVICES is not set CONFIG_UIO=m CONFIG_UIO_CIF=m +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -1230,9 +1392,8 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set @@ -1246,22 +1407,22 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y # CONFIG_XFS_RT is not set -# CONFIG_GFS2_FS is not set +# CONFIG_XFS_DEBUG is not set # CONFIG_OCFS2_FS is not set -CONFIG_MINIX_FS=m -CONFIG_ROMFS_FS=m +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set CONFIG_FUSE_FS=m @@ -1291,11 +1452,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -1312,46 +1473,48 @@ CONFIG_EFS_FS=m CONFIG_JFFS2_FS=m CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_POSIX_ACL=y CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_UBIFS_FS is not set CONFIG_CRAMFS=m CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=m CONFIG_SYSV_FS=m CONFIG_UFS_FS=m # CONFIG_UFS_FS_WRITE is not set # CONFIG_UFS_DEBUG is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1365,10 +1528,6 @@ CONFIG_SUNRPC=y # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m @@ -1409,29 +1568,30 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set -# -# Profiling support -# -# CONFIG_PROFILING is not set - # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -1439,51 +1599,103 @@ CONFIG_CMDLINE="" # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m CONFIG_ASYNC_MEMCPY=m CONFIG_ASYNC_XOR=m CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ABLKCIPHER=m -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set # # Library routines @@ -1491,7 +1703,8 @@ CONFIG_CRYPTO_HW=y CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set CONFIG_CRC16=m -# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig new file mode 100644 index 000000000000..d9536522cff5 --- /dev/null +++ b/arch/mips/configs/pnx8335-stb225_defconfig @@ -0,0 +1,1149 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26 +# Sat Jul 26 09:02:59 2008 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +CONFIG_NXP_STB225=y +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_WR_PPMC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SOC_PNX833X=y +CONFIG_SOC_PNX8335=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_128=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=128 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=y +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x18000000 +CONFIG_MTD_PHYSMAP_LEN=0x04000000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PNX8XXX=y +CONFIG_SERIAL_PNX8XXX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DVB_CORE=y +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_DRX397XD is not set +# CONFIG_DVB_L64781 is not set +CONFIG_DVB_TDA1004X=y +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_TDA10048 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +# CONFIG_SND_PCM_XRUN_DEBUG is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_MIPS=y +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=m +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SAMPLES is not set +# CONFIG_KERNEL_TESTS is not set +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_PRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/mips/emma/Kconfig b/arch/mips/emma/Kconfig new file mode 100644 index 000000000000..9669c72123c9 --- /dev/null +++ b/arch/mips/emma/Kconfig @@ -0,0 +1,29 @@ +choice + prompt "Machine type" + depends on MACH_EMMA + default NEC_MARKEINS + +config NEC_MARKEINS + bool "NEC EMMA2RH Mark-eins board" + select SOC_EMMA2RH + select HW_HAS_PCI + help + This enables support for the NEC Electronics Mark-eins boards. + +endchoice + +config SOC_EMMA2RH + bool + select SOC_EMMA + select SYS_HAS_CPU_R5500 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + +config SOC_EMMA + bool + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SWAP_IO_SPACE + select SYS_SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/emma/common/Makefile b/arch/mips/emma/common/Makefile new file mode 100644 index 000000000000..c392d28c1ef1 --- /dev/null +++ b/arch/mips/emma/common/Makefile @@ -0,0 +1,13 @@ +# +# arch/mips/emma2rh/common/Makefile +# Makefile for the common code of NEC EMMA2RH based board. +# +# Copyright (C) NEC Electronics Corporation 2005-2006 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# + +obj-$(CONFIG_NEC_MARKEINS) += prom.o diff --git a/arch/mips/emma/common/prom.c b/arch/mips/emma/common/prom.c new file mode 100644 index 000000000000..120f53fbdb45 --- /dev/null +++ b/arch/mips/emma/common/prom.c @@ -0,0 +1,72 @@ +/* + * arch/mips/emma2rh/common/prom.c + * This file is prom file. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/common/prom.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include + +#include +#include +#include + +const char *get_system_type(void) +{ +#ifdef CONFIG_NEC_MARKEINS + return "NEC EMMA2RH Mark-eins"; +#else +#error Unknown NEC board +#endif +} + +/* [jsun@junsun.net] PMON passes arguments in C main() style */ +void __init prom_init(void) +{ + int argc = fw_arg0; + char **arg = (char **)fw_arg1; + int i; + + /* if user passes kernel args, ignore the default one */ + if (argc > 1) + arcs_cmdline[0] = '\0'; + + /* arg[0] is "g", the rest is boot parameters */ + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + +#ifdef CONFIG_NEC_MARKEINS + add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); +#else +#error Unknown NEC board +#endif +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/emma/markeins/Makefile b/arch/mips/emma/markeins/Makefile new file mode 100644 index 000000000000..16e0017ba919 --- /dev/null +++ b/arch/mips/emma/markeins/Makefile @@ -0,0 +1,13 @@ +# +# arch/mips/emma2rh/markeins/Makefile +# Makefile for the common code of NEC EMMA2RH based board. +# +# Copyright (C) NEC Electronics Corporation 2005-2006 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# + +obj-$(CONFIG_NEC_MARKEINS) += irq.o setup.o led.o platform.o diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c new file mode 100644 index 000000000000..c2583ecc93cf --- /dev/null +++ b/arch/mips/emma/markeins/irq.c @@ -0,0 +1,331 @@ +/* + * arch/mips/emma2rh/markeins/irq.c + * This file defines the irq handler for EMMA2RH. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static void emma2rh_irq_enable(unsigned int irq) +{ + u32 reg_value; + u32 reg_bitmask; + u32 reg_index; + + irq -= EMMA2RH_IRQ_BASE; + + reg_index = EMMA2RH_BHIF_INT_EN_0 + + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); + reg_value = emma2rh_in32(reg_index); + reg_bitmask = 0x1 << (irq % 32); + emma2rh_out32(reg_index, reg_value | reg_bitmask); +} + +static void emma2rh_irq_disable(unsigned int irq) +{ + u32 reg_value; + u32 reg_bitmask; + u32 reg_index; + + irq -= EMMA2RH_IRQ_BASE; + + reg_index = EMMA2RH_BHIF_INT_EN_0 + + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); + reg_value = emma2rh_in32(reg_index); + reg_bitmask = 0x1 << (irq % 32); + emma2rh_out32(reg_index, reg_value & ~reg_bitmask); +} + +struct irq_chip emma2rh_irq_controller = { + .name = "emma2rh_irq", + .ack = emma2rh_irq_disable, + .mask = emma2rh_irq_disable, + .mask_ack = emma2rh_irq_disable, + .unmask = emma2rh_irq_enable, +}; + +void emma2rh_irq_init(void) +{ + u32 i; + + for (i = 0; i < NUM_EMMA2RH_IRQ; i++) + set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i, + &emma2rh_irq_controller, + handle_level_irq); +} + +static void emma2rh_sw_irq_enable(unsigned int irq) +{ + u32 reg; + + irq -= EMMA2RH_SW_IRQ_BASE; + + reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); + reg |= 1 << irq; + emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); +} + +static void emma2rh_sw_irq_disable(unsigned int irq) +{ + u32 reg; + + irq -= EMMA2RH_SW_IRQ_BASE; + + reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); +} + +struct irq_chip emma2rh_sw_irq_controller = { + .name = "emma2rh_sw_irq", + .ack = emma2rh_sw_irq_disable, + .mask = emma2rh_sw_irq_disable, + .mask_ack = emma2rh_sw_irq_disable, + .unmask = emma2rh_sw_irq_enable, +}; + +void emma2rh_sw_irq_init(void) +{ + u32 i; + + for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) + set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i, + &emma2rh_sw_irq_controller, + handle_level_irq); +} + +static void emma2rh_gpio_irq_enable(unsigned int irq) +{ + u32 reg; + + irq -= EMMA2RH_GPIO_IRQ_BASE; + + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg |= 1 << irq; + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); +} + +static void emma2rh_gpio_irq_disable(unsigned int irq) +{ + u32 reg; + + irq -= EMMA2RH_GPIO_IRQ_BASE; + + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); +} + +static void emma2rh_gpio_irq_ack(unsigned int irq) +{ + u32 reg; + + irq -= EMMA2RH_GPIO_IRQ_BASE; + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); + + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); +} + +static void emma2rh_gpio_irq_end(unsigned int irq) +{ + u32 reg; + + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + + irq -= EMMA2RH_GPIO_IRQ_BASE; + + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg |= 1 << irq; + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); + } +} + +struct irq_chip emma2rh_gpio_irq_controller = { + .name = "emma2rh_gpio_irq", + .ack = emma2rh_gpio_irq_ack, + .mask = emma2rh_gpio_irq_disable, + .mask_ack = emma2rh_gpio_irq_ack, + .unmask = emma2rh_gpio_irq_enable, + .end = emma2rh_gpio_irq_end, +}; + +void emma2rh_gpio_irq_init(void) +{ + u32 i; + + for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) + set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i, + &emma2rh_gpio_irq_controller); +} + +static struct irqaction irq_cascade = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = "cascade", + .dev_id = NULL, + .next = NULL, +}; + +/* + * the first level int-handler will jump here if it is a emma2rh irq + */ +void emma2rh_irq_dispatch(void) +{ + u32 intStatus; + u32 bitmask; + u32 i; + + intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) & + emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); + +#ifdef EMMA2RH_SW_CASCADE + if (intStatus & + (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + u32 swIntStatus; + swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) + & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); + for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { + if (swIntStatus & bitmask) { + do_IRQ(EMMA2RH_SW_IRQ_BASE + i); + return; + } + } + } +#endif + + for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { + if (intStatus & bitmask) { + do_IRQ(EMMA2RH_IRQ_BASE + i); + return; + } + } + + intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) & + emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); + +#ifdef EMMA2RH_GPIO_CASCADE + if (intStatus & + (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + u32 gpioIntStatus; + gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) + & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { + if (gpioIntStatus & bitmask) { + do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i); + return; + } + } + } +#endif + + for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { + if (intStatus & bitmask) { + do_IRQ(EMMA2RH_IRQ_BASE + i); + return; + } + } + + intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) & + emma2rh_in32(EMMA2RH_BHIF_INT_EN_2); + + for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { + if (intStatus & bitmask) { + do_IRQ(EMMA2RH_IRQ_BASE + i); + return; + } + } +} + +void __init arch_init_irq(void) +{ + u32 reg; + + /* by default, interrupts are disabled. */ + emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0); + emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0); + emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0); + emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0); + emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0); + emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0); + emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0); + + clear_c0_status(0xff00); + set_c0_status(0x0400); + +#define GPIO_PCI (0xf<<15) + /* setup GPIO interrupt for PCI interface */ + /* direction input */ + reg = emma2rh_in32(EMMA2RH_GPIO_DIR); + emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI); + /* disable interrupt */ + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI); + /* level triggerd */ + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE); + emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI); + reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A); + emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI)); + /* interrupt clear */ + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI); + + /* init all controllers */ + emma2rh_irq_init(); + emma2rh_sw_irq_init(); + emma2rh_gpio_irq_init(); + mips_cpu_irq_init(); + + /* setup cascade interrupts */ + setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); + setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(CPU_IRQ_BASE + 7); + else if (pending & STATUSF_IP2) + emma2rh_irq_dispatch(); + else if (pending & STATUSF_IP1) + do_IRQ(CPU_IRQ_BASE + 1); + else if (pending & STATUSF_IP0) + do_IRQ(CPU_IRQ_BASE + 0); + else + spurious_interrupt(); +} diff --git a/arch/mips/emma/markeins/led.c b/arch/mips/emma/markeins/led.c new file mode 100644 index 000000000000..377a181b6561 --- /dev/null +++ b/arch/mips/emma/markeins/led.c @@ -0,0 +1,60 @@ +/* + * arch/mips/emma2rh/markeins/led.c + * This file defines the led display for Mark-eins. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include + +const unsigned long clear = 0x20202020; + +#define LED_BASE 0xb1400038 + +void markeins_led_clear(void) +{ + emma2rh_out32(LED_BASE, clear); + emma2rh_out32(LED_BASE + 4, clear); +} + +void markeins_led(const char *str) +{ + int i; + int len = strlen(str); + + markeins_led_clear(); + if (len > 8) + len = 8; + + if (emma2rh_in32(0xb0000800) & (0x1 << 18)) + for (i = 0; i < len; i++) + emma2rh_out8(LED_BASE + i, str[i]); + else + for (i = 0; i < len; i++) + emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)), + str[i]); +} + +void markeins_led_hex(u32 val) +{ + char str[10]; + + sprintf(str, "%08x", val); + markeins_led(str); +} diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c new file mode 100644 index 000000000000..88e87f6b3442 --- /dev/null +++ b/arch/mips/emma/markeins/platform.c @@ -0,0 +1,191 @@ +/* + * arch/mips/emma2rh/markeins/platofrm.c + * This file sets up platform devices for EMMA2RH Mark-eins. + * + * Copyright(C) MontaVista Software Inc, 2006 + * + * Author: dmitry pervushin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + +#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */ + +static struct resource i2c_emma_resources_0[] = { + { + .name = NULL, + .start = EMMA2RH_IRQ_PIIC0, + .end = EMMA2RH_IRQ_PIIC0, + .flags = IORESOURCE_IRQ + }, { + .name = NULL, + .start = EMMA2RH_PIIC0_BASE, + .end = EMMA2RH_PIIC0_BASE + 0x1000, + .flags = 0 + }, +}; + +struct resource i2c_emma_resources_1[] = { + { + .name = NULL, + .start = EMMA2RH_IRQ_PIIC1, + .end = EMMA2RH_IRQ_PIIC1, + .flags = IORESOURCE_IRQ + }, { + .name = NULL, + .start = EMMA2RH_PIIC1_BASE, + .end = EMMA2RH_PIIC1_BASE + 0x1000, + .flags = 0 + }, +}; + +struct resource i2c_emma_resources_2[] = { + { + .name = NULL, + .start = EMMA2RH_IRQ_PIIC2, + .end = EMMA2RH_IRQ_PIIC2, + .flags = IORESOURCE_IRQ + }, { + .name = NULL, + .start = EMMA2RH_PIIC2_BASE, + .end = EMMA2RH_PIIC2_BASE + 0x1000, + .flags = 0 + }, +}; + +struct platform_device i2c_emma_devices[] = { + [0] = { + .name = I2C_EMMA2RH, + .id = 0, + .resource = i2c_emma_resources_0, + .num_resources = ARRAY_SIZE(i2c_emma_resources_0), + }, + [1] = { + .name = I2C_EMMA2RH, + .id = 1, + .resource = i2c_emma_resources_1, + .num_resources = ARRAY_SIZE(i2c_emma_resources_1), + }, + [2] = { + .name = I2C_EMMA2RH, + .id = 2, + .resource = i2c_emma_resources_2, + .num_resources = ARRAY_SIZE(i2c_emma_resources_2), + }, +}; + +#define EMMA2RH_SERIAL_CLOCK 18544000 +#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST + +static struct plat_serial8250_port platform_serial_ports[] = { + [0] = { + .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), + .irq = EMMA2RH_IRQ_PFUR0, + .uartclk = EMMA2RH_SERIAL_CLOCK, + .regshift = 4, + .iotype = UPIO_MEM, + .flags = EMMA2RH_SERIAL_FLAGS, + }, [1] = { + .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), + .irq = EMMA2RH_IRQ_PFUR1, + .uartclk = EMMA2RH_SERIAL_CLOCK, + .regshift = 4, + .iotype = UPIO_MEM, + .flags = EMMA2RH_SERIAL_FLAGS, + }, [2] = { + .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), + .irq = EMMA2RH_IRQ_PFUR2, + .uartclk = EMMA2RH_SERIAL_CLOCK, + .regshift = 4, + .iotype = UPIO_MEM, + .flags = EMMA2RH_SERIAL_FLAGS, + }, [3] = { + .flags = 0, + }, +}; + +static struct platform_device serial_emma = { + .name = "serial8250", + .dev = { + .platform_data = &platform_serial_ports, + }, +}; + +static struct platform_device *devices[] = { + &i2c_emma_devices[0], + &i2c_emma_devices[1], + &i2c_emma_devices[2], + &serial_emma, +}; + +static struct mtd_partition markeins_parts[] = { + [0] = { + .name = "RootFS", + .offset = 0x00000000, + .size = 0x00c00000, + }, + [1] = { + .name = "boot code area", + .offset = MTDPART_OFS_APPEND, + .size = 0x00100000, + }, + [2] = { + .name = "kernel image", + .offset = MTDPART_OFS_APPEND, + .size = 0x00300000, + }, + [3] = { + .name = "RootFS2", + .offset = MTDPART_OFS_APPEND, + .size = 0x00c00000, + }, + [4] = { + .name = "boot code area2", + .offset = MTDPART_OFS_APPEND, + .size = 0x00100000, + }, + [5] = { + .name = "kernel image2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static int __init platform_devices_setup(void) +{ + physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts)); + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +arch_initcall(platform_devices_setup); + diff --git a/arch/mips/emma/markeins/setup.c b/arch/mips/emma/markeins/setup.c new file mode 100644 index 000000000000..67f456500084 --- /dev/null +++ b/arch/mips/emma/markeins/setup.c @@ -0,0 +1,135 @@ +/* + * arch/mips/emma2rh/markeins/setup.c + * This file is setup for EMMA2RH Mark-eins. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c. + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include + +#include +#include + +#include + +#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ + +extern void markeins_led(const char *); + +static int bus_frequency = 0; + +static void markeins_machine_restart(char *command) +{ + static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000; + + printk("cannot EMMA2RH Mark-eins restart.\n"); + markeins_led("restart."); + back_to_prom(); +} + +static void markeins_machine_halt(void) +{ + printk("EMMA2RH Mark-eins halted.\n"); + markeins_led("halted."); + while (1) ; +} + +static void markeins_machine_power_off(void) +{ + printk("EMMA2RH Mark-eins halted. Please turn off the power.\n"); + markeins_led("poweroff."); + while (1) ; +} + +static unsigned long __initdata emma2rh_clock[4] = { + 166500000, 187312500, 199800000, 210600000 +}; + +static unsigned int __init detect_bus_frequency(unsigned long rtc_base) +{ + u32 reg; + + /* detect from boot strap */ + reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); + reg = (reg >> 4) & 0x3; + + return emma2rh_clock[reg]; +} + +void __init plat_time_init(void) +{ + u32 reg; + if (bus_frequency == 0) + bus_frequency = detect_bus_frequency(0); + + reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); + if ((reg & 0x3) == 0) + reg = (reg >> 6) & 0x3; + else { + reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL); + reg = (reg >> 4) & 0x3; + } + mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2; +} + +static void markeins_board_init(void); +extern void markeins_irq_setup(void); + +static void inline __init markeins_sio_setup(void) +{ +} + +void __init plat_mem_setup(void) +{ + /* initialize board - we don't trust the loader */ + markeins_board_init(); + + set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); + + _machine_restart = markeins_machine_restart; + _machine_halt = markeins_machine_halt; + pm_power_off = markeins_machine_power_off; + + /* setup resource limits */ + ioport_resource.start = EMMA2RH_PCI_IO_BASE; + ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1; + iomem_resource.start = EMMA2RH_IO_BASE; + iomem_resource.end = EMMA2RH_ROM_BASE - 1; + + /* Reboot on panic */ + panic_timeout = 180; + + markeins_sio_setup(); +} + +static void __init markeins_board_init(void) +{ + u32 val; + + val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */ + emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa); + val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */ + emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */ + emma2rh_out32(EMMA2RH_PCI_CONTROL, 0); + + markeins_led("MVL E2RH"); +} diff --git a/arch/mips/emma2rh/common/Makefile b/arch/mips/emma2rh/common/Makefile deleted file mode 100644 index 859121b3867d..000000000000 --- a/arch/mips/emma2rh/common/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# arch/mips/emma2rh/common/Makefile -# Makefile for the common code of NEC EMMA2RH based board. -# -# Copyright (C) NEC Electronics Corporation 2005-2006 -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# - -obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c deleted file mode 100644 index 91cbd959ab67..000000000000 --- a/arch/mips/emma2rh/common/irq.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * arch/mips/emma2rh/common/irq.c - * This file is common irq dispatcher. - * - * Copyright (C) NEC Electronics Corporation 2005-2006 - * - * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -/* - * the first level int-handler will jump here if it is a emma2rh irq - */ -void emma2rh_irq_dispatch(void) -{ - u32 intStatus; - u32 bitmask; - u32 i; - - intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) - & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); - -#ifdef EMMA2RH_SW_CASCADE - if (intStatus & - (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { - u32 swIntStatus; - swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) - & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); - for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { - if (swIntStatus & bitmask) { - do_IRQ(EMMA2RH_SW_IRQ_BASE + i); - return; - } - } - } -#endif - - for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { - if (intStatus & bitmask) { - do_IRQ(EMMA2RH_IRQ_BASE + i); - return; - } - } - - intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) - & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); - -#ifdef EMMA2RH_GPIO_CASCADE - if (intStatus & - (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { - u32 gpioIntStatus; - gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) - & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { - if (gpioIntStatus & bitmask) { - do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i); - return; - } - } - } -#endif - - for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { - if (intStatus & bitmask) { - do_IRQ(EMMA2RH_IRQ_BASE + i); - return; - } - } - - intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) - & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2); - - for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { - if (intStatus & bitmask) { - do_IRQ(EMMA2RH_IRQ_BASE + i); - return; - } - } -} diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c deleted file mode 100644 index 96df37b77759..000000000000 --- a/arch/mips/emma2rh/common/irq_emma2rh.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * arch/mips/emma2rh/common/irq_emma2rh.c - * This file defines the irq handler for EMMA2RH. - * - * Copyright (C) NEC Electronics Corporation 2005-2006 - * - * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * EMMA2RH defines 64 IRQs. - * - * This file exports one function: - * emma2rh_irq_init(u32 irq_base); - */ - -#include -#include -#include - -#include - -#include - -/* number of total irqs supported by EMMA2RH */ -#define NUM_EMMA2RH_IRQ 96 - -static int emma2rh_irq_base = -1; - -void ll_emma2rh_irq_enable(int); -void ll_emma2rh_irq_disable(int); - -static void emma2rh_irq_enable(unsigned int irq) -{ - ll_emma2rh_irq_enable(irq - emma2rh_irq_base); -} - -static void emma2rh_irq_disable(unsigned int irq) -{ - ll_emma2rh_irq_disable(irq - emma2rh_irq_base); -} - -struct irq_chip emma2rh_irq_controller = { - .name = "emma2rh_irq", - .ack = emma2rh_irq_disable, - .mask = emma2rh_irq_disable, - .mask_ack = emma2rh_irq_disable, - .unmask = emma2rh_irq_enable, -}; - -void emma2rh_irq_init(u32 irq_base) -{ - u32 i; - - for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) - set_irq_chip_and_handler(i, &emma2rh_irq_controller, - handle_level_irq); - - emma2rh_irq_base = irq_base; -} - -void ll_emma2rh_irq_enable(int emma2rh_irq) -{ - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - reg_index = EMMA2RH_BHIF_INT_EN_0 - + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) - * (emma2rh_irq / 32); - reg_value = emma2rh_in32(reg_index); - reg_bitmask = 0x1 << (emma2rh_irq % 32); - db_assert((reg_value & reg_bitmask) == 0); - emma2rh_out32(reg_index, reg_value | reg_bitmask); -} - -void ll_emma2rh_irq_disable(int emma2rh_irq) -{ - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - reg_index = EMMA2RH_BHIF_INT_EN_0 - + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) - * (emma2rh_irq / 32); - reg_value = emma2rh_in32(reg_index); - reg_bitmask = 0x1 << (emma2rh_irq % 32); - db_assert((reg_value & reg_bitmask) != 0); - emma2rh_out32(reg_index, reg_value & ~reg_bitmask); -} diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c deleted file mode 100644 index e14a2e3d8842..000000000000 --- a/arch/mips/emma2rh/common/prom.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * arch/mips/emma2rh/common/prom.c - * This file is prom file. - * - * Copyright (C) NEC Electronics Corporation 2004-2006 - * - * This file is based on the arch/mips/ddb5xxx/common/prom.c - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include - -#include -#include -#include - -const char *get_system_type(void) -{ -#if defined(CONFIG_MARKEINS) - return "NEC EMMA2RH Mark-eins"; -#else -#error Unknown NEC board -#endif -} - -/* [jsun@junsun.net] PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **)fw_arg1; - int i; - - /* if user passes kernel args, ignore the default one */ - if (argc > 1) - arcs_cmdline[0] = '\0'; - - /* arg[0] is "g", the rest is boot parameters */ - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - -#if defined(CONFIG_MARKEINS) - add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); -#else -#error Unknown NEC board -#endif -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/emma2rh/markeins/Makefile b/arch/mips/emma2rh/markeins/Makefile deleted file mode 100644 index 14fc268b175c..000000000000 --- a/arch/mips/emma2rh/markeins/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# arch/mips/emma2rh/markeins/Makefile -# Makefile for the common code of NEC EMMA2RH based board. -# -# Copyright (C) NEC Electronics Corporation 2005-2006 -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# - -obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c deleted file mode 100644 index 6bcf6a06367a..000000000000 --- a/arch/mips/emma2rh/markeins/irq.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * arch/mips/emma2rh/markeins/irq.c - * This file defines the irq handler for EMMA2RH. - * - * Copyright (C) NEC Electronics Corporation 2004-2006 - * - * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -/* - * IRQ mapping - * - * 0-7: 8 CPU interrupts - * 0 - software interrupt 0 - * 1 - software interrupt 1 - * 2 - most Vrc5477 interrupts are routed to this pin - * 3 - (optional) some other interrupts routed to this pin for debugg - * 4 - not used - * 5 - not used - * 6 - not used - * 7 - cpu timer (used by default) - * - */ - -extern void emma2rh_sw_irq_init(u32 base); -extern void emma2rh_gpio_irq_init(u32 base); -extern void emma2rh_irq_init(u32 base); -extern void emma2rh_irq_dispatch(void); - -static struct irqaction irq_cascade = { - .handler = no_action, - .flags = 0, - .mask = CPU_MASK_NONE, - .name = "cascade", - .dev_id = NULL, - .next = NULL, -}; - -void __init arch_init_irq(void) -{ - u32 reg; - - db_run(printk("markeins_irq_setup invoked.\n")); - - /* by default, interrupts are disabled. */ - emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0); - emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0); - emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0); - emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0); - emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0); - emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0); - emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0); - - clear_c0_status(0xff00); - set_c0_status(0x0400); - -#define GPIO_PCI (0xf<<15) - /* setup GPIO interrupt for PCI interface */ - /* direction input */ - reg = emma2rh_in32(EMMA2RH_GPIO_DIR); - emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI); - /* disable interrupt */ - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI); - /* level triggerd */ - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE); - emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI); - reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A); - emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI)); - /* interrupt clear */ - emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI); - - /* init all controllers */ - emma2rh_irq_init(EMMA2RH_IRQ_BASE); - emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE); - emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE); - mips_cpu_irq_init(); - - /* setup cascade interrupts */ - setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); - setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(CPU_IRQ_BASE + 7); - else if (pending & STATUSF_IP2) - emma2rh_irq_dispatch(); - else if (pending & STATUSF_IP1) - do_IRQ(CPU_IRQ_BASE + 1); - else if (pending & STATUSF_IP0) - do_IRQ(CPU_IRQ_BASE + 0); - else - spurious_interrupt(); -} - - diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c deleted file mode 100644 index fba5c156f472..000000000000 --- a/arch/mips/emma2rh/markeins/irq_markeins.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * arch/mips/emma2rh/markeins/irq_markeins.c - * This file defines the irq handler for Mark-eins. - * - * Copyright (C) NEC Electronics Corporation 2004-2006 - * - * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include - -#include -#include - -static int emma2rh_sw_irq_base = -1; -static int emma2rh_gpio_irq_base = -1; - -void ll_emma2rh_sw_irq_enable(int reg); -void ll_emma2rh_sw_irq_disable(int reg); -void ll_emma2rh_gpio_irq_enable(int reg); -void ll_emma2rh_gpio_irq_disable(int reg); - -static void emma2rh_sw_irq_enable(unsigned int irq) -{ - ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base); -} - -static void emma2rh_sw_irq_disable(unsigned int irq) -{ - ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); -} - -struct irq_chip emma2rh_sw_irq_controller = { - .name = "emma2rh_sw_irq", - .ack = emma2rh_sw_irq_disable, - .mask = emma2rh_sw_irq_disable, - .mask_ack = emma2rh_sw_irq_disable, - .unmask = emma2rh_sw_irq_enable, -}; - -void emma2rh_sw_irq_init(u32 irq_base) -{ - u32 i; - - for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) - set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller, - handle_level_irq); - - emma2rh_sw_irq_base = irq_base; -} - -void ll_emma2rh_sw_irq_enable(int irq) -{ - u32 reg; - - db_assert(irq >= 0); - db_assert(irq < NUM_EMMA2RH_IRQ_SW); - - reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); - reg |= 1 << irq; - emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); -} - -void ll_emma2rh_sw_irq_disable(int irq) -{ - u32 reg; - - db_assert(irq >= 0); - db_assert(irq < 32); - - reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); - reg &= ~(1 << irq); - emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); -} - -static void emma2rh_gpio_irq_enable(unsigned int irq) -{ - ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base); -} - -static void emma2rh_gpio_irq_disable(unsigned int irq) -{ - ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); -} - -static void emma2rh_gpio_irq_ack(unsigned int irq) -{ - irq -= emma2rh_gpio_irq_base; - emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - ll_emma2rh_gpio_irq_disable(irq); -} - -static void emma2rh_gpio_irq_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base); -} - -struct irq_chip emma2rh_gpio_irq_controller = { - .name = "emma2rh_gpio_irq", - .ack = emma2rh_gpio_irq_ack, - .mask = emma2rh_gpio_irq_disable, - .mask_ack = emma2rh_gpio_irq_ack, - .unmask = emma2rh_gpio_irq_enable, - .end = emma2rh_gpio_irq_end, -}; - -void emma2rh_gpio_irq_init(u32 irq_base) -{ - u32 i; - - for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) - set_irq_chip(i, &emma2rh_gpio_irq_controller); - - emma2rh_gpio_irq_base = irq_base; -} - -void ll_emma2rh_gpio_irq_enable(int irq) -{ - u32 reg; - - db_assert(irq >= 0); - db_assert(irq < NUM_EMMA2RH_IRQ_GPIO); - - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg |= 1 << irq; - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); -} - -void ll_emma2rh_gpio_irq_disable(int irq) -{ - u32 reg; - - db_assert(irq >= 0); - db_assert(irq < NUM_EMMA2RH_IRQ_GPIO); - - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg &= ~(1 << irq); - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); -} diff --git a/arch/mips/emma2rh/markeins/led.c b/arch/mips/emma2rh/markeins/led.c deleted file mode 100644 index b65254c1bfe9..000000000000 --- a/arch/mips/emma2rh/markeins/led.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/mips/emma2rh/markeins/led.c - * This file defines the led display for Mark-eins. - * - * Copyright (C) NEC Electronics Corporation 2004-2006 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include - -const unsigned long clear = 0x20202020; - -#define LED_BASE 0xb1400038 - -void markeins_led_clear(void) -{ - emma2rh_out32(LED_BASE, clear); - emma2rh_out32(LED_BASE + 4, clear); -} - -void markeins_led(const char *str) -{ - int i; - int len = strlen(str); - - markeins_led_clear(); - if (len > 8) - len = 8; - - if (emma2rh_in32(0xb0000800) & (0x1 << 18)) - for (i = 0; i < len; i++) - emma2rh_out8(LED_BASE + i, str[i]); - else - for (i = 0; i < len; i++) - emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)), - str[i]); -} - -void markeins_led_hex(u32 val) -{ - char str[10]; - - sprintf(str, "%08x", val); - markeins_led(str); -} diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c deleted file mode 100644 index fb9cda253ab0..000000000000 --- a/arch/mips/emma2rh/markeins/platform.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * arch/mips/emma2rh/markeins/platofrm.c - * This file sets up platform devices for EMMA2RH Mark-eins. - * - * Copyright(C) MontaVista Software Inc, 2006 - * - * Author: dmitry pervushin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - - -#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */ - -static struct resource i2c_emma_resources_0[] = { - { - .name = NULL, - .start = EMMA2RH_IRQ_PIIC0, - .end = EMMA2RH_IRQ_PIIC0, - .flags = IORESOURCE_IRQ - }, { - .name = NULL, - .start = EMMA2RH_PIIC0_BASE, - .end = EMMA2RH_PIIC0_BASE + 0x1000, - .flags = 0 - }, -}; - -struct resource i2c_emma_resources_1[] = { - { - .name = NULL, - .start = EMMA2RH_IRQ_PIIC1, - .end = EMMA2RH_IRQ_PIIC1, - .flags = IORESOURCE_IRQ - }, { - .name = NULL, - .start = EMMA2RH_PIIC1_BASE, - .end = EMMA2RH_PIIC1_BASE + 0x1000, - .flags = 0 - }, -}; - -struct resource i2c_emma_resources_2[] = { - { - .name = NULL, - .start = EMMA2RH_IRQ_PIIC2, - .end = EMMA2RH_IRQ_PIIC2, - .flags = IORESOURCE_IRQ - }, { - .name = NULL, - .start = EMMA2RH_PIIC2_BASE, - .end = EMMA2RH_PIIC2_BASE + 0x1000, - .flags = 0 - }, -}; - -struct platform_device i2c_emma_devices[] = { - [0] = { - .name = I2C_EMMA2RH, - .id = 0, - .resource = i2c_emma_resources_0, - .num_resources = ARRAY_SIZE(i2c_emma_resources_0), - }, - [1] = { - .name = I2C_EMMA2RH, - .id = 1, - .resource = i2c_emma_resources_1, - .num_resources = ARRAY_SIZE(i2c_emma_resources_1), - }, - [2] = { - .name = I2C_EMMA2RH, - .id = 2, - .resource = i2c_emma_resources_2, - .num_resources = ARRAY_SIZE(i2c_emma_resources_2), - }, -}; - -#define EMMA2RH_SERIAL_CLOCK 18544000 -#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST - -static struct plat_serial8250_port platform_serial_ports[] = { - [0] = { - .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), - .irq = EMMA2RH_IRQ_PFUR0, - .uartclk = EMMA2RH_SERIAL_CLOCK, - .regshift = 4, - .iotype = UPIO_MEM, - .flags = EMMA2RH_SERIAL_FLAGS, - }, [1] = { - .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), - .irq = EMMA2RH_IRQ_PFUR1, - .uartclk = EMMA2RH_SERIAL_CLOCK, - .regshift = 4, - .iotype = UPIO_MEM, - .flags = EMMA2RH_SERIAL_FLAGS, - }, [2] = { - .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), - .irq = EMMA2RH_IRQ_PFUR2, - .uartclk = EMMA2RH_SERIAL_CLOCK, - .regshift = 4, - .iotype = UPIO_MEM, - .flags = EMMA2RH_SERIAL_FLAGS, - }, [3] = { - .flags = 0, - }, -}; - -static struct platform_device serial_emma = { - .name = "serial8250", - .dev = { - .platform_data = &platform_serial_ports, - }, -}; - -static struct platform_device *devices[] = { - &i2c_emma_devices[0], - &i2c_emma_devices[1], - &i2c_emma_devices[2], - &serial_emma, -}; - -static struct mtd_partition markeins_parts[] = { - [0] = { - .name = "RootFS", - .offset = 0x00000000, - .size = 0x00c00000, - }, - [1] = { - .name = "boot code area", - .offset = MTDPART_OFS_APPEND, - .size = 0x00100000, - }, - [2] = { - .name = "kernel image", - .offset = MTDPART_OFS_APPEND, - .size = 0x00300000, - }, - [3] = { - .name = "RootFS2", - .offset = MTDPART_OFS_APPEND, - .size = 0x00c00000, - }, - [4] = { - .name = "boot code area2", - .offset = MTDPART_OFS_APPEND, - .size = 0x00100000, - }, - [5] = { - .name = "kernel image2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static int __init platform_devices_setup(void) -{ - physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts)); - return platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -arch_initcall(platform_devices_setup); - diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c deleted file mode 100644 index b6a23ad539f8..000000000000 --- a/arch/mips/emma2rh/markeins/setup.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * arch/mips/emma2rh/markeins/setup.c - * This file is setup for EMMA2RH Mark-eins. - * - * Copyright (C) NEC Electronics Corporation 2004-2006 - * - * This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c. - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include - -#include -#include - -#include - -#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ - -extern void markeins_led(const char *); - -static int bus_frequency = 0; - -static void markeins_machine_restart(char *command) -{ - static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000; - - printk("cannot EMMA2RH Mark-eins restart.\n"); - markeins_led("restart."); - back_to_prom(); -} - -static void markeins_machine_halt(void) -{ - printk("EMMA2RH Mark-eins halted.\n"); - markeins_led("halted."); - while (1) ; -} - -static void markeins_machine_power_off(void) -{ - printk("EMMA2RH Mark-eins halted. Please turn off the power.\n"); - markeins_led("poweroff."); - while (1) ; -} - -static unsigned long __initdata emma2rh_clock[4] = { - 166500000, 187312500, 199800000, 210600000 -}; - -static unsigned int __init detect_bus_frequency(unsigned long rtc_base) -{ - u32 reg; - - /* detect from boot strap */ - reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); - reg = (reg >> 4) & 0x3; - - return emma2rh_clock[reg]; -} - -void __init plat_time_init(void) -{ - u32 reg; - if (bus_frequency == 0) - bus_frequency = detect_bus_frequency(0); - - reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); - if ((reg & 0x3) == 0) - reg = (reg >> 6) & 0x3; - else { - reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL); - reg = (reg >> 4) & 0x3; - } - mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2; -} - -static void markeins_board_init(void); -extern void markeins_irq_setup(void); - -static void inline __init markeins_sio_setup(void) -{ -} - -void __init plat_mem_setup(void) -{ - /* initialize board - we don't trust the loader */ - markeins_board_init(); - - set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); - - _machine_restart = markeins_machine_restart; - _machine_halt = markeins_machine_halt; - pm_power_off = markeins_machine_power_off; - - /* setup resource limits */ - ioport_resource.start = EMMA2RH_PCI_IO_BASE; - ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1; - iomem_resource.start = EMMA2RH_IO_BASE; - iomem_resource.end = EMMA2RH_ROM_BASE - 1; - - /* Reboot on panic */ - panic_timeout = 180; - - markeins_sio_setup(); -} - -static void __init markeins_board_init(void) -{ - u32 val; - - val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */ - emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa); - val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */ - emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */ - emma2rh_out32(EMMA2RH_PCI_CONTROL, 0); - - markeins_led("MVL E2RH"); -} diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 7a881755800f..6c8342ae74db 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -35,6 +35,16 @@ mtc0 \reg, CP0_TCSTATUS _ehb .endm +#elif defined(CONFIG_CPU_MIPSR2) + .macro local_irq_enable reg=t0 + ei + irq_enable_hazard + .endm + + .macro local_irq_disable reg=t0 + di + irq_disable_hazard + .endm #else .macro local_irq_enable reg=t0 mfc0 \reg, CP0_STATUS diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 49df8c4c9d25..bac4a960b24c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * __clear_bit(nr, addr); } -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - /* * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ -static inline unsigned long __fls(unsigned long x) +static inline unsigned long __fls(unsigned long word) { - int lz; + int num; - if (sizeof(x) == 4) { + if (BITS_PER_LONG == 32 && + __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" " .set pop \n" - : "=r" (lz) - : "r" (x)); + : "=r" (num) + : "r" (word)); - return 31 - lz; + return 31 - num; } - BUG_ON(sizeof(x) != 8); + if (BITS_PER_LONG == 64 && + __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) { + __asm__( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (num) + : "r" (word)); - __asm__( - " .set push \n" - " .set mips64 \n" - " dclz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); + return 63 - num; + } + + num = BITS_PER_LONG - 1; - return 63 - lz; +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; } /* @@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word) * This is defined the same way as ffs. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ -static inline int fls(int word) +static inline int fls(int x) { - __asm__("clz %0, %1" : "=r" (word) : "r" (word)); + int r; - return 32 - word; -} + if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + __asm__("clz %0, %1" : "=r" (x) : "r" (x)); -#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) -static inline int fls64(__u64 word) -{ - __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); + return 32 - x; + } - return 64 - word; + r = 32; + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; } -#else + #include -#endif /* * ffs - find first bit set. @@ -646,16 +694,6 @@ static inline int ffs(int word) return fls(word & -word); } -#else - -#include -#include -#include -#include -#include - -#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ - #include #include diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 25b980c91e7e..44437ed765e8 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -29,6 +29,7 @@ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ +#define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_MULOVF 1023 /* Multiply overflow */ #endif /* __ASM_BREAK_H */ diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 7eb63de808bc..08ea46863fe5 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -7,20 +7,31 @@ #include -#define BUG() \ -do { \ - __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ -} while (0) +static inline void __noreturn BUG(void) +{ + __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); + /* Fool GCC into thinking the function doesn't return. */ + while (1) + ; +} #define HAVE_ARCH_BUG #if (_MIPS_ISA > _MIPS_ISA_MIPS1) -#define BUG_ON(condition) \ -do { \ - __asm__ __volatile__("tne $0, %0, %1" \ - : : "r" (condition), "i" (BRK_BUG)); \ -} while (0) +static inline void __BUG_ON(unsigned long condition) +{ + if (__builtin_constant_p(condition)) { + if (condition) + BUG(); + else + return; + } + __asm__ __volatile__("tne $0, %0, %1" + : : "r" (condition), "i" (BRK_BUG)); +} + +#define BUG_ON(C) __BUG_ON((unsigned long)(C)) #define HAVE_ARCH_BUG_ON diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index fe7dc2d59b69..2988d29a0867 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -11,11 +11,19 @@ #include #include -#ifdef __GNUC__ +#if defined(__MIPSEB__) +# define __BIG_ENDIAN +#elif defined(__MIPSEL__) +# define __LITTLE_ENDIAN +#else +# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" +#endif + +#define __SWAB_64_THRU_32__ #ifdef CONFIG_CPU_MIPSR2 -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( " wsbh %0, %1 \n" @@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return x; } -#define __arch__swab16(x) ___arch__swab16(x) +#define __arch_swab16 __arch_swab16 -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( " wsbh %0, %1 \n" @@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) return x; } -#define __arch__swab32(x) ___arch__swab32(x) +#define __arch_swab32 __arch_swab32 #ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) +static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( " dsbh %0, %1 \n" @@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) return x; } - -#define __arch__swab64(x) ___arch__swab64(x) - +#define __arch_swab64 __arch_swab64 #endif /* CONFIG_CPU_MIPS64_R2 */ #endif /* CONFIG_CPU_MIPSR2 */ -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#if defined(__MIPSEB__) -# include -#elif defined(__MIPSEL__) -# include -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif +#include #endif /* _ASM_BYTEORDER_H */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 5ea701fc3425..12d12dfe73c0 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -141,6 +141,8 @@ #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) +#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ + cpu_has_mips64r1 | cpu_has_mips64r2) #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h deleted file mode 100644 index 6983b6ff0af3..000000000000 --- a/arch/mips/include/asm/ds1286.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_DS1286_H -#define _ASM_DS1286_H - -#include - -#endif /* _ASM_DS1286_H */ diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h new file mode 100644 index 000000000000..30aea91de626 --- /dev/null +++ b/arch/mips/include/asm/emma/emma2rh.h @@ -0,0 +1,330 @@ +/* + * arch/mips/include/asm/emma/emma2rh.h + * This file is EMMA2RH common header. + * + * Copyright (C) NEC Electronics Corporation 2005-2006 + * + * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_EMMA_EMMA2RH_H +#define __ASM_EMMA_EMMA2RH_H + +#include + +/* + * EMMA2RH registers + */ +#define REGBASE 0x10000000 + +#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE) +#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE) +#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE) +#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE) +#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE) +#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE) +#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE) +#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE) +#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE) +#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) +#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) +#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) +#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) +#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) +#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) +#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) +#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE) +#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE) +#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE) +#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE) +#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE) +#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE) +#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE) +#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE) +#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE) +#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE) +#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE) +#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE) +#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE) +#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE) +#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE) +#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE) +#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE) +#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE) +#define EMMA2RH_PCI_INT (0x200020+REGBASE) +#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE) +#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE) +#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE) +#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE) +#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE) + +/* + * Memory map (physical address) + * + * Note most of the following address must be properly aligned by the + * corresponding size. For example, if PCI_IO_SIZE is 16MB, then + * PCI_IO_BASE must be aligned along 16MB boundary. + */ + +/* the actual ram size is detected at run-time */ +#define EMMA2RH_RAM_BASE 0x00000000 +#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */ + +#define EMMA2RH_IO_BASE 0x10000000 +#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */ + +#define EMMA2RH_GENERALIO_BASE 0x11000000 +#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */ + +#define EMMA2RH_PCI_IO_BASE 0x12000000 +#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */ + +#define EMMA2RH_PCI_MEM_BASE 0x14000000 +#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */ + +#define EMMA2RH_ROM_BASE 0x1c000000 +#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ + +#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE +#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE + +#define NUM_CPU_IRQ 8 +#define NUM_EMMA2RH_IRQ 96 + +#define CPU_EMMA2RH_CASCADE 2 +#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE +#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) + +/* + * emma2rh irq defs + */ + +#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE) + +#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49 +#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50 +#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51 +#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56 +#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57 +#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58 + +/* + * EMMA2RH Register Access + */ + +#define EMMA2RH_BASE (0xa0000000) + +static inline void emma2rh_sync(void) +{ + volatile u32 *p = (volatile u32 *)0xbfc00000; + (void)(*p); +} + +static inline void emma2rh_out32(u32 offset, u32 val) +{ + *(volatile u32 *)(EMMA2RH_BASE | offset) = val; + emma2rh_sync(); +} + +static inline u32 emma2rh_in32(u32 offset) +{ + u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); + return val; +} + +static inline void emma2rh_out16(u32 offset, u16 val) +{ + *(volatile u16 *)(EMMA2RH_BASE | offset) = val; + emma2rh_sync(); +} + +static inline u16 emma2rh_in16(u32 offset) +{ + u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); + return val; +} + +static inline void emma2rh_out8(u32 offset, u8 val) +{ + *(volatile u8 *)(EMMA2RH_BASE | offset) = val; + emma2rh_sync(); +} + +static inline u8 emma2rh_in8(u32 offset) +{ + u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); + return val; +} + +/** + * IIC registers map + **/ + +/*---------------------------------------------------------------------------*/ +/* CNT - Control register (00H R/W) */ +/*---------------------------------------------------------------------------*/ +#define SPT 0x00000001 +#define STT 0x00000002 +#define ACKE 0x00000004 +#define WTIM 0x00000008 +#define SPIE 0x00000010 +#define WREL 0x00000020 +#define LREL 0x00000040 +#define IICE 0x00000080 +#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ + +#define I2C_EMMA_START (IICE | STT) +#define I2C_EMMA_STOP (IICE | SPT) +#define I2C_EMMA_REPSTART I2C_EMMA_START + +/*---------------------------------------------------------------------------*/ +/* STA - Status register (10H Read) */ +/*---------------------------------------------------------------------------*/ +#define MSTS 0x00000080 +#define ALD 0x00000040 +#define EXC 0x00000020 +#define COI 0x00000010 +#define TRC 0x00000008 +#define ACKD 0x00000004 +#define STD 0x00000002 +#define SPD 0x00000001 + +/*---------------------------------------------------------------------------*/ +/* CSEL - Clock select register (20H R/W) */ +/*---------------------------------------------------------------------------*/ +#define FCL 0x00000080 +#define ND50 0x00000040 +#define CLD 0x00000020 +#define DAD 0x00000010 +#define SMC 0x00000008 +#define DFC 0x00000004 +#define CL 0x00000003 +#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ + +#define FAST397 0x0000008b +#define FAST297 0x0000008a +#define FAST347 0x0000000b +#define FAST260 0x0000000a +#define FAST130 0x00000008 +#define STANDARD108 0x00000083 +#define STANDARD83 0x00000082 +#define STANDARD95 0x00000003 +#define STANDARD73 0x00000002 +#define STANDARD36 0x00000001 +#define STANDARD71 0x00000000 + +/*---------------------------------------------------------------------------*/ +/* SVA - Slave address register (30H R/W) */ +/*---------------------------------------------------------------------------*/ +#define SVA 0x000000fe + +/*---------------------------------------------------------------------------*/ +/* SHR - Shift register (40H R/W) */ +/*---------------------------------------------------------------------------*/ +#define SR 0x000000ff + +/*---------------------------------------------------------------------------*/ +/* INT - Interrupt register (50H R/W) */ +/* INTM - Interrupt mask register (60H R/W) */ +/*---------------------------------------------------------------------------*/ +#define INTE0 0x00000001 + +/*********************************************************************** + * I2C registers + *********************************************************************** + */ +#define I2C_EMMA_CNT 0x00 +#define I2C_EMMA_STA 0x10 +#define I2C_EMMA_CSEL 0x20 +#define I2C_EMMA_SVA 0x30 +#define I2C_EMMA_SHR 0x40 +#define I2C_EMMA_INT 0x50 +#define I2C_EMMA_INTM 0x60 + +/* + * include the board dependent part + */ +#ifdef CONFIG_NEC_MARKEINS +#include +#else +#error "Unknown EMMA2RH board!" +#endif + +#endif /* __ASM_EMMA_EMMA2RH_H */ diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h new file mode 100644 index 000000000000..973b0628490d --- /dev/null +++ b/arch/mips/include/asm/emma/markeins.h @@ -0,0 +1,75 @@ +/* + * include/asm-mips/emma2rh/markeins.h + * This file is EMMA2RH board depended header. + * + * Copyright (C) NEC Electronics Corporation 2005-2006 + * + * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef MARKEINS_H +#define MARKEINS_H + +#define NUM_EMMA2RH_IRQ_SW 32 +#define NUM_EMMA2RH_IRQ_GPIO 32 + +#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0) +#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0) + +#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) +#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) + +#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE) + +#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 +#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 +#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17 +#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18 + +#endif /* CONFIG_MARKEINS */ diff --git a/arch/mips/include/asm/emma2rh/emma2rh.h b/arch/mips/include/asm/emma2rh/emma2rh.h deleted file mode 100644 index 6a1af0af51e3..000000000000 --- a/arch/mips/include/asm/emma2rh/emma2rh.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * include/asm-mips/emma2rh/emma2rh.h - * This file is EMMA2RH common header. - * - * Copyright (C) NEC Electronics Corporation 2005-2006 - * - * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_EMMA2RH_EMMA2RH_H -#define __ASM_EMMA2RH_EMMA2RH_H - -#include - -/* - * EMMA2RH registers - */ -#define REGBASE 0x10000000 - -#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE) -#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE) -#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE) -#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE) -#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE) -#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE) -#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE) -#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE) -#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE) -#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) -#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) -#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) -#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) -#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) -#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) -#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) -#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE) -#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE) -#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE) -#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE) -#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE) -#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE) -#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE) -#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE) -#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE) -#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE) -#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE) -#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE) -#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE) -#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE) -#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE) -#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE) -#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE) -#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE) -#define EMMA2RH_PCI_INT (0x200020+REGBASE) -#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE) -#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE) -#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE) -#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE) -#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE) - -/* - * Memory map (physical address) - * - * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then - * PCI_IO_BASE must be aligned along 16MB boundary. - */ - -/* the actual ram size is detected at run-time */ -#define EMMA2RH_RAM_BASE 0x00000000 -#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */ - -#define EMMA2RH_IO_BASE 0x10000000 -#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */ - -#define EMMA2RH_GENERALIO_BASE 0x11000000 -#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */ - -#define EMMA2RH_PCI_IO_BASE 0x12000000 -#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */ - -#define EMMA2RH_PCI_MEM_BASE 0x14000000 -#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */ - -#define EMMA2RH_ROM_BASE 0x1c000000 -#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ - -#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE -#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE - -#define NUM_CPU_IRQ 8 -#define NUM_EMMA2RH_IRQ 96 - -#define CPU_EMMA2RH_CASCADE 2 -#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE -#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) - -/* - * emma2rh irq defs - */ - -#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE) - -#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49 -#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50 -#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51 -#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56 -#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57 -#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58 - -/* - * EMMA2RH Register Access - */ - -#define EMMA2RH_BASE (0xa0000000) - -static inline void emma2rh_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void emma2rh_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(EMMA2RH_BASE | offset) = val; - emma2rh_sync(); -} - -static inline u32 emma2rh_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); - return val; -} - -static inline void emma2rh_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(EMMA2RH_BASE | offset) = val; - emma2rh_sync(); -} - -static inline u16 emma2rh_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); - return val; -} - -static inline void emma2rh_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(EMMA2RH_BASE | offset) = val; - emma2rh_sync(); -} - -static inline u8 emma2rh_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); - return val; -} - -/** - * IIC registers map - **/ - -/*---------------------------------------------------------------------------*/ -/* CNT - Control register (00H R/W) */ -/*---------------------------------------------------------------------------*/ -#define SPT 0x00000001 -#define STT 0x00000002 -#define ACKE 0x00000004 -#define WTIM 0x00000008 -#define SPIE 0x00000010 -#define WREL 0x00000020 -#define LREL 0x00000040 -#define IICE 0x00000080 -#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ - -#define I2C_EMMA_START (IICE | STT) -#define I2C_EMMA_STOP (IICE | SPT) -#define I2C_EMMA_REPSTART I2C_EMMA_START - -/*---------------------------------------------------------------------------*/ -/* STA - Status register (10H Read) */ -/*---------------------------------------------------------------------------*/ -#define MSTS 0x00000080 -#define ALD 0x00000040 -#define EXC 0x00000020 -#define COI 0x00000010 -#define TRC 0x00000008 -#define ACKD 0x00000004 -#define STD 0x00000002 -#define SPD 0x00000001 - -/*---------------------------------------------------------------------------*/ -/* CSEL - Clock select register (20H R/W) */ -/*---------------------------------------------------------------------------*/ -#define FCL 0x00000080 -#define ND50 0x00000040 -#define CLD 0x00000020 -#define DAD 0x00000010 -#define SMC 0x00000008 -#define DFC 0x00000004 -#define CL 0x00000003 -#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ - -#define FAST397 0x0000008b -#define FAST297 0x0000008a -#define FAST347 0x0000000b -#define FAST260 0x0000000a -#define FAST130 0x00000008 -#define STANDARD108 0x00000083 -#define STANDARD83 0x00000082 -#define STANDARD95 0x00000003 -#define STANDARD73 0x00000002 -#define STANDARD36 0x00000001 -#define STANDARD71 0x00000000 - -/*---------------------------------------------------------------------------*/ -/* SVA - Slave address register (30H R/W) */ -/*---------------------------------------------------------------------------*/ -#define SVA 0x000000fe - -/*---------------------------------------------------------------------------*/ -/* SHR - Shift register (40H R/W) */ -/*---------------------------------------------------------------------------*/ -#define SR 0x000000ff - -/*---------------------------------------------------------------------------*/ -/* INT - Interrupt register (50H R/W) */ -/* INTM - Interrupt mask register (60H R/W) */ -/*---------------------------------------------------------------------------*/ -#define INTE0 0x00000001 - -/*********************************************************************** - * I2C registers - *********************************************************************** - */ -#define I2C_EMMA_CNT 0x00 -#define I2C_EMMA_STA 0x10 -#define I2C_EMMA_CSEL 0x20 -#define I2C_EMMA_SVA 0x30 -#define I2C_EMMA_SHR 0x40 -#define I2C_EMMA_INT 0x50 -#define I2C_EMMA_INTM 0x60 - -/* - * include the board dependent part - */ -#if defined(CONFIG_MARKEINS) -#include -#else -#error "Unknown EMMA2RH board!" -#endif - -#endif /* __ASM_EMMA2RH_EMMA2RH_H */ diff --git a/arch/mips/include/asm/emma2rh/markeins.h b/arch/mips/include/asm/emma2rh/markeins.h deleted file mode 100644 index 973b0628490d..000000000000 --- a/arch/mips/include/asm/emma2rh/markeins.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * include/asm-mips/emma2rh/markeins.h - * This file is EMMA2RH board depended header. - * - * Copyright (C) NEC Electronics Corporation 2005-2006 - * - * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef MARKEINS_H -#define MARKEINS_H - -#define NUM_EMMA2RH_IRQ_SW 32 -#define NUM_EMMA2RH_IRQ_GPIO 32 - -#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0) -#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0) - -#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) -#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) - -#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE) - -#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 -#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 -#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17 -#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18 - -#endif /* CONFIG_MARKEINS */ diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 2731c38bd7ae..e5189572956c 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -23,6 +23,9 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H +#include +#include + struct mips_fpu_emulator_stats { unsigned int emulated; unsigned int loads; @@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats { extern struct mips_fpu_emulator_stats fpuemustats; +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long cpc); +extern int do_dsemulret(struct pt_regs *xcp); + +/* + * Instruction inserted following the badinst to further tag the sequence + */ +#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */ + +/* + * Break instruction with special math emu break code set + */ +#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) + #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h deleted file mode 100644 index f44852e9a96d..000000000000 --- a/arch/mips/include/asm/m48t35.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip - */ -#ifndef _ASM_M48T35_H -#define _ASM_M48T35_H - -#include - -extern spinlock_t rtc_lock; - -struct m48t35_rtc { - volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */ - volatile u8 control; - volatile u8 sec; - volatile u8 min; - volatile u8 hour; - volatile u8 day; - volatile u8 date; - volatile u8 month; - volatile u8 year; -}; - -#define M48T35_RTC_SET 0x80 -#define M48T35_RTC_STOPPED 0x80 -#define M48T35_RTC_READ 0x40 - -#endif /* _ASM_M48T35_H */ diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h new file mode 100644 index 000000000000..ea6aa143b78e --- /dev/null +++ b/arch/mips/include/asm/mach-lemote/pci.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2008 Zhang Le + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + */ + +#ifndef _LEMOTE_PCI_H_ +#define _LEMOTE_PCI_H_ + +#define LOONGSON2E_PCI_MEM_START 0x14000000UL +#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL +#define LOONGSON2E_PCI_IO_START 0x00004000UL +#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL + +#endif /* !_LEMOTE_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h new file mode 100644 index 000000000000..8de0eb9c98a3 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/gpio.h @@ -0,0 +1,172 @@ +/* + * gpio.h: GPIO Support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H +#define __ASM_MIPS_MACH_PNX833X_GPIO_H + +/* BIG FAT WARNING: races danger! + No protections exist here. Current users are only early init code, + when locking is not needed because no cuncurency yet exists there, + and GPIO IRQ dispatcher, which does locking. + However, if many uses will ever happen, proper locking will be needed + - including locking between different uses +*/ + +#include "pnx833x.h" + +#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0) +#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0) + +/* Initialize GPIO to a known state */ +static inline void pnx833x_gpio_init(void) +{ + PNX833X_PIO_DIR = 0; + PNX833X_PIO_DIR2 = 0; + PNX833X_PIO_SEL = 0; + PNX833X_PIO_SEL2 = 0; + PNX833X_PIO_INT_EDGE = 0; + PNX833X_PIO_INT_HI = 0; + PNX833X_PIO_INT_LO = 0; + + /* clear any GPIO interrupt requests */ + PNX833X_PIO_INT_CLEAR = 0xffff; + PNX833X_PIO_INT_CLEAR = 0; + PNX833X_PIO_INT_ENABLE = 0; +} + +/* Select GPIO direction for a pin */ +static inline void pnx833x_gpio_select_input(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} +static inline void pnx833x_gpio_select_output(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_DIR, pin); + else + SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} + +/* Select GPIO or alternate function for a pin */ +static inline void pnx833x_gpio_select_function_io(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} +static inline void pnx833x_gpio_select_function_alt(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_SEL, pin); + else + SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} + +/* Read GPIO pin */ +static inline int pnx833x_gpio_read(unsigned int pin) +{ + if (pin < 32) + return (PNX833X_PIO_IN >> pin) & 1; + else + return (PNX833X_PIO_IN2 >> (pin & 31)) & 1; +} + +/* Write GPIO pin */ +static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) +{ + if (pin < 32) { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); + } else { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + } +} + +/* Configure GPIO interrupt */ +#define GPIO_INT_NONE 0 +#define GPIO_INT_LEVEL_LOW 1 +#define GPIO_INT_LEVEL_HIGH 2 +#define GPIO_INT_EDGE_RISING 3 +#define GPIO_INT_EDGE_FALLING 4 +#define GPIO_INT_EDGE_BOTH 5 +static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin) +{ + switch (when) { + case GPIO_INT_LEVEL_LOW: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_LEVEL_HIGH: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_RISING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_FALLING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_BOTH: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + default: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + } +} + +/* Enable/disable GPIO interrupt */ +static inline void pnx833x_gpio_enable_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} +static inline void pnx833x_gpio_disable_irq(unsigned int pin) +{ + CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} + +/* Clear GPIO interrupt request */ +static inline void pnx833x_gpio_clear_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); +} + +#endif diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h new file mode 100644 index 000000000000..657f089b1724 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h @@ -0,0 +1,126 @@ + +/* + * irq.h: IRQ mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H +#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H +/* + * The "IRQ numbers" are completely virtual. + * + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, + * numbers 49..64 for (virtual) GPIO interrupts. + * + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, + * connected to PIC, which uses core hardware interrupt 2, and also + * a timer interrupt through hardware interrupt 5. + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, + * numbers 65..80 for (virtual) GPIO interrupts. + * + */ +#include + +#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) + +/* Interrupts supported by PIC */ +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) +#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) +#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) +#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) +#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) +#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) +#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) +#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) +#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) +#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) +#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) +#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) +#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) +#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) +#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) +#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) +#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) +#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) +#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) +#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) +#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) +#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) +#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) +#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) +#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) +#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) +#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) + +#if defined(CONFIG_SOC_PNX8335) +#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) +#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) +#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) +#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) +#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) +#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) +#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) +#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) +#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) +#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) +#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) +#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) +#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) +#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) +#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) +#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) +#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) +#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) +#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) +#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) +#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) +#endif + +/* GPIO interrupts */ +#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) +#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) +#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) +#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) +#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) +#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) +#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) +#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) +#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) +#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) +#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) +#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) +#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) +#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) +#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) +#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) + +#endif + diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h new file mode 100644 index 000000000000..745114b1d8d5 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/irq.h @@ -0,0 +1,53 @@ +/* + * irq.h: IRQ mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H +#define __ASM_MIPS_MACH_PNX833X_IRQ_H +/* + * The "IRQ numbers" are completely virtual. + * + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, + * numbers 49..64 for (virtual) GPIO interrupts. + * + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, + * connected to PIC, which uses core hardware interrupt 2, and also + * a timer interrupt through hardware interrupt 5. + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, + * numbers 65..80 for (virtual) GPIO interrupts. + * + */ +#if defined(CONFIG_SOC_PNX8335) + #define PNX833X_PIC_NUM_IRQ 58 +#else + #define PNX833X_PIC_NUM_IRQ 37 +#endif + +#define MIPS_CPU_NUM_IRQ 8 +#define PNX833X_GPIO_NUM_IRQ 16 + +#define MIPS_CPU_IRQ_BASE 0 +#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) +#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ) +#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ) + +#endif diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h new file mode 100644 index 000000000000..100f52870e3c --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h @@ -0,0 +1,202 @@ +/* + * pnx833x.h: Register mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H +#define __ASM_MIPS_MACH_PNX833X_PNX833X_H + +/* All regs are accessed in KSEG1 */ +#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) + +#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs))) + +/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ + +/* Read access to multibit fields */ +#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) +#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) + +/* Use PNX833X_FIELD to extract a field from val */ +#define PNX_FIELD(cpu, val, reg, field) \ + (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ + PNX##cpu##_##reg##_##field##_SHIFT) +#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) +#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) +#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) + +/* Use PNX833X_REGFIELD to extract a field from a register */ +#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) +#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) +#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) + + +#define PNX_WRITEFIELD(cpu, val, reg, field) \ + (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ + ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) +#define PNX833X_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(833X, val, reg, field) +#define PNX8330_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8330, val, reg, field) +#define PNX8335_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8335, val, reg, field) + + +/* Macros to detect CPU type */ + +#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) +#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 +#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 +#define PNX8330_CONFIG_MODULE_MAJREV 4 +#define PNX8335_CONFIG_MODULE_MAJREV 5 +#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8330_CONFIG_MODULE_MAJREV) +#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8335_CONFIG_MODULE_MAJREV) + + + +#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) + +#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) +#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) +#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) +#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ +#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 +#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) + +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) +#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 + +#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 + +#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) +#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ + +#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 + +#define PNX833X_PIO_IN PNX833X_REG(0xF000) +#define PNX833X_PIO_OUT PNX833X_REG(0xF004) +#define PNX833X_PIO_DIR PNX833X_REG(0xF008) +#define PNX833X_PIO_SEL PNX833X_REG(0xF014) +#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) +#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) +#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) +#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) +#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) +#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) +#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) +#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) +#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) +#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) + +#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) +#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) +#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) +#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) + +#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) +#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) + +#define PNX833X_CONFIG_USB PNX833X_REG(0x7008) + +#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) +#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) +#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) +#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) + +#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) +#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) +#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) + +#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX833X_IDE_MODULE_ID_VALUE 0xA009 + + +#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) +#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) +#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) +#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) +#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) +#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) +#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) +#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) + +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 + +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 + +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 + +#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) + +#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) +#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 + +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 + +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 + +#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) +#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 + +#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ + (PNX833X_MIU_CONFIG_SPI = \ + ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ + ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ + ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ + ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT)) + +#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) +#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) +#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) + +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 + + /* I/O location(gets remapped)*/ +#define PNX8335_NAND_BASE 0x18000000 +/* I/O location with CLE high */ +#define PNX8335_NAND_CLE_MASK 0x00100000 +/* I/O location with ALE high */ +#define PNX8335_NAND_ALE_MASK 0x00010000 + +#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) +#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) +#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) + +#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_SATA_MODULE_ID_VALUE 0xA099 + +#endif diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h new file mode 100644 index 000000000000..82cd1e97bc2e --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H +#define __ASM_MIPS_MACH_PNX833X_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index c8e554eafce3..b5cf6457305a 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned extern unsigned get_434_reg(unsigned reg_offs); extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); +extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); +extern void rb532_gpio_set_istat(int bit, unsigned gpio); #endif /* _RC32434_GPIO_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 79e8ef67d0d3..f25a84916703 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -40,12 +40,14 @@ #define BTCS 0x010040 #define BTCOMPARE 0x010044 #define GPIOBASE 0x050000 -#define GPIOCFG 0x050004 -#define GPIOD 0x050008 -#define GPIOILEVEL 0x05000C -#define GPIOISTAT 0x050010 -#define GPIONMIEN 0x050014 -#define IMASK6 0x038038 +/* Offsets relative to GPIOBASE */ +#define GPIOFUNC 0x00 +#define GPIOCFG 0x04 +#define GPIOD 0x08 +#define GPIOILEVEL 0x0C +#define GPIOISTAT 0x10 +#define GPIONMIEN 0x14 +#define IMASK6 0x38 #define LO_WPX (1 << 0) #define LO_ALE (1 << 1) #define LO_CLE (1 << 2) diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h new file mode 100644 index 000000000000..5e6912fdd0ed --- /dev/null +++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h @@ -0,0 +1,26 @@ +#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H +#define __ASM_MACH_TX49XX_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#if defined(CONFIG_TOSHIBA_RBTX4939) && \ + (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \ + defined(__BIG_ENDIAN) +#define NEEDS_TXX9_IOSWABW +extern u16 (*ioswabw)(volatile u16 *a, u16 x); +extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x); +#else +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#endif +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) + +#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 979866000da4..9316324d070d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -192,6 +192,7 @@ #define PM_16M 0x01ffe000 #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 +#define PM_1G 0x7fffe000 #endif diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index de6d09ebbd80..e2e09b2cd265 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -98,6 +98,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "R5000 " #elif defined CONFIG_CPU_R5432 #define MODULE_PROC_FAMILY "R5432 " +#elif defined CONFIG_CPU_R5500 +#define MODULE_PROC_FAMILY "R5500 " #elif defined CONFIG_CPU_R6000 #define MODULE_PROC_FAMILY "R6000 " #elif defined CONFIG_CPU_NEVADA diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 5510c53b7feb..053e4634acee 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -79,6 +79,11 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) /* We don't do dynamic PCI IRQ allocation */ } +#define HAVE_PCI_MMAP + +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + /* * Dynamic DMA mapping stuff. * MIPS has everything mapped statically. diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 9c22571b160d..c2c8bac43307 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -9,10 +9,6 @@ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -#ifdef CONFIG_64BIT -#define __ARCH_WANT_COMPAT_SYS_PTRACE -#endif - /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #define FPR_BASE 32 #define PC 64 @@ -80,25 +76,25 @@ enum pt_watch_style { pt_watch_style_mips64 }; struct mips32_watch_regs { - uint32_t watchlo[8]; + unsigned int watchlo[8]; /* Lower 16 bits of watchhi. */ - uint16_t watchhi[8]; + unsigned short watchhi[8]; /* Valid mask and I R W bits. * bit 0 -- 1 if W bit is usable. * bit 1 -- 1 if R bit is usable. * bit 2 -- 1 if I bit is usable. * bits 3 - 11 -- Valid watchhi mask bits. */ - uint16_t watch_masks[8]; + unsigned short watch_masks[8]; /* The number of valid watch register pairs. */ - uint32_t num_valid; + unsigned int num_valid; } __attribute__((aligned(8))); struct mips64_watch_regs { - uint64_t watchlo[8]; - uint16_t watchhi[8]; - uint16_t watch_masks[8]; - uint32_t num_valid; + unsigned long long watchlo[8]; + unsigned short watchhi[8]; + unsigned short watch_masks[8]; + unsigned int num_valid; } __attribute__((aligned(8))); struct pt_watch_regs { @@ -116,6 +112,7 @@ struct pt_watch_regs { #include #include +#include #include struct task_struct; diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index d3bd5c5aa2ec..9601ea950542 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void) /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CEVT_R4K +#ifdef CONFIG_CSRC_R4K extern int init_mips_clocksource(void); #else static inline int init_mips_clocksource(void) diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h index 4316a3e57678..9cde0090cbf6 100644 --- a/arch/mips/include/asm/txx9/generic.h +++ b/arch/mips/include/asm/txx9/generic.h @@ -86,4 +86,9 @@ void txx9_iocled_init(unsigned long baseaddr, int basenum, unsigned int num, int lowactive, const char *color, char **deftriggers); +/* 7SEG LED */ +void txx9_7segled_init(unsigned int num, + void (*putc)(unsigned int pos, unsigned char val)); +int txx9_7segled_putc(unsigned int pos, char c); + #endif /* __ASM_TXX9_GENERIC_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index d9da7112aaf8..b1372c27f136 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0cf15457ecac..c9207b5fd923 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void) #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) -static inline void cpu_probe_legacy(struct cpuinfo_mips *c) +static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) { switch (c->processor_id & 0xff00) { case PRID_IMP_R2000: c->cputype = CPU_R2000; + __cpu_name[cpu] = "R2000"; c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; @@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) c->tlbsize = 64; break; case PRID_IMP_R3000: - if ((c->processor_id & 0xff) == PRID_REV_R3000A) - if (cpu_has_confreg()) + if ((c->processor_id & 0xff) == PRID_REV_R3000A) { + if (cpu_has_confreg()) { c->cputype = CPU_R3081E; - else + __cpu_name[cpu] = "R3081"; + } else { c->cputype = CPU_R3000A; - else + __cpu_name[cpu] = "R3000A"; + } + break; + } else { c->cputype = CPU_R3000; + __cpu_name[cpu] = "R3000"; + } c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; @@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) + if ((c->processor_id & 0xff) >= PRID_REV_R4400) { c->cputype = CPU_R4400PC; - else + __cpu_name[cpu] = "R4400PC"; + } else { c->cputype = CPU_R4000PC; + __cpu_name[cpu] = "R4000PC"; + } } else { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) + if ((c->processor_id & 0xff) >= PRID_REV_R4400) { c->cputype = CPU_R4400SC; - else + __cpu_name[cpu] = "R4400SC"; + } else { c->cputype = CPU_R4000SC; + __cpu_name[cpu] = "R4000SC"; + } } c->isa_level = MIPS_CPU_ISA_III; @@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; + __cpu_name[cpu] = "NEC VR4111"; break; case PRID_REV_VR4121: c->cputype = CPU_VR4121; + __cpu_name[cpu] = "NEC VR4121"; break; case PRID_REV_VR4122: - if ((c->processor_id & 0xf) < 0x3) + if ((c->processor_id & 0xf) < 0x3) { c->cputype = CPU_VR4122; - else + __cpu_name[cpu] = "NEC VR4122"; + } else { c->cputype = CPU_VR4181A; + __cpu_name[cpu] = "NEC VR4181A"; + } break; case PRID_REV_VR4130: - if ((c->processor_id & 0xf) < 0x4) + if ((c->processor_id & 0xf) < 0x4) { c->cputype = CPU_VR4131; - else + __cpu_name[cpu] = "NEC VR4131"; + } else { c->cputype = CPU_VR4133; + __cpu_name[cpu] = "NEC VR4133"; + } break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); c->cputype = CPU_VR41XX; + __cpu_name[cpu] = "NEC Vr41xx"; break; } c->isa_level = MIPS_CPU_ISA_III; @@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4300: c->cputype = CPU_R4300; + __cpu_name[cpu] = "R4300"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4600: c->cputype = CPU_R4600; + __cpu_name[cpu] = "R4600"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) * it's c0_prid id number with the TX3900. */ c->cputype = CPU_R4650; + __cpu_name[cpu] = "R4650"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; @@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; + __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { switch (c->processor_id & 0xff) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; + __cpu_name[cpu] = "TX3912"; c->tlbsize = 32; break; case PRID_REV_TX3922: c->cputype = CPU_TX3922; + __cpu_name[cpu] = "TX3922"; c->tlbsize = 64; break; - default: - c->cputype = CPU_UNKNOWN; - break; } } break; case PRID_IMP_R4700: c->cputype = CPU_R4700; + __cpu_name[cpu] = "R4700"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_TX49: c->cputype = CPU_TX49XX; + __cpu_name[cpu] = "R49XX"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_LLSC; if (!(c->processor_id & 0x08)) @@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5000: c->cputype = CPU_R5000; + __cpu_name[cpu] = "R5000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5432: c->cputype = CPU_R5432; + __cpu_name[cpu] = "R5432"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5500: c->cputype = CPU_R5500; + __cpu_name[cpu] = "R5500"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_NEVADA: c->cputype = CPU_NEVADA; + __cpu_name[cpu] = "Nevada"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; @@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R6000: c->cputype = CPU_R6000; + __cpu_name[cpu] = "R6000"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; @@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R6000A: c->cputype = CPU_R6000A; + __cpu_name[cpu] = "R6000A"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; @@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_RM7000: c->cputype = CPU_RM7000; + __cpu_name[cpu] = "RM7000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_RM9000: c->cputype = CPU_RM9000; + __cpu_name[cpu] = "RM9000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R8000: c->cputype = CPU_R8000; + __cpu_name[cpu] = "RM8000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R10000: c->cputype = CPU_R10000; + __cpu_name[cpu] = "R10000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R12000: c->cputype = CPU_R12000; + __cpu_name[cpu] = "R12000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R14000: c->cputype = CPU_R14000; + __cpu_name[cpu] = "R14000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_LOONGSON2: c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | @@ -652,21 +692,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) static void __cpuinit decode_configs(struct cpuinfo_mips *c) { + int ok; + /* MIPS32 or MIPS64 compliant CPU. */ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; - /* Read Config registers. */ - if (!decode_config0(c)) - return; /* actually worth a panic() */ - if (!decode_config1(c)) - return; - if (!decode_config2(c)) - return; - if (!decode_config3(c)) - return; + ok = decode_config0(c); /* Read Config registers. */ + BUG_ON(!ok); /* Arch spec violation! */ + if (ok) + ok = decode_config1(c); + if (ok) + ok = decode_config2(c); + if (ok) + ok = decode_config3(c); + + mips_probe_watch_registers(c); } #ifdef CONFIG_CPU_MIPSR2 @@ -675,52 +718,62 @@ extern void spram_config(void); static inline void spram_config(void) {} #endif -static inline void cpu_probe_mips(struct cpuinfo_mips *c) +static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - mips_probe_watch_registers(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; + __cpu_name[cpu] = "MIPS 4Kc"; break; case PRID_IMP_4KEC: c->cputype = CPU_4KEC; + __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KECR2: c->cputype = CPU_4KEC; + __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KSC: case PRID_IMP_4KSD: c->cputype = CPU_4KSC; + __cpu_name[cpu] = "MIPS 4KSc"; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; + __cpu_name[cpu] = "MIPS 5Kc"; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; + __cpu_name[cpu] = "MIPS 20Kc"; break; case PRID_IMP_24K: case PRID_IMP_24KE: c->cputype = CPU_24K; + __cpu_name[cpu] = "MIPS 24Kc"; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; + __cpu_name[cpu] = "MIPS 25Kc"; break; case PRID_IMP_34K: c->cputype = CPU_34K; + __cpu_name[cpu] = "MIPS 34Kc"; break; case PRID_IMP_74K: c->cputype = CPU_74K; + __cpu_name[cpu] = "MIPS 74Kc"; break; case PRID_IMP_1004K: c->cputype = CPU_1004K; + __cpu_name[cpu] = "MIPS 1004Kc"; break; } spram_config(); } -static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) +static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { @@ -729,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) switch ((c->processor_id >> 24) & 0xff) { case 0: c->cputype = CPU_AU1000; + __cpu_name[cpu] = "Au1000"; break; case 1: c->cputype = CPU_AU1500; + __cpu_name[cpu] = "Au1500"; break; case 2: c->cputype = CPU_AU1100; + __cpu_name[cpu] = "Au1100"; break; case 3: c->cputype = CPU_AU1550; + __cpu_name[cpu] = "Au1550"; break; case 4: c->cputype = CPU_AU1200; - if (2 == (c->processor_id & 0xff)) + __cpu_name[cpu] = "Au1200"; + if ((c->processor_id & 0xff) == 2) { c->cputype = CPU_AU1250; + __cpu_name[cpu] = "Au1250"; + } break; case 5: c->cputype = CPU_AU1210; + __cpu_name[cpu] = "Au1210"; break; default: panic("Unknown Au Core!"); @@ -755,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) } } -static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) +static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; + __cpu_name[cpu] = "SiByte SB1"; /* FPU in pass1 is known to have issues. */ if ((c->processor_id & 0xff) < 0x02) c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); break; case PRID_IMP_SB1A: c->cputype = CPU_SB1A; + __cpu_name[cpu] = "SiByte SB1A"; break; } } -static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) +static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; + __cpu_name[cpu] = "Sandcraft SR71000"; c->scache.ways = 8; c->tlbsize = 64; break; } } -static inline void cpu_probe_nxp(struct cpuinfo_mips *c) +static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_PR4450: c->cputype = CPU_PR4450; + __cpu_name[cpu] = "Philips PR4450"; c->isa_level = MIPS_CPU_ISA_M32R1; break; - default: - panic("Unknown NXP Core!"); /* REVISIT: die? */ - break; } } - -static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_BCM3302: c->cputype = CPU_BCM3302; + __cpu_name[cpu] = "Broadcom BCM3302"; break; case PRID_IMP_BCM4710: c->cputype = CPU_BCM4710; - break; - default: - c->cputype = CPU_UNKNOWN; + __cpu_name[cpu] = "Broadcom BCM4710"; break; } } const char *__cpu_name[NR_CPUS]; -/* - * Name a CPU - */ -static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c) -{ - const char *name = NULL; - - switch (c->cputype) { - case CPU_UNKNOWN: name = "unknown"; break; - case CPU_R2000: name = "R2000"; break; - case CPU_R3000: name = "R3000"; break; - case CPU_R3000A: name = "R3000A"; break; - case CPU_R3041: name = "R3041"; break; - case CPU_R3051: name = "R3051"; break; - case CPU_R3052: name = "R3052"; break; - case CPU_R3081: name = "R3081"; break; - case CPU_R3081E: name = "R3081E"; break; - case CPU_R4000PC: name = "R4000PC"; break; - case CPU_R4000SC: name = "R4000SC"; break; - case CPU_R4000MC: name = "R4000MC"; break; - case CPU_R4200: name = "R4200"; break; - case CPU_R4400PC: name = "R4400PC"; break; - case CPU_R4400SC: name = "R4400SC"; break; - case CPU_R4400MC: name = "R4400MC"; break; - case CPU_R4600: name = "R4600"; break; - case CPU_R6000: name = "R6000"; break; - case CPU_R6000A: name = "R6000A"; break; - case CPU_R8000: name = "R8000"; break; - case CPU_R10000: name = "R10000"; break; - case CPU_R12000: name = "R12000"; break; - case CPU_R14000: name = "R14000"; break; - case CPU_R4300: name = "R4300"; break; - case CPU_R4650: name = "R4650"; break; - case CPU_R4700: name = "R4700"; break; - case CPU_R5000: name = "R5000"; break; - case CPU_R5000A: name = "R5000A"; break; - case CPU_R4640: name = "R4640"; break; - case CPU_NEVADA: name = "Nevada"; break; - case CPU_RM7000: name = "RM7000"; break; - case CPU_RM9000: name = "RM9000"; break; - case CPU_R5432: name = "R5432"; break; - case CPU_4KC: name = "MIPS 4Kc"; break; - case CPU_5KC: name = "MIPS 5Kc"; break; - case CPU_R4310: name = "R4310"; break; - case CPU_SB1: name = "SiByte SB1"; break; - case CPU_SB1A: name = "SiByte SB1A"; break; - case CPU_TX3912: name = "TX3912"; break; - case CPU_TX3922: name = "TX3922"; break; - case CPU_TX3927: name = "TX3927"; break; - case CPU_AU1000: name = "Au1000"; break; - case CPU_AU1500: name = "Au1500"; break; - case CPU_AU1100: name = "Au1100"; break; - case CPU_AU1550: name = "Au1550"; break; - case CPU_AU1200: name = "Au1200"; break; - case CPU_AU1210: name = "Au1210"; break; - case CPU_AU1250: name = "Au1250"; break; - case CPU_4KEC: name = "MIPS 4KEc"; break; - case CPU_4KSC: name = "MIPS 4KSc"; break; - case CPU_VR41XX: name = "NEC Vr41xx"; break; - case CPU_R5500: name = "R5500"; break; - case CPU_TX49XX: name = "TX49xx"; break; - case CPU_20KC: name = "MIPS 20Kc"; break; - case CPU_24K: name = "MIPS 24K"; break; - case CPU_25KF: name = "MIPS 25Kf"; break; - case CPU_34K: name = "MIPS 34K"; break; - case CPU_1004K: name = "MIPS 1004K"; break; - case CPU_74K: name = "MIPS 74K"; break; - case CPU_VR4111: name = "NEC VR4111"; break; - case CPU_VR4121: name = "NEC VR4121"; break; - case CPU_VR4122: name = "NEC VR4122"; break; - case CPU_VR4131: name = "NEC VR4131"; break; - case CPU_VR4133: name = "NEC VR4133"; break; - case CPU_VR4181: name = "NEC VR4181"; break; - case CPU_VR4181A: name = "NEC VR4181A"; break; - case CPU_SR71000: name = "Sandcraft SR71000"; break; - case CPU_BCM3302: name = "Broadcom BCM3302"; break; - case CPU_BCM4710: name = "Broadcom BCM4710"; break; - case CPU_PR4450: name = "Philips PR4450"; break; - case CPU_LOONGSON2: name = "ICT Loongson-2"; break; - default: - BUG(); - } - - return name; -} - __cpuinit void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -915,30 +889,31 @@ __cpuinit void cpu_probe(void) c->processor_id = read_c0_prid(); switch (c->processor_id & 0xff0000) { case PRID_COMP_LEGACY: - cpu_probe_legacy(c); + cpu_probe_legacy(c, cpu); break; case PRID_COMP_MIPS: - cpu_probe_mips(c); + cpu_probe_mips(c, cpu); break; case PRID_COMP_ALCHEMY: - cpu_probe_alchemy(c); + cpu_probe_alchemy(c, cpu); break; case PRID_COMP_SIBYTE: - cpu_probe_sibyte(c); + cpu_probe_sibyte(c, cpu); break; case PRID_COMP_BROADCOM: - cpu_probe_broadcom(c); + cpu_probe_broadcom(c, cpu); break; case PRID_COMP_SANDCRAFT: - cpu_probe_sandcraft(c); + cpu_probe_sandcraft(c, cpu); break; case PRID_COMP_NXP: - cpu_probe_nxp(c); + cpu_probe_nxp(c, cpu); break; - default: - c->cputype = CPU_UNKNOWN; } + BUG_ON(!__cpu_name[cpu]); + BUG_ON(c->cputype == CPU_UNKNOWN); + /* * Platform code can force the cpu type to optimize code * generation. In that case be sure the cpu type is correctly @@ -958,8 +933,6 @@ __cpuinit void cpu_probe(void) } } - __cpu_name[cpu] = cpu_to_name(c); - if (cpu_has_mips_r2) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 86e026f067bc..74fb74583b4e 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -27,7 +27,7 @@ int __init init_mips_clocksource(void) if (!cpu_has_counter || !mips_hpt_frequency) return -ENXIO; - /* Calclate a somewhat reasonable rating value */ + /* Calculate a somewhat reasonable rating value */ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 5e75a316f6b1..d0916a55cd77 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -180,7 +180,7 @@ bad_stack: * The system call does not exist in this kernel */ illegal_syscall: - li v0, -ENOSYS # error + li v0, ENOSYS # error sw v0, PT_R2(sp) li t0, 1 # set error flag sw t0, PT_R7(sp) @@ -262,14 +262,11 @@ bad_alignment: LEAF(sys_syscall) subu t0, a0, __NR_O32_Linux # check syscall number sltiu v0, t0, __NR_O32_Linux_syscalls + 1 + beqz t0, einval # do not recurse sll t1, t0, 3 beqz v0, einval - lw t2, sys_call_table(t1) # syscall routine - li v1, 4000 - __NR_O32_Linux # index of sys_syscall - beq t0, v1, einval # do not recurse - /* Some syscalls like execve get their arguments from struct pt_regs and claim zero arguments in the syscall table. Thus we have to assume the worst case and shuffle around all potential arguments. @@ -293,7 +290,7 @@ bad_alignment: jr t2 /* Unreached */ -einval: li v0, -EINVAL +einval: li v0, -ENOSYS jr ra END(sys_syscall) @@ -627,7 +624,7 @@ einval: li v0, -EINVAL sys sys_pselect6 6 sys sys_ppoll 5 sys sys_unshare 1 - sys sys_splice 4 + sys sys_splice 6 sys sys_sync_file_range 7 /* 4305 */ sys sys_tee 4 sys sys_vmsplice 4 diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 3d58204c9d44..a9e171618994 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -117,7 +117,7 @@ syscall_trace_entry: illegal_syscall: /* This also isn't a 64-bit syscall, throw an error. */ - li v0, -ENOSYS # error + li v0, ENOSYS # error sd v0, PT_R2(sp) li t0, 1 # set error flag sd t0, PT_R7(sp) diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index e266b3aa6560..30f3b6317a83 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -390,7 +390,7 @@ EXPORT(sysn32_call_table) PTR sys_splice PTR sys_sync_file_range PTR sys_tee - PTR sys_vmsplice /* 6270 */ + PTR compat_sys_vmsplice /* 6270 */ PTR sys_move_pages PTR compat_sys_set_robust_list PTR compat_sys_get_robust_list diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 6c7ef8313ebd..fefef4af8595 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -174,14 +174,12 @@ not_o32_scall: END(handle_sys) LEAF(sys32_syscall) - sltu v0, a0, __NR_O32_Linux + __NR_O32_Linux_syscalls + 1 + subu t0, a0, __NR_O32_Linux # check syscall number + sltiu v0, t0, __NR_O32_Linux_syscalls + 1 + beqz t0, einval # do not recurse + dsll t1, t0, 3 beqz v0, einval - - dsll v0, a0, 3 - ld t2, (sys_call_table - (__NR_O32_Linux * 8))(v0) - - li v1, 4000 # indirect syscall number - beq a0, v1, einval # do not recurse + ld t2, sys_call_table(t1) # syscall routine move a0, a1 # shift argument registers move a1, a2 @@ -198,7 +196,7 @@ LEAF(sys32_syscall) jr t2 /* Unreached */ -einval: li v0, -EINVAL +einval: li v0, -ENOSYS jr ra END(sys32_syscall) @@ -512,7 +510,7 @@ sys_call_table: PTR sys_splice PTR sys32_sync_file_range /* 4305 */ PTR sys_tee - PTR sys_vmsplice + PTR compat_sys_vmsplice PTR compat_sys_move_pages PTR compat_sys_set_robust_list PTR compat_sys_get_robust_list /* 4310 */ diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 16f8edfe5cdc..4430a1f8fdf1 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -601,8 +601,8 @@ static int __init debugfs_mips(void) struct dentry *d; d = debugfs_create_dir("mips", NULL); - if (IS_ERR(d)) - return PTR_ERR(d); + if (!d) + return -ENOMEM; mips_debugfs_dir = d; return 0; } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 7b59cfb7e602..8bf88faf5afd 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -163,8 +163,10 @@ static void stop_this_cpu(void *dummy) * Remove this CPU: */ cpu_clear(smp_processor_id(), cpu_online_map); - local_irq_enable(); /* May need to service _machine_restart IPI */ - for (;;); /* Wait if available. */ + for (;;) { + if (cpu_wait) + (*cpu_wait)(); /* Wait if available. */ + } } void smp_send_stop(void) @@ -193,12 +195,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) /* preload SMP state for boot cpu */ void __devinit smp_prepare_boot_cpu(void) { - /* - * This assumes that bootup is always handled by the processor - * with the logic and physical number 0. - */ - __cpu_number_map[0] = 0; - __cpu_logical_map[0] = 0; cpu_set(0, phys_cpu_present_map); cpu_set(0, cpu_online_map); cpu_set(0, cpu_callin_map); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 80b9e070c207..353056110f2b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -722,6 +723,21 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, die_if_kernel("Kernel bug detected", regs); force_sig(SIGTRAP, current); break; + case BRK_MEMU: + /* + * Address errors may be deliberately induced by the FPU + * emulator to retake control of the CPU after executing the + * instruction in the delay slot of an emulated branch. + * + * Terminate if exception was recognized as a delay slot return + * otherwise handle as normal. + */ + if (do_dsemulret(regs)) + return; + + die_if_kernel("Math emu break/trap", regs); + force_sig(SIGTRAP, current); + break; default: scnprintf(b, sizeof(b), "%s instruction in kernel code", str); die_if_kernel(b, regs); @@ -1555,6 +1571,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1588,8 +1606,11 @@ void __init trap_init(void) if (cpu_has_veic || cpu_has_vint) ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else + else { ebase = CAC_BASE; + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); + } per_cpu_trap_init(); @@ -1697,11 +1718,11 @@ void __init trap_init(void) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); signal_init(); #ifdef CONFIG_MIPS32_COMPAT diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index c327b21bca81..bf4c4a979abb 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -499,21 +499,9 @@ sigill: asmlinkage void do_ade(struct pt_regs *regs) { - extern int do_dsemulret(struct pt_regs *); unsigned int __user *pc; mm_segment_t seg; - /* - * Address errors may be deliberately induced by the FPU emulator to - * retake control of the CPU after executing the instruction in the - * delay slot of an emulated branch. - */ - /* Terminate if exception was recognized as a delay slot return */ - if (do_dsemulret(regs)) - return; - - /* Otherwise handle as normal */ - /* * Did we catch a fault trying to load an instruction? * Or are we running in MIPS16 mode? @@ -560,12 +548,12 @@ static int __init debugfs_unaligned(void) return -ENODEV; d = debugfs_create_u32("unaligned_instructions", S_IRUGO, mips_debugfs_dir, &unaligned_instructions); - if (IS_ERR(d)) - return PTR_ERR(d); + if (!d) + return -ENOMEM; d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR, mips_debugfs_dir, &unaligned_action); - if (IS_ERR(d)) - return PTR_ERR(d); + if (!d) + return -ENOMEM; return 0; } __initcall(debugfs_unaligned); diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 972b2d2b8401..a1b3da6bad5c 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1134,7 +1134,7 @@ static int vpe_release(struct inode *inode, struct file *filp) /* It's good to be able to run the SP and if it chokes have a look at the /dev/rt?. But if we reset the pointer to the shared struct we - loose what has happened. So perhaps if garbage is sent to the vpe + lose what has happened. So perhaps if garbage is sent to the vpe device, use it as a trigger for the reset. Hopefully a nice executable will be along shortly. */ if (ret < 0) diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c index c1e41f15cc7e..8be03a8e1ad4 100644 --- a/arch/mips/lemote/lm2e/pci.c +++ b/arch/mips/lemote/lm2e/pci.c @@ -30,19 +30,20 @@ #include #include #include +#include extern struct pci_ops bonito64_pci_ops; static struct resource loongson2e_pci_mem_resource = { .name = "LOONGSON2E PCI MEM", - .start = 0x14000000UL, - .end = 0x1fffffffUL, + .start = LOONGSON2E_PCI_MEM_START, + .end = LOONGSON2E_PCI_MEM_END, .flags = IORESOURCE_MEM, }; static struct resource loongson2e_pci_io_resource = { .name = "LOONGSON2E PCI IO MEM", - .start = 0x00004000UL, + .start = LOONGSON2E_PCI_IO_START, .end = IO_SPACE_LIMIT, .flags = IORESOURCE_IO, }; @@ -82,6 +83,12 @@ static void __init ict_pcimap(void) static int __init pcibios_init(void) { ict_pcimap(); + + loongson2e_pci_controller.io_map_base = + (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE, + loongson2e_pci_io_resource.end - + loongson2e_pci_io_resource.start + 1); + register_pci_controller(&loongson2e_pci_controller); return 0; diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index 2cc6745991ab..ebd6ceaef2fd 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c @@ -34,6 +34,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include @@ -42,12 +43,6 @@ extern void mips_reboot_setup(void); -#ifdef CONFIG_64BIT -#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p))) -#else -#define PTR_PAD(p) (p) -#endif - unsigned long cpu_clock_freq; unsigned long bus_clock; unsigned int memsize; @@ -80,8 +75,8 @@ static void wbflush_loongson2e(void) void __init plat_mem_setup(void) { - set_io_port_base(PTR_PAD(0xbfd00000)); - + set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE, + IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1)); mips_reboot_setup(); __wbflush = wbflush_loongson2e; diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 8810dfb915dd..dbcf6511b74e 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_CPU_R4300) += dump_tlb.o obj-$(CONFIG_CPU_R4X00) += dump_tlb.o obj-$(CONFIG_CPU_R5000) += dump_tlb.o obj-$(CONFIG_CPU_R5432) += dump_tlb.o +obj-$(CONFIG_CPU_R5500) += dump_tlb.o obj-$(CONFIG_CPU_R6000) += obj-$(CONFIG_CPU_R8000) += obj-$(CONFIG_CPU_RM7000) += dump_tlb.o diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 465ff0ec85b9..779821cd54ab 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -25,6 +25,7 @@ static inline const char *msk2str(unsigned int mask) case PM_16M: return "16Mb"; case PM_64M: return "64Mb"; case PM_256M: return "256Mb"; + case PM_1G: return "1Gb"; #endif } return ""; diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index b08fc65c13a6..890f77927d62 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -48,7 +48,6 @@ #include #include "ieee754.h" -#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -346,9 +345,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) /* cop control register rd -> gpr[rt] */ u32 value; - if (ir == CP1UNDEF) { - return do_dsemulret(xcp); - } if (MIPSInst_RD(ir) == FPCREG_CSR) { value = ctx->fcr31; value = (value & ~0x3) | mips_rm[value & 0x3]; @@ -1299,12 +1295,12 @@ static int __init debugfs_fpuemu(void) if (!mips_debugfs_dir) return -ENODEV; dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); - if (IS_ERR(dir)) - return PTR_ERR(dir); + if (!dir) + return -ENOMEM; for (i = 0; i < ARRAY_SIZE(vars); i++) { d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); - if (IS_ERR(d)) - return PTR_ERR(d); + if (!d) + return -ENOMEM; } return 0; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 653e325849e4..df7b9d928efc 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -18,7 +18,6 @@ #include #include "ieee754.h" -#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -94,7 +93,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) return SIGBUS; err = __put_user(ir, &fr->emul); - err |= __put_user((mips_instruction)BADINST, &fr->badinst); + err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); err |= __put_user(cpc, &fr->epc); @@ -130,13 +129,13 @@ int do_dsemulret(struct pt_regs *xcp) /* * Do some sanity checking on the stackframe: * - * - Is the instruction pointed to by the EPC an BADINST? + * - Is the instruction pointed to by the EPC an BREAK_MATH? * - Is the following memory word the BD_COOKIE? */ err = __get_user(insn, &fr->badinst); err |= __get_user(cookie, &fr->cookie); - if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { + if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { fpuemustats.errors++; return 0; } diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h deleted file mode 100644 index 091f0e76730f..000000000000 --- a/arch/mips/math-emu/dsemul.h +++ /dev/null @@ -1,17 +0,0 @@ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); -extern int do_dsemulret(struct pt_regs *xcp); - -/* Instruction which will always cause an address error */ -#define AdELOAD 0x8c000001 /* lw $0,1($0) */ -/* Instruction which will plainly cause a CP1 exception when FPU is disabled */ -#define CP1UNDEF 0x44400001 /* cfc1 $0,$0 undef */ - -/* Instruction inserted following the badinst to further tag the sequence */ -#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */ - -/* Setup which instruction to use for trampoline */ -#ifdef STANDALONE_EMULATOR -#define BADINST CP1UNDEF -#else -#define BADINST AdELOAD -#endif diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 44e8dd8106bf..95ba32b5b720 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o +obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 891312f8e5a6..e6708b3ad343 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -111,6 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent); void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { + plat_unmap_dma_mem(dma_handle); free_pages((unsigned long) vaddr, get_order(size)); } @@ -121,6 +122,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, { unsigned long addr = (unsigned long) vaddr; + plat_unmap_dma_mem(dma_handle); + if (!plat_device_is_coherent(dev)) addr = CAC_ADDR(addr); @@ -324,7 +327,6 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, if (cpu_is_noncoherent_r10000(dev)) __dma_sync((unsigned long)page_address(sg_page(sg)), sg->length, direction); - plat_unmap_dma_mem(sg->dma_address); } } @@ -342,7 +344,6 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele if (!plat_device_is_coherent(dev)) __dma_sync((unsigned long)page_address(sg_page(sg)), sg->length, direction); - plat_unmap_dma_mem(sg->dma_address); } } diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c index 1f602a110e10..13adb5782110 100644 --- a/arch/mips/mm/sc-ip22.c +++ b/arch/mips/mm/sc-ip22.c @@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void) /* XXX Check with wje if the Indy caches can differenciate between writeback + invalidate and just invalidate. */ -struct bcache_ops indy_sc_ops = { +static struct bcache_ops indy_sc_ops = { .bc_enable = indy_sc_enable, .bc_disable = indy_sc_disable, .bc_wback_inv = indy_sc_wback_invalidate, diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile index cef2db8d2225..32e847808df1 100644 --- a/arch/mips/mti-malta/Makefile +++ b/arch/mips/mti-malta/Makefile @@ -7,9 +7,8 @@ # obj-y := malta-amon.o malta-cmdline.o \ malta-display.o malta-init.o malta-int.o \ - malta-memory.o malta-mtd.o \ - malta-platform.o malta-reset.o \ - malta-setup.o malta-time.o + malta-memory.o malta-platform.o \ + malta-reset.o malta-setup.o malta-time.o obj-$(CONFIG_EARLY_PRINTK) += malta-console.o obj-$(CONFIG_PCI) += malta-pci.o diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index 96236bf33838..df9e526312a2 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -22,9 +22,9 @@ #include #include -#include -#include -#include +#include +#include +#include int amon_cpu_avail(int cpu) { diff --git a/arch/mips/mti-malta/malta-mtd.c b/arch/mips/mti-malta/malta-mtd.c deleted file mode 100644 index 8ad9bdf25dce..000000000000 --- a/arch/mips/mti-malta/malta-mtd.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 MIPS Technologies, Inc. - * written by Ralf Baechle - */ - -#include -#include -#include -#include -#include - -static struct mtd_partition malta_mtd_partitions[] = { - { - .name = "YAMON", - .offset = 0x0, - .size = 0x100000, - .mask_flags = MTD_WRITEABLE - }, { - .name = "User FS", - .offset = 0x100000, - .size = 0x2e0000 - }, { - .name = "Board Config", - .offset = 0x3e0000, - .size = 0x020000, - .mask_flags = MTD_WRITEABLE - } -}; - -static struct physmap_flash_data malta_flash_data = { - .width = 4, - .nr_parts = ARRAY_SIZE(malta_mtd_partitions), - .parts = malta_mtd_partitions -}; - -static struct resource malta_flash_resource = { - .start = 0x1e000000, - .end = 0x1e3fffff, - .flags = IORESOURCE_MEM -}; - -static struct platform_device malta_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &malta_flash_data, - }, - .num_resources = 1, - .resource = &malta_flash_resource, -}; - -static int __init malta_mtd_init(void) -{ - platform_device_register(&malta_flash); - - return 0; -} - -module_init(malta_mtd_init) diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c index 83b9bab3cd3f..72e32a7715be 100644 --- a/arch/mips/mti-malta/malta-platform.c +++ b/arch/mips/mti-malta/malta-platform.c @@ -3,10 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2007 MIPS Technologies, Inc. + * Copyright (C) 2006, 07 MIPS Technologies, Inc. * written by Ralf Baechle (ralf@linux-mips.org) + * written by Ralf Baechle * - * Probe driver for the Malta's UART ports: + * Copyright (C) 2008 Wind River Systems, Inc. + * updated by Tiejun Chen + * + * 1. Probe driver for the Malta's UART ports: * * o 2 ports in the SMC SuperIO * o 1 port in the CBUS UART, a discrete 16550 which normally is only used @@ -14,10 +18,17 @@ * * We don't use 8250_platform.c on Malta as it would result in the CBUS * UART becoming ttyS0. + * + * 2. Register RTC-CMOS platform device on Malta. */ -#include #include #include +#include +#include +#include +#include +#include +#include #define SMC_PORT(base, int) \ { \ @@ -45,21 +56,93 @@ static struct plat_serial8250_port uart8250_data[] = { { }, }; -static struct platform_device uart8250_device = { +static struct platform_device malta_uart8250_device = { .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = uart8250_data, }, }; -static int __init uart8250_init(void) +struct resource malta_rtc_resources[] = { + { + .start = RTC_PORT(0), + .end = RTC_PORT(7), + .flags = IORESOURCE_IO, + }, { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device malta_rtc_device = { + .name = "rtc_cmos", + .id = -1, + .resource = malta_rtc_resources, + .num_resources = ARRAY_SIZE(malta_rtc_resources), +}; + +static struct mtd_partition malta_mtd_partitions[] = { + { + .name = "YAMON", + .offset = 0x0, + .size = 0x100000, + .mask_flags = MTD_WRITEABLE + }, { + .name = "User FS", + .offset = 0x100000, + .size = 0x2e0000 + }, { + .name = "Board Config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE + } +}; + +static struct physmap_flash_data malta_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(malta_mtd_partitions), + .parts = malta_mtd_partitions +}; + +static struct resource malta_flash_resource = { + .start = 0x1e000000, + .end = 0x1e3fffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device malta_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &malta_flash_data, + }, + .num_resources = 1, + .resource = &malta_flash_resource, +}; + +static struct platform_device *malta_devices[] __initdata = { + &malta_uart8250_device, + &malta_rtc_device, + &malta_flash_device, +}; + +static int __init malta_add_devices(void) { - return platform_device_register(&uart8250_device); -} + int err; -module_init(uart8250_init); + err = platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices)); + if (err) + return err; + + /* + * Set RTC to BCD mode to support current alarm code. + */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) & ~RTC_DM_BINARY, RTC_CONTROL); + + return 0; +} -MODULE_AUTHOR("Ralf Baechle "); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART"); +device_initcall(malta_add_devices); diff --git a/arch/mips/nxp/pnx833x/common/Makefile b/arch/mips/nxp/pnx833x/common/Makefile new file mode 100644 index 000000000000..4a16f3b503b5 --- /dev/null +++ b/arch/mips/nxp/pnx833x/common/Makefile @@ -0,0 +1,3 @@ +obj-y := interrupts.o platform.o prom.o setup.o reset.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c new file mode 100644 index 000000000000..30533ba200e2 --- /dev/null +++ b/arch/mips/nxp/pnx833x/common/interrupts.c @@ -0,0 +1,380 @@ +/* + * interrupts.c: Interrupt mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int mips_cpu_timer_irq; + +static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] = +{ + 0, /* unused */ + 4, /* PNX833X_PIC_I2C0_INT 1 */ + 4, /* PNX833X_PIC_I2C1_INT 2 */ + 1, /* PNX833X_PIC_UART0_INT 3 */ + 1, /* PNX833X_PIC_UART1_INT 4 */ + 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */ + 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */ + 7, /* PNX833X_PIC_GPIO_INT 7 */ + 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */ + 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */ + 4, /* PNX833X_PIC_CONFIG_INT 10 */ + 4, /* PNX833X_PIC_AOI_INT 11 */ + 9, /* PNX833X_PIC_SYNC_INT 12 */ + 9, /* PNX8335_PIC_SATA_INT 13 */ + 4, /* PNX833X_PIC_OSD_INT 14 */ + 9, /* PNX833X_PIC_DISP1_INT 15 */ + 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */ + 9, /* PNX833X_PIC_DISPLAY2_INT 17 */ + 4, /* PNX833X_PIC_VC_INT 18 */ + 4, /* PNX833X_PIC_SC_INT 19 */ + 9, /* PNX833X_PIC_IDE_INT 20 */ + 9, /* PNX833X_PIC_IDE_DMA_INT 21 */ + 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */ + 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */ + 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */ + 4, /* PNX833X_PIC_TS_OUT_INT 25 */ + 4, /* PNX833X_PIC_IR_INT 26 */ + 3, /* PNX833X_PIC_VMSP1_INT 27 */ + 3, /* PNX833X_PIC_VMSP2_INT 28 */ + 4, /* PNX833X_PIC_PIBC_INT 29 */ + 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */ + 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */ + 5, /* PNX833X_PIC_USB_INT 32 */ + 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */ + 4, /* PNX833X_PIC_CLOCK_INT 34 */ + 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */ + 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */ +#if defined(CONFIG_SOC_PNX8335) + 4, /* PNX8335_PIC_MIU_INT 37 */ + 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */ + 9, /* PNX8335_PIC_SYNC_HD_INT 39 */ + 9, /* PNX8335_PIC_DISP_HD_INT 40 */ + 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */ + 4, /* PNX8335_PIC_OSD_HD1_INT 42 */ + 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */ + 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */ + 4, /* PNX8335_PIC_DENC_TTX_INT 47 */ + 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */ + 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */ + 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */ + 4, /* PNX8335_PIC_PIBCS_INT 51 */ + 12, /* PNX8335_PIC_ETHERNET_INT 52 */ + 3, /* PNX8335_PIC_VMSP1_0_INT 53 */ + 3, /* PNX8335_PIC_VMSP1_1_INT 54 */ + 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */ + 4, /* PNX8335_PIC_TDGR_DE_INT 56 */ + 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */ +#endif +}; + +static void pnx833x_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + +static void pic_dispatch(void) +{ + unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC); + + if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) { + unsigned long priority = PNX833X_PIC_INT_PRIORITY; + PNX833X_PIC_INT_PRIORITY = irq_prio[irq]; + + if (irq == PNX833X_PIC_GPIO_INT) { + unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE; + int pin; + while ((pin = ffs(mask & 0xffff))) { + pin -= 1; + do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); + mask &= ~(1 << pin); + } + } else { + do_IRQ(irq + PNX833X_PIC_IRQ_BASE); + } + + PNX833X_PIC_INT_PRIORITY = priority; + } else { + printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP4) + pic_dispatch(); + else if (pending & STATUSF_IP7) + do_IRQ(PNX833X_TIMER_IRQ); + else + spurious_interrupt(); +} + +static inline void pnx833x_hard_enable_pic_irq(unsigned int irq) +{ + /* Currently we do this by setting IRQ priority to 1. + If priority support is being implemented, 1 should be repalced + by a better value. */ + PNX833X_PIC_INT_REG(irq) = irq_prio[irq]; +} + +static inline void pnx833x_hard_disable_pic_irq(unsigned int irq) +{ + /* Disable IRQ by writing setting it's priority to 0 */ + PNX833X_PIC_INT_REG(irq) = 0; +} + +static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */ +#define IRQFLAG_STARTED 1 +#define IRQFLAG_DISABLED 2 + +static DEFINE_SPINLOCK(pnx833x_irq_lock); + +static unsigned int pnx833x_startup_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */ + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); + return 0; +} + +static void pnx833x_shutdown_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] = 0; /* not started */ + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_enable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] &= ~IRQFLAG_DISABLED; + if (irqflags[pic_irq] == IRQFLAG_STARTED) + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_disable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] |= IRQFLAG_DISABLED; + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_ack_pic_irq(unsigned int irq) +{ +} + +static void pnx833x_end_pic_irq(unsigned int irq) +{ +} + +static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock); + +static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_enable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); + return 0; +} + +static void pnx833x_enable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_enable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); +} + +static void pnx833x_disable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_disable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); +} + +static void pnx833x_ack_gpio_irq(unsigned int irq) +{ +} + +static void pnx833x_end_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_clear_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); +} + +static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + int gpio_mode; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + gpio_mode = GPIO_INT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + gpio_mode = GPIO_INT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + gpio_mode = GPIO_INT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + gpio_mode = GPIO_INT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + gpio_mode = GPIO_INT_LEVEL_LOW; + break; + default: + gpio_mode = GPIO_INT_NONE; + break; + } + + pnx833x_gpio_setup_irq(gpio_mode, pin); + + return 0; +} + +static struct irq_chip pnx833x_pic_irq_type = { + .typename = "PNX-PIC", + .startup = pnx833x_startup_pic_irq, + .shutdown = pnx833x_shutdown_pic_irq, + .enable = pnx833x_enable_pic_irq, + .disable = pnx833x_disable_pic_irq, + .ack = pnx833x_ack_pic_irq, + .end = pnx833x_end_pic_irq +}; + +static struct irq_chip pnx833x_gpio_irq_type = { + .typename = "PNX-GPIO", + .startup = pnx833x_startup_gpio_irq, + .shutdown = pnx833x_disable_gpio_irq, + .enable = pnx833x_enable_gpio_irq, + .disable = pnx833x_disable_gpio_irq, + .ack = pnx833x_ack_gpio_irq, + .end = pnx833x_end_gpio_irq, + .set_type = pnx833x_set_type_gpio_irq +}; + +void __init arch_init_irq(void) +{ + unsigned int irq; + + /* setup standard internal cpu irqs */ + mips_cpu_irq_init(); + + /* Set IRQ information in irq_desc */ + for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { + pnx833x_hard_disable_pic_irq(irq); + set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); + } + + for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) + set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); + + /* Set PIC priority limiter register to 0 */ + PNX833X_PIC_INT_PRIORITY = 0; + + /* Setup GPIO IRQ dispatching */ + pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT); + + /* Enable PIC IRQs (HWIRQ2) */ + if (cpu_has_vint) + set_vi_handler(4, pic_dispatch); + + write_c0_status(read_c0_status() | IE_IRQ2); +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch); + + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */ + + extern unsigned long mips_hpt_frequency; + unsigned long reg = PNX833X_CLOCK_CPUCP_CTL; + + if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) { + /* Functional clock is disabled so use crystal frequency */ + mips_hpt_frequency = 25; + } else { +#if defined(CONFIG_SOC_PNX8335) + /* Functional clock is enabled, so get clock multiplier */ + mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ)); +#else + static const unsigned long int freq[4] = {240, 160, 120, 80}; + mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)]; +#endif + } + + printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency); + + mips_hpt_frequency *= 500000; +} + diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/nxp/pnx833x/common/platform.c new file mode 100644 index 000000000000..b1ccbcc18f78 --- /dev/null +++ b/arch/mips/nxp/pnx833x/common/platform.c @@ -0,0 +1,319 @@ +/* + * platform.c: platform support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_I2C_PNX0105 +/* Until i2c driver available in kernel.*/ +#include +#endif + +#include +#include +#include + +static u64 uart_dmamask = DMA_32BIT_MASK; + +static struct resource pnx833x_uart_resources[] = { + [0] = { + .start = PNX833X_UART0_PORTS_START, + .end = PNX833X_UART0_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX833X_PIC_UART0_INT, + .end = PNX833X_PIC_UART0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = PNX833X_UART1_PORTS_START, + .end = PNX833X_UART1_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = PNX833X_PIC_UART1_INT, + .end = PNX833X_PIC_UART1_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct pnx8xxx_port pnx8xxx_ports[] = { + [0] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX833X_UART0_PORTS_START, + .mapbase = PNX833X_UART0_PORTS_START, + .irq = PNX833X_PIC_UART0_INT, + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX833X_UART1_PORTS_START, + .mapbase = PNX833X_UART1_PORTS_START, + .irq = PNX833X_PIC_UART1_INT, + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, + }, + }, +}; + +static struct platform_device pnx833x_uart_device = { + .name = "pnx8xxx-uart", + .id = -1, + .dev = { + .dma_mask = &uart_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = pnx8xxx_ports, + }, + .num_resources = ARRAY_SIZE(pnx833x_uart_resources), + .resource = pnx833x_uart_resources, +}; + +static u64 ehci_dmamask = DMA_32BIT_MASK; + +static struct resource pnx833x_usb_ehci_resources[] = { + [0] = { + .start = PNX833X_USB_PORTS_START, + .end = PNX833X_USB_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX833X_PIC_USB_INT, + .end = PNX833X_PIC_USB_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_usb_ehci_device = { + .name = "pnx833x-ehci", + .id = -1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources), + .resource = pnx833x_usb_ehci_resources, +}; + +#ifdef CONFIG_I2C_PNX0105 +static struct resource pnx833x_i2c0_resources[] = { + { + .start = PNX833X_I2C0_PORTS_START, + .end = PNX833X_I2C0_PORTS_END, + .flags = IORESOURCE_MEM, + }, + { + .start = PNX833X_PIC_I2C0_INT, + .end = PNX833X_PIC_I2C0_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource pnx833x_i2c1_resources[] = { + { + .start = PNX833X_I2C1_PORTS_START, + .end = PNX833X_I2C1_PORTS_END, + .flags = IORESOURCE_MEM, + }, + { + .start = PNX833X_PIC_I2C1_INT, + .end = PNX833X_PIC_I2C1_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = { + { + .base = PNX833X_I2C0_PORTS_START, + .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */ + .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */ + .bus_addr = 0, /* no slave support */ + }, + { + .base = PNX833X_I2C1_PORTS_START, + .irq = -1, /* on high freq, polling is faster */ + /*.irq = PNX833X_PIC_I2C1_INT,*/ + .clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */ + .bus_addr = 0, /* no slave support */ + }, +}; + +static struct platform_device pnx833x_i2c0_device = { + .name = "i2c-pnx0105", + .id = 0, + .dev = { + .platform_data = &pnx833x_i2c_dev[0], + }, + .num_resources = ARRAY_SIZE(pnx833x_i2c0_resources), + .resource = pnx833x_i2c0_resources, +}; + +static struct platform_device pnx833x_i2c1_device = { + .name = "i2c-pnx0105", + .id = 1, + .dev = { + .platform_data = &pnx833x_i2c_dev[1], + }, + .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources), + .resource = pnx833x_i2c1_resources, +}; +#endif + +static u64 ethernet_dmamask = DMA_32BIT_MASK; + +static struct resource pnx833x_ethernet_resources[] = { + [0] = { + .start = PNX8335_IP3902_PORTS_START, + .end = PNX8335_IP3902_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8335_PIC_ETHERNET_INT, + .end = PNX8335_PIC_ETHERNET_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_ethernet_device = { + .name = "ip3902-eth", + .id = -1, + .dev = { + .dma_mask = ðernet_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources), + .resource = pnx833x_ethernet_resources, +}; + +static struct resource pnx833x_sata_resources[] = { + [0] = { + .start = PNX8335_SATA_PORTS_START, + .end = PNX8335_SATA_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8335_PIC_SATA_INT, + .end = PNX8335_PIC_SATA_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_sata_device = { + .name = "pnx833x-sata", + .id = -1, + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), + .resource = pnx833x_sata_resources, +}; + +static const char *part_probes[] = { + "cmdlinepart", + NULL +}; + +static void +pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK)); + else + writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK)); +} + +static struct platform_nand_data pnx833x_flash_nand_data = { + .chip = { + .chip_delay = 25, + .part_probe_types = part_probes, + }, + .ctrl = { + .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl + } +}; + +/* + * Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!), + * 12 bytes more seems to be the standard that allows for NAND access. + */ +static struct resource pnx833x_flash_nand_resource = { + .start = PNX8335_NAND_BASE, + .end = PNX8335_NAND_BASE + 12, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pnx833x_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = &pnx833x_flash_nand_resource, + .dev = { + .platform_data = &pnx833x_flash_nand_data, + }, +}; + +static struct platform_device *pnx833x_platform_devices[] __initdata = { + &pnx833x_uart_device, + &pnx833x_usb_ehci_device, +#ifdef CONFIG_I2C_PNX0105 + &pnx833x_i2c0_device, + &pnx833x_i2c1_device, +#endif + &pnx833x_ethernet_device, + &pnx833x_sata_device, + &pnx833x_flash_nand, +}; + +static int __init pnx833x_platform_init(void) +{ + int res; + + res = platform_add_devices(pnx833x_platform_devices, + ARRAY_SIZE(pnx833x_platform_devices)); + + return res; +} + +arch_initcall(pnx833x_platform_init); diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/nxp/pnx833x/common/prom.c new file mode 100644 index 000000000000..2a41e8fec210 --- /dev/null +++ b/arch/mips/nxp/pnx833x/common/prom.c @@ -0,0 +1,70 @@ +/* + * prom.c: + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **)fw_arg1; + char *c = &(arcs_cmdline[0]); + int i; + + for (i = 1; i < argc; i++) { + strcpy(c, argv[i]); + c += strlen(argv[i]); + if (i < argc-1) + *c++ = ' '; + } + *c = 0; +} + +char __init *prom_getenv(char *envname) +{ + extern char **prom_envp; + char **env = prom_envp; + int i; + + i = strlen(envname); + + while (*env) { + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') + return *env + i + 1; + env++; + } + + return 0; +} + +void __init prom_free_prom_memory(void) +{ +} + +char * __init prom_getcmdline(void) +{ + return arcs_cmdline; +} + diff --git a/arch/mips/nxp/pnx833x/common/reset.c b/arch/mips/nxp/pnx833x/common/reset.c new file mode 100644 index 000000000000..a9bc9bacad2b --- /dev/null +++ b/arch/mips/nxp/pnx833x/common/reset.c @@ -0,0 +1,45 @@ +/* + * reset.c: reset support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +void pnx833x_machine_restart(char *command) +{ + PNX833X_RESET_CONTROL_2 = 0; + PNX833X_RESET_CONTROL = 0; +} + +void pnx833x_machine_halt(void) +{ + while (1) + __asm__ __volatile__ ("wait"); + +} + +void pnx833x_machine_power_off(void) +{ + pnx833x_machine_halt(); +} diff --git a/arch/mips/nxp/pnx833x/common/setup.c b/arch/mips/nxp/pnx833x/common/setup.c new file mode 100644 index 000000000000..e51fbc4b644d --- /dev/null +++ b/arch/mips/nxp/pnx833x/common/setup.c @@ -0,0 +1,64 @@ +/* + * setup.c: Setup PNX833X Soc. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +extern void pnx833x_board_setup(void); +extern void pnx833x_machine_restart(char *); +extern void pnx833x_machine_halt(void); +extern void pnx833x_machine_power_off(void); + +int __init plat_mem_setup(void) +{ + /* fake pci bus to avoid bounce buffers */ + PCI_DMA_BUS_IS_PHYS = 1; + + /* set mips clock to 320MHz */ +#if defined(CONFIG_SOC_PNX8335) + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ); +#endif + pnx833x_gpio_init(); /* so it will be ready in board_setup() */ + + pnx833x_board_setup(); + + _machine_restart = pnx833x_machine_restart; + _machine_halt = pnx833x_machine_halt; + pm_power_off = pnx833x_machine_power_off; + + /* IO/MEM resources. */ + set_io_port_base(KSEG1); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + return 0; +} diff --git a/arch/mips/nxp/pnx833x/stb22x/Makefile b/arch/mips/nxp/pnx833x/stb22x/Makefile new file mode 100644 index 000000000000..f81c5801f455 --- /dev/null +++ b/arch/mips/nxp/pnx833x/stb22x/Makefile @@ -0,0 +1,3 @@ +lib-y := board.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/nxp/pnx833x/stb22x/board.c new file mode 100644 index 000000000000..90cc604bdadf --- /dev/null +++ b/arch/mips/nxp/pnx833x/stb22x/board.c @@ -0,0 +1,133 @@ +/* + * board.c: STB225 board support. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +/* endianess twiddlers */ +#define PNX8335_DEBUG0 0x4400 +#define PNX8335_DEBUG1 0x4404 +#define PNX8335_DEBUG2 0x4408 +#define PNX8335_DEBUG3 0x440c +#define PNX8335_DEBUG4 0x4410 +#define PNX8335_DEBUG5 0x4414 +#define PNX8335_DEBUG6 0x4418 +#define PNX8335_DEBUG7 0x441c + +int prom_argc; +char **prom_argv = 0, **prom_envp = 0; + +extern void prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP STB22x"; +} + +static inline unsigned long env_or_default(char *env, unsigned long dfl) +{ + char *str = prom_getenv(env); + return str ? simple_strtol(str, 0, 0) : dfl; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize = env_or_default("memsize", 0x02000000); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void __init pnx833x_board_setup(void) +{ + pnx833x_gpio_select_function_alt(4); + pnx833x_gpio_select_output(4); + pnx833x_gpio_select_function_alt(5); + pnx833x_gpio_select_input(5); + pnx833x_gpio_select_function_alt(6); + pnx833x_gpio_select_input(6); + pnx833x_gpio_select_function_alt(7); + pnx833x_gpio_select_output(7); + + pnx833x_gpio_select_function_alt(25); + pnx833x_gpio_select_function_alt(26); + + pnx833x_gpio_select_function_alt(27); + pnx833x_gpio_select_function_alt(28); + pnx833x_gpio_select_function_alt(29); + pnx833x_gpio_select_function_alt(30); + pnx833x_gpio_select_function_alt(31); + pnx833x_gpio_select_function_alt(32); + pnx833x_gpio_select_function_alt(33); + +#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + /* Setup MIU for NAND access on CS0... + * + * (it seems that we must also configure CS1 for reliable operation, + * otherwise the first read ID command will fail if it's read as 4 bytes + * but pass if it's read as 1 word.) + */ + + /* Setup MIU CS0 & CS1 timing */ + PNX833X_MIU_SEL0 = 0; + PNX833X_MIU_SEL1 = 0; + PNX833X_MIU_SEL0_TIMING = 0x50003081; + PNX833X_MIU_SEL1_TIMING = 0x50003081; + + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + pnx833x_gpio_select_function_alt(0); + + /* Setup GPIO 04 to input NAND read/busy signal */ + pnx833x_gpio_select_function_io(4); + pnx833x_gpio_select_input(4); + + /* Setup GPIO 05 to disable NAND write protect */ + pnx833x_gpio_select_function_io(5); + pnx833x_gpio_select_output(5); + pnx833x_gpio_write(1, 5); + +#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE) + + /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ + + /* Setup MIU CS0 & CS1 timing */ + PNX833X_MIU_SEL0 = 1; + PNX833X_MIU_SEL1 = 1; + PNX833X_MIU_SEL0_TIMING = 0x6A08D082; + PNX833X_MIU_SEL1_TIMING = 0x6A08D082; + + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + pnx833x_gpio_select_function_alt(0); +#endif +} diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index b1886244cedf..e8a97f59e066 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o -obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o +obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c index 846eae9cdd05..fba5aad00d51 100644 --- a/arch/mips/pci/fixup-emma2rh.c +++ b/arch/mips/pci/fixup-emma2rh.c @@ -30,7 +30,7 @@ #include -#include +#include #define EMMA2RH_PCI_HOST_SLOT 0x09 #define EMMA2RH_USB_SLOT 0x03 diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c index 75b90dcb7a09..3d86823d03a0 100644 --- a/arch/mips/pci/fixup-rc32434.c +++ b/arch/mips/pci/fixup-rc32434.c @@ -30,6 +30,7 @@ #include #include +#include static int __devinitdata irq_map[2][12] = { {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1}, diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c index d31bfc6d4150..5947a70b0b7f 100644 --- a/arch/mips/pci/ops-emma2rh.c +++ b/arch/mips/pci/ops-emma2rh.c @@ -30,7 +30,7 @@ #include #include -#include +#include #define RTABORT (0x1<<9) #define RMABORT (0x1<<10) diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c index 772e283daa63..2df4190232cd 100644 --- a/arch/mips/pci/pci-emma2rh.c +++ b/arch/mips/pci/pci-emma2rh.c @@ -30,7 +30,7 @@ #include -#include +#include static struct resource pci_io_resource = { .name = "pci IO space", diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index a377e9d2d029..62cae740e250 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -354,6 +354,30 @@ EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); #endif +int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine) +{ + unsigned long prot; + + /* + * I/O space can be accessed via normal processor loads and stores on + * this platform but for now we elect not to do this and portable + * drivers should not do this anyway. + */ + if (mmap_state == pci_mmap_io) + return -EINVAL; + + /* + * Ignore write-combine; for now only return uncached mappings. + */ + prot = pgprot_val(vma->vm_page_prot); + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; + vma->vm_page_prot = __pgprot(prot); + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot); +} + char * (*pcibios_plat_setup)(char *str) __devinitdata; char *__devinit pcibios_setup(char *str) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 31619c601b11..c1c29181bd46 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = { /* Resources and device for NAND */ static int rb532_dev_ready(struct mtd_info *mtd) { - return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; + return gpio_get_value(GPIO_RDY); } static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) @@ -280,7 +280,7 @@ static int __init plat_setup_devices(void) { /* Look for the CF card reader */ if (!readl(IDT434_REG_BASE + DEV1MASK)) - rb532_devs[1] = NULL; + rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */ else { cf_slot0_res[0].start = readl(IDT434_REG_BASE + DEV1BASE); diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 76a7fd96d564..0e84c8ab6a39 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -39,10 +39,6 @@ struct rb532_gpio_chip { struct gpio_chip chip; void __iomem *regbase; - void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_level)(struct gpio_chip *chip, unsigned offset); - void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value); - int (*get_int_status)(struct gpio_chip *chip, unsigned offset); }; struct mpmc_device dev3; @@ -111,15 +107,47 @@ unsigned char get_latch_u5(void) } EXPORT_SYMBOL(get_latch_u5); +/* rb532_set_bit - sanely set a bit + * + * bitval: new value for the bit + * offset: bit index in the 4 byte address range + * ioaddr: 4 byte aligned address being altered + */ +static inline void rb532_set_bit(unsigned bitval, + unsigned offset, void __iomem *ioaddr) +{ + unsigned long flags; + u32 val; + + bitval = !!bitval; /* map parameter to {0,1} */ + + local_irq_save(flags); + + val = readl(ioaddr); + val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ + val |= ( bitval << offset ); /* set bit if bitval == 1 */ + writel(val, ioaddr); + + local_irq_restore(flags); +} + +/* rb532_get_bit - read a bit + * + * returns the boolean state of the bit, which may be > 1 + */ +static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) +{ + return (readl(ioaddr) & (1 << offset)); +} + /* * Return GPIO level */ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) { - u32 mask = 1 << offset; struct rb532_gpio_chip *gpch; gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOD) & mask; + return rb532_get_bit(offset, gpch->regbase + GPIOD); } /* @@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) static void rb532_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpvr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpvr = gpch->regbase + GPIOD; - - local_irq_save(flags); - tmp = readl(gpvr); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpvr); - local_irq_restore(flags); + rb532_set_bit(value, offset, gpch->regbase + GPIOD); } /* @@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip, */ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - unsigned long flags; - u32 mask = 1 << offset; - u32 value; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - value = readl(gpdr); - value &= ~mask; - writel(value, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); return 0; } @@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int rb532_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; struct rb532_gpio_chip *gpch; - void __iomem *gpdr; gpch = container_of(chip, struct rb532_gpio_chip, chip); - writel(mask, gpch->regbase + GPIOD); - gpdr = gpch->regbase + GPIOCFG; - local_irq_save(flags); - tmp = readl(gpdr); - tmp |= mask; - writel(tmp, gpdr); - local_irq_restore(flags); + if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) + return 1; /* alternate function, GPIOCFG is ignored */ + + /* set the initial output value */ + rb532_set_bit(value, offset, gpch->regbase + GPIOD); + rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); return 0; } -/* - * Set the GPIO interrupt level - */ -static void rb532_gpio_set_int_level(struct gpio_chip *chip, - unsigned offset, int value) -{ - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpil; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpil = gpch->regbase + GPIOILEVEL; - - local_irq_save(flags); - tmp = readl(gpil); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpil); - local_irq_restore(flags); -} +static struct rb532_gpio_chip rb532_gpio_chip[] = { + [0] = { + .chip = { + .label = "gpio0", + .direction_input = rb532_gpio_direction_input, + .direction_output = rb532_gpio_direction_output, + .get = rb532_gpio_get, + .set = rb532_gpio_set, + .base = 0, + .ngpio = 32, + }, + }, +}; /* - * Get the GPIO interrupt level + * Set GPIO interrupt level */ -static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset) +void rb532_gpio_set_ilevel(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOILEVEL) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); } +EXPORT_SYMBOL(rb532_gpio_set_ilevel); /* - * Set the GPIO interrupt status + * Set GPIO interrupt status */ -static void rb532_gpio_set_int_status(struct gpio_chip *chip, - unsigned offset, int value) +void rb532_gpio_set_istat(int bit, unsigned gpio) { - unsigned long flags; - u32 mask = 1 << offset; - u32 tmp; - struct rb532_gpio_chip *gpch; - void __iomem *gpis; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - gpis = gpch->regbase + GPIOISTAT; - - local_irq_save(flags); - tmp = readl(gpis); - if (value) - tmp |= mask; - else - tmp &= ~mask; - writel(tmp, gpis); - local_irq_restore(flags); + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); } +EXPORT_SYMBOL(rb532_gpio_set_istat); /* - * Get the GPIO interrupt status + * Configure GPIO alternate function */ -static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset) +static void rb532_gpio_set_func(int bit, unsigned gpio) { - u32 mask = 1 << offset; - struct rb532_gpio_chip *gpch; - - gpch = container_of(chip, struct rb532_gpio_chip, chip); - return readl(gpch->regbase + GPIOISTAT) & mask; + rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); } -static struct rb532_gpio_chip rb532_gpio_chip[] = { - [0] = { - .chip = { - .label = "gpio0", - .direction_input = rb532_gpio_direction_input, - .direction_output = rb532_gpio_direction_output, - .get = rb532_gpio_get, - .set = rb532_gpio_set, - .base = 0, - .ngpio = 32, - }, - .get_int_level = rb532_gpio_get_int_level, - .set_int_level = rb532_gpio_set_int_level, - .get_int_status = rb532_gpio_get_int_status, - .set_int_status = rb532_gpio_set_int_status, - }, -}; - int __init rb532_gpio_init(void) { struct resource *r; @@ -310,6 +261,12 @@ int __init rb532_gpio_init(void) return -ENXIO; } + /* configure CF_GPIO_NUM as CFRDY IRQ source */ + rb532_gpio_set_func(0, CF_GPIO_NUM); + rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); + rb532_gpio_set_ilevel(1, CF_GPIO_NUM); + rb532_gpio_set_istat(0, CF_GPIO_NUM); + return 0; } arch_initcall(rb532_gpio_init); diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index f6d9bf4b26e7..f8b18af141a1 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -12,20 +12,11 @@ #include #include #include -#include -#include #include -#include -#include -#include #include -#include #include #include -#include - -/* #define DEBUG_SGINT */ /* So far nothing hangs here */ #undef USE_LIO3_IRQ @@ -68,7 +59,7 @@ static void enable_local1_irq(unsigned int irq) sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); } -void disable_local1_irq(unsigned int irq) +static void disable_local1_irq(unsigned int irq) { sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); } @@ -87,7 +78,7 @@ static void enable_local2_irq(unsigned int irq) sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); } -void disable_local2_irq(unsigned int irq) +static void disable_local2_irq(unsigned int irq) { sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); if (!sgint->cmeimask0) @@ -108,7 +99,7 @@ static void enable_local3_irq(unsigned int irq) sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); } -void disable_local3_irq(unsigned int irq) +static void disable_local3_irq(unsigned int irq) { sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); if (!sgint->cmeimask1) @@ -344,6 +335,6 @@ void __init arch_init_irq(void) #ifdef CONFIG_EISA if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ - ip22_eisa_init(); + ip22_eisa_init(); #endif } diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index 17052db4161d..226e8bb2f0a1 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -46,9 +46,10 @@ config TOSHIBA_RBTX4938 support this machine type config TOSHIBA_RBTX4939 - bool "Toshiba RBTX4939 bobard" + bool "Toshiba RBTX4939 board" depends on MACH_TX49XX select SOC_TX4939 + select TXX9_7SEGLED help This Toshiba board is based on the TX4939 processor. Say Y here to support this machine type @@ -86,6 +87,9 @@ config SOC_TX4939 select HW_HAS_PCI select PCI_TX4927 +config TXX9_7SEGLED + bool + config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" depends on PCI && MACH_TXX9 diff --git a/arch/mips/txx9/generic/7segled.c b/arch/mips/txx9/generic/7segled.c new file mode 100644 index 000000000000..727ab21b6618 --- /dev/null +++ b/arch/mips/txx9/generic/7segled.c @@ -0,0 +1,112 @@ +/* + * 7 Segment LED routines + * Based on RBTX49xx patch from CELF patch archive. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright TOSHIBA CORPORATION 2005-2007 + * All Rights Reserved. + */ +#include +#include +#include +#include + +static unsigned int tx_7segled_num; +static void (*tx_7segled_putc)(unsigned int pos, unsigned char val); + +void __init txx9_7segled_init(unsigned int num, + void (*putc)(unsigned int pos, unsigned char val)) +{ + tx_7segled_num = num; + tx_7segled_putc = putc; +} + +static SEG7_CONVERSION_MAP(txx9_seg7map, MAP_ASCII7SEG_ALPHANUM_LC); + +int txx9_7segled_putc(unsigned int pos, char c) +{ + if (pos >= tx_7segled_num) + return -EINVAL; + c = map_to_seg7(&txx9_seg7map, c); + if (c < 0) + return c; + tx_7segled_putc(pos, c); + return 0; +} + +static ssize_t ascii_store(struct sys_device *dev, + struct sysdev_attribute *attr, + const char *buf, size_t size) +{ + unsigned int ch = dev->id; + txx9_7segled_putc(ch, buf[0]); + return size; +} + +static ssize_t raw_store(struct sys_device *dev, + struct sysdev_attribute *attr, + const char *buf, size_t size) +{ + unsigned int ch = dev->id; + tx_7segled_putc(ch, buf[0]); + return size; +} + +static SYSDEV_ATTR(ascii, 0200, NULL, ascii_store); +static SYSDEV_ATTR(raw, 0200, NULL, raw_store); + +static ssize_t map_seg7_show(struct sysdev_class *class, char *buf) +{ + memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map)); + return sizeof(txx9_seg7map); +} + +static ssize_t map_seg7_store(struct sysdev_class *class, + const char *buf, size_t size) +{ + if (size != sizeof(txx9_seg7map)) + return -EINVAL; + memcpy(&txx9_seg7map, buf, size); + return size; +} + +static SYSDEV_CLASS_ATTR(map_seg7, 0600, map_seg7_show, map_seg7_store); + +static struct sysdev_class tx_7segled_sysdev_class = { + .name = "7segled", +}; + +static int __init tx_7segled_init_sysfs(void) +{ + int error, i; + if (!tx_7segled_num) + return -ENODEV; + error = sysdev_class_register(&tx_7segled_sysdev_class); + if (error) + return error; + error = sysdev_class_create_file(&tx_7segled_sysdev_class, + &attr_map_seg7); + if (error) + return error; + for (i = 0; i < tx_7segled_num; i++) { + struct sys_device *dev; + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + error = -ENODEV; + break; + } + dev->id = i; + dev->cls = &tx_7segled_sysdev_class; + error = sysdev_register(dev); + if (!error) { + sysdev_create_file(dev, &attr_ascii); + sysdev_create_file(dev, &attr_raw); + } + } + return error; +} + +device_initcall(tx_7segled_init_sysfs); diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index 0030d23bef5b..f2579ce054a1 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o obj-$(CONFIG_SPI) += spi_eeprom.o +obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 5526375010f8..a13a08b8c9ec 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -156,11 +156,23 @@ static struct txx9_board_vec *__init find_board_byname(const char *name) static void __init prom_init_cmdline(void) { - int argc = (int)fw_arg0; - int *argv32 = (int *)fw_arg1; + int argc; + int *argv32; int i; /* Always ignore the "-c" at argv[0] */ char builtin[CL_SIZE]; + if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { + /* + * argc is not a valid number, or argv32 is not a valid + * pointer + */ + argc = 0; + argv32 = NULL; + } else { + argc = (int)fw_arg0; + argv32 = (int *)fw_arg1; + } + /* ignore all built-in args if any f/w args given */ /* * But if built-in strings was started with '+', append them @@ -414,10 +426,12 @@ char * __init prom_getcmdline(void) const char *__init prom_getenv(const char *name) { - const s32 *str = (const s32 *)fw_arg2; + const s32 *str; - if (!str) + if (fw_arg2 < CKSEG0) return NULL; + + str = (const s32 *)fw_arg2; /* YAMON style ("name", "value" pairs) */ while (str[0] && str[1]) { if (!strcmp((const char *)(unsigned long)str[0], name)) @@ -622,6 +636,21 @@ unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none; EXPORT_SYMBOL(__swizzle_addr_b); #endif +#ifdef NEEDS_TXX9_IOSWABW +static u16 ioswabw_default(volatile u16 *a, u16 x) +{ + return le16_to_cpu(x); +} +static u16 __mem_ioswabw_default(volatile u16 *a, u16 x) +{ + return x; +} +u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default; +EXPORT_SYMBOL(ioswabw); +u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default; +EXPORT_SYMBOL(__mem_ioswabw); +#endif + void __init txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size, const struct physmap_flash_data *pdata) diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 4a74423b2ba8..01129a9d50fa 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void) /* TX4927-SIO DTR on (PIO[15]) */ gpio_request(15, "sio-dtr"); gpio_direction_output(15, 1); - gpio_request(0, "led"); - gpio_direction_output(0, 1); - gpio_request(1, "led"); - gpio_direction_output(1, 1); tx4927_sio_init(0, 0); #ifdef CONFIG_SERIAL_TXX9_CONSOLE @@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void) tx4927_mtd_init(i); } +static void __init rbtx4927_gpioled_init(void) +{ + static struct gpio_led leds[] = { + { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, + { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, + }; + static struct gpio_led_platform_data pdata = { + .num_leds = ARRAY_SIZE(leds), + .leds = leds, + }; + struct platform_device *pdev = platform_device_alloc("leds-gpio", 0); + + if (!pdev) + return; + pdev->dev.platform_data = &pdata; + if (platform_device_add(pdev)) + platform_device_put(pdev); +} + static void __init rbtx4927_device_init(void) { toshiba_rbtx4927_rtc_init(); @@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void) tx4927_wdt_init(); rbtx4927_mtd_init(); txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); + rbtx4927_gpioled_init(); } struct txx9_board_vec rbtx4927_vec __initdata = { diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 9855d7bccc20..98fbd9391bf8 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -33,6 +35,21 @@ static void __init rbtx4939_time_init(void) tx4939_time_init(0); } +#if defined(__BIG_ENDIAN) && \ + (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) +#define HAVE_RBTX4939_IOSWAB +#define IS_CE1_ADDR(addr) \ + ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1)) +static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x) +{ + return IS_CE1_ADDR(a) ? x : le16_to_cpu(x); +} +static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x) +{ + return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x); +} +#endif /* __BIG_ENDIAN && CONFIG_SMC91X */ + static void __init rbtx4939_pci_setup(void) { #ifdef CONFIG_PCI @@ -239,6 +256,32 @@ static inline void rbtx4939_led_setup(void) } #endif +static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val) +{ +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) + unsigned long flags; + local_irq_save(flags); + /* bit7: reserved for LED class */ + led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f); + val = led_val[pos]; + local_irq_restore(flags); +#endif + writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4)); +} + +static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val) +{ + /* convert from map_to_seg7() notation */ + val = (val & 0x88) | + ((val & 0x40) >> 6) | + ((val & 0x20) >> 4) | + ((val & 0x10) >> 2) | + ((val & 0x04) << 2) | + ((val & 0x02) << 4) | + ((val & 0x01) << 6); + __rbtx4939_7segled_putc(pos, val); +} + static void __init rbtx4939_arch_init(void) { rbtx4939_pci_setup(); @@ -246,22 +289,50 @@ static void __init rbtx4939_arch_init(void) static void __init rbtx4939_device_init(void) { + unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE; + struct resource smc_res[] = { + { + .start = smc_addr, + .end = smc_addr + 0x10 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = RBTX4939_IRQ_ETHER, + /* override default irq flag defined in smc91x.h */ + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, + }; + struct smc91x_platdata smc_pdata = { + .flags = SMC91X_USE_16BIT, + }; + struct platform_device *pdev; #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) int i, j; unsigned char ethaddr[2][6]; + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + for (i = 0; i < 2; i++) { unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10); - if (readb(rbtx4939_bdipsw_addr) & 8) { + if (bdipsw == 0) + memcpy(ethaddr[i], (void *)area, 6); + else { u16 buf[3]; - area -= 0x03000000; + if (bdipsw & 8) + area -= 0x03000000; + else + area -= 0x01000000; for (j = 0; j < 3; j++) buf[j] = le16_to_cpup((u16 *)(area + j * 2)); memcpy(ethaddr[i], buf, 6); - } else - memcpy(ethaddr[i], (void *)area, 6); + } } tx4939_ethaddr_init(ethaddr[0], ethaddr[1]); #endif + pdev = platform_device_alloc("smc91x", -1); + if (!pdev || + platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) || + platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) || + platform_device_add(pdev)) + platform_device_put(pdev); rbtx4939_led_setup(); tx4939_wdt_init(); tx4939_ata_init(); @@ -269,6 +340,8 @@ static void __init rbtx4939_device_init(void) static void __init rbtx4939_setup(void) { + int i; + rbtx4939_ebusc_setup(); /* always enable ATA0 */ txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE); @@ -276,9 +349,16 @@ static void __init rbtx4939_setup(void) if (txx9_master_clock == 0) txx9_master_clock = 20000000; tx4939_setup(); +#ifdef HAVE_RBTX4939_IOSWAB + ioswabw = rbtx4939_ioswabw; + __mem_ioswabw = rbtx4939_mem_ioswabw; +#endif _machine_restart = rbtx4939_machine_restart; + txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc); + for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) + txx9_7segled_putc(i, '-'); pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr), readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr)); diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug index 524e33819f32..ff80e86b9bd2 100644 --- a/arch/mn10300/Kconfig.debug +++ b/arch/mn10300/Kconfig.debug @@ -15,6 +15,15 @@ config DEBUG_DECOMPRESS_KERNEL decompressing Linux seeing "Uncompressing Linux... " and "Ok, booting the kernel.\n" on console. +config TEST_MISALIGNMENT_HANDLER + bool "Run tests on the misalignment handler" + depends on DEBUG_KERNEL + default n + help + If you say Y here the kernel will execute a list of misaligned memory + accesses to make sure the misalignment handler deals them with + correctly. If it does not, the kernel will throw a BUG. + config KPROBES bool "Kprobes" depends on DEBUG_KERNEL diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S index b7cbb1487af4..62fba8aa9b6e 100644 --- a/arch/mn10300/kernel/entry.S +++ b/arch/mn10300/kernel/entry.S @@ -180,6 +180,7 @@ ENTRY(resume_userspace) #ifdef CONFIG_PREEMPT ENTRY(resume_kernel) + __cli mov (TI_preempt_count,a2),d0 # non-zero preempt_count ? cmp 0,d0 bne restore_all @@ -190,7 +191,7 @@ need_resched: mov (REG_EPSW,fp),d0 and EPSW_IM,d0 cmp EPSW_IM_7,d0 # interrupts off (exception path) ? - beq restore_all + bne restore_all call preempt_schedule_irq[],0 jmp need_resched #endif diff --git a/arch/mn10300/kernel/gdb-io-serial.c b/arch/mn10300/kernel/gdb-io-serial.c index 9a6d4e8ebe73..11584c51acd9 100644 --- a/arch/mn10300/kernel/gdb-io-serial.c +++ b/arch/mn10300/kernel/gdb-io-serial.c @@ -99,6 +99,7 @@ int gdbstub_io_rx_char(unsigned char *_ch, int nonblock) try_again: /* pull chars out of the buffer */ ix = gdbstub_rx_outp; + barrier(); if (ix == gdbstub_rx_inp) { if (nonblock) return -EAGAIN; @@ -110,6 +111,7 @@ int gdbstub_io_rx_char(unsigned char *_ch, int nonblock) ch = gdbstub_rx_buffer[ix++]; st = gdbstub_rx_buffer[ix++]; + barrier(); gdbstub_rx_outp = ix & 0x00000fff; if (st & UART_LSR_BI) { diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c index 54be6afb5555..0ea7482c1522 100644 --- a/arch/mn10300/kernel/gdb-stub.c +++ b/arch/mn10300/kernel/gdb-stub.c @@ -522,17 +522,7 @@ static int gdbstub_single_step(struct pt_regs *regs) } else { switch (cur) { /* Bxx (d8,PC) */ - case 0xc0: - case 0xc1: - case 0xc2: - case 0xc3: - case 0xc4: - case 0xc5: - case 0xc6: - case 0xc7: - case 0xc8: - case 0xc9: - case 0xca: + case 0xc0 ... 0xca: if (gdbstub_read_byte(pc + 1, (u8 *) &x) < 0) goto fault; if (!__gdbstub_mark_bp(pc + 2, 0)) @@ -543,17 +533,7 @@ static int gdbstub_single_step(struct pt_regs *regs) break; /* LXX (d8,PC) */ - case 0xd0: - case 0xd1: - case 0xd2: - case 0xd3: - case 0xd4: - case 0xd5: - case 0xd6: - case 0xd7: - case 0xd8: - case 0xd9: - case 0xda: + case 0xd0 ... 0xda: if (!__gdbstub_mark_bp(pc + 1, 0)) goto fault; if (regs->pc != regs->lar && diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c index aa07d0cd1905..59b9c4bf9583 100644 --- a/arch/mn10300/kernel/mn10300-serial.c +++ b/arch/mn10300/kernel/mn10300-serial.c @@ -566,6 +566,11 @@ static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port) { _enter("%s", port->name); + if (!port->uart.info || !port->uart.info->port.tty) { + mn10300_serial_dis_tx_intr(port); + return; + } + if (uart_tx_stopped(&port->uart) || uart_circ_empty(&port->uart.info->xmit)) mn10300_serial_dis_tx_intr(port); diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c index 8fa36893df7a..6b287f2e8e84 100644 --- a/arch/mn10300/kernel/module.c +++ b/arch/mn10300/kernel/module.c @@ -1,6 +1,6 @@ /* MN10300 Kernel module helper routines * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Copyright (C) 2007, 2008 Red Hat, Inc. All Rights Reserved. * Written by Mark Salter (msalter@redhat.com) * - Derived from arch/i386/kernel/module.c * @@ -64,21 +64,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, return 0; } -static uint32_t reloc_get16(uint8_t *p) -{ - return p[0] | (p[1] << 8); -} - -static uint32_t reloc_get24(uint8_t *p) -{ - return reloc_get16(p) | (p[2] << 16); -} - -static uint32_t reloc_get32(uint8_t *p) -{ - return reloc_get16(p) | (reloc_get16(p+2) << 16); -} - static void reloc_put16(uint8_t *p, uint32_t val) { p[0] = val & 0xff; @@ -144,25 +129,19 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, relocation = sym->st_value + rel[i].r_addend; switch (ELF32_R_TYPE(rel[i].r_info)) { - /* for the first four relocation types, we add the - * adjustment into the value at the location given */ + /* for the first four relocation types, we simply + * store the adjustment at the location given */ case R_MN10300_32: - value = reloc_get32(location); - value += relocation; - reloc_put32(location, value); + reloc_put32(location, relocation); break; case R_MN10300_24: - value = reloc_get24(location); - value += relocation; - reloc_put24(location, value); + reloc_put24(location, relocation); break; case R_MN10300_16: - value = reloc_get16(location); - value += relocation; - reloc_put16(location, value); + reloc_put16(location, relocation); break; case R_MN10300_8: - *location += relocation; + *location = relocation; break; /* for the next three relocation types, we write the diff --git a/arch/mn10300/kernel/setup.c b/arch/mn10300/kernel/setup.c index 017121ce896f..e1d88ab51008 100644 --- a/arch/mn10300/kernel/setup.c +++ b/arch/mn10300/kernel/setup.c @@ -161,7 +161,7 @@ void __init setup_arch(char **cmdline_p) reserve the page it is occupying. */ if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS && CONFIG_INTERRUPT_VECTOR_BASE < memory_end) - reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, 1, + reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, PAGE_SIZE, BOOTMEM_DEFAULT); reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size, diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S index a3e80f444f55..b8259668f7dc 100644 --- a/arch/mn10300/kernel/vmlinux.lds.S +++ b/arch/mn10300/kernel/vmlinux.lds.S @@ -11,6 +11,7 @@ #define __VMLINUX_LDS__ #include #include +#include OUTPUT_FORMAT("elf32-am33lin", "elf32-am33lin", "elf32-am33lin") OUTPUT_ARCH(mn10300) @@ -55,13 +56,13 @@ SECTIONS CONSTRUCTORS } - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __nosave_begin = .; .data_nosave : { *(.data.nosave) } - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __nosave_end = .; - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); .data.page_aligned : { *(.data.idt) } . = ALIGN(32); @@ -78,7 +79,7 @@ SECTIONS .data.init_task : { *(.data.init_task) } /* might get freed after init */ - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { __smp_locks = .; *(.smp_locks) @@ -86,7 +87,7 @@ SECTIONS } /* will be freed after init */ - . = ALIGN(4096); /* Init code and data */ + . = ALIGN(PAGE_SIZE); /* Init code and data */ __init_begin = .; .init.text : { _sinittext = .; @@ -120,17 +121,14 @@ SECTIONS .exit.data : { *(.exit.data) } #ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __initramfs_start = .; .init.ramfs : { *(.init.ramfs) } __initramfs_end = .; #endif - . = ALIGN(32); - __per_cpu_start = .; - .data.percpu : { *(.data.percpu) } - __per_cpu_end = .; - . = ALIGN(4096); + PERCPU(32) + . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ @@ -145,7 +143,7 @@ SECTIONS _end = . ; /* This is where the kernel creates the early boot page tables */ - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); pg0 = .; /* Sections to be discarded */ diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index 32aa89dc3848..94c4a4358065 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -37,26 +37,22 @@ #include #if 0 -#define kdebug(FMT, ...) printk(KERN_DEBUG FMT, ##__VA_ARGS__) +#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__) #else #define kdebug(FMT, ...) do {} while (0) #endif -static int misalignment_addr(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, - void **_address, unsigned long **_postinc); +static int misalignment_addr(unsigned long *registers, unsigned long sp, + unsigned params, unsigned opcode, + unsigned long disp, + void **_address, unsigned long **_postinc, + unsigned long *_inc); static int misalignment_reg(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, + unsigned opcode, unsigned long disp, unsigned long **_register); -static inline unsigned int_log2(unsigned x) -{ - unsigned y; - asm("bsch %1,%0" : "=r"(y) : "r"(x), "0"(0)); - return y; -} -#define log2(x) int_log2(x) +static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode); static const unsigned Dreg_index[] = { REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 @@ -86,9 +82,10 @@ enum format_id { FMT_D7, FMT_D8, FMT_D9, + FMT_D10, }; -struct { +static const struct { u_int8_t opsz, dispsz; } format_tbl[16] = { [FMT_S0] = { 8, 0 }, @@ -103,6 +100,7 @@ struct { [FMT_D7] = { 24, 8 }, [FMT_D8] = { 24, 24 }, [FMT_D9] = { 24, 32 }, + [FMT_D10] = { 32, 0 }, }; enum value_id { @@ -128,9 +126,14 @@ enum value_id { SD24, /* 24-bit signed displacement */ SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */ SIMM8, /* 8-bit signed immediate */ + IMM8, /* 8-bit unsigned immediate */ + IMM16, /* 16-bit unsigned immediate */ IMM24, /* 24-bit unsigned immediate */ IMM32, /* 32-bit unsigned immediate */ - IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */ + IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */ + + IMM32_MEM, /* 32-bit unsigned displacement */ + IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */ DN0 = DM0, DN1 = DM1, @@ -149,7 +152,7 @@ enum value_id { }; struct mn10300_opcode { - const char *name; + const char name[8]; u_int32_t opcode; u_int32_t opmask; unsigned exclusion; @@ -185,6 +188,10 @@ struct mn10300_opcode { Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static const struct mn10300_opcode mn10300_opcodes[] = { +{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, +{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, +{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, @@ -197,8 +204,6 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, -{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, -{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, @@ -207,24 +212,46 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, +{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, +{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, +{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, +{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, +{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, +{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, +{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, +{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, +{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, +{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, @@ -232,29 +259,58 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, -{ 0, 0, 0, 0, 0, 0, {0}}, + +{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, + +{ "", 0, 0, 0, 0, 0, {0}}, }; /* @@ -265,18 +321,21 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) const struct exception_table_entry *fixup; const struct mn10300_opcode *pop; unsigned long *registers = (unsigned long *) regs; - unsigned long data, *store, *postinc; + unsigned long data, *store, *postinc, disp, inc, sp; mm_segment_t seg; siginfo_t info; - uint32_t opcode, disp, noc, xo, xm; - uint8_t *pc, byte; + uint32_t opcode, noc, xo, xm; + uint8_t *pc, byte, datasz; void *address; - unsigned tmp, npop; + unsigned tmp, npop, dispsz, loop; + + /* we don't fix up userspace misalignment faults */ + if (user_mode(regs)) + goto bus_error; - kdebug("MISALIGN at %lx\n", regs->pc); + sp = (unsigned long) regs + sizeof(*regs); - if (in_interrupt()) - die("Misalignment trap in interrupt context", regs, code); + kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp); if (regs->epsw & EPSW_IE) asm volatile("or %0,epsw" : : "i"(EPSW_IE)); @@ -294,8 +353,8 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) opcode = byte; noc = 8; - for (pop = mn10300_opcodes; pop->name; pop++) { - npop = log2(pop->opcode | pop->opmask); + for (pop = mn10300_opcodes; pop->name[0]; pop++) { + npop = ilog2(pop->opcode | pop->opmask); if (npop <= 0 || npop > 31) continue; npop = (npop + 8) & ~7; @@ -328,15 +387,15 @@ asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) } /* didn't manage to find a fixup */ - if (!user_mode(regs)) - printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", - regs->pc, opcode); + printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", + regs->pc, opcode); failed: set_fs(seg); if (die_if_no_fixup("misalignment error", regs, code)) return; +bus_error: info.si_signo = SIGBUS; info.si_errno = 0; info.si_code = BUS_ADRALN; @@ -346,31 +405,27 @@ failed: /* error reading opcodes */ fetch_error: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %p: fault whilst reading instruction data\n", - pc); + printk(KERN_CRIT + "MISALIGN: %p: fault whilst reading instruction data\n", + pc); goto failed; bad_addr_mode: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx: unsupported addressing mode %x\n", - regs->pc, opcode); + printk(KERN_CRIT + "MISALIGN: %lx: unsupported addressing mode %x\n", + regs->pc, opcode); goto failed; bad_reg_mode: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx: unsupported register mode %x\n", - regs->pc, opcode); + printk(KERN_CRIT + "MISALIGN: %lx: unsupported register mode %x\n", + regs->pc, opcode); goto failed; unsupported_instruction: - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx: unsupported instruction %x (%s)\n", - regs->pc, opcode, pop->name); + printk(KERN_CRIT + "MISALIGN: %lx: unsupported instruction %x (%s)\n", + regs->pc, opcode, pop->name); goto failed; transfer_failed: @@ -391,7 +446,7 @@ transfer_failed: /* we matched the opcode */ found_opcode: - kdebug("MISALIGN: %lx: %x==%x { %x, %x }\n", + kdebug("%lx: %x==%x { %x, %x }", regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]); tmp = format_tbl[pop->format].opsz; @@ -406,106 +461,108 @@ found_opcode: /* grab the extra displacement (note it's LSB first) */ disp = 0; - tmp = format_tbl[pop->format].dispsz >> 3; - while (tmp > 0) { - tmp--; - disp <<= 8; - + dispsz = format_tbl[pop->format].dispsz; + for (loop = 0; loop < dispsz; loop += 8) { pc++; if (__get_user(byte, pc) != 0) goto fetch_error; - disp |= byte; + disp |= byte << loop; + kdebug("{%p} disp[%02x]=%02x", pc, loop, byte); } + kdebug("disp=%lx", disp); + set_fs(KERNEL_XDS); - if (fixup || regs->epsw & EPSW_nSL) + if (fixup) set_fs(seg); tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000; if (!tmp) { - if (!user_mode(regs)) - printk(KERN_CRIT - "MISALIGN: %lx:" - " insn not move to/from memory %x\n", - regs->pc, opcode); + printk(KERN_CRIT + "MISALIGN: %lx: insn not move to/from memory %x\n", + regs->pc, opcode); goto failed; } + /* determine the data transfer size of the move */ + if (pop->name[3] == 0 || /* "mov" */ + pop->name[4] == 'l') /* mov_lcc */ + inc = datasz = 4; + else if (pop->name[3] == 'h') /* movhu */ + inc = datasz = 2; + else + goto unsupported_instruction; + if (pop->params[0] & 0x80000000) { /* move memory to register */ - if (!misalignment_addr(registers, pop->params[0], opcode, disp, - &address, &postinc)) + if (!misalignment_addr(registers, sp, + pop->params[0], opcode, disp, + &address, &postinc, &inc)) goto bad_addr_mode; if (!misalignment_reg(registers, pop->params[1], opcode, disp, &store)) goto bad_reg_mode; - if (strcmp(pop->name, "mov") == 0) { - kdebug("FIXUP: mov (%p),DARn\n", address); - if (copy_from_user(&data, (void *) address, 4) != 0) - goto transfer_failed; - if (pop->params[0] & 0x1000000) - *postinc += 4; - } else if (strcmp(pop->name, "movhu") == 0) { - kdebug("FIXUP: movhu (%p),DARn\n", address); - data = 0; - if (copy_from_user(&data, (void *) address, 2) != 0) - goto transfer_failed; - if (pop->params[0] & 0x1000000) - *postinc += 2; - } else { - goto unsupported_instruction; + kdebug("mov%u (%p),DARn", datasz, address); + if (copy_from_user(&data, (void *) address, datasz) != 0) + goto transfer_failed; + if (pop->params[0] & 0x1000000) { + kdebug("inc=%lx", inc); + *postinc += inc; } *store = data; + kdebug("loaded %lx", data); } else { /* move register to memory */ if (!misalignment_reg(registers, pop->params[0], opcode, disp, &store)) goto bad_reg_mode; - if (!misalignment_addr(registers, pop->params[1], opcode, disp, - &address, &postinc)) + if (!misalignment_addr(registers, sp, + pop->params[1], opcode, disp, + &address, &postinc, &inc)) goto bad_addr_mode; data = *store; - if (strcmp(pop->name, "mov") == 0) { - kdebug("FIXUP: mov %lx,(%p)\n", data, address); - if (copy_to_user((void *) address, &data, 4) != 0) - goto transfer_failed; - if (pop->params[1] & 0x1000000) - *postinc += 4; - } else if (strcmp(pop->name, "movhu") == 0) { - kdebug("FIXUP: movhu %hx,(%p)\n", - (uint16_t) data, address); - if (copy_to_user((void *) address, &data, 2) != 0) - goto transfer_failed; - if (pop->params[1] & 0x1000000) - *postinc += 2; - } else { - goto unsupported_instruction; - } + kdebug("mov%u %lx,(%p)", datasz, data, address); + if (copy_to_user((void *) address, &data, datasz) != 0) + goto transfer_failed; + if (pop->params[1] & 0x1000000) + *postinc += inc; } tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz; regs->pc += tmp >> 3; + /* handle MOV_Lcc, which are currently the only FMT_D10 insns that + * access memory */ + if (pop->format == FMT_D10) + misalignment_MOV_Lcc(regs, opcode); + set_fs(seg); - return; } /* * determine the address that was being accessed */ -static int misalignment_addr(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, - void **_address, unsigned long **_postinc) +static int misalignment_addr(unsigned long *registers, unsigned long sp, + unsigned params, unsigned opcode, + unsigned long disp, + void **_address, unsigned long **_postinc, + unsigned long *_inc) { unsigned long *postinc = NULL, address = 0, tmp; - params &= 0x7fffffff; + if (!(params & 0x1000000)) { + kdebug("noinc"); + *_inc = 0; + _inc = NULL; + } + + params &= 0x00ffffff; do { switch (params & 0xff) { @@ -514,11 +571,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += *postinc; break; case DM1: - postinc = ®isters[Dreg_index[opcode >> 2 & 0x0c]]; + postinc = ®isters[Dreg_index[opcode >> 2 & 0x03]]; address += *postinc; break; case DM2: - postinc = ®isters[Dreg_index[opcode >> 4 & 0x30]]; + postinc = ®isters[Dreg_index[opcode >> 4 & 0x03]]; address += *postinc; break; case AM0: @@ -526,11 +583,11 @@ static int misalignment_addr(unsigned long *registers, unsigned params, address += *postinc; break; case AM1: - postinc = ®isters[Areg_index[opcode >> 2 & 0x0c]]; + postinc = ®isters[Areg_index[opcode >> 2 & 0x03]]; address += *postinc; break; case AM2: - postinc = ®isters[Areg_index[opcode >> 4 & 0x30]]; + postinc = ®isters[Areg_index[opcode >> 4 & 0x03]]; address += *postinc; break; case RM0: @@ -561,33 +618,53 @@ static int misalignment_addr(unsigned long *registers, unsigned params, postinc = ®isters[Rreg_index[disp >> 4 & 0x0f]]; address += *postinc; break; + case SP: + address += sp; + break; + /* displacements are either to be added to the address + * before use, or, in the case of post-inc addressing, + * to be added into the base register after use */ case SD8: case SIMM8: - address += (int32_t) (int8_t) (disp & 0xff); - break; + disp = (long) (int8_t) (disp & 0xff); + goto displace_or_inc; case SD16: - address += (int32_t) (int16_t) (disp & 0xffff); - break; + disp = (long) (int16_t) (disp & 0xffff); + goto displace_or_inc; case SD24: tmp = disp << 8; asm("asr 8,%0" : "=r"(tmp) : "0"(tmp)); - address += tmp; - break; + disp = (long) tmp; + goto displace_or_inc; case SIMM4_2: tmp = opcode >> 4 & 0x0f; tmp <<= 28; asm("asr 28,%0" : "=r"(tmp) : "0"(tmp)); - address += tmp; - break; + disp = (long) tmp; + goto displace_or_inc; + case IMM8: + disp &= 0x000000ff; + goto displace_or_inc; + case IMM16: + disp &= 0x0000ffff; + goto displace_or_inc; case IMM24: - address += disp & 0x00ffffff; - break; + disp &= 0x00ffffff; + goto displace_or_inc; case IMM32: + case IMM32_MEM: case IMM32_HIGH8: - address += disp; + case IMM32_HIGH8_MEM: + displace_or_inc: + kdebug("%s %lx", _inc ? "incr" : "disp", disp); + if (!_inc) + address += disp; + else + *_inc = disp; break; default: + BUG(); return 0; } } while ((params >>= 8)); @@ -601,7 +678,7 @@ static int misalignment_addr(unsigned long *registers, unsigned params, * determine the register that is acting as source/dest */ static int misalignment_reg(unsigned long *registers, unsigned params, - unsigned opcode, unsigned disp, + unsigned opcode, unsigned long disp, unsigned long **_register) { params &= 0x7fffffff; @@ -654,8 +731,239 @@ static int misalignment_reg(unsigned long *registers, unsigned params, break; default: + BUG(); return 0; } return 1; } + +/* + * handle the conditional loop part of the move-and-loop instructions + */ +static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode) +{ + unsigned long epsw = regs->epsw; + unsigned long NxorV; + + kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf); + + /* calculate N^V and shift onto the same bit position as Z */ + NxorV = ((epsw >> 3) ^ epsw >> 1) & 1; + + switch (opcode & 0xf) { + case 0x0: /* MOV_LLT: N^V */ + if (NxorV) + goto take_the_loop; + return; + case 0x1: /* MOV_LGT: ~(Z or (N^V))*/ + if (!((epsw & EPSW_FLAG_Z) | NxorV)) + goto take_the_loop; + return; + case 0x2: /* MOV_LGE: ~(N^V) */ + if (!NxorV) + goto take_the_loop; + return; + case 0x3: /* MOV_LLE: Z or (N^V) */ + if ((epsw & EPSW_FLAG_Z) | NxorV) + goto take_the_loop; + return; + + case 0x4: /* MOV_LCS: C */ + if (epsw & EPSW_FLAG_C) + goto take_the_loop; + return; + case 0x5: /* MOV_LHI: ~(C or Z) */ + if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))) + goto take_the_loop; + return; + case 0x6: /* MOV_LCC: ~C */ + if (!(epsw & EPSW_FLAG_C)) + goto take_the_loop; + return; + case 0x7: /* MOV_LLS: C or Z */ + if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)) + goto take_the_loop; + return; + + case 0x8: /* MOV_LEQ: Z */ + if (epsw & EPSW_FLAG_Z) + goto take_the_loop; + return; + case 0x9: /* MOV_LNE: ~Z */ + if (!(epsw & EPSW_FLAG_Z)) + goto take_the_loop; + return; + case 0xa: /* MOV_LRA: always */ + goto take_the_loop; + + default: + BUG(); + } + +take_the_loop: + /* wind the PC back to just after the SETLB insn */ + kdebug("loop LAR=%lx", regs->lar); + regs->pc = regs->lar - 4; +} + +/* + * misalignment handler tests + */ +#ifdef CONFIG_TEST_MISALIGNMENT_HANDLER +static u8 __initdata testbuf[512] __attribute__((aligned(16))) = { + [257] = 0x11, + [258] = 0x22, + [259] = 0x33, + [260] = 0x44, +}; + +#define ASSERTCMP(X, OP, Y) \ +do { \ + if (unlikely(!((X) OP (Y)))) { \ + printk(KERN_ERR "\n"); \ + printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \ + __LINE__); \ + printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \ + (unsigned long)(X), (unsigned long)(Y)); \ + BUG(); \ + } \ +} while(0) + +static int __init test_misalignment(void) +{ + register void *r asm("e0"); + register u32 y asm("e1"); + void *p = testbuf, *q; + u32 tmp, tmp2, x; + + printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p); + p++; + + printk(KERN_NOTICE "___ MOV (Am),Dn ___\n"); + q = p + 256; + asm volatile("mov (%0),%1" : "+a"(q), "=d"(x)); + ASSERTCMP(q, ==, p + 256); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n"); + q = p; + asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x)); + ASSERTCMP(q, ==, p); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n"); + tmp = 256; + q = p; + asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp)); + ASSERTCMP(q, ==, p); + ASSERTCMP(x, ==, 0x44332211); + ASSERTCMP(tmp, ==, 256); + + printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n"); + r = p; + asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y)); + ASSERTCMP(r, ==, p); + ASSERTCMP(y, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n"); + r = p + 256; + asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y)); + ASSERTCMP(r, ==, p + 256 + 4); + ASSERTCMP(y, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n"); + r = p + 256; + asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y)); + ASSERTCMP(r, ==, p + 256 + 8); + ASSERTCMP(y, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n"); + asm volatile( + "add -16,sp \n" + "mov +0x11,%0 \n" + "movbu %0,(7,sp) \n" + "mov +0x22,%0 \n" + "movbu %0,(8,sp) \n" + "mov +0x33,%0 \n" + "movbu %0,(9,sp) \n" + "mov +0x44,%0 \n" + "movbu %0,(10,sp) \n" + "mov (7,sp),%1 \n" + "add +16,sp \n" + : "+a"(q), "=d"(x)); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n"); + asm volatile( + "add -264,sp \n" + "mov +0x11,%0 \n" + "movbu %0,(259,sp) \n" + "mov +0x22,%0 \n" + "movbu %0,(260,sp) \n" + "mov +0x33,%0 \n" + "movbu %0,(261,sp) \n" + "mov +0x55,%0 \n" + "movbu %0,(262,sp) \n" + "mov (259,sp),%1 \n" + "add +264,sp \n" + : "+d"(tmp), "=d"(x)); + ASSERTCMP(x, ==, 0x55332211); + + printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n"); + asm volatile( + "add -264,sp \n" + "mov +0x11,%0 \n" + "movbu %0,(260,sp) \n" + "mov +0x22,%0 \n" + "movbu %0,(261,sp) \n" + "mov +0x33,%0 \n" + "movbu %0,(262,sp) \n" + "mov +0x55,%0 \n" + "movbu %0,(263,sp) \n" + "mov (260,sp),%1 \n" + "add +264,sp \n" + : "+d"(tmp), "=d"(x)); + ASSERTCMP(x, ==, 0x55332211); + + + printk(KERN_NOTICE "___ MOV_LNE ___\n"); + tmp = 1; + tmp2 = 2; + q = p + 256; + asm volatile( + "setlb \n" + "mov %2,%3 \n" + "mov %1,%2 \n" + "cmp +0,%1 \n" + "mov_lne (%0+,4),%1" + : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x) + : + : "cc"); + ASSERTCMP(q, ==, p + 256 + 12); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "___ MOV in SETLB ___\n"); + tmp = 1; + tmp2 = 2; + q = p + 256; + asm volatile( + "setlb \n" + "mov %1,%3 \n" + "mov (%0+),%1 \n" + "cmp +0,%1 \n" + "lne " + : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x) + : + : "cc"); + + ASSERTCMP(q, ==, p + 256 + 8); + ASSERTCMP(x, ==, 0x44332211); + + printk(KERN_NOTICE "<==test_misalignment()\n"); + return 0; +} + +arch_initcall(test_misalignment); + +#endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */ diff --git a/arch/parisc/include/asm/parisc-device.h b/arch/parisc/include/asm/parisc-device.h index 7aa13f2add7a..9afdad6c2ffb 100644 --- a/arch/parisc/include/asm/parisc-device.h +++ b/arch/parisc/include/asm/parisc-device.h @@ -42,9 +42,9 @@ struct parisc_driver { #define to_parisc_driver(d) container_of(d, struct parisc_driver, drv) #define parisc_parent(d) to_parisc_device(d->dev.parent) -static inline char *parisc_pathname(struct parisc_device *d) +static inline const char *parisc_pathname(struct parisc_device *d) { - return d->dev.bus_id; + return dev_name(&d->dev); } static inline void diff --git a/arch/parisc/include/asm/posix_types.h b/arch/parisc/include/asm/posix_types.h index bb725a6630bb..00da29a340ba 100644 --- a/arch/parisc/include/asm/posix_types.h +++ b/arch/parisc/include/asm/posix_types.h @@ -24,13 +24,12 @@ typedef int __kernel_daddr_t; typedef unsigned long __kernel_size_t; typedef long __kernel_ssize_t; typedef long __kernel_ptrdiff_t; -typedef long __kernel_time_t; #else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; #endif +typedef long __kernel_time_t; typedef char * __kernel_caddr_t; typedef unsigned short __kernel_uid16_t; diff --git a/arch/parisc/include/asm/ptrace.h b/arch/parisc/include/asm/ptrace.h index afa5333187b4..302f68dc889c 100644 --- a/arch/parisc/include/asm/ptrace.h +++ b/arch/parisc/include/asm/ptrace.h @@ -47,8 +47,6 @@ struct pt_regs { #define task_regs(task) ((struct pt_regs *) ((char *)(task) + TASK_REGS)) -#define __ARCH_WANT_COMPAT_SYS_PTRACE - struct task_struct; #define arch_has_single_step() 1 void user_disable_single_step(struct task_struct *task); diff --git a/arch/parisc/include/asm/smp.h b/arch/parisc/include/asm/smp.h index 398cdbaf4e54..409e698f4361 100644 --- a/arch/parisc/include/asm/smp.h +++ b/arch/parisc/include/asm/smp.h @@ -44,8 +44,6 @@ extern void arch_send_call_function_ipi(cpumask_t mask); #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */ -extern unsigned long cpu_present_mask; - #define raw_smp_processor_id() (current_thread_info()->cpu) #else /* CONFIG_SMP */ diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c index 2ca654bd6322..884b7ce16a3b 100644 --- a/arch/parisc/kernel/drivers.c +++ b/arch/parisc/kernel/drivers.c @@ -43,7 +43,7 @@ struct hppa_dma_ops *hppa_dma_ops __read_mostly; EXPORT_SYMBOL(hppa_dma_ops); static struct device root = { - .bus_id = "parisc", + .init_name = "parisc", }; static inline int check_dev(struct device *dev) @@ -393,7 +393,8 @@ EXPORT_SYMBOL(print_pci_hwpath); static void setup_bus_id(struct parisc_device *padev) { struct hardware_path path; - char *output = padev->dev.bus_id; + char name[20]; + char *output = name; int i; get_node_path(padev->dev.parent, &path); @@ -404,6 +405,7 @@ static void setup_bus_id(struct parisc_device *padev) output += sprintf(output, "%u:", (unsigned char) path.bc[i]); } sprintf(output, "%u", (unsigned char) padev->hw_path); + dev_set_name(&padev->dev, name); } struct parisc_device * create_tree_node(char id, struct device *parent) diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c index 90904f9dfc50..927db3668b6f 100644 --- a/arch/parisc/kernel/ptrace.c +++ b/arch/parisc/kernel/ptrace.c @@ -183,10 +183,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) * being 64 bit in both cases. */ -static long translate_usr_offset(long offset) +static compat_ulong_t translate_usr_offset(compat_ulong_t offset) { if (offset < 0) - return -1; + return sizeof(struct pt_regs); else if (offset <= 32*4) /* gr[0..31] */ return offset * 2 + 4; else if (offset <= 32*4+32*8) /* gr[0..31] + fr[0..31] */ @@ -194,7 +194,7 @@ static long translate_usr_offset(long offset) else if (offset < sizeof(struct pt_regs)/2 + 32*4) return offset * 2 + 4 - 32*8; else - return -1; + return sizeof(struct pt_regs); } long compat_arch_ptrace(struct task_struct *child, compat_long_t request, @@ -209,7 +209,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, if (addr & (sizeof(compat_uint_t)-1)) break; addr = translate_usr_offset(addr); - if (addr < 0) + if (addr >= sizeof(struct pt_regs)) break; tmp = *(compat_uint_t *) ((char *) task_regs(child) + addr); @@ -236,7 +236,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, if (addr & (sizeof(compat_uint_t)-1)) break; addr = translate_usr_offset(addr); - if (addr < 0) + if (addr >= sizeof(struct pt_regs)) break; if (addr >= PT_FR0 && addr <= PT_FR31 + 4) { /* Special case, fp regs are 64 bits anyway */ diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c index 675f1d098f05..4c771cd580ec 100644 --- a/arch/parisc/kernel/traps.c +++ b/arch/parisc/kernel/traps.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include @@ -51,7 +50,7 @@ DEFINE_SPINLOCK(pa_dbit_lock); #endif -void parisc_show_stack(struct task_struct *t, unsigned long *sp, +static void parisc_show_stack(struct task_struct *task, unsigned long *sp, struct pt_regs *regs); static int printbinary(char *buf, unsigned long x, int nbits) @@ -121,18 +120,19 @@ static void print_fr(char *level, struct pt_regs *regs) void show_regs(struct pt_regs *regs) { - int i; + int i, user; char *level; unsigned long cr30, cr31; - level = user_mode(regs) ? KERN_DEBUG : KERN_CRIT; + user = user_mode(regs); + level = user ? KERN_DEBUG : KERN_CRIT; print_gr(level, regs); for (i = 0; i < 8; i += 4) PRINTREGS(level, regs->sr, "sr", RFMT, i); - if (user_mode(regs)) + if (user) print_fr(level, regs); cr30 = mfctl(30); @@ -145,14 +145,18 @@ void show_regs(struct pt_regs *regs) printk("%s CPU: %8d CR30: " RFMT " CR31: " RFMT "\n", level, current_thread_info()->cpu, cr30, cr31); printk("%s ORIG_R28: " RFMT "\n", level, regs->orig_r28); - printk(level); - print_symbol(" IAOQ[0]: %s\n", regs->iaoq[0]); - printk(level); - print_symbol(" IAOQ[1]: %s\n", regs->iaoq[1]); - printk(level); - print_symbol(" RP(r2): %s\n", regs->gr[2]); - - parisc_show_stack(current, NULL, regs); + + if (user) { + printk("%s IAOQ[0]: " RFMT "\n", level, regs->iaoq[0]); + printk("%s IAOQ[1]: " RFMT "\n", level, regs->iaoq[1]); + printk("%s RP(r2): " RFMT "\n", level, regs->gr[2]); + } else { + printk("%s IAOQ[0]: %pS\n", level, (void *) regs->iaoq[0]); + printk("%s IAOQ[1]: %pS\n", level, (void *) regs->iaoq[1]); + printk("%s RP(r2): %pS\n", level, (void *) regs->gr[2]); + + parisc_show_stack(current, NULL, regs); + } } @@ -173,20 +177,15 @@ static void do_show_stack(struct unwind_frame_info *info) break; if (__kernel_text_address(info->ip)) { - printk("%s [<" RFMT ">] ", (i&0x3)==1 ? KERN_CRIT : "", info->ip); -#ifdef CONFIG_KALLSYMS - print_symbol("%s\n", info->ip); -#else - if ((i & 0x03) == 0) - printk("\n"); -#endif + printk(KERN_CRIT " [<" RFMT ">] %pS\n", + info->ip, (void *) info->ip); i++; } } - printk("\n"); + printk(KERN_CRIT "\n"); } -void parisc_show_stack(struct task_struct *task, unsigned long *sp, +static void parisc_show_stack(struct task_struct *task, unsigned long *sp, struct pt_regs *regs) { struct unwind_frame_info info; diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 5b1527883fcb..525c13a4de93 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -108,8 +108,7 @@ config ARCH_NO_VIRT_TO_BUS config PPC bool default y - select HAVE_DYNAMIC_FTRACE - select HAVE_FTRACE + select HAVE_FUNCTION_TRACER select ARCH_WANT_OPTIONAL_GPIOLIB select HAVE_IDE select HAVE_IOREMAP_PROT diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 24dd1a37f8fb..1f0667069940 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -122,7 +122,7 @@ KBUILD_CFLAGS += -mcpu=powerpc endif # Work around a gcc code-gen bug with -fno-omit-frame-pointer. -ifeq ($(CONFIG_FTRACE),y) +ifeq ($(CONFIG_FUNCTION_TRACER),y) KBUILD_CFLAGS += -mno-sched-epilog endif diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 8fc6d72849ae..3d3daa674299 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -41,6 +41,7 @@ $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 +$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 diff --git a/arch/powerpc/boot/addnote.c b/arch/powerpc/boot/addnote.c index 3091d1d21aef..b1e5611b2ab1 100644 --- a/arch/powerpc/boot/addnote.c +++ b/arch/powerpc/boot/addnote.c @@ -11,12 +11,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * Usage: addnote [-r realbase] zImage [note.elf] - * - * If note.elf is supplied, it is the name of an ELF file that contains - * an RPA note to use instead of the built-in one. Alternatively, the - * note.elf file may be empty, in which case the built-in RPA note is - * used (this is to simplify how this is invoked from the wrapper script). + * Usage: addnote zImage */ #include #include @@ -48,29 +43,27 @@ char rpaname[] = "IBM,RPA-Client-Config"; */ #define N_RPA_DESCR 8 unsigned int rpanote[N_RPA_DESCR] = { - 1, /* lparaffinity */ - 128, /* min_rmo_size */ + 0, /* lparaffinity */ + 64, /* min_rmo_size */ 0, /* min_rmo_percent */ - 46, /* max_pft_size */ + 40, /* max_pft_size */ 1, /* splpar */ -1, /* min_load */ - 1, /* new_mem_def */ - 0, /* ignore_my_client_config */ + 0, /* new_mem_def */ + 1, /* ignore_my_client_config */ }; #define ROUNDUP(len) (((len) + 3) & ~3) unsigned char buf[512]; -unsigned char notebuf[512]; -#define GET_16BE(b, off) (((b)[off] << 8) + ((b)[(off)+1])) -#define GET_32BE(b, off) ((GET_16BE((b), (off)) << 16) + \ - GET_16BE((b), (off)+2)) +#define GET_16BE(off) ((buf[off] << 8) + (buf[(off)+1])) +#define GET_32BE(off) ((GET_16BE(off) << 16) + GET_16BE((off)+2)) -#define PUT_16BE(b, off, v) ((b)[off] = ((v) >> 8) & 0xff, \ - (b)[(off) + 1] = (v) & 0xff) -#define PUT_32BE(b, off, v) (PUT_16BE((b), (off), (v) >> 16), \ - PUT_16BE((b), (off) + 2, (v))) +#define PUT_16BE(off, v) (buf[off] = ((v) >> 8) & 0xff, \ + buf[(off) + 1] = (v) & 0xff) +#define PUT_32BE(off, v) (PUT_16BE((off), (v) >> 16), \ + PUT_16BE((off) + 2, (v))) /* Structure of an ELF file */ #define E_IDENT 0 /* ELF header */ @@ -95,95 +88,25 @@ unsigned char notebuf[512]; unsigned char elf_magic[4] = { 0x7f, 'E', 'L', 'F' }; -unsigned char *read_rpanote(const char *fname, int *nnp) -{ - int notefd, nr, i; - int ph, ps, np; - int note, notesize; - - notefd = open(fname, O_RDONLY); - if (notefd < 0) { - perror(fname); - exit(1); - } - nr = read(notefd, notebuf, sizeof(notebuf)); - if (nr < 0) { - perror("read note"); - exit(1); - } - if (nr == 0) /* empty file */ - return NULL; - if (nr < E_HSIZE || - memcmp(¬ebuf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0 || - notebuf[E_IDENT+EI_CLASS] != ELFCLASS32 || - notebuf[E_IDENT+EI_DATA] != ELFDATA2MSB) - goto notelf; - close(notefd); - - /* now look for the RPA-note */ - ph = GET_32BE(notebuf, E_PHOFF); - ps = GET_16BE(notebuf, E_PHENTSIZE); - np = GET_16BE(notebuf, E_PHNUM); - if (ph < E_HSIZE || ps < PH_HSIZE || np < 1) - goto notelf; - - for (i = 0; i < np; ++i, ph += ps) { - if (GET_32BE(notebuf, ph + PH_TYPE) != PT_NOTE) - continue; - note = GET_32BE(notebuf, ph + PH_OFFSET); - notesize = GET_32BE(notebuf, ph + PH_FILESZ); - if (notesize < 34 || note + notesize > nr) - continue; - if (GET_32BE(notebuf, note) != strlen(rpaname) + 1 || - GET_32BE(notebuf, note + 8) != 0x12759999 || - strcmp((char *)¬ebuf[note + 12], rpaname) != 0) - continue; - /* looks like an RPA note, return it */ - *nnp = notesize; - return ¬ebuf[note]; - } - /* no RPA note found */ - return NULL; - - notelf: - fprintf(stderr, "%s is not a big-endian 32-bit ELF image\n", fname); - exit(1); -} - int main(int ac, char **av) { - int fd, n, i, ai; + int fd, n, i; int ph, ps, np; int nnote, nnote2, ns; - unsigned char *rpap; - char *p, *endp; - - ai = 1; - if (ac >= ai + 2 && strcmp(av[ai], "-r") == 0) { - /* process -r realbase */ - p = av[ai + 1]; - descr[1] = strtol(p, &endp, 16); - if (endp == p || *endp != 0) { - fprintf(stderr, "Can't parse -r argument '%s' as hex\n", - p); - exit(1); - } - ai += 2; - } - if (ac != ai + 1 && ac != ai + 2) { - fprintf(stderr, "Usage: %s [-r realbase] elf-file [rpanote.elf]\n", av[0]); + + if (ac != 2) { + fprintf(stderr, "Usage: %s elf-file\n", av[0]); exit(1); } - fd = open(av[ai], O_RDWR); + fd = open(av[1], O_RDWR); if (fd < 0) { - perror(av[ai]); + perror(av[1]); exit(1); } nnote = 12 + ROUNDUP(strlen(arch) + 1) + sizeof(descr); nnote2 = 12 + ROUNDUP(strlen(rpaname) + 1) + sizeof(rpanote); - rpap = NULL; n = read(fd, buf, sizeof(buf)); if (n < 0) { @@ -197,25 +120,22 @@ main(int ac, char **av) if (buf[E_IDENT+EI_CLASS] != ELFCLASS32 || buf[E_IDENT+EI_DATA] != ELFDATA2MSB) { fprintf(stderr, "%s is not a big-endian 32-bit ELF image\n", - av[ai]); + av[1]); exit(1); } - if (ac == ai + 2) - rpap = read_rpanote(av[ai + 1], &nnote2); - - ph = GET_32BE(buf, E_PHOFF); - ps = GET_16BE(buf, E_PHENTSIZE); - np = GET_16BE(buf, E_PHNUM); + ph = GET_32BE(E_PHOFF); + ps = GET_16BE(E_PHENTSIZE); + np = GET_16BE(E_PHNUM); if (ph < E_HSIZE || ps < PH_HSIZE || np < 1) goto notelf; if (ph + (np + 2) * ps + nnote + nnote2 > n) goto nospace; for (i = 0; i < np; ++i) { - if (GET_32BE(buf, ph + PH_TYPE) == PT_NOTE) { + if (GET_32BE(ph + PH_TYPE) == PT_NOTE) { fprintf(stderr, "%s already has a note entry\n", - av[ai]); + av[1]); exit(0); } ph += ps; @@ -228,42 +148,37 @@ main(int ac, char **av) /* fill in the program header entry */ ns = ph + 2 * ps; - PUT_32BE(buf, ph + PH_TYPE, PT_NOTE); - PUT_32BE(buf, ph + PH_OFFSET, ns); - PUT_32BE(buf, ph + PH_FILESZ, nnote); + PUT_32BE(ph + PH_TYPE, PT_NOTE); + PUT_32BE(ph + PH_OFFSET, ns); + PUT_32BE(ph + PH_FILESZ, nnote); /* fill in the note area we point to */ /* XXX we should probably make this a proper section */ - PUT_32BE(buf, ns, strlen(arch) + 1); - PUT_32BE(buf, ns + 4, N_DESCR * 4); - PUT_32BE(buf, ns + 8, 0x1275); + PUT_32BE(ns, strlen(arch) + 1); + PUT_32BE(ns + 4, N_DESCR * 4); + PUT_32BE(ns + 8, 0x1275); strcpy((char *) &buf[ns + 12], arch); ns += 12 + strlen(arch) + 1; for (i = 0; i < N_DESCR; ++i, ns += 4) - PUT_32BE(buf, ns, descr[i]); + PUT_32BE(ns, descr[i]); /* fill in the second program header entry and the RPA note area */ ph += ps; - PUT_32BE(buf, ph + PH_TYPE, PT_NOTE); - PUT_32BE(buf, ph + PH_OFFSET, ns); - PUT_32BE(buf, ph + PH_FILESZ, nnote2); + PUT_32BE(ph + PH_TYPE, PT_NOTE); + PUT_32BE(ph + PH_OFFSET, ns); + PUT_32BE(ph + PH_FILESZ, nnote2); /* fill in the note area we point to */ - if (rpap) { - /* RPA note supplied in file, just copy the whole thing over */ - memcpy(buf + ns, rpap, nnote2); - } else { - PUT_32BE(buf, ns, strlen(rpaname) + 1); - PUT_32BE(buf, ns + 4, sizeof(rpanote)); - PUT_32BE(buf, ns + 8, 0x12759999); - strcpy((char *) &buf[ns + 12], rpaname); - ns += 12 + ROUNDUP(strlen(rpaname) + 1); - for (i = 0; i < N_RPA_DESCR; ++i, ns += 4) - PUT_32BE(buf, ns, rpanote[i]); - } + PUT_32BE(ns, strlen(rpaname) + 1); + PUT_32BE(ns + 4, sizeof(rpanote)); + PUT_32BE(ns + 8, 0x12759999); + strcpy((char *) &buf[ns + 12], rpaname); + ns += 12 + ROUNDUP(strlen(rpaname) + 1); + for (i = 0; i < N_RPA_DESCR; ++i, ns += 4) + PUT_32BE(ns, rpanote[i]); /* Update the number of program headers */ - PUT_16BE(buf, E_PHNUM, np + 2); + PUT_16BE(E_PHNUM, np + 2); /* write back */ lseek(fd, (long) 0, SEEK_SET); @@ -273,18 +188,18 @@ main(int ac, char **av) exit(1); } if (i < n) { - fprintf(stderr, "%s: write truncated\n", av[ai]); + fprintf(stderr, "%s: write truncated\n", av[1]); exit(1); } exit(0); notelf: - fprintf(stderr, "%s does not appear to be an ELF file\n", av[ai]); + fprintf(stderr, "%s does not appear to be an ELF file\n", av[1]); exit(1); nospace: fprintf(stderr, "sorry, I can't find space in %s to put the note\n", - av[ai]); + av[1]); exit(1); } diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 6ed608322ddc..e48cfa740c8a 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -108,7 +108,7 @@ compatible = "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M - bus-frequency = <0>; + bus-frequency = <33333333>; i2c1: i2c@3000 { #address-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index 747f27676332..503031766825 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -164,45 +164,6 @@ mode = "cpu"; }; - dma@82a8 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; - reg = <0x82a8 4>; - ranges = <0 0x8100 0x1a8>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; - reg = <0 0x80>; - cell-index = <0>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@80 { - compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@100 { - compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@180 { - compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel"; - reg = <0x180 0x28>; - cell-index = <3>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - }; - /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ usb@23000 { compatible = "fsl-usb2-dr"; diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 226ff066652b..dea30910c136 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -18,8 +18,8 @@ #size-cells = <1>; aliases { - ethernet0 = &enet0; - ethernet1 = &enet1; + ethernet0 = &enet1; + ethernet1 = &enet0; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index 2c9d54a35bc3..4bdbaf4993a1 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -91,6 +91,14 @@ interrupts = <18 0x8>; interrupt-parent = <&ipic>; }; + + mcu_pio: mcu@a { + #gpio-cells = <2>; + compatible = "fsl,mc9s08qg8-mpc8349emitx", + "fsl,mcu-mpc8349emitx"; + reg = <0x0a>; + gpio-controller; + }; }; spi@7000 { @@ -139,14 +147,6 @@ interrupt-parent = <&ipic>; interrupts = <71 8>; }; - - mcu_pio: mcu@a { - #gpio-cells = <2>; - compatible = "fsl,mc9s08qg8-mpc8349emitx", - "fsl,mcu-mpc8349emitx"; - reg = <0x0a>; - gpio-controller; - }; }; usb@22000 { diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index cadd4652a695..5c69b2fafd32 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -90,7 +90,7 @@ compatible = "fsl,mpc8572-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes - cache-size = <0x80000>; // L2, 512K + cache-size = <0x100000>; // L2, 1M interrupt-parent = <&mpic>; interrupts = <16 2>; }; diff --git a/arch/powerpc/boot/libfdt/fdt_ro.c b/arch/powerpc/boot/libfdt/fdt_ro.c index 129b532bcc1a..fbbba44fcd0d 100644 --- a/arch/powerpc/boot/libfdt/fdt_ro.c +++ b/arch/powerpc/boot/libfdt/fdt_ro.c @@ -104,8 +104,8 @@ int fdt_subnode_offset_namelen(const void *fdt, int offset, FDT_CHECK_HEADER(fdt); - for (depth = 0; - offset >= 0; + for (depth = 0, offset = fdt_next_node(fdt, offset, &depth); + (offset >= 0) && (depth > 0); offset = fdt_next_node(fdt, offset, &depth)) { if (depth < 0) return -FDT_ERR_NOTFOUND; @@ -114,7 +114,10 @@ int fdt_subnode_offset_namelen(const void *fdt, int offset, return offset; } - return offset; /* error */ + if (offset < 0) + return offset; /* error */ + else + return -FDT_ERR_NOTFOUND; } int fdt_subnode_offset(const void *fdt, int parentoffset, diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c index ae32801ebd69..a28f02165e97 100644 --- a/arch/powerpc/boot/main.c +++ b/arch/powerpc/boot/main.c @@ -63,7 +63,7 @@ static struct addr_range prep_kernel(void) */ if ((unsigned long)_start < ei.loadsize) fatal("Insufficient memory for kernel at address 0!" - " (_start=%p, uncomressed size=%08x)\n\r", + " (_start=%p, uncompressed size=%08lx)\n\r", _start, ei.loadsize); if ((unsigned long)_end < ei.memsize) diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index f39073511a49..965c237c122d 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -306,13 +306,8 @@ fi # post-processing needed for some platforms case "$platform" in -pseries) - ${CROSS}objcopy -O binary -j .fakeelf "$kernel" "$ofile".rpanote - $objbin/addnote "$ofile" "$ofile".rpanote - rm -r "$ofile".rpanote - ;; -chrp) - $objbin/addnote -r c00000 "$ofile" +pseries|chrp) + $objbin/addnote "$ofile" ;; coff) ${CROSS}objcopy -O aixcoff-rs6000 --set-start "$entry" "$ofile" diff --git a/arch/powerpc/configs/40x/acadia_defconfig b/arch/powerpc/configs/40x/acadia_defconfig index 39bd9eb453f0..25572cc837ca 100644 --- a/arch/powerpc/configs/40x/acadia_defconfig +++ b/arch/powerpc/configs/40x/acadia_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc5 -# Mon Oct 13 13:47:16 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 08:49:18 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -103,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -117,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -153,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -161,8 +160,10 @@ CONFIG_CLASSIC_RCU=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set CONFIG_ACADIA=y # CONFIG_EP405 is not set +# CONFIG_HCU4 is not set # CONFIG_KILAUEA is not set # CONFIG_MAKALU is not set # CONFIG_WALNUT is not set @@ -186,7 +187,6 @@ CONFIG_405EZ=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -200,6 +200,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -214,15 +216,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -309,6 +311,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -329,14 +332,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -516,6 +513,7 @@ CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT=y CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR=y # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -613,6 +611,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -646,6 +645,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -655,6 +655,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -663,10 +664,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -696,6 +698,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -733,6 +736,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -753,7 +757,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -806,15 +809,21 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -835,14 +844,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -915,6 +929,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/40x/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig index 2113ae2ab401..b80ba7aa3129 100644 --- a/arch/powerpc/configs/40x/ep405_defconfig +++ b/arch/powerpc/configs/40x/ep405_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 19:34:03 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 08:49:20 2008 # # CONFIG_PPC64 is not set @@ -19,14 +19,13 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -88,7 +87,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -105,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -155,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -163,11 +160,15 @@ CONFIG_CLASSIC_RCU=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_ACADIA is not set CONFIG_EP405=y +# CONFIG_HCU4 is not set # CONFIG_KILAUEA is not set # CONFIG_MAKALU is not set # CONFIG_WALNUT is not set # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set +# CONFIG_PPC40x_SIMPLE is not set CONFIG_405GP=y CONFIG_IBM405_ERR77=y CONFIG_IBM405_ERR51=y @@ -188,7 +189,6 @@ CONFIG_IBM405_ERR51=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -202,6 +202,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -216,15 +218,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -311,6 +313,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -331,14 +334,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -520,8 +517,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -542,18 +543,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -658,6 +663,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -707,6 +714,9 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -726,6 +736,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -733,6 +745,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -747,7 +760,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # USB Imaging devices # # CONFIG_USB_MDC800 is not set -CONFIG_USB_MON=y # # USB port drivers @@ -760,7 +772,7 @@ CONFIG_USB_MON=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -777,7 +789,9 @@ CONFIG_USB_MON=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -787,6 +801,7 @@ CONFIG_USB_MON=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -795,10 +810,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -828,6 +844,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -865,6 +882,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -885,7 +903,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -938,14 +955,21 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -954,6 +978,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -965,14 +990,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1045,6 +1075,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/40x/hcu4_defconfig b/arch/powerpc/configs/40x/hcu4_defconfig index 682fce02c73a..45dcb824503f 100644 --- a/arch/powerpc/configs/40x/hcu4_defconfig +++ b/arch/powerpc/configs/40x/hcu4_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26.5 -# Tue Sep 16 00:44:33 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 08:49:22 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -29,6 +29,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -86,13 +87,11 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_HOTPLUG=y CONFIG_PRINTK=y -# CONFIG_LOGBUFFER is not set CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_COMPAT_BRK=y @@ -104,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -113,10 +114,12 @@ CONFIG_SLUB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -133,6 +136,7 @@ CONFIG_LBD=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -147,22 +151,25 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # # Platform support # -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_ACADIA is not set # CONFIG_EP405 is not set CONFIG_HCU4=y # CONFIG_KILAUEA is not set # CONFIG_MAKALU is not set # CONFIG_WALNUT is not set # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set +# CONFIG_PPC40x_SIMPLE is not set +CONFIG_405GPR=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set @@ -180,7 +187,6 @@ CONFIG_HCU4=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -194,6 +200,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -208,17 +216,19 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" # CONFIG_PM is not set CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -229,6 +239,7 @@ CONFIG_ISA_DMA_API=y CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y @@ -256,10 +267,6 @@ CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 CONFIG_CONSISTENT_START=0xff100000 CONFIG_CONSISTENT_SIZE=0x00200000 - -# -# Networking -# CONFIG_NET=y # @@ -304,6 +311,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -324,14 +332,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -346,6 +348,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -449,12 +453,14 @@ CONFIG_BLK_DEV_RAM_SIZE=35000 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -481,7 +487,6 @@ CONFIG_HAVE_IDE=y # CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -509,14 +514,17 @@ CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0 # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set # CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_NS83820 is not set @@ -531,18 +539,23 @@ CONFIG_NETDEV_1000=y # CONFIG_BNX2 is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -618,6 +631,8 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_DEVPORT=y # CONFIG_I2C is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set @@ -634,8 +649,11 @@ CONFIG_SSB_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -667,12 +685,9 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -682,6 +697,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -690,10 +706,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -723,6 +740,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -739,11 +757,11 @@ CONFIG_TMPFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_YAFFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -754,13 +772,13 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -781,9 +799,9 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -809,6 +827,8 @@ CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -826,17 +846,36 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set # CONFIG_BDI_SWITCH is not set @@ -847,14 +886,19 @@ CONFIG_DEBUG_BUGVERBOSE=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -893,6 +937,10 @@ CONFIG_CRYPTO_PCBC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -923,6 +971,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig index 565ed9666c54..e2f3695d9d0b 100644 --- a/arch/powerpc/configs/40x/kilauea_defconfig +++ b/arch/powerpc/configs/40x/kilauea_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 19:36:14 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 08:49:23 2008 # # CONFIG_PPC64 is not set @@ -19,14 +19,13 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -88,7 +87,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -105,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -155,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -163,11 +160,15 @@ CONFIG_PPC4xx_PCI_EXPRESS=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_ACADIA is not set # CONFIG_EP405 is not set +# CONFIG_HCU4 is not set CONFIG_KILAUEA=y # CONFIG_MAKALU is not set # CONFIG_WALNUT is not set # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set +# CONFIG_PPC40x_SIMPLE is not set CONFIG_405EX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -186,7 +187,6 @@ CONFIG_405EX=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -200,6 +200,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -214,15 +216,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -309,6 +311,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -329,14 +332,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -511,8 +508,12 @@ CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0 CONFIG_IBM_NEW_EMAC_RGMII=y # CONFIG_IBM_NEW_EMAC_TAH is not set CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -609,6 +610,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -642,6 +645,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -651,6 +655,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -659,10 +664,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -692,6 +698,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -729,6 +736,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -749,7 +757,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -802,14 +809,21 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -818,6 +832,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -829,14 +844,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -909,6 +929,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/40x/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig index 987a4481800f..413c778ecd7c 100644 --- a/arch/powerpc/configs/40x/makalu_defconfig +++ b/arch/powerpc/configs/40x/makalu_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 19:38:39 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 08:49:25 2008 # # CONFIG_PPC64 is not set @@ -19,14 +19,13 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -88,7 +87,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -105,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -155,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -163,11 +160,15 @@ CONFIG_PPC4xx_PCI_EXPRESS=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_ACADIA is not set # CONFIG_EP405 is not set +# CONFIG_HCU4 is not set # CONFIG_KILAUEA is not set CONFIG_MAKALU=y # CONFIG_WALNUT is not set # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set +# CONFIG_PPC40x_SIMPLE is not set CONFIG_405EX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -186,7 +187,6 @@ CONFIG_405EX=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -200,6 +200,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -214,15 +216,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -309,6 +311,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -329,14 +332,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -511,8 +508,12 @@ CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0 CONFIG_IBM_NEW_EMAC_RGMII=y # CONFIG_IBM_NEW_EMAC_TAH is not set CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -609,6 +610,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -642,6 +645,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -651,6 +655,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -659,10 +664,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -692,6 +698,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -729,6 +736,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -749,7 +757,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -802,14 +809,21 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -818,6 +832,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -829,14 +844,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -909,6 +929,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig new file mode 100644 index 000000000000..9a9350ded292 --- /dev/null +++ b/arch/powerpc/configs/40x/virtex_defconfig @@ -0,0 +1,1176 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28-rc4 +# Fri Nov 14 10:49:16 2008 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +CONFIG_40x=y +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_4xx=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set +# CONFIG_PPC4xx_PCI_EXPRESS is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_XILINX_VIRTEX=y +# CONFIG_ACADIA is not set +# CONFIG_EP405 is not set +# CONFIG_HCU4 is not set +# CONFIG_KILAUEA is not set +# CONFIG_MAKALU is not set +# CONFIG_WALNUT is not set +CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y +# CONFIG_PPC40x_SIMPLE is not set +CONFIG_XILINX_VIRTEX_II_PRO=y +CONFIG_XILINX_VIRTEX_4_FX=y +CONFIG_IBM405_ERR77=y +CONFIG_IBM405_ERR51=y +# CONFIG_IPIC is not set +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_RESOURCES_64BIT=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="" +CONFIG_EXTRA_TARGETS="" +# CONFIG_PM is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=m +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_XILINX_SYSACE=y +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# Enable only one of the two stacks, unless you know what you are doing +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +CONFIG_SERIO_XILINX_XPS_PS2=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +CONFIG_XILINX_HWICAP=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_XILINX=y + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_CT65550 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_XILINX=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set +# CONFIG_IRQSTACKS is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/40x/walnut_defconfig b/arch/powerpc/configs/40x/walnut_defconfig index aee79338f41f..5820e0a4fc55 100644 --- a/arch/powerpc/configs/40x/walnut_defconfig +++ b/arch/powerpc/configs/40x/walnut_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 19:40:56 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 08:49:27 2008 # # CONFIG_PPC64 is not set @@ -19,14 +19,13 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -88,7 +87,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -105,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -155,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -163,11 +160,15 @@ CONFIG_CLASSIC_RCU=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_ACADIA is not set # CONFIG_EP405 is not set +# CONFIG_HCU4 is not set # CONFIG_KILAUEA is not set # CONFIG_MAKALU is not set CONFIG_WALNUT=y # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set +# CONFIG_PPC40x_SIMPLE is not set CONFIG_405GP=y CONFIG_IBM405_ERR77=y CONFIG_IBM405_ERR51=y @@ -189,7 +190,6 @@ CONFIG_OF_RTC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -203,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -217,15 +219,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -312,6 +314,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -332,14 +335,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -520,8 +517,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -542,18 +543,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -649,6 +654,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -689,10 +696,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -702,6 +714,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -710,10 +723,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -743,6 +757,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -780,6 +795,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -800,7 +816,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -853,14 +868,21 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -869,6 +891,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -880,14 +903,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -960,6 +988,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig index 70f46078eb6a..082158d591c5 100644 --- a/arch/powerpc/configs/44x/arches_defconfig +++ b/arch/powerpc/configs/44x/arches_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc5 -# Wed Oct 1 15:54:57 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:04 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -103,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -117,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -153,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -175,6 +174,7 @@ CONFIG_ARCHES=y # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_460EX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -207,6 +207,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -221,15 +223,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -316,6 +318,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -336,14 +339,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -440,8 +437,12 @@ CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0 # CONFIG_IBM_NEW_EMAC_RGMII is not set CONFIG_IBM_NEW_EMAC_TAH=y CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -540,6 +541,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -573,6 +575,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -582,6 +585,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -590,10 +594,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -623,6 +628,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -659,6 +665,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -679,7 +686,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -732,15 +738,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -761,6 +773,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/bamboo_defconfig b/arch/powerpc/configs/44x/bamboo_defconfig index e920693535af..f47c2f3420f6 100644 --- a/arch/powerpc/configs/44x/bamboo_defconfig +++ b/arch/powerpc/configs/44x/bamboo_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 08:43:44 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:06 2008 # # CONFIG_PPC64 is not set @@ -23,14 +23,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -92,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -109,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +123,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -159,6 +155,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -175,9 +172,13 @@ CONFIG_BAMBOO=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_440EP=y CONFIG_IBM440EP_ERR42=y # CONFIG_IPIC is not set @@ -197,7 +198,6 @@ CONFIG_IBM440EP_ERR42=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -211,6 +211,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -225,15 +227,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -320,6 +322,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -340,14 +343,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -450,8 +447,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -472,18 +473,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -579,6 +584,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -619,10 +626,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -632,6 +644,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -640,10 +653,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -673,6 +687,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -709,6 +724,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -729,7 +745,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -782,14 +797,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -798,6 +820,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -809,14 +832,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -889,6 +917,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig index 74da5c7754a4..0694756ac759 100644 --- a/arch/powerpc/configs/44x/canyonlands_defconfig +++ b/arch/powerpc/configs/44x/canyonlands_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 08:46:14 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:08 2008 # # CONFIG_PPC64 is not set @@ -23,14 +23,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -88,7 +87,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -105,7 +103,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -155,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -171,9 +168,13 @@ CONFIG_PPC4xx_PCI_EXPRESS=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set CONFIG_CANYONLANDS=y +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_460EX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -201,11 +202,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -220,15 +223,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -315,6 +318,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -335,14 +339,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -439,8 +437,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y CONFIG_IBM_NEW_EMAC_RGMII=y CONFIG_IBM_NEW_EMAC_TAH=y CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -538,6 +540,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -571,6 +575,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -580,6 +585,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -588,10 +594,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -621,6 +628,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -657,6 +665,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -677,7 +686,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -730,14 +738,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -746,6 +761,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -757,6 +773,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig index 17615750b494..c9937578ef7f 100644 --- a/arch/powerpc/configs/44x/ebony_defconfig +++ b/arch/powerpc/configs/44x/ebony_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:04:12 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:09 2008 # # CONFIG_PPC64 is not set @@ -22,14 +22,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -91,7 +90,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -108,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +122,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +154,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -174,9 +171,13 @@ CONFIG_EBONY=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set CONFIG_440GP=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -196,7 +197,6 @@ CONFIG_OF_RTC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -210,6 +210,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -224,15 +226,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -318,6 +320,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,14 +341,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -525,8 +522,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -547,18 +548,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -654,6 +659,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -694,10 +701,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -707,6 +719,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -715,10 +728,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -748,6 +762,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -795,6 +810,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -815,7 +831,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -869,14 +884,21 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -885,6 +907,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -896,14 +919,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -976,6 +1004,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig index 7bc4082a1c93..e326ee8bd195 100644 --- a/arch/powerpc/configs/44x/katmai_defconfig +++ b/arch/powerpc/configs/44x/katmai_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:06:51 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:11 2008 # # CONFIG_PPC64 is not set @@ -22,14 +22,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -87,7 +86,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -104,7 +102,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -118,10 +118,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -154,6 +150,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -170,9 +167,13 @@ CONFIG_PPC4xx_PCI_EXPRESS=y CONFIG_KATMAI=y # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_440SPe=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -191,7 +192,6 @@ CONFIG_440SPe=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -205,6 +205,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -219,15 +221,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -314,6 +316,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -334,14 +337,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -446,8 +443,12 @@ CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0 # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -468,18 +469,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -576,6 +581,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -616,10 +623,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -629,6 +641,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -637,10 +650,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -670,6 +684,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -706,6 +721,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -726,7 +742,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -779,14 +794,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -795,6 +817,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -805,14 +828,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -885,6 +913,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig index 0479648a9141..927f829e2087 100644 --- a/arch/powerpc/configs/44x/rainier_defconfig +++ b/arch/powerpc/configs/44x/rainier_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:09:35 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:13 2008 # # CONFIG_PPC64 is not set @@ -22,14 +22,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -91,7 +90,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -108,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +122,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +154,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -174,9 +171,13 @@ CONFIG_CLASSIC_RCU=y # CONFIG_KATMAI is not set CONFIG_RAINIER=y # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_440GRX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -195,7 +196,6 @@ CONFIG_440GRX=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -209,6 +209,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -223,15 +225,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -318,6 +320,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,14 +341,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -532,18 +529,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -639,6 +640,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -679,10 +682,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -692,6 +700,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -700,10 +709,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -733,6 +743,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -780,6 +791,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -800,7 +812,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -854,14 +865,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -870,6 +888,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -894,14 +913,19 @@ CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x1 # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -974,6 +998,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/sam440ep_defconfig b/arch/powerpc/configs/44x/sam440ep_defconfig index 0ed2de05f4e8..15f48e03ec2e 100644 --- a/arch/powerpc/configs/44x/sam440ep_defconfig +++ b/arch/powerpc/configs/44x/sam440ep_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:12:48 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:15 2008 # # CONFIG_PPC64 is not set @@ -23,14 +23,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -93,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y @@ -109,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +123,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -159,6 +155,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -175,9 +172,13 @@ CONFIG_SAM440EP=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set CONFIG_440EP=y CONFIG_IBM440EP_ERR42=y # CONFIG_IPIC is not set @@ -197,7 +198,6 @@ CONFIG_IBM440EP_ERR42=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -211,6 +211,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -225,15 +227,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -319,6 +321,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -339,14 +342,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -536,8 +533,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -573,7 +574,7 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -607,6 +608,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -673,6 +675,7 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y # @@ -761,6 +764,9 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set # # Multimedia devices @@ -788,6 +794,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -828,6 +835,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -839,6 +847,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_CARMINE is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_ILI9320 is not set @@ -875,9 +884,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -895,6 +931,9 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -917,6 +956,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -924,6 +965,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -953,7 +995,6 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -966,7 +1007,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -984,7 +1025,9 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1031,12 +1074,15 @@ CONFIG_RTC_DRV_M41T80_WDT=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1045,6 +1091,7 @@ CONFIG_RTC_DRV_M41T80_WDT=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1058,7 +1105,7 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y @@ -1067,6 +1114,7 @@ CONFIG_REISERFS_FS=y # CONFIG_REISERFS_FS_XATTR is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1102,6 +1150,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1196,7 +1245,6 @@ CONFIG_NLS_ISO8859_1=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1227,12 +1275,13 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1243,6 +1292,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig index e40b1023265c..562beeaab53d 100644 --- a/arch/powerpc/configs/44x/sequoia_defconfig +++ b/arch/powerpc/configs/44x/sequoia_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:15:13 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:16 2008 # # CONFIG_PPC64 is not set @@ -23,14 +23,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -92,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -109,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +123,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -159,6 +155,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -175,9 +172,13 @@ CONFIG_SEQUOIA=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_440EPX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -205,11 +206,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -224,15 +227,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -319,6 +322,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -339,14 +343,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -527,8 +525,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y CONFIG_IBM_NEW_EMAC_RGMII=y # CONFIG_IBM_NEW_EMAC_TAH is not set CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -549,18 +551,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -656,6 +662,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -696,10 +704,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -709,6 +722,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -717,10 +731,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -750,6 +765,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -797,6 +813,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -817,7 +834,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -871,14 +887,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -887,6 +910,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -911,14 +935,19 @@ CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x1 # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -991,6 +1020,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig index 5075873bdb1b..427bb6a11be5 100644 --- a/arch/powerpc/configs/44x/taishan_defconfig +++ b/arch/powerpc/configs/44x/taishan_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:17:48 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:18 2008 # # CONFIG_PPC64 is not set @@ -22,14 +22,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -91,7 +90,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -108,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +122,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +154,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -174,9 +171,13 @@ CONFIG_TAISHAN=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set CONFIG_440GX=y # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -195,7 +196,6 @@ CONFIG_440GX=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -209,6 +209,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -223,15 +225,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -318,6 +320,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,14 +341,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -528,8 +525,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y CONFIG_IBM_NEW_EMAC_RGMII=y CONFIG_IBM_NEW_EMAC_TAH=y CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -550,18 +551,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -657,6 +662,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -697,10 +704,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -710,6 +722,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -718,10 +731,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -751,6 +765,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -788,6 +803,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -808,7 +824,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -861,14 +876,21 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -877,6 +899,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -888,14 +911,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -968,6 +996,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig index 663ec512b33b..7513d360e0b0 100644 --- a/arch/powerpc/configs/44x/virtex5_defconfig +++ b/arch/powerpc/configs/44x/virtex5_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:20:16 2008 +# Linux kernel version: 2.6.28-rc4 +# Fri Nov 14 10:31:16 2008 # # CONFIG_PPC64 is not set @@ -22,14 +22,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -40,6 +39,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y # CONFIG_ARCH_NO_VIRT_TO_BUS is not set CONFIG_PPC=y CONFIG_EARLY_PRINTK=y @@ -93,8 +93,8 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y @@ -109,7 +109,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -122,10 +124,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +156,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # CONFIG_PPC4xx_PCI_EXPRESS is not set # @@ -174,9 +173,13 @@ CONFIG_CLASSIC_RCU=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set # CONFIG_WARP is not set +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set CONFIG_XILINX_VIRTEX=y CONFIG_XILINX_VIRTEX_5_FXT=y # CONFIG_IPIC is not set @@ -196,7 +199,6 @@ CONFIG_XILINX_VIRTEX_5_FXT=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -211,6 +213,8 @@ CONFIG_HZ=250 CONFIG_PREEMPT=y # CONFIG_PREEMPT_RCU is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -225,15 +229,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -256,6 +260,7 @@ CONFIG_PCI_SYSCALL=y CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -317,7 +322,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -352,8 +356,8 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set @@ -361,36 +365,38 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set # CONFIG_NETFILTER_XT_MATCH_MAC is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=m -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set # CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set # CONFIG_IP_NF_MATCH_TTL is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set CONFIG_IP_NF_FILTER=m # CONFIG_IP_NF_TARGET_REJECT is not set # CONFIG_IP_NF_TARGET_LOG is not set @@ -411,6 +417,7 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -431,11 +438,10 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -455,11 +461,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set # CONFIG_MTD is not set CONFIG_OF_DEVICE=y -CONFIG_OF_I2C=y +CONFIG_OF_GPIO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set @@ -478,7 +486,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_XILINX_SYSACE is not set +CONFIG_XILINX_SYSACE=y # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set @@ -487,6 +495,7 @@ CONFIG_MISC_DEVICES=y # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -534,8 +543,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -556,6 +569,7 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -604,6 +618,7 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -611,9 +626,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -624,11 +641,11 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_SERPORT is not set # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_XILINX_XPS_PS2 is not set +CONFIG_SERIO_XILINX_XPS_PS2=y # CONFIG_GAMEPORT is not set # @@ -656,11 +673,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # # Non-8250 serial port support # -# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set -CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -674,87 +692,41 @@ CONFIG_XILINX_HWICAP=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y # -# I2C system bus drivers (mostly embedded / system-on-chip) +# Memory mapped GPIO expanders: # -# CONFIG_I2C_IBM_IIC is not set -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set +CONFIG_GPIO_XILINX=y # -# External I2C/SMBus adapter drivers +# I2C GPIO expanders: # -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set # -# Graphics adapter I2C/DDC channel drivers +# PCI GPIO expanders: # -# CONFIG_I2C_VOODOO3 is not set +# CONFIG_GPIO_BT8XX is not set # -# Other I2C/SMBus bus drivers +# SPI GPIO expanders: # -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_AT24 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -CONFIG_I2C_DEBUG_CORE=y -CONFIG_I2C_DEBUG_ALGO=y -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -763,6 +735,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -790,6 +764,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -826,6 +801,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -838,6 +814,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_IBM_GXT4500 is not set CONFIG_FB_XILINX=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -870,6 +848,7 @@ CONFIG_LOGO_LINUX_CLUT224=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -879,6 +858,8 @@ CONFIG_LOGO_LINUX_CLUT224=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -887,10 +868,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -899,7 +881,7 @@ CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m +# CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems @@ -923,6 +905,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -954,19 +937,15 @@ CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=y -# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1023,7 +1002,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1041,7 +1019,7 @@ CONFIG_HAVE_LMB=y # # Kernel hacking # -# CONFIG_PRINTK_TIME is not set +CONFIG_PRINTK_TIME=y CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 @@ -1049,19 +1027,62 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set +# CONFIG_BDI_SWITCH is not set # CONFIG_PPC_EARLY_DEBUG is not set # @@ -1069,12 +1090,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1147,6 +1170,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/44x/warp_defconfig b/arch/powerpc/configs/44x/warp_defconfig index d9375a969c67..59cbd2761ed7 100644 --- a/arch/powerpc/configs/44x/warp_defconfig +++ b/arch/powerpc/configs/44x/warp_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 09:23:39 2008 +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 09:16:22 2008 # # CONFIG_PPC64 is not set @@ -23,14 +23,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -92,7 +91,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -109,6 +107,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -122,10 +121,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +153,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -173,9 +169,13 @@ CONFIG_CLASSIC_RCU=y # CONFIG_KATMAI is not set # CONFIG_RAINIER is not set CONFIG_WARP=y +# CONFIG_ARCHES is not set # CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set # CONFIG_YOSEMITE is not set # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set CONFIG_440EP=y CONFIG_IBM440EP_ERR42=y # CONFIG_IPIC is not set @@ -195,7 +195,6 @@ CONFIG_IBM440EP_ERR42=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -209,6 +208,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -223,15 +224,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -308,7 +309,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -322,10 +322,12 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -334,6 +336,7 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set @@ -355,14 +358,8 @@ CONFIG_VLAN_8021Q=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -550,6 +547,9 @@ CONFIG_IBM_NEW_EMAC_ZMII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -629,6 +629,7 @@ CONFIG_HW_RANDOM=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support @@ -678,6 +679,7 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -742,6 +744,9 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set # # Multimedia devices @@ -789,6 +794,9 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -805,6 +813,7 @@ CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -812,6 +821,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -840,7 +850,6 @@ CONFIG_USB_STORAGE=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -CONFIG_USB_MON=y # # USB port drivers @@ -853,7 +862,7 @@ CONFIG_USB_MON=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -869,13 +878,14 @@ CONFIG_USB_MON=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set CONFIG_MMC=m # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK_BOUNCE=y @@ -883,7 +893,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_WBSD is not set @@ -894,6 +904,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -902,10 +913,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -938,6 +950,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set @@ -984,6 +997,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1043,7 +1057,6 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1096,14 +1109,21 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y CONFIG_HAVE_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE=y # CONFIG_FTRACE is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1112,6 +1132,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -1123,12 +1144,14 @@ CONFIG_BDI_SWITCH=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1201,6 +1224,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/52xx/cm5200_defconfig b/arch/powerpc/configs/52xx/cm5200_defconfig index c10f7395aa1b..3df627494b65 100644 --- a/arch/powerpc/configs/52xx/cm5200_defconfig +++ b/arch/powerpc/configs/52xx/cm5200_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Tue Apr 29 07:11:37 2008 +# Linux kernel version: 2.6.28-rc4 +# Thu Nov 13 02:12:40 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -102,6 +103,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -110,9 +112,13 @@ CONFIG_SLUB=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -123,6 +129,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -137,19 +144,16 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support # CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set CONFIG_PPC_MPC52xx=y CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_EFIKA is not set @@ -159,7 +163,10 @@ CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -183,7 +190,6 @@ CONFIG_PPC_BESTCOMM_FEC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -197,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -211,19 +219,20 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -233,7 +242,7 @@ CONFIG_ISA_DMA_API=y # CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y -CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y # CONFIG_PCI is not set # CONFIG_PCI_DOMAINS is not set # CONFIG_PCI_SYSCALL is not set @@ -254,10 +263,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -308,6 +313,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -328,14 +334,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -446,6 +446,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -487,11 +488,11 @@ CONFIG_CHR_DEV_SG=y # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -521,6 +522,9 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FEC_MPC52xx=y CONFIG_FEC_MPC52xx_MDIO=y @@ -532,7 +536,6 @@ CONFIG_FEC_MPC52xx_MDIO=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI is not set # CONFIG_IWLWIFI_LEDS is not set # @@ -567,6 +570,7 @@ CONFIG_FEC_MPC52xx_MDIO=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -596,25 +600,40 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# CONFIG_I2C_MPC=y # CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -623,10 +642,13 @@ CONFIG_I2C_MPC=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -640,24 +662,39 @@ CONFIG_WATCHDOG=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# # CONFIG_DAB is not set # @@ -672,10 +709,6 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -695,11 +728,16 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PPC_SOC=y CONFIG_USB_OHCI_HCD_PPC_OF=y @@ -710,12 +748,16 @@ CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y # CONFIG_USB_OHCI_LITTLE_ENDIAN is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -744,7 +786,6 @@ CONFIG_USB_STORAGE=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -757,7 +798,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -773,14 +814,19 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_EDAC is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -792,12 +838,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -830,6 +877,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -860,6 +908,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -870,14 +919,14 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -953,9 +1002,9 @@ CONFIG_NLS_ISO8859_1=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -982,9 +1031,12 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set @@ -998,16 +1050,37 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set # CONFIG_BOOTX_TEXT is not set @@ -1018,14 +1091,19 @@ CONFIG_SCHED_DEBUG=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1063,6 +1141,10 @@ CONFIG_CRYPTO_PCBC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -1093,6 +1175,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y diff --git a/arch/powerpc/configs/52xx/lite5200b_defconfig b/arch/powerpc/configs/52xx/lite5200b_defconfig index 1a8a250fa11b..5b969f9c925e 100644 --- a/arch/powerpc/configs/52xx/lite5200b_defconfig +++ b/arch/powerpc/configs/52xx/lite5200b_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Tue Apr 29 07:12:56 2008 +# Linux kernel version: 2.6.28-rc4 +# Thu Nov 13 02:10:16 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -103,7 +104,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -111,24 +114,30 @@ CONFIG_SLUB=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -143,19 +152,16 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # Platform support # CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set CONFIG_PPC_MPC52xx=y CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_EFIKA is not set @@ -165,7 +171,10 @@ CONFIG_PPC_LITE5200=y # CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -198,11 +207,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -217,19 +228,20 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y @@ -243,7 +255,7 @@ CONFIG_ISA_DMA_API=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y # CONFIG_PPC_INDIRECT_PCI is not set -CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y @@ -269,10 +281,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -323,6 +331,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -343,14 +352,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -390,12 +393,16 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -412,7 +419,7 @@ CONFIG_SCSI_DMA=y # # SCSI support type (disk, tape, CD-ROM) # -# CONFIG_BLK_DEV_SD is not set +CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set @@ -474,12 +481,12 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set # CONFIG_SATA_SIL24 is not set -# CONFIG_SATA_FSL is not set CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set # CONFIG_ATA_PIIX is not set @@ -535,18 +542,22 @@ CONFIG_PATA_MPC52xx=y # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # + +# +# Enable only one of the two stacks, unless you know what you are doing +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -583,16 +594,19 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set CONFIG_FEC_MPC52xx=y CONFIG_FEC_MPC52xx_MDIO=y +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set # CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_NS83820 is not set @@ -605,22 +619,27 @@ CONFIG_NETDEV_1000=y # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set -# CONFIG_GIANFAR is not set # CONFIG_MV643XX_ETH is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set # CONFIG_TR is not set # @@ -628,7 +647,6 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI is not set # CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set @@ -657,6 +675,7 @@ CONFIG_NETDEV_10000=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -691,42 +710,63 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# PC SMBus host controller drivers +# # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_MPC=y # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_MPC=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -735,29 +775,47 @@ CONFIG_I2C_MPC=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# # CONFIG_DAB is not set # @@ -774,10 +832,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -787,18 +841,26 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set # CONFIG_EDAC is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -810,12 +872,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -845,6 +908,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -864,6 +928,7 @@ CONFIG_TMPFS=y # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -874,14 +939,14 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -902,9 +967,9 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -929,9 +994,12 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set @@ -945,17 +1013,37 @@ CONFIG_SCHED_DEBUG=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set # CONFIG_BOOTX_TEXT is not set @@ -966,14 +1054,19 @@ CONFIG_DEBUG_INFO=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1012,6 +1105,10 @@ CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -1042,6 +1139,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/52xx/motionpro_defconfig b/arch/powerpc/configs/52xx/motionpro_defconfig index 8c7ba7c6ba49..3c0d4e561726 100644 --- a/arch/powerpc/configs/52xx/motionpro_defconfig +++ b/arch/powerpc/configs/52xx/motionpro_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Tue Apr 29 07:12:22 2008 +# Linux kernel version: 2.6.28-rc4 +# Thu Nov 13 02:11:02 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -102,6 +103,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -110,9 +112,13 @@ CONFIG_SLUB=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -123,6 +129,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -137,19 +144,16 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support # CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set CONFIG_PPC_MPC52xx=y CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_EFIKA is not set @@ -159,7 +163,10 @@ CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -183,7 +190,6 @@ CONFIG_PPC_BESTCOMM_FEC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -197,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -211,19 +219,20 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -233,7 +242,7 @@ CONFIG_ISA_DMA_API=y # CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y -CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y # CONFIG_PCI is not set # CONFIG_PCI_DOMAINS is not set # CONFIG_PCI_SYSCALL is not set @@ -254,10 +263,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -308,6 +313,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -328,14 +334,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -445,9 +445,12 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -490,10 +493,10 @@ CONFIG_CHR_DEV_SG=y CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y -# CONFIG_SATA_FSL is not set CONFIG_ATA_SFF=y # CONFIG_SATA_MV is not set CONFIG_PATA_MPC52xx=y @@ -501,7 +504,6 @@ CONFIG_PATA_MPC52xx=y # CONFIG_MD is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -531,6 +533,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FEC_MPC52xx=y CONFIG_FEC_MPC52xx_MDIO=y @@ -542,7 +547,6 @@ CONFIG_FEC_MPC52xx_MDIO=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI is not set # CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set @@ -568,6 +572,7 @@ CONFIG_FEC_MPC52xx_MDIO=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -596,24 +601,39 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# CONFIG_I2C_MPC=y # CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set CONFIG_SENSORS_EEPROM=y # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -622,10 +642,13 @@ CONFIG_SENSORS_EEPROM=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -633,6 +656,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set @@ -675,6 +699,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -683,24 +708,39 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_MPC5200_WDT is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# CONFIG_DAB=y # @@ -715,10 +755,6 @@ CONFIG_DAB=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set @@ -729,6 +765,7 @@ CONFIG_LEDS_CLASS=y # # LED drivers # +# CONFIG_LEDS_PCA955X is not set # # LED Triggers @@ -736,7 +773,9 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_EDAC is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y @@ -767,6 +806,8 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers @@ -776,19 +817,25 @@ CONFIG_RTC_DRV_DS1307=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # +# CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -800,12 +847,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -838,6 +886,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -868,6 +917,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -878,14 +928,14 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -961,9 +1011,9 @@ CONFIG_NLS_ISO8859_1=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -990,9 +1040,12 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set @@ -1006,16 +1059,37 @@ CONFIG_SCHED_DEBUG=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set # CONFIG_BOOTX_TEXT is not set @@ -1026,14 +1100,19 @@ CONFIG_DEBUG_INFO=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1071,6 +1150,10 @@ CONFIG_CRYPTO_PCBC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -1101,6 +1184,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y diff --git a/arch/powerpc/configs/52xx/pcm030_defconfig b/arch/powerpc/configs/52xx/pcm030_defconfig index 9c0caa488b2e..9d0207783d60 100644 --- a/arch/powerpc/configs/52xx/pcm030_defconfig +++ b/arch/powerpc/configs/52xx/pcm030_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Tue Apr 29 07:13:19 2008 +# Linux kernel version: 2.6.28-rc4 +# Thu Nov 13 02:13:16 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -104,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y # CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -112,24 +115,30 @@ CONFIG_SLAB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -144,19 +153,16 @@ CONFIG_IOSCHED_NOOP=y CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support # CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set CONFIG_PPC_MPC52xx=y CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_EFIKA is not set @@ -166,7 +172,10 @@ CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -199,12 +208,14 @@ CONFIG_HZ_100=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=100 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y # CONFIG_PREEMPT_RCU is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -219,17 +230,19 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" # CONFIG_PM is not set # CONFIG_SECCOMP is not set CONFIG_ISA_DMA_API=y @@ -240,7 +253,7 @@ CONFIG_ISA_DMA_API=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y # CONFIG_PPC_INDIRECT_PCI is not set -CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y @@ -265,10 +278,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -313,6 +322,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -333,14 +343,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -484,12 +488,12 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=m # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set # CONFIG_SATA_SIL24 is not set -# CONFIG_SATA_FSL is not set CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set # CONFIG_ATA_PIIX is not set @@ -545,18 +549,22 @@ CONFIG_PATA_MPC52xx=m # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # + +# +# Enable only one of the two stacks, unless you know what you are doing +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -593,10 +601,14 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set CONFIG_FEC_MPC52xx=y CONFIG_FEC_MPC52xx_MDIO=y +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -606,7 +618,6 @@ CONFIG_FEC_MPC52xx_MDIO=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI is not set # CONFIG_IWLWIFI_LEDS is not set # @@ -644,6 +655,7 @@ CONFIG_FEC_MPC52xx_MDIO=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -675,43 +687,64 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# PC SMBus host controller drivers +# # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_MPC=y # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_MPC=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set CONFIG_SENSORS_EEPROM=m # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -720,29 +753,47 @@ CONFIG_SENSORS_EEPROM=m # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# # CONFIG_DAB is not set # @@ -759,10 +810,6 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -781,12 +828,17 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_HCD_PPC_SOC is not set CONFIG_USB_OHCI_HCD_PPC_OF=y @@ -799,12 +851,17 @@ CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -833,7 +890,6 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -846,7 +902,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -862,10 +918,14 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set # CONFIG_EDAC is not set CONFIG_RTC_LIB=m @@ -894,6 +954,8 @@ CONFIG_RTC_DRV_PCF8563=m # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers @@ -903,19 +965,25 @@ CONFIG_RTC_DRV_PCF8563=m # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # +# CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -927,12 +995,13 @@ CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=m CONFIG_FS_MBCACHE=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -964,6 +1033,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -994,6 +1064,7 @@ CONFIG_JFFS2_RTIME=y # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -1004,13 +1075,13 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1070,9 +1141,9 @@ CONFIG_NLS_ISO8859_1=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -1098,7 +1169,17 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set # CONFIG_BOOTX_TEXT is not set # CONFIG_PPC_EARLY_DEBUG is not set @@ -1108,6 +1189,7 @@ CONFIG_FRAME_WARN=1024 # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/52xx/tqm5200_defconfig b/arch/powerpc/configs/52xx/tqm5200_defconfig index 7672bfba3566..bc190051e8d5 100644 --- a/arch/powerpc/configs/52xx/tqm5200_defconfig +++ b/arch/powerpc/configs/52xx/tqm5200_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Tue Apr 29 07:12:39 2008 +# Linux kernel version: 2.6.28-rc4 +# Thu Nov 13 02:09:30 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -32,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -102,6 +103,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -110,14 +112,19 @@ CONFIG_SLUB=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y @@ -128,6 +135,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -142,19 +150,16 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support # CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set CONFIG_PPC_MPC52xx=y CONFIG_PPC_MPC5200_SIMPLE=y # CONFIG_PPC_EFIKA is not set @@ -164,7 +169,10 @@ CONFIG_PPC_MPC5200_BUGFIX=y # CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set # CONFIG_IPIC is not set # CONFIG_MPIC is not set @@ -188,7 +196,6 @@ CONFIG_PPC_BESTCOMM_FEC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -202,6 +209,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -216,19 +225,20 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -238,7 +248,7 @@ CONFIG_ISA_DMA_API=y # CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y -CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y # CONFIG_PCI is not set # CONFIG_PCI_DOMAINS is not set # CONFIG_PCI_SYSCALL is not set @@ -259,10 +269,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -313,6 +319,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -333,14 +340,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -451,6 +452,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -495,10 +497,10 @@ CONFIG_SCSI_WAIT_SCAN=m CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y -# CONFIG_SATA_FSL is not set CONFIG_ATA_SFF=y # CONFIG_SATA_MV is not set CONFIG_PATA_MPC52xx=y @@ -507,7 +509,6 @@ CONFIG_PATA_PLATFORM=y # CONFIG_MD is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -537,6 +538,9 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FEC_MPC52xx=y CONFIG_FEC_MPC52xx_MDIO=y @@ -548,7 +552,6 @@ CONFIG_FEC_MPC52xx_MDIO=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI is not set # CONFIG_IWLWIFI_LEDS is not set # @@ -583,6 +586,7 @@ CONFIG_FEC_MPC52xx_MDIO=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -611,26 +615,41 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# CONFIG_I2C_MPC=y # CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set # CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -639,10 +658,13 @@ CONFIG_I2C_MPC=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -650,6 +672,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set @@ -692,6 +715,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -705,24 +729,39 @@ CONFIG_WATCHDOG=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# # CONFIG_DAB is not set # @@ -737,10 +776,6 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -760,11 +795,16 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PPC_SOC=y CONFIG_USB_OHCI_HCD_PPC_OF=y @@ -775,12 +815,16 @@ CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y # CONFIG_USB_OHCI_LITTLE_ENDIAN is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -809,7 +853,6 @@ CONFIG_USB_STORAGE=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -CONFIG_USB_MON=y # # USB port drivers @@ -822,7 +865,7 @@ CONFIG_USB_MON=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -838,10 +881,13 @@ CONFIG_USB_MON=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_EDAC is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y @@ -872,6 +918,8 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers @@ -881,19 +929,25 @@ CONFIG_RTC_DRV_DS1307=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # +# CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -905,12 +959,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -943,6 +998,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -973,6 +1029,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -983,14 +1040,14 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1066,9 +1123,9 @@ CONFIG_NLS_ISO8859_1=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -1095,9 +1152,12 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set @@ -1111,17 +1171,37 @@ CONFIG_SCHED_DEBUG=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set # CONFIG_BOOTX_TEXT is not set @@ -1132,14 +1212,19 @@ CONFIG_DEBUG_INFO=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1178,6 +1263,10 @@ CONFIG_CRYPTO_PCBC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -1208,6 +1297,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y diff --git a/arch/powerpc/configs/83xx/asp8347_defconfig b/arch/powerpc/configs/83xx/asp8347_defconfig index 0b1fa20f745c..cbecaf3d7906 100644 --- a/arch/powerpc/configs/83xx/asp8347_defconfig +++ b/arch/powerpc/configs/83xx/asp8347_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:01 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:49 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -54,8 +54,6 @@ CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y # CONFIG_DEFAULT_UIMAGE is not set CONFIG_REDBOOT=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -99,7 +97,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -109,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +121,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +153,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -165,10 +161,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -188,24 +184,21 @@ CONFIG_ASP834x=y CONFIG_PPC_MPC834x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -225,6 +218,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -239,15 +234,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -259,7 +254,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -272,7 +266,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -340,6 +334,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -360,11 +355,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -470,7 +464,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -547,8 +540,6 @@ CONFIG_PHYLIB=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -559,8 +550,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -583,6 +578,7 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -667,14 +663,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set @@ -710,12 +703,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -753,6 +740,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -774,7 +762,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -829,7 +816,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -855,6 +841,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -907,6 +904,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -923,6 +922,8 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -930,6 +931,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -956,6 +958,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -972,7 +975,9 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1018,12 +1023,15 @@ CONFIG_RTC_DRV_DS1374=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1032,6 +1040,7 @@ CONFIG_RTC_DRV_DS1374=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1043,12 +1052,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1078,6 +1088,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1126,6 +1137,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1197,7 +1209,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1229,13 +1240,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1247,14 +1260,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1327,6 +1345,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig index b7eae2bdf19c..bfc32ea265a7 100644 --- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:17 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:50 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,21 @@ CONFIG_MPC831x_RDB=y CONFIG_PPC_MPC831x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -224,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -238,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -271,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -340,6 +334,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -360,11 +355,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -470,6 +464,7 @@ CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ALAUDA is not set CONFIG_MTD_NAND_FSL_ELBC=y +# CONFIG_MTD_NAND_FSL_UPM is not set # CONFIG_MTD_ONENAND is not set # @@ -482,7 +477,6 @@ CONFIG_OF_SPI=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -583,13 +577,12 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -638,8 +631,6 @@ CONFIG_CICADA_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -651,6 +642,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -671,6 +665,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -693,18 +688,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -790,14 +789,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -833,12 +829,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -876,6 +866,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -913,7 +904,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -935,6 +925,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set @@ -969,7 +960,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -995,6 +985,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1037,12 +1038,18 @@ CONFIG_HID=y # USB Input Devices # # CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1061,6 +1068,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1084,6 +1093,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # CONFIG_USB_GADGET_MUSB_HDRC is not set # @@ -1092,6 +1103,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1113,7 +1125,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1134,6 +1145,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1151,23 +1163,26 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -CONFIG_USB_GADGET_NET2280=y -CONFIG_USB_NET2280=y -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set # CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=y +# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set @@ -1179,6 +1194,7 @@ CONFIG_USB_ETH_RNDIS=y # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1224,17 +1240,21 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1243,6 +1263,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1254,12 +1275,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1289,6 +1311,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1337,6 +1360,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1373,7 +1397,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1427,15 +1450,23 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1444,6 +1475,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1455,14 +1487,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1535,6 +1572,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig index b0a27a67d8c7..aad0e1a98c55 100644 --- a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:18 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:51 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,21 @@ CONFIG_MPC831x_RDB=y CONFIG_PPC_MPC831x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -224,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -238,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -271,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -340,6 +334,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -360,11 +355,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -470,6 +464,7 @@ CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_NAND_FSL_UPM is not set # CONFIG_MTD_ONENAND is not set # @@ -482,7 +477,6 @@ CONFIG_OF_SPI=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -584,8 +578,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -651,6 +643,7 @@ CONFIG_ATA_SFF=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -699,8 +692,6 @@ CONFIG_PHYLIB=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -712,6 +703,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -732,6 +726,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -754,18 +749,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -851,14 +850,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -894,12 +890,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -937,6 +927,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -974,7 +965,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -996,6 +986,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set @@ -1030,7 +1021,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -1056,6 +1046,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1098,12 +1099,18 @@ CONFIG_HID=y # USB Input Devices # # CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1122,6 +1129,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1145,6 +1154,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # CONFIG_USB_GADGET_MUSB_HDRC is not set # @@ -1153,6 +1164,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1174,7 +1186,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1195,6 +1206,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1212,23 +1224,26 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -CONFIG_USB_GADGET_NET2280=y -CONFIG_USB_NET2280=y -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set # CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=y +# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set @@ -1240,6 +1255,7 @@ CONFIG_USB_ETH_RNDIS=y # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1285,17 +1301,21 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1304,6 +1324,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1315,12 +1336,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1350,6 +1372,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1398,6 +1421,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1434,7 +1458,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1488,15 +1511,23 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1505,6 +1536,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1516,14 +1548,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1596,6 +1633,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc832x_mds_defconfig b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig index ad825bcddd1f..9cb8c8b956e4 100644 --- a/arch/powerpc/configs/83xx/mpc832x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:18 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:53 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,20 @@ CONFIG_MPC832x_MDS=y CONFIG_PPC_MPC832x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set CONFIG_QUICC_ENGINE=y +# CONFIG_QE_GPIO is not set # CONFIG_FSL_ULI1575 is not set # @@ -225,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -240,15 +234,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -260,7 +254,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -273,7 +266,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -341,6 +334,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -361,11 +355,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -391,7 +384,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -491,8 +483,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set # CONFIG_ATA is not set @@ -537,8 +527,6 @@ CONFIG_DAVICOM_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -549,8 +537,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -577,18 +569,22 @@ CONFIG_UCC_GETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -665,15 +661,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set # CONFIG_SERIAL_QE is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -709,12 +702,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -751,6 +738,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -772,7 +760,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -827,7 +814,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -848,6 +834,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -884,6 +881,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -900,6 +903,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -945,12 +949,15 @@ CONFIG_RTC_DRV_DS1374=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -959,6 +966,7 @@ CONFIG_RTC_DRV_DS1374=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -970,12 +978,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1005,6 +1014,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1042,6 +1052,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1071,13 +1082,11 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_DLM is not set CONFIG_UCC_FAST=y CONFIG_UCC=y -# CONFIG_QE_GPIO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1107,13 +1116,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1125,14 +1136,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1205,6 +1221,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig index 38267501f44d..9cc976f010c9 100644 --- a/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:19 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:54 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,20 @@ CONFIG_MPC832x_RDB=y CONFIG_PPC_MPC832x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set CONFIG_QUICC_ENGINE=y +# CONFIG_QE_GPIO is not set # CONFIG_FSL_ULI1575 is not set # @@ -225,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -240,15 +234,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -260,7 +254,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -273,7 +266,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -341,6 +334,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -361,11 +355,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -392,7 +385,6 @@ CONFIG_OF_SPI=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -493,8 +485,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set # CONFIG_ATA is not set @@ -539,8 +529,6 @@ CONFIG_ICPLUS_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -552,13 +540,16 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -581,18 +572,22 @@ CONFIG_UCC_GETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -678,15 +673,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set # CONFIG_SERIAL_QE is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -724,12 +716,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -767,6 +753,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -803,7 +790,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -825,6 +811,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set @@ -859,7 +846,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -885,6 +871,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -927,12 +924,18 @@ CONFIG_HID=y # USB Input Devices # # CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -951,6 +954,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -974,6 +979,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -981,6 +988,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1002,7 +1010,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1023,6 +1030,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1040,13 +1048,15 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y @@ -1054,7 +1064,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_WBSD is not set @@ -1068,6 +1078,7 @@ CONFIG_MMC_SPI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1079,12 +1090,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1117,6 +1129,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1154,6 +1167,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1227,13 +1241,11 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_DLM is not set CONFIG_UCC_FAST=y CONFIG_UCC=y -# CONFIG_QE_GPIO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1263,13 +1275,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1281,14 +1295,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1361,6 +1380,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc834x_itx_defconfig b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig index 90aab340e7ff..07a674f5344e 100644 --- a/arch/powerpc/configs/83xx/mpc834x_itx_defconfig +++ b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:20 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:56 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,21 @@ CONFIG_MPC834x_ITX=y CONFIG_PPC_MPC834x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -224,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -238,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -271,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -339,6 +333,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -359,11 +354,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -469,7 +463,6 @@ CONFIG_OF_SPI=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -496,7 +489,54 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -# CONFIG_BLK_DEV_IDE is not set + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_PLATFORM is not set + +# +# PCI IDE chipsets support +# +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_IDEDMA is not set # # SCSI device support @@ -572,8 +612,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -640,6 +678,7 @@ CONFIG_PATA_OF_PLATFORM=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -684,7 +723,7 @@ CONFIG_CICADA_PHY=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set -# CONFIG_FIXED_PHY is not set +CONFIG_FIXED_PHY=y # CONFIG_MDIO_BITBANG is not set # CONFIG_NET_ETHERNET is not set CONFIG_NETDEV_1000=y @@ -709,18 +748,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -786,14 +829,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -829,12 +869,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -872,6 +906,7 @@ CONFIG_SENSORS_PCF8574=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -907,7 +942,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -933,6 +967,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -984,6 +1029,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1000,6 +1047,8 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1007,6 +1056,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1027,7 +1077,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1048,6 +1097,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1065,7 +1115,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1111,17 +1163,21 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1130,6 +1186,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1141,12 +1198,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1179,6 +1237,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1217,6 +1276,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1292,7 +1352,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1322,13 +1381,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1340,14 +1401,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1420,6 +1486,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig index 7458a242d251..426232cb0097 100644 --- a/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig +++ b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:21 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:57 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,21 @@ CONFIG_MPC834x_ITX=y CONFIG_PPC_MPC834x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -224,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -238,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -271,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -339,6 +333,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -359,11 +354,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -469,7 +463,6 @@ CONFIG_OF_SPI=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -570,8 +563,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set # CONFIG_ATA is not set @@ -637,18 +628,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -714,14 +709,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -757,12 +749,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -800,6 +786,7 @@ CONFIG_SENSORS_PCF8574=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -835,7 +822,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -861,6 +847,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -912,6 +909,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -928,6 +927,8 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -935,6 +936,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -955,7 +957,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -976,6 +977,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -992,7 +994,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1038,17 +1042,21 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1057,6 +1065,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1068,12 +1077,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1106,6 +1116,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1144,6 +1155,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1219,7 +1231,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1249,13 +1260,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1267,14 +1280,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1347,6 +1365,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc834x_mds_defconfig b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig index 1a92798938cf..36e2e93a1c53 100644 --- a/arch/powerpc/configs/83xx/mpc834x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:21 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:58 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,24 +183,21 @@ CONFIG_MPC834x_MDS=y CONFIG_PPC_MPC834x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -224,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -238,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -271,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -339,6 +333,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -359,11 +354,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -389,7 +383,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -465,8 +458,6 @@ CONFIG_MARVELL_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -477,6 +468,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -497,6 +491,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -519,18 +514,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -606,14 +605,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set @@ -649,12 +645,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -691,6 +681,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -712,7 +703,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -767,7 +757,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -788,6 +777,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -824,6 +824,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -840,6 +846,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -885,12 +892,15 @@ CONFIG_RTC_DRV_DS1374=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -899,6 +909,7 @@ CONFIG_RTC_DRV_DS1374=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -910,12 +921,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -945,6 +957,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -982,6 +995,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1014,7 +1028,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1044,13 +1057,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1062,14 +1077,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1142,6 +1162,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig index 03d8cede0272..80eb6c9a05c4 100644 --- a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:22 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:59 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -164,10 +160,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -186,24 +182,20 @@ CONFIG_MPC836x_MDS=y # CONFIG_ASP834x is not set # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set CONFIG_QUICC_ENGINE=y +# CONFIG_QE_GPIO is not set # CONFIG_FSL_ULI1575 is not set # @@ -224,6 +216,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -238,15 +232,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +252,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -271,7 +264,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -339,6 +332,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -359,11 +353,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -466,7 +459,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -566,8 +558,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set # CONFIG_ATA is not set @@ -612,8 +602,6 @@ CONFIG_MARVELL_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -624,8 +612,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -652,18 +644,22 @@ CONFIG_UCC_GETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -740,15 +736,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set # CONFIG_SERIAL_QE is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -784,12 +777,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -826,6 +813,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -847,7 +835,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -902,7 +889,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -923,6 +909,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -959,6 +956,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -975,6 +978,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1020,12 +1024,15 @@ CONFIG_RTC_DRV_DS1374=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1034,6 +1041,7 @@ CONFIG_RTC_DRV_DS1374=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1045,12 +1053,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1080,6 +1089,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1096,6 +1106,7 @@ CONFIG_TMPFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set @@ -1117,6 +1128,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1146,13 +1158,11 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_DLM is not set CONFIG_UCC_FAST=y CONFIG_UCC=y -# CONFIG_QE_GPIO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1182,13 +1192,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1200,14 +1212,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1280,6 +1297,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig index cdf84177370a..b9b236806e9f 100644 --- a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig +++ b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:24 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:00 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -54,8 +54,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -99,7 +97,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -109,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +121,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +153,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -165,10 +161,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -187,31 +183,26 @@ CONFIG_MPC836x_RDK=y # CONFIG_ASP834x is not set # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set CONFIG_QUICC_ENGINE=y +CONFIG_QE_GPIO=y # CONFIG_FSL_ULI1575 is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -225,6 +216,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -239,15 +232,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -259,7 +252,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -274,7 +266,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -342,6 +334,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -362,11 +355,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -480,7 +472,6 @@ CONFIG_OF_SPI=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -581,6 +572,7 @@ CONFIG_UCC_GETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -660,15 +652,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_SERIAL_QE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -705,12 +694,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -749,6 +732,7 @@ CONFIG_I2C_MPC=y # CONFIG_TPS65010 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -804,7 +788,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -825,6 +808,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -852,6 +846,7 @@ CONFIG_DAB=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -874,9 +869,6 @@ CONFIG_FB_MACMODES=y # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set CONFIG_FB_OF=y -# CONFIG_FB_CONTROL is not set -# CONFIG_FB_PLATINUM is not set -# CONFIG_FB_VALKYRIE is not set # CONFIG_FB_CT65550 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set @@ -891,6 +883,7 @@ CONFIG_FB_OF=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -903,6 +896,7 @@ CONFIG_FB_OF=y # CONFIG_FB_FSL_DIU is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -930,7 +924,14 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -940,6 +941,7 @@ CONFIG_HID=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -951,12 +953,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -986,6 +989,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1034,6 +1038,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1064,13 +1069,11 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_UCC_SLOW=y CONFIG_UCC_FAST=y CONFIG_UCC=y -CONFIG_QE_GPIO=y # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1102,13 +1105,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1116,7 +1121,7 @@ CONFIG_HAVE_ARCH_KGDB=y CONFIG_PPC_EARLY_DEBUG=y # CONFIG_PPC_EARLY_DEBUG_LPAR is not set # CONFIG_PPC_EARLY_DEBUG_G5 is not set -CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL=y +# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set # CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set # CONFIG_PPC_EARLY_DEBUG_MAPLE is not set # CONFIG_PPC_EARLY_DEBUG_ISERIES is not set @@ -1131,14 +1136,19 @@ CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1211,6 +1221,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc837x_mds_defconfig b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig index 97e02d7a5b09..f6350d7e1688 100644 --- a/arch/powerpc/configs/83xx/mpc837x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:23 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:00 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -99,7 +97,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -109,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -122,10 +121,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +153,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -165,10 +161,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -188,30 +184,26 @@ CONFIG_MPC837x_MDS=y CONFIG_PPC_MPC837x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -225,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -239,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -259,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -272,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -340,6 +333,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -360,11 +354,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -390,7 +383,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -491,8 +483,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -597,8 +587,6 @@ CONFIG_MARVELL_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -609,8 +597,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -633,18 +625,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -721,14 +717,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set @@ -766,12 +759,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -808,6 +795,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -829,7 +817,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -884,7 +871,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -905,6 +891,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -941,6 +938,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -957,6 +960,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -966,6 +970,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -977,12 +982,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1012,6 +1018,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1049,6 +1056,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1085,7 +1093,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1113,13 +1120,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1131,14 +1140,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1211,6 +1225,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig index 5ac33054ce2c..f447de16f75d 100644 --- a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:25 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:01 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -99,7 +97,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -109,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -122,10 +121,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,6 +153,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -165,10 +161,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -188,30 +184,26 @@ CONFIG_MPC837x_RDB=y CONFIG_PPC_MPC837x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -225,6 +217,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -239,15 +233,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -259,7 +253,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -272,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -335,6 +328,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -355,11 +349,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -385,7 +378,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -487,8 +479,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -554,6 +544,7 @@ CONFIG_ATA_SFF=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set CONFIG_MD_RAID1=y @@ -603,8 +594,6 @@ CONFIG_FIXED_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -615,8 +604,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -639,6 +632,7 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -673,7 +667,7 @@ CONFIG_GIANFAR=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -724,14 +718,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set @@ -769,12 +760,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -812,6 +797,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -833,7 +819,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -888,7 +873,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -914,6 +898,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -956,9 +951,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -977,6 +999,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -993,6 +1017,8 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1000,6 +1026,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1028,6 +1055,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1044,7 +1072,9 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1054,6 +1084,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1065,12 +1096,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1100,6 +1132,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1137,6 +1170,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1173,7 +1207,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1201,13 +1234,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1219,6 +1254,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y @@ -1229,8 +1265,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1303,6 +1343,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/83xx/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig index c359cc2a380e..8d2d7eeab5f5 100644 --- a/arch/powerpc/configs/83xx/sbc834x_defconfig +++ b/arch/powerpc/configs/83xx/sbc834x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:27 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:02 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -53,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -98,7 +96,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -108,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -120,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -156,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -163,10 +159,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -186,30 +182,26 @@ CONFIG_SBC834x=y CONFIG_PPC_MPC834x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -223,6 +215,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -237,15 +231,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -257,7 +251,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -270,7 +263,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -338,6 +331,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -358,11 +352,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -388,7 +381,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -464,8 +456,6 @@ CONFIG_BROADCOM_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -476,8 +466,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -500,6 +494,7 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -575,14 +570,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set @@ -620,12 +612,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -662,6 +648,7 @@ CONFIG_I2C_MPC=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -683,7 +670,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -738,7 +724,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -759,6 +744,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -795,7 +791,14 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -805,16 +808,18 @@ CONFIG_HID=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -844,6 +849,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -881,6 +887,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -893,7 +900,6 @@ CONFIG_RPCSEC_GSS_KRB5=y # Partition Types # # CONFIG_PARTITION_ADVANCED is not set -CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y # CONFIG_NLS is not set # CONFIG_DLM is not set @@ -902,7 +908,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -930,13 +935,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -948,14 +955,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1028,6 +1040,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/85xx/ksi8560_defconfig b/arch/powerpc/configs/85xx/ksi8560_defconfig index 8bb89f26a20d..1af7b9e37b61 100644 --- a/arch/powerpc/configs/85xx/ksi8560_defconfig +++ b/arch/powerpc/configs/85xx/ksi8560_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:28 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:03 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -104,6 +104,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -117,10 +118,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -147,6 +145,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -181,15 +180,16 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # CONFIG_HIGHMEM=y -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -203,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -217,15 +219,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -311,6 +313,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -331,11 +334,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -454,17 +456,16 @@ CONFIG_MISC_DEVICES=y # CONFIG_ENCLOSURE_SERVICES is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set -# CONFIG_BLK_DEV_IDEDISK is not set -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -515,6 +516,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set @@ -590,12 +594,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -659,6 +657,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -692,6 +698,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -715,6 +727,7 @@ CONFIG_USB_SUPPORT=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -726,13 +739,14 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -762,6 +776,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -797,6 +812,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -829,7 +845,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -882,15 +897,23 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -899,6 +922,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -910,12 +934,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -987,6 +1013,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_TALITOS is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/85xx/mpc8536_ds_defconfig b/arch/powerpc/configs/85xx/mpc8536_ds_defconfig index 6b516bea6e75..e243e14a6708 100644 --- a/arch/powerpc/configs/85xx/mpc8536_ds_defconfig +++ b/arch/powerpc/configs/85xx/mpc8536_ds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 07:18:18 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:05 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -124,10 +126,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,6 +158,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -194,8 +193,10 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -215,6 +216,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -229,15 +232,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -260,7 +263,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -362,6 +365,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -382,12 +386,11 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -633,8 +636,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -658,18 +665,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -704,7 +715,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -872,6 +883,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -912,7 +934,6 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_USB is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_CINERGYT2 is not set # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -929,6 +950,11 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # CONFIG_DVB_PLUTO2 is not set +# +# Supported SDMC DM1105 Adapters +# +# CONFIG_DVB_DM1105 is not set + # # Supported DVB Frontends # @@ -945,6 +971,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_CX24123 is not set # CONFIG_DVB_MT312 is not set # CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set # CONFIG_DVB_STV0299 is not set # CONFIG_DVB_TDA8083 is not set # CONFIG_DVB_TDA10086 is not set @@ -952,6 +980,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TDA826X is not set # CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set # # DVB-T (terrestrial) frontends @@ -1004,6 +1034,13 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_LNBP21 is not set # CONFIG_DVB_ISL6405 is not set # CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -1029,6 +1066,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1127,9 +1165,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1148,6 +1213,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1171,6 +1238,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1178,6 +1247,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1199,7 +1269,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1220,6 +1289,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1237,7 +1307,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1283,12 +1355,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1309,6 +1384,7 @@ CONFIG_DMA_ENGINE=y # CONFIG_NET_DMA is not set # CONFIG_DMATEST is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1320,13 +1396,14 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1364,6 +1441,7 @@ CONFIG_NTFS_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1408,6 +1486,7 @@ CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1483,7 +1562,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1537,15 +1615,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1554,6 +1640,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -1565,16 +1652,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1647,6 +1737,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_CRYPTO_DEV_TALITOS=y diff --git a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig index 1ea181f826f1..d790cbab80b8 100644 --- a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig +++ b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:30 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:06 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -107,6 +107,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -120,10 +121,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -150,6 +147,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -184,8 +182,10 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -205,6 +205,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -219,15 +221,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -313,6 +315,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -333,11 +336,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -421,6 +423,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_NETDEV_1000=y CONFIG_GIANFAR=y @@ -544,6 +549,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -577,6 +590,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -600,6 +619,7 @@ CONFIG_USB_SUPPORT=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -611,12 +631,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -646,6 +667,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -680,6 +702,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -712,7 +735,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -764,15 +786,23 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -781,6 +811,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -791,12 +822,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -868,6 +901,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_TALITOS is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/85xx/mpc8544_ds_defconfig b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig index 1aecdeab9841..f6cb01495ea6 100644 --- a/arch/powerpc/configs/85xx/mpc8544_ds_defconfig +++ b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 07:20:43 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:08 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -124,10 +126,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,6 +158,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -194,8 +193,10 @@ CONFIG_PPC_I8259=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set CONFIG_FSL_ULI1575=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -215,6 +216,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -229,15 +232,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -261,7 +264,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -363,6 +366,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -383,12 +387,11 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -634,8 +637,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -657,18 +664,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -703,7 +714,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -872,6 +883,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -912,7 +934,6 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_USB is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_CINERGYT2 is not set # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -929,6 +950,11 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # CONFIG_DVB_PLUTO2 is not set +# +# Supported SDMC DM1105 Adapters +# +# CONFIG_DVB_DM1105 is not set + # # Supported DVB Frontends # @@ -945,6 +971,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_CX24123 is not set # CONFIG_DVB_MT312 is not set # CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set # CONFIG_DVB_STV0299 is not set # CONFIG_DVB_TDA8083 is not set # CONFIG_DVB_TDA10086 is not set @@ -952,6 +980,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TDA826X is not set # CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set # # DVB-T (terrestrial) frontends @@ -1004,6 +1034,13 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_LNBP21 is not set # CONFIG_DVB_ISL6405 is not set # CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -1029,6 +1066,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1129,9 +1167,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1150,6 +1215,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1173,6 +1240,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1180,6 +1249,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1201,7 +1271,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1222,6 +1291,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1239,7 +1309,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1285,12 +1357,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1311,6 +1386,7 @@ CONFIG_DMA_ENGINE=y # CONFIG_NET_DMA is not set # CONFIG_DMATEST is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1322,12 +1398,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1365,6 +1442,7 @@ CONFIG_NTFS_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1409,6 +1487,7 @@ CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1484,7 +1563,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1538,15 +1616,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1555,6 +1641,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1565,16 +1652,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1647,6 +1737,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_CRYPTO_DEV_TALITOS=y diff --git a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig index 06e26d906f65..6cf929259ba7 100644 --- a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig +++ b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:32 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:09 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -108,7 +108,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +123,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -151,6 +150,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -185,15 +185,16 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -207,6 +208,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -221,15 +224,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -252,7 +255,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set CONFIG_PCI_DEBUG=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -322,6 +325,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -342,11 +346,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -459,8 +462,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set CONFIG_FS_ENET_HAS_FCC=y @@ -469,7 +476,6 @@ CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -487,18 +493,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -571,12 +581,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -CONFIG_SERIAL_CPM_SCC2=y -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y @@ -648,6 +652,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -683,6 +695,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -699,6 +717,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -708,6 +727,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -719,12 +739,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -754,6 +775,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -788,6 +810,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -820,7 +843,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -872,15 +894,23 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -889,6 +919,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -899,12 +930,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -976,6 +1009,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/mpc8568mds_defconfig b/arch/powerpc/configs/85xx/mpc8568mds_defconfig index dc27c74955fa..597be8491812 100644 --- a/arch/powerpc/configs/85xx/mpc8568mds_defconfig +++ b/arch/powerpc/configs/85xx/mpc8568mds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:33 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:11 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -105,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -118,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -154,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -189,8 +188,10 @@ CONFIG_MPIC=y # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set CONFIG_QUICC_ENGINE=y +# CONFIG_QE_GPIO is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -210,6 +211,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -224,15 +227,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -255,7 +258,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -325,6 +328,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -345,11 +349,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -530,8 +533,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -554,18 +561,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -815,6 +826,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -851,6 +873,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -867,6 +895,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -912,12 +941,15 @@ CONFIG_RTC_DRV_DS1374=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -926,6 +958,7 @@ CONFIG_RTC_DRV_DS1374=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -937,12 +970,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -972,6 +1006,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1009,6 +1044,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1036,13 +1072,11 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_SYSV68_PARTITION is not set # CONFIG_NLS is not set # CONFIG_DLM is not set -# CONFIG_QE_GPIO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1094,15 +1128,23 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1111,6 +1153,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1132,14 +1175,19 @@ CONFIG_PPC_EARLY_DEBUG=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1212,6 +1260,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/mpc8572_ds_defconfig b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig index eda45bb8a13f..635588319e0d 100644 --- a/arch/powerpc/configs/85xx/mpc8572_ds_defconfig +++ b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 07:21:42 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:13 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -124,10 +126,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,6 +158,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -194,8 +193,10 @@ CONFIG_PPC_I8259=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set CONFIG_FSL_ULI1575=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -215,6 +216,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -229,15 +232,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -261,7 +264,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -363,6 +366,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -383,12 +387,11 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -634,8 +637,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -657,18 +664,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -703,7 +714,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -872,6 +883,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -912,7 +934,6 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_USB is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_CINERGYT2 is not set # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -929,6 +950,11 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # CONFIG_DVB_PLUTO2 is not set +# +# Supported SDMC DM1105 Adapters +# +# CONFIG_DVB_DM1105 is not set + # # Supported DVB Frontends # @@ -945,6 +971,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_CX24123 is not set # CONFIG_DVB_MT312 is not set # CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set # CONFIG_DVB_STV0299 is not set # CONFIG_DVB_TDA8083 is not set # CONFIG_DVB_TDA10086 is not set @@ -952,6 +980,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TDA826X is not set # CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set # # DVB-T (terrestrial) frontends @@ -1004,6 +1034,13 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_LNBP21 is not set # CONFIG_DVB_ISL6405 is not set # CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -1029,6 +1066,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1129,9 +1167,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1150,6 +1215,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1173,6 +1240,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1180,6 +1249,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1201,7 +1271,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1222,6 +1291,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1239,7 +1309,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1285,12 +1357,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1299,6 +1374,7 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1310,12 +1386,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1353,6 +1430,7 @@ CONFIG_NTFS_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1397,6 +1475,7 @@ CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1472,7 +1551,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1526,15 +1604,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1543,6 +1629,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1553,16 +1640,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1635,6 +1725,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_CRYPTO_DEV_TALITOS=y diff --git a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig index 97f3c4fe440b..8769359dfe6a 100644 --- a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig +++ b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:34 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:14 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -107,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -120,10 +122,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -150,6 +148,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -184,8 +183,10 @@ CONFIG_PPC_I8259=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -205,6 +206,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -219,15 +222,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -250,7 +253,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -320,6 +323,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -340,11 +344,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -396,18 +399,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -# CONFIG_BLK_DEV_IDEDISK is not set -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -510,13 +512,16 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -534,18 +539,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -678,6 +687,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -713,6 +730,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -729,6 +752,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -738,6 +762,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -749,12 +774,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -784,6 +810,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -818,6 +845,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -850,7 +878,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -902,15 +929,23 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -919,6 +954,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -929,12 +965,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1006,6 +1044,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/sbc8548_defconfig b/arch/powerpc/configs/85xx/sbc8548_defconfig index 41cedc4b63f6..bfe3c9731573 100644 --- a/arch/powerpc/configs/85xx/sbc8548_defconfig +++ b/arch/powerpc/configs/85xx/sbc8548_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:35 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:16 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -106,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -118,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -148,6 +146,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -182,14 +181,15 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -203,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -217,15 +219,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -248,7 +250,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -317,6 +319,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -337,11 +340,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -451,8 +453,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -474,18 +480,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -618,6 +628,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -651,6 +669,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -660,16 +679,18 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -699,6 +720,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -733,6 +755,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -753,7 +776,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -781,13 +803,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -798,12 +822,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -875,6 +901,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig index daef36f41b42..8c507f8d15a8 100644 --- a/arch/powerpc/configs/85xx/sbc8560_defconfig +++ b/arch/powerpc/configs/85xx/sbc8560_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:36 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:17 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -107,6 +107,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -119,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -149,6 +146,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -183,14 +181,15 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -204,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -218,15 +219,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -312,6 +313,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -332,11 +334,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -420,6 +421,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_NETDEV_1000=y CONFIG_GIANFAR=y @@ -541,6 +545,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -574,6 +586,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -617,12 +635,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set CONFIG_RTC_DRV_M48T59=y +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -631,16 +652,18 @@ CONFIG_RTC_DRV_M48T59=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -670,6 +693,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -704,6 +728,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -736,7 +761,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -787,15 +811,23 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -804,6 +836,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -825,12 +858,14 @@ CONFIG_PPC_EARLY_DEBUG=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -902,6 +937,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_TALITOS is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/85xx/stx_gp3_defconfig b/arch/powerpc/configs/85xx/stx_gp3_defconfig index 2b05d43f8f7e..5a0cf58d2b8c 100644 --- a/arch/powerpc/configs/85xx/stx_gp3_defconfig +++ b/arch/powerpc/configs/85xx/stx_gp3_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:37 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:19 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -108,7 +108,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +124,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +156,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -191,15 +191,16 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # CONFIG_HIGHMEM=y -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -213,6 +214,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -227,15 +230,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -258,7 +261,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -319,7 +322,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -335,44 +337,46 @@ CONFIG_NETFILTER_ADVANCED=y CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set # CONFIG_NETFILTER_XT_MATCH_MAC is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=m -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set # CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set # CONFIG_IP_NF_MATCH_TTL is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set CONFIG_IP_NF_FILTER=m # CONFIG_IP_NF_TARGET_REJECT is not set # CONFIG_IP_NF_TARGET_LOG is not set @@ -385,6 +389,7 @@ CONFIG_IP_NF_FILTER=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -405,11 +410,10 @@ CONFIG_NET_PKTGEN=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -470,18 +474,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=m CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -651,9 +654,13 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set # CONFIG_NET_POCKET is not set +# CONFIG_ATL2 is not set # CONFIG_FS_ENET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set @@ -676,18 +683,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -746,6 +757,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set @@ -791,12 +803,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -CONFIG_SERIAL_CPM_SCC2=y -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y @@ -980,6 +986,16 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1019,12 +1035,19 @@ CONFIG_DRM=m # # CONFIG_DISPLAY_SUPPORT is not set CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set # CONFIG_SND is not set # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1041,6 +1064,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1051,6 +1075,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1062,12 +1087,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1103,6 +1129,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1139,6 +1166,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1199,7 +1227,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=m @@ -1253,15 +1280,23 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1270,6 +1305,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set CONFIG_BDI_SWITCH=y @@ -1280,12 +1316,14 @@ CONFIG_BDI_SWITCH=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1358,6 +1396,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/tqm8540_defconfig b/arch/powerpc/configs/85xx/tqm8540_defconfig index 1b2d5d577915..f3e4f3481fda 100644 --- a/arch/powerpc/configs/85xx/tqm8540_defconfig +++ b/arch/powerpc/configs/85xx/tqm8540_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:37 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:20 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -105,7 +105,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -118,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -148,6 +146,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -183,14 +182,15 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -204,6 +204,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -218,15 +220,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -249,7 +251,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_HAS_RAPIDIO is not set # @@ -316,6 +318,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -336,11 +339,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -466,18 +468,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -580,6 +581,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -600,6 +604,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -621,18 +626,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -867,6 +876,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -903,6 +923,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -919,6 +945,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -928,6 +955,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -939,12 +967,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -974,6 +1003,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1019,6 +1049,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1051,7 +1082,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1083,13 +1113,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1100,12 +1132,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1177,6 +1211,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/tqm8541_defconfig b/arch/powerpc/configs/85xx/tqm8541_defconfig index da841a09755c..c62489394535 100644 --- a/arch/powerpc/configs/85xx/tqm8541_defconfig +++ b/arch/powerpc/configs/85xx/tqm8541_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:39 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:21 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -106,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +121,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -149,6 +148,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -184,15 +184,16 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -206,6 +207,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -220,15 +223,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -251,7 +254,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_HAS_RAPIDIO is not set # @@ -318,6 +321,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,11 +342,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -469,18 +472,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -583,6 +585,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -603,6 +608,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set # CONFIG_FS_ENET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set @@ -625,18 +631,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -715,12 +725,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y @@ -900,6 +904,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -936,6 +951,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -952,6 +973,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -961,6 +983,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -972,12 +995,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1007,6 +1031,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1052,6 +1077,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1084,7 +1110,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1116,13 +1141,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1133,12 +1160,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1210,6 +1239,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/tqm8548_defconfig b/arch/powerpc/configs/85xx/tqm8548_defconfig index ca1234d26855..eef45b97dc3e 100644 --- a/arch/powerpc/configs/85xx/tqm8548_defconfig +++ b/arch/powerpc/configs/85xx/tqm8548_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:40 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:22 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -107,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -121,10 +123,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -157,6 +155,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -192,8 +191,10 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -213,6 +214,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -227,15 +230,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -260,7 +263,7 @@ CONFIG_PCIEAER=y # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -330,6 +333,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -350,11 +354,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -458,6 +461,7 @@ CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_NANDSIM is not set # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_NAND_FSL_UPM is not set # CONFIG_MTD_ONENAND is not set # @@ -502,18 +506,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -# CONFIG_BLK_DEV_IDEDISK is not set -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -616,13 +619,16 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -640,18 +646,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -885,6 +895,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -921,6 +942,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -937,6 +964,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -982,12 +1010,15 @@ CONFIG_RTC_DRV_DS1307=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -996,6 +1027,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1007,12 +1039,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1042,6 +1075,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1078,6 +1112,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1110,7 +1145,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1162,15 +1196,23 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1179,6 +1221,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1189,12 +1232,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1267,6 +1312,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/tqm8555_defconfig b/arch/powerpc/configs/85xx/tqm8555_defconfig index dcf9cfe28b55..11b637e99a54 100644 --- a/arch/powerpc/configs/85xx/tqm8555_defconfig +++ b/arch/powerpc/configs/85xx/tqm8555_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:42 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:23 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -106,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +121,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -149,6 +148,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -184,15 +184,16 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -206,6 +207,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -220,15 +223,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -251,7 +254,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_HAS_RAPIDIO is not set # @@ -318,6 +321,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,11 +342,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -469,18 +472,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -583,6 +585,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -603,6 +608,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set # CONFIG_FS_ENET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set @@ -625,18 +631,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -715,12 +725,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y @@ -900,6 +904,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -936,6 +951,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -952,6 +973,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -961,6 +983,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -972,12 +995,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1007,6 +1031,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1052,6 +1077,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1084,7 +1110,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1116,13 +1141,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1133,12 +1160,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1210,6 +1239,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/85xx/tqm8560_defconfig b/arch/powerpc/configs/85xx/tqm8560_defconfig index 8d676629cdb1..2519169b6d4b 100644 --- a/arch/powerpc/configs/85xx/tqm8560_defconfig +++ b/arch/powerpc/configs/85xx/tqm8560_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:43 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:25 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -106,7 +106,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +121,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -149,6 +148,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -184,15 +184,16 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -206,6 +207,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -220,15 +223,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -251,7 +254,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_HAS_RAPIDIO is not set # @@ -318,6 +321,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,11 +342,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -469,18 +472,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -583,6 +585,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -603,6 +608,7 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set # CONFIG_FS_ENET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set @@ -625,18 +631,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -715,12 +725,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y @@ -900,6 +904,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -936,6 +951,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -952,6 +973,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -961,6 +983,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -972,12 +995,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1007,6 +1031,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1052,6 +1077,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1084,7 +1110,6 @@ CONFIG_PARTITION_ADVANCED=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1116,13 +1141,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1133,12 +1160,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1210,6 +1239,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 312d7afbbe44..07ccaf89f379 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc5 -# Wed Jun 11 12:06:53 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:30 2008 # # CONFIG_PPC64 is not set @@ -15,6 +15,7 @@ CONFIG_6xx=y # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y @@ -23,7 +24,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -33,6 +34,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_LOCKBREAK=y @@ -92,7 +94,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -109,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -117,10 +120,13 @@ CONFIG_SLAB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -138,6 +144,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -152,6 +159,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -159,15 +167,16 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set # CONFIG_PPC_PMAC is not set -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -CONFIG_PPC_86xx=y -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +CONFIG_PPC_86xx=y # CONFIG_MPC8641_HPCN is not set # CONFIG_SBC8641D is not set # CONFIG_MPC8610_HPCD is not set @@ -184,7 +193,10 @@ CONFIG_MPIC=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -199,17 +211,20 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_300 is not set CONFIG_HZ_1000=y CONFIG_HZ=1000 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y # CONFIG_PREEMPT_RCU is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_KEXEC is not set CONFIG_IRQ_ALL_CPUS=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y @@ -219,17 +234,19 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" # CONFIG_PM is not set CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -242,6 +259,7 @@ CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_FSL_SOC=y CONFIG_FSL_PCI=y +CONFIG_PPC_PCI_CHOICE=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y @@ -250,7 +268,7 @@ CONFIG_PCIEAER=y # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set CONFIG_PCI_DEBUG=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -270,10 +288,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -287,6 +301,7 @@ CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y @@ -325,7 +340,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -362,8 +376,8 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set @@ -372,37 +386,39 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set # CONFIG_NETFILTER_XT_MATCH_MAC is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m # CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -411,6 +427,7 @@ CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_ECN=m # CONFIG_IP_NF_TARGET_TTL is not set CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m @@ -420,24 +437,21 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -# CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_MH is not set -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m # CONFIG_IP6_NF_TARGET_REJECT is not set CONFIG_IP6_NF_MANGLE=m # CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# +# CONFIG_IP6_NF_SECURITY is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=m @@ -456,8 +470,11 @@ CONFIG_ATM_LANE=m CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set @@ -477,7 +494,7 @@ CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m -# CONFIG_NET_SCH_RR is not set +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -515,12 +532,11 @@ CONFIG_NET_PKTGEN=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -646,12 +662,14 @@ CONFIG_BLK_DEV_RAM_SIZE=131072 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -731,6 +749,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y @@ -798,12 +817,15 @@ CONFIG_SATA_SIL=y # # IEEE 1394 (FireWire) support # + +# +# Enable only one of the two stacks, unless you know what you are doing +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set CONFIG_DUMMY=m CONFIG_BONDING=m # CONFIG_MACVLAN is not set @@ -816,7 +838,7 @@ CONFIG_PHYLIB=y # # MII PHY device drivers # -CONFIG_MARVELL_PHY=y +# CONFIG_MARVELL_PHY is not set # CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_LXT_PHY is not set @@ -840,14 +862,17 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set # CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_NS83820 is not set @@ -861,9 +886,11 @@ CONFIG_NETDEV_1000=y # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set CONFIG_GIANFAR=y -# CONFIG_GFAR_NAPI is not set +# CONFIG_MV643XX_ETH is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -895,7 +922,7 @@ CONFIG_ATM_DRIVERS=y # CONFIG_ATM_AMBASSADOR is not set # CONFIG_ATM_HORIZON is not set # CONFIG_ATM_IA is not set -# CONFIG_ATM_FORE200E_MAYBE is not set +# CONFIG_ATM_FORE200E is not set # CONFIG_ATM_HE is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -928,7 +955,7 @@ CONFIG_NET_POLL_CONTROLLER=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -962,6 +989,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set @@ -1000,43 +1028,64 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# PC SMBus host controller drivers +# # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_MPC=y # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_MPC=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # CONFIG_DS1682=y +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -1045,10 +1094,13 @@ CONFIG_DS1682=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -1102,6 +1154,7 @@ CONFIG_SENSORS_LM92=y # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -1109,6 +1162,8 @@ CONFIG_WATCHDOG=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_8xxx_WDT is not set # # PCI-based Watchdog Cards @@ -1130,8 +1185,21 @@ CONFIG_SSB_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1171,10 +1239,6 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y @@ -1185,9 +1249,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1205,6 +1296,9 @@ CONFIG_USB=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1225,6 +1319,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1232,6 +1328,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1261,7 +1358,6 @@ CONFIG_USB_STORAGE=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -1274,7 +1370,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1291,8 +1387,10 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_ATM is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1325,6 +1423,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set # # SPI RTC drivers @@ -1334,12 +1433,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1348,6 +1450,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1361,12 +1464,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1399,6 +1503,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1419,6 +1524,7 @@ CONFIG_TMPFS=y # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -1429,14 +1535,14 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1502,9 +1608,9 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -1531,6 +1637,8 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -1547,20 +1655,42 @@ CONFIG_SCHED_DEBUG=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -CONFIG_DEBUGGER=y +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set +# CONFIG_BOOTX_TEXT is not set # CONFIG_PPC_EARLY_DEBUG is not set # @@ -1568,9 +1698,9 @@ CONFIG_DEBUGGER=y # # CONFIG_KEYS is not set CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y # CONFIG_SECURITY_NETWORK_XFRM is not set -CONFIG_SECURITY_CAPABILITIES=y # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_SECURITY_ROOTPLUG is not set CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 @@ -1579,10 +1709,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m @@ -1621,6 +1753,10 @@ CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m @@ -1652,6 +1788,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig index c98c6ee44492..72854a10dfa1 100644 --- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig +++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:10 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:28 2008 # # CONFIG_PPC64 is not set @@ -15,6 +15,7 @@ CONFIG_6xx=y # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y @@ -22,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -52,8 +53,6 @@ CONFIG_PPC_UDBG_16550=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -99,7 +98,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -109,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +123,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -159,6 +155,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -166,10 +163,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -179,26 +176,24 @@ CONFIG_PPC_86xx=y # CONFIG_MPC8641_HPCN is not set # CONFIG_SBC8641D is not set CONFIG_MPC8610_HPCD=y +# CONFIG_GEF_SBC610 is not set CONFIG_MPC8610=y # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_FSL_ULI1575=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -218,6 +213,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -232,15 +229,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=12 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -252,7 +249,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -267,7 +263,7 @@ CONFIG_PCIEAER=y # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set CONFIG_PCI_DEBUG=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -353,6 +349,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -373,11 +370,10 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -493,7 +489,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -519,7 +514,54 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -# CONFIG_BLK_DEV_IDE is not set + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_PLATFORM is not set + +# +# PCI IDE chipsets support +# +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_IDEDMA is not set # # SCSI device support @@ -595,8 +637,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -685,8 +725,6 @@ CONFIG_DUMMY=y # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y # CONFIG_MII is not set -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -703,8 +741,12 @@ CONFIG_ULI526X=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -796,13 +838,10 @@ CONFIG_SERIAL_8250_RSA=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set @@ -838,12 +877,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -907,6 +940,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -934,6 +978,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -956,9 +1001,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_OF is not set -# CONFIG_FB_CONTROL is not set -# CONFIG_FB_PLATINUM is not set -# CONFIG_FB_VALKYRIE is not set # CONFIG_FB_CT65550 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set @@ -973,6 +1015,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -985,6 +1028,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_FSL_DIU=y # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1001,6 +1045,7 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE is not set # CONFIG_LOGO is not set CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1082,11 +1127,10 @@ CONFIG_SND_PCI=y # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set CONFIG_SND_PPC=y -# CONFIG_SND_POWERMAC is not set -# CONFIG_SND_AOA is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_MPC8610=y CONFIG_SND_SOC_MPC8610_HPCD=y +# CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_CS4270=y CONFIG_SND_SOC_CS4270_VD33_ERRATA=y # CONFIG_SOUND_PRIME is not set @@ -1094,6 +1138,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1110,6 +1160,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1155,12 +1206,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1169,6 +1223,7 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1180,12 +1235,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -1214,6 +1270,7 @@ CONFIG_FS_MBCACHE=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1254,6 +1311,7 @@ CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1330,7 +1388,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1383,15 +1440,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1400,6 +1465,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1411,12 +1477,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1489,6 +1557,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig index 444ddf98436d..41220ece603d 100644 --- a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig +++ b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:11 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:29 2008 # # CONFIG_PPC64 is not set @@ -15,6 +15,7 @@ CONFIG_6xx=y # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y @@ -23,7 +24,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -100,7 +101,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -124,10 +126,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -161,6 +160,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -168,10 +168,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -181,25 +181,23 @@ CONFIG_PPC_86xx=y CONFIG_MPC8641_HPCN=y # CONFIG_SBC8641D is not set # CONFIG_MPC8610_HPCD is not set +# CONFIG_GEF_SBC610 is not set CONFIG_MPC8641=y -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_FSL_ULI1575=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -219,9 +217,10 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m # CONFIG_IOMMU_HELPER is not set -# CONFIG_HOTPLUG_CPU is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y @@ -235,15 +234,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -255,7 +254,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -268,7 +266,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -370,6 +368,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -390,12 +389,11 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -425,7 +423,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -528,8 +525,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -634,8 +629,6 @@ CONFIG_VITESSE_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -646,8 +639,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -670,18 +667,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -716,7 +717,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -781,14 +782,11 @@ CONFIG_SERIAL_8250_RSA=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set CONFIG_NVRAM=y @@ -824,12 +822,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -894,6 +886,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -934,7 +937,6 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_USB is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_CINERGYT2 is not set # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -951,6 +953,11 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # CONFIG_DVB_PLUTO2 is not set +# +# Supported SDMC DM1105 Adapters +# +# CONFIG_DVB_DM1105 is not set + # # Supported DVB Frontends # @@ -967,6 +974,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_CX24123 is not set # CONFIG_DVB_MT312 is not set # CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set # CONFIG_DVB_STV0299 is not set # CONFIG_DVB_TDA8083 is not set # CONFIG_DVB_TDA10086 is not set @@ -974,6 +983,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TDA826X is not set # CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set # # DVB-T (terrestrial) frontends @@ -1026,6 +1037,13 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_LNBP21 is not set # CONFIG_DVB_ISL6405 is not set # CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -1051,6 +1069,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1135,8 +1154,6 @@ CONFIG_SND_INTEL8X0=y # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set CONFIG_SND_PPC=y -# CONFIG_SND_POWERMAC is not set -# CONFIG_SND_AOA is not set CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set # CONFIG_SND_USB_USX2Y is not set @@ -1153,9 +1170,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1174,6 +1218,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1197,6 +1243,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1204,6 +1252,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1225,7 +1274,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1246,6 +1294,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1263,7 +1312,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1309,12 +1360,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1323,6 +1377,7 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1334,12 +1389,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1377,6 +1433,7 @@ CONFIG_NTFS_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1421,6 +1478,7 @@ CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1496,7 +1554,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1550,15 +1607,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1567,6 +1632,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1578,15 +1644,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1659,6 +1729,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/86xx/sbc8641d_defconfig b/arch/powerpc/configs/86xx/sbc8641d_defconfig index d900f8f376cf..a4342862f6ef 100644 --- a/arch/powerpc/configs/86xx/sbc8641d_defconfig +++ b/arch/powerpc/configs/86xx/sbc8641d_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:15 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:40:26 2008 # # CONFIG_PPC64 is not set @@ -15,6 +15,7 @@ CONFIG_6xx=y # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y @@ -23,7 +24,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -100,7 +101,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -123,10 +125,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,6 +159,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -167,10 +167,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -180,25 +180,23 @@ CONFIG_PPC_86xx=y # CONFIG_MPC8641_HPCN is not set CONFIG_SBC8641D=y # CONFIG_MPC8610_HPCD is not set +# CONFIG_GEF_SBC610 is not set CONFIG_MPC8641=y -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -219,9 +217,10 @@ CONFIG_SCHED_HRTICK=y CONFIG_PREEMPT=y # CONFIG_PREEMPT_RCU is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m # CONFIG_IOMMU_HELPER is not set -# CONFIG_HOTPLUG_CPU is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y @@ -235,15 +234,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -255,7 +254,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -270,7 +268,7 @@ CONFIG_PCIEAER=y # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -341,7 +339,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -378,8 +375,8 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set @@ -388,37 +385,39 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set # CONFIG_NETFILTER_XT_MATCH_MAC is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m # CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -437,25 +436,21 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -# CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_MH is not set -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m # CONFIG_IP6_NF_TARGET_REJECT is not set CONFIG_IP6_NF_MANGLE=m # CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_RAW=m # CONFIG_IP6_NF_SECURITY is not set - -# -# Bridge: Netfilter Configuration -# # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=m @@ -476,6 +471,7 @@ CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set CONFIG_STP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set @@ -497,6 +493,7 @@ CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -534,12 +531,11 @@ CONFIG_NET_PKTGEN=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -649,7 +645,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -686,6 +681,7 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -742,8 +738,6 @@ CONFIG_BROADCOM_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -754,8 +748,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -778,6 +776,7 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -890,14 +889,11 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m # CONFIG_NVRAM is not set @@ -934,12 +930,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -997,7 +987,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -1052,7 +1041,6 @@ CONFIG_WATCHDOG=y CONFIG_SOFT_WATCHDOG=m # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -1073,6 +1061,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1116,6 +1115,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1132,6 +1137,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1141,6 +1147,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1154,9 +1161,11 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set @@ -1166,12 +1175,14 @@ CONFIG_REISERFS_FS_POSIX_ACL=y # CONFIG_REISERFS_FS_SECURITY is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set CONFIG_OCFS2_FS=m CONFIG_OCFS2_FS_O2CB=m CONFIG_OCFS2_FS_STATS=y CONFIG_OCFS2_DEBUG_MASKLOG=y # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1199,6 +1210,7 @@ CONFIG_AUTOFS4_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1237,6 +1249,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1257,7 +1270,6 @@ CONFIG_CIFS_POSIX=y # Partition Types # # CONFIG_PARTITION_ADVANCED is not set -CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" @@ -1305,7 +1317,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1358,16 +1369,24 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1376,6 +1395,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -1388,6 +1408,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y # CONFIG_SECURITY_NETWORK_XFRM is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set @@ -1397,10 +1418,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m @@ -1474,6 +1497,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs/adder875_defconfig index 63cd51fbb4b9..024f279af90a 100644 --- a/arch/powerpc/configs/adder875_defconfig +++ b/arch/powerpc/configs/adder875_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:00 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:32 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_8xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -102,6 +102,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -115,10 +116,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y # CONFIG_TINY_SHMEM is not set @@ -144,6 +142,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -156,6 +155,7 @@ CONFIG_CPM1=y # CONFIG_MPC885ADS is not set # CONFIG_PPC_EP88XC is not set CONFIG_PPC_ADDER875=y +# CONFIG_PPC_MGSUVD is not set # # MPC8xx CPM Options @@ -184,6 +184,7 @@ CONFIG_NO_UCODE_PATCH=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -191,7 +192,6 @@ CONFIG_CPM=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -205,6 +205,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_8XX_MINIMAL_FPEMU is not set @@ -220,15 +222,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -310,6 +312,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -330,11 +333,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -476,6 +478,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set @@ -534,6 +539,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set @@ -573,12 +579,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set @@ -613,6 +613,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -652,16 +660,18 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -690,6 +700,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -727,6 +738,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -762,7 +774,6 @@ CONFIG_MSDOS_PARTITION=y # # Library routines # -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -812,14 +823,22 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -828,6 +847,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -839,6 +859,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig index c16521ffb477..5078594cd1f5 100644 --- a/arch/powerpc/configs/c2k_defconfig +++ b/arch/powerpc/configs/c2k_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:02 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:34 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_NOT_COHERENT_CACHE=y CONFIG_CHECK_CACHE_COHERENCY=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -114,7 +114,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -130,10 +132,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -166,6 +164,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -227,7 +226,6 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=m # Kernel options # CONFIG_HIGHMEM=y -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -241,6 +239,8 @@ CONFIG_HZ=250 CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -255,15 +255,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -285,7 +285,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_PCI_MSI=y -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set CONFIG_HOTPLUG_PCI=y @@ -361,36 +361,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y # CONFIG_IPV6_ROUTER_PREF is not set @@ -427,8 +397,8 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set # CONFIG_NETFILTER_XT_TARGET_SECMARK is not set @@ -438,37 +408,70 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set # CONFIG_NETFILTER_XT_MATCH_MAC is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m # CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -487,25 +490,21 @@ CONFIG_IP_NF_ARP_MANGLE=m # # CONFIG_IP6_NF_QUEUE is not set CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -# CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_MH is not set -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m # CONFIG_IP6_NF_TARGET_REJECT is not set CONFIG_IP6_NF_MANGLE=m # CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_RAW=m # CONFIG_IP6_NF_SECURITY is not set - -# -# Bridge: Netfilter Configuration -# CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -545,6 +544,7 @@ CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set CONFIG_STP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set @@ -566,6 +566,7 @@ CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -627,12 +628,11 @@ CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_MAC80211 is not set @@ -910,8 +910,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -933,6 +937,7 @@ CONFIG_MV643XX_ETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -998,6 +1003,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set CONFIG_INPUT_UINPUT=m # @@ -1226,6 +1232,16 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1283,6 +1299,8 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1305,6 +1323,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # Enable Host or Gadget support to see Inventra options @@ -1316,6 +1336,7 @@ CONFIG_USB_UHCI_HCD=m CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1337,7 +1358,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1413,6 +1433,7 @@ CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_EMI62=m # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m @@ -1430,12 +1451,14 @@ CONFIG_USB_LED=m # CONFIG_USB_IOWARRIOR is not set CONFIG_USB_TEST=m # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m # CONFIG_USB_CXACRU is not set # CONFIG_USB_UEAGLEATM is not set # CONFIG_USB_XUSBATM is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1464,8 +1487,8 @@ CONFIG_DMADEVICES=y # # DMA Devices # -# CONFIG_FSL_DMA is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1475,12 +1498,13 @@ CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=m CONFIG_FS_MBCACHE=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1519,6 +1543,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1570,12 +1595,14 @@ CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_XPRT_RDMA=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y # CONFIG_CIFS_DEBUG2 is not set @@ -1651,7 +1678,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=m @@ -1707,17 +1733,25 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1726,6 +1760,7 @@ CONFIG_DEBUG_STACK_USAGE=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1738,6 +1773,7 @@ CONFIG_BOOTX_TEXT=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y # CONFIG_SECURITY_NETWORK_XFRM is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set @@ -1756,10 +1792,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m @@ -1833,6 +1871,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/chrp32_defconfig b/arch/powerpc/configs/chrp32_defconfig index 2e0ef8c18227..63b3c2372ce8 100644 --- a/arch/powerpc/configs/chrp32_defconfig +++ b/arch/powerpc/configs/chrp32_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:12:40 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:35:37 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -108,7 +108,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -122,10 +124,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -159,6 +158,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -212,6 +212,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -227,15 +229,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_MIGRATION is not set # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -310,7 +312,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -334,10 +335,12 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set # CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_IPTABLES=m @@ -361,6 +364,7 @@ CONFIG_NF_NAT_SIP=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -381,14 +385,8 @@ CONFIG_NF_NAT_SIP=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -443,19 +441,18 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -616,7 +613,23 @@ CONFIG_NETDEVICES=y # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_HAPPYMEAL is not set @@ -641,6 +654,9 @@ CONFIG_DE4X5=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y # CONFIG_AMD8111_ETH is not set @@ -669,6 +685,7 @@ CONFIG_8139TOO=y CONFIG_VIA_RHINE=y # CONFIG_VIA_RHINE_MMIO is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -690,18 +707,22 @@ CONFIG_MV643XX_ETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -777,6 +798,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set @@ -795,6 +817,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set CONFIG_INPUT_UINPUT=y # @@ -953,6 +976,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -980,6 +1014,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -1028,6 +1063,7 @@ CONFIG_FB_ATY_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set CONFIG_FB_3DFX=y @@ -1040,6 +1076,7 @@ CONFIG_FB_3DFX=y # CONFIG_FB_CARMINE is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_ILI9320 is not set @@ -1083,9 +1120,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1102,6 +1166,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1121,6 +1187,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1128,6 +1196,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1149,7 +1218,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1170,6 +1238,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1187,7 +1256,9 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1197,6 +1268,7 @@ CONFIG_USB_STORAGE=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1208,12 +1280,18 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set CONFIG_JBD=y +CONFIG_JBD2=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1248,6 +1326,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1349,9 +1428,8 @@ CONFIG_NLS_ISO8859_1=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y @@ -1404,15 +1482,23 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1421,6 +1507,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set CONFIG_XMON=y CONFIG_XMON_DEFAULT=y CONFIG_XMON_DISASSEMBLY=y @@ -1435,14 +1522,19 @@ CONFIG_IRQSTACKS=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_MANAGER=m # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1515,6 +1607,11 @@ CONFIG_CRYPTO_ARC4=m # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/ep8248e_defconfig b/arch/powerpc/configs/ep8248e_defconfig index cd691f770810..a6f1cff564e6 100644 --- a/arch/powerpc/configs/ep8248e_defconfig +++ b/arch/powerpc/configs/ep8248e_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:03 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:36 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -48,13 +48,11 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_PPC_OF=y CONFIG_OF=y -CONFIG_PPC_UDBG_16550=y +# CONFIG_PPC_UDBG_16550 is not set # CONFIG_GENERIC_TBSYNC is not set CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y # CONFIG_DEFAULT_UIMAGE is not set -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -93,7 +91,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -103,7 +100,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -115,10 +114,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -144,6 +140,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -151,39 +148,36 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set CONFIG_PPC_82xx=y # CONFIG_MPC8272_ADS is not set # CONFIG_PQ2FADS is not set CONFIG_EP8248E=y +# CONFIG_MGCOGE is not set # CONFIG_PQ2ADS is not set CONFIG_8260=y CONFIG_8272=y # CONFIG_PPC_83xx is not set # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -192,7 +186,6 @@ CONFIG_CPM=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -206,6 +199,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -215,15 +210,15 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -235,7 +230,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_FSL_SOC=y @@ -247,7 +241,7 @@ CONFIG_PCI_8260=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -303,7 +297,6 @@ CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_IP_VS is not set CONFIG_IPV6=y # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -330,10 +323,12 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -360,11 +355,10 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -469,7 +463,6 @@ CONFIG_OF_GPIO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -534,8 +527,6 @@ CONFIG_MDIO_BITBANG=y # CONFIG_MDIO_OF_GPIO is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -546,8 +537,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set CONFIG_FS_ENET_HAS_FCC=y @@ -570,18 +565,23 @@ CONFIG_NETDEV_1000=y # CONFIG_GIANFAR is not set # CONFIG_MV643XX_ETH is not set # CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -629,21 +629,12 @@ CONFIG_DEVKMEM=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -CONFIG_SERIAL_CPM_SCC4=y -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -692,6 +683,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -732,6 +731,7 @@ CONFIG_DAB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -741,10 +741,12 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -774,6 +776,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -874,7 +877,6 @@ CONFIG_NLS_UTF8=y # # Library routines # -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -924,15 +926,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_STACKOVERFLOW is not set @@ -940,6 +950,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set CONFIG_BDI_SWITCH=y @@ -951,14 +962,19 @@ CONFIG_BDI_SWITCH=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -1025,6 +1041,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y diff --git a/arch/powerpc/configs/ep88xc_defconfig b/arch/powerpc/configs/ep88xc_defconfig index 480225be2f39..870d28976a44 100644 --- a/arch/powerpc/configs/ep88xc_defconfig +++ b/arch/powerpc/configs/ep88xc_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:04 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:37 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_8xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -101,6 +101,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -114,10 +115,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y # CONFIG_TINY_SHMEM is not set @@ -143,6 +141,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -155,6 +154,7 @@ CONFIG_CPM1=y # CONFIG_MPC885ADS is not set CONFIG_PPC_EP88XC=y # CONFIG_PPC_ADDER875 is not set +# CONFIG_PPC_MGSUVD is not set # # MPC8xx CPM Options @@ -183,6 +183,7 @@ CONFIG_NO_UCODE_PATCH=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -204,6 +205,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set CONFIG_8XX_MINIMAL_FPEMU=y @@ -219,15 +222,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -309,6 +312,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -329,11 +333,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -475,6 +478,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set @@ -529,12 +535,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set @@ -570,6 +570,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -608,16 +616,18 @@ CONFIG_DAB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -646,6 +656,7 @@ CONFIG_DAB=y CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -683,6 +694,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -718,7 +730,6 @@ CONFIG_MSDOS_PARTITION=y # # Library routines # -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -768,14 +779,22 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -784,6 +803,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -794,6 +814,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig index cfa5d053ee5e..f85e71ccb989 100644 --- a/arch/powerpc/configs/g5_defconfig +++ b/arch/powerpc/configs/g5_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:15:06 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:36:30 2008 # CONFIG_PPC64=y @@ -21,7 +21,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_64BIT=y CONFIG_WORD_SIZE=64 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -112,7 +112,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -129,8 +131,6 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -163,6 +163,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set +CONFIG_PPC_MSI_BITMAP=y # # Platform support @@ -233,6 +235,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_IOMMU_VMERGE=y @@ -242,7 +246,6 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set CONFIG_IRQ_ALL_CPUS=y # CONFIG_NUMA is not set CONFIG_ARCH_SELECT_MEMORY_MODEL=y @@ -255,14 +258,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_MIGRATION is not set CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y +CONFIG_UNEVICTABLE_LRU=y # CONFIG_PPC_HAS_HASH_64K is not set # CONFIG_PPC_64K_PAGES is not set CONFIG_FORCE_MAX_ZONEORDER=13 @@ -292,6 +296,7 @@ CONFIG_PCI_MSI=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set +# CONFIG_RELOCATABLE is not set CONFIG_PAGE_OFFSET=0xc000000000000000 CONFIG_KERNEL_START=0xc000000000000000 CONFIG_PHYSICAL_START=0x00000000 @@ -336,7 +341,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -367,10 +371,12 @@ CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m @@ -381,6 +387,7 @@ CONFIG_IP_NF_QUEUE=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=y @@ -402,11 +409,10 @@ CONFIG_LLC=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -463,19 +469,18 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -658,6 +663,7 @@ CONFIG_SATA_SVW=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -744,14 +750,17 @@ CONFIG_SUNGEM=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y CONFIG_ACENIC=y CONFIG_ACENIC_OMIT_TIGON_I=y # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -768,18 +777,22 @@ CONFIG_TIGON3=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set CONFIG_TR=y CONFIG_IBMOL=y @@ -804,6 +817,7 @@ CONFIG_USB_USBNET=m # CONFIG_USB_NET_AX8817X is not set CONFIG_USB_NET_CDCETHER=m # CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set # CONFIG_USB_NET_GL620A is not set # CONFIG_USB_NET_NET1080 is not set # CONFIG_USB_NET_PLUSB is not set @@ -1015,6 +1029,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1044,6 +1069,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -1085,6 +1111,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -1096,6 +1123,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_CARMINE is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_ILI9320 is not set @@ -1124,6 +1152,7 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1234,15 +1263,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -CONFIG_HID_FF=y CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y CONFIG_LOGITECH_FF=y # CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y # CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y CONFIG_THRUSTMASTER_FF=y # CONFIG_ZEROPLUS_FF is not set -CONFIG_USB_HIDDEV=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1259,6 +1309,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1281,6 +1333,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1288,6 +1342,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_ACM=m CONFIG_USB_PRINTER=y # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1309,7 +1364,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1385,6 +1439,7 @@ CONFIG_USB_SERIAL_OMNINET=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1402,7 +1457,9 @@ CONFIG_USB_APPLEDISPLAY=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1412,6 +1469,7 @@ CONFIG_USB_APPLEDISPLAY=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1421,14 +1479,20 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_FS_XIP=y CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y # CONFIG_REISERFS_CHECK is not set @@ -1438,6 +1502,7 @@ CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set CONFIG_XFS_POSIX_ACL=y @@ -1478,6 +1543,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1521,6 +1587,7 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1601,9 +1668,8 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y @@ -1657,19 +1723,26 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1678,6 +1751,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set CONFIG_IRQSTACKS=y # CONFIG_VIRQ_DEBUG is not set @@ -1689,16 +1763,19 @@ CONFIG_BOOTX_TEXT=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m @@ -1772,6 +1849,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/iseries_defconfig b/arch/powerpc/configs/iseries_defconfig index 2c3f13577f4b..f925c555508e 100644 --- a/arch/powerpc/configs/iseries_defconfig +++ b/arch/powerpc/configs/iseries_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:15:49 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:36:38 2008 # CONFIG_PPC64=y @@ -21,7 +21,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_64BIT=y CONFIG_WORD_SIZE=64 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -111,7 +111,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -127,8 +129,6 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -161,6 +161,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -219,6 +220,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_IOMMU_VMERGE=y CONFIG_IOMMU_HELPER=y @@ -226,7 +229,6 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_KEXEC is not set -# CONFIG_CRASH_DUMP is not set CONFIG_IRQ_ALL_CPUS=y # CONFIG_NUMA is not set CONFIG_ARCH_SELECT_MEMORY_MODEL=y @@ -239,14 +241,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_MIGRATION is not set CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y +CONFIG_UNEVICTABLE_LRU=y # CONFIG_PPC_HAS_HASH_64K is not set # CONFIG_PPC_64K_PAGES is not set CONFIG_FORCE_MAX_ZONEORDER=13 @@ -275,6 +278,7 @@ CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set +# CONFIG_RELOCATABLE is not set CONFIG_PAGE_OFFSET=0xc000000000000000 CONFIG_KERNEL_START=0xc000000000000000 CONFIG_PHYSICAL_START=0x00000000 @@ -319,7 +323,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -349,15 +352,17 @@ CONFIG_NF_CONNTRACK_IRC=m # CONFIG_NF_CONNTRACK_SIP is not set CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m # CONFIG_NETFILTER_XT_TARGET_TRACE is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -369,40 +374,44 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set CONFIG_NETFILTER_XT_MATCH_DSCP=m # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_HELPER is not set CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set CONFIG_NETFILTER_XT_MATCH_OWNER=m # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set # CONFIG_NETFILTER_XT_MATCH_STATE is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m # CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -410,8 +419,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m # CONFIG_NF_NAT_SNMP_BASIC is not set CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m @@ -421,9 +430,9 @@ CONFIG_NF_NAT_TFTP=m # CONFIG_NF_NAT_H323 is not set # CONFIG_NF_NAT_SIP is not set CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -438,6 +447,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=y @@ -460,14 +470,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -597,6 +601,7 @@ CONFIG_SCSI_IBMVSCSI=m # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -647,6 +652,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y # CONFIG_AMD8111_ETH is not set @@ -667,12 +675,12 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y CONFIG_ACENIC=m # CONFIG_ACENIC_OMIT_TIGON_I is not set # CONFIG_DL2K is not set CONFIG_E1000=m -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -689,18 +697,22 @@ CONFIG_E1000=m # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set CONFIG_TR=y CONFIG_IBMOL=y @@ -837,6 +849,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -877,6 +897,7 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -886,6 +907,7 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -895,14 +917,20 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_FS_XIP=y CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y # CONFIG_REISERFS_CHECK is not set @@ -916,6 +944,7 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set CONFIG_XFS_POSIX_ACL=y @@ -958,6 +987,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y @@ -1001,6 +1031,7 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set @@ -1067,9 +1098,8 @@ CONFIG_DLM=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y @@ -1127,19 +1157,26 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1148,6 +1185,7 @@ CONFIG_DEBUG_STACK_USAGE=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set CONFIG_IRQSTACKS=y # CONFIG_VIRQ_DEBUG is not set @@ -1159,16 +1197,19 @@ CONFIG_IRQSTACKS=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m @@ -1242,6 +1283,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/linkstation_defconfig b/arch/powerpc/configs/linkstation_defconfig index 6fc4c2127757..54fa62481373 100644 --- a/arch/powerpc/configs/linkstation_defconfig +++ b/arch/powerpc/configs/linkstation_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:05 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:38 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -90,7 +90,7 @@ CONFIG_NAMESPACES=y # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_SYSCTL_SYSCALL=y @@ -101,7 +101,7 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y +# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -124,10 +126,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,6 +158,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -199,6 +198,7 @@ CONFIG_MPIC=y # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set # @@ -219,6 +219,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -233,15 +235,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -263,7 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -324,7 +326,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -354,13 +355,14 @@ CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set @@ -374,19 +376,21 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # CONFIG_NETFILTER_XT_MATCH_HELPER is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set CONFIG_NETFILTER_XT_MATCH_MAC=m # CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set CONFIG_NETFILTER_XT_MATCH_STATE=m # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set @@ -394,20 +398,20 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -# CONFIG_IP_NF_MATCH_ECN is not set +CONFIG_IP_NF_MATCH_ADDRTYPE=m # CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set # CONFIG_IP_NF_MATCH_TTL is not set -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m # CONFIG_IP_NF_TARGET_LOG is not set @@ -415,8 +419,8 @@ CONFIG_IP_NF_TARGET_REJECT=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m # CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=m # CONFIG_NF_NAT_SNMP_BASIC is not set CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_SCTP=m @@ -428,9 +432,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -440,6 +444,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -460,11 +465,10 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_MAC80211 is not set @@ -772,7 +776,7 @@ CONFIG_TUN=m # CONFIG_ARCNET is not set # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -792,8 +796,12 @@ CONFIG_TULIP_MMIO=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -816,18 +824,22 @@ CONFIG_R8169=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -892,6 +904,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set CONFIG_INPUT_UINPUT=m # @@ -934,7 +947,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set -CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -1091,6 +1104,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1138,12 +1162,18 @@ CONFIG_HID=m # USB Input Devices # # CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1160,6 +1190,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1183,6 +1215,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1190,6 +1224,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set CONFIG_USB_PRINTER=m # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1211,7 +1246,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1275,6 +1309,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1292,7 +1327,9 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1338,12 +1375,15 @@ CONFIG_RTC_DRV_RS5C372=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1352,6 +1392,7 @@ CONFIG_RTC_DRV_RS5C372=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1363,12 +1404,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -1410,6 +1452,7 @@ CONFIG_NTFS_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1453,6 +1496,7 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1517,7 +1561,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1573,15 +1616,23 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1590,6 +1641,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -1601,15 +1653,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1683,6 +1739,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/maple_defconfig b/arch/powerpc/configs/maple_defconfig index 1a3b6423222b..045f1b008ce5 100644 --- a/arch/powerpc/configs/maple_defconfig +++ b/arch/powerpc/configs/maple_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:18:58 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:36:45 2008 # CONFIG_PPC64=y @@ -20,7 +20,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_64BIT=y CONFIG_WORD_SIZE=64 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -107,7 +107,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -125,8 +127,6 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -159,6 +159,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set +CONFIG_PPC_MSI_BITMAP=y # # Platform support @@ -213,6 +215,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_IOMMU_VMERGE=y @@ -221,7 +225,6 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set CONFIG_IRQ_ALL_CPUS=y # CONFIG_NUMA is not set CONFIG_ARCH_SELECT_MEMORY_MODEL=y @@ -234,14 +237,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_MIGRATION is not set CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y +CONFIG_UNEVICTABLE_LRU=y # CONFIG_PPC_HAS_HASH_64K is not set # CONFIG_PPC_64K_PAGES is not set CONFIG_FORCE_MAX_ZONEORDER=13 @@ -265,11 +269,12 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_PCI_MSI=y -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set +# CONFIG_RELOCATABLE is not set CONFIG_PAGE_OFFSET=0xc000000000000000 CONFIG_KERNEL_START=0xc000000000000000 CONFIG_PHYSICAL_START=0x00000000 @@ -323,6 +328,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -344,14 +350,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -402,19 +402,18 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set CONFIG_IDE_TASK_IOCTL=y CONFIG_IDE_PROC_FS=y @@ -644,6 +643,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set CONFIG_AMD8111_ETH=y @@ -664,11 +666,11 @@ CONFIG_AMD8111_ETH=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -685,18 +687,22 @@ CONFIG_TIGON3=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -895,6 +901,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -942,9 +959,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -961,6 +1005,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -980,6 +1026,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -987,6 +1035,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1070,6 +1119,7 @@ CONFIG_USB_SERIAL_TI=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1087,7 +1137,9 @@ CONFIG_USB_SERIAL_TI=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1097,6 +1149,7 @@ CONFIG_USB_SERIAL_TI=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1104,15 +1157,23 @@ CONFIG_USB_SERIAL_TI=m CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_FS_XIP=y CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set @@ -1146,6 +1207,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1185,6 +1247,7 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1260,9 +1323,8 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y @@ -1315,21 +1377,28 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y # CONFIG_SYSCTL_SYSCALL_CHECK is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1338,6 +1407,7 @@ CONFIG_DEBUG_STACK_USAGE=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set CONFIG_XMON=y CONFIG_XMON_DEFAULT=y CONFIG_XMON_DISASSEMBLY=y @@ -1352,14 +1422,19 @@ CONFIG_BOOTX_TEXT=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1432,6 +1507,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig index cc9eaba8c9c9..8d3c62324009 100644 --- a/arch/powerpc/configs/mgcoge_defconfig +++ b/arch/powerpc/configs/mgcoge_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc2 -# Thu May 22 08:18:47 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:38 2008 # # CONFIG_PPC64 is not set @@ -15,13 +15,14 @@ CONFIG_6xx=y # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_FPU=y +# CONFIG_ALTIVEC is not set CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y # CONFIG_PPC_MM_SLICES is not set # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -31,12 +32,14 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y # CONFIG_ARCH_NO_VIRT_TO_BUS is not set CONFIG_PPC=y CONFIG_EARLY_PRINTK=y @@ -45,11 +48,13 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_PPC_OF=y CONFIG_OF=y -# CONFIG_PPC_UDBG_16550 is not set +CONFIG_PPC_UDBG_16550=y # CONFIG_GENERIC_TBSYNC is not set CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y # CONFIG_DEFAULT_UIMAGE is not set +CONFIG_HIBERNATE_32=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -82,7 +87,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -90,6 +94,7 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -99,17 +104,22 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -119,6 +129,7 @@ CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -133,18 +144,21 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support # -# CONFIG_PPC_MULTIPLATFORM is not set -CONFIG_PPC_82xx=y -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +CONFIG_PPC_CHRP=y +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +CONFIG_PPC_PMAC=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +CONFIG_PPC_82xx=y # CONFIG_MPC8272_ADS is not set # CONFIG_PQ2FADS is not set # CONFIG_EP8248E is not set @@ -152,19 +166,28 @@ CONFIG_MGCOGE=y # CONFIG_PQ2ADS is not set CONFIG_8260=y CONFIG_8272=y +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set +# CONFIG_EMBEDDED6xx is not set +CONFIG_PPC_NATIVE=y +# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set -# CONFIG_MPIC is not set +CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set -# CONFIG_PPC_I8259 is not set -# CONFIG_PPC_RTAS is not set +CONFIG_PPC_I8259=y +CONFIG_PPC_RTAS=y +# CONFIG_RTAS_ERROR_LOGGING is not set +CONFIG_RTAS_PROC=y # CONFIG_MMIO_NVRAM is not set -# CONFIG_PPC_MPC106 is not set +CONFIG_PPC_MPC106=y # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_PPC601_SYNC_FIX is not set +# CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y -CONFIG_PPC_CPM_NEW_BINDING=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -172,7 +195,6 @@ CONFIG_CPM=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -186,6 +208,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -195,17 +219,19 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" # CONFIG_PM is not set # CONFIG_SECCOMP is not set CONFIG_ISA_DMA_API=y @@ -213,13 +239,22 @@ CONFIG_ISA_DMA_API=y # # Bus options # +# CONFIG_ISA is not set CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y CONFIG_FSL_SOC=y -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_8260=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set # @@ -235,10 +270,6 @@ CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 - -# -# Networking -# CONFIG_NET=y # @@ -276,7 +307,6 @@ CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -290,10 +320,12 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -314,11 +346,10 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -398,11 +429,13 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # +# CONFIG_MTD_PMC551 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -422,19 +455,26 @@ CONFIG_MTD_PHYSMAP_OF=y # # CONFIG_MTD_UBI is not set CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set +# CONFIG_MAC_FLOPPY is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -448,14 +488,25 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# A new alternative FireWire stack is available with EXPERIMENTAL=y +# +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set +# CONFIG_ARCNET is not set CONFIG_PHYLIB=y # @@ -475,17 +526,31 @@ CONFIG_FIXED_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_MACE is not set +# CONFIG_BMAC is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_FS_ENET=y CONFIG_FS_ENET_HAS_SCC=y # CONFIG_FS_ENET_HAS_FCC is not set # CONFIG_FS_ENET_MDIO_FCC is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set # # Wireless LAN @@ -494,6 +559,7 @@ CONFIG_FS_ENET_HAS_SCC=y # CONFIG_WLAN_80211 is not set # CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set +# CONFIG_FDDI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NETPOLL is not set @@ -530,29 +596,47 @@ CONFIG_DEVKMEM=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_PMACZILOG is not set CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_BRIQ_PANEL is not set +# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set # CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y # CONFIG_I2C is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set # @@ -564,8 +648,18 @@ CONFIG_SSB_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -586,6 +680,8 @@ CONFIG_SSB_POSSIBLE=y # # Graphics support # +# CONFIG_AGP is not set +# CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set @@ -595,19 +691,17 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -617,11 +711,13 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -651,6 +747,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -673,6 +770,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -682,8 +780,8 @@ CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y @@ -759,9 +857,9 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -804,20 +902,41 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set -# CONFIG_KGDB_CONSOLE is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set CONFIG_BDI_SWITCH=y +# CONFIG_BOOTX_TEXT is not set # CONFIG_PPC_EARLY_DEBUG is not set # @@ -825,13 +944,19 @@ CONFIG_BDI_SWITCH=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -865,6 +990,10 @@ CONFIG_CRYPTO_PCBC=y # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -894,7 +1023,12 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set -# CONFIG_PPC_CLOCK is not set +CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/mgsuvd_defconfig b/arch/powerpc/configs/mgsuvd_defconfig index 3cd6ce4be827..fbaa67f7b0ef 100644 --- a/arch/powerpc/configs/mgsuvd_defconfig +++ b/arch/powerpc/configs/mgsuvd_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc2 -# Wed May 21 13:30:33 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:39 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_8xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -29,6 +29,7 @@ CONFIG_GENERIC_HARDIRQS=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y @@ -99,6 +100,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -106,10 +108,13 @@ CONFIG_SLAB=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -120,6 +125,7 @@ CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -134,12 +140,11 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support # -# CONFIG_PPC_MPC512x is not set -# CONFIG_PPC_MPC5121 is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set CONFIG_CPM1=y @@ -158,6 +163,7 @@ CONFIG_PPC_MGSUVD=y # Generic MPC8xx Options # CONFIG_8xx_COPYBACK=y +# CONFIG_8xx_GPIO is not set CONFIG_8xx_CPU6=y CONFIG_8xx_CPU15=y # CONFIG_NO_UCODE_PATCH is not set @@ -177,7 +183,7 @@ CONFIG_UCODE_PATCH=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -CONFIG_PPC_CPM_NEW_BINDING=y +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -185,7 +191,6 @@ CONFIG_CPM=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -199,6 +204,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -213,17 +220,19 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" # CONFIG_PM is not set # CONFIG_SECCOMP is not set CONFIG_ISA_DMA_API=y @@ -255,10 +264,6 @@ CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0x80000000 CONFIG_CONSISTENT_START=0xfd000000 CONFIG_CONSISTENT_SIZE=0x00200000 - -# -# Networking -# CONFIG_NET=y # @@ -309,6 +314,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -329,11 +335,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -447,6 +452,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -462,7 +468,6 @@ CONFIG_HAVE_IDE=y # CONFIG_MD is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -492,6 +497,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FS_ENET=y CONFIG_FS_ENET_HAS_SCC=y @@ -546,12 +554,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -# CONFIG_SERIAL_CPM_SMC2 is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set @@ -564,10 +566,13 @@ CONFIG_GEN_RTC=y # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set # @@ -579,8 +584,18 @@ CONFIG_SSB_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -610,10 +625,6 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set @@ -624,6 +635,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -637,13 +649,14 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -673,6 +686,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -703,6 +717,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -713,13 +728,13 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -756,9 +771,9 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -783,7 +798,17 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set # CONFIG_PPC_EARLY_DEBUG is not set @@ -793,12 +818,14 @@ CONFIG_DEBUG_FS=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -836,6 +863,10 @@ CONFIG_CRYPTO=y # CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -866,7 +897,13 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_PPC_CLOCK is not set +# CONFIG_CRYPTO_DEV_TALITOS is not set +CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/mpc5200_defconfig b/arch/powerpc/configs/mpc5200_defconfig index 740c9f2b7de6..15c5604d0b26 100644 --- a/arch/powerpc/configs/mpc5200_defconfig +++ b/arch/powerpc/configs/mpc5200_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.24-rc6 -# Fri Jan 18 14:19:54 2008 +# Linux kernel version: 2.6.28-rc4 +# Thu Nov 13 02:09:07 2008 # # CONFIG_PPC64 is not set @@ -22,14 +22,18 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y @@ -47,7 +51,8 @@ CONFIG_OF=y # CONFIG_GENERIC_TBSYNC is not set CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y -# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_DEFAULT_UIMAGE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -66,17 +71,15 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -88,32 +91,49 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y # CONFIG_EPOLL is not set CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -127,29 +147,34 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # Platform support # CONFIG_PPC_MULTIPLATFORM=y -# CONFIG_PPC_82xx is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set CONFIG_PPC_MPC52xx=y -CONFIG_PPC_MPC5200=y -CONFIG_PPC_MPC5200_BUGFIX=y CONFIG_PPC_MPC5200_SIMPLE=y CONFIG_PPC_EFIKA=y CONFIG_PPC_LITE5200=y +CONFIG_PPC_MPC5200_BUGFIX=y +# CONFIG_PPC_MPC5200_GPIO is not set # CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_82xx is not set # CONFIG_PQ2ADS is not set +# CONFIG_PPC_83xx is not set +# CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set CONFIG_PPC_NATIVE=y # CONFIG_UDBG_RTAS_CONSOLE is not set +# CONFIG_IPIC is not set # CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set # CONFIG_PPC_I8259 is not set @@ -163,7 +188,6 @@ CONFIG_RTAS_PROC=y # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set # CONFIG_TAU is not set -# CONFIG_CPM2 is not set # CONFIG_FSL_ULI1575 is not set CONFIG_PPC_BESTCOMM=y CONFIG_PPC_BESTCOMM_ATA=y @@ -183,12 +207,18 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set +# CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_KEXEC is not set CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y @@ -198,26 +228,25 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y -CONFIG_SUSPEND_UP_POSSIBLE=y CONFIG_SUSPEND=y -CONFIG_HIBERNATION_UP_POSSIBLE=y -# CONFIG_HIBERNATION is not set +CONFIG_SUSPEND_FREEZER=y CONFIG_SECCOMP=y -CONFIG_WANT_DEVICE_TREE=y -CONFIG_DEVICE_TREE="" CONFIG_ISA_DMA_API=y # @@ -226,7 +255,7 @@ CONFIG_ISA_DMA_API=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y # CONFIG_PPC_INDIRECT_PCI is not set -CONFIG_FSL_SOC=y +CONFIG_PPC_PCI_CHOICE=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y @@ -237,6 +266,7 @@ CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set # # Advanced setup @@ -246,15 +276,11 @@ CONFIG_PCI_LEGACY=y # # Default settings for advanced configuration options are used # -CONFIG_HIGHMEM_START=0xfe000000 CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 CONFIG_TASK_SIZE=0xc0000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Networking -# CONFIG_NET=y # @@ -267,6 +293,7 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -297,8 +324,6 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -306,6 +331,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -322,17 +348,12 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -357,6 +378,8 @@ CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_OF_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -428,6 +451,7 @@ CONFIG_MTD_PHYSMAP_OF=y # # CONFIG_MTD_UBI is not set CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set @@ -444,14 +468,20 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=32768 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -516,6 +546,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set @@ -528,9 +559,13 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set # CONFIG_ATA_PIIX is not set # CONFIG_SATA_MV is not set @@ -540,7 +575,6 @@ CONFIG_ATA=y # CONFIG_SATA_PROMISE is not set # CONFIG_SATA_SX4 is not set # CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIL24 is not set # CONFIG_SATA_SIS is not set # CONFIG_SATA_ULI is not set # CONFIG_SATA_VIA is not set @@ -570,6 +604,7 @@ CONFIG_PATA_MPC52xx=y # CONFIG_PATA_MPIIX is not set # CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set @@ -586,25 +621,28 @@ CONFIG_PATA_MPC52xx=y # CONFIG_PATA_WINBOND is not set CONFIG_PATA_PLATFORM=y # CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # + +# +# Enable only one of the two stacks, unless you know what you are doing +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -# CONFIG_IP1000 is not set # CONFIG_ARCNET is not set CONFIG_PHYLIB=y @@ -620,6 +658,7 @@ CONFIG_PHYLIB=y # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -634,10 +673,14 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set CONFIG_FEC_MPC52xx=y CONFIG_FEC_MPC52xx_MDIO=y +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -647,6 +690,7 @@ CONFIG_FEC_MPC52xx_MDIO=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -662,7 +706,6 @@ CONFIG_FEC_MPC52xx_MDIO=y # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -672,7 +715,30 @@ CONFIG_FEC_MPC52xx_MDIO=y # # Input device support # -# CONFIG_INPUT is not set +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Hardware I/O ports @@ -683,8 +749,14 @@ CONFIG_FEC_MPC52xx_MDIO=y # # Character devices # -# CONFIG_VT is not set +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -718,16 +790,15 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y # -# I2C Algorithms +# I2C Hardware Bus support # -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set # -# I2C Hardware Bus support +# PC SMBus host controller drivers # # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set @@ -735,52 +806,64 @@ CONFIG_I2C_CHARDEV=y # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_MPC=y # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_MPC=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + # # Miscellaneous I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_M41T00 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -788,7 +871,9 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -818,6 +903,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set @@ -827,9 +913,12 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -837,6 +926,7 @@ CONFIG_WATCHDOG=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set # CONFIG_MPC5200_WDT is not set # CONFIG_WATCHDOG_RTAS is not set @@ -850,23 +940,39 @@ CONFIG_WATCHDOG=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -874,11 +980,78 @@ CONFIG_DAB=y # Graphics support # # CONFIG_AGP is not set -# CONFIG_DRM is not set +CONFIG_DRM=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set # CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +CONFIG_FB_MACMODES=y +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_CT65550 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_CORGI is not set # # Display device support @@ -886,15 +1059,64 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m # CONFIG_DISPLAY_SUPPORT is not set # -# Sound -# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y # CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +# CONFIG_HID_APPLE is not set +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +# CONFIG_HID_CHICONY is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options @@ -903,14 +1125,20 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set -# CONFIG_USB_PERSIST is not set # CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PPC_SOC=y CONFIG_USB_OHCI_HCD_PPC_OF=y @@ -923,12 +1151,17 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -948,7 +1181,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -956,15 +1191,10 @@ CONFIG_USB_STORAGE=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -CONFIG_USB_MON=y # # USB port drivers # - -# -# USB Serial Converter support -# # CONFIG_USB_SERIAL is not set # @@ -973,7 +1203,7 @@ CONFIG_USB_MON=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -989,18 +1219,14 @@ CONFIG_USB_MON=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# - -# -# USB Gadget Support -# +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS is not set # # LED drivers @@ -1009,17 +1235,15 @@ CONFIG_LEDS_CLASS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set # CONFIG_EDAC is not set # CONFIG_RTC_CLASS is not set - -# -# Userspace I/O -# +# CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -1031,21 +1255,19 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -1072,6 +1294,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1101,8 +1324,11 @@ CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -1110,15 +1336,14 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1173,7 +1398,6 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set -# CONFIG_UCC_SLOW is not set # # Library routines @@ -1181,6 +1405,7 @@ CONFIG_NLS_ISO8859_1=y CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set @@ -1191,7 +1416,7 @@ CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -# CONFIG_INSTRUMENTATION is not set +CONFIG_HAVE_LMB=y # # Kernel hacking @@ -1199,6 +1424,7 @@ CONFIG_HAS_DMA=y CONFIG_PRINTK_TIME=y CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set @@ -1206,10 +1432,14 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -1220,17 +1450,39 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FORCED_INLINING=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set +# CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set # CONFIG_BOOTX_TEXT is not set # CONFIG_PPC_EARLY_DEBUG is not set @@ -1240,47 +1492,98 @@ CONFIG_FORCED_INLINING=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_ECB is not set -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# # CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/mpc7448_hpc2_defconfig b/arch/powerpc/configs/mpc7448_hpc2_defconfig index ab5199f26a24..f80b1ca43afb 100644 --- a/arch/powerpc/configs/mpc7448_hpc2_defconfig +++ b/arch/powerpc/configs/mpc7448_hpc2_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:06 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:40 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -104,7 +104,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -117,10 +119,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -147,6 +145,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -204,6 +203,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -218,15 +219,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -247,7 +248,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -315,6 +316,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -335,11 +337,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -576,6 +577,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -600,6 +604,7 @@ CONFIG_8139TOO=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -622,18 +627,22 @@ CONFIG_TSI108_ETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -766,6 +775,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -801,6 +818,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -817,6 +840,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -826,6 +850,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -837,12 +862,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -872,6 +898,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -906,6 +933,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -942,7 +970,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -972,13 +999,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -990,12 +1019,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1067,6 +1098,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/mpc8272_ads_defconfig b/arch/powerpc/configs/mpc8272_ads_defconfig index ff6f7c475f47..c8f5dec1b696 100644 --- a/arch/powerpc/configs/mpc8272_ads_defconfig +++ b/arch/powerpc/configs/mpc8272_ads_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:07 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:41 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -48,13 +48,11 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_PPC_OF=y CONFIG_OF=y -CONFIG_PPC_UDBG_16550=y +# CONFIG_PPC_UDBG_16550 is not set # CONFIG_GENERIC_TBSYNC is not set CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -93,7 +91,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -103,7 +100,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -116,10 +115,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -145,6 +141,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -152,16 +149,17 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set CONFIG_PPC_82xx=y CONFIG_MPC8272_ADS=y # CONFIG_PQ2FADS is not set # CONFIG_EP8248E is not set +# CONFIG_MGCOGE is not set CONFIG_PQ2ADS=y CONFIG_8260=y CONFIG_8272=y @@ -169,23 +167,19 @@ CONFIG_PQ2_ADS_PCI_PIC=y # CONFIG_PPC_83xx is not set # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -208,6 +202,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -217,15 +213,15 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -237,7 +233,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_FSL_SOC=y @@ -249,7 +244,7 @@ CONFIG_PCI_8260=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -305,7 +300,6 @@ CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_IP_VS is not set CONFIG_IPV6=y # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -332,10 +326,12 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -362,11 +358,10 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -472,7 +467,6 @@ CONFIG_OF_GPIO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -537,8 +531,6 @@ CONFIG_MDIO_BITBANG=y # CONFIG_MDIO_OF_GPIO is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -549,8 +541,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set CONFIG_FS_ENET_HAS_FCC=y @@ -573,18 +569,23 @@ CONFIG_NETDEV_1000=y # CONFIG_GIANFAR is not set # CONFIG_MV643XX_ETH is not set # CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -645,6 +646,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set @@ -684,21 +686,12 @@ CONFIG_DEVKMEM=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -CONFIG_SERIAL_CPM_SCC4=y -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -747,6 +740,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -788,6 +789,7 @@ CONFIG_DAB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -799,11 +801,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -833,6 +837,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -935,7 +940,6 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -989,15 +993,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_STACKOVERFLOW is not set @@ -1005,6 +1017,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set CONFIG_BDI_SWITCH=y @@ -1016,14 +1029,19 @@ CONFIG_BDI_SWITCH=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -1090,6 +1108,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_PPC_CLOCK=y CONFIG_PPC_LIB_RHEAP=y diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig index 991c9bda12a9..d582014b0a38 100644 --- a/arch/powerpc/configs/mpc83xx_defconfig +++ b/arch/powerpc/configs/mpc83xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 07:16:25 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:42 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -55,8 +55,6 @@ CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y CONFIG_REDBOOT=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set @@ -101,7 +99,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -111,7 +108,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -124,10 +123,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,6 +155,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -167,10 +163,10 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PPC_82xx is not set @@ -193,31 +189,27 @@ CONFIG_PPC_MPC834x=y CONFIG_PPC_MPC837x=y # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set CONFIG_IPIC=y -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set CONFIG_QUICC_ENGINE=y +CONFIG_QE_GPIO=y # CONFIG_FSL_ULI1575 is not set +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -231,6 +223,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -246,15 +240,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -266,7 +260,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_PPC_INDIRECT_PCI=y @@ -281,7 +274,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -349,6 +342,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -369,11 +363,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -488,7 +481,6 @@ CONFIG_OF_I2C=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -590,8 +582,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_MESH is not set -# CONFIG_SCSI_MAC53C94 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y @@ -692,12 +682,10 @@ CONFIG_VITESSE_PHY=y # CONFIG_BROADCOM_PHY is not set CONFIG_ICPLUS_PHY=y # CONFIG_REALTEK_PHY is not set -# CONFIG_FIXED_PHY is not set +CONFIG_FIXED_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -708,8 +696,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -736,18 +728,22 @@ CONFIG_UCC_GETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -782,7 +778,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -833,15 +829,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_OF_PLATFORM is not set # CONFIG_SERIAL_QE is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -879,12 +872,6 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set -# -# Mac SMBus host controller drivers -# -# CONFIG_I2C_HYDRA is not set -CONFIG_I2C_POWERMAC=y - # # I2C system bus drivers (mostly embedded / system-on-chip) # @@ -924,6 +911,7 @@ CONFIG_I2C_MPC=y # CONFIG_TPS65010 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set +# CONFIG_MCU_MPC8349EMITX is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -963,7 +951,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_AMS is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -1018,7 +1005,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -# CONFIG_WATCHDOG_RTAS is not set # # PCI-based Watchdog Cards @@ -1044,6 +1030,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1086,9 +1083,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1107,6 +1131,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1123,6 +1149,8 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1130,6 +1158,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1158,6 +1187,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1174,7 +1204,9 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1184,6 +1216,7 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1195,12 +1228,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1230,6 +1264,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1268,6 +1303,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1301,13 +1337,11 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_DLM is not set CONFIG_UCC_FAST=y CONFIG_UCC=y -CONFIG_QE_GPIO=y # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1335,13 +1369,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1353,16 +1389,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1435,6 +1474,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_CRYPTO_DEV_TALITOS=y diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index f0a13bebf50c..c87b53abc617 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 07:15:20 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:43 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_SPE=y # CONFIG_PPC_MM_SLICES is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -111,7 +111,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -125,10 +127,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -161,6 +160,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -197,9 +197,11 @@ CONFIG_PPC_I8259=y # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set CONFIG_QUICC_ENGINE=y +# CONFIG_QE_GPIO is not set CONFIG_CPM2=y CONFIG_FSL_ULI1575=y CONFIG_CPM=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -219,6 +221,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -233,15 +237,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -265,7 +269,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -367,6 +371,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -387,12 +392,11 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -639,8 +643,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set # CONFIG_FS_ENET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set @@ -664,18 +672,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -710,7 +722,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -902,7 +914,19 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -943,7 +967,6 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_USB is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_CINERGYT2 is not set # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -960,6 +983,11 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # CONFIG_DVB_PLUTO2 is not set +# +# Supported SDMC DM1105 Adapters +# +# CONFIG_DVB_DM1105 is not set + # # Supported DVB Frontends # @@ -976,6 +1004,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_CX24123 is not set # CONFIG_DVB_MT312 is not set # CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set # CONFIG_DVB_STV0299 is not set # CONFIG_DVB_TDA8083 is not set # CONFIG_DVB_TDA10086 is not set @@ -983,6 +1013,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TDA826X is not set # CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set # # DVB-T (terrestrial) frontends @@ -1035,6 +1067,13 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_LNBP21 is not set # CONFIG_DVB_ISL6405 is not set # CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -1060,6 +1099,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1160,9 +1200,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1181,6 +1248,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1204,6 +1273,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # CONFIG_USB_MUSB_HDRC is not set # @@ -1212,6 +1283,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1233,7 +1305,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1254,6 +1325,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1271,7 +1343,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1324,12 +1398,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1350,6 +1427,7 @@ CONFIG_DMA_ENGINE=y # CONFIG_NET_DMA is not set # CONFIG_DMATEST is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1361,13 +1439,14 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1405,6 +1484,7 @@ CONFIG_NTFS_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1449,6 +1529,7 @@ CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1519,13 +1600,11 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_KOI8_U is not set CONFIG_NLS_UTF8=m # CONFIG_DLM is not set -# CONFIG_QE_GPIO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1579,15 +1658,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1596,6 +1683,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set CONFIG_VIRQ_DEBUG=y @@ -1607,15 +1695,19 @@ CONFIG_VIRQ_DEBUG=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1688,6 +1780,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig index 1501c4336b3d..8272b1ac71f9 100644 --- a/arch/powerpc/configs/mpc866_ads_defconfig +++ b/arch/powerpc/configs/mpc866_ads_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:11 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:43 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_8xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -99,6 +99,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -112,10 +113,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -142,6 +140,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -154,6 +153,7 @@ CONFIG_MPC86XADS=y # CONFIG_MPC885ADS is not set # CONFIG_PPC_EP88XC is not set # CONFIG_PPC_ADDER875 is not set +# CONFIG_PPC_MGSUVD is not set # # MPC8xx CPM Options @@ -182,6 +182,7 @@ CONFIG_NO_UCODE_PATCH=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -203,6 +204,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -217,15 +220,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_PROC_DEVICETREE is not set # CONFIG_CMDLINE_BOOL is not set @@ -311,6 +314,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -331,11 +335,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -412,6 +415,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FS_ENET=y CONFIG_FS_ENET_HAS_SCC=y @@ -471,6 +477,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set @@ -510,12 +517,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set @@ -563,6 +564,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -596,6 +605,12 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -619,6 +634,7 @@ CONFIG_USB_SUPPORT=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -632,12 +648,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -667,6 +684,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -703,6 +721,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -739,7 +758,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -769,12 +787,14 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -785,12 +805,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -862,6 +884,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_TALITOS is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/mpc86xx_defconfig b/arch/powerpc/configs/mpc86xx_defconfig index 9d4be820cf1f..1736bbc281ec 100644 --- a/arch/powerpc/configs/mpc86xx_defconfig +++ b/arch/powerpc/configs/mpc86xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc5 -# Tue Sep 23 23:28:38 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:44 2008 # # CONFIG_PPC64 is not set @@ -15,6 +15,7 @@ CONFIG_6xx=y # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y @@ -23,7 +24,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -109,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +126,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -160,7 +160,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y -# CONFIG_MPC8xxx_GPIO is not set +# CONFIG_FREEZER is not set # # Platform support @@ -196,7 +196,9 @@ CONFIG_PPC_I8259=y # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_FSL_ULI1575=y +# CONFIG_MPC8xxx_GPIO is not set # # Kernel options @@ -216,6 +218,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -231,15 +235,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -263,7 +267,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -365,6 +369,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -385,12 +390,11 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -636,8 +640,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -660,18 +668,22 @@ CONFIG_GIANFAR=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -706,7 +718,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # @@ -875,6 +887,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -915,7 +938,6 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_USB is not set # CONFIG_DVB_TTUSB_BUDGET is not set # CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_CINERGYT2 is not set # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -932,6 +954,11 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # # CONFIG_DVB_PLUTO2 is not set +# +# Supported SDMC DM1105 Adapters +# +# CONFIG_DVB_DM1105 is not set + # # Supported DVB Frontends # @@ -948,6 +975,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_CX24123 is not set # CONFIG_DVB_MT312 is not set # CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set # CONFIG_DVB_STV0299 is not set # CONFIG_DVB_TDA8083 is not set # CONFIG_DVB_TDA10086 is not set @@ -955,6 +984,8 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_TUNER_ITD1000 is not set # CONFIG_DVB_TDA826X is not set # CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set # # DVB-T (terrestrial) frontends @@ -1007,6 +1038,13 @@ CONFIG_DVB_CAPTURE_DRIVERS=y # CONFIG_DVB_LNBP21 is not set # CONFIG_DVB_ISL6405 is not set # CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y # CONFIG_USB_DABUSB is not set @@ -1032,6 +1070,7 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1132,9 +1171,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1153,6 +1219,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1176,6 +1244,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1183,6 +1253,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1204,7 +1275,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1225,6 +1295,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1242,7 +1313,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1288,12 +1361,15 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1302,6 +1378,7 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1313,12 +1390,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1356,6 +1434,7 @@ CONFIG_NTFS_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1400,6 +1479,7 @@ CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1475,7 +1555,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1529,15 +1608,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1558,15 +1645,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1639,6 +1730,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig index fc3f6dc58126..a4283b6a43d2 100644 --- a/arch/powerpc/configs/mpc885_ads_defconfig +++ b/arch/powerpc/configs/mpc885_ads_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:12 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:46 2008 # # CONFIG_PPC64 is not set @@ -19,7 +19,7 @@ CONFIG_8xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -101,6 +101,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set @@ -114,10 +115,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y # CONFIG_TINY_SHMEM is not set @@ -143,6 +141,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -155,6 +154,7 @@ CONFIG_CPM1=y CONFIG_MPC885ADS=y # CONFIG_PPC_EP88XC is not set # CONFIG_PPC_ADDER875 is not set +# CONFIG_PPC_MGSUVD is not set # # Freescale Ethernet driver platform-specific options @@ -190,6 +190,7 @@ CONFIG_NO_UCODE_PATCH=y # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -211,6 +212,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set CONFIG_8XX_MINIMAL_FPEMU=y @@ -226,15 +229,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -316,6 +319,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -336,11 +340,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -486,6 +489,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set @@ -540,12 +546,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set @@ -581,6 +581,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -619,16 +627,18 @@ CONFIG_DAB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -657,6 +667,7 @@ CONFIG_DAB=y CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -694,6 +705,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -729,7 +741,6 @@ CONFIG_MSDOS_PARTITION=y # # Library routines # -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -779,14 +790,22 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -795,6 +814,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set @@ -805,6 +825,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set CONFIG_PPC_CLOCK=y diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig index 80481f270133..de9b121820a6 100644 --- a/arch/powerpc/configs/pmac32_defconfig +++ b/arch/powerpc/configs/pmac32_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:20:26 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:36:51 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -125,10 +127,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -161,6 +159,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # Platform support @@ -232,6 +231,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -246,15 +247,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_MIGRATION is not set # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -362,7 +363,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -392,13 +392,14 @@ CONFIG_NF_CONNTRACK_IRC=m # CONFIG_NF_CONNTRACK_SIP is not set CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -412,19 +413,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m # CONFIG_NETFILTER_XT_MATCH_STATE is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set @@ -432,20 +436,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -453,8 +457,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m # CONFIG_NF_NAT_SNMP_BASIC is not set CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_FTP=m @@ -465,9 +469,9 @@ CONFIG_NF_NAT_TFTP=m # CONFIG_NF_NAT_H323 is not set # CONFIG_NF_NAT_SIP is not set CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -494,6 +498,7 @@ CONFIG_IP_DCCP_TFRC_LIB=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -585,12 +590,11 @@ CONFIG_BT_HCIBFUSB=m # CONFIG_BT_HCIBTUART is not set # CONFIG_BT_HCIVHCI is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y CONFIG_CFG80211=m CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_MAC80211=m @@ -599,7 +603,9 @@ CONFIG_MAC80211=m # Rate control algorithm selection # CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_RC_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT="pid" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y @@ -663,7 +669,6 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives @@ -671,14 +676,14 @@ CONFIG_BLK_DEV_IDE=y CONFIG_IDE_TIMINGS=y CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECS=m # CONFIG_BLK_DEV_DELKIN is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=y CONFIG_BLK_DEV_IDESCSI=y # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -899,6 +904,9 @@ CONFIG_SUNGEM=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y # CONFIG_AMD8111_ETH is not set @@ -919,6 +927,7 @@ CONFIG_PCNET32=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -940,18 +949,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -964,6 +977,7 @@ CONFIG_WLAN_80211=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set # CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_AIRO is not set CONFIG_HERMES=m CONFIG_APPLE_AIRPORT=m @@ -1023,6 +1037,7 @@ CONFIG_USB_USBNET=m CONFIG_USB_NET_AX8817X=m CONFIG_USB_NET_CDCETHER=m # CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set # CONFIG_USB_NET_GL620A is not set CONFIG_USB_NET_NET1080=m # CONFIG_USB_NET_PLUSB is not set @@ -1239,6 +1254,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_APM_POWER=y # CONFIG_BATTERY_DS2760 is not set CONFIG_BATTERY_PMU=y +# CONFIG_BATTERY_BQ27x00 is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set @@ -1266,6 +1282,17 @@ CONFIG_SSB_DRIVER_PCICORE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1301,6 +1328,7 @@ CONFIG_VGASTATE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -1357,6 +1385,7 @@ CONFIG_FB_ATY_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set CONFIG_FB_3DFX=y @@ -1369,6 +1398,7 @@ CONFIG_FB_3DFX=y # CONFIG_FB_CARMINE is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_ILI9320 is not set @@ -1401,6 +1431,7 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1514,9 +1545,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -CONFIG_USB_HIDINPUT_POWERBOOK=y -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1534,6 +1592,8 @@ CONFIG_USB_DYNAMIC_MINORS=y # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1553,6 +1613,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1560,6 +1622,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1581,7 +1644,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set CONFIG_USB_STORAGE_ONETOUCH=y # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1656,6 +1718,7 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1673,7 +1736,9 @@ CONFIG_USB_APPLEDISPLAY=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -1692,6 +1757,7 @@ CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_TIMER is not set CONFIG_LEDS_TRIGGER_IDE_DISK=y # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set @@ -1699,6 +1765,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1710,12 +1777,18 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set CONFIG_JBD=y +CONFIG_JBD2=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set @@ -1752,6 +1825,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1794,6 +1868,7 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1870,7 +1945,6 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -1927,18 +2001,25 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1946,6 +2027,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set CONFIG_XMON=y CONFIG_XMON_DEFAULT=y CONFIG_XMON_DISASSEMBLY=y @@ -1960,16 +2042,19 @@ CONFIG_BOOTX_TEXT=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m @@ -2043,6 +2128,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig index 6a5b713a07e0..4256e2c4534b 100644 --- a/arch/powerpc/configs/ppc40x_defconfig +++ b/arch/powerpc/configs/ppc40x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 12:34:33 2008 +# Linux kernel version: 2.6.28-rc4 +# Fri Nov 14 09:54:44 2008 # # CONFIG_PPC64 is not set @@ -19,14 +19,13 @@ CONFIG_4xx=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -37,6 +36,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y # CONFIG_ARCH_NO_VIRT_TO_BUS is not set CONFIG_PPC=y CONFIG_EARLY_PRINTK=y @@ -88,7 +88,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -105,7 +104,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -119,10 +120,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -155,6 +152,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -163,14 +161,20 @@ CONFIG_PPC4xx_PCI_EXPRESS=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set # CONFIG_PQ2ADS is not set +CONFIG_PPC4xx_GPIO=y CONFIG_XILINX_VIRTEX=y +CONFIG_ACADIA=y CONFIG_EP405=y +CONFIG_HCU4=y CONFIG_KILAUEA=y CONFIG_MAKALU=y CONFIG_WALNUT=y CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y +CONFIG_PPC40x_SIMPLE=y CONFIG_405GP=y CONFIG_405EX=y +CONFIG_405EZ=y +CONFIG_405GPR=y CONFIG_XILINX_VIRTEX_II_PRO=y CONFIG_XILINX_VIRTEX_4_FX=y CONFIG_IBM405_ERR77=y @@ -193,7 +197,6 @@ CONFIG_OF_RTC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -207,6 +210,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -221,15 +226,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -339,6 +344,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -359,11 +365,10 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -476,6 +481,7 @@ CONFIG_MTD_UBI_GLUEBI=y # # CONFIG_MTD_UBI_DEBUG is not set CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y CONFIG_OF_I2C=m # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y @@ -494,15 +500,17 @@ CONFIG_BLK_DEV_RAM_SIZE=35000 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_XILINX_SYSACE is not set +CONFIG_XILINX_SYSACE=m # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -556,8 +564,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y CONFIG_IBM_NEW_EMAC_RGMII=y # CONFIG_IBM_NEW_EMAC_TAH is not set CONFIG_IBM_NEW_EMAC_EMAC4=y +CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL=y +CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT=y +CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR=y # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -578,18 +590,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -618,7 +634,13 @@ CONFIG_NETDEV_10000=y # # Hardware I/O ports # -# CONFIG_SERIO is not set +CONFIG_SERIO=m +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +CONFIG_SERIO_XILINX_XPS_PS2=m # CONFIG_GAMEPORT is not set # @@ -646,7 +668,8 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # # Non-8250 serial port support # -# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set @@ -667,6 +690,8 @@ CONFIG_DEVPORT=y CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support @@ -693,6 +718,7 @@ CONFIG_I2C_CHARDEV=m # # I2C system bus drivers (mostly embedded / system-on-chip) # +CONFIG_I2C_GPIO=m CONFIG_I2C_IBM_IIC=m # CONFIG_I2C_MPC is not set # CONFIG_I2C_OCORES is not set @@ -725,6 +751,7 @@ CONFIG_I2C_IBM_IIC=m # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set @@ -733,17 +760,41 @@ CONFIG_I2C_IBM_IIC=m # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_XILINX=y + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set CONFIG_THERMAL=y # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -752,6 +803,10 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -776,13 +831,65 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DRM is not set # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set +CONFIG_FB=m +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_XILINX=m +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_LOGO is not set # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -792,10 +899,15 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# +# Enable Host or Gadget support to see Inventra options +# + # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -805,6 +917,8 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -816,13 +930,14 @@ CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=m # CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y +CONFIG_FS_MBCACHE=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -855,6 +970,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -908,6 +1024,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -967,7 +1084,6 @@ CONFIG_NLS_ISO8859_1=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set CONFIG_CRC16=m # CONFIG_CRC_T10DIF is not set @@ -1023,14 +1139,23 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1039,6 +1164,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_VIRQ_DEBUG is not set @@ -1050,14 +1176,19 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1130,6 +1261,11 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig index c7825dcbf415..cfc94cfcf4cb 100644 --- a/arch/powerpc/configs/ppc44x_defconfig +++ b/arch/powerpc/configs/ppc44x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc1 -# Tue Aug 5 10:01:31 2008 +# Linux kernel version: 2.6.28-rc4 +# Fri Nov 14 10:06:19 2008 # # CONFIG_PPC64 is not set @@ -23,14 +23,13 @@ CONFIG_PHYS_64BIT=y CONFIG_NOT_COHERENT_CACHE=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y -# CONFIG_HAVE_GET_USER_PAGES_FAST is not set # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -41,6 +40,7 @@ CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y # CONFIG_ARCH_NO_VIRT_TO_BUS is not set CONFIG_PPC=y CONFIG_EARLY_PRINTK=y @@ -92,7 +92,6 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y @@ -109,7 +108,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +124,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -158,7 +155,9 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_PREEMPT_NOTIFIERS=y CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set CONFIG_PPC4xx_PCI_EXPRESS=y # @@ -175,9 +174,13 @@ CONFIG_TAISHAN=y CONFIG_KATMAI=y CONFIG_RAINIER=y CONFIG_WARP=y +CONFIG_ARCHES=y CONFIG_CANYONLANDS=y +CONFIG_GLACIER=y CONFIG_YOSEMITE=y CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y +CONFIG_PPC44x_SIMPLE=y +CONFIG_PPC4xx_GPIO=y CONFIG_440EP=y CONFIG_440EPX=y CONFIG_440GRX=y @@ -206,7 +209,6 @@ CONFIG_OF_RTC=y # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -220,6 +222,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y # CONFIG_IOMMU_HELPER is not set @@ -234,15 +238,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -351,6 +355,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -371,14 +376,8 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -487,6 +486,7 @@ CONFIG_MTD_UBI_GLUEBI=y # # CONFIG_MTD_UBI_DEBUG is not set CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y CONFIG_OF_I2C=m # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y @@ -506,15 +506,17 @@ CONFIG_BLK_DEV_RAM_SIZE=35000 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_XILINX_SYSACE is not set +CONFIG_XILINX_SYSACE=m # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -600,8 +602,12 @@ CONFIG_IBM_NEW_EMAC_ZMII=y CONFIG_IBM_NEW_EMAC_RGMII=y CONFIG_IBM_NEW_EMAC_TAH=y CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -622,18 +628,22 @@ CONFIG_NETDEV_1000=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -672,7 +682,13 @@ CONFIG_NETDEV_10000=y # # Hardware I/O ports # -# CONFIG_SERIO is not set +CONFIG_SERIO=m +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +CONFIG_SERIO_XILINX_XPS_PS2=m # CONFIG_GAMEPORT is not set # @@ -700,7 +716,8 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # # Non-8250 serial port support # -# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set @@ -721,6 +738,8 @@ CONFIG_DEVPORT=y CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support @@ -747,6 +766,7 @@ CONFIG_I2C_CHARDEV=m # # I2C system bus drivers (mostly embedded / system-on-chip) # +CONFIG_I2C_GPIO=m CONFIG_I2C_IBM_IIC=m # CONFIG_I2C_MPC is not set # CONFIG_I2C_OCORES is not set @@ -780,6 +800,7 @@ CONFIG_I2C_IBM_IIC=m # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set @@ -788,18 +809,42 @@ CONFIG_I2C_IBM_IIC=m # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +CONFIG_GPIO_XILINX=y + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -808,6 +853,10 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -832,13 +881,65 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set +CONFIG_FB=m +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_XILINX=m +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_LOGO is not set # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -857,6 +958,9 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -881,6 +985,12 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# Enable Host or Gadget support to see Inventra options +# # # USB Device Class drivers @@ -888,6 +998,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -916,7 +1027,6 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -929,7 +1039,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -946,7 +1056,9 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -956,6 +1068,8 @@ CONFIG_USB_STORAGE=m # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -967,12 +1081,13 @@ CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=m -CONFIG_FS_MBCACHE=y +CONFIG_FS_MBCACHE=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1005,6 +1120,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1058,6 +1174,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1117,7 +1234,6 @@ CONFIG_NLS_ISO8859_1=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set CONFIG_CRC16=m CONFIG_CRC_T10DIF=m @@ -1173,14 +1289,23 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1189,24 +1314,29 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set # CONFIG_BDI_SWITCH is not set -# CONFIG_PPC_EARLY_DEBUG is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1279,6 +1409,15 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set -# CONFIG_VIRTUALIZATION is not set +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_KVM_BOOKE_HOST=y +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig index fc5930caeb5f..069ae1bbac29 100644 --- a/arch/powerpc/configs/ppc64_defconfig +++ b/arch/powerpc/configs/ppc64_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:22:03 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:36:56 2008 # CONFIG_PPC64=y @@ -22,7 +22,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_64BIT=y CONFIG_WORD_SIZE=64 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -87,6 +87,7 @@ CONFIG_LOG_BUF_SHIFT=17 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set # CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set # CONFIG_CGROUP_DEVICE is not set CONFIG_CPUSETS=y # CONFIG_GROUP_SCHED is not set @@ -124,12 +125,15 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y CONFIG_MARKERS=y CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y @@ -141,8 +145,6 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -175,6 +177,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set +CONFIG_PPC_MSI_BITMAP=y # # Platform support @@ -294,6 +298,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_IOMMU_VMERGE=y @@ -303,7 +309,6 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set # CONFIG_PHYP_DUMP is not set CONFIG_IRQ_ALL_CPUS=y # CONFIG_NUMA is not set @@ -318,7 +323,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -329,8 +333,10 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_ARCH_MEMORY_PROBE=y CONFIG_PPC_HAS_HASH_64K=y # CONFIG_PPC_64K_PAGES is not set @@ -379,6 +385,7 @@ CONFIG_HOTPLUG_PCI=m CONFIG_HOTPLUG_PCI_RPA=m CONFIG_HOTPLUG_PCI_RPA_DLPAR=m # CONFIG_HAS_RAPIDIO is not set +# CONFIG_RELOCATABLE is not set CONFIG_PAGE_OFFSET=0xc000000000000000 CONFIG_KERNEL_START=0xc000000000000000 CONFIG_PHYSICAL_START=0x00000000 @@ -426,7 +433,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -457,15 +463,17 @@ CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -477,40 +485,44 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m # CONFIG_NETFILTER_XT_MATCH_TIME is not set CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -518,8 +530,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_SCTP=m @@ -531,9 +543,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -543,6 +555,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=y @@ -565,11 +578,10 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -624,21 +636,20 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECS is not set # CONFIG_BLK_DEV_DELKIN is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -835,6 +846,7 @@ CONFIG_SATA_SVW=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -926,6 +938,9 @@ CONFIG_IBM_NEW_EMAC_ZMII=y CONFIG_IBM_NEW_EMAC_RGMII=y CONFIG_IBM_NEW_EMAC_TAH=y CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y # CONFIG_AMD8111_ETH is not set @@ -946,12 +961,12 @@ CONFIG_E100=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y CONFIG_ACENIC=y CONFIG_ACENIC_OMIT_TIGON_I=y # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -969,10 +984,12 @@ CONFIG_SPIDER_NET=m # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set CONFIG_EHEA=m +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set CONFIG_IXGB=m # CONFIG_S2IO is not set @@ -980,9 +997,11 @@ CONFIG_IXGB=m # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set CONFIG_PASEMI_MAC=y +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set CONFIG_TR=y CONFIG_IBMOL=y @@ -1065,6 +1084,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set @@ -1080,6 +1100,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # @@ -1255,6 +1276,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1282,6 +1314,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -1326,6 +1359,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -1337,6 +1371,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_CARMINE is not set CONFIG_FB_IBM_GXT4500=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_ILI9320 is not set @@ -1370,6 +1405,7 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1481,9 +1517,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1500,6 +1563,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1520,6 +1585,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1527,6 +1594,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1548,7 +1616,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1569,6 +1636,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1586,7 +1654,9 @@ CONFIG_USB_APPLEDISPLAY=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1656,12 +1726,15 @@ CONFIG_RTC_DRV_DS1307=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1670,6 +1743,7 @@ CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PPC=y # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1679,14 +1753,20 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_XIP=y CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y # CONFIG_REISERFS_CHECK is not set @@ -1700,6 +1780,7 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set CONFIG_XFS_POSIX_ACL=y @@ -1740,6 +1821,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1785,6 +1867,7 @@ CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_XPRT_RDMA=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set @@ -1866,9 +1949,8 @@ CONFIG_NLS_UTF8=m # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y @@ -1929,22 +2011,31 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y CONFIG_TRACING=y -# CONFIG_FTRACE is not set + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set CONFIG_IRQSOFF_TRACER=y CONFIG_SCHED_TRACER=y CONFIG_CONTEXT_SWITCH_TRACER=y +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set # CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1954,6 +2045,7 @@ CONFIG_DEBUG_STACK_USAGE=y # CONFIG_HCALL_STATS is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set CONFIG_XMON=y # CONFIG_XMON_DEFAULT is not set CONFIG_XMON_DISASSEMBLY=y @@ -1968,6 +2060,7 @@ CONFIG_BOOTX_TEXT=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y @@ -1978,10 +2071,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -2055,6 +2150,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 3c6dbdef56eb..01f05ec5abf3 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:29:50 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:37:01 2008 # # CONFIG_PPC64 is not set @@ -23,7 +23,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -89,6 +89,7 @@ CONFIG_LOG_BUF_SHIFT=17 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_NS=y +# CONFIG_CGROUP_FREEZER is not set CONFIG_CGROUP_DEVICE=y CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y @@ -128,12 +129,15 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y CONFIG_MARKERS=y CONFIG_OPROFILE=m CONFIG_HAVE_OPROFILE=y @@ -144,10 +148,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -180,6 +181,8 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y +CONFIG_PPC_MSI_BITMAP=y # # Platform support @@ -202,6 +205,7 @@ CONFIG_PPC_82xx=y CONFIG_MPC8272_ADS=y CONFIG_PQ2FADS=y CONFIG_EP8248E=y +CONFIG_MGCOGE=y CONFIG_PQ2ADS=y CONFIG_8260=y CONFIG_8272=y @@ -226,6 +230,7 @@ CONFIG_PPC_86xx=y CONFIG_MPC8641_HPCN=y CONFIG_SBC8641D=y CONFIG_MPC8610_HPCD=y +CONFIG_GEF_SBC610=y CONFIG_MPC8641=y CONFIG_MPC8610=y # CONFIG_EMBEDDED6xx is not set @@ -268,6 +273,7 @@ CONFIG_TAU=y # CONFIG_TAU_INT is not set CONFIG_TAU_AVERAGE=y CONFIG_QUICC_ENGINE=y +CONFIG_QE_GPIO=y CONFIG_CPM2=y CONFIG_FSL_ULI1575=y CONFIG_CPM=y @@ -275,6 +281,7 @@ CONFIG_PPC_BESTCOMM=y CONFIG_PPC_BESTCOMM_ATA=m CONFIG_PPC_BESTCOMM_FEC=m CONFIG_PPC_BESTCOMM_GEN_BD=m +CONFIG_MPC8xxx_GPIO=y # # Kernel options @@ -294,6 +301,8 @@ CONFIG_SCHED_HRTICK=y CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set @@ -309,15 +318,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_MIGRATION is not set CONFIG_RESOURCES_64BIT=y +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -359,7 +368,7 @@ CONFIG_PCIEASPM=y # CONFIG_PCIEASPM_DEBUG is not set CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_PCI_MSI=y -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set CONFIG_PCCARD=y # CONFIG_PCMCIA_DEBUG is not set @@ -466,7 +475,6 @@ CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -# CONFIG_IP_VS is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y @@ -521,18 +529,20 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m @@ -543,41 +553,45 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m # CONFIG_NF_CONNTRACK_PROC_COMPAT is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -585,8 +599,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_PROTO_GRE=m @@ -600,9 +614,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m @@ -615,16 +629,16 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_TARGET_HL=m @@ -635,10 +649,6 @@ CONFIG_IP6_NF_SECURITY=m # DECnet: Netfilter Configuration # # CONFIG_DECNET_NF_GRABULATOR is not set - -# -# Bridge: Netfilter Configuration -# CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -698,6 +708,7 @@ CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set CONFIG_STP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set CONFIG_DECNET=m @@ -727,6 +738,7 @@ CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -767,6 +779,7 @@ CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m CONFIG_NET_CLS_IND=y CONFIG_NET_SCH_FIFO=y @@ -853,13 +866,12 @@ CONFIG_BT_HCIBLUECARD=m CONFIG_BT_HCIBTUART=m CONFIG_BT_HCIVHCI=m # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y CONFIG_CFG80211=m CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_MAC80211=m @@ -868,7 +880,9 @@ CONFIG_MAC80211=m # Rate control algorithm selection # CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_RC_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT="pid" CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y @@ -917,7 +931,7 @@ CONFIG_PARPORT_SERIAL=m CONFIG_PARPORT_1284=y CONFIG_PARPORT_NOT_PC=y CONFIG_PNP=y -# CONFIG_PNP_DEBUG is not set +CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols @@ -958,22 +972,20 @@ CONFIG_ENCLOSURE_SERVICES=m # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y -CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECS is not set # CONFIG_BLK_DEV_DELKIN is not set CONFIG_BLK_DEV_IDECD=m CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=m # CONFIG_BLK_DEV_IDESCSI is not set CONFIG_IDE_TASK_IOCTL=y CONFIG_IDE_PROC_FS=y @@ -1201,6 +1213,7 @@ CONFIG_PATA_OF_PLATFORM=m CONFIG_PATA_SCH=m CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m @@ -1332,6 +1345,9 @@ CONFIG_NE2000=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=m CONFIG_AMD8111_ETH=m @@ -1370,13 +1386,13 @@ CONFIG_DE600=m CONFIG_DE620=m CONFIG_FEC_MPC52xx=m CONFIG_FEC_MPC52xx_MDIO=y +# CONFIG_ATL2 is not set # CONFIG_FS_ENET is not set CONFIG_NETDEV_1000=y CONFIG_ACENIC=m # CONFIG_ACENIC_OMIT_TIGON_I is not set CONFIG_DL2K=m CONFIG_E1000=m -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set CONFIG_E1000E=m CONFIG_IP1000=m CONFIG_IGB=m @@ -1400,19 +1416,23 @@ CONFIG_MV643XX_ETH=m CONFIG_QLA3XXX=m CONFIG_ATL1=m # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y CONFIG_CHELSIO_T1=m CONFIG_CHELSIO_T1_1G=y CONFIG_CHELSIO_T3=m +# CONFIG_ENIC is not set CONFIG_IXGBE=m CONFIG_IXGB=m CONFIG_S2IO=m CONFIG_MYRI10GE=m CONFIG_NETXEN_NIC=m CONFIG_NIU=m +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set CONFIG_TEHUTI=m CONFIG_BNX2X=m +CONFIG_QLGE=m CONFIG_SFC=m # CONFIG_TR is not set @@ -1434,6 +1454,7 @@ CONFIG_USB_USBNET=m CONFIG_USB_NET_AX8817X=m CONFIG_USB_NET_CDCETHER=m CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m @@ -1546,6 +1567,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m CONFIG_MOUSE_APPLETOUCH=m @@ -1598,6 +1620,7 @@ CONFIG_INPUT_ATI_REMOTE2=m CONFIG_INPUT_KEYSPAN_REMOTE=m CONFIG_INPUT_POWERMATE=m CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m CONFIG_INPUT_UINPUT=m # @@ -1787,6 +1810,7 @@ CONFIG_SENSORS_PCF8591=m # CONFIG_TPS65010 is not set CONFIG_SENSORS_MAX6875=m CONFIG_SENSORS_TSL2550=m +CONFIG_MCU_MPC8349EMITX=m # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -1837,6 +1861,7 @@ CONFIG_POWER_SUPPLY=m CONFIG_APM_POWER=m # CONFIG_BATTERY_DS2760 is not set CONFIG_BATTERY_PMU=m +# CONFIG_BATTERY_BQ27x00 is not set CONFIG_HWMON=m CONFIG_HWMON_VID=m # CONFIG_SENSORS_AD7414 is not set @@ -1946,8 +1971,21 @@ CONFIG_SSB_DRIVER_PCICORE=y # # CONFIG_MFD_CORE is not set CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y # CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1999,6 +2037,7 @@ CONFIG_VIDEO_TVEEPROM=m CONFIG_VIDEO_TUNER=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set CONFIG_VIDEO_IR_I2C=m @@ -2079,14 +2118,12 @@ CONFIG_VIDEO_CPIA_USB=m CONFIG_VIDEO_CPIA2=m CONFIG_VIDEO_SAA5246A=m CONFIG_VIDEO_SAA5249=m -CONFIG_TUNER_3036=m # CONFIG_VIDEO_STRADIS is not set # CONFIG_VIDEO_ZORAN is not set CONFIG_VIDEO_SAA7134=m CONFIG_VIDEO_SAA7134_ALSA=m CONFIG_VIDEO_SAA7134_DVB=m CONFIG_VIDEO_MXB=m -CONFIG_VIDEO_DPC=m CONFIG_VIDEO_HEXIUM_ORION=m CONFIG_VIDEO_HEXIUM_GEMINI=m CONFIG_VIDEO_CX88=m @@ -2100,10 +2137,40 @@ CONFIG_VIDEO_IVTV=m CONFIG_VIDEO_FB_IVTV=m CONFIG_VIDEO_CX18=m # CONFIG_VIDEO_CAFE_CCIC is not set +CONFIG_SOC_CAMERA=m +CONFIG_SOC_CAMERA_MT9M001=m +# CONFIG_MT9M001_PCA9536_SWITCH is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +CONFIG_SOC_CAMERA_MT9V022=m +# CONFIG_MT9V022_PCA9536_SWITCH is not set +# CONFIG_SOC_CAMERA_PLATFORM is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set CONFIG_V4L_USB_DRIVERS=y CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_ZC3XX is not set CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y @@ -2130,13 +2197,6 @@ CONFIG_USB_PWC=m CONFIG_USB_ZR364XX=m CONFIG_USB_STKWEBCAM=m # CONFIG_USB_S2255 is not set -CONFIG_SOC_CAMERA=m -CONFIG_SOC_CAMERA_MT9M001=m -# CONFIG_MT9M001_PCA9536_SWITCH is not set -CONFIG_SOC_CAMERA_MT9V022=m -# CONFIG_MT9V022_PCA9536_SWITCH is not set -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set CONFIG_RADIO_ADAPTERS=y # CONFIG_RADIO_CADET is not set # CONFIG_RADIO_RTRACK is not set @@ -2154,6 +2214,7 @@ CONFIG_RADIO_MAESTRO=m # CONFIG_RADIO_ZOLTRIX is not set CONFIG_USB_DSBR=m CONFIG_USB_SI470X=m +CONFIG_USB_MR800=m CONFIG_DVB_CAPTURE_DRIVERS=y # @@ -2194,16 +2255,12 @@ CONFIG_DVB_USB_OPERA1=m CONFIG_DVB_USB_AF9005=m CONFIG_DVB_USB_AF9005_REMOTE=m # CONFIG_DVB_USB_DW2102 is not set +# CONFIG_DVB_USB_CINERGY_T2 is not set # CONFIG_DVB_USB_ANYSEE is not set +# CONFIG_DVB_USB_DTV5100 is not set +# CONFIG_DVB_USB_AF9015 is not set CONFIG_DVB_TTUSB_BUDGET=m CONFIG_DVB_TTUSB_DEC=m -CONFIG_DVB_CINERGYT2=m -CONFIG_DVB_CINERGYT2_TUNING=y -CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32 -CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512 -CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250 -CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y -CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100 # CONFIG_DVB_SIANO_SMS1XXX is not set # @@ -2224,6 +2281,11 @@ CONFIG_DVB_BT8XX=m # CONFIG_DVB_PLUTO2=m +# +# Supported SDMC DM1105 Adapters +# +CONFIG_DVB_DM1105=m + # # Supported DVB Frontends # @@ -2240,6 +2302,8 @@ CONFIG_DVB_CX24110=m CONFIG_DVB_CX24123=m CONFIG_DVB_MT312=m CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m CONFIG_DVB_STV0299=m CONFIG_DVB_TDA8083=m CONFIG_DVB_TDA10086=m @@ -2247,6 +2311,8 @@ CONFIG_DVB_VES1X93=m CONFIG_DVB_TUNER_ITD1000=m CONFIG_DVB_TDA826X=m CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_SI21XX=m # # DVB-T (terrestrial) frontends @@ -2299,6 +2365,13 @@ CONFIG_DVB_TUNER_DIB0070=m CONFIG_DVB_LNBP21=m CONFIG_DVB_ISL6405=m CONFIG_DVB_ISL6421=m +CONFIG_DVB_LGS8GL5=m + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set CONFIG_DAB=y CONFIG_USB_DABUSB=m @@ -2320,6 +2393,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -2382,6 +2456,7 @@ CONFIG_FB_SAVAGE=m CONFIG_FB_SAVAGE_I2C=y CONFIG_FB_SAVAGE_ACCEL=y # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set CONFIG_FB_NEOMAGIC=m CONFIG_FB_KYRO=m CONFIG_FB_3DFX=m @@ -2397,6 +2472,7 @@ CONFIG_FB_TRIDENT_ACCEL=y CONFIG_FB_SM501=m CONFIG_FB_IBM_GXT4500=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_ILI9320 is not set @@ -2432,6 +2508,7 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -2594,15 +2671,36 @@ CONFIG_HIDRAW=y # USB Input Devices # CONFIG_USB_HID=y -CONFIG_USB_HIDINPUT_POWERBOOK=y -CONFIG_HID_FF=y CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y CONFIG_LOGITECH_FF=y CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y CONFIG_THRUSTMASTER_FF=y CONFIG_ZEROPLUS_FF=y -CONFIG_USB_HIDDEV=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -2620,6 +2718,8 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -2647,6 +2747,8 @@ CONFIG_USB_U132_HCD=m CONFIG_USB_SL811_HCD=m # CONFIG_USB_SL811_CS is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # CONFIG_USB_MUSB_HDRC is not set # @@ -2655,6 +2757,7 @@ CONFIG_USB_SL811_HCD=m CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -2676,7 +2779,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y CONFIG_USB_STORAGE_ONETOUCH=y CONFIG_USB_STORAGE_KARMA=y -# CONFIG_USB_STORAGE_SIERRA is not set CONFIG_USB_STORAGE_CYPRESS_ATACB=y # CONFIG_USB_LIBUSUAL is not set @@ -2741,6 +2843,7 @@ CONFIG_USB_SERIAL_DEBUG=m CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m # CONFIG_USB_RIO500 is not set CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m @@ -2762,12 +2865,14 @@ CONFIG_USB_TRANCEVIBRATOR=m CONFIG_USB_IOWARRIOR=m # CONFIG_USB_TEST is not set CONFIG_USB_ISIGHTFW=m +CONFIG_USB_VST=m CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m CONFIG_USB_UEAGLEATM=m CONFIG_USB_XUSBATM=m # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -2787,6 +2892,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_IDE_DISK=y CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_ACCESSIBILITY=y CONFIG_A11Y_BRAILLE_CONSOLE=y @@ -2837,12 +2943,15 @@ CONFIG_RTC_DRV_FM3130=m # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set CONFIG_RTC_DRV_DS1511=m CONFIG_RTC_DRV_DS1553=m CONFIG_RTC_DRV_DS1742=m CONFIG_RTC_DRV_STK17TA8=m # CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_BQ4802 is not set CONFIG_RTC_DRV_V3020=m # @@ -2862,7 +2971,10 @@ CONFIG_KS0108_DELAY=2 CONFIG_UIO=m CONFIG_UIO_CIF=m CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m CONFIG_UIO_SMX=m +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_STAGING is not set # # File systems @@ -2872,20 +2984,21 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=m CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4DEV_FS=m -CONFIG_EXT4DEV_FS_XATTR=y -CONFIG_EXT4DEV_FS_POSIX_ACL=y -CONFIG_EXT4DEV_FS_SECURITY=y +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_FS_XIP=y CONFIG_JBD=m # CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=m +CONFIG_JBD2=y CONFIG_JBD2_DEBUG=y -CONFIG_FS_MBCACHE=m +CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set CONFIG_REISERFS_PROC_INFO=y @@ -2898,6 +3011,7 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y @@ -2911,6 +3025,7 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCFS2_FS_STATS=y # CONFIG_OCFS2_DEBUG_MASKLOG is not set # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -2950,6 +3065,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y @@ -2996,17 +3112,18 @@ CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=m CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y # CONFIG_CIFS_DEBUG2 is not set CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_CIFS_UPCALL=y CONFIG_CIFS_DFS_UPCALL=y CONFIG_NCP_FS=m CONFIG_NCPFS_PACKET_SIGNING=y @@ -3084,15 +3201,13 @@ CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m CONFIG_DLM=m CONFIG_DLM_DEBUG=y -CONFIG_QE_GPIO=y # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m -CONFIG_CRC16=m +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y @@ -3157,28 +3272,38 @@ CONFIG_DEBUG_SG=y CONFIG_FRAME_POINTER=y CONFIG_BOOT_PRINTK_DELAY=y # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set CONFIG_FAULT_INJECTION=y CONFIG_FAILSLAB=y CONFIG_FAIL_PAGE_ALLOC=y CONFIG_FAIL_MAKE_REQUEST=y +CONFIG_FAIL_IO_TIMEOUT=y CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y CONFIG_TRACING=y -CONFIG_FTRACE=y + +# +# Tracers +# +CONFIG_FUNCTION_TRACER=y CONFIG_SCHED_TRACER=y CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_DYNAMIC_FTRACE=y +# CONFIG_BOOT_TRACER is not set +CONFIG_STACK_TRACER=y # CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set # CONFIG_BUILD_DOCSRC is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -3186,6 +3311,7 @@ CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_DEBUG_STACK_USAGE=y # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set CONFIG_XMON=y # CONFIG_XMON_DEFAULT is not set CONFIG_XMON_DISASSEMBLY=y @@ -3202,6 +3328,7 @@ CONFIG_BOOTX_TEXT=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_SECURITY_FILE_CAPABILITIES=y @@ -3226,10 +3353,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -3303,6 +3432,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_HIFN_795X=m CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y diff --git a/arch/powerpc/configs/pq2fads_defconfig b/arch/powerpc/configs/pq2fads_defconfig index 7e17862c38b8..228099d77c3b 100644 --- a/arch/powerpc/configs/pq2fads_defconfig +++ b/arch/powerpc/configs/pq2fads_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:13 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:47 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -48,13 +48,11 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_PPC_OF=y CONFIG_OF=y -CONFIG_PPC_UDBG_16550=y +# CONFIG_PPC_UDBG_16550 is not set # CONFIG_GENERIC_TBSYNC is not set CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_DEFAULT_UIMAGE=y -CONFIG_HIBERNATE_32=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -94,7 +92,6 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y @@ -104,7 +101,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -117,10 +116,7 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -146,6 +142,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -153,39 +150,36 @@ CONFIG_CLASSIC_RCU=y CONFIG_PPC_MULTIPLATFORM=y CONFIG_CLASSIC32=y # CONFIG_PPC_CHRP is not set -# CONFIG_PPC_PMAC is not set # CONFIG_MPC5121_ADS is not set # CONFIG_MPC5121_GENERIC is not set # CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_CELL_NATIVE is not set CONFIG_PPC_82xx=y # CONFIG_MPC8272_ADS is not set CONFIG_PQ2FADS=y # CONFIG_EP8248E is not set +# CONFIG_MGCOGE is not set CONFIG_PQ2ADS=y CONFIG_8260=y CONFIG_PQ2_ADS_PCI_PIC=y # CONFIG_PPC_83xx is not set # CONFIG_PPC_86xx is not set # CONFIG_EMBEDDED6xx is not set -CONFIG_PPC_NATIVE=y -# CONFIG_UDBG_RTAS_CONSOLE is not set # CONFIG_IPIC is not set -CONFIG_MPIC=y +# CONFIG_MPIC is not set # CONFIG_MPIC_WEIRD is not set -CONFIG_PPC_I8259=y -CONFIG_PPC_RTAS=y -# CONFIG_RTAS_ERROR_LOGGING is not set -CONFIG_RTAS_PROC=y +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set # CONFIG_MMIO_NVRAM is not set -CONFIG_PPC_MPC106=y +# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PPC601_SYNC_FIX is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set CONFIG_CPM2=y # CONFIG_FSL_ULI1575 is not set CONFIG_CPM=y @@ -208,6 +202,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -217,15 +213,15 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -237,7 +233,6 @@ CONFIG_ISA_DMA_API=y # # Bus options # -# CONFIG_ISA is not set CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_FSL_SOC=y @@ -250,7 +245,7 @@ CONFIG_PCI_8260=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -306,7 +301,6 @@ CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_IP_VS is not set CONFIG_IPV6=y # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -333,10 +327,12 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -363,11 +359,10 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -473,7 +468,6 @@ CONFIG_OF_GPIO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set -# CONFIG_MAC_FLOPPY is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -494,17 +488,16 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -539,7 +532,6 @@ CONFIG_IDE_PROC_FS=y # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set # CONFIG_BLK_DEV_TC86C001 is not set -# CONFIG_BLK_DEV_IDE_PMAC is not set # CONFIG_BLK_DEV_IDEDMA is not set # @@ -590,8 +582,6 @@ CONFIG_MDIO_BITBANG=y # CONFIG_MDIO_OF_GPIO is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_MACE is not set -# CONFIG_BMAC is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set @@ -602,8 +592,12 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set +# CONFIG_ATL2 is not set CONFIG_FS_ENET=y # CONFIG_FS_ENET_HAS_SCC is not set CONFIG_FS_ENET_HAS_FCC=y @@ -626,18 +620,23 @@ CONFIG_NETDEV_1000=y # CONFIG_GIANFAR is not set # CONFIG_MV643XX_ETH is not set # CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -698,6 +697,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set @@ -739,21 +739,12 @@ CONFIG_DEVKMEM=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_PMACZILOG is not set CONFIG_SERIAL_CPM=y CONFIG_SERIAL_CPM_CONSOLE=y -CONFIG_SERIAL_CPM_SCC1=y -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -CONFIG_SERIAL_CPM_SCC4=y -# CONFIG_SERIAL_CPM_SMC1 is not set -# CONFIG_SERIAL_CPM_SMC2 is not set # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_BRIQ_PANEL is not set -# CONFIG_HVC_RTAS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_NVRAM is not set @@ -802,6 +793,14 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set + # # Multimedia devices # @@ -850,20 +849,22 @@ CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set # CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set CONFIG_USB_GADGET_M66592=y CONFIG_USB_M66592=y -# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_NET2280 is not set # CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set @@ -883,6 +884,7 @@ CONFIG_USB_ETH_RNDIS=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -894,11 +896,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -928,6 +932,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1030,7 +1035,6 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1084,15 +1088,23 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_STACKOVERFLOW is not set @@ -1100,6 +1112,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set # CONFIG_XMON is not set # CONFIG_IRQSTACKS is not set CONFIG_BDI_SWITCH=y @@ -1111,14 +1124,19 @@ CONFIG_BDI_SWITCH=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -1185,6 +1203,11 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_CRYPTO_DEV_TALITOS is not set diff --git a/arch/powerpc/configs/prpmc2800_defconfig b/arch/powerpc/configs/prpmc2800_defconfig index 01b54eac1ff6..6046dc0cbd82 100644 --- a/arch/powerpc/configs/prpmc2800_defconfig +++ b/arch/powerpc/configs/prpmc2800_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:14 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:48 2008 # # CONFIG_PPC64 is not set @@ -24,7 +24,7 @@ CONFIG_NOT_COHERENT_CACHE=y CONFIG_CHECK_CACHE_COHERENCY=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -110,7 +110,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -123,10 +125,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -153,6 +151,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -210,6 +209,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -224,15 +225,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -253,7 +254,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -323,6 +324,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -343,11 +345,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -478,17 +479,16 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -721,6 +721,9 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -745,11 +748,11 @@ CONFIG_8139TOO=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -767,18 +770,22 @@ CONFIG_MV643XX_ETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -813,7 +820,7 @@ CONFIG_NETDEV_10000=y # Input device support # CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_POLLDEV is not set # @@ -1025,6 +1032,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1073,9 +1091,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_ZEROPLUS_FF=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1092,6 +1137,8 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1111,6 +1158,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1118,6 +1167,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1146,6 +1196,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1163,7 +1214,9 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1209,12 +1262,15 @@ CONFIG_RTC_DRV_MAX6900=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1223,6 +1279,7 @@ CONFIG_RTC_DRV_MAX6900=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1234,12 +1291,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1269,6 +1327,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1304,6 +1363,7 @@ CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1340,7 +1400,6 @@ CONFIG_MSDOS_PARTITION=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1370,13 +1429,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1388,12 +1449,14 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1465,6 +1528,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_PPC_CLOCK is not set diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index e77c5e7a0be2..1e520ab65118 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Tue Aug 26 13:31:07 2008 +# Linux kernel version: 2.6.28-rc3 +# Tue Nov 11 19:37:06 2008 # CONFIG_PPC64=y @@ -22,7 +22,7 @@ CONFIG_SMP=y CONFIG_NR_CPUS=128 CONFIG_64BIT=y CONFIG_WORD_SIZE=64 -CONFIG_PPC_MERGE=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -86,6 +86,7 @@ CONFIG_LOG_BUF_SHIFT=17 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_NS=y +CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_DEVICE=y CONFIG_CPUSETS=y # CONFIG_GROUP_SCHED is not set @@ -123,12 +124,15 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y CONFIG_MARKERS=y CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y @@ -141,8 +145,6 @@ CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_ATTRS=y CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -175,6 +177,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y +CONFIG_PPC_MSI_BITMAP=y # # Platform support @@ -237,6 +241,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_IOMMU_VMERGE=y @@ -246,7 +252,6 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set # CONFIG_PHYP_DUMP is not set CONFIG_IRQ_ALL_CPUS=y CONFIG_NUMA=y @@ -262,7 +267,6 @@ CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y CONFIG_HAVE_MEMORY_PRESENT=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -271,8 +275,10 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_NODES_SPAN_OTHER_NODES=y # CONFIG_PPC_HAS_HASH_64K is not set # CONFIG_PPC_64K_PAGES is not set @@ -307,6 +313,7 @@ CONFIG_HOTPLUG_PCI=m CONFIG_HOTPLUG_PCI_RPA=m CONFIG_HOTPLUG_PCI_RPA_DLPAR=m # CONFIG_HAS_RAPIDIO is not set +# CONFIG_RELOCATABLE is not set CONFIG_PAGE_OFFSET=0xc000000000000000 CONFIG_KERNEL_START=0xc000000000000000 CONFIG_PHYSICAL_START=0x00000000 @@ -351,7 +358,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -383,9 +389,10 @@ CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m @@ -396,19 +403,22 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -416,20 +426,20 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -437,8 +447,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_UDPLITE=m CONFIG_NF_NAT_FTP=m @@ -456,6 +466,7 @@ CONFIG_NF_NAT_TFTP=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=y @@ -479,14 +490,8 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -546,19 +551,18 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -696,6 +700,7 @@ CONFIG_SATA_PMP=y # CONFIG_ATA_SFF is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -765,6 +770,9 @@ CONFIG_IBMVETH=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=y # CONFIG_AMD8111_ETH is not set @@ -786,12 +794,12 @@ CONFIG_E100=y # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set # CONFIG_NET_POCKET is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y CONFIG_ACENIC=y CONFIG_ACENIC_OMIT_TIGON_I=y # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set @@ -808,19 +816,23 @@ CONFIG_TIGON3=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set CONFIG_EHEA=y +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set CONFIG_IXGB=m CONFIG_S2IO=m # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set CONFIG_TR=y CONFIG_IBMOL=y @@ -902,6 +914,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set @@ -917,6 +930,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # @@ -1076,6 +1090,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -1103,6 +1128,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -1146,6 +1172,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -1157,6 +1184,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_CARMINE is not set CONFIG_FB_IBM_GXT4500=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_ILI9320 is not set @@ -1198,9 +1226,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1217,6 +1272,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1236,6 +1293,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1243,6 +1302,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1264,7 +1324,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_ALAUDA is not set CONFIG_USB_STORAGE_ONETOUCH=y # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -1286,6 +1345,7 @@ CONFIG_USB_STORAGE_ONETOUCH=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1303,7 +1363,9 @@ CONFIG_USB_STORAGE_ONETOUCH=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1331,6 +1393,7 @@ CONFIG_INFINIBAND_SRP=m # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1340,14 +1403,20 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_XIP=y CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y # CONFIG_REISERFS_CHECK is not set @@ -1361,6 +1430,7 @@ CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set CONFIG_XFS_POSIX_ACL=y @@ -1372,6 +1442,7 @@ CONFIG_OCFS2_FS_O2CB=m CONFIG_OCFS2_FS_STATS=y CONFIG_OCFS2_DEBUG_MASKLOG=y # CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_COMPAT_JBD is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1405,6 +1476,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1449,6 +1521,7 @@ CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_XPRT_RDMA=m +# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set @@ -1514,9 +1587,8 @@ CONFIG_NLS_ISO8859_1=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_CRC32=y @@ -1580,21 +1652,31 @@ CONFIG_DEBUG_MEMORY_INIT=y CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y CONFIG_TRACING=y -# CONFIG_FTRACE is not set + +# +# Tracers +# +CONFIG_FUNCTION_TRACER=y CONFIG_IRQSOFF_TRACER=y CONFIG_SCHED_TRACER=y CONFIG_CONTEXT_SWITCH_TRACER=y +# CONFIG_BOOT_TRACER is not set +CONFIG_STACK_TRACER=y # CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1604,6 +1686,7 @@ CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_HCALL_STATS=y # CONFIG_CODE_PATCHING_SELFTEST is not set # CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set CONFIG_XMON=y CONFIG_XMON_DEFAULT=y CONFIG_XMON_DISASSEMBLY=y @@ -1618,16 +1701,19 @@ CONFIG_VIRQ_DEBUG=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1701,6 +1787,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_PPC_CLOCK is not set # CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig index 4340cc1c5b6a..b3f5671972a9 100644 --- a/arch/powerpc/configs/storcenter_defconfig +++ b/arch/powerpc/configs/storcenter_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 00:52:16 2008 +# Linux kernel version: 2.6.28-rc3 +# Sat Nov 8 12:39:48 2008 # # CONFIG_PPC64 is not set @@ -22,7 +22,7 @@ CONFIG_PPC_STD_MMU_32=y # CONFIG_SMP is not set CONFIG_PPC32=y CONFIG_WORD_SIZE=32 -CONFIG_PPC_MERGE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_MMU=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_TIME=y @@ -102,7 +102,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -115,10 +117,6 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -151,6 +149,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Platform support @@ -190,13 +189,13 @@ CONFIG_MPIC=y # CONFIG_GENERIC_IOMAP is not set # CONFIG_CPU_FREQ is not set # CONFIG_TAU is not set +# CONFIG_QUICC_ENGINE is not set # CONFIG_FSL_ULI1575 is not set # # Kernel options # # CONFIG_HIGHMEM is not set -# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -210,6 +209,8 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y @@ -224,15 +225,15 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y CONFIG_CMDLINE_BOOL=y @@ -255,7 +256,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -318,6 +319,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -338,11 +340,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -471,18 +472,17 @@ CONFIG_MISC_DEVICES=y # CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -605,6 +605,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y @@ -636,6 +637,7 @@ CONFIG_DUMMY=m # CONFIG_VETH is not set # CONFIG_ARCNET is not set # CONFIG_NET_ETHERNET is not set +CONFIG_MII=y CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -658,6 +660,7 @@ CONFIG_R8169=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -827,6 +830,17 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set # # Multimedia devices @@ -877,6 +891,8 @@ CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -897,6 +913,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -904,6 +922,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -924,7 +943,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SIERRA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set @@ -945,6 +963,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -962,7 +981,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1008,12 +1029,15 @@ CONFIG_RTC_DRV_DS1307=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1022,6 +1046,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_PPC is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1033,12 +1058,13 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -1072,6 +1098,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1177,7 +1204,6 @@ CONFIG_NLS_UTF8=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y @@ -1209,13 +1235,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_IRQSTACKS is not set @@ -1227,6 +1255,7 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y diff --git a/arch/powerpc/include/asm/ftrace.h b/arch/powerpc/include/asm/ftrace.h index de921326cca8..b298f7a631e6 100644 --- a/arch/powerpc/include/asm/ftrace.h +++ b/arch/powerpc/include/asm/ftrace.h @@ -1,7 +1,7 @@ #ifndef _ASM_POWERPC_FTRACE #define _ASM_POWERPC_FTRACE -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #define MCOUNT_ADDR ((long)(_mcount)) #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ diff --git a/arch/powerpc/include/asm/immap_cpm2.h b/arch/powerpc/include/asm/immap_cpm2.h index 4080bab0468c..d4f069bf0e57 100644 --- a/arch/powerpc/include/asm/immap_cpm2.h +++ b/arch/powerpc/include/asm/immap_cpm2.h @@ -554,14 +554,11 @@ typedef struct usb_ctlr { u8 usb_usadr; u8 usb_uscom; u8 res1[1]; - u16 usb_usep1; - u16 usb_usep2; - u16 usb_usep3; - u16 usb_usep4; + __be16 usb_usep[4]; u8 res2[4]; - u16 usb_usber; + __be16 usb_usber; u8 res3[2]; - u16 usb_usbmr; + __be16 usb_usbmr; u8 usb_usbs; u8 res4[7]; } usb_cpm2_t; diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 3c2fced3ac22..c346d0bcd230 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -215,10 +215,7 @@ struct usb_ctlr { u8 usb_usadr; u8 usb_uscom; u8 res1[1]; - __be16 usb_usep1; - __be16 usb_usep2; - __be16 usb_usep3; - __be16 usb_usep4; + __be16 usb_usep[4]; u8 res2[4]; __be16 usb_usber; u8 res3[2]; diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h index 51ecfef8d843..7464c0daddd1 100644 --- a/arch/powerpc/include/asm/iommu.h +++ b/arch/powerpc/include/asm/iommu.h @@ -92,13 +92,14 @@ extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl, unsigned long mask, gfp_t flag, int node); extern void iommu_free_coherent(struct iommu_table *tbl, size_t size, void *vaddr, dma_addr_t dma_handle); -extern dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl, - void *vaddr, size_t size, unsigned long mask, - enum dma_data_direction direction, - struct dma_attrs *attrs); -extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction, - struct dma_attrs *attrs); +extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl, + struct page *page, unsigned long offset, + size_t size, unsigned long mask, + enum dma_data_direction direction, + struct dma_attrs *attrs); +extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle, + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs); extern void iommu_init_early_pSeries(void); extern void iommu_init_early_iSeries(void); diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h index a503da9d56f3..b07ebb9784d3 100644 --- a/arch/powerpc/include/asm/kdump.h +++ b/arch/powerpc/include/asm/kdump.h @@ -9,12 +9,6 @@ * Reserve to the end of the FWNMI area, see head_64.S */ #define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */ -/* - * Used to differentiate between relocatable kdump kernel and other - * kernels - */ -#define KDUMP_SIGNATURE 0xfeed1234 - #ifdef CONFIG_CRASH_DUMP #define KDUMP_TRAMPOLINE_START 0x0100 @@ -26,8 +20,6 @@ #ifndef __ASSEMBLY__ -extern unsigned long __kdump_flag; - #if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_RELOCATABLE) extern void reserve_kdump_trampoline(void); extern void setup_kdump_trampoline(void); diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h index 8931ba729d2b..bb62ad876de3 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h @@ -104,4 +104,6 @@ static inline void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 new_pid) } } +extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu); + #endif /* __POWERPC_KVM_PPC_H__ */ diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index 5a441742ffba..68b752626808 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -280,7 +280,6 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access, extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, unsigned long pstart, unsigned long prot, int psize, int ssize); -extern void set_huge_psize(int psize); extern void add_gpage(unsigned long addr, unsigned long page_size, unsigned long number_of_pages); extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index 34d9ac433ace..c2ccca53b991 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -355,6 +355,8 @@ struct mpic #define MPIC_NO_BIAS 0x00000400 /* Ignore NIRQS as reported by FRR */ #define MPIC_BROKEN_FRR_NIRQS 0x00000800 +/* Destination only supports a single CPU at a time */ +#define MPIC_SINGLE_DEST_CPU 0x00001000 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 39d547fde956..57a2a494886b 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -208,6 +208,8 @@ extern void pcibios_setup_new_device(struct pci_dev *dev); extern void pcibios_claim_one_bus(struct pci_bus *b); +extern void pcibios_allocate_bus_resources(struct pci_bus *bus); + extern void pcibios_resource_survey(void); extern struct pci_controller *init_phb_dynamic(struct device_node *dn); diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index 280a90cc9894..c9c678fb2538 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -55,8 +55,6 @@ struct pt_regs { #ifdef __powerpc64__ -#define __ARCH_WANT_COMPAT_SYS_PTRACE - #define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ #define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ #define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index fdb58253fa5b..92673b43858d 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -12,7 +12,7 @@ CFLAGS_prom_init.o += -fPIC CFLAGS_btext.o += -fPIC endif -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER # Do not trace early boot code CFLAGS_REMOVE_cputable.o = -pg -mno-sched-epilog CFLAGS_REMOVE_prom_init.o = -pg -mno-sched-epilog diff --git a/arch/powerpc/kernel/cpu_setup_44x.S b/arch/powerpc/kernel/cpu_setup_44x.S index 80cac984d85d..10b4ab1008af 100644 --- a/arch/powerpc/kernel/cpu_setup_44x.S +++ b/arch/powerpc/kernel/cpu_setup_44x.S @@ -34,7 +34,13 @@ _GLOBAL(__setup_cpu_440grx) blr _GLOBAL(__setup_cpu_460ex) _GLOBAL(__setup_cpu_460gt) - b __init_fpu_44x + mflr r4 + bl __init_fpu_44x + bl __fixup_440A_mcheck + mtlr r4 + blr + +_GLOBAL(__setup_cpu_440x5) _GLOBAL(__setup_cpu_440gx) _GLOBAL(__setup_cpu_440spe) b __fixup_440A_mcheck diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index b1eb834bc0fc..7e8719504f39 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -39,6 +39,7 @@ extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec); +extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); @@ -1500,6 +1501,8 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_user_features = COMMON_USER_BOOKE, .icache_bsize = 32, .dcache_bsize = 32, + .cpu_setup = __setup_cpu_440x5, + .machine_check = machine_check_440A, .platform = "ppc440", }, { /* 460EX */ diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c index 49248f89ce23..14183af1b3fb 100644 --- a/arch/powerpc/kernel/dma-iommu.c +++ b/arch/powerpc/kernel/dma-iommu.c @@ -30,28 +30,26 @@ static void dma_iommu_free_coherent(struct device *dev, size_t size, } /* Creates TCEs for a user provided buffer. The user buffer must be - * contiguous real kernel storage (not vmalloc). The address of the buffer - * passed here is the kernel (virtual) address of the buffer. The buffer - * need not be page aligned, the dma_addr_t returned will point to the same - * byte within the page as vaddr. + * contiguous real kernel storage (not vmalloc). The address passed here + * comprises a page address and offset into that page. The dma_addr_t + * returned will point to the same byte within the page as was passed in. */ -static dma_addr_t dma_iommu_map_single(struct device *dev, void *vaddr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static dma_addr_t dma_iommu_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { - return iommu_map_single(dev, dev->archdata.dma_data, vaddr, size, - device_to_mask(dev), direction, attrs); + return iommu_map_page(dev, dev->archdata.dma_data, page, offset, size, + device_to_mask(dev), direction, attrs); } -static void dma_iommu_unmap_single(struct device *dev, dma_addr_t dma_handle, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static void dma_iommu_unmap_page(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) { - iommu_unmap_single(dev->archdata.dma_data, dma_handle, size, direction, - attrs); + iommu_unmap_page(dev->archdata.dma_data, dma_handle, size, direction, + attrs); } @@ -94,10 +92,10 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask) struct dma_mapping_ops dma_iommu_ops = { .alloc_coherent = dma_iommu_alloc_coherent, .free_coherent = dma_iommu_free_coherent, - .map_single = dma_iommu_map_single, - .unmap_single = dma_iommu_unmap_single, .map_sg = dma_iommu_map_sg, .unmap_sg = dma_iommu_unmap_sg, .dma_supported = dma_iommu_dma_supported, + .map_page = dma_iommu_map_page, + .unmap_page = dma_iommu_unmap_page, }; EXPORT_SYMBOL(dma_iommu_ops); diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index 1562daf8839a..3a6eaa876ee1 100644 --- a/arch/powerpc/kernel/dma.c +++ b/arch/powerpc/kernel/dma.c @@ -75,6 +75,7 @@ static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, for_each_sg(sgl, sg, nents, i) { sg->dma_address = sg_phys(sg) + get_dma_direct_offset(dev); sg->dma_length = sg->length; + __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction); } return nents; diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 1cbbf7033641..7ecc0d1855c3 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -1158,7 +1158,7 @@ machine_check_in_rtas: #endif /* CONFIG_PPC_RTAS */ -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE _GLOBAL(mcount) _GLOBAL(_mcount) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index fd8b4bae9b04..e0bcf9354286 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -57,12 +57,18 @@ system_call_common: beq- 1f ld r1,PACAKSAVE(r13) 1: std r10,0(r1) - crclr so std r11,_NIP(r1) std r12,_MSR(r1) std r0,GPR0(r1) std r10,GPR1(r1) ACCOUNT_CPU_USER_ENTRY(r10, r11) + /* + * This "crclr so" clears CR0.SO, which is the error indication on + * return from this system call. There must be no cmp instruction + * between it and the "mfcr r9" below, otherwise if XER.SO is set, + * CR0.SO will get set, causing all system calls to appear to fail. + */ + crclr so std r2,GPR2(r1) std r3,GPR3(r1) std r4,GPR4(r1) @@ -884,7 +890,7 @@ _GLOBAL(enter_prom) mtlr r0 blr -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE _GLOBAL(mcount) _GLOBAL(_mcount) diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c index 3855ceb937b0..f4b006ed0ab1 100644 --- a/arch/powerpc/kernel/ftrace.c +++ b/arch/powerpc/kernel/ftrace.c @@ -28,17 +28,17 @@ static unsigned int ftrace_nop = 0x60000000; #endif -static unsigned int notrace ftrace_calc_offset(long ip, long addr) +static unsigned int ftrace_calc_offset(long ip, long addr) { return (int)(addr - ip); } -notrace unsigned char *ftrace_nop_replace(void) +unsigned char *ftrace_nop_replace(void) { return (char *)&ftrace_nop; } -notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) { static unsigned int op; @@ -68,7 +68,7 @@ notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) # define _ASM_PTR " .long " #endif -notrace int +int ftrace_modify_code(unsigned long ip, unsigned char *old_code, unsigned char *new_code) { @@ -113,7 +113,7 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code, return faulted; } -notrace int ftrace_update_ftrace_func(ftrace_func_t func) +int ftrace_update_ftrace_func(ftrace_func_t func) { unsigned long ip = (unsigned long)(&ftrace_call); unsigned char old[MCOUNT_INSN_SIZE], *new; @@ -126,23 +126,6 @@ notrace int ftrace_update_ftrace_func(ftrace_func_t func) return ret; } -notrace int ftrace_mcount_set(unsigned long *data) -{ - unsigned long ip = (long)(&mcount_call); - unsigned long *addr = data; - unsigned char old[MCOUNT_INSN_SIZE], *new; - - /* - * Replace the mcount stub with a pointer to the - * ip recorder function. - */ - memcpy(old, &mcount_call, MCOUNT_INSN_SIZE); - new = ftrace_call_replace(ip, *addr); - *addr = ftrace_modify_code(ip, old, new); - - return 0; -} - int __init ftrace_dyn_arch_init(void *data) { /* This is running in kstop_machine */ diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 69489bd3210c..b4bcf5a930fa 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -97,12 +97,6 @@ __secondary_hold_spinloop: __secondary_hold_acknowledge: .llong 0x0 - /* This flag is set by purgatory if we should be a kdump kernel. */ - /* Do not move this variable as purgatory knows about it. */ - .globl __kdump_flag -__kdump_flag: - .llong 0x0 - #ifdef CONFIG_PPC_ISERIES /* * At offset 0x20, there is a pointer to iSeries LPAR data. @@ -112,6 +106,20 @@ __kdump_flag: .llong hvReleaseData-KERNELBASE #endif /* CONFIG_PPC_ISERIES */ +#ifdef CONFIG_CRASH_DUMP + /* This flag is set to 1 by a loader if the kernel should run + * at the loaded address instead of the linked address. This + * is used by kexec-tools to keep the the kdump kernel in the + * crash_kernel region. The loader is responsible for + * observing the alignment requirement. + */ + /* Do not move this variable as kexec-tools knows about it. */ + . = 0x5c + .globl __run_at_load +__run_at_load: + .long 0x72756e30 /* "run0" -- relocate to 0 by default */ +#endif + . = 0x60 /* * The following code is used to hold secondary processors @@ -1391,8 +1399,8 @@ _STATIC(__after_prom_start) lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ sldi r25,r25,32 #ifdef CONFIG_CRASH_DUMP - ld r7,__kdump_flag-_stext(r26) - cmpldi cr0,r7,1 /* kdump kernel ? - stay where we are */ + lwz r7,__run_at_load-_stext(r26) + cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */ bne 1f add r25,r25,r26 #endif @@ -1416,11 +1424,11 @@ _STATIC(__after_prom_start) #ifdef CONFIG_CRASH_DUMP /* * Check if the kernel has to be running as relocatable kernel based on the - * variable __kdump_flag, if it is set the kernel is treated as relocatable + * variable __run_at_load, if it is set the kernel is treated as relocatable * kernel, otherwise it will be moved to PHYSICAL_START */ - ld r7,__kdump_flag-_stext(r26) - cmpldi cr0,r7,1 + lwz r7,__run_at_load-_stext(r26) + cmplwi cr0,r7,1 bne 3f li r5,__end_interrupts - _stext /* just copy interrupts */ diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c index a06362223f8d..64299d28f364 100644 --- a/arch/powerpc/kernel/ibmebus.c +++ b/arch/powerpc/kernel/ibmebus.c @@ -79,20 +79,21 @@ static void ibmebus_free_coherent(struct device *dev, kfree(vaddr); } -static dma_addr_t ibmebus_map_single(struct device *dev, - void *ptr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static dma_addr_t ibmebus_map_page(struct device *dev, + struct page *page, + unsigned long offset, + size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { - return (dma_addr_t)(ptr); + return (dma_addr_t)(page_address(page) + offset); } -static void ibmebus_unmap_single(struct device *dev, - dma_addr_t dma_addr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static void ibmebus_unmap_page(struct device *dev, + dma_addr_t dma_addr, + size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { return; } @@ -129,11 +130,11 @@ static int ibmebus_dma_supported(struct device *dev, u64 mask) static struct dma_mapping_ops ibmebus_dma_ops = { .alloc_coherent = ibmebus_alloc_coherent, .free_coherent = ibmebus_free_coherent, - .map_single = ibmebus_map_single, - .unmap_single = ibmebus_unmap_single, .map_sg = ibmebus_map_sg, .unmap_sg = ibmebus_unmap_sg, .dma_supported = ibmebus_dma_supported, + .map_page = ibmebus_map_page, + .unmap_page = ibmebus_unmap_page, }; static int ibmebus_match_path(struct device *dev, void *data) diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index 3857d7e2af0c..1bfa706b96e7 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -460,7 +461,7 @@ void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, static void iommu_table_clear(struct iommu_table *tbl) { - if (!__kdump_flag) { + if (!is_kdump_kernel()) { /* Clear the table in case firmware left allocations in it */ ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size); return; @@ -564,21 +565,23 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name) } /* Creates TCEs for a user provided buffer. The user buffer must be - * contiguous real kernel storage (not vmalloc). The address of the buffer - * passed here is the kernel (virtual) address of the buffer. The buffer - * need not be page aligned, the dma_addr_t returned will point to the same - * byte within the page as vaddr. + * contiguous real kernel storage (not vmalloc). The address passed here + * comprises a page address and offset into that page. The dma_addr_t + * returned will point to the same byte within the page as was passed in. */ -dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl, - void *vaddr, size_t size, unsigned long mask, - enum dma_data_direction direction, struct dma_attrs *attrs) +dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl, + struct page *page, unsigned long offset, size_t size, + unsigned long mask, enum dma_data_direction direction, + struct dma_attrs *attrs) { dma_addr_t dma_handle = DMA_ERROR_CODE; + void *vaddr; unsigned long uaddr; unsigned int npages, align; BUG_ON(direction == DMA_NONE); + vaddr = page_address(page) + offset; uaddr = (unsigned long)vaddr; npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE); @@ -604,9 +607,9 @@ dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl, return dma_handle; } -void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction, - struct dma_attrs *attrs) +void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle, + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) { unsigned int npages; diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c index e6efec788c4d..3c4ca046e854 100644 --- a/arch/powerpc/kernel/machine_kexec_64.c +++ b/arch/powerpc/kernel/machine_kexec_64.c @@ -255,14 +255,11 @@ static union thread_union kexec_stack /* Our assembly helper, in kexec_stub.S */ extern NORET_TYPE void kexec_sequence(void *newstack, unsigned long start, void *image, void *control, - void (*clear_all)(void), - unsigned long kdump_flag) ATTRIB_NORET; + void (*clear_all)(void)) ATTRIB_NORET; /* too late to fail here */ void default_machine_kexec(struct kimage *image) { - unsigned long kdump_flag = 0; - /* prepare control code if any */ /* @@ -275,8 +272,6 @@ void default_machine_kexec(struct kimage *image) if (crashing_cpu == -1) kexec_prepare_cpus(); - else - kdump_flag = KDUMP_SIGNATURE; /* switch to a staticly allocated stack. Based on irq stack code. * XXX: the task struct will likely be invalid once we do the copy! @@ -289,7 +284,7 @@ void default_machine_kexec(struct kimage *image) */ kexec_sequence(&kexec_stack, image->start, image, page_address(image->control_code_page), - ppc_md.hpte_clear_all, kdump_flag); + ppc_md.hpte_clear_all); /* NOTREACHED */ } diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 6a9b4bf0d173..5c33bc14bd9f 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -470,6 +470,8 @@ _GLOBAL(_tlbil_pid) mfspr r3,SPRN_MMUCSR0 andi. r3,r3,MMUCSR0_TLBFI@l bne 1b + msync + isync blr /* @@ -477,15 +479,20 @@ _GLOBAL(_tlbil_pid) * (no broadcast) */ _GLOBAL(_tlbil_va) + mfmsr r10 + wrteei 0 slwi r4,r4,16 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ tlbsx 0,r3 mfspr r4,SPRN_MAS1 /* check valid */ andis. r3,r4,MAS1_VALID@h - beqlr + beq 1f rlwinm r4,r4,0,1,31 mtspr SPRN_MAS1,r4 tlbwe + msync + isync +1: wrtee r10 blr #endif /* CONFIG_FSL_BOOKE */ diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index a243fd072a77..3053fe5c62f2 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -611,12 +611,10 @@ real_mode: /* assume normal blr return */ /* - * kexec_sequence(newstack, start, image, control, clear_all(), kdump_flag) + * kexec_sequence(newstack, start, image, control, clear_all()) * * does the grungy work with stack switching and real mode switches * also does simple calls to other code - * - * kdump_flag says whether the next kernel should be a kdump kernel. */ _GLOBAL(kexec_sequence) @@ -649,7 +647,7 @@ _GLOBAL(kexec_sequence) mr r29,r5 /* image (virt) */ mr r28,r6 /* control, unused */ mr r27,r7 /* clear_all() fn desc */ - mr r26,r8 /* kdump flag */ + mr r26,r8 /* spare */ lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */ /* disable interrupts, we are overwriting kernel data next */ @@ -711,6 +709,5 @@ _GLOBAL(kexec_sequence) mr r4,r30 # start, aka phys mem offset mtlr 4 li r5,0 - mr r6,r26 /* kdump_flag */ - blr /* image->start(physid, image->start, 0, kdump_flag); */ + blr /* image->start(physid, image->start, 0); */ #endif /* CONFIG_KEXEC */ diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c index 93ae5b169f41..f3c9cae01dd5 100644 --- a/arch/powerpc/kernel/of_device.c +++ b/arch/powerpc/kernel/of_device.c @@ -78,7 +78,6 @@ struct of_device *of_device_alloc(struct device_node *np, dev->dev.parent = parent; dev->dev.release = of_release_dev; dev->dev.archdata.of_node = np; - set_dev_node(&dev->dev, of_node_to_nid(np)); if (bus_id) strlcpy(dev->dev.bus_id, bus_id, BUS_ID_SIZE); diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 1ec73938a00f..f36936d9fda3 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -1239,69 +1239,66 @@ static int __init reparent_resources(struct resource *parent, * as well. */ -static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) +void pcibios_allocate_bus_resources(struct pci_bus *bus) { - struct pci_bus *bus; + struct pci_bus *b; int i; struct resource *res, *pr; - /* Depth-First Search on bus tree */ - list_for_each_entry(bus, bus_list, node) { - for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { - if ((res = bus->resource[i]) == NULL || !res->flags - || res->start > res->end) - continue; - if (bus->parent == NULL) - pr = (res->flags & IORESOURCE_IO) ? - &ioport_resource : &iomem_resource; - else { - /* Don't bother with non-root busses when - * re-assigning all resources. We clear the - * resource flags as if they were colliding - * and as such ensure proper re-allocation - * later. + for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { + if ((res = bus->resource[i]) == NULL || !res->flags + || res->start > res->end) + continue; + if (bus->parent == NULL) + pr = (res->flags & IORESOURCE_IO) ? + &ioport_resource : &iomem_resource; + else { + /* Don't bother with non-root busses when + * re-assigning all resources. We clear the + * resource flags as if they were colliding + * and as such ensure proper re-allocation + * later. + */ + if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) + goto clear_resource; + pr = pci_find_parent_resource(bus->self, res); + if (pr == res) { + /* this happens when the generic PCI + * code (wrongly) decides that this + * bridge is transparent -- paulus */ - if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) - goto clear_resource; - pr = pci_find_parent_resource(bus->self, res); - if (pr == res) { - /* this happens when the generic PCI - * code (wrongly) decides that this - * bridge is transparent -- paulus - */ - continue; - } + continue; } + } - DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " - "[0x%x], parent %p (%s)\n", - bus->self ? pci_name(bus->self) : "PHB", - bus->number, i, - (unsigned long long)res->start, - (unsigned long long)res->end, - (unsigned int)res->flags, - pr, (pr && pr->name) ? pr->name : "nil"); - - if (pr && !(pr->flags & IORESOURCE_UNSET)) { - if (request_resource(pr, res) == 0) - continue; - /* - * Must be a conflict with an existing entry. - * Move that entry (or entries) under the - * bridge resource and try again. - */ - if (reparent_resources(pr, res) == 0) - continue; - } - printk(KERN_WARNING - "PCI: Cannot allocate resource region " - "%d of PCI bridge %d, will remap\n", - i, bus->number); -clear_resource: - res->flags = 0; + DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " + "[0x%x], parent %p (%s)\n", + bus->self ? pci_name(bus->self) : "PHB", + bus->number, i, + (unsigned long long)res->start, + (unsigned long long)res->end, + (unsigned int)res->flags, + pr, (pr && pr->name) ? pr->name : "nil"); + + if (pr && !(pr->flags & IORESOURCE_UNSET)) { + if (request_resource(pr, res) == 0) + continue; + /* + * Must be a conflict with an existing entry. + * Move that entry (or entries) under the + * bridge resource and try again. + */ + if (reparent_resources(pr, res) == 0) + continue; } - pcibios_allocate_bus_resources(&bus->children); + printk(KERN_WARNING "PCI: Cannot allocate resource region " + "%d of PCI bridge %d, will remap\n", i, bus->number); +clear_resource: + res->flags = 0; } + + list_for_each_entry(b, &bus->children, node) + pcibios_allocate_bus_resources(b); } static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) @@ -1372,10 +1369,13 @@ static void __init pcibios_allocate_resources(int pass) void __init pcibios_resource_survey(void) { + struct pci_bus *b; + /* Allocate and assign resources. If we re-assign everything, then * we skip the allocate phase */ - pcibios_allocate_bus_resources(&pci_root_buses); + list_for_each_entry(b, &pci_root_buses, node) + pcibios_allocate_bus_resources(b); if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { pcibios_allocate_resources(0); diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c index 8247cff1cb3e..3502b9101e6b 100644 --- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c @@ -426,7 +426,7 @@ int pcibios_unmap_io_space(struct pci_bus *bus) pci_name(bus->self)); __flush_hash_table_range(&init_mm, res->start + _IO_BASE, - res->end - res->start + 1); + res->end + _IO_BASE + 1); return 0; } diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c index 8edc2359c419..260089dccfb0 100644 --- a/arch/powerpc/kernel/ppc_ksyms.c +++ b/arch/powerpc/kernel/ppc_ksyms.c @@ -68,7 +68,7 @@ EXPORT_SYMBOL(single_step_exception); EXPORT_SYMBOL(sys_sigreturn); #endif -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER EXPORT_SYMBOL(_mcount); #endif diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index 23e0db203329..2445945d3761 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c @@ -671,7 +671,7 @@ static struct fake_elf { u32 ignore_me; } rpadesc; } rpanote; -} fake_elf __section(.fakeelf) = { +} fake_elf = { .elfhdr = { .e_ident = { 0x7f, 'E', 'L', 'F', ELFCLASS32, ELFDATA2MSB, EV_CURRENT }, @@ -713,13 +713,13 @@ static struct fake_elf { .type = 0x12759999, .name = "IBM,RPA-Client-Config", .rpadesc = { - .lpar_affinity = 1, - .min_rmo_size = 128, /* in megabytes */ + .lpar_affinity = 0, + .min_rmo_size = 64, /* in megabytes */ .min_rmo_percent = 0, - .max_pft_size = 46, /* 2^46 bytes max PFT size */ + .max_pft_size = 48, /* 2^48 bytes max PFT size */ .splpar = 1, .min_load = ~0U, - .new_mem_def = 1 + .new_mem_def = 0 } } }; diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c index bc1fb27368af..a11d68976dc8 100644 --- a/arch/powerpc/kernel/prom_parse.c +++ b/arch/powerpc/kernel/prom_parse.c @@ -250,8 +250,11 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) * parsing */ dn = pci_device_to_OF_node(pdev); - if (dn) - return of_irq_map_one(dn, 0, out_irq); + if (dn) { + rc = of_irq_map_one(dn, 0, out_irq); + if (!rc) + return rc; + } /* Ok, we don't, time to have fun. Let's start by building up an * interrupt spec. we assume #interrupt-cells is 1, which is standard diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index 843c0af210d0..169d74cef157 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -444,9 +444,9 @@ void __init setup_system(void) if (htab_address) printk("htab_address = 0x%p\n", htab_address); printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); -#if PHYSICAL_START > 0 - printk("physical_start = 0x%lx\n", PHYSICAL_START); -#endif + if (PHYSICAL_START > 0) + printk("physical_start = 0x%lx\n", + PHYSICAL_START); printk("-----------------------------------------------------\n"); DBG(" <- setup_system()\n"); diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 3e80aa32b8b0..b13abf305996 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -410,7 +410,7 @@ inline unsigned long copy_fpr_from_user(struct task_struct *task, * altivec/spe instructions at some point. */ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, - int sigret) + int sigret, int ctx_has_vsx_region) { unsigned long msr = regs->msr; @@ -451,7 +451,7 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, * the saved MSR value to indicate that frame->mc_vregs * contains valid data */ - if (current->thread.used_vsr) { + if (current->thread.used_vsr && ctx_has_vsx_region) { __giveup_vsx(current); if (copy_vsx_to_user(&frame->mc_vsregs, current)) return 1; @@ -858,11 +858,11 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka, frame = &rt_sf->uc.uc_mcontext; addr = frame; if (vdso32_rt_sigtramp && current->mm->context.vdso_base) { - if (save_user_regs(regs, frame, 0)) + if (save_user_regs(regs, frame, 0, 1)) goto badframe; regs->link = current->mm->context.vdso_base + vdso32_rt_sigtramp; } else { - if (save_user_regs(regs, frame, __NR_rt_sigreturn)) + if (save_user_regs(regs, frame, __NR_rt_sigreturn, 1)) goto badframe; regs->link = (unsigned long) frame->tramp; } @@ -936,13 +936,26 @@ long sys_swapcontext(struct ucontext __user *old_ctx, int ctx_size, int r6, int r7, int r8, struct pt_regs *regs) { unsigned char tmp; + int ctx_has_vsx_region = 0; #ifdef CONFIG_PPC64 unsigned long new_msr = 0; - if (new_ctx && - __get_user(new_msr, &new_ctx->uc_mcontext.mc_gregs[PT_MSR])) - return -EFAULT; + if (new_ctx) { + struct mcontext __user *mcp; + u32 cmcp; + + /* + * Get pointer to the real mcontext. No need for + * access_ok since we are dealing with compat + * pointers. + */ + if (__get_user(cmcp, &new_ctx->uc_regs)) + return -EFAULT; + mcp = (struct mcontext __user *)(u64)cmcp; + if (__get_user(new_msr, &mcp->mc_gregs[PT_MSR])) + return -EFAULT; + } /* * Check that the context is not smaller than the original * size (with VMX but without VSX) @@ -956,16 +969,9 @@ long sys_swapcontext(struct ucontext __user *old_ctx, if ((ctx_size < sizeof(struct ucontext)) && (new_msr & MSR_VSX)) return -EINVAL; -#ifdef CONFIG_VSX - /* - * If userspace doesn't provide enough room for VSX data, - * but current thread has used VSX, we don't have anywhere - * to store the full context back into. - */ - if ((ctx_size < sizeof(struct ucontext)) && - (current->thread.used_vsr && old_ctx)) - return -EINVAL; -#endif + /* Does the context have enough room to store VSX data? */ + if (ctx_size >= sizeof(struct ucontext)) + ctx_has_vsx_region = 1; #else /* Context size is for future use. Right now, we only make sure * we are passed something we understand @@ -985,17 +991,17 @@ long sys_swapcontext(struct ucontext __user *old_ctx, */ mctx = (struct mcontext __user *) ((unsigned long) &old_ctx->uc_mcontext & ~0xfUL); - if (!access_ok(VERIFY_WRITE, old_ctx, sizeof(*old_ctx)) - || save_user_regs(regs, mctx, 0) + if (!access_ok(VERIFY_WRITE, old_ctx, ctx_size) + || save_user_regs(regs, mctx, 0, ctx_has_vsx_region) || put_sigset_t(&old_ctx->uc_sigmask, ¤t->blocked) || __put_user(to_user_ptr(mctx), &old_ctx->uc_regs)) return -EFAULT; } if (new_ctx == NULL) return 0; - if (!access_ok(VERIFY_READ, new_ctx, sizeof(*new_ctx)) + if (!access_ok(VERIFY_READ, new_ctx, ctx_size) || __get_user(tmp, (u8 __user *) new_ctx) - || __get_user(tmp, (u8 __user *) (new_ctx + 1) - 1)) + || __get_user(tmp, (u8 __user *) new_ctx + ctx_size - 1)) return -EFAULT; /* @@ -1196,11 +1202,11 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka, goto badframe; if (vdso32_sigtramp && current->mm->context.vdso_base) { - if (save_user_regs(regs, &frame->mctx, 0)) + if (save_user_regs(regs, &frame->mctx, 0, 1)) goto badframe; regs->link = current->mm->context.vdso_base + vdso32_sigtramp; } else { - if (save_user_regs(regs, &frame->mctx, __NR_sigreturn)) + if (save_user_regs(regs, &frame->mctx, __NR_sigreturn, 1)) goto badframe; regs->link = (unsigned long) frame->mctx.tramp; } diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index c6a8f2326b6f..e132891d3cea 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -74,7 +74,8 @@ static const char fmt64[] = KERN_INFO \ */ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, - int signr, sigset_t *set, unsigned long handler) + int signr, sigset_t *set, unsigned long handler, + int ctx_has_vsx_region) { /* When CONFIG_ALTIVEC is set, we _always_ setup v_regs even if the * process never used altivec yet (MSR_VEC is zero in pt_regs of @@ -121,7 +122,7 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, * then out to userspace. Update v_regs to point after the * VMX data. */ - if (current->thread.used_vsr) { + if (current->thread.used_vsr && ctx_has_vsx_region) { __giveup_vsx(current); v_regs += ELF_NVRREG; err |= copy_vsx_to_user(v_regs, current); @@ -282,9 +283,10 @@ int sys_swapcontext(struct ucontext __user *old_ctx, unsigned char tmp; sigset_t set; unsigned long new_msr = 0; + int ctx_has_vsx_region = 0; if (new_ctx && - __get_user(new_msr, &new_ctx->uc_mcontext.gp_regs[PT_MSR])) + get_user(new_msr, &new_ctx->uc_mcontext.gp_regs[PT_MSR])) return -EFAULT; /* * Check that the context is not smaller than the original @@ -299,28 +301,23 @@ int sys_swapcontext(struct ucontext __user *old_ctx, if ((ctx_size < sizeof(struct ucontext)) && (new_msr & MSR_VSX)) return -EINVAL; -#ifdef CONFIG_VSX - /* - * If userspace doesn't provide enough room for VSX data, - * but current thread has used VSX, we don't have anywhere - * to store the full context back into. - */ - if ((ctx_size < sizeof(struct ucontext)) && - (current->thread.used_vsr && old_ctx)) - return -EINVAL; -#endif + /* Does the context have enough room to store VSX data? */ + if (ctx_size >= sizeof(struct ucontext)) + ctx_has_vsx_region = 1; + if (old_ctx != NULL) { - if (!access_ok(VERIFY_WRITE, old_ctx, sizeof(*old_ctx)) - || setup_sigcontext(&old_ctx->uc_mcontext, regs, 0, NULL, 0) + if (!access_ok(VERIFY_WRITE, old_ctx, ctx_size) + || setup_sigcontext(&old_ctx->uc_mcontext, regs, 0, NULL, 0, + ctx_has_vsx_region) || __copy_to_user(&old_ctx->uc_sigmask, ¤t->blocked, sizeof(sigset_t))) return -EFAULT; } if (new_ctx == NULL) return 0; - if (!access_ok(VERIFY_READ, new_ctx, sizeof(*new_ctx)) + if (!access_ok(VERIFY_READ, new_ctx, ctx_size) || __get_user(tmp, (u8 __user *) new_ctx) - || __get_user(tmp, (u8 __user *) (new_ctx + 1) - 1)) + || __get_user(tmp, (u8 __user *) new_ctx + ctx_size - 1)) return -EFAULT; /* @@ -423,7 +420,7 @@ int handle_rt_signal64(int signr, struct k_sigaction *ka, siginfo_t *info, &frame->uc.uc_stack.ss_flags); err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, signr, NULL, - (unsigned long)ka->sa.sa_handler); + (unsigned long)ka->sa.sa_handler, 1); err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); if (err) goto badframe; diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c index 86a2ffccef25..20885a38237a 100644 --- a/arch/powerpc/kernel/sysfs.c +++ b/arch/powerpc/kernel/sysfs.c @@ -717,9 +717,11 @@ static void unregister_cpu_online(unsigned int cpu) BUG_ON(!c->hotpluggable); +#ifdef CONFIG_PPC64 if (!firmware_has_feature(FW_FEATURE_ISERIES) && cpu_has_feature(CPU_FTR_SMT)) sysdev_remove_file(s, &attr_smt_snooze_delay); +#endif /* PMC stuff */ switch (cur_cpu_spec->pmc_type) { diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index 434c92a85c03..a11e6bc59b30 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -516,10 +516,10 @@ static void vio_dma_iommu_free_coherent(struct device *dev, size_t size, vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE)); } -static dma_addr_t vio_dma_iommu_map_single(struct device *dev, void *vaddr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static dma_addr_t vio_dma_iommu_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { struct vio_dev *viodev = to_vio_dev(dev); dma_addr_t ret = DMA_ERROR_CODE; @@ -529,7 +529,7 @@ static dma_addr_t vio_dma_iommu_map_single(struct device *dev, void *vaddr, return ret; } - ret = dma_iommu_ops.map_single(dev, vaddr, size, direction, attrs); + ret = dma_iommu_ops.map_page(dev, page, offset, size, direction, attrs); if (unlikely(dma_mapping_error(dev, ret))) { vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE)); atomic_inc(&viodev->cmo.allocs_failed); @@ -538,14 +538,14 @@ static dma_addr_t vio_dma_iommu_map_single(struct device *dev, void *vaddr, return ret; } -static void vio_dma_iommu_unmap_single(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static void vio_dma_iommu_unmap_page(struct device *dev, dma_addr_t dma_handle, + size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { struct vio_dev *viodev = to_vio_dev(dev); - dma_iommu_ops.unmap_single(dev, dma_handle, size, direction, attrs); + dma_iommu_ops.unmap_page(dev, dma_handle, size, direction, attrs); vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE)); } @@ -603,10 +603,11 @@ static void vio_dma_iommu_unmap_sg(struct device *dev, struct dma_mapping_ops vio_dma_mapping_ops = { .alloc_coherent = vio_dma_iommu_alloc_coherent, .free_coherent = vio_dma_iommu_free_coherent, - .map_single = vio_dma_iommu_map_single, - .unmap_single = vio_dma_iommu_unmap_single, .map_sg = vio_dma_iommu_map_sg, .unmap_sg = vio_dma_iommu_unmap_sg, + .map_page = vio_dma_iommu_map_page, + .unmap_page = vio_dma_iommu_unmap_page, + }; /** diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index b39c27ed7919..2412c056baa4 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -187,6 +187,7 @@ SECTIONS *(.machine.desc) __machine_desc_end = . ; } +#ifdef CONFIG_RELOCATABLE . = ALIGN(8); .dynsym : AT(ADDR(.dynsym) - LOAD_OFFSET) { *(.dynsym) } .dynstr : AT(ADDR(.dynstr) - LOAD_OFFSET) { *(.dynstr) } @@ -202,9 +203,7 @@ SECTIONS __rela_dyn_start = .; *(.rela*) } - - /* Fake ELF header containing RPA note; for addnote */ - .fakeelf : AT(ADDR(.fakeelf) - LOAD_OFFSET) { *(.fakeelf) } +#endif /* freed after init ends here */ . = ALIGN(PAGE_SIZE); diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c index 2e227a412bc2..ad72c6f9811f 100644 --- a/arch/powerpc/kvm/44x_tlb.c +++ b/arch/powerpc/kvm/44x_tlb.c @@ -124,6 +124,14 @@ static void kvmppc_44x_shadow_release(struct kvm_vcpu *vcpu, } } +void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu) +{ + int i; + + for (i = 0; i <= tlb_44x_hwater; i++) + kvmppc_44x_shadow_release(vcpu, i); +} + void kvmppc_tlbe_set_modified(struct kvm_vcpu *vcpu, unsigned int i) { vcpu->arch.shadow_tlb_mod[i] = 1; diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index 90a6fc422b23..fda9baada132 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -238,6 +238,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) { + kvmppc_core_destroy_mmu(vcpu); } /* Note: clearing MSR[DE] just means that the debug interrupt will not be diff --git a/arch/powerpc/lib/rheap.c b/arch/powerpc/lib/rheap.c index 29b2941cada0..45907c1dae66 100644 --- a/arch/powerpc/lib/rheap.c +++ b/arch/powerpc/lib/rheap.c @@ -556,6 +556,7 @@ unsigned long rh_alloc_fixed(rh_info_t * info, unsigned long start, int size, co be = blk->start + blk->size; if (s >= bs && e <= be) break; + blk = NULL; } if (blk == NULL) diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c index cecbbc76f624..29954dc28942 100644 --- a/arch/powerpc/mm/40x_mmu.c +++ b/arch/powerpc/mm/40x_mmu.c @@ -93,7 +93,7 @@ void __init MMU_init_hw(void) unsigned long __init mmu_mapin_ram(void) { - unsigned long v, s; + unsigned long v, s, mapped; phys_addr_t p; v = KERNELBASE; @@ -130,5 +130,17 @@ unsigned long __init mmu_mapin_ram(void) s -= LARGE_PAGE_SIZE_4M; } - return total_lowmem - s; + mapped = total_lowmem - s; + + /* If the size of RAM is not an exact power of two, we may not + * have covered RAM in its entirety with 16 and 4 MiB + * pages. Consequently, restrict the top end of RAM currently + * allocable so that calls to the LMB to allocate PTEs for "tail" + * coverage with normal-sized pages (or other reasons) do not + * attempt to allocate outside the allowed range. + */ + + __initial_memory_limit_addr = memstart_addr + mapped; + + return mapped; } diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c index a117024ab8cd..f0c3b88d50fa 100644 --- a/arch/powerpc/mm/hugetlbpage.c +++ b/arch/powerpc/mm/hugetlbpage.c @@ -507,6 +507,9 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr, { struct hstate *hstate = hstate_file(file); int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate)); + + if (!mmu_huge_psizes[mmu_psize]) + return -EINVAL; return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0); } @@ -677,7 +680,7 @@ repeat: return err; } -void set_huge_psize(int psize) +static void __init set_huge_psize(int psize) { /* Check that it is a page size supported by the hardware and * that it fits within pagetable limits. */ diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index eb505ad34a85..cf81049e1e51 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -865,10 +865,77 @@ static struct notifier_block __cpuinitdata ppc64_numa_nb = { .priority = 1 /* Must run before sched domains notifier. */ }; +static void mark_reserved_regions_for_nid(int nid) +{ + struct pglist_data *node = NODE_DATA(nid); + int i; + + for (i = 0; i < lmb.reserved.cnt; i++) { + unsigned long physbase = lmb.reserved.region[i].base; + unsigned long size = lmb.reserved.region[i].size; + unsigned long start_pfn = physbase >> PAGE_SHIFT; + unsigned long end_pfn = ((physbase + size) >> PAGE_SHIFT); + struct node_active_region node_ar; + unsigned long node_end_pfn = node->node_start_pfn + + node->node_spanned_pages; + + /* + * Check to make sure that this lmb.reserved area is + * within the bounds of the node that we care about. + * Checking the nid of the start and end points is not + * sufficient because the reserved area could span the + * entire node. + */ + if (end_pfn <= node->node_start_pfn || + start_pfn >= node_end_pfn) + continue; + + get_node_active_region(start_pfn, &node_ar); + while (start_pfn < end_pfn && + node_ar.start_pfn < node_ar.end_pfn) { + unsigned long reserve_size = size; + /* + * if reserved region extends past active region + * then trim size to active region + */ + if (end_pfn > node_ar.end_pfn) + reserve_size = (node_ar.end_pfn << PAGE_SHIFT) + - (start_pfn << PAGE_SHIFT); + /* + * Only worry about *this* node, others may not + * yet have valid NODE_DATA(). + */ + if (node_ar.nid == nid) { + dbg("reserve_bootmem %lx %lx nid=%d\n", + physbase, reserve_size, node_ar.nid); + reserve_bootmem_node(NODE_DATA(node_ar.nid), + physbase, reserve_size, + BOOTMEM_DEFAULT); + } + /* + * if reserved region is contained in the active region + * then done. + */ + if (end_pfn <= node_ar.end_pfn) + break; + + /* + * reserved region extends past the active region + * get next active region that contains this + * reserved region + */ + start_pfn = node_ar.end_pfn; + physbase = start_pfn << PAGE_SHIFT; + size = size - reserve_size; + get_node_active_region(start_pfn, &node_ar); + } + } +} + + void __init do_init_bootmem(void) { int nid; - unsigned int i; min_low_pfn = 0; max_low_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT; @@ -890,7 +957,13 @@ void __init do_init_bootmem(void) get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); - /* Allocate the node structure node local if possible */ + /* + * Allocate the node structure node local if possible + * + * Be careful moving this around, as it relies on all + * previous nodes' bootmem to be initialized and have + * all reserved areas marked. + */ NODE_DATA(nid) = careful_allocation(nid, sizeof(struct pglist_data), SMP_CACHE_BYTES, end_pfn); @@ -922,53 +995,14 @@ void __init do_init_bootmem(void) start_pfn, end_pfn); free_bootmem_with_active_regions(nid, end_pfn); - } - - /* Mark reserved regions */ - for (i = 0; i < lmb.reserved.cnt; i++) { - unsigned long physbase = lmb.reserved.region[i].base; - unsigned long size = lmb.reserved.region[i].size; - unsigned long start_pfn = physbase >> PAGE_SHIFT; - unsigned long end_pfn = ((physbase + size) >> PAGE_SHIFT); - struct node_active_region node_ar; - - get_node_active_region(start_pfn, &node_ar); - while (start_pfn < end_pfn && - node_ar.start_pfn < node_ar.end_pfn) { - unsigned long reserve_size = size; - /* - * if reserved region extends past active region - * then trim size to active region - */ - if (end_pfn > node_ar.end_pfn) - reserve_size = (node_ar.end_pfn << PAGE_SHIFT) - - (start_pfn << PAGE_SHIFT); - dbg("reserve_bootmem %lx %lx nid=%d\n", physbase, - reserve_size, node_ar.nid); - reserve_bootmem_node(NODE_DATA(node_ar.nid), physbase, - reserve_size, BOOTMEM_DEFAULT); - /* - * if reserved region is contained in the active region - * then done. - */ - if (end_pfn <= node_ar.end_pfn) - break; - - /* - * reserved region extends past the active region - * get next active region that contains this - * reserved region - */ - start_pfn = node_ar.end_pfn; - physbase = start_pfn << PAGE_SHIFT; - size = size - reserve_size; - get_node_active_region(start_pfn, &node_ar); - } - - } - - for_each_online_node(nid) + /* + * Be very careful about moving this around. Future + * calls to careful_allocation() depend on this getting + * done correctly. + */ + mark_reserved_regions_for_nid(nid); sparse_memory_present_with_active_regions(nid); + } } void __init paging_init(void) diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c index 35141a8bc3d9..25a4ec2514a3 100644 --- a/arch/powerpc/oprofile/op_model_cell.c +++ b/arch/powerpc/oprofile/op_model_cell.c @@ -582,6 +582,13 @@ static int cell_reg_setup(struct op_counter_config *ctr, num_counters = num_ctrs; + if (unlikely(num_ctrs > NR_PHYS_CTRS)) { + printk(KERN_ERR + "%s: Oprofile, number of specified events " \ + "exceeds number of physical counters\n", + __func__); + return -EIO; + } pm_regs.group_control = 0; pm_regs.debug_bus_control = 0; @@ -830,13 +837,13 @@ static int calculate_lfsr(int n) static int pm_rtas_activate_spu_profiling(u32 node) { int ret, i; - struct pm_signal pm_signal_local[NR_PHYS_CTRS]; + struct pm_signal pm_signal_local[NUM_SPUS_PER_NODE]; /* * Set up the rtas call to configure the debug bus to * route the SPU PCs. Setup the pm_signal for each SPU */ - for (i = 0; i < NUM_SPUS_PER_NODE; i++) { + for (i = 0; i < ARRAY_SIZE(pm_signal_local); i++) { pm_signal_local[i].cpu = node; pm_signal_local[i].signal_group = 41; /* spu i on word (i/2) */ @@ -848,7 +855,7 @@ static int pm_rtas_activate_spu_profiling(u32 node) ret = rtas_ibm_cbe_perftools(SUBFUNC_ACTIVATE, PASSTHRU_ENABLE, pm_signal_local, - (NUM_SPUS_PER_NODE + (ARRAY_SIZE(pm_signal_local) * sizeof(struct pm_signal))); if (unlikely(ret)) { diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig index 65730275e012..14e027f5be66 100644 --- a/arch/powerpc/platforms/40x/Kconfig +++ b/arch/powerpc/platforms/40x/Kconfig @@ -35,7 +35,7 @@ config EP405 config HCU4 bool "Hcu4" depends on 40x - default y + default n select 405GPR help This option enables support for the Nestal Maschinen HCU4 board. diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 483b65cbabae..613bf8c2e30d 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c @@ -78,7 +78,8 @@ void __init mpc85xx_ds_pic_init(void) mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET | - MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | + MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); BUG_ON(mpic == NULL); of_node_put(np); diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c index 8881c5de500d..668275d9e668 100644 --- a/arch/powerpc/platforms/86xx/pic.c +++ b/arch/powerpc/platforms/86xx/pic.c @@ -44,7 +44,8 @@ void __init mpc86xx_init_irq(void) mpic = mpic_alloc(np, res.start, MPIC_PRIMARY | MPIC_WANTS_RESET | - MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | + MPIC_SINGLE_DEST_CPU, 0, 256, " MPIC "); of_node_put(np); BUG_ON(mpic == NULL); diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index 896548ba1ca1..0ce45c2b42f8 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -95,6 +95,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) struct axon_msic *msic = get_irq_data(irq); u32 write_offset, msi; int idx; + int retry = 0; write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); @@ -102,7 +103,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) /* write_offset doesn't wrap properly, so we have to mask it */ write_offset &= MSIC_FIFO_SIZE_MASK; - while (msic->read_offset != write_offset) { + while (msic->read_offset != write_offset && retry < 100) { idx = msic->read_offset / sizeof(__le32); msi = le32_to_cpu(msic->fifo_virt[idx]); msi &= 0xFFFF; @@ -110,13 +111,37 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) pr_debug("axon_msi: woff %x roff %x msi %x\n", write_offset, msic->read_offset, msi); + if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) { + generic_handle_irq(msi); + msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); + } else { + /* + * Reading the MSIC_WRITE_OFFSET_REG does not + * reliably flush the outstanding DMA to the + * FIFO buffer. Here we were reading stale + * data, so we need to retry. + */ + udelay(1); + retry++; + pr_debug("axon_msi: invalid irq 0x%x!\n", msi); + continue; + } + + if (retry) { + pr_debug("axon_msi: late irq 0x%x, retry %d\n", + msi, retry); + retry = 0; + } + msic->read_offset += MSIC_FIFO_ENTRY_SIZE; msic->read_offset &= MSIC_FIFO_SIZE_MASK; + } - if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) - generic_handle_irq(msi); - else - pr_debug("axon_msi: invalid irq 0x%x!\n", msi); + if (retry) { + printk(KERN_WARNING "axon_msi: irq timed out\n"); + + msic->read_offset += MSIC_FIFO_ENTRY_SIZE; + msic->read_offset &= MSIC_FIFO_SIZE_MASK; } desc->chip->eoi(irq); @@ -364,6 +389,7 @@ static int axon_msi_probe(struct of_device *device, dn->full_name); goto out_free_fifo; } + memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP, NR_IRQS, &msic_host_ops, 0); @@ -387,6 +413,9 @@ static int axon_msi_probe(struct of_device *device, MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE | MSIC_CTRL_FIFO_SIZE); + msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) + & MSIC_FIFO_SIZE_MASK; + device->dev.platform_data = msic; ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs; diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c index ef92e7146215..3168272ab0d7 100644 --- a/arch/powerpc/platforms/cell/iommu.c +++ b/arch/powerpc/platforms/cell/iommu.c @@ -593,31 +593,30 @@ static void dma_fixed_free_coherent(struct device *dev, size_t size, dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle); } -static dma_addr_t dma_fixed_map_single(struct device *dev, void *ptr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) - return dma_direct_ops.map_single(dev, ptr, size, direction, - attrs); + return dma_direct_ops.map_page(dev, page, offset, size, + direction, attrs); else - return iommu_map_single(dev, cell_get_iommu_table(dev), ptr, - size, device_to_mask(dev), direction, - attrs); + return iommu_map_page(dev, cell_get_iommu_table(dev), page, + offset, size, device_to_mask(dev), + direction, attrs); } -static void dma_fixed_unmap_single(struct device *dev, dma_addr_t dma_addr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static void dma_fixed_unmap_page(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) { if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) - dma_direct_ops.unmap_single(dev, dma_addr, size, direction, - attrs); + dma_direct_ops.unmap_page(dev, dma_addr, size, direction, + attrs); else - iommu_unmap_single(cell_get_iommu_table(dev), dma_addr, size, - direction, attrs); + iommu_unmap_page(cell_get_iommu_table(dev), dma_addr, size, + direction, attrs); } static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg, @@ -652,12 +651,12 @@ static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask); struct dma_mapping_ops dma_iommu_fixed_ops = { .alloc_coherent = dma_fixed_alloc_coherent, .free_coherent = dma_fixed_free_coherent, - .map_single = dma_fixed_map_single, - .unmap_single = dma_fixed_unmap_single, .map_sg = dma_fixed_map_sg, .unmap_sg = dma_fixed_unmap_sg, .dma_supported = dma_fixed_dma_supported, .set_dma_mask = dma_set_mask_and_switch, + .map_page = dma_fixed_map_page, + .unmap_page = dma_fixed_unmap_page, }; static void cell_dma_dev_setup_fixed(struct device *dev); diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c index 665af1c4195b..7b4cefa2199b 100644 --- a/arch/powerpc/platforms/cell/ras.c +++ b/arch/powerpc/platforms/cell/ras.c @@ -13,15 +13,16 @@ #include #include #include +#include +#include +#include #include #include #include -#include #include #include #include -#include #include "ras.h" @@ -112,7 +113,7 @@ static int __init cbe_ptcal_enable_on_node(int nid, int order) int ret = -ENOMEM; unsigned long addr; - if (__kdump_flag) + if (is_kdump_kernel()) rtas_call(ptcal_stop_tok, 1, 1, NULL, nid); area = kmalloc(sizeof(*area), GFP_KERNEL); diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c index c0d86e1f56ea..9046803c8276 100644 --- a/arch/powerpc/platforms/cell/smp.c +++ b/arch/powerpc/platforms/cell/smp.c @@ -129,10 +129,15 @@ static int __init smp_iic_probe(void) return cpus_weight(cpu_possible_map); } -static void __devinit smp_iic_setup_cpu(int cpu) +static void __devinit smp_cell_setup_cpu(int cpu) { if (cpu != boot_cpuid) iic_setup_cpu(); + + /* + * change default DABRX to allow user watchpoints + */ + mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); } static DEFINE_SPINLOCK(timebase_lock); @@ -192,7 +197,7 @@ static struct smp_ops_t bpa_iic_smp_ops = { .message_pass = smp_iic_message_pass, .probe = smp_iic_probe, .kick_cpu = smp_cell_kick_cpu, - .setup_cpu = smp_iic_setup_cpu, + .setup_cpu = smp_cell_setup_cpu, .cpu_bootable = smp_cell_cpu_bootable, }; diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c index b73c369cc6f1..1b26071a86ca 100644 --- a/arch/powerpc/platforms/cell/spufs/file.c +++ b/arch/powerpc/platforms/cell/spufs/file.c @@ -390,6 +390,9 @@ static int spufs_ps_fault(struct vm_area_struct *vma, if (offset >= ps_size) return VM_FAULT_SIGBUS; + if (fatal_signal_pending(current)) + return VM_FAULT_SIGBUS; + /* * Because we release the mmap_sem, the context may be destroyed while * we're in spu_wait. Grab an extra reference so it isn't destroyed diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c index eb5d74e26fe9..2ca7be65c2d2 100644 --- a/arch/powerpc/platforms/embedded6xx/linkstation.c +++ b/arch/powerpc/platforms/embedded6xx/linkstation.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -54,6 +55,19 @@ static struct mtd_partition linkstation_physmap_partitions[] = { }, }; +static __initdata struct of_device_id of_bus_ids[] = { + { .type = "soc", }, + { .compatible = "simple-bus", }, + {}, +}; + +static int __init declare_of_platform_devices(void) +{ + of_platform_bus_probe(NULL, of_bus_ids, NULL); + return 0; +} +machine_device_initcall(linkstation, declare_of_platform_devices); + static int __init linkstation_add_bridge(struct device_node *dev) { #ifdef CONFIG_PCI diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c index bb464d1211b2..bbe828f1b885 100644 --- a/arch/powerpc/platforms/iseries/iommu.c +++ b/arch/powerpc/platforms/iseries/iommu.c @@ -215,14 +215,15 @@ EXPORT_SYMBOL_GPL(iseries_hv_free); dma_addr_t iseries_hv_map(void *vaddr, size_t size, enum dma_data_direction direction) { - return iommu_map_single(NULL, &vio_iommu_table, vaddr, size, - DMA_32BIT_MASK, direction, NULL); + return iommu_map_page(NULL, &vio_iommu_table, virt_to_page(vaddr), + (unsigned long)vaddr % PAGE_SIZE, size, + DMA_32BIT_MASK, direction, NULL); } void iseries_hv_unmap(dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - iommu_unmap_single(&vio_iommu_table, dma_handle, size, direction, NULL); + iommu_unmap_page(&vio_iommu_table, dma_handle, size, direction, NULL); } void __init iommu_vio_init(void) diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile index be60d64be7ad..50f169392551 100644 --- a/arch/powerpc/platforms/powermac/Makefile +++ b/arch/powerpc/platforms/powermac/Makefile @@ -1,6 +1,6 @@ CFLAGS_bootx_init.o += -fPIC -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER # Do not trace early boot code CFLAGS_REMOVE_bootx_init.o = -pg -mno-sched-epilog endif diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index a789bf58ca8b..661e9f77ebf6 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c @@ -555,18 +555,19 @@ static void ps3_free_coherent(struct device *_dev, size_t size, void *vaddr, } /* Creates TCEs for a user provided buffer. The user buffer must be - * contiguous real kernel storage (not vmalloc). The address of the buffer - * passed here is the kernel (virtual) address of the buffer. The buffer - * need not be page aligned, the dma_addr_t returned will point to the same - * byte within the page as vaddr. + * contiguous real kernel storage (not vmalloc). The address passed here + * comprises a page address and offset into that page. The dma_addr_t + * returned will point to the same byte within the page as was passed in. */ -static dma_addr_t ps3_sb_map_single(struct device *_dev, void *ptr, size_t size, - enum dma_data_direction direction, struct dma_attrs *attrs) +static dma_addr_t ps3_sb_map_page(struct device *_dev, struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); int result; unsigned long bus_addr; + void *ptr = page_address(page) + offset; result = ps3_dma_map(dev->d_region, (unsigned long)ptr, size, &bus_addr, @@ -580,15 +581,16 @@ static dma_addr_t ps3_sb_map_single(struct device *_dev, void *ptr, size_t size, return bus_addr; } -static dma_addr_t ps3_ioc0_map_single(struct device *_dev, void *ptr, - size_t size, - enum dma_data_direction direction, - struct dma_attrs *attrs) +static dma_addr_t ps3_ioc0_map_page(struct device *_dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); int result; unsigned long bus_addr; u64 iopte_flag; + void *ptr = page_address(page) + offset; iopte_flag = IOPTE_M; switch (direction) { @@ -615,7 +617,7 @@ static dma_addr_t ps3_ioc0_map_single(struct device *_dev, void *ptr, return bus_addr; } -static void ps3_unmap_single(struct device *_dev, dma_addr_t dma_addr, +static void ps3_unmap_page(struct device *_dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); @@ -689,21 +691,21 @@ static int ps3_dma_supported(struct device *_dev, u64 mask) static struct dma_mapping_ops ps3_sb_dma_ops = { .alloc_coherent = ps3_alloc_coherent, .free_coherent = ps3_free_coherent, - .map_single = ps3_sb_map_single, - .unmap_single = ps3_unmap_single, .map_sg = ps3_sb_map_sg, .unmap_sg = ps3_sb_unmap_sg, - .dma_supported = ps3_dma_supported + .dma_supported = ps3_dma_supported, + .map_page = ps3_sb_map_page, + .unmap_page = ps3_unmap_page, }; static struct dma_mapping_ops ps3_ioc0_dma_ops = { .alloc_coherent = ps3_alloc_coherent, .free_coherent = ps3_free_coherent, - .map_single = ps3_ioc0_map_single, - .unmap_single = ps3_unmap_single, .map_sg = ps3_ioc0_map_sg, .unmap_sg = ps3_ioc0_unmap_sg, - .dma_supported = ps3_dma_supported + .dma_supported = ps3_dma_supported, + .map_page = ps3_ioc0_map_page, + .unmap_page = ps3_unmap_page, }; /** diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index d56491d182d3..c90817acb472 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,6 @@ #include #include #include -#include #include "plpar_wrappers.h" @@ -292,7 +292,7 @@ static void iommu_table_setparms(struct pci_controller *phb, tbl->it_base = (unsigned long)__va(*basep); - if (!__kdump_flag) + if (!is_kdump_kernel()) memset((void *)tbl->it_base, 0, *sizep); tbl->it_busno = phb->bus->number; diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c index 21a6d55418f1..7190493e9bdc 100644 --- a/arch/powerpc/platforms/pseries/pci_dlpar.c +++ b/arch/powerpc/platforms/pseries/pci_dlpar.c @@ -203,6 +203,7 @@ struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn) eeh_add_device_tree_early(dn); scan_phb(phb); + pcibios_allocate_bus_resources(phb->bus); pcibios_fixup_new_pci_devices(phb->bus); pci_bus_add_devices(phb->bus); eeh_add_device_tree_late(phb->bus); diff --git a/arch/powerpc/sysdev/bestcomm/Kconfig b/arch/powerpc/sysdev/bestcomm/Kconfig index 57cc56562567..0b192a1c429d 100644 --- a/arch/powerpc/sysdev/bestcomm/Kconfig +++ b/arch/powerpc/sysdev/bestcomm/Kconfig @@ -17,23 +17,20 @@ config PPC_BESTCOMM answer Y or M. Otherwise say N. config PPC_BESTCOMM_ATA - tristate "Bestcomm ATA task support" + tristate depends on PPC_BESTCOMM - default n help This option enables the support for the ATA task. config PPC_BESTCOMM_FEC - tristate "Bestcomm FEC tasks support" + tristate depends on PPC_BESTCOMM - default n help This option enables the support for the FEC tasks. config PPC_BESTCOMM_GEN_BD - tristate "Bestcomm GenBD tasks support" + tristate depends on PPC_BESTCOMM - default n help This option enables the support for the GenBD tasks. diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 01b884b25696..26ecb96f9731 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -223,6 +223,8 @@ static int gfar_mdio_of_init_one(struct device_node *np) if (ret) return ret; + /* The gianfar device will try to use the same ID created below to find + * this bus, to coordinate register access (since they share). */ mdio_dev = platform_device_register_simple("fsl-gianfar_mdio", res.start&0xfffff, &res, 1); if (IS_ERR(mdio_dev)) @@ -394,6 +396,30 @@ static int __init gfar_of_init(void) of_node_put(mdio); } + /* Get MDIO bus controlled by this eTSEC, if any. Normally only + * eTSEC 1 will control an MDIO bus, not necessarily the same + * bus that its PHY is on ('mdio' above), so we can't just use + * that. What we do is look for a gianfar mdio device that has + * overlapping registers with this device. That's really the + * whole point, to find the device sharing our registers to + * coordinate access with it. + */ + for_each_compatible_node(mdio, NULL, "fsl,gianfar-mdio") { + if (of_address_to_resource(mdio, 0, &res)) + continue; + + if (res.start >= r[0].start && res.end <= r[0].end) { + /* Get the ID the mdio bus platform device was + * registered with. gfar_data.bus_id is + * different because it's for finding a PHY, + * while this is for finding a MII bus. + */ + gfar_data.mdio_bus = res.start&0xfffff; + of_node_put(mdio); + break; + } + } + ret = platform_device_add_data(gfar_dev, &gfar_data, sizeof(struct diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 8e3478c995ef..1890fb085cde 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -563,6 +563,51 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic) #endif /* CONFIG_MPIC_U3_HT_IRQS */ +#ifdef CONFIG_SMP +static int irq_choose_cpu(unsigned int virt_irq) +{ + cpumask_t mask = irq_desc[virt_irq].affinity; + int cpuid; + + if (cpus_equal(mask, CPU_MASK_ALL)) { + static int irq_rover; + static DEFINE_SPINLOCK(irq_rover_lock); + unsigned long flags; + + /* Round-robin distribution... */ + do_round_robin: + spin_lock_irqsave(&irq_rover_lock, flags); + + while (!cpu_online(irq_rover)) { + if (++irq_rover >= NR_CPUS) + irq_rover = 0; + } + cpuid = irq_rover; + do { + if (++irq_rover >= NR_CPUS) + irq_rover = 0; + } while (!cpu_online(irq_rover)); + + spin_unlock_irqrestore(&irq_rover_lock, flags); + } else { + cpumask_t tmp; + + cpus_and(tmp, cpu_online_map, mask); + + if (cpus_empty(tmp)) + goto do_round_robin; + + cpuid = first_cpu(tmp); + } + + return get_hard_smp_processor_id(cpuid); +} +#else +static int irq_choose_cpu(unsigned int virt_irq) +{ + return hard_smp_processor_id(); +} +#endif #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) @@ -777,12 +822,18 @@ void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) struct mpic *mpic = mpic_from_irq(irq); unsigned int src = mpic_irq_to_hw(irq); - cpumask_t tmp; + if (mpic->flags & MPIC_SINGLE_DEST_CPU) { + int cpuid = irq_choose_cpu(irq); + + mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); + } else { + cpumask_t tmp; - cpus_and(tmp, cpumask, cpu_online_map); + cpus_and(tmp, cpumask, cpu_online_map); - mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), - mpic_physmask(cpus_addr(tmp)[0])); + mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), + mpic_physmask(cpus_addr(tmp)[0])); + } } static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) @@ -1220,6 +1271,7 @@ void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) void __init mpic_init(struct mpic *mpic) { int i; + int cpu; BUG_ON(mpic->num_sources == 0); @@ -1262,6 +1314,11 @@ void __init mpic_init(struct mpic *mpic) mpic_pasemi_msi_init(mpic); + if (mpic->flags & MPIC_PRIMARY) + cpu = hard_smp_processor_id(); + else + cpu = 0; + for (i = 0; i < mpic->num_sources; i++) { /* start with vector = source number, and masked */ u32 vecpri = MPIC_VECPRI_MASK | i | @@ -1272,8 +1329,7 @@ void __init mpic_init(struct mpic *mpic) continue; /* init hw */ mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); - mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), - 1 << hard_smp_processor_id()); + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); } /* Init spurious vector */ diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index b7aefd0d45cb..a22e1a2df1af 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c @@ -107,8 +107,8 @@ xilinx_intc_init(struct device_node *np) } regs = ioremap(res.start, 32); - printk(KERN_INFO "Xilinx intc at 0x%08LX mapped to 0x%p\n", - res.start, regs); + printk(KERN_INFO "Xilinx intc at 0x%08llx mapped to 0x%p\n", + (unsigned long long) res.start, regs); /* Setup interrupt controller */ out_be32(regs + XINTC_IER, 0); /* disable all irqs */ diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 34c3d0688fe0..076368c8b8a9 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -1353,6 +1353,7 @@ static void backtrace(struct pt_regs *excp) static void print_bug_trap(struct pt_regs *regs) { +#ifdef CONFIG_BUG const struct bug_entry *bug; unsigned long addr; @@ -1373,6 +1374,7 @@ static void print_bug_trap(struct pt_regs *regs) #else printf("kernel BUG at %p!\n", (void *)bug->bug_addr); #endif +#endif /* CONFIG_BUG */ } static void excprint(struct pt_regs *fp) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 70b7645ce745..8116a3328a19 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -241,19 +241,17 @@ config PACK_STACK Say Y if you are unsure. config SMALL_STACK - bool "Use 4kb/8kb for kernel stack instead of 8kb/16kb" - depends on PACK_STACK && !LOCKDEP + bool "Use 8kb for kernel stack instead of 16kb" + depends on PACK_STACK && 64BIT && !LOCKDEP help If you say Y here and the compiler supports the -mkernel-backchain - option the kernel will use a smaller kernel stack size. For 31 bit - the reduced size is 4kb instead of 8kb and for 64 bit it is 8kb - instead of 16kb. This allows to run more thread on a system and - reduces the pressure on the memory management for higher order - page allocations. + option the kernel will use a smaller kernel stack size. The reduced + size is 8kb instead of 16kb. This allows to run more threads on a + system and reduces the pressure on the memory management for higher + order page allocations. Say N if you are unsure. - config CHECK_STACK bool "Detect kernel stack overflow" help @@ -384,7 +382,7 @@ config IPL choice prompt "IPL method generated into head.S" depends on IPL - default IPL_TAPE + default IPL_VM help Select "tape" if you want to IPL the image from a Tape. diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c index a7f8979fb925..a06a47cdd5e0 100644 --- a/arch/s390/appldata/appldata_base.c +++ b/arch/s390/appldata/appldata_base.c @@ -424,7 +424,7 @@ out: */ int appldata_register_ops(struct appldata_ops *ops) { - if ((ops->size > APPLDATA_MAX_REC_SIZE) || (ops->size < 0)) + if (ops->size > APPLDATA_MAX_REC_SIZE) return -EINVAL; ops->ctl_table = kzalloc(4 * sizeof(struct ctl_table), GFP_KERNEL); diff --git a/arch/s390/defconfig b/arch/s390/defconfig index 9b0bc2c9fba0..a0e748da9909 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-rc4 -# Thu Aug 21 19:43:29 2008 +# Linux kernel version: 2.6.28-rc6 +# Thu Nov 27 11:00:49 2008 # CONFIG_SCHED_MC=y CONFIG_MMU=y @@ -45,6 +45,7 @@ CONFIG_LOG_BUF_SHIFT=17 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_NS=y +# CONFIG_CGROUP_FREEZER is not set # CONFIG_CGROUP_DEVICE is not set # CONFIG_CPUSETS is not set CONFIG_GROUP_SCHED=y @@ -84,6 +85,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -92,16 +94,10 @@ CONFIG_SLAB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y CONFIG_KPROBES=y -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set CONFIG_KRETPROBES=y -# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_ARCH_TRACEHOOK=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -135,6 +131,7 @@ CONFIG_DEFAULT_DEADLINE=y CONFIG_DEFAULT_IOSCHED="deadline" CONFIG_PREEMPT_NOTIFIERS=y CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Base setup @@ -189,7 +186,6 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -200,9 +196,11 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # # I/O subsystem configuration @@ -220,6 +218,8 @@ CONFIG_IPL=y CONFIG_IPL_VM=y CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_FORCE_MAX_ZONEORDER=9 # CONFIG_PROCESS_DEBUG is not set @@ -255,7 +255,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y # CONFIG_NET_KEY_MIGRATE is not set -CONFIG_IUCV=m +CONFIG_IUCV=y CONFIG_AFIUCV=m CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -282,7 +282,6 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=y # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -331,10 +330,12 @@ CONFIG_NF_CONNTRACK=m # CONFIG_NF_CONNTRACK_TFTP is not set # CONFIG_NF_CT_NETLINK is not set # CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_NF_CONNTRACK_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set @@ -374,6 +375,7 @@ CONFIG_NET_SCH_CBQ=m # CONFIG_NET_SCH_HTB is not set # CONFIG_NET_SCH_HFSC is not set CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=y CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -406,6 +408,7 @@ CONFIG_NET_ACT_POLICE=y CONFIG_NET_ACT_NAT=m # CONFIG_NET_ACT_PEDIT is not set # CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set # CONFIG_NET_CLS_IND is not set CONFIG_NET_SCH_FIFO=y @@ -424,6 +427,7 @@ CONFIG_CAN_BCM=m CONFIG_CAN_VCAN=m # CONFIG_CAN_DEBUG_DEVICES is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # CONFIG_PCMCIA is not set @@ -473,7 +477,7 @@ CONFIG_VIRTIO_BLK=m CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HAVE_IDE is not set +# CONFIG_C2PORT is not set # # SCSI device support @@ -525,6 +529,7 @@ CONFIG_SCSI_DH_EMC=m CONFIG_SCSI_DH_ALUA=m CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m @@ -555,6 +560,9 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NETDEV_1000=y CONFIG_NETDEV_10000=y # CONFIG_TR is not set @@ -632,13 +640,12 @@ CONFIG_S390_VMUR=m # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# +# CONFIG_REGULATOR is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set CONFIG_ACCESSIBILITY=y +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # File systems @@ -650,13 +657,14 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set @@ -688,6 +696,7 @@ CONFIG_GENERIC_ACL=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y @@ -728,6 +737,7 @@ CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -800,12 +810,24 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_SG is not set # CONFIG_FRAME_POINTER is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set CONFIG_SAMPLES=y # CONFIG_SAMPLE_KOBJECT is not set # CONFIG_SAMPLE_KPROBES is not set @@ -816,16 +838,19 @@ CONFIG_SAMPLES=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m # CONFIG_CRYPTO_NULL is not set @@ -877,7 +902,7 @@ CONFIG_CRYPTO_SHA1=m # # Ciphers # -# CONFIG_CRYPTO_AES is not set +CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set @@ -898,6 +923,11 @@ CONFIG_CRYPTO_SEED=m # # CONFIG_CRYPTO_DEFLATE is not set CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_HW=y CONFIG_ZCRYPT=m # CONFIG_ZCRYPT_MONOLITHIC is not set @@ -912,8 +942,6 @@ CONFIG_S390_PRNG=m # Library routines # CONFIG_BITREVERSE=m -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y diff --git a/arch/s390/include/asm/kvm_virtio.h b/arch/s390/include/asm/kvm_virtio.h index 146100224def..c13568b9351c 100644 --- a/arch/s390/include/asm/kvm_virtio.h +++ b/arch/s390/include/asm/kvm_virtio.h @@ -52,7 +52,7 @@ struct kvm_vqconfig { #ifdef __KERNEL__ /* early virtio console setup */ -#ifdef CONFIG_VIRTIO_CONSOLE +#ifdef CONFIG_S390_GUEST extern void s390_virtio_console_init(void); #else static inline void s390_virtio_console_init(void) diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h index 5dd5e7b3476f..d2b4ff831477 100644 --- a/arch/s390/include/asm/mmu.h +++ b/arch/s390/include/asm/mmu.h @@ -7,7 +7,8 @@ typedef struct { unsigned long asce_bits; unsigned long asce_limit; int noexec; - int pgstes; + int has_pgste; /* The mmu context has extended page tables */ + int alloc_pgste; /* cloned contexts will have extended page tables */ } mm_context_t; #endif diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index 4c2fbf48c9c4..28ec870655af 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -20,12 +20,25 @@ static inline int init_new_context(struct task_struct *tsk, #ifdef CONFIG_64BIT mm->context.asce_bits |= _ASCE_TYPE_REGION3; #endif - if (current->mm->context.pgstes) { + if (current->mm->context.alloc_pgste) { + /* + * alloc_pgste indicates, that any NEW context will be created + * with extended page tables. The old context is unchanged. The + * page table allocation and the page table operations will + * look at has_pgste to distinguish normal and extended page + * tables. The only way to create extended page tables is to + * set alloc_pgste and then create a new context (e.g. dup_mm). + * The page table allocation is called after init_new_context + * and if has_pgste is set, it will create extended page + * tables. + */ mm->context.noexec = 0; - mm->context.pgstes = 1; + mm->context.has_pgste = 1; + mm->context.alloc_pgste = 1; } else { mm->context.noexec = s390_noexec; - mm->context.pgstes = 0; + mm->context.has_pgste = 0; + mm->context.alloc_pgste = 0; } mm->context.asce_limit = STACK_TOP_MAX; crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm)); diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 1a928f84afd6..5caddd4f7bed 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -679,8 +679,6 @@ static inline void pmd_clear(pmd_t *pmd) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { - if (mm->context.pgstes) - ptep_rcp_copy(ptep); pte_val(*ptep) = _PAGE_TYPE_EMPTY; if (mm->context.noexec) pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY; @@ -763,7 +761,7 @@ static inline int kvm_s390_test_and_clear_page_dirty(struct mm_struct *mm, struct page *page; unsigned int skey; - if (!mm->context.pgstes) + if (!mm->context.has_pgste) return -EINVAL; rcp_lock(ptep); pgste = (unsigned long *) (ptep + PTRS_PER_PTE); @@ -794,7 +792,7 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, int young; unsigned long *pgste; - if (!vma->vm_mm->context.pgstes) + if (!vma->vm_mm->context.has_pgste) return 0; physpage = pte_val(*ptep) & PAGE_MASK; pgste = (unsigned long *) (ptep + PTRS_PER_PTE); @@ -844,7 +842,7 @@ static inline void __ptep_ipte(unsigned long address, pte_t *ptep) static inline void ptep_invalidate(struct mm_struct *mm, unsigned long address, pte_t *ptep) { - if (mm->context.pgstes) { + if (mm->context.has_pgste) { rcp_lock(ptep); __ptep_ipte(address, ptep); ptep_rcp_copy(ptep); diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index a7226f8143fb..5396f9f12263 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -321,8 +321,8 @@ struct pt_regs psw_t psw; unsigned long gprs[NUM_GPRS]; unsigned long orig_gpr2; + unsigned short svcnr; unsigned short ilc; - unsigned short trap; }; #endif @@ -486,8 +486,6 @@ struct task_struct; extern void user_enable_single_step(struct task_struct *); extern void user_disable_single_step(struct task_struct *); -#define __ARCH_WANT_COMPAT_SYS_PTRACE - #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0) #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN) #define user_stack_pointer(regs)((regs)->gprs[15]) diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h index 6e623971fbb9..2429b87eb28d 100644 --- a/arch/s390/include/asm/syscall.h +++ b/arch/s390/include/asm/syscall.h @@ -17,9 +17,7 @@ static inline long syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { - if (regs->trap != __LC_SVC_OLD_PSW) - return -1; - return regs->gprs[2]; + return regs->svcnr ? regs->svcnr : -1; } static inline void syscall_rollback(struct task_struct *task, @@ -52,18 +50,20 @@ static inline void syscall_get_arguments(struct task_struct *task, unsigned int i, unsigned int n, unsigned long *args) { + unsigned long mask = -1UL; + BUG_ON(i + n > 6); #ifdef CONFIG_COMPAT - if (test_tsk_thread_flag(task, TIF_31BIT)) { - if (i + n == 6) - args[--n] = (u32) regs->args[0]; - while (n-- > 0) - args[n] = (u32) regs->gprs[2 + i + n]; - } + if (test_tsk_thread_flag(task, TIF_31BIT)) + mask = 0xffffffff; #endif if (i + n == 6) - args[--n] = regs->args[0]; - memcpy(args, ®s->gprs[2 + i], n * sizeof(args[0])); + args[--n] = regs->args[0] & mask; + while (n-- > 0) + if (i + n > 0) + args[n] = regs->gprs[2 + i + n] & mask; + if (i == 0) + args[0] = regs->orig_gpr2 & mask; } static inline void syscall_set_arguments(struct task_struct *task, @@ -74,7 +74,11 @@ static inline void syscall_set_arguments(struct task_struct *task, BUG_ON(i + n > 6); if (i + n == 6) regs->args[0] = args[--n]; - memcpy(®s->gprs[2 + i], args, n * sizeof(args[0])); + while (n-- > 0) + if (i + n > 0) + regs->gprs[2 + i + n] = args[n]; + if (i == 0) + regs->orig_gpr2 = args[0]; } #endif /* _ASM_SYSCALL_H */ diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index de3fad60c682..c1eaf9604da7 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -15,13 +15,8 @@ * Size of kernel stack for each process */ #ifndef __s390x__ -#ifndef __SMALL_STACK #define THREAD_ORDER 1 #define ASYNC_ORDER 1 -#else -#define THREAD_ORDER 0 -#define ASYNC_ORDER 0 -#endif #else /* __s390x__ */ #ifndef __SMALL_STACK #define THREAD_ORDER 2 diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index fa28ecae636b..3d144e6020c6 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -32,7 +32,7 @@ int main(void) DEFINE(__PT_GPRS, offsetof(struct pt_regs, gprs)); DEFINE(__PT_ORIG_GPR2, offsetof(struct pt_regs, orig_gpr2)); DEFINE(__PT_ILC, offsetof(struct pt_regs, ilc)); - DEFINE(__PT_TRAP, offsetof(struct pt_regs, trap)); + DEFINE(__PT_SVCNR, offsetof(struct pt_regs, svcnr)); DEFINE(__PT_SIZE, sizeof(struct pt_regs)); BLANK(); DEFINE(__SF_BACKCHAIN, offsetof(struct stack_frame, back_chain)); diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c index c7f02e777af2..b537cb0e9b55 100644 --- a/arch/s390/kernel/compat_signal.c +++ b/arch/s390/kernel/compat_signal.c @@ -340,7 +340,7 @@ static int restore_sigregs32(struct pt_regs *regs,_sigregs32 __user *sregs) return err; restore_fp_regs(¤t->thread.fp_regs); - regs->trap = -1; /* disable syscall checks */ + regs->svcnr = 0; /* disable syscall checks */ return 0; } diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index ed500ef799b7..198ea18a534d 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -46,7 +46,7 @@ SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 60 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC -SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP +SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ @@ -61,22 +61,25 @@ STACK_SIZE = 1 << STACK_SHIFT #ifdef CONFIG_TRACE_IRQFLAGS .macro TRACE_IRQS_ON - l %r1,BASED(.Ltrace_irq_on) + basr %r2,%r0 + l %r1,BASED(.Ltrace_irq_on_caller) basr %r14,%r1 .endm .macro TRACE_IRQS_OFF - l %r1,BASED(.Ltrace_irq_off) + basr %r2,%r0 + l %r1,BASED(.Ltrace_irq_off_caller) basr %r14,%r1 .endm .macro TRACE_IRQS_CHECK + basr %r2,%r0 tm SP_PSW(%r15),0x03 # irqs enabled? jz 0f - l %r1,BASED(.Ltrace_irq_on) + l %r1,BASED(.Ltrace_irq_on_caller) basr %r14,%r1 j 1f -0: l %r1,BASED(.Ltrace_irq_off) +0: l %r1,BASED(.Ltrace_irq_off_caller) basr %r14,%r1 1: .endm @@ -180,11 +183,10 @@ STACK_SIZE = 1 << STACK_SHIFT .macro CREATE_STACK_FRAME psworg,savearea s %r15,BASED(.Lc_spsize) # make room for registers & psw mvc SP_PSW(8,%r15),0(%r12) # move user PSW to stack - la %r12,\psworg st %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 - icm %r12,12,__LC_SVC_ILC + icm %r12,3,__LC_SVC_ILC stm %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack - st %r12,SP_ILC(%r15) + st %r12,SP_SVCNR(%r15) mvc SP_R12(16,%r15),\savearea # move %r12-%r15 to stack la %r12,0 st %r12,__SF_BACKCHAIN(%r15) # clear back chain @@ -261,16 +263,17 @@ sysc_update: #endif sysc_do_svc: l %r9,__LC_THREAD_INFO # load pointer to thread_info struct - sla %r7,2 # *4 and test for svc 0 + ltr %r7,%r7 # test for svc 0 bnz BASED(sysc_nr_ok) # svc number > 0 # svc 0: system call number in %r1 cl %r1,BASED(.Lnr_syscalls) bnl BASED(sysc_nr_ok) lr %r7,%r1 # copy svc number to %r7 - sla %r7,2 # *4 sysc_nr_ok: mvc SP_ARGS(4,%r15),SP_R7(%r15) sysc_do_restart: + sth %r7,SP_SVCNR(%r15) + sll %r7,2 # svc number *4 l %r8,BASED(.Lsysc_table) tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) l %r8,0(%r7,%r8) # get system call addr. @@ -373,7 +376,6 @@ sysc_notify_resume: sysc_restart: ni __TI_flags+3(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC l %r7,SP_R2(%r15) # load new svc number - sla %r7,2 mvc SP_R2(4,%r15),SP_ORIG_R2(%r15) # restore first argument lm %r2,%r6,SP_R2(%r15) # load svc arguments b BASED(sysc_do_restart) # restart svc @@ -383,7 +385,8 @@ sysc_restart: # sysc_singlestep: ni __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP - mvi SP_TRAP+1(%r15),0x28 # set trap indication to pgm check + mvi SP_SVCNR(%r15),0xff # set trap indication to pgm check + mvi SP_SVCNR+1(%r15),0xff la %r2,SP_PTREGS(%r15) # address of register-save area l %r1,BASED(.Lhandle_per) # load adr. of per handler la %r14,BASED(sysc_return) # load adr. of system return @@ -404,7 +407,7 @@ sysc_tracesys: bnl BASED(sysc_tracenogo) l %r8,BASED(.Lsysc_table) lr %r7,%r2 - sll %r7,2 # *4 + sll %r7,2 # svc number *4 l %r8,0(%r7,%r8) sysc_tracego: lm %r3,%r6,SP_R3(%r15) @@ -583,7 +586,8 @@ pgm_svcper: # per was called from kernel, must be kprobes # kernel_per: - mvi SP_TRAP+1(%r15),0x28 # set trap indication to pgm check + mvi SP_SVCNR(%r15),0xff # set trap indication to pgm check + mvi SP_SVCNR+1(%r15),0xff la %r2,SP_PTREGS(%r15) # address of register-save area l %r1,BASED(.Lhandle_per) # load adr. of per handler la %r14,BASED(sysc_restore)# load adr. of system return @@ -1113,9 +1117,12 @@ cleanup_io_leave_insn: .Lschedtail: .long schedule_tail .Lsysc_table: .long sys_call_table #ifdef CONFIG_TRACE_IRQFLAGS -.Ltrace_irq_on: .long trace_hardirqs_on -.Ltrace_irq_off: - .long trace_hardirqs_off +.Ltrace_irq_on_caller: + .long trace_hardirqs_on_caller +.Ltrace_irq_off_caller: + .long trace_hardirqs_off_caller +#endif +#ifdef CONFIG_LOCKDEP .Llockdep_sys_exit: .long lockdep_sys_exit #endif diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index d7ce150453f2..89c121ae6339 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -46,7 +46,7 @@ SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC -SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP +SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER @@ -61,19 +61,22 @@ _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ #ifdef CONFIG_TRACE_IRQFLAGS .macro TRACE_IRQS_ON - brasl %r14,trace_hardirqs_on + basr %r2,%r0 + brasl %r14,trace_hardirqs_on_caller .endm .macro TRACE_IRQS_OFF - brasl %r14,trace_hardirqs_off + basr %r2,%r0 + brasl %r14,trace_hardirqs_off_caller .endm .macro TRACE_IRQS_CHECK + basr %r2,%r0 tm SP_PSW(%r15),0x03 # irqs enabled? jz 0f - brasl %r14,trace_hardirqs_on + brasl %r14,trace_hardirqs_on_caller j 1f -0: brasl %r14,trace_hardirqs_off +0: brasl %r14,trace_hardirqs_off_caller 1: .endm #else @@ -168,11 +171,10 @@ _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ .macro CREATE_STACK_FRAME psworg,savearea aghi %r15,-SP_SIZE # make room for registers & psw mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack - la %r12,\psworg stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2 - icm %r12,12,__LC_SVC_ILC + icm %r12,3,__LC_SVC_ILC stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack - st %r12,SP_ILC(%r15) + st %r12,SP_SVCNR(%r15) mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack la %r12,0 stg %r12,__SF_BACKCHAIN(%r15) @@ -247,16 +249,17 @@ sysc_update: #endif sysc_do_svc: lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct - slag %r7,%r7,2 # *4 and test for svc 0 + ltgr %r7,%r7 # test for svc 0 jnz sysc_nr_ok # svc 0: system call number in %r1 cl %r1,BASED(.Lnr_syscalls) jnl sysc_nr_ok lgfr %r7,%r1 # clear high word in r1 - slag %r7,%r7,2 # svc 0: system call number in %r1 sysc_nr_ok: mvc SP_ARGS(8,%r15),SP_R7(%r15) sysc_do_restart: + sth %r7,SP_SVCNR(%r15) + sllg %r7,%r7,2 # svc number * 4 larl %r10,sys_call_table #ifdef CONFIG_COMPAT tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ? @@ -360,7 +363,6 @@ sysc_notify_resume: sysc_restart: ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC lg %r7,SP_R2(%r15) # load new svc number - slag %r7,%r7,2 # *4 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument lmg %r2,%r6,SP_R2(%r15) # load svc arguments j sysc_do_restart # restart svc @@ -369,9 +371,8 @@ sysc_restart: # _TIF_SINGLE_STEP is set, call do_single_step # sysc_singlestep: - ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP - lhi %r0,__LC_PGM_OLD_PSW - sth %r0,SP_TRAP(%r15) # set trap indication to pgm check + ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP + xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number la %r2,SP_PTREGS(%r15) # address of register-save area larl %r14,sysc_return # load adr. of system return jg do_single_step # branch to do_sigtrap @@ -389,7 +390,7 @@ sysc_tracesys: lghi %r0,NR_syscalls clgr %r0,%r2 jnh sysc_tracenogo - slag %r7,%r2,2 # *4 + sllg %r7,%r2,2 # svc number *4 lgf %r8,0(%r7,%r10) sysc_tracego: lmg %r3,%r6,SP_R3(%r15) @@ -564,8 +565,7 @@ pgm_svcper: # per was called from kernel, must be kprobes # kernel_per: - lhi %r0,__LC_PGM_OLD_PSW - sth %r0,SP_TRAP(%r15) # set trap indication to pgm check + xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number la %r2,SP_PTREGS(%r15) # address of register-save area larl %r14,sysc_restore # load adr. of system ret, no work jg do_single_step # branch to do_single_step diff --git a/arch/s390/kernel/init_task.c b/arch/s390/kernel/init_task.c index 7ad003969251..e80716843619 100644 --- a/arch/s390/kernel/init_task.c +++ b/arch/s390/kernel/init_task.c @@ -26,7 +26,7 @@ EXPORT_SYMBOL(init_mm); /* * Initial thread structure. * - * We need to make sure that this is 8192-byte aligned due to the + * We need to make sure that this is THREAD_SIZE aligned due to the * way process stacks are handled. This is done by having a special * "init_task" linker map entry.. */ diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 3e2c05cb6a87..04f8c67a6101 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -136,9 +136,12 @@ static void default_idle(void) return; } trace_hardirqs_on(); + /* Don't trace preempt off for idle. */ + stop_critical_timings(); /* Wait for external, I/O or machine check interrupt. */ __load_psw_mask(psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_IO | PSW_MASK_EXT); + start_critical_timings(); } void cpu_idle(void) diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 1f31be1ecc4b..38ff2bce1203 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -657,7 +657,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) * debugger stored an invalid system call number. Skip * the system call and the system call restart handling. */ - regs->trap = -1; + regs->svcnr = 0; ret = -1; } diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 62122bad1e33..400b040df7fa 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -604,13 +604,13 @@ setup_memory(void) if (memory_chunk[i].type != CHUNK_READ_WRITE) continue; start_chunk = PFN_DOWN(memory_chunk[i].addr); - end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size) - 1; + end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size); end_chunk = min(end_chunk, end_pfn); if (start_chunk >= end_chunk) continue; add_active_range(0, start_chunk, end_chunk); pfn = max(start_chunk, start_pfn); - for (; pfn <= end_chunk; pfn++) + for (; pfn < end_chunk; pfn++) page_set_storage_key(PFN_PHYS(pfn), PAGE_DEFAULT_KEY); } diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index 4f7fc3059a8e..8e6812a22670 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -160,7 +160,7 @@ static int restore_sigregs(struct pt_regs *regs, _sigregs __user *sregs) current->thread.fp_regs.fpc &= FPC_VALID_MASK; restore_fp_regs(¤t->thread.fp_regs); - regs->trap = -1; /* disable syscall checks */ + regs->svcnr = 0; /* disable syscall checks */ return 0; } @@ -445,7 +445,7 @@ void do_signal(struct pt_regs *regs) oldset = ¤t->blocked; /* Are we from a system call? */ - if (regs->trap == __LC_SVC_OLD_PSW) { + if (regs->svcnr) { continue_addr = regs->psw.addr; restart_addr = continue_addr - regs->ilc; retval = regs->gprs[2]; @@ -462,7 +462,7 @@ void do_signal(struct pt_regs *regs) case -ERESTART_RESTARTBLOCK: regs->gprs[2] = -EINTR; } - regs->trap = -1; /* Don't deal with this again. */ + regs->svcnr = 0; /* Don't deal with this again. */ } /* Get signal to deliver. When running under ptrace, at this point diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 9e8b1f9b8f4d..b5595688a477 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -1119,9 +1119,7 @@ out: return rc; } -static ssize_t __ref rescan_store(struct sys_device *dev, - struct sysdev_attribute *attr, - const char *buf, +static ssize_t __ref rescan_store(struct sysdev_class *class, const char *buf, size_t count) { int rc; @@ -1129,12 +1127,10 @@ static ssize_t __ref rescan_store(struct sys_device *dev, rc = smp_rescan_cpus(); return rc ? rc : count; } -static SYSDEV_ATTR(rescan, 0200, NULL, rescan_store); +static SYSDEV_CLASS_ATTR(rescan, 0200, NULL, rescan_store); #endif /* CONFIG_HOTPLUG_CPU */ -static ssize_t dispatching_show(struct sys_device *dev, - struct sysdev_attribute *attr, - char *buf) +static ssize_t dispatching_show(struct sysdev_class *class, char *buf) { ssize_t count; @@ -1144,9 +1140,8 @@ static ssize_t dispatching_show(struct sys_device *dev, return count; } -static ssize_t dispatching_store(struct sys_device *dev, - struct sysdev_attribute *attr, - const char *buf, size_t count) +static ssize_t dispatching_store(struct sysdev_class *dev, const char *buf, + size_t count) { int val, rc; char delim; @@ -1168,7 +1163,8 @@ out: put_online_cpus(); return rc ? rc : count; } -static SYSDEV_ATTR(dispatching, 0644, dispatching_show, dispatching_store); +static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show, + dispatching_store); static int __init topology_init(void) { @@ -1178,13 +1174,11 @@ static int __init topology_init(void) register_cpu_notifier(&smp_cpu_nb); #ifdef CONFIG_HOTPLUG_CPU - rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj, - &attr_rescan.attr); + rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_rescan); if (rc) return rc; #endif - rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj, - &attr_dispatching.attr); + rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_dispatching); if (rc) return rc; for_each_present_cpu(cpu) { diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c index 5fdb799062b7..4fe952e557ac 100644 --- a/arch/s390/kernel/sys_s390.c +++ b/arch/s390/kernel/sys_s390.c @@ -198,7 +198,7 @@ asmlinkage long s390x_newuname(struct new_utsname __user *name) { int ret = sys_newuname(name); - if (current->personality == PER_LINUX32 && !ret) { + if (personality(current->personality) == PER_LINUX32 && !ret) { ret = copy_to_user(name->machine, "s390\0\0\0\0", 8); if (ret) ret = -EFAULT; } diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index b94e9e3b694a..eccefbbff887 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -59,7 +59,7 @@ static ext_int_info_t ext_int_info_cc; static ext_int_info_t ext_int_etr_cc; -static u64 jiffies_timer_cc; +static u64 sched_clock_base_cc; static DEFINE_PER_CPU(struct clock_event_device, comparators); @@ -68,7 +68,7 @@ static DEFINE_PER_CPU(struct clock_event_device, comparators); */ unsigned long long sched_clock(void) { - return ((get_clock_xt() - jiffies_timer_cc) * 125) >> 9; + return ((get_clock_xt() - sched_clock_base_cc) * 125) >> 9; } /* @@ -229,13 +229,10 @@ static struct clocksource clocksource_tod = { */ void __init time_init(void) { - u64 init_timer_cc; - - init_timer_cc = reset_tod_clock(); - jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY; + sched_clock_base_cc = reset_tod_clock(); /* set xtime */ - tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime); + tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, &xtime); set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); @@ -289,7 +286,7 @@ static unsigned long long adjust_time(unsigned long long old, delta = -delta; adjust.offset = -ticks * (1000000 / HZ); } - jiffies_timer_cc += delta; + sched_clock_base_cc += delta; if (adjust.offset != 0) { printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n", adjust.offset); diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index 632b13e10053..a947899dcba1 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -65,18 +65,21 @@ static int machine_has_topology_irq; static struct timer_list topology_timer; static void set_topology_timer(void); static DECLARE_WORK(topology_work, topology_work_fn); +/* topology_lock protects the core linked list */ +static DEFINE_SPINLOCK(topology_lock); cpumask_t cpu_core_map[NR_CPUS]; cpumask_t cpu_coregroup_map(unsigned int cpu) { struct core_info *core = &core_info; + unsigned long flags; cpumask_t mask; cpus_clear(mask); if (!machine_has_topology) return cpu_present_map; - mutex_lock(&smp_cpu_state_mutex); + spin_lock_irqsave(&topology_lock, flags); while (core) { if (cpu_isset(cpu, core->mask)) { mask = core->mask; @@ -84,7 +87,7 @@ cpumask_t cpu_coregroup_map(unsigned int cpu) } core = core->next; } - mutex_unlock(&smp_cpu_state_mutex); + spin_unlock_irqrestore(&topology_lock, flags); if (cpus_empty(mask)) mask = cpumask_of_cpu(cpu); return mask; @@ -133,7 +136,7 @@ static void tl_to_cores(struct tl_info *info) union tl_entry *tle, *end; struct core_info *core = &core_info; - mutex_lock(&smp_cpu_state_mutex); + spin_lock_irq(&topology_lock); clear_cores(); tle = info->tle; end = (union tl_entry *)((unsigned long)info + info->length); @@ -157,7 +160,7 @@ static void tl_to_cores(struct tl_info *info) } tle = next_tle(tle); } - mutex_unlock(&smp_cpu_state_mutex); + spin_unlock_irq(&topology_lock); } static void topology_update_polarization_simple(void) diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index 607bd67a18ce..d796d05c9c01 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -2,6 +2,7 @@ * Written by Martin Schwidefsky (schwidefsky@de.ibm.com) */ +#include #include #include @@ -86,7 +87,7 @@ SECTIONS } _edata = .; /* End of data section */ - . = ALIGN(2 * PAGE_SIZE); /* init_task */ + . = ALIGN(THREAD_SIZE); /* init_task */ .data.init_task : { *(.data.init_task) } diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c index 170392687ce0..2a01b9e02801 100644 --- a/arch/s390/kvm/sigp.c +++ b/arch/s390/kvm/sigp.c @@ -237,6 +237,11 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu) u8 order_code; int rc; + /* sigp in userspace can exit */ + if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) + return kvm_s390_inject_program_int(vcpu, + PGM_PRIVILEGED_OPERATION); + order_code = disp2; if (base2) order_code += vcpu->arch.guest_gprs[base2]; diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 3d98ba82ea67..ef3635b52fc0 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -169,7 +169,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm) unsigned long *table; unsigned long bits; - bits = (mm->context.noexec || mm->context.pgstes) ? 3UL : 1UL; + bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL; spin_lock(&mm->page_table_lock); page = NULL; if (!list_empty(&mm->context.pgtable_list)) { @@ -186,7 +186,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm) pgtable_page_ctor(page); page->flags &= ~FRAG_MASK; table = (unsigned long *) page_to_phys(page); - if (mm->context.pgstes) + if (mm->context.has_pgste) clear_table_pgstes(table); else clear_table(table, _PAGE_TYPE_EMPTY, PAGE_SIZE); @@ -210,7 +210,7 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) struct page *page; unsigned long bits; - bits = (mm->context.noexec || mm->context.pgstes) ? 3UL : 1UL; + bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL; bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long); page = pfn_to_page(__pa(table) >> PAGE_SHIFT); spin_lock(&mm->page_table_lock); @@ -257,7 +257,7 @@ int s390_enable_sie(void) struct mm_struct *mm, *old_mm; /* Do we have pgstes? if yes, we are done */ - if (tsk->mm->context.pgstes) + if (tsk->mm->context.has_pgste) return 0; /* lets check if we are allowed to replace the mm */ @@ -269,14 +269,14 @@ int s390_enable_sie(void) } task_unlock(tsk); - /* we copy the mm with pgstes enabled */ - tsk->mm->context.pgstes = 1; + /* we copy the mm and let dup_mm create the page tables with_pgstes */ + tsk->mm->context.alloc_pgste = 1; mm = dup_mm(tsk); - tsk->mm->context.pgstes = 0; + tsk->mm->context.alloc_pgste = 0; if (!mm) return -ENOMEM; - /* Now lets check again if somebody attached ptrace etc */ + /* Now lets check again if something happened */ task_lock(tsk); if (!tsk->mm || atomic_read(&tsk->mm->mm_users) > 1 || tsk->mm != tsk->active_mm || tsk->mm->ioctx_list) { diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index cb2c87df70ce..5c9cbfc14c4d 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -24,7 +24,7 @@ config SUPERH32 select HAVE_KPROBES select HAVE_KRETPROBES select HAVE_ARCH_TRACEHOOK - select HAVE_FTRACE + select HAVE_FUNCTION_TRACER config SUPERH64 def_bool y if CPU_SH5 @@ -55,6 +55,8 @@ config GENERIC_HARDIRQS config GENERIC_HARDIRQS_NO__DO_IRQ def_bool y + depends on SUPERH32 && (!SH_DREAMCAST && !SH_SH4202_MICRODEV && \ + !SH_7751_SYSTEMH && !HD64461) config GENERIC_IRQ_PROBE def_bool y diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 1f409bf81809..c43eb0d7fa3b 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -2,7 +2,7 @@ # arch/sh/Makefile # # Copyright (C) 1999 Kaz Kojima -# Copyright (C) 2002, 2003, 2004 Paul Mundt +# Copyright (C) 2002 - 2008 Paul Mundt # Copyright (C) 2002 M. R. Brown # # This file is subject to the terms and conditions of the GNU General Public @@ -18,16 +18,12 @@ isa-$(CONFIG_CPU_SH4) := sh4 isa-$(CONFIG_CPU_SH4A) := sh4a isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al isa-$(CONFIG_CPU_SH5) := shmedia -isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp -ifndef CONFIG_SH_DSP -ifndef CONFIG_SH_FPU -isa-y := $(isa-y)-nofpu -endif +ifeq ($(CONFIG_SUPERH32),y) +isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp +isa-y := $(isa-y)-up endif -isa-y := $(isa-y)-up - cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,) cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \ $(call cc-option,-m2a-nofpu,) @@ -38,6 +34,22 @@ cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \ $(call cc-option,-m4a-nofpu,) cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,) +ifeq ($(cflags-y),) +# +# In the case where we are stuck with a compiler that has been uselessly +# restricted to a particular ISA, a favourite default of newer GCCs when +# extensive multilib targets are not provided, ensure we get the best fit +# regarding FP generation. This is necessary to avoid references to FP +# variants in libgcc where integer variants exist, which otherwise result +# in link errors. This is intentionally stupid (albeit many orders of +# magnitude less than GCC's default behaviour), as anything with a large +# number of multilib targets better have been built correctly for +# the target in mind. +# +cflags-y += $(shell $(CC) $(KBUILD_CFLAGS) -print-multi-lib | \ + grep nofpu | sed q | sed -e 's/^/-/;s/;.*$$//') +endif + cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml @@ -65,7 +77,8 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \ -R .stab -R .stabstr -S # Give the various platforms the opportunity to set default image types -defaultimage-$(CONFIG_SUPERH32) := zImage +defaultimage-$(CONFIG_SUPERH32) := zImage +defaultimage-$(CONFIG_SH_SH7785LCR) := uImage # Set some sensible Kbuild defaults KBUILD_DEFCONFIG := shx3_defconfig diff --git a/arch/sh/boot/compressed/Makefile_32 b/arch/sh/boot/compressed/Makefile_32 index 301e6d503256..b96a055b053e 100644 --- a/arch/sh/boot/compressed/Makefile_32 +++ b/arch/sh/boot/compressed/Makefile_32 @@ -23,7 +23,7 @@ IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \ LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) -ifeq ($(CONFIG_FTRACE),y) +ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig index 7892361eedc8..f43d18373f22 100644 --- a/arch/sh/cchips/Kconfig +++ b/arch/sh/cchips/Kconfig @@ -22,20 +22,6 @@ config HD64461 Say Y if you want support for the HD64461. Otherwise, say N. -config HD64465 - bool "Hitachi HD64465 companion chip support" - ---help--- - The Hitachi HD64465 provides an interface for - the SH7750 CPU, supporting a LCD controller, - CRT color controller, IrDA, USB, PCMCIA, - keyboard controller, and a printer interface. - - More information is available at - . - - Say Y if you want support for the HD64465. - Otherwise, say N. - endchoice # These will also be split into the Kconfig's below @@ -61,23 +47,4 @@ config HD64461_ENABLER via the HD64461 companion chip. Otherwise, say N. -config HD64465_IOBASE - hex "HD64465 start address" - depends on HD64465 - default "0xb0000000" - help - The default setting of the HD64465 IO base address is 0xb0000000. - - Do not change this unless you know what you are doing. - -config HD64465_IRQ - int "HD64465 IRQ" - depends on HD64465 - default "5" - help - The default setting of the HD64465 IRQ is 5. - - Do not change this unless you know what you are doing. - endmenu - diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile index f7de4076e242..9682e3ab668f 100644 --- a/arch/sh/cchips/hd6446x/Makefile +++ b/arch/sh/cchips/hd6446x/Makefile @@ -1,4 +1,3 @@ obj-$(CONFIG_HD64461) += hd64461.o -obj-$(CONFIG_HD64465) += hd64465/ EXTRA_CFLAGS += -Werror diff --git a/arch/sh/cchips/hd6446x/hd64465/Makefile b/arch/sh/cchips/hd6446x/hd64465/Makefile deleted file mode 100644 index f66edcb52c5b..000000000000 --- a/arch/sh/cchips/hd6446x/hd64465/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the HD64465 -# - -obj-y := setup.o io.o gpio.o - diff --git a/arch/sh/cchips/hd6446x/hd64465/gpio.c b/arch/sh/cchips/hd6446x/hd64465/gpio.c deleted file mode 100644 index 43431855ec86..000000000000 --- a/arch/sh/cchips/hd6446x/hd64465/gpio.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * $Id: gpio.c,v 1.4 2003/05/19 22:24:18 lethal Exp $ - * by Greg Banks - * (c) 2000 PocketPenguins Inc - * - * GPIO pin support for HD64465 companion chip. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define _PORTOF(portpin) (((portpin)>>3)&0x7) -#define _PINOF(portpin) ((portpin)&0x7) - -/* Register addresses parametrised on port */ -#define GPIO_CR(port) (HD64465_REG_GPACR+((port)<<1)) -#define GPIO_DR(port) (HD64465_REG_GPADR+((port)<<1)) -#define GPIO_ICR(port) (HD64465_REG_GPAICR+((port)<<1)) -#define GPIO_ISR(port) (HD64465_REG_GPAISR+((port)<<1)) - -#define GPIO_NPORTS 5 - -#define MODNAME "hd64465_gpio" - -EXPORT_SYMBOL(hd64465_gpio_configure); -EXPORT_SYMBOL(hd64465_gpio_get_pin); -EXPORT_SYMBOL(hd64465_gpio_get_port); -EXPORT_SYMBOL(hd64465_gpio_register_irq); -EXPORT_SYMBOL(hd64465_gpio_set_pin); -EXPORT_SYMBOL(hd64465_gpio_set_port); -EXPORT_SYMBOL(hd64465_gpio_unregister_irq); - -/* TODO: each port should be protected with a spinlock */ - - -void hd64465_gpio_configure(int portpin, int direction) -{ - unsigned short cr; - unsigned int shift = (_PINOF(portpin)<<1); - - cr = inw(GPIO_CR(_PORTOF(portpin))); - cr &= ~(3< - * (c) 2000 PocketPenguins Inc - * - * Derived from io_hd64461.c, which bore the message: - * Copyright (C) 2000 YAEGASHI Takeshi - * - * Typical I/O routines for HD64465 system. - */ - -#include -#include -#include -#include - - -#define HD64465_DEBUG 0 - -#if HD64465_DEBUG -#define DPRINTK(args...) printk(args) -#define DIPRINTK(n, args...) if (hd64465_io_debug>(n)) printk(args) -#else -#define DPRINTK(args...) -#define DIPRINTK(n, args...) -#endif - - - -/* This is a hack suitable only for debugging IO port problems */ -int hd64465_io_debug; -EXPORT_SYMBOL(hd64465_io_debug); - -/* Low iomap maps port 0-1K to addresses in 8byte chunks */ -#define HD64465_IOMAP_LO_THRESH 0x400 -#define HD64465_IOMAP_LO_SHIFT 3 -#define HD64465_IOMAP_LO_MASK ((1<>HD64465_IOMAP_LO_SHIFT) -static unsigned long hd64465_iomap_lo[HD64465_IOMAP_LO_NMAP]; -static unsigned char hd64465_iomap_lo_shift[HD64465_IOMAP_LO_NMAP]; - -/* High iomap maps port 1K-64K to addresses in 1K chunks */ -#define HD64465_IOMAP_HI_THRESH 0x10000 -#define HD64465_IOMAP_HI_SHIFT 10 -#define HD64465_IOMAP_HI_MASK ((1<>HD64465_IOMAP_HI_SHIFT) -static unsigned long hd64465_iomap_hi[HD64465_IOMAP_HI_NMAP]; -static unsigned char hd64465_iomap_hi_shift[HD64465_IOMAP_HI_NMAP]; - -#define PORT2ADDR(x) (sh_mv.mv_isa_port2addr(x)) - -void hd64465_port_map(unsigned short baseport, unsigned int nports, - unsigned long addr, unsigned char shift) -{ - unsigned int port, endport = baseport + nports; - - DPRINTK("hd64465_port_map(base=0x%04hx, n=0x%04hx, addr=0x%08lx,endport=0x%04x)\n", - baseport, nports, addr,endport); - - for (port = baseport ; - port < endport && port < HD64465_IOMAP_LO_THRESH ; - port += (1<>HD64465_IOMAP_LO_SHIFT] = addr; - hd64465_iomap_lo_shift[port>>HD64465_IOMAP_LO_SHIFT] = shift; - addr += (1<<(HD64465_IOMAP_LO_SHIFT)); - } - - for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH); - port < endport && port < HD64465_IOMAP_HI_THRESH ; - port += (1<>HD64465_IOMAP_HI_SHIFT] = addr; - hd64465_iomap_hi_shift[port>>HD64465_IOMAP_HI_SHIFT] = shift; - addr += (1<<(HD64465_IOMAP_HI_SHIFT)); - } -} -EXPORT_SYMBOL(hd64465_port_map); - -void hd64465_port_unmap(unsigned short baseport, unsigned int nports) -{ - unsigned int port, endport = baseport + nports; - - DPRINTK("hd64465_port_unmap(base=0x%04hx, n=0x%04hx)\n", - baseport, nports); - - for (port = baseport ; - port < endport && port < HD64465_IOMAP_LO_THRESH ; - port += (1<>HD64465_IOMAP_LO_SHIFT] = 0; - } - - for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH); - port < endport && port < HD64465_IOMAP_HI_THRESH ; - port += (1<>HD64465_IOMAP_HI_SHIFT] = 0; - } -} -EXPORT_SYMBOL(hd64465_port_unmap); - -unsigned long hd64465_isa_port2addr(unsigned long port) -{ - unsigned long addr = 0; - unsigned char shift; - - /* handle remapping of low IO ports */ - if (port < HD64465_IOMAP_LO_THRESH) { - addr = hd64465_iomap_lo[port >> HD64465_IOMAP_LO_SHIFT]; - shift = hd64465_iomap_lo_shift[port >> HD64465_IOMAP_LO_SHIFT]; - if (addr != 0) - addr += (port & HD64465_IOMAP_LO_MASK) << shift; - else - printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port); - } else if (port < HD64465_IOMAP_HI_THRESH) { - addr = hd64465_iomap_hi[port >> HD64465_IOMAP_HI_SHIFT]; - shift = hd64465_iomap_hi_shift[port >> HD64465_IOMAP_HI_SHIFT]; - if (addr != 0) - addr += (port & HD64465_IOMAP_HI_MASK) << shift; - else - printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port); - } - - /* HD64465 internal devices (0xb0000000) */ - else if (port < 0x20000) - addr = CONFIG_HD64465_IOBASE + port - 0x10000; - - /* Whole physical address space (0xa0000000) */ - else - addr = P2SEGADDR(port); - - DIPRINTK(2, "PORT2ADDR(0x%08lx) = 0x%08lx\n", port, addr); - - return addr; -} - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - -unsigned char hd64465_inb(unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - unsigned long b = (addr == 0 ? 0 : *(volatile unsigned char*)addr); - - DIPRINTK(0, "inb(%08lx) = %02x\n", addr, (unsigned)b); - return b; -} - -unsigned char hd64465_inb_p(unsigned long port) -{ - unsigned long v; - unsigned long addr = PORT2ADDR(port); - - v = (addr == 0 ? 0 : *(volatile unsigned char*)addr); - delay(); - DIPRINTK(0, "inb_p(%08lx) = %02x\n", addr, (unsigned)v); - return v; -} - -unsigned short hd64465_inw(unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - unsigned long b = (addr == 0 ? 0 : *(volatile unsigned short*)addr); - DIPRINTK(0, "inw(%08lx) = %04lx\n", addr, b); - return b; -} - -unsigned int hd64465_inl(unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - unsigned int b = (addr == 0 ? 0 : *(volatile unsigned long*)addr); - DIPRINTK(0, "inl(%08lx) = %08x\n", addr, b); - return b; -} - -void hd64465_outb(unsigned char b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - - DIPRINTK(0, "outb(%02x, %08lx)\n", (unsigned)b, addr); - if (addr != 0) - *(volatile unsigned char*)addr = b; -} - -void hd64465_outb_p(unsigned char b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - - DIPRINTK(0, "outb_p(%02x, %08lx)\n", (unsigned)b, addr); - if (addr != 0) - *(volatile unsigned char*)addr = b; - delay(); -} - -void hd64465_outw(unsigned short b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - DIPRINTK(0, "outw(%04x, %08lx)\n", (unsigned)b, addr); - if (addr != 0) - *(volatile unsigned short*)addr = b; -} - -void hd64465_outl(unsigned int b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - DIPRINTK(0, "outl(%08x, %08lx)\n", b, addr); - if (addr != 0) - *(volatile unsigned long*)addr = b; -} - diff --git a/arch/sh/cchips/hd6446x/hd64465/setup.c b/arch/sh/cchips/hd6446x/hd64465/setup.c deleted file mode 100644 index 9b8820c36701..000000000000 --- a/arch/sh/cchips/hd6446x/hd64465/setup.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * $Id: setup.c,v 1.4 2003/08/03 03:05:10 lethal Exp $ - * - * Setup and IRQ handling code for the HD64465 companion chip. - * by Greg Banks - * Copyright (c) 2000 PocketPenguins Inc - * - * Derived from setup_hd64461.c which bore the message: - * Copyright (C) 2000 YAEGASHI Takeshi - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void disable_hd64465_irq(unsigned int irq) -{ - unsigned short nimr; - unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); - - pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask); - nimr = inw(HD64465_REG_NIMR); - nimr |= mask; - outw(nimr, HD64465_REG_NIMR); -} - -static void enable_hd64465_irq(unsigned int irq) -{ - unsigned short nimr; - unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); - - pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask); - nimr = inw(HD64465_REG_NIMR); - nimr &= ~mask; - outw(nimr, HD64465_REG_NIMR); -} - -static void mask_and_ack_hd64465(unsigned int irq) -{ - disable_hd64465_irq(irq); -} - -static void end_hd64465_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_hd64465_irq(irq); -} - -static unsigned int startup_hd64465_irq(unsigned int irq) -{ - enable_hd64465_irq(irq); - return 0; -} - -static void shutdown_hd64465_irq(unsigned int irq) -{ - disable_hd64465_irq(irq); -} - -static struct hw_interrupt_type hd64465_irq_type = { - .typename = "HD64465-IRQ", - .startup = startup_hd64465_irq, - .shutdown = shutdown_hd64465_irq, - .enable = enable_hd64465_irq, - .disable = disable_hd64465_irq, - .ack = mask_and_ack_hd64465, - .end = end_hd64465_irq, -}; - -static irqreturn_t hd64465_interrupt(int irq, void *dev_id) -{ - printk(KERN_INFO - "HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n", - inw(HD64465_REG_NIRR), inw(HD64465_REG_NIMR)); - - return IRQ_NONE; -} - -/* - * Support for a secondary IRQ demux step. This is necessary - * because the HD64465 presents a very thin interface to the - * PCMCIA bus; a lot of features (such as remapping interrupts) - * normally done in hardware by other PCMCIA host bridges is - * instead done in software. - */ -static struct { - int (*func)(int, void *); - void *dev; -} hd64465_demux[HD64465_IRQ_NUM]; - -void hd64465_register_irq_demux(int irq, - int (*demux)(int irq, void *dev), void *dev) -{ - hd64465_demux[irq - HD64465_IRQ_BASE].func = demux; - hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev; -} -EXPORT_SYMBOL(hd64465_register_irq_demux); - -void hd64465_unregister_irq_demux(int irq) -{ - hd64465_demux[irq - HD64465_IRQ_BASE].func = 0; -} -EXPORT_SYMBOL(hd64465_unregister_irq_demux); - -int hd64465_irq_demux(int irq) -{ - if (irq == CONFIG_HD64465_IRQ) { - unsigned short i, bit; - unsigned short nirr = inw(HD64465_REG_NIRR); - unsigned short nimr = inw(HD64465_REG_NIMR); - - pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr); - nirr &= ~nimr; - for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++) - if (nirr & bit) - break; - - if (i < HD64465_IRQ_NUM) { - irq = HD64465_IRQ_BASE + i; - if (hd64465_demux[i].func != 0) - irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev); - } - } - return irq; -} - -static struct irqaction irq0 = { - .handler = hd64465_interrupt, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, - .name = "HD64465", -}; - -static int __init setup_hd64465(void) -{ - int i; - unsigned short rev; - unsigned short smscr; - - if (!MACH_HD64465) - return 0; - - printk(KERN_INFO "HD64465 configured at 0x%x on irq %d(mapped into %d to %d)\n", - CONFIG_HD64465_IOBASE, - CONFIG_HD64465_IRQ, - HD64465_IRQ_BASE, - HD64465_IRQ_BASE+HD64465_IRQ_NUM-1); - - if (inw(HD64465_REG_SDID) != HD64465_SDID) { - printk(KERN_ERR "HD64465 device ID not found, check base address\n"); - } - - rev = inw(HD64465_REG_SRR); - printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff); - - outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */ - - for (i = 0; i < HD64465_IRQ_NUM ; i++) { - irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type; - } - - setup_irq(CONFIG_HD64465_IRQ, &irq0); - - /* wake up the UART from STANDBY at this point */ - smscr = inw(HD64465_REG_SMSCR); - outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR); - - /* remap IO ports for first ISA serial port to HD64465 UART */ - hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1); - - return 0; -} -module_init(setup_hd64465); diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig index 624c47aa66d3..30cac42f25e7 100644 --- a/arch/sh/configs/migor_defconfig +++ b/arch/sh/configs/migor_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27 -# Tue Oct 21 12:57:28 2008 +# Linux kernel version: 2.6.28-rc2 +# Fri Oct 31 15:58:06 2008 # CONFIG_SUPERH=y CONFIG_SUPERH32=y @@ -73,7 +73,6 @@ CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -285,7 +284,7 @@ CONFIG_GUSA=y CONFIG_ZERO_PAGE_OFFSET=0x00001000 CONFIG_BOOT_LINK_OFFSET=0x00800000 CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on" +CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp" # # Bus options @@ -718,6 +717,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set @@ -969,7 +969,23 @@ CONFIG_TMPFS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -1019,7 +1035,12 @@ CONFIG_CRYPTO=y # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -1096,7 +1117,7 @@ CONFIG_CRYPTO=y # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_HW is not set # # Library routines diff --git a/arch/sh/configs/ul2_defconfig b/arch/sh/configs/ul2_defconfig new file mode 100644 index 000000000000..9afff67d9ff2 --- /dev/null +++ b/arch/sh/configs/ul2_defconfig @@ -0,0 +1,1169 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28-rc2 +# Tue Oct 28 17:35:17 2008 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_SYS_SUPPORTS_NUMA=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +CONFIG_CPU_SH4AL_DSP=y +CONFIG_CPU_SHX2=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +# CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +CONFIG_CPU_SUBTYPE_SH7366=y +# CONFIG_CPU_SUBTYPE_SH5_101 is not set +# CONFIG_CPU_SUBTYPE_SH5_103 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_MEMORY_START=0x08000000 +CONFIG_MEMORY_SIZE=0x01f00000 +CONFIG_29BIT=y +# CONFIG_X2TLB is not set +CONFIG_VSYSCALL=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=1 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_HUGETLB_PAGE_SIZE_64K=y +# CONFIG_HUGETLB_PAGE_SIZE_256K is not set +# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set +# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set +# CONFIG_HUGETLB_PAGE_SIZE_64MB is not set +# CONFIG_HUGETLB_PAGE_SIZE_512MB is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +# CONFIG_DISCONTIGMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_STATIC=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_MIGRATION is not set +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=2 +CONFIG_UNEVICTABLE_LRU=y + +# +# Cache configuration +# +# CONFIG_SH_DIRECT_MAPPED is not set +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_SH_FPU_EMU is not set +# CONFIG_SH_DSP is not set +# CONFIG_SH_STORE_QUEUES is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_PTEA=y +CONFIG_CPU_HAS_DSP=y + +# +# Board support +# + +# +# Timer and clock configuration +# +CONFIG_SH_TMU=y +CONFIG_SH_TIMER_IRQ=16 +CONFIG_SH_PCLK_FREQ=33333333 +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +# CONFIG_SH_DMA is not set + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +# CONFIG_HEARTBEAT is not set +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_KEXEC=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_SECCOMP is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_GUSA=y + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/nfs ip=dhcp" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211=y +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_RC_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT="pid" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_IEEE80211=m +CONFIG_IEEE80211_DEBUG=y +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +CONFIG_PATA_PLATFORM=y +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_STNIC is not set +# CONFIG_SMC91X is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_DEBUG=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_HOSTAP is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=1 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_R8A66597_HCD=y +# CONFIG_SUPERH_ON_CHIP_R8A66597 is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FTRACE=y +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +# CONFIG_SH_STANDARD_BIOS is not set +# CONFIG_EARLY_SCIF_CONSOLE is not set +# CONFIG_SH_KGDB is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/sh/include/asm/byteorder.h b/arch/sh/include/asm/byteorder.h index 4c13e6117563..f5fa0653ebc6 100644 --- a/arch/sh/include/asm/byteorder.h +++ b/arch/sh/include/asm/byteorder.h @@ -8,7 +8,15 @@ #include #include -static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) +#ifdef __LITTLE_ENDIAN__ +# define __LITTLE_ENDIAN +#else +# define __BIG_ENDIAN +#endif + +#define __SWAB_64_THRU_32__ + +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( #ifdef __SH5__ @@ -24,8 +32,9 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) return x; } +#define __arch_swab32 __arch_swab32 -static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( #ifdef __SH5__ @@ -39,32 +48,21 @@ static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) return x; } +#define __arch_swab16 __arch_swab16 -static inline __u64 ___arch__swab64(__u64 val) +static inline __u64 __arch_swab64(__u64 val) { union { struct { __u32 a,b; } s; __u64 u; } v, w; v.u = val; - w.s.b = ___arch__swab32(v.s.a); - w.s.a = ___arch__swab32(v.s.b); + w.s.b = __arch_swab32(v.s.a); + w.s.a = __arch_swab32(v.s.b); return w.u; } +#define __arch_swab64 __arch_swab64 -#define __arch__swab64(x) ___arch__swab64(x) -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __LITTLE_ENDIAN__ -#include -#else -#include -#endif +#include #endif /* __ASM_SH_BYTEORDER_H */ diff --git a/arch/sh/include/asm/hd64465/gpio.h b/arch/sh/include/asm/hd64465/gpio.h deleted file mode 100644 index a3cdca2713dd..000000000000 --- a/arch/sh/include/asm/hd64465/gpio.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef _ASM_SH_HD64465_GPIO_ -#define _ASM_SH_HD64465_GPIO_ 1 -/* - * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $ - * - * Hitachi HD64465 companion chip: General Purpose IO pins support. - * This layer enables other device drivers to configure GPIO - * pins, get and set their values, and register an interrupt - * routine for when input pins change in hardware. - * - * by Greg Banks - * (c) 2000 PocketPenguins Inc. - */ -#include - -/* Macro to construct a portpin number (used in all - * subsequent functions) from a port letter and a pin - * number, e.g. HD64465_GPIO_PORTPIN('A', 5). - */ -#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin)) - -/* Pin configuration constants for _configure() */ -#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */ -#define HD64465_GPIO_OUT 1 /* output */ -#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */ -#define HD64465_GPIO_IN 3 /* input */ - -/* Configure a pin's direction */ -extern void hd64465_gpio_configure(int portpin, int direction); - -/* Get, set value */ -extern void hd64465_gpio_set_pin(int portpin, unsigned int value); -extern unsigned int hd64465_gpio_get_pin(int portpin); -extern void hd64465_gpio_set_port(int port, unsigned int value); -extern unsigned int hd64465_gpio_get_port(int port); - -/* mode constants for _register_irq() */ -#define HD64465_GPIO_FALLING 0 -#define HD64465_GPIO_RISING 1 - -/* Interrupt on external value change */ -extern void hd64465_gpio_register_irq(int portpin, int mode, - void (*handler)(int portpin, void *dev), void *dev); -extern void hd64465_gpio_unregister_irq(int portpin); - -#endif /* _ASM_SH_HD64465_GPIO_ */ diff --git a/arch/sh/include/asm/hd64465/hd64465.h b/arch/sh/include/asm/hd64465/hd64465.h deleted file mode 100644 index cfd0e803d2a2..000000000000 --- a/arch/sh/include/asm/hd64465/hd64465.h +++ /dev/null @@ -1,256 +0,0 @@ -#ifndef _ASM_SH_HD64465_ -#define _ASM_SH_HD64465_ 1 -/* - * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $ - * - * Hitachi HD64465 companion chip support - * - * by Greg Banks - * (c) 2000 PocketPenguins Inc. - * - * Derived from which bore the message: - * Copyright (C) 2000 YAEGASHI Takeshi - */ -#include -#include - -/* - * Note that registers are defined here as virtual port numbers, - * which have no meaning except to get translated by hd64465_isa_port2addr() - * to an address in the range 0xb0000000-0xb3ffffff. Note that - * this translation happens to consist of adding the lower 16 bits - * of the virtual port number to 0xb0000000. Note also that the manual - * shows addresses as absolute physical addresses starting at 0x10000000, - * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the - * manual, and accessed using address 0xb0005000 - Greg. - */ - -/* System registers */ -#define HD64465_REG_SRR 0x1000c /* System Revision Register */ -#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */ -#define HD64465_SDID 0x8122 /* 64465 device ID */ - -/* Power Management registers */ -#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */ -#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */ -#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */ -#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */ -#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */ -#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */ -#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */ -#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */ -#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */ -#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */ -#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */ -#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */ -#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */ - -/* Interrupt Controller registers */ -#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */ -#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */ -#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */ - -/* Timer registers */ -#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */ -#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */ -#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */ -#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */ -#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */ -#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */ -#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */ -#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */ -#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */ -#define HD64465_TCR_PST_1 0x06 /* 1:1 */ -#define HD64465_TCR_PST_4 0x04 /* 1:4 */ -#define HD64465_TCR_PST_8 0x02 /* 1:8 */ -#define HD64465_TCR_PST_16 0x00 /* 1:16 */ -#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */ -#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */ -#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */ -#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */ -#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */ -#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */ -#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */ -#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */ -#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */ - -/* Analog/Digital Converter registers */ -#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */ -#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */ -#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */ -#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */ -#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */ -#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */ -#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */ -#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */ -#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */ -#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */ -#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */ -#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */ -#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */ -#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */ - - -/* General Purpose I/O ports registers */ -#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */ -#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */ -#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */ -#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */ -#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */ -#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */ -#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */ -#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */ -#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */ -#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */ -#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */ -#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */ -#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */ -#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */ -#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */ -#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */ -#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */ -#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */ -#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */ -#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */ - -/* PCMCIA bridge interface */ -#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */ -#define HD64465_PCCISR_PIREQ 0x80 -#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */ -#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */ -#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */ -#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */ -#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */ -#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */ -#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */ -#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */ -#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64465_PCCGCR_PDRV 0x80 /* output drive */ -#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */ -#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */ -#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */ -#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */ -#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */ -#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */ -#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */ -#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */ -#define HD64465_PCCCSCR_PRC 0x04 /* ready change */ -#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */ -#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */ -#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */ -#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */ -#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */ -#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */ -#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */ -#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */ -#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */ -#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/ -#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */ -#define HD64465_PCCSCR_SWP 0x01 /* write protect */ -#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */ -#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */ - - -/* PS/2 Keyboard and mouse controller -- *not* register compatible */ -#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */ -#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */ -#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */ -#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */ -#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */ -#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */ -#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */ -#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */ -#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */ -#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */ -#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */ -#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */ -#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */ -#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */ - - -/* - * Logical address at which the HD64465 is mapped. Note that this - * should always be in the P2 segment (uncached and untranslated). - */ -#ifndef CONFIG_HD64465_IOBASE -#define CONFIG_HD64465_IOBASE 0xb0000000 -#endif -/* - * The HD64465 multiplexes all its modules' interrupts onto - * this single interrupt. - */ -#ifndef CONFIG_HD64465_IRQ -#define CONFIG_HD64465_IRQ 5 -#endif - - -#define _HD64465_IO_MASK 0xf8000000 -#define is_hd64465_addr(addr) \ - ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK)) - -/* - * A range of 16 virtual interrupts generated by - * demuxing the HD64465 muxed interrupt. - */ -#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE -#define HD64465_IRQ_NUM 16 -#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0) -#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1) -#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2) -#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3) -/* bit 4 is reserved */ -#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5) -#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6) -#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7) -#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8) -#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9) -#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10) -#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11) -#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12) -#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13) -#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14) -#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15) - -/* Constants for PCMCIA mappings */ -#define HD64465_PCC_WINDOW 0x01000000 - -#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */ -#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE) -#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW) -#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW) - -#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */ -#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE) -#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW) -#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW) - -/* - * Base of USB controller interface (as memory) - */ -#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000) -#define HD64465_USB_LEN 0x1000 -/* - * Base of embedded SRAM, used for USB controller. - */ -#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000) -#define HD64465_SRAM_LEN 0x1000 - - - -#endif /* _ASM_SH_HD64465_ */ diff --git a/arch/sh/include/asm/hd64465/io.h b/arch/sh/include/asm/hd64465/io.h deleted file mode 100644 index 139f1472e5bb..000000000000 --- a/arch/sh/include/asm/hd64465/io.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * include/asm-sh/hd64465/io.h - * - * By Greg Banks - * (c) 2000 PocketPenguins Inc. - * - * Derived from io_hd64461.h, which bore the message: - * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller". - */ - -#ifndef _ASM_SH_IO_HD64465_H -#define _ASM_SH_IO_HD64465_H - -extern unsigned char hd64465_inb(unsigned long port); -extern unsigned short hd64465_inw(unsigned long port); -extern unsigned int hd64465_inl(unsigned long port); - -extern void hd64465_outb(unsigned char value, unsigned long port); -extern void hd64465_outw(unsigned short value, unsigned long port); -extern void hd64465_outl(unsigned int value, unsigned long port); - -extern unsigned char hd64465_inb_p(unsigned long port); -extern void hd64465_outb_p(unsigned char value, unsigned long port); - -extern unsigned long hd64465_isa_port2addr(unsigned long offset); -extern int hd64465_irq_demux(int irq); -/* Provision for generic secondary demux step -- used by PCMCIA code */ -extern void hd64465_register_irq_demux(int irq, - int (*demux)(int irq, void *dev), void *dev); -extern void hd64465_unregister_irq_demux(int irq); -/* Set this variable to 1 to see port traffic */ -extern int hd64465_io_debug; -/* Map a range of ports to a range of kernel virtual memory. - */ -extern void hd64465_port_map(unsigned short baseport, unsigned int nports, - unsigned long addr, unsigned char shift); -extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports); - -#endif /* _ASM_SH_IO_HD64465_H */ diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index 436c28539577..65eaae34e753 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -293,6 +293,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) */ #define xlate_dev_kmem_ptr(p) p +#define ARCH_HAS_VALID_PHYS_ADDR_RANGE +int valid_phys_addr_range(unsigned long addr, size_t size); +int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); + #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h index 52220d70a096..b517ae08b9c0 100644 --- a/arch/sh/include/asm/pgtable.h +++ b/arch/sh/include/asm/pgtable.h @@ -148,6 +148,12 @@ extern void paging_init(void); extern void page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd); +#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_CPU_SH4) && defined(CONFIG_MMU) +extern void kmap_coherent_init(void); +#else +#define kmap_coherent_init() do { } while (0) +#endif + #include #endif /* __ASM_SH_PGTABLE_H */ diff --git a/arch/sh/include/asm/serial.h b/arch/sh/include/asm/serial.h index e13cc948ee60..11f854dd1363 100644 --- a/arch/sh/include/asm/serial.h +++ b/arch/sh/include/asm/serial.h @@ -7,8 +7,6 @@ #ifndef _ASM_SERIAL_H #define _ASM_SERIAL_H -#include - /* * This assumes you have a 1.8432 MHz clock for your UART. * @@ -18,19 +16,4 @@ */ #define BASE_BAUD ( 1843200 / 16 ) -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) - -#ifdef CONFIG_HD64465 -#include - -#define SERIAL_PORT_DFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ - -#else - -#define SERIAL_PORT_DFNS - -#endif - #endif /* _ASM_SERIAL_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/rtc.h b/arch/sh/include/cpu-sh4/cpu/rtc.h index 25b1e6adfe8c..95e6fb76c24d 100644 --- a/arch/sh/include/cpu-sh4/cpu/rtc.h +++ b/arch/sh/include/cpu-sh4/cpu/rtc.h @@ -1,7 +1,7 @@ #ifndef __ASM_SH_CPU_SH4_RTC_H #define __ASM_SH_CPU_SH4_RTC_H -#ifdef CONFIG_CPU_SUBTYPE_SH7723 +#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7723) #define rtc_reg_size sizeof(u16) #else #define rtc_reg_size sizeof(u32) diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 6851dba02f31..e17db39b97aa 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -36,6 +36,32 @@ static struct platform_device iic_device = { .resource = iic_resources, }; +static struct resource usb_host_resources[] = { + [0] = { + .name = "r8a66597_hcd", + .start = 0xa4d80000, + .end = 0xa4d800ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "r8a66597_hcd", + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_host_resources), + .resource = usb_host_resources, +}; + static struct uio_info vpu_platform_data = { .name = "VPU5", .version = "0", @@ -142,6 +168,7 @@ static struct platform_device sci_device = { static struct platform_device *sh7366_devices[] __initdata = { &iic_device, &sci_device, + &usb_host_device, &vpu_device, &veu0_device, &veu1_device, @@ -158,6 +185,7 @@ static int __init sh7366_devices_setup(void) clk_always_enable("mstp022"); /* INTC */ clk_always_enable("mstp020"); /* SuperHyway */ clk_always_enable("mstp109"); /* I2C */ + clk_always_enable("mstp211"); /* USB */ clk_always_enable("mstp207"); /* VEU-2 */ clk_always_enable("mstp202"); /* VEU-1 */ clk_always_enable("mstp201"); /* VPU */ diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index de1ede92176e..ef77ee1d9f53 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -1,7 +1,7 @@ /* * SH7722 Setup * - * Copyright (C) 2006 - 2007 Paul Mundt + * Copyright (C) 2006 - 2008 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -16,6 +16,36 @@ #include #include +static struct resource rtc_resources[] = { + [0] = { + .start = 0xa465fec0, + .end = 0xa465fec0 + 0x58 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 45, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 46, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 44, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + static struct resource usbf_resources[] = { [0] = { .name = "m66592_udc", @@ -150,6 +180,7 @@ static struct platform_device sci_device = { }; static struct platform_device *sh7722_devices[] __initdata = { + &rtc_device, &usbf_device, &iic_device, &sci_device, @@ -202,7 +233,6 @@ enum { IRDA, JPU, LCDC, /* interrupt groups */ - SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a7412cede534..6d9e6972cfc9 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -119,17 +119,17 @@ static struct plat_sci_port sci_platform_data[] = { },{ .mapbase = 0xa4e30000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 56, 56, 56, 56 }, },{ .mapbase = 0xa4e40000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 88, 88, 88, 88 }, },{ .mapbase = 0xa4e50000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 109, 109, 109, 109 }, }, { .flags = 0, diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index 6b7d166694e2..a952dcf9999d 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -75,6 +75,7 @@ static struct console bios_console = { #endif static struct uart_port scif_port = { + .type = PORT_SCIF, .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT, .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT, }; @@ -84,9 +85,9 @@ static void scif_sercon_putc(int c) while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE)) ; - sci_out(&scif_port, SCxTDR, c); sci_in(&scif_port, SCxSR); sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40)); + sci_out(&scif_port, SCxTDR, c); while ((sci_in(&scif_port, SCxSR) & 0x40) == 0) ; diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S index 1a5cf9dd82de..5b7efc4016fa 100644 --- a/arch/sh/kernel/entry-common.S +++ b/arch/sh/kernel/entry-common.S @@ -372,7 +372,7 @@ syscall_exit: 7: .long do_syscall_trace_enter 8: .long do_syscall_trace_leave -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER .align 2 .globl _mcount .type _mcount,@function @@ -414,4 +414,4 @@ skip_trace: ftrace_stub: rts nop -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c index d366a7443720..92ae5e6c099e 100644 --- a/arch/sh/kernel/sh_ksyms_32.c +++ b/arch/sh/kernel/sh_ksyms_32.c @@ -50,7 +50,10 @@ EXPORT_SYMBOL(__udelay); EXPORT_SYMBOL(__ndelay); EXPORT_SYMBOL(__const_udelay); -#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) +#define DECLARE_EXPORT(name) \ + extern void name(void);EXPORT_SYMBOL(name) +#define MAYBE_DECLARE_EXPORT(name) \ + extern void name(void) __weak;EXPORT_SYMBOL(name) /* These symbols are generated by the compiler itself */ DECLARE_EXPORT(__udivsi3); @@ -109,10 +112,8 @@ DECLARE_EXPORT(__movmemSI12_i4); * compiler which include backported patches. */ DECLARE_EXPORT(__udiv_qrnnd_16); -#if !defined(CONFIG_CPU_SH2) -DECLARE_EXPORT(__sdivsi3_i4i); -DECLARE_EXPORT(__udivsi3_i4i); -#endif +MAYBE_DECLARE_EXPORT(__sdivsi3_i4i); +MAYBE_DECLARE_EXPORT(__udivsi3_i4i); #endif #else /* GCC 3.x */ DECLARE_EXPORT(__movstr_i4_even); @@ -133,7 +134,7 @@ EXPORT_SYMBOL(flush_dcache_page); EXPORT_SYMBOL(clear_user_page); #endif -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER EXPORT_SYMBOL(mcount); #endif EXPORT_SYMBOL(csum_partial); diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c index aaaf90d06b85..3c61ddd4d43e 100644 --- a/arch/sh/kernel/timers/timer-tmu.c +++ b/arch/sh/kernel/timers/timer-tmu.c @@ -120,7 +120,7 @@ static void tmu_set_mode(enum clock_event_mode mode, { switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - ctrl_outl(ctrl_inl(TMU0_TCNT), TMU0_TCOR); + ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR); break; case CLOCK_EVT_MODE_ONESHOT: ctrl_outl(0, TMU0_TCOR); diff --git a/arch/sh/lib/copy_page.S b/arch/sh/lib/copy_page.S index 5d12e657be34..43de7e8e4e17 100644 --- a/arch/sh/lib/copy_page.S +++ b/arch/sh/lib/copy_page.S @@ -80,6 +80,11 @@ ENTRY(copy_page) .section __ex_table, "a"; \ .long 9999b, 6000f ; \ .previous +#define EX_NO_POP(...) \ + 9999: __VA_ARGS__ ; \ + .section __ex_table, "a"; \ + .long 9999b, 6005f ; \ + .previous ENTRY(__copy_user) ! Check if small number of bytes mov #11,r0 @@ -139,9 +144,9 @@ EX( mov.b r1,@r4 ) bt 1f 2: -EX( mov.b @r5+,r0 ) +EX_NO_POP( mov.b @r5+,r0 ) dt r6 -EX( mov.b r0,@r4 ) +EX_NO_POP( mov.b r0,@r4 ) bf/s 2b add #1,r4 @@ -150,7 +155,7 @@ EX( mov.b r0,@r4 ) # Exception handler: .section .fixup, "ax" -6000: +6005: mov.l 8000f,r1 mov r3,r0 jmp @r1 diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32 index 70e0906023cc..f066e76da204 100644 --- a/arch/sh/mm/Makefile_32 +++ b/arch/sh/mm/Makefile_32 @@ -2,7 +2,7 @@ # Makefile for the Linux SuperH-specific parts of the memory manager. # -obj-y := init.o extable_32.o consistent.o +obj-y := init.o extable_32.o consistent.o mmap.o ifndef CONFIG_CACHE_OFF cache-$(CONFIG_CPU_SH2) := cache-sh2.o diff --git a/arch/sh/mm/Makefile_64 b/arch/sh/mm/Makefile_64 index 0d92a8a3ac9a..9481d0f54efd 100644 --- a/arch/sh/mm/Makefile_64 +++ b/arch/sh/mm/Makefile_64 @@ -2,7 +2,7 @@ # Makefile for the Linux SuperH-specific parts of the memory manager. # -obj-y := init.o consistent.o +obj-y := init.o consistent.o mmap.o mmu-y := tlb-nommu.o pg-nommu.o extable_32.o mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \ diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c index 62c0c5f35120..24d86a794065 100644 --- a/arch/sh/mm/cache-sh2a.c +++ b/arch/sh/mm/cache-sh2a.c @@ -59,7 +59,7 @@ void __flush_purge_region(void *start, int size) for (v = begin; v < end; v+=L1_CACHE_BYTES) { ctrl_outl((v & CACHE_PHYSADDR_MASK), - CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); + CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); } back_to_cached(); local_irq_restore(flags); @@ -82,14 +82,14 @@ void __flush_invalidate_region(void *start, int size) /* I-cache invalidate */ for (v = begin; v < end; v+=L1_CACHE_BYTES) { ctrl_outl((v & CACHE_PHYSADDR_MASK), - CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); + CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); } #else for (v = begin; v < end; v+=L1_CACHE_BYTES) { ctrl_outl((v & CACHE_PHYSADDR_MASK), - CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); + CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); ctrl_outl((v & CACHE_PHYSADDR_MASK), - CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); + CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); } #endif back_to_cached(); diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index 4abf00031dae..6cbef8caeb56 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -137,6 +137,7 @@ void __init page_table_range_init(unsigned long start, unsigned long end, void __init paging_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES]; + unsigned long vaddr; int nid; /* We don't need to map the kernel through the TLB, as @@ -148,10 +149,15 @@ void __init paging_init(void) * check for a null value. */ set_TTB(swapper_pg_dir); - /* Populate the relevant portions of swapper_pg_dir so that + /* + * Populate the relevant portions of swapper_pg_dir so that * we can use the fixmap entries without calling kmalloc. - * pte's will be filled in by __set_fixmap(). */ - page_table_range_init(FIXADDR_START, FIXADDR_TOP, swapper_pg_dir); + * pte's will be filled in by __set_fixmap(). + */ + vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; + page_table_range_init(vaddr, 0, swapper_pg_dir); + + kmap_coherent_init(); memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c new file mode 100644 index 000000000000..8837d511710a --- /dev/null +++ b/arch/sh/mm/mmap.c @@ -0,0 +1,31 @@ +/* + * arch/sh/mm/mmap.c + * + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include + +/* + * You really shouldn't be using read() or write() on /dev/mem. This + * might go away in the future. + */ +int valid_phys_addr_range(unsigned long addr, size_t count) +{ + if (addr < __MEMORY_START) + return 0; + if (addr + count > __pa(high_memory)) + return 0; + + return 1; +} + +int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) +{ + return 1; +} diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c index 38870e0fc182..2fe14da1f839 100644 --- a/arch/sh/mm/pg-sh4.c +++ b/arch/sh/mm/pg-sh4.c @@ -7,6 +7,7 @@ * Released under the terms of the GNU GPL v2.0. */ #include +#include #include #include #include @@ -16,6 +17,20 @@ #define CACHE_ALIAS (current_cpu_data.dcache.alias_mask) +#define kmap_get_fixmap_pte(vaddr) \ + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) + +static pte_t *kmap_coherent_pte; + +void __init kmap_coherent_init(void) +{ + unsigned long vaddr; + + /* cache the first coherent kmap pte */ + vaddr = __fix_to_virt(FIX_CMAP_BEGIN); + kmap_coherent_pte = kmap_get_fixmap_pte(vaddr); +} + static inline void *kmap_coherent(struct page *page, unsigned long addr) { enum fixed_addresses idx; @@ -34,6 +49,8 @@ static inline void *kmap_coherent(struct page *page, unsigned long addr) update_mmu_cache(NULL, vaddr, pte); + set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte); + return (void *)vaddr; } diff --git a/arch/sh/oprofile/op_model_sh7750.c b/arch/sh/oprofile/op_model_sh7750.c index 6b9a98e07004..008b3b03750a 100644 --- a/arch/sh/oprofile/op_model_sh7750.c +++ b/arch/sh/oprofile/op_model_sh7750.c @@ -255,10 +255,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) return -ENODEV; ops = &sh7750_perf_counter_ops; - ops->cpu_type = (char *)get_cpu_subtype(¤t_cpu_data); + ops->cpu_type = "sh/sh7750"; - printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n", - sh7750_perf_counter_ops.cpu_type); + printk(KERN_INFO "oprofile: using SH-4 performance monitoring.\n"); /* Clear the counters */ ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1); @@ -270,4 +269,3 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) void oprofile_arch_exit(void) { } - diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index d4fb11f7e2ee..d0c2928d1066 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -13,7 +13,6 @@ RTS7751R2D SH_RTS7751R2D # List of companion chips / MFDs. # HD64461 HD64461 -HD64465 HD64465 # # List of boards. diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h index 68b98a7e6454..9cf4ae0cd7ba 100644 --- a/arch/sparc/include/asm/bitops_32.h +++ b/arch/sparc/include/asm/bitops_32.h @@ -98,6 +98,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) #include #include #include +#include #include #include #include diff --git a/arch/sparc/include/asm/byteorder.h b/arch/sparc/include/asm/byteorder.h index bcd83aa351c5..5a70f137f1f7 100644 --- a/arch/sparc/include/asm/byteorder.h +++ b/arch/sparc/include/asm/byteorder.h @@ -4,15 +4,14 @@ #include #include -#ifdef __GNUC__ +#define __BIG_ENDIAN #ifdef CONFIG_SPARC32 #define __SWAB_64_THRU_32__ #endif #ifdef CONFIG_SPARC64 - -static inline __u16 ___arch__swab16p(const __u16 *addr) +static inline __u16 __arch_swab16p(const __u16 *addr) { __u16 ret; @@ -21,8 +20,9 @@ static inline __u16 ___arch__swab16p(const __u16 *addr) : "r" (addr), "i" (ASI_PL)); return ret; } +#define __arch_swab16p __arch_swab16p -static inline __u32 ___arch__swab32p(const __u32 *addr) +static inline __u32 __arch_swab32p(const __u32 *addr) { __u32 ret; @@ -31,8 +31,9 @@ static inline __u32 ___arch__swab32p(const __u32 *addr) : "r" (addr), "i" (ASI_PL)); return ret; } +#define __arch_swab32p __arch_swab32p -static inline __u64 ___arch__swab64p(const __u64 *addr) +static inline __u64 __arch_swab64p(const __u64 *addr) { __u64 ret; @@ -41,17 +42,10 @@ static inline __u64 ___arch__swab64p(const __u64 *addr) : "r" (addr), "i" (ASI_PL)); return ret; } - -#define __arch__swab16p(x) ___arch__swab16p(x) -#define __arch__swab32p(x) ___arch__swab32p(x) -#define __arch__swab64p(x) ___arch__swab64p(x) +#define __arch_swab64p __arch_swab64p #endif /* CONFIG_SPARC64 */ -#define __BYTEORDER_HAS_U64__ - -#endif - -#include +#include #endif /* _SPARC_BYTEORDER_H */ diff --git a/arch/sparc/include/asm/kdebug_32.h b/arch/sparc/include/asm/kdebug_32.h index f69fe7d84b3c..1d0b240222ef 100644 --- a/arch/sparc/include/asm/kdebug_32.h +++ b/arch/sparc/include/asm/kdebug_32.h @@ -60,6 +60,7 @@ static inline void sp_enter_debugger(void) enum die_val { DIE_UNUSED, + DIE_OOPS, }; #endif /* !(__ASSEMBLY__) */ diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h index 137a6bd72fc8..59fcebb8f440 100644 --- a/arch/sparc/include/asm/processor_64.h +++ b/arch/sparc/include/asm/processor_64.h @@ -36,10 +36,10 @@ #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3)) #endif -#define TASK_SIZE ((unsigned long)-VPTE_SIZE) #define TASK_SIZE_OF(tsk) \ (test_tsk_thread_flag(tsk,TIF_32BIT) ? \ - (1UL << 32UL) : TASK_SIZE) + (1UL << 32UL) : ((unsigned long)-VPTE_SIZE)) +#define TASK_SIZE TASK_SIZE_OF(current) #ifdef __KERNEL__ #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) diff --git a/arch/sparc/include/asm/ptrace_32.h b/arch/sparc/include/asm/ptrace_32.h index d409c4f21a5c..4cef450167dd 100644 --- a/arch/sparc/include/asm/ptrace_32.h +++ b/arch/sparc/include/asm/ptrace_32.h @@ -62,6 +62,8 @@ struct sparc_stackf { #ifdef __KERNEL__ +#include + static inline bool pt_regs_is_syscall(struct pt_regs *regs) { return (regs->psr & PSR_SYSCALL); @@ -72,6 +74,14 @@ static inline bool pt_regs_clear_syscall(struct pt_regs *regs) return (regs->psr &= ~PSR_SYSCALL); } +#define arch_ptrace_stop_needed(exit_code, info) \ +({ flush_user_windows(); \ + current_thread_info()->w_saved != 0; \ +}) + +#define arch_ptrace_stop(exit_code, info) \ + synchronize_user_stack() + #define user_mode(regs) (!((regs)->psr & PSR_PS)) #define instruction_pointer(regs) ((regs)->pc) #define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP]) diff --git a/arch/sparc/include/asm/ptrace_64.h b/arch/sparc/include/asm/ptrace_64.h index 3d3e9c161d8b..cd6fbfc20435 100644 --- a/arch/sparc/include/asm/ptrace_64.h +++ b/arch/sparc/include/asm/ptrace_64.h @@ -114,6 +114,7 @@ struct sparc_trapf { #ifdef __KERNEL__ #include +#include static inline int pt_regs_trap_type(struct pt_regs *regs) { @@ -130,6 +131,14 @@ static inline bool pt_regs_clear_syscall(struct pt_regs *regs) return (regs->tstate &= ~TSTATE_SYSCALL); } +#define arch_ptrace_stop_needed(exit_code, info) \ +({ flush_user_windows(); \ + get_thread_wsaved() != 0; \ +}) + +#define arch_ptrace_stop(exit_code, info) \ + synchronize_user_stack() + struct global_reg_snapshot { unsigned long tstate; unsigned long tpc; @@ -142,8 +151,6 @@ struct global_reg_snapshot { }; extern struct global_reg_snapshot global_reg_snapshot[NR_CPUS]; -#define __ARCH_WANT_COMPAT_SYS_PTRACE - #define force_successful_syscall_return() \ do { current_thread_info()->syscall_noerror = 1; \ } while (0) diff --git a/arch/sparc/include/asm/termbits.h b/arch/sparc/include/asm/termbits.h index d6ca3e2754f5..d72dfed1f9d7 100644 --- a/arch/sparc/include/asm/termbits.h +++ b/arch/sparc/include/asm/termbits.h @@ -29,10 +29,11 @@ struct termios { tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ +#ifndef __KERNEL__ cc_t c_cc[NCCS]; /* control characters */ -#ifdef __KERNEL__ +#else + cc_t c_cc[NCCS+2]; /* kernel needs 2 more to hold vmin/vtime */ #define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t)) - cc_t _x_cc[2]; /* We need them to hold vmin/vtime */ #endif }; @@ -42,8 +43,7 @@ struct termios2 { tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - cc_t _x_cc[2]; /* padding to match ktermios */ + cc_t c_cc[NCCS+2]; /* control characters */ speed_t c_ispeed; /* input speed */ speed_t c_ospeed; /* output speed */ }; @@ -54,8 +54,7 @@ struct ktermios { tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - cc_t _x_cc[2]; /* We need them to hold vmin/vtime */ + cc_t c_cc[NCCS+2]; /* control characters */ speed_t c_ispeed; /* input speed */ speed_t c_ospeed; /* output speed */ }; diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h index 296ef30e05c8..c64e767a3e4b 100644 --- a/arch/sparc/include/asm/uaccess_64.h +++ b/arch/sparc/include/asm/uaccess_64.h @@ -265,8 +265,8 @@ extern long __strnlen_user(const char __user *, long len); #define strlen_user __strlen_user #define strnlen_user __strnlen_user -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user +#define __copy_to_user_inatomic ___copy_to_user +#define __copy_from_user_inatomic ___copy_from_user #endif /* __ASSEMBLY__ */ diff --git a/arch/sparc/include/asm/unistd_32.h b/arch/sparc/include/asm/unistd_32.h index 648643a9f139..0d13d2a4c76f 100644 --- a/arch/sparc/include/asm/unistd_32.h +++ b/arch/sparc/include/asm/unistd_32.h @@ -338,8 +338,9 @@ #define __NR_dup3 320 #define __NR_pipe2 321 #define __NR_inotify_init1 322 +#define __NR_accept4 323 -#define NR_SYSCALLS 323 +#define NR_SYSCALLS 324 /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, * it never had the plain ones and there is no value to adding those diff --git a/arch/sparc/include/asm/unistd_64.h b/arch/sparc/include/asm/unistd_64.h index c5cc0e052321..fa5d3c0343c7 100644 --- a/arch/sparc/include/asm/unistd_64.h +++ b/arch/sparc/include/asm/unistd_64.h @@ -340,8 +340,9 @@ #define __NR_dup3 320 #define __NR_pipe2 321 #define __NR_inotify_init1 322 +#define __NR_accept4 323 -#define NR_SYSCALLS 323 +#define NR_SYSCALLS 324 #ifdef __KERNEL__ #define __ARCH_WANT_IPC_PARSE_VERSION diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index e7a0edfc1a32..1fc17f59c6bf 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c @@ -126,7 +126,7 @@ char *sparc_fpu_type; unsigned int fsr_storage; -void __init cpu_probe(void) +void __cpuinit cpu_probe(void) { int psr_impl, psr_vers, fpu_vers; int i, psr; diff --git a/arch/sparc/kernel/head.S b/arch/sparc/kernel/head.S index 2fe2c117e772..51b40426f9c6 100644 --- a/arch/sparc/kernel/head.S +++ b/arch/sparc/kernel/head.S @@ -72,7 +72,7 @@ sun4e_notsup: .align 4 /* The Sparc trap table, bootloader gives us control at _start. */ - .text + .section .text.head,"ax" .globl start, _stext, _start, __stext .globl trapbase _start: /* danger danger */ @@ -465,7 +465,6 @@ gokernel: mov %o7, %g4 ! Save %o7 /* Jump to it, and pray... */ - __INIT current_pc: call 1f nop diff --git a/arch/sparc/kernel/of_device.c b/arch/sparc/kernel/of_device.c index 0837bd52e28f..0a83bd737654 100644 --- a/arch/sparc/kernel/of_device.c +++ b/arch/sparc/kernel/of_device.c @@ -563,9 +563,9 @@ build_resources: op->dev.parent = parent; op->dev.bus = &of_platform_bus_type; if (!parent) - strcpy(op->dev.bus_id, "root"); + dev_set_name(&op->dev, "root"); else - sprintf(op->dev.bus_id, "%08x", dp->node); + dev_set_name(&op->dev, "%08x", dp->node); if (of_device_register(op)) { printk("%s: Could not register of device.\n", diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c index 1619ec15c099..e396c1f17a92 100644 --- a/arch/sparc/kernel/smp.c +++ b/arch/sparc/kernel/smp.c @@ -35,7 +35,7 @@ #include "irq.h" -volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,}; +volatile unsigned long cpu_callin_map[NR_CPUS] __cpuinitdata = {0,}; unsigned char boot_cpu_id = 0; unsigned char boot_cpu_id4 = 0; /* boot_cpu_id << 2 */ @@ -120,7 +120,7 @@ void cpu_panic(void) panic("SMP bolixed\n"); } -struct linux_prom_registers smp_penguin_ctable __initdata = { 0 }; +struct linux_prom_registers smp_penguin_ctable __cpuinitdata = { 0 }; void smp_send_reschedule(int cpu) { diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c index 7a6a5e795928..16ab0cb731c5 100644 --- a/arch/sparc/kernel/sun4d_smp.c +++ b/arch/sparc/kernel/sun4d_smp.c @@ -83,7 +83,7 @@ static inline void show_leds(int cpuid) "i" (ASI_M_CTL)); } -void __init smp4d_callin(void) +void __cpuinit smp4d_callin(void) { int cpuid = hard_smp4d_processor_id(); extern spinlock_t sun4d_imsk_lock; @@ -386,7 +386,7 @@ void smp4d_percpu_timer_interrupt(struct pt_regs *regs) extern unsigned int lvl14_resolution; -static void __init smp_setup_percpu_timer(void) +static void __cpuinit smp_setup_percpu_timer(void) { int cpu = hard_smp4d_processor_id(); diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c index 5fc386d08c47..4f8d60586b07 100644 --- a/arch/sparc/kernel/sun4m_smp.c +++ b/arch/sparc/kernel/sun4m_smp.c @@ -343,7 +343,7 @@ void smp4m_percpu_timer_interrupt(struct pt_regs *regs) extern unsigned int lvl14_resolution; -static void __init smp_setup_percpu_timer(void) +static void __cpuinit smp_setup_percpu_timer(void) { int cpu = smp_processor_id(); diff --git a/arch/sparc/kernel/systbls.S b/arch/sparc/kernel/systbls.S index e1b9233b90ab..7d0807586442 100644 --- a/arch/sparc/kernel/systbls.S +++ b/arch/sparc/kernel/systbls.S @@ -81,4 +81,4 @@ sys_call_table: /*305*/ .long sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait /*310*/ .long sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate /*315*/ .long sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1 -/*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1 +/*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4 diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c index 62c1d94cb434..00f7383c7657 100644 --- a/arch/sparc/kernel/time.c +++ b/arch/sparc/kernel/time.c @@ -119,35 +119,16 @@ static unsigned char mostek_read_byte(struct device *dev, u32 ofs) { struct platform_device *pdev = to_platform_device(dev); struct m48t59_plat_data *pdata = pdev->dev.platform_data; - void __iomem *regs = pdata->ioaddr; - unsigned char val = readb(regs + ofs); - - /* the year 0 is 1968 */ - if (ofs == pdata->offset + M48T59_YEAR) { - val += 0x68; - if ((val & 0xf) > 9) - val += 6; - } - return val; + + return readb(pdata->ioaddr + ofs); } static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) { struct platform_device *pdev = to_platform_device(dev); struct m48t59_plat_data *pdata = pdev->dev.platform_data; - void __iomem *regs = pdata->ioaddr; - - if (ofs == pdata->offset + M48T59_YEAR) { - if (val < 0x68) - val += 0x32; - else - val -= 0x68; - if ((val & 0xf) > 9) - val += 6; - if ((val & 0xf0) > 0x9A) - val += 0x60; - } - writeb(val, regs + ofs); + + writeb(val, pdata->ioaddr + ofs); } static struct m48t59_plat_data m48t59_data = { diff --git a/arch/sparc/kernel/trampoline.S b/arch/sparc/kernel/trampoline.S index 356c56aebc62..5e235c52d667 100644 --- a/arch/sparc/kernel/trampoline.S +++ b/arch/sparc/kernel/trampoline.S @@ -18,7 +18,7 @@ .globl sun4m_cpu_startup, __smp4m_processor_id .globl sun4d_cpu_startup, __smp4d_processor_id - __INIT + __CPUINIT .align 4 /* When we start up a cpu for the first time it enters this routine. @@ -109,7 +109,7 @@ __smp4d_processor_id: /* CPUID in bootbus can be found at PA 0xff0140000 */ #define SUN4D_BOOTBUS_CPUID 0xf0140000 - __INIT + __CPUINIT .align 4 sun4d_cpu_startup: diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S index b1002c607196..5b7e69a8c32f 100644 --- a/arch/sparc/kernel/vmlinux.lds.S +++ b/arch/sparc/kernel/vmlinux.lds.S @@ -13,6 +13,7 @@ SECTIONS .text 0xf0004000 : { _text = .; + *(.text.head) TEXT_TEXT SCHED_TEXT LOCK_TEXT diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index 6a5d7cabc044..dd8aa36f366c 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -1251,7 +1251,7 @@ static inline void map_kernel(void) /* Paging initialization on the Sparc Reference MMU. */ extern void sparc_context_init(int); -void (*poke_srmmu)(void) __initdata = NULL; +void (*poke_srmmu)(void) __cpuinitdata = NULL; extern unsigned long bootmem_init(unsigned long *pages_avail); @@ -1446,7 +1446,7 @@ static void __init init_vac_layout(void) (int)vac_cache_size, (int)vac_line_size); } -static void __init poke_hypersparc(void) +static void __cpuinit poke_hypersparc(void) { volatile unsigned long clear; unsigned long mreg = srmmu_get_mmureg(); @@ -1501,7 +1501,7 @@ static void __init init_hypersparc(void) hypersparc_setup_blockops(); } -static void __init poke_cypress(void) +static void __cpuinit poke_cypress(void) { unsigned long mreg = srmmu_get_mmureg(); unsigned long faddr, tagval; @@ -1589,7 +1589,7 @@ static void __init init_cypress_605(unsigned long mrev) init_cypress_common(); } -static void __init poke_swift(void) +static void __cpuinit poke_swift(void) { unsigned long mreg; @@ -1771,7 +1771,7 @@ static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long } -static void __init poke_turbosparc(void) +static void __cpuinit poke_turbosparc(void) { unsigned long mreg = srmmu_get_mmureg(); unsigned long ccreg; @@ -1834,7 +1834,7 @@ static void __init init_turbosparc(void) poke_srmmu = poke_turbosparc; } -static void __init poke_tsunami(void) +static void __cpuinit poke_tsunami(void) { unsigned long mreg = srmmu_get_mmureg(); @@ -1876,7 +1876,7 @@ static void __init init_tsunami(void) tsunami_setup_blockops(); } -static void __init poke_viking(void) +static void __cpuinit poke_viking(void) { unsigned long mreg = srmmu_get_mmureg(); static int smp_catch; diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig index 035b15af90d8..3b96e70b4670 100644 --- a/arch/sparc64/Kconfig +++ b/arch/sparc64/Kconfig @@ -11,8 +11,7 @@ config SPARC config SPARC64 bool default y - select HAVE_DYNAMIC_FTRACE - select HAVE_FTRACE + select HAVE_FUNCTION_TRACER select HAVE_IDE select HAVE_LMB select HAVE_ARCH_KGDB diff --git a/arch/sparc64/Kconfig.debug b/arch/sparc64/Kconfig.debug index d6d32d178fc8..c40515c06690 100644 --- a/arch/sparc64/Kconfig.debug +++ b/arch/sparc64/Kconfig.debug @@ -33,7 +33,7 @@ config DEBUG_PAGEALLOC config MCOUNT bool - depends on STACK_DEBUG || FTRACE + depends on STACK_DEBUG || FUNCTION_TRACER default y config FRAME_POINTER diff --git a/arch/sparc64/defconfig b/arch/sparc64/defconfig index 82cab5cc8070..05d19a3e590f 100644 --- a/arch/sparc64/defconfig +++ b/arch/sparc64/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26 -# Fri Jul 18 00:47:07 2008 +# Linux kernel version: 2.6.28-rc4 +# Mon Nov 10 12:35:09 2008 # CONFIG_SPARC=y CONFIG_SPARC64=y @@ -62,7 +62,6 @@ CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -79,7 +78,9 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -92,9 +93,9 @@ CONFIG_KPROBES=y CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_USE_GENERIC_SMP_HELPERS=y -CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -126,6 +127,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Processor type and features @@ -138,7 +140,7 @@ CONFIG_HZ_100=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=100 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SCHED_HRTICK=y CONFIG_HOTPLUG_CPU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_TICK_ONESHOT=y @@ -148,6 +150,7 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_SMP=y CONFIG_NR_CPUS=64 # CONFIG_CPU_FREQ is not set +CONFIG_US3_MC=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -169,7 +172,6 @@ CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y CONFIG_HAVE_MEMORY_PRESENT=y -# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y @@ -177,8 +179,10 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_NR_QUICK=1 +CONFIG_UNEVICTABLE_LRU=y CONFIG_SBUS=y CONFIG_SBUSCHAR=y CONFIG_SUN_AUXIO=y @@ -198,6 +202,8 @@ CONFIG_SUN_OPENPROMFS=m # CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y @@ -207,10 +213,6 @@ CONFIG_SCHED_MC=y CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # CONFIG_CMDLINE_BOOL is not set - -# -# Networking -# CONFIG_NET=y # @@ -224,6 +226,7 @@ CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y CONFIG_NET_KEY=m CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -299,7 +302,9 @@ CONFIG_IP_DCCP_TFRC_LIB=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set # CONFIG_IPX is not set @@ -320,11 +325,10 @@ CONFIG_NET_TCPPROBE=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set @@ -375,21 +379,21 @@ CONFIG_MISC_DEVICES=y # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set CONFIG_IDE_PROC_FS=y @@ -413,10 +417,8 @@ CONFIG_BLK_DEV_ALI15X3=y # CONFIG_BLK_DEV_AMD74XX is not set # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set @@ -540,7 +542,6 @@ CONFIG_DM_ZERO=m # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -548,7 +549,22 @@ CONFIG_NETDEVICES=y # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=m + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=m # CONFIG_SUNLANCE is not set @@ -565,6 +581,9 @@ CONFIG_SUNVNET=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -582,16 +601,15 @@ CONFIG_NET_PCI=y # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=m -CONFIG_E1000_NAPI=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_MYRI_SBUS is not set @@ -607,18 +625,23 @@ CONFIG_TIGON3=m CONFIG_BNX2=m # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set CONFIG_NIU=m +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set +# CONFIG_QLGE is not set # CONFIG_SFC is not set # CONFIG_TR is not set @@ -694,9 +717,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=y # CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -708,6 +733,7 @@ CONFIG_INPUT_SPARCSPKR=y # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # @@ -725,6 +751,7 @@ CONFIG_SERIO_RAW=m # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set @@ -735,6 +762,7 @@ CONFIG_HW_CONSOLE=y # # Serial drivers # +# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support @@ -762,6 +790,7 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y # @@ -827,10 +856,13 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -882,6 +914,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_ULTRA45 is not set # CONFIG_HWMON_DEBUG_CHIP is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set @@ -896,8 +929,14 @@ CONFIG_SSB_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -924,6 +963,7 @@ CONFIG_SSB_POSSIBLE=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -975,6 +1015,7 @@ CONFIG_FB_ATY_GX=y # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set @@ -983,7 +1024,10 @@ CONFIG_FB_ATY_GX=y # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1015,6 +1059,7 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_CLUT224 is not set CONFIG_LOGO_SUN_CLUT224=y CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1120,9 +1165,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1138,6 +1210,9 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -1155,6 +1230,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers @@ -1162,6 +1239,7 @@ CONFIG_USB_UHCI_HCD=m # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1191,7 +1269,6 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -1204,7 +1281,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1222,21 +1299,80 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +CONFIG_RTC_DRV_M48T59=y +CONFIG_RTC_DRV_BQ4802=y +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SUN4V=y +CONFIG_RTC_DRV_STARFIRE=y +# CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y # # Misc Linux/SPARC drivers # CONFIG_SUN_OPENPROMIO=y # CONFIG_OBP_FLASH is not set -# CONFIG_SUN_BPP is not set +# CONFIG_TADPOLE_TS102_UCTRL is not set # CONFIG_BBC_I2C is not set # CONFIG_ENVCTRL is not set # CONFIG_DISPLAY7SEG is not set @@ -1253,13 +1389,14 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set @@ -1290,6 +1427,7 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1311,6 +1449,7 @@ CONFIG_HUGETLB_PAGE=y # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -1388,6 +1527,8 @@ CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 # CONFIG_SCHED_DEBUG is not set CONFIG_SCHEDSTATS=y # CONFIG_TIMER_STATS is not set @@ -1408,20 +1549,30 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -1436,6 +1587,7 @@ CONFIG_HAVE_ARCH_KGDB=y CONFIG_KEYS=y # CONFIG_KEYS_DEBUG_PROC_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m @@ -1446,10 +1598,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m @@ -1523,6 +1677,11 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=y # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set @@ -1530,7 +1689,6 @@ CONFIG_CRYPTO_HW=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m # CONFIG_CRC_T10DIF is not set diff --git a/arch/sparc64/kernel/Makefile b/arch/sparc64/kernel/Makefile index c0b8009ab196..b3e0b986bef8 100644 --- a/arch/sparc64/kernel/Makefile +++ b/arch/sparc64/kernel/Makefile @@ -5,6 +5,8 @@ EXTRA_AFLAGS := -ansi EXTRA_CFLAGS := -Werror +CFLAGS_REMOVE_ftrace.o = -pg + extra-y := head.o init_task.o vmlinux.lds obj-y := process.o setup.o cpu.o idprom.o reboot.o \ diff --git a/arch/sparc64/kernel/ftrace.c b/arch/sparc64/kernel/ftrace.c index 4298d0aee713..d0218e73f982 100644 --- a/arch/sparc64/kernel/ftrace.c +++ b/arch/sparc64/kernel/ftrace.c @@ -9,12 +9,12 @@ static const u32 ftrace_nop = 0x01000000; -notrace unsigned char *ftrace_nop_replace(void) +unsigned char *ftrace_nop_replace(void) { return (char *)&ftrace_nop; } -notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) { static u32 call; s32 off; @@ -25,7 +25,7 @@ notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) return (unsigned char *) &call; } -notrace int +int ftrace_modify_code(unsigned long ip, unsigned char *old_code, unsigned char *new_code) { @@ -59,7 +59,7 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code, return faulted; } -notrace int ftrace_update_ftrace_func(ftrace_func_t func) +int ftrace_update_ftrace_func(ftrace_func_t func) { unsigned long ip = (unsigned long)(&ftrace_call); unsigned char old[MCOUNT_INSN_SIZE], *new; @@ -69,24 +69,6 @@ notrace int ftrace_update_ftrace_func(ftrace_func_t func) return ftrace_modify_code(ip, old, new); } -notrace int ftrace_mcount_set(unsigned long *data) -{ - unsigned long ip = (long)(&mcount_call); - unsigned long *addr = data; - unsigned char old[MCOUNT_INSN_SIZE], *new; - - /* - * Replace the mcount stub with a pointer to the - * ip recorder function. - */ - memcpy(old, &mcount_call, MCOUNT_INSN_SIZE); - new = ftrace_call_replace(ip, *addr); - *addr = ftrace_modify_code(ip, old, new); - - return 0; -} - - int __init ftrace_dyn_arch_init(void *data) { ftrace_mcount_set(data); diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c index 242ac1ccae7d..bdb7c0a6d83d 100644 --- a/arch/sparc64/kernel/pci.c +++ b/arch/sparc64/kernel/pci.c @@ -889,6 +889,7 @@ static int __pci_mmap_make_offset(struct pci_dev *pdev, for (i = 0; i <= PCI_ROM_RESOURCE; i++) { struct resource *rp = &pdev->resource[i]; + resource_size_t aligned_end; /* Active? */ if (!rp->flags) @@ -906,8 +907,15 @@ static int __pci_mmap_make_offset(struct pci_dev *pdev, continue; } + /* Align the resource end to the next page address. + * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), + * because actually we need the address of the next byte + * after rp->end. + */ + aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; + if ((rp->start <= user_paddr) && - (user_paddr + user_size) <= (rp->end + 1UL)) + (user_paddr + user_size) <= aligned_end) break; } diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c index f43adbc773ca..a941c610e7ce 100644 --- a/arch/sparc64/kernel/ptrace.c +++ b/arch/sparc64/kernel/ptrace.c @@ -1014,7 +1014,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) break; case PTRACE_SETFPREGS64: - ret = copy_regset_to_user(child, view, REGSET_FP, + ret = copy_regset_from_user(child, view, REGSET_FP, 0 * sizeof(u64), 33 * sizeof(u64), fps); diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c index e5627118e613..f500b0618bb0 100644 --- a/arch/sparc64/kernel/smp.c +++ b/arch/sparc64/kernel/smp.c @@ -282,7 +282,7 @@ static unsigned long kimage_addr_to_ra(void *p) return kern_base + (val - KERNBASE); } -static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg) +static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg) { extern unsigned long sparc64_ttable_tl0; extern unsigned long kern_locked_tte_data; @@ -343,7 +343,7 @@ extern unsigned long sparc64_cpu_startup; */ static struct thread_info *cpu_new_thread = NULL; -static int __devinit smp_boot_one_cpu(unsigned int cpu) +static int __cpuinit smp_boot_one_cpu(unsigned int cpu) { struct trap_per_cpu *tb = &trap_block[cpu]; unsigned long entry = diff --git a/arch/sparc64/kernel/sys32.S b/arch/sparc64/kernel/sys32.S index ade18ba0c686..f061c4dda9ef 100644 --- a/arch/sparc64/kernel/sys32.S +++ b/arch/sparc64/kernel/sys32.S @@ -150,7 +150,7 @@ sys32_mmap2: sys32_socketcall: /* %o0=call, %o1=args */ cmp %o0, 1 bl,pn %xcc, do_einval - cmp %o0, 17 + cmp %o0, 18 bg,pn %xcc, do_einval sub %o0, 1, %o0 sllx %o0, 5, %o0 @@ -319,6 +319,15 @@ do_sys_recvmsg: /* compat_sys_recvmsg(int, struct compat_msghdr *, unsigned int) nop nop nop +do_sys_accept4: /* sys_accept4(int, struct sockaddr *, int *, int) */ +63: ldswa [%o1 + 0x0] %asi, %o0 + sethi %hi(sys_accept4), %g1 +64: lduwa [%o1 + 0x8] %asi, %o2 +65: ldswa [%o1 + 0xc] %asi, %o3 + jmpl %g1 + %lo(sys_accept4), %g0 +66: lduwa [%o1 + 0x4] %asi, %o1 + nop + nop .section __ex_table,"a" .align 4 @@ -353,4 +362,6 @@ do_sys_recvmsg: /* compat_sys_recvmsg(int, struct compat_msghdr *, unsigned int) .word 57b, __retl_efault, 58b, __retl_efault .word 59b, __retl_efault, 60b, __retl_efault .word 61b, __retl_efault, 62b, __retl_efault + .word 63b, __retl_efault, 64b, __retl_efault + .word 65b, __retl_efault, 66b, __retl_efault .previous diff --git a/arch/sparc64/kernel/systbls.S b/arch/sparc64/kernel/systbls.S index b2fa4c163638..9fc78cf354bd 100644 --- a/arch/sparc64/kernel/systbls.S +++ b/arch/sparc64/kernel/systbls.S @@ -82,7 +82,7 @@ sys_call_table32: .word compat_sys_set_mempolicy, compat_sys_kexec_load, compat_sys_move_pages, sys_getcpu, compat_sys_epoll_pwait /*310*/ .word compat_sys_utimensat, compat_sys_signalfd, sys_timerfd_create, sys_eventfd, compat_sys_fallocate .word compat_sys_timerfd_settime, compat_sys_timerfd_gettime, compat_sys_signalfd4, sys_eventfd2, sys_epoll_create1 -/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1 +/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4 #endif /* CONFIG_COMPAT */ @@ -156,4 +156,4 @@ sys_call_table: .word sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait /*310*/ .word sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate .word sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1 -/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1 +/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4 diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c index 80d71a5ce1e3..141da3759091 100644 --- a/arch/sparc64/kernel/time.c +++ b/arch/sparc64/kernel/time.c @@ -490,6 +490,7 @@ static struct of_device_id __initdata bq4802_match[] = { .name = "rtc", .compatible = "bq4802", }, + {}, }; static struct of_platform_driver bq4802_driver = { @@ -503,39 +504,16 @@ static struct of_platform_driver bq4802_driver = { static unsigned char mostek_read_byte(struct device *dev, u32 ofs) { struct platform_device *pdev = to_platform_device(dev); - struct m48t59_plat_data *pdata = pdev->dev.platform_data; - void __iomem *regs; - unsigned char val; - - regs = (void __iomem *) pdev->resource[0].start; - val = readb(regs + ofs); - - /* the year 0 is 1968 */ - if (ofs == pdata->offset + M48T59_YEAR) { - val += 0x68; - if ((val & 0xf) > 9) - val += 6; - } - return val; + void __iomem *regs = (void __iomem *) pdev->resource[0].start; + + return readb(regs + ofs); } static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) { struct platform_device *pdev = to_platform_device(dev); - struct m48t59_plat_data *pdata = pdev->dev.platform_data; - void __iomem *regs; - - regs = (void __iomem *) pdev->resource[0].start; - if (ofs == pdata->offset + M48T59_YEAR) { - if (val < 0x68) - val += 0x32; - else - val -= 0x68; - if ((val & 0xf) > 9) - val += 6; - if ((val & 0xf0) > 0x9A) - val += 0x60; - } + void __iomem *regs = (void __iomem *) pdev->resource[0].start; + writeb(val, regs + ofs); } diff --git a/arch/sparc64/kernel/visemul.c b/arch/sparc64/kernel/visemul.c index 9e05cb5cb855..b956fd71c131 100644 --- a/arch/sparc64/kernel/visemul.c +++ b/arch/sparc64/kernel/visemul.c @@ -131,7 +131,7 @@ #define VIS_OPF_SHIFT 5 #define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT) -#define RS1(INSN) (((INSN) >> 24) & 0x1f) +#define RS1(INSN) (((INSN) >> 14) & 0x1f) #define RS2(INSN) (((INSN) >> 0) & 0x1f) #define RD(INSN) (((INSN) >> 25) & 0x1f) @@ -445,7 +445,7 @@ static void pdist(struct pt_regs *regs, unsigned int insn) unsigned long i; rs1 = fpd_regval(f, RS1(insn)); - rs2 = fpd_regval(f, RS1(insn)); + rs2 = fpd_regval(f, RS2(insn)); rd = fpd_regaddr(f, RD(insn)); rd_val = *rd; @@ -807,6 +807,8 @@ int vis_emul(struct pt_regs *regs, unsigned int insn) if (get_user(insn, (u32 __user *) pc)) return -EFAULT; + save_and_clear_fpu(); + opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT; switch (opf) { default: diff --git a/arch/sparc64/lib/PeeCeeI.c b/arch/sparc64/lib/PeeCeeI.c index 8b313f11bc8d..46053e6ddd7b 100644 --- a/arch/sparc64/lib/PeeCeeI.c +++ b/arch/sparc64/lib/PeeCeeI.c @@ -20,107 +20,62 @@ void outsw(unsigned long __addr, const void *src, unsigned long count) { void __iomem *addr = (void __iomem *) __addr; - if (count) { - u16 *ps = (u16 *)src; - u32 *pi; - - if (((u64)src) & 0x2) { - u16 val = le16_to_cpup(ps); - outw(val, addr); - ps++; - count--; - } - pi = (u32 *)ps; - while (count >= 2) { - u32 w = le32_to_cpup(pi); - - pi++; - outw(w >> 0, addr); - outw(w >> 16, addr); - count -= 2; - } - ps = (u16 *)pi; - if (count) { - u16 val = le16_to_cpup(ps); - outw(val, addr); - } + while (count--) { + __raw_writew(*(u16 *)src, addr); + src += sizeof(u16); } } void outsl(unsigned long __addr, const void *src, unsigned long count) { void __iomem *addr = (void __iomem *) __addr; + u32 l, l2; - if (count) { - if ((((u64)src) & 0x3) == 0) { - u32 *p = (u32 *)src; - while (count--) { - u32 val = cpu_to_le32p(p); - outl(val, addr); - p++; - } - } else { - u8 *pb; - u16 *ps = (u16 *)src; - u32 l = 0, l2; - u32 *pi; - - switch (((u64)src) & 0x3) { - case 0x2: - count -= 1; - l = cpu_to_le16p(ps) << 16; - ps++; - pi = (u32 *)ps; - while (count--) { - l2 = cpu_to_le32p(pi); - pi++; - outl(((l >> 16) | (l2 << 16)), addr); - l = l2; - } - ps = (u16 *)pi; - l2 = cpu_to_le16p(ps); - outl(((l >> 16) | (l2 << 16)), addr); - break; - - case 0x1: - count -= 1; - pb = (u8 *)src; - l = (*pb++ << 8); - ps = (u16 *)pb; - l2 = cpu_to_le16p(ps); - ps++; - l |= (l2 << 16); - pi = (u32 *)ps; - while (count--) { - l2 = cpu_to_le32p(pi); - pi++; - outl(((l >> 8) | (l2 << 24)), addr); - l = l2; - } - pb = (u8 *)pi; - outl(((l >> 8) | (*pb << 24)), addr); - break; + if (!count) + return; - case 0x3: - count -= 1; - pb = (u8 *)src; - l = (*pb++ << 24); - pi = (u32 *)pb; - while (count--) { - l2 = cpu_to_le32p(pi); - pi++; - outl(((l >> 24) | (l2 << 8)), addr); - l = l2; - } - ps = (u16 *)pi; - l2 = cpu_to_le16p(ps); - ps++; - pb = (u8 *)ps; - l2 |= (*pb << 16); - outl(((l >> 24) | (l2 << 8)), addr); - break; - } + switch (((unsigned long)src) & 0x3) { + case 0x0: + /* src is naturally aligned */ + while (count--) { + __raw_writel(*(u32 *)src, addr); + src += sizeof(u32); + } + break; + case 0x2: + /* 2-byte alignment */ + while (count--) { + l = (*(u16 *)src) << 16; + l |= *(u16 *)(src + sizeof(u16)); + __raw_writel(l, addr); + src += sizeof(u32); + } + break; + case 0x1: + /* Hold three bytes in l each time, grab a byte from l2 */ + l = (*(u8 *)src) << 24; + l |= (*(u16 *)(src + sizeof(u8))) << 8; + src += sizeof(u8) + sizeof(u16); + while (count--) { + l2 = *(u32 *)src; + l |= (l2 >> 24); + __raw_writel(l, addr); + l = l2 << 8; + src += sizeof(u32); + } + break; + case 0x3: + /* Hold a byte in l each time, grab 3 bytes from l2 */ + l = (*(u8 *)src) << 24; + src += sizeof(u8); + while (count--) { + l2 = *(u32 *)src; + l |= (l2 >> 8); + __raw_writel(l, addr); + l = l2 << 24; + src += sizeof(u32); } + break; } } diff --git a/arch/sparc64/lib/mcount.S b/arch/sparc64/lib/mcount.S index fad90ddb3a28..7ce9c65f3592 100644 --- a/arch/sparc64/lib/mcount.S +++ b/arch/sparc64/lib/mcount.S @@ -93,7 +93,7 @@ mcount: nop 1: #endif -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE mov %o7, %o0 .globl mcount_call @@ -119,7 +119,7 @@ mcount_call: .size _mcount,.-_mcount .size mcount,.-mcount -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER .globl ftrace_stub .type ftrace_stub,#function ftrace_stub: diff --git a/arch/sparc64/lib/user_fixup.c b/arch/sparc64/lib/user_fixup.c index 19d1fdb17d0e..05a361b0a1a4 100644 --- a/arch/sparc64/lib/user_fixup.c +++ b/arch/sparc64/lib/user_fixup.c @@ -24,7 +24,7 @@ static unsigned long compute_size(unsigned long start, unsigned long size, unsig if (fault_addr < start || fault_addr >= end) { *offset = 0; } else { - *offset = start - fault_addr; + *offset = fault_addr - start; size = end - fault_addr; } return size; diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c index 3c10daf8fc01..185f34679110 100644 --- a/arch/sparc64/mm/init.c +++ b/arch/sparc64/mm/init.c @@ -956,7 +956,7 @@ int of_node_to_nid(struct device_node *dp) return nid; } -static void add_node_ranges(void) +static void __init add_node_ranges(void) { int i; diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c index 19d579d74d27..8f44ebb0dec8 100644 --- a/arch/um/drivers/mconsole_kern.c +++ b/arch/um/drivers/mconsole_kern.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include #include @@ -785,7 +787,7 @@ static int __init mconsole_init(void) /* long to avoid size mismatch warnings from gcc */ long sock; int err; - char file[256]; + char file[UNIX_PATH_MAX]; if (umid_file_name("mconsole", file, sizeof(file))) return -1; diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f4ed47db79ee..1cbec0269d39 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -19,6 +19,8 @@ config X86_64 config X86 def_bool y select HAVE_AOUT if X86_32 + select HAVE_READQ + select HAVE_WRITEQ select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILE @@ -28,7 +30,7 @@ config X86 select HAVE_KRETPROBES select HAVE_FTRACE_MCOUNT_RECORD select HAVE_DYNAMIC_FTRACE - select HAVE_FTRACE + select HAVE_FUNCTION_TRACER select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64) select HAVE_ARCH_KGDB if !X86_VOYAGER select HAVE_ARCH_TRACEHOOK @@ -87,6 +89,10 @@ config GENERIC_IOMAP config GENERIC_BUG def_bool y depends on BUG + select GENERIC_BUG_RELATIVE_POINTERS if X86_64 + +config GENERIC_BUG_RELATIVE_POINTERS + bool config GENERIC_HWEIGHT def_bool y @@ -167,9 +173,12 @@ config GENERIC_PENDING_IRQ config X86_SMP bool depends on SMP && ((X86_32 && !X86_VOYAGER) || X86_64) - select USE_GENERIC_SMP_HELPERS default y +config USE_GENERIC_SMP_HELPERS + def_bool y + depends on SMP + config X86_32_SMP def_bool y depends on X86_32 && SMP @@ -231,25 +240,21 @@ config SMP If you don't know what to do here, say N. +config X86_HAS_BOOT_CPU_ID + def_bool y + depends on X86_VOYAGER + config X86_FIND_SMP_CONFIG def_bool y depends on X86_MPPARSE || X86_VOYAGER -if ACPI config X86_MPPARSE - def_bool y - bool "Enable MPS table" + bool "Enable MPS table" if ACPI + default y depends on X86_LOCAL_APIC help For old smp systems that do not have proper acpi support. Newer systems (esp with 64bit cpus) with acpi support, MADT and DSDT will override it -endif - -if !ACPI -config X86_MPPARSE - def_bool y - depends on X86_LOCAL_APIC -endif choice prompt "Subarchitecture Type" @@ -458,10 +463,6 @@ config X86_CYCLONE_TIMER def_bool y depends on X86_GENERICARCH -config ES7000_CLUSTERED_APIC - def_bool y - depends on SMP && X86_ES7000 && MPENTIUMIII - source "arch/x86/Kconfig.cpu" config HPET_TIMER @@ -973,24 +974,37 @@ config X86_PAE config ARCH_PHYS_ADDR_T_64BIT def_bool X86_64 || X86_PAE +config DIRECT_GBPAGES + bool "Enable 1GB pages for kernel pagetables" if EMBEDDED + default y + depends on X86_64 + help + Allow the kernel linear mapping to use 1GB pages on CPUs that + support it. This can improve the kernel's performance a tiny bit by + reducing TLB pressure. If in doubt, say "Y". + # Common NUMA Features config NUMA - bool "Numa Memory Allocation and Scheduler Support (EXPERIMENTAL)" + bool "Numa Memory Allocation and Scheduler Support" depends on SMP depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || X86_BIGSMP || X86_SUMMIT && ACPI) && EXPERIMENTAL) default n if X86_PC default y if (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP) help Enable NUMA (Non Uniform Memory Access) support. + The kernel will try to allocate memory used by a CPU on the local memory controller of the CPU and add some more NUMA awareness to the kernel. - For 32-bit this is currently highly experimental and should be only - used for kernel development. It might also cause boot failures. - For 64-bit this is recommended on all multiprocessor Opteron systems. - If the system is EM64T, you should say N unless your system is - EM64T NUMA. + For 64-bit this is recommended if the system is Intel Core i7 + (or later), AMD Opteron, or EM64T NUMA. + + For 32-bit this is only needed on (rare) 32-bit-only platforms + that support NUMA topologies, such as NUMAQ / Summit, or if you + boot a 32-bit kernel on a 64-bit NUMA platform. + + Otherwise, you should say N. comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI" depends on X86_32 && X86_SUMMIT && (!HIGHMEM64G || !ACPI) @@ -1510,11 +1524,15 @@ config ARCH_ENABLE_MEMORY_HOTPLUG def_bool y depends on X86_64 || (X86_32 && HIGHMEM) +config ARCH_ENABLE_MEMORY_HOTREMOVE + def_bool y + depends on MEMORY_HOTPLUG + config HAVE_ARCH_EARLY_PFN_TO_NID def_bool X86_64 depends on NUMA -menu "Power management options" +menu "Power management and ACPI options" depends on !X86_VOYAGER config ARCH_HIBERNATION_HEADER @@ -1649,13 +1667,6 @@ config APM_ALLOW_INTS many of the newer IBM Thinkpads. If you experience hangs when you suspend, try setting this to Y. Otherwise, say N. -config APM_REAL_MODE_POWER_OFF - bool "Use real mode APM BIOS call to power off" - help - Use real mode APM BIOS calls to switch off the computer. This is - a work-around for a number of buggy BIOSes. Switch this option on if - your computer crashes instead of powering off properly. - endif # APM source "arch/x86/kernel/cpu/cpufreq/Kconfig" @@ -1914,6 +1925,10 @@ config SYSVIPC_COMPAT endmenu +config HAVE_ATOMIC_IOMAP + def_bool y + depends on X86_32 + source "net/Kconfig" source "drivers/Kconfig" diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 0b7c4a3f0651..b815664fe370 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -513,19 +513,19 @@ config CPU_SUP_UMC_32 If unsure, say N. config X86_DS - bool "Debug Store support" - default y - help - Add support for Debug Store. - This allows the kernel to provide a memory buffer to the hardware - to store various profiling and tracing events. + def_bool X86_PTRACE_BTS + depends on X86_DEBUGCTLMSR config X86_PTRACE_BTS - bool "ptrace interface to Branch Trace Store" + bool "Branch Trace Store" default y - depends on (X86_DS && X86_DEBUGCTLMSR) + depends on X86_DEBUGCTLMSR help - Add a ptrace interface to allow collecting an execution trace - of the traced task. - This collects control flow changes in a (cyclic) buffer and allows - debuggers to fill in the gaps and show an execution trace of the debuggee. + This adds a ptrace interface to the hardware's branch trace store. + + Debuggers may use it to collect an execution trace of the debugged + application in order to answer the question 'how did I get here?'. + Debuggers may trace user mode as well as kernel mode. + + Say Y unless there is no application development on this machine + and you want to save a small amount of code size. diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 2a3dfbd5e677..4ee768660f75 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -114,18 +114,6 @@ config DEBUG_RODATA data. This is recommended so that we can catch kernel bugs sooner. If in doubt, say "Y". -config DIRECT_GBPAGES - bool "Enable gbpages-mapped kernel pagetables" - depends on DEBUG_KERNEL && EXPERIMENTAL && X86_64 - help - Enable gigabyte pages support (if the CPU supports it). This can - improve the kernel's performance a tiny bit by reducing TLB - pressure. - - This is experimental code. - - If in doubt, say "N". - config DEBUG_RODATA_TEST bool "Testcase for the DEBUG_RODATA feature" depends on DEBUG_RODATA @@ -307,10 +295,10 @@ config OPTIMIZE_INLINING developers have marked 'inline'. Doing so takes away freedom from gcc to do what it thinks is best, which is desirable for the gcc 3.x series of compilers. The gcc 4.x series have a rewritten inlining algorithm and - disabling this option will generate a smaller kernel there. Hopefully - this algorithm is so good that allowing gcc4 to make the decision can - become the default in the future, until then this option is there to - test gcc for this. + enabling this option will generate a smaller kernel there. Hopefully + this algorithm is so good that allowing gcc 4.x and above to make the + decision will become the default in the future. Until then this option + is there to test gcc for this. If unsure, say N. diff --git a/arch/x86/boot/compressed/.gitignore b/arch/x86/boot/compressed/.gitignore index be0ed065249b..63eff3b04d01 100644 --- a/arch/x86/boot/compressed/.gitignore +++ b/arch/x86/boot/compressed/.gitignore @@ -1 +1,3 @@ relocs +vmlinux.bin.all +vmlinux.relocs diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c index 0be77b39328a..7e8e8b25f5f6 100644 --- a/arch/x86/boot/tty.c +++ b/arch/x86/boot/tty.c @@ -74,7 +74,7 @@ static int kbd_pending(void) { u8 pending; asm volatile("int $0x16; setnz %0" - : "=rm" (pending) + : "=qm" (pending) : "a" (0x0100)); return pending; } diff --git a/arch/x86/boot/video-vga.c b/arch/x86/boot/video-vga.c index b939cb476dec..5d4742ed4aa2 100644 --- a/arch/x86/boot/video-vga.c +++ b/arch/x86/boot/video-vga.c @@ -34,7 +34,7 @@ static struct mode_info cga_modes[] = { { VIDEO_80x25, 80, 25, 0 }, }; -__videocard video_vga; +static __videocard video_vga; /* Set basic 80x25 mode */ static u8 vga_set_basic_mode(void) @@ -259,7 +259,7 @@ static int vga_probe(void) return mode_count[adapter]; } -__videocard video_vga = { +static __videocard video_vga = { .card_name = "VGA", .probe = vga_probe, .set_mode = vga_set_mode, diff --git a/arch/x86/boot/video.c b/arch/x86/boot/video.c index 83598b23093a..3bef2c1febe9 100644 --- a/arch/x86/boot/video.c +++ b/arch/x86/boot/video.c @@ -226,7 +226,7 @@ static unsigned int mode_menu(void) #ifdef CONFIG_VIDEO_RETAIN /* Save screen content to the heap */ -struct saved_screen { +static struct saved_screen { int x, y; int curx, cury; u16 *data; diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig index 13b8c86ae985..b30a08ed8eb4 100644 --- a/arch/x86/configs/i386_defconfig +++ b/arch/x86/configs/i386_defconfig @@ -77,7 +77,7 @@ CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_TREE=y # CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_NS=y @@ -298,7 +298,7 @@ CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y # CONFIG_KEXEC_JUMP is not set CONFIG_PHYSICAL_START=0x1000000 -CONFIG_RELOCATABLE=y +# CONFIG_RELOCATABLE is not set CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_HOTPLUG_CPU=y # CONFIG_COMPAT_VDSO is not set diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig index f0a03d7a7d63..0e7dbc0a3e46 100644 --- a/arch/x86/configs/x86_64_defconfig +++ b/arch/x86/configs/x86_64_defconfig @@ -77,7 +77,7 @@ CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_TREE=y # CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_NS=y @@ -298,7 +298,7 @@ CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y CONFIG_PHYSICAL_START=0x1000000 -CONFIG_RELOCATABLE=y +# CONFIG_RELOCATABLE is not set CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_HOTPLUG_CPU=y # CONFIG_COMPAT_VDSO is not set diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index 4bc02b23674b..b195f85526e3 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -32,6 +32,8 @@ #include #include +#include + #define DEBUG_SIG 0 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) @@ -41,7 +43,6 @@ X86_EFLAGS_ZF | X86_EFLAGS_AF | X86_EFLAGS_PF | \ X86_EFLAGS_CF) -asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset); void signal_fault(struct pt_regs *regs, void __user *frame, char *where); int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) @@ -173,47 +174,28 @@ asmlinkage long sys32_sigaltstack(const stack_ia32_t __user *uss_ptr, /* * Do a signal return; undo the signal stack. */ +#define COPY(x) { \ + err |= __get_user(regs->x, &sc->x); \ +} -struct sigframe -{ - u32 pretcode; - int sig; - struct sigcontext_ia32 sc; - struct _fpstate_ia32 fpstate_unused; /* look at kernel/sigframe.h */ - unsigned int extramask[_COMPAT_NSIG_WORDS-1]; - char retcode[8]; - /* fp state follows here */ -}; - -struct rt_sigframe -{ - u32 pretcode; - int sig; - u32 pinfo; - u32 puc; - compat_siginfo_t info; - struct ucontext_ia32 uc; - char retcode[8]; - /* fp state follows here */ -}; - -#define COPY(x) { \ - unsigned int reg; \ - err |= __get_user(reg, &sc->x); \ - regs->x = reg; \ +#define COPY_SEG_CPL3(seg) { \ + unsigned short tmp; \ + err |= __get_user(tmp, &sc->seg); \ + regs->seg = tmp | 3; \ } -#define RELOAD_SEG(seg,mask) \ - { unsigned int cur; \ - unsigned short pre; \ - err |= __get_user(pre, &sc->seg); \ - savesegment(seg, cur); \ - pre |= mask; \ - if (pre != cur) loadsegment(seg, pre); } +#define RELOAD_SEG(seg) { \ + unsigned int cur, pre; \ + err |= __get_user(pre, &sc->seg); \ + savesegment(seg, cur); \ + pre |= 3; \ + if (pre != cur) \ + loadsegment(seg, pre); \ +} static int ia32_restore_sigcontext(struct pt_regs *regs, struct sigcontext_ia32 __user *sc, - unsigned int *peax) + unsigned int *pax) { unsigned int tmpflags, gs, oldgs, err = 0; void __user *buf; @@ -240,18 +222,16 @@ static int ia32_restore_sigcontext(struct pt_regs *regs, if (gs != oldgs) load_gs_index(gs); - RELOAD_SEG(fs, 3); - RELOAD_SEG(ds, 3); - RELOAD_SEG(es, 3); + RELOAD_SEG(fs); + RELOAD_SEG(ds); + RELOAD_SEG(es); COPY(di); COPY(si); COPY(bp); COPY(sp); COPY(bx); COPY(dx); COPY(cx); COPY(ip); /* Don't touch extended registers */ - err |= __get_user(regs->cs, &sc->cs); - regs->cs |= 3; - err |= __get_user(regs->ss, &sc->ss); - regs->ss |= 3; + COPY_SEG_CPL3(cs); + COPY_SEG_CPL3(ss); err |= __get_user(tmpflags, &sc->flags); regs->flags = (regs->flags & ~FIX_EFLAGS) | (tmpflags & FIX_EFLAGS); @@ -262,15 +242,13 @@ static int ia32_restore_sigcontext(struct pt_regs *regs, buf = compat_ptr(tmp); err |= restore_i387_xstate_ia32(buf); - err |= __get_user(tmp, &sc->ax); - *peax = tmp; - + err |= __get_user(*pax, &sc->ax); return err; } asmlinkage long sys32_sigreturn(struct pt_regs *regs) { - struct sigframe __user *frame = (struct sigframe __user *)(regs->sp-8); + struct sigframe_ia32 __user *frame = (struct sigframe_ia32 __user *)(regs->sp-8); sigset_t set; unsigned int ax; @@ -300,12 +278,12 @@ badframe: asmlinkage long sys32_rt_sigreturn(struct pt_regs *regs) { - struct rt_sigframe __user *frame; + struct rt_sigframe_ia32 __user *frame; sigset_t set; unsigned int ax; struct pt_regs tregs; - frame = (struct rt_sigframe __user *)(regs->sp - 4); + frame = (struct rt_sigframe_ia32 __user *)(regs->sp - 4); if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -359,20 +337,15 @@ static int ia32_setup_sigcontext(struct sigcontext_ia32 __user *sc, err |= __put_user(regs->dx, &sc->dx); err |= __put_user(regs->cx, &sc->cx); err |= __put_user(regs->ax, &sc->ax); - err |= __put_user(regs->cs, &sc->cs); - err |= __put_user(regs->ss, &sc->ss); err |= __put_user(current->thread.trap_no, &sc->trapno); err |= __put_user(current->thread.error_code, &sc->err); err |= __put_user(regs->ip, &sc->ip); + err |= __put_user(regs->cs, (unsigned int __user *)&sc->cs); err |= __put_user(regs->flags, &sc->flags); err |= __put_user(regs->sp, &sc->sp_at_signal); + err |= __put_user(regs->ss, (unsigned int __user *)&sc->ss); - tmp = save_i387_xstate_ia32(fpstate); - if (tmp < 0) - err = -EFAULT; - else - err |= __put_user(ptr_to_compat(tmp ? fpstate : NULL), - &sc->fpstate); + err |= __put_user(ptr_to_compat(fpstate), &sc->fpstate); /* non-iBCS2 extensions.. */ err |= __put_user(mask, &sc->oldmask); @@ -400,7 +373,7 @@ static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, } /* This is the legacy signal stack switching. */ - else if ((regs->ss & 0xffff) != __USER_DS && + else if ((regs->ss & 0xffff) != __USER32_DS && !(ka->sa.sa_flags & SA_RESTORER) && ka->sa.sa_restorer) sp = (unsigned long) ka->sa.sa_restorer; @@ -408,6 +381,8 @@ static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, if (used_math()) { sp = sp - sig_xstate_ia32_size; *fpstate = (struct _fpstate_ia32 *) sp; + if (save_i387_xstate_ia32(*fpstate) < 0) + return (void __user *) -1L; } sp -= frame_size; @@ -420,7 +395,7 @@ static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int ia32_setup_frame(int sig, struct k_sigaction *ka, compat_sigset_t *set, struct pt_regs *regs) { - struct sigframe __user *frame; + struct sigframe_ia32 __user *frame; void __user *restorer; int err = 0; void __user *fpstate = NULL; @@ -430,12 +405,10 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka, u16 poplmovl; u32 val; u16 int80; - u16 pad; } __attribute__((packed)) code = { 0xb858, /* popl %eax ; movl $...,%eax */ __NR_ia32_sigreturn, 0x80cd, /* int $0x80 */ - 0, }; frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate); @@ -471,7 +444,7 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka, * These are actually not used anymore, but left because some * gdb versions depend on them as a marker. */ - err |= __copy_to_user(frame->retcode, &code, 8); + err |= __put_user(*((u64 *)&code), (u64 *)frame->retcode); if (err) return -EFAULT; @@ -501,7 +474,7 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka, int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, compat_sigset_t *set, struct pt_regs *regs) { - struct rt_sigframe __user *frame; + struct rt_sigframe_ia32 __user *frame; void __user *restorer; int err = 0; void __user *fpstate = NULL; @@ -511,8 +484,7 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, u8 movl; u32 val; u16 int80; - u16 pad; - u8 pad2; + u8 pad; } __attribute__((packed)) code = { 0xb8, __NR_ia32_rt_sigreturn, @@ -559,7 +531,7 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, * Not actually used anymore, but left because some gdb * versions need it. */ - err |= __copy_to_user(frame->retcode, &code, 8); + err |= __put_user(*((u64 *)&code), (u64 *)frame->retcode); if (err) return -EFAULT; @@ -572,11 +544,6 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, regs->dx = (unsigned long) &frame->info; regs->cx = (unsigned long) &frame->uc; - /* Make -mregparm=3 work */ - regs->ax = sig; - regs->dx = (unsigned long) &frame->info; - regs->cx = (unsigned long) &frame->uc; - loadsegment(ds, __USER32_DS); loadsegment(es, __USER32_DS); diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 8d676d8ecde9..9830681446ad 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -113,7 +113,6 @@ static inline void acpi_disable_pci(void) acpi_pci_disabled = 1; acpi_noirq_set(); } -extern int acpi_irq_balance_set(char *str); /* routines for saving/restoring kernel state */ extern int acpi_save_state_mem(void); diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h index 1a30c0440c6b..ac302a2fa339 100644 --- a/arch/x86/include/asm/amd_iommu_types.h +++ b/arch/x86/include/asm/amd_iommu_types.h @@ -251,13 +251,6 @@ struct amd_iommu { /* Pointer to PCI device of this IOMMU */ struct pci_dev *dev; - /* - * Capability pointer. There could be more than one IOMMU per PCI - * device function if there are more than one AMD IOMMU capability - * pointers. - */ - u16 cap_ptr; - /* physical address of MMIO space */ u64 mmio_phys; /* virtual address of MMIO space */ @@ -266,6 +259,13 @@ struct amd_iommu { /* capabilities of that IOMMU read from ACPI */ u32 cap; + /* + * Capability pointer. There could be more than one IOMMU per PCI + * device function if there are more than one AMD IOMMU capability + * pointers. + */ + u16 cap_ptr; + /* pci domain of this IOMMU */ u16 pci_seg; @@ -284,19 +284,19 @@ struct amd_iommu { /* size of command buffer */ u32 cmd_buf_size; - /* event buffer virtual address */ - u8 *evt_buf; /* size of event buffer */ u32 evt_buf_size; + /* event buffer virtual address */ + u8 *evt_buf; /* MSI number for event interrupt */ u16 evt_msi_num; - /* if one, we need to send a completion wait command */ - int need_sync; - /* true if interrupts for this IOMMU are already enabled */ bool int_enabled; + /* if one, we need to send a completion wait command */ + int need_sync; + /* default dma_ops domain for that IOMMU */ struct dma_ops_domain *default_dom; }; diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 3b1510b4fc57..25caa0738af5 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -193,6 +193,7 @@ extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); static inline void lapic_shutdown(void) { } #define local_apic_timer_c2_ok 1 static inline void init_apic_mappings(void) { } +static inline void disable_local_APIC(void) { } #endif /* !CONFIG_X86_LOCAL_APIC */ diff --git a/arch/x86/include/asm/bigsmp/apic.h b/arch/x86/include/asm/bigsmp/apic.h index 1d9543b9d358..ce547f24a1cd 100644 --- a/arch/x86/include/asm/bigsmp/apic.h +++ b/arch/x86/include/asm/bigsmp/apic.h @@ -24,8 +24,6 @@ static inline cpumask_t target_cpus(void) #define INT_DELIVERY_MODE (dest_Fixed) #define INT_DEST_MODE (0) /* phys delivery to target proc */ #define NO_BALANCE_IRQ (0) -#define WAKE_SECONDARY_VIA_INIT - static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) { diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 360010322711..9fa9dcdf344b 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -168,7 +168,15 @@ static inline void __change_bit(int nr, volatile unsigned long *addr) */ static inline void change_bit(int nr, volatile unsigned long *addr) { - asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr)); + if (IS_IMMEDIATE(nr)) { + asm volatile(LOCK_PREFIX "xorb %1,%0" + : CONST_MASK_ADDR(nr, addr) + : "iq" ((u8)CONST_MASK(nr))); + } else { + asm volatile(LOCK_PREFIX "btc %1,%0" + : BITOP_ADDR(addr) + : "Ir" (nr)); + } } /** diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h index 3def2065fcea..d9cf1cd156d2 100644 --- a/arch/x86/include/asm/bug.h +++ b/arch/x86/include/asm/bug.h @@ -9,7 +9,7 @@ #ifdef CONFIG_X86_32 # define __BUG_C0 "2:\t.long 1b, %c0\n" #else -# define __BUG_C0 "2:\t.quad 1b, %c0\n" +# define __BUG_C0 "2:\t.long 1b - 2b, %c0 - 2b\n" #endif #define BUG() \ diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h index e02ae2d89acf..f110ad417df3 100644 --- a/arch/x86/include/asm/byteorder.h +++ b/arch/x86/include/asm/byteorder.h @@ -4,26 +4,33 @@ #include #include -#ifdef __GNUC__ +#define __LITTLE_ENDIAN -#ifdef __i386__ - -static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) +static inline __attribute_const__ __u32 __arch_swab32(__u32 val) { -#ifdef CONFIG_X86_BSWAP - asm("bswap %0" : "=r" (x) : "0" (x)); -#else +#ifdef __i386__ +# ifdef CONFIG_X86_BSWAP + asm("bswap %0" : "=r" (val) : "0" (val)); +# else asm("xchgb %b0,%h0\n\t" /* swap lower bytes */ "rorl $16,%0\n\t" /* swap words */ "xchgb %b0,%h0" /* swap higher bytes */ - : "=q" (x) - : "0" (x)); + : "=q" (val) + : "0" (val)); +# endif + +#else /* __i386__ */ + asm("bswapl %0" + : "=r" (val) + : "0" (val)); #endif - return x; + return val; } +#define __arch_swab32 __arch_swab32 -static inline __attribute_const__ __u64 ___arch__swab64(__u64 val) +static inline __attribute_const__ __u64 __arch_swab64(__u64 val) { +#ifdef __i386__ union { struct { __u32 a; @@ -32,50 +39,27 @@ static inline __attribute_const__ __u64 ___arch__swab64(__u64 val) __u64 u; } v; v.u = val; -#ifdef CONFIG_X86_BSWAP +# ifdef CONFIG_X86_BSWAP asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1" : "=r" (v.s.a), "=r" (v.s.b) : "0" (v.s.a), "1" (v.s.b)); -#else - v.s.a = ___arch__swab32(v.s.a); - v.s.b = ___arch__swab32(v.s.b); +# else + v.s.a = __arch_swab32(v.s.a); + v.s.b = __arch_swab32(v.s.b); asm("xchgl %0,%1" : "=r" (v.s.a), "=r" (v.s.b) : "0" (v.s.a), "1" (v.s.b)); -#endif +# endif return v.u; -} - #else /* __i386__ */ - -static inline __attribute_const__ __u64 ___arch__swab64(__u64 x) -{ asm("bswapq %0" - : "=r" (x) - : "0" (x)); - return x; -} - -static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - asm("bswapl %0" - : "=r" (x) - : "0" (x)); - return x; -} - + : "=r" (val) + : "0" (val)); + return val; #endif +} +#define __arch_swab64 __arch_swab64 -/* Do not define swab16. Gcc is smart enough to recognize "C" version and - convert it into rotation or exhange. */ - -#define __arch__swab64(x) ___arch__swab64(x) -#define __arch__swab32(x) ___arch__swab32(x) - -#define __BYTEORDER_HAS_U64__ - -#endif /* __GNUC__ */ - -#include +#include #endif /* _ASM_X86_BYTEORDER_H */ diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index f73e95d75b45..ea408dcba513 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -80,7 +80,6 @@ #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ -#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ @@ -91,7 +90,9 @@ #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ -#define X86_FEATURE_XTOPOLOGY (3*32+21) /* cpu topology enum extensions */ +#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ +#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ +#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ @@ -117,6 +118,7 @@ #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ +#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ @@ -237,6 +239,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) +#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) # define cpu_has_invlpg 1 diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h index 4a5397bfce27..097794ff6b79 100644 --- a/arch/x86/include/asm/dma-mapping.h +++ b/arch/x86/include/asm/dma-mapping.h @@ -71,15 +71,13 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev) /* Make sure we keep the same behaviour */ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { -#ifdef CONFIG_X86_32 - return 0; -#else +#ifdef CONFIG_X86_64 struct dma_mapping_ops *ops = get_dma_ops(dev); if (ops->mapping_error) return ops->mapping_error(dev, dma_addr); - return (dma_addr == bad_dma_address); #endif + return (dma_addr == bad_dma_address); } #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) @@ -255,9 +253,11 @@ static inline unsigned long dma_alloc_coherent_mask(struct device *dev, static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp) { -#ifdef CONFIG_X86_64 unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp); + if (dma_mask <= DMA_24BIT_MASK) + gfp |= GFP_DMA; +#ifdef CONFIG_X86_64 if (dma_mask <= DMA_32BIT_MASK && !(gfp & GFP_DMA)) gfp |= GFP_DMA32; #endif diff --git a/arch/x86/include/asm/ds.h b/arch/x86/include/asm/ds.h index 72c5a190bf48..a95008457ea4 100644 --- a/arch/x86/include/asm/ds.h +++ b/arch/x86/include/asm/ds.h @@ -23,12 +23,13 @@ #ifndef _ASM_X86_DS_H #define _ASM_X86_DS_H -#ifdef CONFIG_X86_DS #include #include +#ifdef CONFIG_X86_DS + struct task_struct; /* @@ -232,7 +233,8 @@ extern void ds_free(struct ds_context *context); #else /* CONFIG_X86_DS */ -#define ds_init_intel(config) do {} while (0) +struct cpuinfo_x86; +static inline void __cpuinit ds_init_intel(struct cpuinfo_x86 *ignored) {} #endif /* CONFIG_X86_DS */ #endif /* _ASM_X86_DS_H */ diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h index 94826cf87455..cc70c1c78ca4 100644 --- a/arch/x86/include/asm/emergency-restart.h +++ b/arch/x86/include/asm/emergency-restart.h @@ -8,7 +8,9 @@ enum reboot_type { BOOT_BIOS = 'b', #endif BOOT_ACPI = 'a', - BOOT_EFI = 'e' + BOOT_EFI = 'e', + BOOT_CF9 = 'p', + BOOT_CF9_COND = 'q', }; extern enum reboot_type reboot_type; diff --git a/arch/x86/include/asm/es7000/apic.h b/arch/x86/include/asm/es7000/apic.h index 380f0b4f17ed..e24ef876915f 100644 --- a/arch/x86/include/asm/es7000/apic.h +++ b/arch/x86/include/asm/es7000/apic.h @@ -9,31 +9,27 @@ static inline int apic_id_registered(void) return (1); } -static inline cpumask_t target_cpus(void) +static inline cpumask_t target_cpus_cluster(void) { -#if defined CONFIG_ES7000_CLUSTERED_APIC return CPU_MASK_ALL; -#else +} + +static inline cpumask_t target_cpus(void) +{ return cpumask_of_cpu(smp_processor_id()); -#endif } -#if defined CONFIG_ES7000_CLUSTERED_APIC -#define APIC_DFR_VALUE (APIC_DFR_CLUSTER) -#define INT_DELIVERY_MODE (dest_LowestPrio) -#define INT_DEST_MODE (1) /* logical delivery broadcast to all procs */ -#define NO_BALANCE_IRQ (1) -#undef WAKE_SECONDARY_VIA_INIT -#define WAKE_SECONDARY_VIA_MIP -#else +#define APIC_DFR_VALUE_CLUSTER (APIC_DFR_CLUSTER) +#define INT_DELIVERY_MODE_CLUSTER (dest_LowestPrio) +#define INT_DEST_MODE_CLUSTER (1) /* logical delivery broadcast to all procs */ +#define NO_BALANCE_IRQ_CLUSTER (1) + #define APIC_DFR_VALUE (APIC_DFR_FLAT) #define INT_DELIVERY_MODE (dest_Fixed) #define INT_DEST_MODE (0) /* phys delivery to target procs */ #define NO_BALANCE_IRQ (0) #undef APIC_DEST_LOGICAL #define APIC_DEST_LOGICAL 0x0 -#define WAKE_SECONDARY_VIA_INIT -#endif static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) { @@ -60,6 +56,16 @@ static inline unsigned long calculate_ldr(int cpu) * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel * document number 292116). So here it goes... */ +static inline void init_apic_ldr_cluster(void) +{ + unsigned long val; + int cpu = smp_processor_id(); + + apic_write(APIC_DFR, APIC_DFR_VALUE_CLUSTER); + val = calculate_ldr(cpu); + apic_write(APIC_LDR, val); +} + static inline void init_apic_ldr(void) { unsigned long val; @@ -70,10 +76,6 @@ static inline void init_apic_ldr(void) apic_write(APIC_LDR, val); } -#ifndef CONFIG_X86_GENERICARCH -extern void enable_apic_mode(void); -#endif - extern int apic_version [MAX_APICS]; static inline void setup_apic_routing(void) { @@ -144,7 +146,7 @@ static inline int check_phys_apicid_present(int cpu_physical_apicid) return (1); } -static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) +static inline unsigned int cpu_mask_to_apicid_cluster(cpumask_t cpumask) { int num_bits_set; int cpus_found = 0; @@ -154,11 +156,7 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) num_bits_set = cpus_weight(cpumask); /* Return id to all */ if (num_bits_set == NR_CPUS) -#if defined CONFIG_ES7000_CLUSTERED_APIC return 0xFF; -#else - return cpu_to_logical_apicid(0); -#endif /* * The cpus in the mask must all be on the apic cluster. If are not * on the same apicid cluster return default value of TARGET_CPUS. @@ -171,11 +169,40 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) if (apicid_cluster(apicid) != apicid_cluster(new_apicid)){ printk ("%s: Not a valid mask!\n", __func__); -#if defined CONFIG_ES7000_CLUSTERED_APIC return 0xFF; -#else + } + apicid = new_apicid; + cpus_found++; + } + cpu++; + } + return apicid; +} + +static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) +{ + int num_bits_set; + int cpus_found = 0; + int cpu; + int apicid; + + num_bits_set = cpus_weight(cpumask); + /* Return id to all */ + if (num_bits_set == NR_CPUS) + return cpu_to_logical_apicid(0); + /* + * The cpus in the mask must all be on the apic cluster. If are not + * on the same apicid cluster return default value of TARGET_CPUS. + */ + cpu = first_cpu(cpumask); + apicid = cpu_to_logical_apicid(cpu); + while (cpus_found < num_bits_set) { + if (cpu_isset(cpu, cpumask)) { + int new_apicid = cpu_to_logical_apicid(cpu); + if (apicid_cluster(apicid) != + apicid_cluster(new_apicid)){ + printk ("%s: Not a valid mask!\n", __func__); return cpu_to_logical_apicid(0); -#endif } apicid = new_apicid; cpus_found++; diff --git a/arch/x86/include/asm/es7000/wakecpu.h b/arch/x86/include/asm/es7000/wakecpu.h index 3ffc5a7bf667..78f0daaee436 100644 --- a/arch/x86/include/asm/es7000/wakecpu.h +++ b/arch/x86/include/asm/es7000/wakecpu.h @@ -1,36 +1,12 @@ #ifndef __ASM_ES7000_WAKECPU_H #define __ASM_ES7000_WAKECPU_H -/* - * This file copes with machines that wakeup secondary CPUs by the - * INIT, INIT, STARTUP sequence. - */ - -#ifdef CONFIG_ES7000_CLUSTERED_APIC -#define WAKE_SECONDARY_VIA_MIP -#else -#define WAKE_SECONDARY_VIA_INIT -#endif - -#ifdef WAKE_SECONDARY_VIA_MIP -extern int es7000_start_cpu(int cpu, unsigned long eip); -static inline int -wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) -{ - int boot_error = 0; - boot_error = es7000_start_cpu(phys_apicid, start_eip); - return boot_error; -} -#endif - -#define TRAMPOLINE_LOW phys_to_virt(0x467) -#define TRAMPOLINE_HIGH phys_to_virt(0x469) - -#define boot_cpu_apicid boot_cpu_physical_apicid +#define TRAMPOLINE_PHYS_LOW 0x467 +#define TRAMPOLINE_PHYS_HIGH 0x469 static inline void wait_for_init_deassert(atomic_t *deassert) { -#ifdef WAKE_SECONDARY_VIA_INIT +#ifndef CONFIG_ES7000_CLUSTERED_APIC while (!atomic_read(deassert)) cpu_relax(); #endif @@ -50,10 +26,12 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) { } -#if APIC_DEBUG - #define inquire_remote_apic(apicid) __inquire_remote_apic(apicid) -#else - #define inquire_remote_apic(apicid) {} -#endif +extern void __inquire_remote_apic(int apicid); + +static inline void inquire_remote_apic(int apicid) +{ + if (apic_verbosity >= APIC_DEBUG) + __inquire_remote_apic(apicid); +} #endif /* __ASM_MACH_WAKECPU_H */ diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index 8668a94f850e..23696d44a0af 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -9,6 +9,10 @@ extern int fixmaps_set; +extern pte_t *kmap_pte; +extern pgprot_t kmap_prot; +extern pte_t *pkmap_page_table; + void __native_set_fixmap(enum fixed_addresses idx, pte_t pte); void native_set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t flags); diff --git a/arch/x86/include/asm/fixmap_32.h b/arch/x86/include/asm/fixmap_32.h index 09f29ab5c139..c7115c1d7217 100644 --- a/arch/x86/include/asm/fixmap_32.h +++ b/arch/x86/include/asm/fixmap_32.h @@ -28,10 +28,8 @@ extern unsigned long __FIXADDR_TOP; #include #include #include -#ifdef CONFIG_HIGHMEM #include #include -#endif /* * Here we define all the compile-time 'special' virtual @@ -75,10 +73,8 @@ enum fixed_addresses { #ifdef CONFIG_X86_CYCLONE_TIMER FIX_CYCLONE_TIMER, /*cyclone timer register*/ #endif -#ifdef CONFIG_HIGHMEM FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, -#endif #ifdef CONFIG_PCI_MMCONFIG FIX_PCIE_MCFG, #endif diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h index 47f7e65e6c1d..9e8bc29b8b17 100644 --- a/arch/x86/include/asm/ftrace.h +++ b/arch/x86/include/asm/ftrace.h @@ -1,7 +1,7 @@ #ifndef _ASM_X86_FTRACE_H #define _ASM_X86_FTRACE_H -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #define MCOUNT_ADDR ((long)(mcount)) #define MCOUNT_INSN_SIZE 5 /* sizeof mcount call */ @@ -19,6 +19,6 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr) } #endif -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ #endif /* _ASM_X86_FTRACE_H */ diff --git a/arch/x86/include/asm/genapic_32.h b/arch/x86/include/asm/genapic_32.h index 5cbd4fcc06fd..0ac17d33a8c7 100644 --- a/arch/x86/include/asm/genapic_32.h +++ b/arch/x86/include/asm/genapic_32.h @@ -2,6 +2,7 @@ #define _ASM_X86_GENAPIC_32_H #include +#include /* * Generic APIC driver interface. @@ -65,6 +66,14 @@ struct genapic { void (*send_IPI_allbutself)(int vector); void (*send_IPI_all)(int vector); #endif + int (*wakeup_cpu)(int apicid, unsigned long start_eip); + int trampoline_phys_low; + int trampoline_phys_high; + void (*wait_for_init_deassert)(atomic_t *deassert); + void (*smp_callin_clear_local_apic)(void); + void (*store_NMI_vector)(unsigned short *high, unsigned short *low); + void (*restore_NMI_vector)(unsigned short *high, unsigned short *low); + void (*inquire_remote_apic)(int apicid); }; #define APICFUNC(x) .x = x, @@ -105,16 +114,24 @@ struct genapic { APICFUNC(get_apic_id) \ .apic_id_mask = APIC_ID_MASK, \ APICFUNC(cpu_mask_to_apicid) \ - APICFUNC(vector_allocation_domain) \ + APICFUNC(vector_allocation_domain) \ APICFUNC(acpi_madt_oem_check) \ IPIFUNC(send_IPI_mask) \ IPIFUNC(send_IPI_allbutself) \ IPIFUNC(send_IPI_all) \ APICFUNC(enable_apic_mode) \ APICFUNC(phys_pkg_id) \ + .trampoline_phys_low = TRAMPOLINE_PHYS_LOW, \ + .trampoline_phys_high = TRAMPOLINE_PHYS_HIGH, \ + APICFUNC(wait_for_init_deassert) \ + APICFUNC(smp_callin_clear_local_apic) \ + APICFUNC(store_NMI_vector) \ + APICFUNC(restore_NMI_vector) \ + APICFUNC(inquire_remote_apic) \ } extern struct genapic *genapic; +extern void es7000_update_genapic_to_cluster(void); enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC}; #define get_uv_system_type() UV_NONE diff --git a/arch/x86/include/asm/genapic_64.h b/arch/x86/include/asm/genapic_64.h index 13c4e96199ea..2cae011668b7 100644 --- a/arch/x86/include/asm/genapic_64.h +++ b/arch/x86/include/asm/genapic_64.h @@ -32,6 +32,8 @@ struct genapic { unsigned int (*get_apic_id)(unsigned long x); unsigned long (*set_apic_id)(unsigned int id); unsigned long apic_id_mask; + /* wakeup_secondary_cpu */ + int (*wakeup_cpu)(int apicid, unsigned long start_eip); }; extern struct genapic *genapic; diff --git a/arch/x86/include/asm/highmem.h b/arch/x86/include/asm/highmem.h index a3b3b7c3027b..bf9276bea660 100644 --- a/arch/x86/include/asm/highmem.h +++ b/arch/x86/include/asm/highmem.h @@ -25,14 +25,11 @@ #include #include #include +#include /* declarations for highmem.c */ extern unsigned long highstart_pfn, highend_pfn; -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; -extern pte_t *pkmap_page_table; - /* * Right now we initialize only a single pte table. It can be extended * easily, subsequent pte tables have to be allocated in one physical diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h new file mode 100644 index 000000000000..369f5c5d09a1 --- /dev/null +++ b/arch/x86/include/asm/hypervisor.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2008, VMware, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef ASM_X86__HYPERVISOR_H +#define ASM_X86__HYPERVISOR_H + +extern unsigned long get_hypervisor_tsc_freq(void); +extern void init_hypervisor(struct cpuinfo_x86 *c); + +#endif diff --git a/arch/x86/include/asm/ia32.h b/arch/x86/include/asm/ia32.h index 97989c0e534c..50ca486fd88c 100644 --- a/arch/x86/include/asm/ia32.h +++ b/arch/x86/include/asm/ia32.h @@ -129,24 +129,6 @@ typedef struct compat_siginfo { } _sifields; } compat_siginfo_t; -struct sigframe32 { - u32 pretcode; - int sig; - struct sigcontext_ia32 sc; - struct _fpstate_ia32 fpstate; - unsigned int extramask[_COMPAT_NSIG_WORDS-1]; -}; - -struct rt_sigframe32 { - u32 pretcode; - int sig; - u32 pinfo; - u32 puc; - compat_siginfo_t info; - struct ucontext_ia32 uc; - struct _fpstate_ia32 fpstate; -}; - struct ustat32 { __u32 f_tfree; compat_ino_t f_tinode; diff --git a/arch/x86/include/asm/idle.h b/arch/x86/include/asm/idle.h index 44c89c3a23e9..38d87379e270 100644 --- a/arch/x86/include/asm/idle.h +++ b/arch/x86/include/asm/idle.h @@ -8,8 +8,13 @@ struct notifier_block; void idle_notifier_register(struct notifier_block *n); void idle_notifier_unregister(struct notifier_block *n); +#ifdef CONFIG_X86_64 void enter_idle(void); void exit_idle(void); +#else /* !CONFIG_X86_64 */ +static inline void enter_idle(void) { } +static inline void exit_idle(void) { } +#endif /* CONFIG_X86_64 */ void c1e_remove_cpu(int cpu); diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 5618a103f395..33513b9a67f3 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -4,6 +4,7 @@ #define ARCH_HAS_IOREMAP_WC #include +#include #define build_mmio_read(name, size, type, reg, barrier) \ static inline type name(const volatile void __iomem *addr) \ @@ -45,20 +46,40 @@ build_mmio_write(__writel, "l", unsigned int, "r", ) #define mmiowb() barrier() #ifdef CONFIG_X86_64 + build_mmio_read(readq, "q", unsigned long, "=r", :"memory") -build_mmio_read(__readq, "q", unsigned long, "=r", ) build_mmio_write(writeq, "q", unsigned long, "r", :"memory") -build_mmio_write(__writeq, "q", unsigned long, "r", ) -#define readq_relaxed(a) __readq(a) -#define __raw_readq __readq -#define __raw_writeq writeq +#else + +static inline __u64 readq(const volatile void __iomem *addr) +{ + const volatile u32 __iomem *p = addr; + u32 low, high; + + low = readl(p); + high = readl(p + 1); + + return low + ((u64)high << 32); +} + +static inline void writeq(__u64 val, volatile void __iomem *addr) +{ + writel(val, addr); + writel(val >> 32, addr+4); +} -/* Let people know we have them */ -#define readq readq -#define writeq writeq #endif +#define readq_relaxed(a) readq(a) + +#define __raw_readq(a) readq(a) +#define __raw_writeq(val, addr) writeq(val, addr) + +/* Let people know that we have them */ +#define readq readq +#define writeq writeq + extern int iommu_bio_merge; #ifdef CONFIG_X86_32 @@ -82,9 +103,9 @@ extern void __iomem *ioremap_wc(unsigned long offset, unsigned long size); extern void early_ioremap_init(void); extern void early_ioremap_clear(void); extern void early_ioremap_reset(void); -extern void *early_ioremap(unsigned long offset, unsigned long size); -extern void *early_memremap(unsigned long offset, unsigned long size); -extern void early_iounmap(void *addr, unsigned long size); +extern void __iomem *early_ioremap(unsigned long offset, unsigned long size); +extern void __iomem *early_memremap(unsigned long offset, unsigned long size); +extern void early_iounmap(void __iomem *addr, unsigned long size); extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); diff --git a/arch/x86/include/asm/iomap.h b/arch/x86/include/asm/iomap.h new file mode 100644 index 000000000000..c1f06289b14b --- /dev/null +++ b/arch/x86/include/asm/iomap.h @@ -0,0 +1,30 @@ +/* + * Copyright © 2008 Ingo Molnar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include +#include +#include +#include +#include +#include + +void * +iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); + +void +iounmap_atomic(void *kvaddr, enum km_type type); diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index 98e28ea8cd16..0b500c5b6446 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -6,8 +6,6 @@ extern void no_iommu_init(void); extern struct dma_mapping_ops nommu_dma_ops; extern int force_iommu, no_iommu; extern int iommu_detected; -extern int dmar_disabled; -extern int forbid_dac; extern unsigned long iommu_nr_pages(unsigned long addr, unsigned long len); diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index bae0eda95486..28e409fc73f3 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -31,10 +31,6 @@ static inline int irq_canonicalize(int irq) # endif #endif -#ifdef CONFIG_IRQBALANCE -extern int irqbalance_disable(char *str); -#endif - #ifdef CONFIG_HOTPLUG_CPU #include extern void fixup_irqs(cpumask_t map); diff --git a/arch/x86/include/asm/irq_regs_32.h b/arch/x86/include/asm/irq_regs_32.h index af2f02d27fc7..86afd7473457 100644 --- a/arch/x86/include/asm/irq_regs_32.h +++ b/arch/x86/include/asm/irq_regs_32.h @@ -9,6 +9,8 @@ #include +#define ARCH_HAS_OWN_IRQ_REGS + DECLARE_PER_CPU(struct pt_regs *, irq_regs); static inline struct pt_regs *get_irq_regs(void) diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index d843ed0e9b2e..0005adb0f941 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -101,30 +101,22 @@ #define LAST_VM86_IRQ 15 #define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) -#ifdef CONFIG_X86_64 +#if defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_VOYAGER) # if NR_CPUS < MAX_IO_APICS # define NR_IRQS (NR_VECTORS + (32 * NR_CPUS)) # else # define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS)) # endif -#elif !defined(CONFIG_X86_VOYAGER) +#elif defined(CONFIG_X86_VOYAGER) -# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS) - -# define NR_IRQS 224 - -# else /* IO_APIC || PARAVIRT */ - -# define NR_IRQS 16 - -# endif +# define NR_IRQS 224 -#else /* !VISWS && !VOYAGER */ +#else /* IO_APIC || VOYAGER */ -# define NR_IRQS 224 +# define NR_IRQS 16 -#endif /* VISWS */ +#endif /* Voyager specific defines */ /* These define the CPIs we use in linux */ diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h index a1f22771a15a..c61d8b2ab8b9 100644 --- a/arch/x86/include/asm/kexec.h +++ b/arch/x86/include/asm/kexec.h @@ -5,21 +5,8 @@ # define PA_CONTROL_PAGE 0 # define VA_CONTROL_PAGE 1 # define PA_PGD 2 -# define VA_PGD 3 -# define PA_PTE_0 4 -# define VA_PTE_0 5 -# define PA_PTE_1 6 -# define VA_PTE_1 7 -# define PA_SWAP_PAGE 8 -# ifdef CONFIG_X86_PAE -# define PA_PMD_0 9 -# define VA_PMD_0 10 -# define PA_PMD_1 11 -# define VA_PMD_1 12 -# define PAGES_NR 13 -# else -# define PAGES_NR 9 -# endif +# define PA_SWAP_PAGE 3 +# define PAGES_NR 4 #else # define PA_CONTROL_PAGE 0 # define VA_CONTROL_PAGE 1 @@ -170,6 +157,20 @@ relocate_kernel(unsigned long indirection_page, unsigned long start_address) ATTRIB_NORET; #endif +#ifdef CONFIG_X86_32 +#define ARCH_HAS_KIMAGE_ARCH + +struct kimage_arch { + pgd_t *pgd; +#ifdef CONFIG_X86_PAE + pmd_t *pmd0; + pmd_t *pmd1; +#endif + pte_t *pte0; + pte_t *pte1; +}; +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_KEXEC_H */ diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 65679d006337..8346be87cfa1 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -364,6 +364,9 @@ struct kvm_arch{ struct page *ept_identity_pagetable; bool ept_identity_pagetable_done; + + unsigned long irq_sources_bitmap; + unsigned long irq_states[KVM_IOAPIC_NUM_PINS]; }; struct kvm_vm_stat { diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h index ff3a6c236c00..6cb3a467e067 100644 --- a/arch/x86/include/asm/mach-default/mach_apic.h +++ b/arch/x86/include/asm/mach-default/mach_apic.h @@ -32,11 +32,13 @@ static inline cpumask_t target_cpus(void) #define vector_allocation_domain (genapic->vector_allocation_domain) #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID))) #define send_IPI_self (genapic->send_IPI_self) +#define wakeup_secondary_cpu (genapic->wakeup_cpu) extern void setup_apic_routing(void); #else #define INT_DELIVERY_MODE dest_LowestPrio #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ #define TARGET_CPUS (target_cpus()) +#define wakeup_secondary_cpu wakeup_secondary_cpu_via_init /* * Set up the logical destination ID. * diff --git a/arch/x86/include/asm/mach-default/mach_wakecpu.h b/arch/x86/include/asm/mach-default/mach_wakecpu.h index d5c0b826a4ff..ceb013660146 100644 --- a/arch/x86/include/asm/mach-default/mach_wakecpu.h +++ b/arch/x86/include/asm/mach-default/mach_wakecpu.h @@ -1,17 +1,8 @@ #ifndef _ASM_X86_MACH_DEFAULT_MACH_WAKECPU_H #define _ASM_X86_MACH_DEFAULT_MACH_WAKECPU_H -/* - * This file copes with machines that wakeup secondary CPUs by the - * INIT, INIT, STARTUP sequence. - */ - -#define WAKE_SECONDARY_VIA_INIT - -#define TRAMPOLINE_LOW phys_to_virt(0x467) -#define TRAMPOLINE_HIGH phys_to_virt(0x469) - -#define boot_cpu_apicid boot_cpu_physical_apicid +#define TRAMPOLINE_PHYS_LOW (0x467) +#define TRAMPOLINE_PHYS_HIGH (0x469) static inline void wait_for_init_deassert(atomic_t *deassert) { @@ -33,10 +24,12 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) { } -#if APIC_DEBUG - #define inquire_remote_apic(apicid) __inquire_remote_apic(apicid) -#else - #define inquire_remote_apic(apicid) {} -#endif +extern void __inquire_remote_apic(int apicid); + +static inline void inquire_remote_apic(int apicid) +{ + if (apic_verbosity >= APIC_DEBUG) + __inquire_remote_apic(apicid); +} #endif /* _ASM_X86_MACH_DEFAULT_MACH_WAKECPU_H */ diff --git a/arch/x86/include/asm/mach-default/smpboot_hooks.h b/arch/x86/include/asm/mach-default/smpboot_hooks.h index dbab36d64d48..23bf52103b89 100644 --- a/arch/x86/include/asm/mach-default/smpboot_hooks.h +++ b/arch/x86/include/asm/mach-default/smpboot_hooks.h @@ -13,9 +13,11 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) CMOS_WRITE(0xa, 0xf); local_flush_tlb(); pr_debug("1.\n"); - *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4; + *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = + start_eip >> 4; pr_debug("2.\n"); - *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf; + *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = + start_eip & 0xf; pr_debug("3.\n"); } @@ -32,7 +34,7 @@ static inline void smpboot_restore_warm_reset_vector(void) */ CMOS_WRITE(0, 0xf); - *((volatile long *) phys_to_virt(0x467)) = 0; + *((volatile long *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; } static inline void __init smpboot_setup_io_apic(void) diff --git a/arch/x86/include/asm/mach-generic/mach_apic.h b/arch/x86/include/asm/mach-generic/mach_apic.h index 5180bd7478fb..e430f47df667 100644 --- a/arch/x86/include/asm/mach-generic/mach_apic.h +++ b/arch/x86/include/asm/mach-generic/mach_apic.h @@ -27,6 +27,7 @@ #define vector_allocation_domain (genapic->vector_allocation_domain) #define enable_apic_mode (genapic->enable_apic_mode) #define phys_pkg_id (genapic->phys_pkg_id) +#define wakeup_secondary_cpu (genapic->wakeup_cpu) extern void generic_bigsmp_probe(void); diff --git a/arch/x86/include/asm/mach-generic/mach_wakecpu.h b/arch/x86/include/asm/mach-generic/mach_wakecpu.h new file mode 100644 index 000000000000..1ab16b168c8a --- /dev/null +++ b/arch/x86/include/asm/mach-generic/mach_wakecpu.h @@ -0,0 +1,12 @@ +#ifndef _ASM_X86_MACH_GENERIC_MACH_WAKECPU_H +#define _ASM_X86_MACH_GENERIC_MACH_WAKECPU_H + +#define TRAMPOLINE_PHYS_LOW (genapic->trampoline_phys_low) +#define TRAMPOLINE_PHYS_HIGH (genapic->trampoline_phys_high) +#define wait_for_init_deassert (genapic->wait_for_init_deassert) +#define smp_callin_clear_local_apic (genapic->smp_callin_clear_local_apic) +#define store_NMI_vector (genapic->store_NMI_vector) +#define restore_NMI_vector (genapic->restore_NMI_vector) +#define inquire_remote_apic (genapic->inquire_remote_apic) + +#endif /* _ASM_X86_MACH_GENERIC_MACH_APIC_H */ diff --git a/arch/x86/include/asm/mmu_context_32.h b/arch/x86/include/asm/mmu_context_32.h index 8e10015781fb..7e98ce1d2c0e 100644 --- a/arch/x86/include/asm/mmu_context_32.h +++ b/arch/x86/include/asm/mmu_context_32.h @@ -4,9 +4,8 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { #ifdef CONFIG_SMP - unsigned cpu = smp_processor_id(); - if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) - per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_LAZY; + if (x86_read_percpu(cpu_tlbstate.state) == TLBSTATE_OK) + x86_write_percpu(cpu_tlbstate.state, TLBSTATE_LAZY); #endif } @@ -20,8 +19,8 @@ static inline void switch_mm(struct mm_struct *prev, /* stop flush ipis for the previous mm */ cpu_clear(cpu, prev->cpu_vm_mask); #ifdef CONFIG_SMP - per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK; - per_cpu(cpu_tlbstate, cpu).active_mm = next; + x86_write_percpu(cpu_tlbstate.state, TLBSTATE_OK); + x86_write_percpu(cpu_tlbstate.active_mm, next); #endif cpu_set(cpu, next->cpu_vm_mask); @@ -36,8 +35,8 @@ static inline void switch_mm(struct mm_struct *prev, } #ifdef CONFIG_SMP else { - per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK; - BUG_ON(per_cpu(cpu_tlbstate, cpu).active_mm != next); + x86_write_percpu(cpu_tlbstate.state, TLBSTATE_OK); + BUG_ON(x86_read_percpu(cpu_tlbstate.active_mm) != next); if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) { /* We were in lazy tlb mode and leave_mm disabled diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h index 485bdf059ffb..07f1af494ca5 100644 --- a/arch/x86/include/asm/mmzone_32.h +++ b/arch/x86/include/asm/mmzone_32.h @@ -34,10 +34,14 @@ static inline void get_memcfg_numa(void) extern int early_pfn_to_nid(unsigned long pfn); +extern void resume_map_numa_kva(pgd_t *pgd); + #else /* !CONFIG_NUMA */ #define get_memcfg_numa get_memcfg_numa_flat +static inline void resume_map_numa_kva(pgd_t *pgd) {} + #endif /* CONFIG_NUMA */ #ifdef CONFIG_DISCONTIGMEM diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e38859d577a1..cb58643947b9 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -85,7 +85,9 @@ /* AMD64 MSRs. Not complete. See the architecture manual for a more complete list. */ +#define MSR_AMD64_PATCH_LEVEL 0x0000008b #define MSR_AMD64_NB_CFG 0xc001001f +#define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 46be2fa7ac26..4640ddd58fb9 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -22,10 +22,10 @@ static inline unsigned long long native_read_tscp(unsigned int *aux) } /* - * i386 calling convention returns 64-bit value in edx:eax, while - * x86_64 returns at rax. Also, the "A" constraint does not really - * mean rdx:rax in x86_64, so we need specialized behaviour for each - * architecture + * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" + * constraint has different meanings. For i386, "A" means exactly + * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, + * it means rax *or* rdx. */ #ifdef CONFIG_X86_64 #define DECLARE_ARGS(val, low, high) unsigned low, high @@ -108,9 +108,7 @@ static __always_inline unsigned long long __native_read_tsc(void) { DECLARE_ARGS(val, low, high); - rdtsc_barrier(); asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); - rdtsc_barrier(); return EAX_EDX_VAL(val, low, high); } @@ -183,10 +181,10 @@ static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) } #define rdtscl(low) \ - ((low) = (u32)native_read_tsc()) + ((low) = (u32)__native_read_tsc()) #define rdtscll(val) \ - ((val) = native_read_tsc()) + ((val) = __native_read_tsc()) #define rdpmc(counter, low, high) \ do { \ diff --git a/arch/x86/include/asm/numaq/wakecpu.h b/arch/x86/include/asm/numaq/wakecpu.h index c577bda5b1c5..6f499df8eddb 100644 --- a/arch/x86/include/asm/numaq/wakecpu.h +++ b/arch/x86/include/asm/numaq/wakecpu.h @@ -3,12 +3,8 @@ /* This file copes with machines that wakeup secondary CPUs by NMIs */ -#define WAKE_SECONDARY_VIA_NMI - -#define TRAMPOLINE_LOW phys_to_virt(0x8) -#define TRAMPOLINE_HIGH phys_to_virt(0xa) - -#define boot_cpu_apicid boot_cpu_logical_apicid +#define TRAMPOLINE_PHYS_LOW (0x8) +#define TRAMPOLINE_PHYS_HIGH (0xa) /* We don't do anything here because we use NMI's to boot instead */ static inline void wait_for_init_deassert(atomic_t *deassert) @@ -27,17 +23,23 @@ static inline void smp_callin_clear_local_apic(void) static inline void store_NMI_vector(unsigned short *high, unsigned short *low) { printk("Storing NMI vector\n"); - *high = *((volatile unsigned short *) TRAMPOLINE_HIGH); - *low = *((volatile unsigned short *) TRAMPOLINE_LOW); + *high = + *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)); + *low = + *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)); } static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) { printk("Restoring NMI vector\n"); - *((volatile unsigned short *) TRAMPOLINE_HIGH) = *high; - *((volatile unsigned short *) TRAMPOLINE_LOW) = *low; + *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = + *high; + *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = + *low; } -#define inquire_remote_apic(apicid) {} +static inline void inquire_remote_apic(int apicid) +{ +} #endif /* __ASM_NUMAQ_WAKECPU_H */ diff --git a/arch/x86/include/asm/pci_64.h b/arch/x86/include/asm/pci_64.h index 5b28995d664e..d02d936840a3 100644 --- a/arch/x86/include/asm/pci_64.h +++ b/arch/x86/include/asm/pci_64.h @@ -34,8 +34,6 @@ extern void pci_iommu_alloc(void); */ #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) -#if defined(CONFIG_GART_IOMMU) || defined(CONFIG_CALGARY_IOMMU) - #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ dma_addr_t ADDR_NAME; #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ @@ -49,18 +47,6 @@ extern void pci_iommu_alloc(void); #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ (((PTR)->LEN_NAME) = (VAL)) -#else -/* No IOMMU */ - -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#endif - #endif /* __KERNEL__ */ #endif /* _ASM_X86_PCI_64_H */ diff --git a/arch/x86/include/asm/pgtable-2level.h b/arch/x86/include/asm/pgtable-2level.h index b17edfd23628..e0d199fe1d83 100644 --- a/arch/x86/include/asm/pgtable-2level.h +++ b/arch/x86/include/asm/pgtable-2level.h @@ -56,23 +56,55 @@ static inline pte_t native_ptep_get_and_clear(pte_t *xp) #define pte_none(x) (!(x).pte_low) /* - * Bits 0, 6 and 7 are taken, split up the 29 bits of offset - * into this range: + * Bits _PAGE_BIT_PRESENT, _PAGE_BIT_FILE and _PAGE_BIT_PROTNONE are taken, + * split up the 29 bits of offset into this range: */ #define PTE_FILE_MAX_BITS 29 +#define PTE_FILE_SHIFT1 (_PAGE_BIT_PRESENT + 1) +#if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE +#define PTE_FILE_SHIFT2 (_PAGE_BIT_FILE + 1) +#define PTE_FILE_SHIFT3 (_PAGE_BIT_PROTNONE + 1) +#else +#define PTE_FILE_SHIFT2 (_PAGE_BIT_PROTNONE + 1) +#define PTE_FILE_SHIFT3 (_PAGE_BIT_FILE + 1) +#endif +#define PTE_FILE_BITS1 (PTE_FILE_SHIFT2 - PTE_FILE_SHIFT1 - 1) +#define PTE_FILE_BITS2 (PTE_FILE_SHIFT3 - PTE_FILE_SHIFT2 - 1) #define pte_to_pgoff(pte) \ - ((((pte).pte_low >> 1) & 0x1f) + (((pte).pte_low >> 8) << 5)) + ((((pte).pte_low >> PTE_FILE_SHIFT1) \ + & ((1U << PTE_FILE_BITS1) - 1)) \ + + ((((pte).pte_low >> PTE_FILE_SHIFT2) \ + & ((1U << PTE_FILE_BITS2) - 1)) << PTE_FILE_BITS1) \ + + (((pte).pte_low >> PTE_FILE_SHIFT3) \ + << (PTE_FILE_BITS1 + PTE_FILE_BITS2))) #define pgoff_to_pte(off) \ - ((pte_t) { .pte_low = (((off) & 0x1f) << 1) + \ - (((off) >> 5) << 8) + _PAGE_FILE }) + ((pte_t) { .pte_low = \ + (((off) & ((1U << PTE_FILE_BITS1) - 1)) << PTE_FILE_SHIFT1) \ + + ((((off) >> PTE_FILE_BITS1) & ((1U << PTE_FILE_BITS2) - 1)) \ + << PTE_FILE_SHIFT2) \ + + (((off) >> (PTE_FILE_BITS1 + PTE_FILE_BITS2)) \ + << PTE_FILE_SHIFT3) \ + + _PAGE_FILE }) /* Encode and de-code a swap entry */ -#define __swp_type(x) (((x).val >> 1) & 0x1f) -#define __swp_offset(x) ((x).val >> 8) -#define __swp_entry(type, offset) \ - ((swp_entry_t) { ((type) << 1) | ((offset) << 8) }) +#if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE +#define SWP_TYPE_BITS (_PAGE_BIT_FILE - _PAGE_BIT_PRESENT - 1) +#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1) +#else +#define SWP_TYPE_BITS (_PAGE_BIT_PROTNONE - _PAGE_BIT_PRESENT - 1) +#define SWP_OFFSET_SHIFT (_PAGE_BIT_FILE + 1) +#endif + +#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) + +#define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \ + & ((1U << SWP_TYPE_BITS) - 1)) +#define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT) +#define __swp_entry(type, offset) ((swp_entry_t) { \ + ((type) << (_PAGE_BIT_PRESENT + 1)) \ + | ((offset) << SWP_OFFSET_SHIFT) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low }) #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index fb16cec702e4..447da43cddb3 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h @@ -120,13 +120,13 @@ static inline void pud_clear(pud_t *pudp) write_cr3(pgd); } -#define pud_page(pud) ((struct page *) __va(pud_val(pud) & PTE_PFN_MASK)) +#define pud_page(pud) pfn_to_page(pud_val(pud) >> PAGE_SHIFT) #define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PTE_PFN_MASK)) /* Find an entry in the second-level page table.. */ -#define pmd_offset(pud, address) ((pmd_t *)pud_page(*(pud)) + \ +#define pmd_offset(pud, address) ((pmd_t *)pud_page_vaddr(*(pud)) + \ pmd_index(address)) #ifdef CONFIG_SMP @@ -166,6 +166,7 @@ static inline int pte_none(pte_t pte) #define PTE_FILE_MAX_BITS 32 /* Encode and de-code a swap entry */ +#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5) #define __swp_type(x) (((x).val) & 0x1f) #define __swp_offset(x) ((x).val >> 5) #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index c012f3b11671..83e69f4a37f0 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -10,7 +10,6 @@ #define _PAGE_BIT_PCD 4 /* page cache disabled */ #define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */ #define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */ -#define _PAGE_BIT_FILE 6 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */ #define _PAGE_BIT_PAT 7 /* on 4KB pages */ #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */ @@ -22,6 +21,12 @@ #define _PAGE_BIT_CPA_TEST _PAGE_BIT_UNUSED1 #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */ +/* If _PAGE_BIT_PRESENT is clear, we use these: */ +/* - if the user mapped it with PROT_NONE; pte_present gives true */ +#define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL +/* - set: nonlinear file mapping, saved PTE; unset:swap */ +#define _PAGE_BIT_FILE _PAGE_BIT_DIRTY + #define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT) #define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW) #define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER) @@ -46,11 +51,8 @@ #define _PAGE_NX (_AT(pteval_t, 0)) #endif -/* If _PAGE_PRESENT is clear, we use these: */ -#define _PAGE_FILE _PAGE_DIRTY /* nonlinear file mapping, - * saved PTE; unset:swap */ -#define _PAGE_PROTNONE _PAGE_PSE /* if the user mapped it with PROT_NONE; - pte_present gives true */ +#define _PAGE_FILE (_AT(pteval_t, 1) << _PAGE_BIT_FILE) +#define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE) #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \ _PAGE_ACCESSED | _PAGE_DIRTY) @@ -158,8 +160,19 @@ #define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */ #endif +/* + * Macro to mark a page protection value as UC- + */ +#define pgprot_noncached(prot) \ + ((boot_cpu_data.x86 > 3) \ + ? (__pgprot(pgprot_val(prot) | _PAGE_CACHE_UC_MINUS)) \ + : (prot)) + #ifndef __ASSEMBLY__ +#define pgprot_writecombine pgprot_writecombine +extern pgprot_t pgprot_writecombine(pgprot_t prot); + /* * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. @@ -329,6 +342,9 @@ static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) #define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask) #ifndef __ASSEMBLY__ +/* Indicate that x86 has its own track and untrack pfn vma functions */ +#define __HAVE_PFNMAP_TRACKING + #define __HAVE_PHYS_MEM_ACCESS_PROT struct file; pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h index f9d5889b336b..72b020deb46b 100644 --- a/arch/x86/include/asm/pgtable_32.h +++ b/arch/x86/include/asm/pgtable_32.h @@ -100,15 +100,6 @@ extern unsigned long pg0[]; # include #endif -/* - * Macro to mark a page protection value as "uncacheable". - * On processors which do not support it, this is a no-op. - */ -#define pgprot_noncached(prot) \ - ((boot_cpu_data.x86 > 3) \ - ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) \ - : (prot)) - /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index 545a0e042bb2..ba09289accaa 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -146,7 +146,7 @@ static inline void native_pgd_clear(pgd_t *pgd) #define PGDIR_MASK (~(PGDIR_SIZE - 1)) -#define MAXMEM _AC(0x00003fffffffffff, UL) +#define MAXMEM _AC(__AC(1, UL) << MAX_PHYSMEM_BITS, UL) #define VMALLOC_START _AC(0xffffc20000000000, UL) #define VMALLOC_END _AC(0xffffe1ffffffffff, UL) #define VMEMMAP_START _AC(0xffffe20000000000, UL) @@ -176,12 +176,6 @@ static inline int pmd_bad(pmd_t pmd) #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) /* FIXME: is this right? */ -/* - * Macro to mark a page protection value as "uncacheable". - */ -#define pgprot_noncached(prot) \ - (__pgprot(pgprot_val((prot)) | _PAGE_PCD | _PAGE_PWT)) - /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. @@ -250,10 +244,22 @@ static inline int pud_large(pud_t pte) extern int direct_gbpages; /* Encode and de-code a swap entry */ -#define __swp_type(x) (((x).val >> 1) & 0x3f) -#define __swp_offset(x) ((x).val >> 8) -#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | \ - ((offset) << 8) }) +#if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE +#define SWP_TYPE_BITS (_PAGE_BIT_FILE - _PAGE_BIT_PRESENT - 1) +#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1) +#else +#define SWP_TYPE_BITS (_PAGE_BIT_PROTNONE - _PAGE_BIT_PRESENT - 1) +#define SWP_OFFSET_SHIFT (_PAGE_BIT_FILE + 1) +#endif + +#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) + +#define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \ + & ((1U << SWP_TYPE_BITS) - 1)) +#define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT) +#define __swp_entry(type, offset) ((swp_entry_t) { \ + ((type) << (_PAGE_BIT_PRESENT + 1)) \ + | ((offset) << SWP_OFFSET_SHIFT) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) }) #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) diff --git a/arch/x86/include/asm/prctl.h b/arch/x86/include/asm/prctl.h index fe681147a4f7..a8894647dd9a 100644 --- a/arch/x86/include/asm/prctl.h +++ b/arch/x86/include/asm/prctl.h @@ -6,5 +6,8 @@ #define ARCH_GET_FS 0x1003 #define ARCH_GET_GS 0x1004 +#ifdef CONFIG_X86_64 +extern long sys_arch_prctl(int, unsigned long); +#endif /* CONFIG_X86_64 */ #endif /* _ASM_X86_PRCTL_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 5ca01e383269..a570eafa4755 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -110,6 +110,7 @@ struct cpuinfo_x86 { /* Index into per_cpu list: */ u16 cpu_index; #endif + unsigned int x86_hyper_vendor; } __attribute__((__aligned__(SMP_CACHE_BYTES))); #define X86_VENDOR_INTEL 0 @@ -123,6 +124,9 @@ struct cpuinfo_x86 { #define X86_VENDOR_UNKNOWN 0xff +#define X86_HYPER_VENDOR_NONE 0 +#define X86_HYPER_VENDOR_VMWARE 1 + /* * capabilities of CPUs */ diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index d1531c8480b7..eefb0594b058 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -271,8 +271,6 @@ extern int do_get_thread_area(struct task_struct *p, int idx, extern int do_set_thread_area(struct task_struct *p, int idx, struct user_desc __user *info, int can_allocate); -#define __ARCH_WANT_COMPAT_SYS_PTRACE - #endif /* __KERNEL__ */ #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h index df7710354f85..562d4fd31ba8 100644 --- a/arch/x86/include/asm/reboot.h +++ b/arch/x86/include/asm/reboot.h @@ -1,6 +1,8 @@ #ifndef _ASM_X86_REBOOT_H #define _ASM_X86_REBOOT_H +#include + struct pt_regs; struct machine_ops { @@ -18,4 +20,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs); void native_machine_shutdown(void); void machine_real_restart(const unsigned char *code, int length); +typedef void (*nmi_shootdown_cb)(int, struct die_args*); +void nmi_shootdown_cpus(nmi_shootdown_cb callback); + #endif /* _ASM_X86_REBOOT_H */ diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index f12d37237465..4fcd53fd5f43 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -8,6 +8,10 @@ /* Interrupt control for vSMPowered x86_64 systems */ void vsmp_init(void); + +void setup_bios_corruption_check(void); + + #ifdef CONFIG_X86_VISWS extern void visws_early_detect(void); extern int is_visws_box(void); @@ -16,6 +20,8 @@ static inline void visws_early_detect(void) { } static inline int is_visws_box(void) { return 0; } #endif +extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); +extern int wakeup_secondary_cpu_via_init(int apicid, unsigned long start_eip); /* * Any setup quirks to be performed? */ @@ -39,6 +45,7 @@ struct x86_quirks { void (*smp_read_mpc_oem)(struct mp_config_oemtable *oemtable, unsigned short oemsize); int (*setup_ioapic_ids)(void); + int (*update_genapic)(void); }; extern struct x86_quirks *x86_quirks; diff --git a/arch/x86/include/asm/sigframe.h b/arch/x86/include/asm/sigframe.h new file mode 100644 index 000000000000..4e0fe26d27d3 --- /dev/null +++ b/arch/x86/include/asm/sigframe.h @@ -0,0 +1,70 @@ +#ifndef _ASM_X86_SIGFRAME_H +#define _ASM_X86_SIGFRAME_H + +#include +#include +#include + +#ifdef CONFIG_X86_32 +#define sigframe_ia32 sigframe +#define rt_sigframe_ia32 rt_sigframe +#define sigcontext_ia32 sigcontext +#define _fpstate_ia32 _fpstate +#define ucontext_ia32 ucontext +#else /* !CONFIG_X86_32 */ + +#ifdef CONFIG_IA32_EMULATION +#include +#endif /* CONFIG_IA32_EMULATION */ + +#endif /* CONFIG_X86_32 */ + +#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) +struct sigframe_ia32 { + u32 pretcode; + int sig; + struct sigcontext_ia32 sc; + /* + * fpstate is unused. fpstate is moved/allocated after + * retcode[] below. This movement allows to have the FP state and the + * future state extensions (xsave) stay together. + * And at the same time retaining the unused fpstate, prevents changing + * the offset of extramask[] in the sigframe and thus prevent any + * legacy application accessing/modifying it. + */ + struct _fpstate_ia32 fpstate_unused; +#ifdef CONFIG_IA32_EMULATION + unsigned int extramask[_COMPAT_NSIG_WORDS-1]; +#else /* !CONFIG_IA32_EMULATION */ + unsigned long extramask[_NSIG_WORDS-1]; +#endif /* CONFIG_IA32_EMULATION */ + char retcode[8]; + /* fp state follows here */ +}; + +struct rt_sigframe_ia32 { + u32 pretcode; + int sig; + u32 pinfo; + u32 puc; +#ifdef CONFIG_IA32_EMULATION + compat_siginfo_t info; +#else /* !CONFIG_IA32_EMULATION */ + struct siginfo info; +#endif /* CONFIG_IA32_EMULATION */ + struct ucontext_ia32 uc; + char retcode[8]; + /* fp state follows here */ +}; +#endif /* defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) */ + +#ifdef CONFIG_X86_64 +struct rt_sigframe { + char __user *pretcode; + struct ucontext uc; + struct siginfo info; + /* fp state follows here */ +}; +#endif /* CONFIG_X86_64 */ + +#endif /* _ASM_X86_SIGFRAME_H */ diff --git a/arch/x86/include/asm/signal.h b/arch/x86/include/asm/signal.h index 96ac44f275da..7761a5d554bb 100644 --- a/arch/x86/include/asm/signal.h +++ b/arch/x86/include/asm/signal.h @@ -121,6 +121,10 @@ typedef unsigned long sigset_t; #ifndef __ASSEMBLY__ +# ifdef __KERNEL__ +extern void do_notify_resume(struct pt_regs *, void *, __u32); +# endif /* __KERNEL__ */ + #ifdef __i386__ # ifdef __KERNEL__ struct old_sigaction { @@ -141,8 +145,6 @@ struct k_sigaction { struct sigaction sa; }; -extern void do_notify_resume(struct pt_regs *, void *, __u32); - # else /* __KERNEL__ */ /* Here we must cater to libcs that poke about in kernel headers. */ diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 2766021aef80..d12811ce51d9 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -225,5 +225,11 @@ static inline int hard_smp_processor_id(void) #endif /* CONFIG_X86_LOCAL_APIC */ +#ifdef CONFIG_X86_HAS_BOOT_CPU_ID +extern unsigned char boot_cpu_id; +#else +#define boot_cpu_id 0 +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_SMP_H */ diff --git a/arch/x86/include/asm/sparsemem.h b/arch/x86/include/asm/sparsemem.h index be44f7dab395..e3cc3c063ec5 100644 --- a/arch/x86/include/asm/sparsemem.h +++ b/arch/x86/include/asm/sparsemem.h @@ -27,7 +27,7 @@ #else /* CONFIG_X86_32 */ # define SECTION_SIZE_BITS 27 /* matt - 128 is convenient right now */ # define MAX_PHYSADDR_BITS 44 -# define MAX_PHYSMEM_BITS 44 +# define MAX_PHYSMEM_BITS 44 /* Can be max 45 bits */ #endif #endif /* CONFIG_SPARSEMEM */ diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h index 87803da44010..9c6797c3e56c 100644 --- a/arch/x86/include/asm/syscalls.h +++ b/arch/x86/include/asm/syscalls.h @@ -19,6 +19,13 @@ /* kernel/ioport.c */ asmlinkage long sys_ioperm(unsigned long, unsigned long, int); +/* kernel/ldt.c */ +asmlinkage int sys_modify_ldt(int, void __user *, unsigned long); + +/* kernel/tls.c */ +asmlinkage int sys_set_thread_area(struct user_desc __user *); +asmlinkage int sys_get_thread_area(struct user_desc __user *); + /* X86_32 only */ #ifdef CONFIG_X86_32 /* kernel/process_32.c */ @@ -33,14 +40,11 @@ asmlinkage int sys_sigaction(int, const struct old_sigaction __user *, struct old_sigaction __user *); asmlinkage int sys_sigaltstack(unsigned long); asmlinkage unsigned long sys_sigreturn(unsigned long); -asmlinkage int sys_rt_sigreturn(unsigned long); +asmlinkage int sys_rt_sigreturn(struct pt_regs); /* kernel/ioport.c */ asmlinkage long sys_iopl(unsigned long); -/* kernel/ldt.c */ -asmlinkage int sys_modify_ldt(int, void __user *, unsigned long); - /* kernel/sys_i386_32.c */ asmlinkage long sys_mmap2(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long); @@ -54,10 +58,6 @@ asmlinkage int sys_uname(struct old_utsname __user *); struct oldold_utsname; asmlinkage int sys_olduname(struct oldold_utsname __user *); -/* kernel/tls.c */ -asmlinkage int sys_set_thread_area(struct user_desc __user *); -asmlinkage int sys_get_thread_area(struct user_desc __user *); - /* kernel/vm86_32.c */ asmlinkage int sys_vm86old(struct pt_regs); asmlinkage int sys_vm86(struct pt_regs); diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h index 2ed3f0f44ff7..8e626ea33a1a 100644 --- a/arch/x86/include/asm/system.h +++ b/arch/x86/include/asm/system.h @@ -17,12 +17,12 @@ # define AT_VECTOR_SIZE_ARCH 1 #endif -#ifdef CONFIG_X86_32 - struct task_struct; /* one of the stranger aspects of C forward declarations */ struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next); +#ifdef CONFIG_X86_32 + /* * Saving eflags is important. It switches not only IOPL between tasks, * it also protects other tasks from NT leaking through sysenter etc. @@ -314,6 +314,8 @@ extern void free_init_pages(char *what, unsigned long begin, unsigned long end); void default_idle(void); +void stop_this_cpu(void *dummy); + /* * Force strict CPU ordering. * And yes, this is required on UP too when we're talking diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index e44d379faad2..8dbc57390d25 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -24,7 +24,7 @@ struct exec_domain; struct thread_info { struct task_struct *task; /* main task structure */ struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ + __u32 flags; /* low level flags */ __u32 status; /* thread synchronous flags */ __u32 cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 90ac7718469a..ff386ff50ed7 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -154,7 +154,7 @@ extern unsigned long node_remap_size[]; #endif -/* sched_domains SD_NODE_INIT for NUMAQ machines */ +/* sched_domains SD_NODE_INIT for NUMA machines */ #define SD_NODE_INIT (struct sched_domain) { \ .min_interval = 8, \ .max_interval = 32, \ @@ -169,8 +169,9 @@ extern unsigned long node_remap_size[]; .flags = SD_LOAD_BALANCE \ | SD_BALANCE_EXEC \ | SD_BALANCE_FORK \ - | SD_SERIALIZE \ - | SD_WAKE_BALANCE, \ + | SD_WAKE_AFFINE \ + | SD_WAKE_BALANCE \ + | SD_SERIALIZE, \ .last_balance = jiffies, \ .balance_interval = 1, \ } @@ -238,7 +239,7 @@ struct pci_bus; void set_pci_bus_resources_arch_default(struct pci_bus *b); #ifdef CONFIG_SMP -#define mc_capable() (boot_cpu_data.x86_max_cores > 1) +#define mc_capable() (cpus_weight(per_cpu(cpu_core_map, 0)) != nr_cpu_ids) #define smt_capable() (smp_num_siblings > 1) #endif diff --git a/arch/x86/include/asm/trampoline.h b/arch/x86/include/asm/trampoline.h index fa0d79facdbc..780ba0ab94f9 100644 --- a/arch/x86/include/asm/trampoline.h +++ b/arch/x86/include/asm/trampoline.h @@ -3,6 +3,7 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_X86_TRAMPOLINE /* * Trampoline 80x86 program as an array. */ @@ -13,8 +14,14 @@ extern unsigned char *trampoline_base; extern unsigned long init_rsp; extern unsigned long initial_code; +#define TRAMPOLINE_SIZE roundup(trampoline_end - trampoline_data, PAGE_SIZE) #define TRAMPOLINE_BASE 0x6000 + extern unsigned long setup_trampoline(void); +extern void __init reserve_trampoline_memory(void); +#else +static inline void reserve_trampoline_memory(void) {}; +#endif /* CONFIG_X86_TRAMPOLINE */ #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 45dee286e45c..2ee0a3bceedf 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -46,6 +46,10 @@ dotraplinkage void do_coprocessor_segment_overrun(struct pt_regs *, long); dotraplinkage void do_invalid_TSS(struct pt_regs *, long); dotraplinkage void do_segment_not_present(struct pt_regs *, long); dotraplinkage void do_stack_segment(struct pt_regs *, long); +#ifdef CONFIG_X86_64 +dotraplinkage void do_double_fault(struct pt_regs *, long); +asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *); +#endif dotraplinkage void do_general_protection(struct pt_regs *, long); dotraplinkage void do_page_fault(struct pt_regs *, unsigned long); dotraplinkage void do_spurious_interrupt_bug(struct pt_regs *, long); @@ -72,10 +76,13 @@ static inline int get_si_code(unsigned long condition) extern int panic_on_unrecovered_nmi; extern int kstack_depth_to_print; -#ifdef CONFIG_X86_32 void math_error(void __user *); -unsigned long patch_espfix_desc(unsigned long, unsigned long); asmlinkage void math_emulate(long); +#ifdef CONFIG_X86_32 +unsigned long patch_espfix_desc(unsigned long, unsigned long); +#else +asmlinkage void smp_thermal_interrupt(void); +asmlinkage void mce_threshold_interrupt(void); #endif #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 35c54921b2e4..580c3ee6c58c 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -350,14 +350,14 @@ do { \ #define __put_user_nocheck(x, ptr, size) \ ({ \ - long __pu_err; \ + int __pu_err; \ __put_user_size((x), (ptr), (size), __pu_err, -EFAULT); \ __pu_err; \ }) #define __get_user_nocheck(x, ptr, size) \ ({ \ - long __gu_err; \ + int __gu_err; \ unsigned long __gu_val; \ __get_user_size(__gu_val, (ptr), (size), __gu_err, -EFAULT); \ (x) = (__force __typeof__(*(ptr)))__gu_val; \ diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h index 664f15280f14..f8cfd00db450 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -46,7 +46,7 @@ int __copy_from_user(void *dst, const void __user *src, unsigned size) return ret; case 10: __get_user_asm(*(u64 *)dst, (u64 __user *)src, - ret, "q", "", "=r", 16); + ret, "q", "", "=r", 10); if (unlikely(ret)) return ret; __get_user_asm(*(u16 *)(8 + (char *)dst), diff --git a/arch/x86/include/asm/unistd_64.h b/arch/x86/include/asm/unistd_64.h index 834b2c1d89fb..d2e415e6666f 100644 --- a/arch/x86/include/asm/unistd_64.h +++ b/arch/x86/include/asm/unistd_64.h @@ -639,8 +639,8 @@ __SYSCALL(__NR_fallocate, sys_fallocate) __SYSCALL(__NR_timerfd_settime, sys_timerfd_settime) #define __NR_timerfd_gettime 287 __SYSCALL(__NR_timerfd_gettime, sys_timerfd_gettime) -#define __NR_paccept 288 -__SYSCALL(__NR_paccept, sys_paccept) +#define __NR_accept4 288 +__SYSCALL(__NR_accept4, sys_accept4) #define __NR_signalfd4 289 __SYSCALL(__NR_signalfd4, sys_signalfd4) #define __NR_eventfd2 290 diff --git a/arch/x86/include/asm/uv/bios.h b/arch/x86/include/asm/uv/bios.h index d931d3b7e6f7..7ed17ff502b9 100644 --- a/arch/x86/include/asm/uv/bios.h +++ b/arch/x86/include/asm/uv/bios.h @@ -32,13 +32,18 @@ enum uv_bios_cmd { UV_BIOS_COMMON, UV_BIOS_GET_SN_INFO, - UV_BIOS_FREQ_BASE + UV_BIOS_FREQ_BASE, + UV_BIOS_WATCHLIST_ALLOC, + UV_BIOS_WATCHLIST_FREE, + UV_BIOS_MEMPROTECT, + UV_BIOS_GET_PARTITION_ADDR }; /* * Status values returned from a BIOS call. */ enum { + BIOS_STATUS_MORE_PASSES = 1, BIOS_STATUS_SUCCESS = 0, BIOS_STATUS_UNIMPLEMENTED = -ENOSYS, BIOS_STATUS_EINVAL = -EINVAL, @@ -71,6 +76,21 @@ union partition_info_u { }; }; +union uv_watchlist_u { + u64 val; + struct { + u64 blade : 16, + size : 32, + filler : 16; + }; +}; + +enum uv_memprotect { + UV_MEMPROT_RESTRICT_ACCESS, + UV_MEMPROT_ALLOW_AMO, + UV_MEMPROT_ALLOW_RW +}; + /* * bios calls have 6 parameters */ @@ -80,14 +100,20 @@ extern s64 uv_bios_call_reentrant(enum uv_bios_cmd, u64, u64, u64, u64, u64); extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *); extern s64 uv_bios_freq_base(u64, u64 *); +extern int uv_bios_mq_watchlist_alloc(int, unsigned long, unsigned int, + unsigned long *); +extern int uv_bios_mq_watchlist_free(int, int); +extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect); +extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *); extern void uv_bios_init(void); +extern unsigned long sn_rtc_cycles_per_second; extern int uv_type; extern long sn_partition_id; -extern long uv_coherency_id; -extern long uv_region_size; -#define partition_coherence_id() (uv_coherency_id) +extern long sn_coherency_id; +extern long sn_region_size; +#define partition_coherence_id() (sn_coherency_id) extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */ diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index c6ad93e315c8..777327ef05c1 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -112,25 +113,37 @@ */ #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) +struct uv_scir_s { + struct timer_list timer; + unsigned long offset; + unsigned long last; + unsigned long idle_on; + unsigned long idle_off; + unsigned char state; + unsigned char enabled; +}; + /* * The following defines attributes of the HUB chip. These attributes are * frequently referenced and are kept in the per-cpu data areas of each cpu. * They are kept together in a struct to minimize cache misses. */ struct uv_hub_info_s { - unsigned long global_mmr_base; - unsigned long gpa_mask; - unsigned long gnode_upper; - unsigned long lowmem_remap_top; - unsigned long lowmem_remap_base; - unsigned short pnode; - unsigned short pnode_mask; - unsigned short coherency_domain_number; - unsigned short numa_blade_id; - unsigned char blade_processor_id; - unsigned char m_val; - unsigned char n_val; + unsigned long global_mmr_base; + unsigned long gpa_mask; + unsigned long gnode_upper; + unsigned long lowmem_remap_top; + unsigned long lowmem_remap_base; + unsigned short pnode; + unsigned short pnode_mask; + unsigned short coherency_domain_number; + unsigned short numa_blade_id; + unsigned char blade_processor_id; + unsigned char m_val; + unsigned char n_val; + struct uv_scir_s scir; }; + DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) @@ -162,6 +175,30 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); #define UV_APIC_PNODE_SHIFT 6 +/* Local Bus from cpu's perspective */ +#define LOCAL_BUS_BASE 0x1c00000 +#define LOCAL_BUS_SIZE (4 * 1024 * 1024) + +/* + * System Controller Interface Reg + * + * Note there are NO leds on a UV system. This register is only + * used by the system controller to monitor system-wide operation. + * There are 64 regs per node. With Nahelem cpus (2 cores per node, + * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on + * a node. + * + * The window is located at top of ACPI MMR space + */ +#define SCIR_WINDOW_COUNT 64 +#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ + LOCAL_BUS_SIZE - \ + SCIR_WINDOW_COUNT) + +#define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ +#define SCIR_CPU_ACTIVITY 0x02 /* not idle */ +#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ + /* * Macros for converting between kernel virtual addresses, socket local physical * addresses, and UV global physical addresses. @@ -173,7 +210,7 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) { if (paddr < uv_hub_info->lowmem_remap_top) - paddr += uv_hub_info->lowmem_remap_base; + paddr |= uv_hub_info->lowmem_remap_base; return paddr | uv_hub_info->gnode_upper; } @@ -181,19 +218,7 @@ static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) /* socket virtual --> UV global physical address */ static inline unsigned long uv_gpa(void *v) { - return __pa(v) | uv_hub_info->gnode_upper; -} - -/* socket virtual --> UV global physical address */ -static inline void *uv_vgpa(void *v) -{ - return (void *)uv_gpa(v); -} - -/* UV global physical address --> socket virtual */ -static inline void *uv_va(unsigned long gpa) -{ - return __va(gpa & uv_hub_info->gpa_mask); + return uv_soc_phys_ram_to_gpa(__pa(v)); } /* pnode, offset --> socket virtual */ @@ -276,6 +301,16 @@ static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) *uv_local_mmr_address(offset) = val; } +static inline unsigned char uv_read_local_mmr8(unsigned long offset) +{ + return *((unsigned char *)uv_local_mmr_address(offset)); +} + +static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) +{ + *((unsigned char *)uv_local_mmr_address(offset)) = val; +} + /* * Structures and definitions for converting between cpu, node, pnode, and blade * numbers. @@ -350,5 +385,20 @@ static inline int uv_num_possible_blades(void) return uv_possible_blades; } -#endif /* _ASM_X86_UV_UV_HUB_H */ +/* Update SCIR state */ +static inline void uv_set_scir_bits(unsigned char value) +{ + if (uv_hub_info->scir.state != value) { + uv_hub_info->scir.state = value; + uv_write_local_mmr8(uv_hub_info->scir.offset, value); + } +} +static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) +{ + if (uv_cpu_hub_info(cpu)->scir.state != value) { + uv_cpu_hub_info(cpu)->scir.state = value; + uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value); + } +} +#endif /* _ASM_X86_UV_UV_HUB_H */ diff --git a/arch/x86/include/asm/vmi.h b/arch/x86/include/asm/vmi.h index b7c0dea119fe..61e08c0a2907 100644 --- a/arch/x86/include/asm/vmi.h +++ b/arch/x86/include/asm/vmi.h @@ -223,9 +223,15 @@ struct pci_header { } __attribute__((packed)); /* Function prototypes for bootstrapping */ +#ifdef CONFIG_VMI extern void vmi_init(void); +extern void vmi_activate(void); extern void vmi_bringup(void); -extern void vmi_apply_boot_page_allocations(void); +#else +static inline void vmi_init(void) {} +static inline void vmi_activate(void) {} +static inline void vmi_bringup(void) {} +#endif /* State needed to start an application processor in an SMP system. */ struct vmi_ap_state { diff --git a/arch/x86/include/asm/vmware.h b/arch/x86/include/asm/vmware.h new file mode 100644 index 000000000000..c11b7e100d83 --- /dev/null +++ b/arch/x86/include/asm/vmware.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2008, VMware, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef ASM_X86__VMWARE_H +#define ASM_X86__VMWARE_H + +extern unsigned long vmware_get_tsc_khz(void); +extern int vmware_platform(void); +extern void vmware_set_feature_bits(struct cpuinfo_x86 *c); + +#endif diff --git a/arch/x86/include/asm/voyager.h b/arch/x86/include/asm/voyager.h index 9c811d2e6f91..b3e647307625 100644 --- a/arch/x86/include/asm/voyager.h +++ b/arch/x86/include/asm/voyager.h @@ -520,6 +520,7 @@ extern void voyager_restart(void); extern void voyager_cat_power_off(void); extern void voyager_cat_do_common_interrupt(void); extern void voyager_handle_nmi(void); +extern void voyager_smp_intr_init(void); /* Commands for the following are */ #define VOYAGER_PSI_READ 0 #define VOYAGER_PSI_WRITE 1 diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h index 3f6000d95fe2..5e79ca694326 100644 --- a/arch/x86/include/asm/xen/hypercall.h +++ b/arch/x86/include/asm/xen/hypercall.h @@ -33,8 +33,14 @@ #ifndef _ASM_X86_XEN_HYPERCALL_H #define _ASM_X86_XEN_HYPERCALL_H +#include +#include #include #include +#include + +#include +#include #include #include diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h index a38d25ac87d2..81fbd735aec4 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -33,39 +33,10 @@ #ifndef _ASM_X86_XEN_HYPERVISOR_H #define _ASM_X86_XEN_HYPERVISOR_H -#include -#include - -#include -#include - -#include -#include -#include -#if defined(__i386__) -# ifdef CONFIG_X86_PAE -# include -# else -# include -# endif -#endif -#include - /* arch/i386/kernel/setup.c */ extern struct shared_info *HYPERVISOR_shared_info; extern struct start_info *xen_start_info; -/* arch/i386/mach-xen/evtchn.c */ -/* Force a proper event-channel callback from Xen. */ -extern void force_evtchn_callback(void); - -/* Turn jiffies into Xen system time. */ -u64 jiffies_to_st(unsigned long jiffies); - - -#define MULTI_UVMFLAGS_INDEX 3 -#define MULTI_UVMDOMID_INDEX 4 - enum xen_domain_type { XEN_NATIVE, XEN_PV_DOMAIN, @@ -74,9 +45,15 @@ enum xen_domain_type { extern enum xen_domain_type xen_domain_type; +#ifdef CONFIG_XEN #define xen_domain() (xen_domain_type != XEN_NATIVE) -#define xen_pv_domain() (xen_domain_type == XEN_PV_DOMAIN) +#else +#define xen_domain() (0) +#endif + +#define xen_pv_domain() (xen_domain() && xen_domain_type == XEN_PV_DOMAIN) +#define xen_hvm_domain() (xen_domain() && xen_domain_type == XEN_HVM_DOMAIN) + #define xen_initial_domain() (xen_pv_domain() && xen_start_info->flags & SIF_INITDOMAIN) -#define xen_hvm_domain() (xen_domain_type == XEN_HVM_DOMAIN) #endif /* _ASM_X86_XEN_HYPERVISOR_H */ diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h index bc628998a1b9..7ef617ef1df3 100644 --- a/arch/x86/include/asm/xen/page.h +++ b/arch/x86/include/asm/xen/page.h @@ -1,11 +1,16 @@ #ifndef _ASM_X86_XEN_PAGE_H #define _ASM_X86_XEN_PAGE_H +#include +#include +#include #include #include +#include #include +#include #include /* Xen machine address */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index d7e5a58ee22f..1f208aaee780 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -6,11 +6,13 @@ extra-y := head_$(BITS).o head$(BITS).o head.o init_task.o vmlinu CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE) -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER # Do not profile debug and lowlevel utilities CFLAGS_REMOVE_tsc.o = -pg CFLAGS_REMOVE_rtc.o = -pg CFLAGS_REMOVE_paravirt-spinlocks.o = -pg +CFLAGS_REMOVE_ftrace.o = -pg +CFLAGS_REMOVE_early_printk.o = -pg endif # @@ -22,9 +24,9 @@ CFLAGS_vsyscall_64.o := $(PROFILING) -g0 $(nostackp) CFLAGS_hpet.o := $(nostackp) CFLAGS_tsc.o := $(nostackp) -obj-y := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o +obj-y := process_$(BITS).o signal.o entry_$(BITS).o obj-y += traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o -obj-y += time_$(BITS).o ioport.o ldt.o +obj-y += time_$(BITS).o ioport.o ldt.o dumpstack.o obj-y += setup.o i8259.o irqinit_$(BITS).o setup_percpu.o obj-$(CONFIG_X86_VISWS) += visws_quirks.o obj-$(CONFIG_X86_32) += probe_roms_32.o @@ -40,7 +42,7 @@ obj-$(CONFIG_X86_TRAMPOLINE) += trampoline.o obj-y += process.o obj-y += i387.o xsave.o obj-y += ptrace.o -obj-y += ds.o +obj-$(CONFIG_X86_DS) += ds.o obj-$(CONFIG_X86_32) += tls.o obj-$(CONFIG_IA32_EMULATION) += tls.o obj-y += step.o @@ -104,6 +106,8 @@ microcode-$(CONFIG_MICROCODE_INTEL) += microcode_intel.o microcode-$(CONFIG_MICROCODE_AMD) += microcode_amd.o obj-$(CONFIG_MICROCODE) += microcode.o +obj-$(CONFIG_X86_CHECK_BIOS_CORRUPTION) += check.o + ### # 64 bit specific files ifeq ($(CONFIG_X86_64),y) diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 8c1f76abae9e..65d0b72777ea 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1343,7 +1343,6 @@ static void __init acpi_process_madt(void) error = acpi_parse_madt_ioapic_entries(); if (!error) { acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC; - acpi_irq_balance_set(NULL); acpi_ioapic = 1; smp_found_config = 1; @@ -1361,6 +1360,17 @@ static void __init acpi_process_madt(void) disable_acpi(); } } + + /* + * ACPI supports both logical (e.g. Hyper-Threading) and physical + * processors, where MPS only supports physical. + */ + if (acpi_lapic && acpi_ioapic) + printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " + "information\n"); + else if (acpi_lapic) + printk(KERN_INFO "Using ACPI for processor (LAPIC) " + "configuration information\n"); #endif return; } diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c index a8fd9ebdc8e2..0a60d60ed036 100644 --- a/arch/x86/kernel/amd_iommu.c +++ b/arch/x86/kernel/amd_iommu.c @@ -50,7 +50,7 @@ static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, /* returns !0 if the IOMMU is caching non-present entries in its TLB */ static int iommu_has_npcache(struct amd_iommu *iommu) { - return iommu->cap & IOMMU_CAP_NPCACHE; + return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); } /**************************************************************************** @@ -187,6 +187,8 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) spin_lock_irqsave(&iommu->lock, flags); ret = __iommu_queue_command(iommu, cmd); + if (!ret) + iommu->need_sync = 1; spin_unlock_irqrestore(&iommu->lock, flags); return ret; @@ -210,10 +212,13 @@ static int iommu_completion_wait(struct amd_iommu *iommu) cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); - iommu->need_sync = 0; - spin_lock_irqsave(&iommu->lock, flags); + if (!iommu->need_sync) + goto out; + + iommu->need_sync = 0; + ret = __iommu_queue_command(iommu, &cmd); if (ret) @@ -230,8 +235,9 @@ static int iommu_completion_wait(struct amd_iommu *iommu) status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); - if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit())) - printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n"); + if (unlikely(i == EXIT_LOOP_COUNT)) + panic("AMD IOMMU: Completion wait loop failed\n"); + out: spin_unlock_irqrestore(&iommu->lock, flags); @@ -254,8 +260,6 @@ static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) ret = iommu_queue_command(iommu, &cmd); - iommu->need_sync = 1; - return ret; } @@ -281,8 +285,6 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, ret = iommu_queue_command(iommu, &cmd); - iommu->need_sync = 1; - return ret; } @@ -343,7 +345,7 @@ static int iommu_map(struct protection_domain *dom, u64 __pte, *pte, *page; bus_addr = PAGE_ALIGN(bus_addr); - phys_addr = PAGE_ALIGN(bus_addr); + phys_addr = PAGE_ALIGN(phys_addr); /* only support 512GB address spaces for now */ if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) @@ -536,6 +538,9 @@ static void dma_ops_free_addresses(struct dma_ops_domain *dom, { address >>= PAGE_SHIFT; iommu_area_free(dom->bitmap, address, pages); + + if (address >= dom->next_bit) + dom->need_flush = true; } /**************************************************************************** @@ -596,7 +601,7 @@ static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom) continue; p2 = IOMMU_PTE_PAGE(p1[i]); - for (j = 0; j < 512; ++i) { + for (j = 0; j < 512; ++j) { if (!IOMMU_PTE_PRESENT(p2[j])) continue; p3 = IOMMU_PTE_PAGE(p2[j]); @@ -759,8 +764,6 @@ static void set_device_domain(struct amd_iommu *iommu, write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); iommu_queue_inv_dev_entry(iommu, devid); - - iommu->need_sync = 1; } /***************************************************************************** @@ -855,6 +858,9 @@ static int get_device_resources(struct device *dev, print_devid(_bdf, 1); } + if (domain_for_device(_bdf) == NULL) + set_device_domain(*iommu, *domain, _bdf); + return 1; } @@ -905,7 +911,7 @@ static void dma_ops_domain_unmap(struct amd_iommu *iommu, if (address >= dom->aperture_size) return; - WARN_ON(address & 0xfffULL || address > dom->aperture_size); + WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; pte += IOMMU_PTE_L0_INDEX(address); @@ -917,8 +923,8 @@ static void dma_ops_domain_unmap(struct amd_iommu *iommu, /* * This function contains common code for mapping of a physically - * contiguous memory region into DMA address space. It is uses by all - * mapping functions provided by this IOMMU driver. + * contiguous memory region into DMA address space. It is used by all + * mapping functions provided with this IOMMU driver. * Must be called with the domain lock held. */ static dma_addr_t __map_single(struct device *dev, @@ -978,7 +984,8 @@ static void __unmap_single(struct amd_iommu *iommu, dma_addr_t i, start; unsigned int pages; - if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) + if ((dma_addr == bad_dma_address) || + (dma_addr + size > dma_dom->aperture_size)) return; pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); @@ -992,8 +999,10 @@ static void __unmap_single(struct amd_iommu *iommu, dma_ops_free_addresses(dma_dom, dma_addr, pages); - if (amd_iommu_unmap_flush) + if (amd_iommu_unmap_flush || dma_dom->need_flush) { iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); + dma_dom->need_flush = false; + } } /* @@ -1026,8 +1035,7 @@ static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, if (addr == bad_dma_address) goto out; - if (unlikely(iommu->need_sync)) - iommu_completion_wait(iommu); + iommu_completion_wait(iommu); out: spin_unlock_irqrestore(&domain->lock, flags); @@ -1055,8 +1063,7 @@ static void unmap_single(struct device *dev, dma_addr_t dma_addr, __unmap_single(iommu, domain->priv, dma_addr, size, dir); - if (unlikely(iommu->need_sync)) - iommu_completion_wait(iommu); + iommu_completion_wait(iommu); spin_unlock_irqrestore(&domain->lock, flags); } @@ -1122,8 +1129,7 @@ static int map_sg(struct device *dev, struct scatterlist *sglist, goto unmap; } - if (unlikely(iommu->need_sync)) - iommu_completion_wait(iommu); + iommu_completion_wait(iommu); out: spin_unlock_irqrestore(&domain->lock, flags); @@ -1168,8 +1174,7 @@ static void unmap_sg(struct device *dev, struct scatterlist *sglist, s->dma_address = s->dma_length = 0; } - if (unlikely(iommu->need_sync)) - iommu_completion_wait(iommu); + iommu_completion_wait(iommu); spin_unlock_irqrestore(&domain->lock, flags); } @@ -1220,8 +1225,7 @@ static void *alloc_coherent(struct device *dev, size_t size, goto out; } - if (unlikely(iommu->need_sync)) - iommu_completion_wait(iommu); + iommu_completion_wait(iommu); out: spin_unlock_irqrestore(&domain->lock, flags); @@ -1252,8 +1256,7 @@ static void free_coherent(struct device *dev, size_t size, __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); - if (unlikely(iommu->need_sync)) - iommu_completion_wait(iommu); + iommu_completion_wait(iommu); spin_unlock_irqrestore(&domain->lock, flags); diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c index 0cdcda35a05f..c6cc22815d35 100644 --- a/arch/x86/kernel/amd_iommu_init.c +++ b/arch/x86/kernel/amd_iommu_init.c @@ -121,7 +121,7 @@ u16 amd_iommu_last_bdf; /* largest PCI device id we have LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings we find in ACPI */ unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ -int amd_iommu_isolate; /* if 1, device isolation is enabled */ +int amd_iommu_isolate = 1; /* if 1, device isolation is enabled */ bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the @@ -427,6 +427,10 @@ static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, &entry, sizeof(entry)); + /* set head and tail to zero manually */ + writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); + writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); + iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); return cmd_buf; @@ -1074,7 +1078,8 @@ int __init amd_iommu_init(void) goto free; /* IOMMU rlookup table - find the IOMMU for a specific device */ - amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL, + amd_iommu_rlookup_table = (void *)__get_free_pages( + GFP_KERNEL | __GFP_ZERO, get_order(rlookup_table_size)); if (amd_iommu_rlookup_table == NULL) goto free; @@ -1213,7 +1218,9 @@ static int __init parse_amd_iommu_options(char *str) for (; *str; ++str) { if (strncmp(str, "isolate", 7) == 0) amd_iommu_isolate = 1; - if (strncmp(str, "fullflush", 11) == 0) + if (strncmp(str, "share", 5) == 0) + amd_iommu_isolate = 0; + if (strncmp(str, "fullflush", 9) == 0) amd_iommu_unmap_flush = true; } diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c index 04a7f960bbc0..20c6e12c0475 100644 --- a/arch/x86/kernel/apic.c +++ b/arch/x86/kernel/apic.c @@ -441,6 +441,7 @@ static void lapic_timer_setup(enum clock_event_mode mode, v = apic_read(APIC_LVTT); v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); apic_write(APIC_LVTT, v); + apic_write(APIC_TMICT, 0xffffffff); break; case CLOCK_EVT_MODE_RESUME: /* Nothing to do here */ @@ -559,13 +560,13 @@ static int __init calibrate_by_pmtimer(long deltapm, long *delta) } else { res = (((u64)deltapm) * mult) >> 22; do_div(res, 1000000); - printk(KERN_WARNING "APIC calibration not consistent " + pr_warning("APIC calibration not consistent " "with PM Timer: %ldms instead of 100ms\n", (long)res); /* Correct the lapic counter value */ res = (((u64)(*delta)) * pm_100ms); do_div(res, deltapm); - printk(KERN_INFO "APIC delta adjusted to PM-Timer: " + pr_info("APIC delta adjusted to PM-Timer: " "%lu (%ld)\n", (unsigned long)res, *delta); *delta = (long)res; } @@ -645,8 +646,7 @@ static int __init calibrate_APIC_clock(void) */ if (calibration_result < (1000000 / HZ)) { local_irq_enable(); - printk(KERN_WARNING - "APIC frequency too slow, disabling apic timer\n"); + pr_warning("APIC frequency too slow, disabling apic timer\n"); return -1; } @@ -672,13 +672,9 @@ static int __init calibrate_APIC_clock(void) while (lapic_cal_loops <= LAPIC_CAL_LOOPS) cpu_relax(); - local_irq_disable(); - /* Stop the lapic timer */ lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); - local_irq_enable(); - /* Jiffies delta */ deltaj = lapic_cal_j2 - lapic_cal_j1; apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); @@ -692,8 +688,7 @@ static int __init calibrate_APIC_clock(void) local_irq_enable(); if (levt->features & CLOCK_EVT_FEAT_DUMMY) { - printk(KERN_WARNING - "APIC timer disabled due to verification failure.\n"); + pr_warning("APIC timer disabled due to verification failure.\n"); return -1; } @@ -714,7 +709,7 @@ void __init setup_boot_APIC_clock(void) * broadcast mechanism is used. On UP systems simply ignore it. */ if (disable_apic_timer) { - printk(KERN_INFO "Disabling APIC timer\n"); + pr_info("Disabling APIC timer\n"); /* No broadcast on UP ! */ if (num_possible_cpus() > 1) { lapic_clockevent.mult = 1; @@ -741,7 +736,7 @@ void __init setup_boot_APIC_clock(void) if (nmi_watchdog != NMI_IO_APIC) lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; else - printk(KERN_WARNING "APIC timer registered as dummy," + pr_warning("APIC timer registered as dummy," " due to nmi_watchdog=%d!\n", nmi_watchdog); /* Setup the lapic or request the broadcast */ @@ -773,8 +768,7 @@ static void local_apic_timer_interrupt(void) * spurious. */ if (!evt->event_handler) { - printk(KERN_WARNING - "Spurious LAPIC timer interrupt on cpu %d\n", cpu); + pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); /* Switch it off */ lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); return; @@ -814,9 +808,7 @@ void smp_apic_timer_interrupt(struct pt_regs *regs) * Besides, if we don't timer interrupts ignore the global * interrupt lock, which is the WrongThing (tm) to do. */ -#ifdef CONFIG_X86_64 exit_idle(); -#endif irq_enter(); local_apic_timer_interrupt(); irq_exit(); @@ -1093,7 +1085,7 @@ static void __cpuinit lapic_setup_esr(void) unsigned int oldvalue, value, maxlvt; if (!lapic_is_integrated()) { - printk(KERN_INFO "No ESR for 82489DX.\n"); + pr_info("No ESR for 82489DX.\n"); return; } @@ -1104,7 +1096,7 @@ static void __cpuinit lapic_setup_esr(void) * ESR disabled - we can't do anything useful with the * errors anyway - mbligh */ - printk(KERN_INFO "Leaving ESR disabled.\n"); + pr_info("Leaving ESR disabled.\n"); return; } @@ -1298,7 +1290,7 @@ void check_x2apic(void) rdmsr(MSR_IA32_APICBASE, msr, msr2); if (msr & X2APIC_ENABLE) { - printk("x2apic enabled by BIOS, switching to x2apic ops\n"); + pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); x2apic_preenabled = x2apic = 1; apic_ops = &x2apic_ops; } @@ -1310,12 +1302,12 @@ void enable_x2apic(void) rdmsr(MSR_IA32_APICBASE, msr, msr2); if (!(msr & X2APIC_ENABLE)) { - printk("Enabling x2apic\n"); + pr_info("Enabling x2apic\n"); wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); } } -void enable_IR_x2apic(void) +void __init enable_IR_x2apic(void) { #ifdef CONFIG_INTR_REMAP int ret; @@ -1325,9 +1317,8 @@ void enable_IR_x2apic(void) return; if (!x2apic_preenabled && disable_x2apic) { - printk(KERN_INFO - "Skipped enabling x2apic and Interrupt-remapping " - "because of nox2apic\n"); + pr_info("Skipped enabling x2apic and Interrupt-remapping " + "because of nox2apic\n"); return; } @@ -1335,22 +1326,19 @@ void enable_IR_x2apic(void) panic("Bios already enabled x2apic, can't enforce nox2apic"); if (!x2apic_preenabled && skip_ioapic_setup) { - printk(KERN_INFO - "Skipped enabling x2apic and Interrupt-remapping " - "because of skipping io-apic setup\n"); + pr_info("Skipped enabling x2apic and Interrupt-remapping " + "because of skipping io-apic setup\n"); return; } ret = dmar_table_init(); if (ret) { - printk(KERN_INFO - "dmar_table_init() failed with %d:\n", ret); + pr_info("dmar_table_init() failed with %d:\n", ret); if (x2apic_preenabled) panic("x2apic enabled by bios. But IR enabling failed"); else - printk(KERN_INFO - "Not enabling x2apic,Intr-remapping\n"); + pr_info("Not enabling x2apic,Intr-remapping\n"); return; } @@ -1359,7 +1347,7 @@ void enable_IR_x2apic(void) ret = save_mask_IO_APIC_setup(); if (ret) { - printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret); + pr_info("Saving IO-APIC state failed: %d\n", ret); goto end; } @@ -1394,14 +1382,11 @@ end: if (!ret) { if (!x2apic_preenabled) - printk(KERN_INFO - "Enabled x2apic and interrupt-remapping\n"); + pr_info("Enabled x2apic and interrupt-remapping\n"); else - printk(KERN_INFO - "Enabled Interrupt-remapping\n"); + pr_info("Enabled Interrupt-remapping\n"); } else - printk(KERN_ERR - "Failed to enable Interrupt-remapping and x2apic\n"); + pr_err("Failed to enable Interrupt-remapping and x2apic\n"); #else if (!cpu_has_x2apic) return; @@ -1410,8 +1395,8 @@ end: panic("x2apic enabled prior OS handover," " enable CONFIG_INTR_REMAP"); - printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " - " and x2apic\n"); + pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " + " and x2apic\n"); #endif return; @@ -1428,7 +1413,7 @@ end: static int __init detect_init_APIC(void) { if (!cpu_has_apic) { - printk(KERN_INFO "No local APIC present\n"); + pr_info("No local APIC present\n"); return -1; } @@ -1469,8 +1454,8 @@ static int __init detect_init_APIC(void) * "lapic" specified. */ if (!force_enable_local_apic) { - printk(KERN_INFO "Local APIC disabled by BIOS -- " - "you can enable it with \"lapic\"\n"); + pr_info("Local APIC disabled by BIOS -- " + "you can enable it with \"lapic\"\n"); return -1; } /* @@ -1480,8 +1465,7 @@ static int __init detect_init_APIC(void) */ rdmsr(MSR_IA32_APICBASE, l, h); if (!(l & MSR_IA32_APICBASE_ENABLE)) { - printk(KERN_INFO - "Local APIC disabled by BIOS -- reenabling.\n"); + pr_info("Local APIC disabled by BIOS -- reenabling.\n"); l &= ~MSR_IA32_APICBASE_BASE; l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; wrmsr(MSR_IA32_APICBASE, l, h); @@ -1494,7 +1478,7 @@ static int __init detect_init_APIC(void) */ features = cpuid_edx(1); if (!(features & (1 << X86_FEATURE_APIC))) { - printk(KERN_WARNING "Could not enable APIC!\n"); + pr_warning("Could not enable APIC!\n"); return -1; } set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); @@ -1505,14 +1489,14 @@ static int __init detect_init_APIC(void) if (l & MSR_IA32_APICBASE_ENABLE) mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; - printk(KERN_INFO "Found and enabled local APIC!\n"); + pr_info("Found and enabled local APIC!\n"); apic_pm_activate(); return 0; no_apic: - printk(KERN_INFO "No local APIC present or hardware disabled\n"); + pr_info("No local APIC present or hardware disabled\n"); return -1; } #endif @@ -1588,12 +1572,12 @@ int __init APIC_init_uniprocessor(void) { #ifdef CONFIG_X86_64 if (disable_apic) { - printk(KERN_INFO "Apic disabled\n"); + pr_info("Apic disabled\n"); return -1; } if (!cpu_has_apic) { disable_apic = 1; - printk(KERN_INFO "Apic disabled by BIOS\n"); + pr_info("Apic disabled by BIOS\n"); return -1; } #else @@ -1605,8 +1589,8 @@ int __init APIC_init_uniprocessor(void) */ if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { - printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n", - boot_cpu_physical_apicid); + pr_err("BIOS bug, local APIC 0x%x not detected!...\n", + boot_cpu_physical_apicid); clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); return -1; } @@ -1682,9 +1666,7 @@ void smp_spurious_interrupt(struct pt_regs *regs) { u32 v; -#ifdef CONFIG_X86_64 exit_idle(); -#endif irq_enter(); /* * Check if this really is a spurious interrupt and ACK it @@ -1699,8 +1681,8 @@ void smp_spurious_interrupt(struct pt_regs *regs) add_pda(irq_spurious_count, 1); #else /* see sw-dev-man vol 3, chapter 7.4.13.5 */ - printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " - "should never happen.\n", smp_processor_id()); + pr_info("spurious APIC interrupt on CPU#%d, " + "should never happen.\n", smp_processor_id()); __get_cpu_var(irq_stat).irq_spurious_count++; #endif irq_exit(); @@ -1713,9 +1695,7 @@ void smp_error_interrupt(struct pt_regs *regs) { u32 v, v1; -#ifdef CONFIG_X86_64 exit_idle(); -#endif irq_enter(); /* First tickle the hardware, only then report what went on. -- REW */ v = apic_read(APIC_ESR); @@ -1724,17 +1704,18 @@ void smp_error_interrupt(struct pt_regs *regs) ack_APIC_irq(); atomic_inc(&irq_err_count); - /* Here is what the APIC error bits mean: - 0: Send CS error - 1: Receive CS error - 2: Send accept error - 3: Receive accept error - 4: Reserved - 5: Send illegal vector - 6: Received illegal vector - 7: Illegal register address - */ - printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", + /* + * Here is what the APIC error bits mean: + * 0: Send CS error + * 1: Receive CS error + * 2: Send accept error + * 3: Receive accept error + * 4: Reserved + * 5: Send illegal vector + * 6: Received illegal vector + * 7: Illegal register address + */ + pr_debug("APIC error on CPU%d: %02x(%02x)\n", smp_processor_id(), v , v1); irq_exit(); } @@ -1838,15 +1819,15 @@ void __cpuinit generic_processor_info(int apicid, int version) * Validate version */ if (version == 0x0) { - printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " - "fixing up to 0x10. (tell your hw vendor)\n", - version); + pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " + "fixing up to 0x10. (tell your hw vendor)\n", + version); version = 0x10; } apic_version[apicid] = version; if (num_processors >= NR_CPUS) { - printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." + pr_warning("WARNING: NR_CPUS limit of %i reached." " Processor ignored.\n", NR_CPUS); return; } @@ -2209,7 +2190,7 @@ static int __init apic_set_verbosity(char *arg) else if (strcmp("verbose", arg) == 0) apic_verbosity = APIC_VERBOSE; else { - printk(KERN_WARNING "APIC Verbosity level %s not recognised" + pr_warning("APIC Verbosity level %s not recognised" " use apic=verbose or apic=debug\n", arg); return -EINVAL; } diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 5145a6e72bbb..3a26525a3f31 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -391,11 +391,7 @@ static int power_off; #else static int power_off = 1; #endif -#ifdef CONFIG_APM_REAL_MODE_POWER_OFF -static int realmode_power_off = 1; -#else static int realmode_power_off; -#endif #ifdef CONFIG_APM_ALLOW_INTS static int allow_ints = 1; #else diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c index 6649d09ad88f..ee4df08feee6 100644 --- a/arch/x86/kernel/asm-offsets_32.c +++ b/arch/x86/kernel/asm-offsets_32.c @@ -11,7 +11,7 @@ #include #include #include -#include "sigframe.h" +#include #include #include #include diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c index 7fcf63d22f8b..1d41d3f1edbc 100644 --- a/arch/x86/kernel/asm-offsets_64.c +++ b/arch/x86/kernel/asm-offsets_64.c @@ -20,6 +20,8 @@ #include +#include + #define __NO_STUBS 1 #undef __SYSCALL #undef _ASM_X86_UNISTD_64_H @@ -87,7 +89,7 @@ int main(void) BLANK(); #undef ENTRY DEFINE(IA32_RT_SIGFRAME_sigcontext, - offsetof (struct rt_sigframe32, uc.uc_mcontext)); + offsetof (struct rt_sigframe_ia32, uc.uc_mcontext)); BLANK(); #endif DEFINE(pbe_address, offsetof(struct pbe, address)); diff --git a/arch/x86/kernel/bios_uv.c b/arch/x86/kernel/bios_uv.c index f0dfe6f17e7e..2a0a2a3cac26 100644 --- a/arch/x86/kernel/bios_uv.c +++ b/arch/x86/kernel/bios_uv.c @@ -69,10 +69,10 @@ s64 uv_bios_call_reentrant(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, long sn_partition_id; EXPORT_SYMBOL_GPL(sn_partition_id); -long uv_coherency_id; -EXPORT_SYMBOL_GPL(uv_coherency_id); -long uv_region_size; -EXPORT_SYMBOL_GPL(uv_region_size); +long sn_coherency_id; +EXPORT_SYMBOL_GPL(sn_coherency_id); +long sn_region_size; +EXPORT_SYMBOL_GPL(sn_region_size); int uv_type; @@ -100,6 +100,56 @@ s64 uv_bios_get_sn_info(int fc, int *uvtype, long *partid, long *coher, return ret; } +int +uv_bios_mq_watchlist_alloc(int blade, unsigned long addr, unsigned int mq_size, + unsigned long *intr_mmr_offset) +{ + union uv_watchlist_u size_blade; + u64 watchlist; + s64 ret; + + size_blade.size = mq_size; + size_blade.blade = blade; + + /* + * bios returns watchlist number or negative error number. + */ + ret = (int)uv_bios_call_irqsave(UV_BIOS_WATCHLIST_ALLOC, addr, + size_blade.val, (u64)intr_mmr_offset, + (u64)&watchlist, 0); + if (ret < BIOS_STATUS_SUCCESS) + return ret; + + return watchlist; +} +EXPORT_SYMBOL_GPL(uv_bios_mq_watchlist_alloc); + +int +uv_bios_mq_watchlist_free(int blade, int watchlist_num) +{ + return (int)uv_bios_call_irqsave(UV_BIOS_WATCHLIST_FREE, + blade, watchlist_num, 0, 0, 0); +} +EXPORT_SYMBOL_GPL(uv_bios_mq_watchlist_free); + +s64 +uv_bios_change_memprotect(u64 paddr, u64 len, enum uv_memprotect perms) +{ + return uv_bios_call_irqsave(UV_BIOS_MEMPROTECT, paddr, len, + perms, 0, 0); +} +EXPORT_SYMBOL_GPL(uv_bios_change_memprotect); + +s64 +uv_bios_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len) +{ + s64 ret; + + ret = uv_bios_call_irqsave(UV_BIOS_GET_PARTITION_ADDR, (u64)cookie, + (u64)addr, buf, (u64)len, 0); + return ret; +} +EXPORT_SYMBOL_GPL(uv_bios_reserved_page_pa); s64 uv_bios_freq_base(u64 clock_type, u64 *ticks_per_second) { diff --git a/arch/x86/kernel/check.c b/arch/x86/kernel/check.c new file mode 100644 index 000000000000..2ac0ab71412a --- /dev/null +++ b/arch/x86/kernel/check.c @@ -0,0 +1,161 @@ +#include +#include +#include +#include +#include +#include + +/* + * Some BIOSes seem to corrupt the low 64k of memory during events + * like suspend/resume and unplugging an HDMI cable. Reserve all + * remaining free memory in that area and fill it with a distinct + * pattern. + */ +#define MAX_SCAN_AREAS 8 + +static int __read_mostly memory_corruption_check = -1; + +static unsigned __read_mostly corruption_check_size = 64*1024; +static unsigned __read_mostly corruption_check_period = 60; /* seconds */ + +static struct e820entry scan_areas[MAX_SCAN_AREAS]; +static int num_scan_areas; + + +static __init int set_corruption_check(char *arg) +{ + char *end; + + memory_corruption_check = simple_strtol(arg, &end, 10); + + return (*end == 0) ? 0 : -EINVAL; +} +early_param("memory_corruption_check", set_corruption_check); + +static __init int set_corruption_check_period(char *arg) +{ + char *end; + + corruption_check_period = simple_strtoul(arg, &end, 10); + + return (*end == 0) ? 0 : -EINVAL; +} +early_param("memory_corruption_check_period", set_corruption_check_period); + +static __init int set_corruption_check_size(char *arg) +{ + char *end; + unsigned size; + + size = memparse(arg, &end); + + if (*end == '\0') + corruption_check_size = size; + + return (size == corruption_check_size) ? 0 : -EINVAL; +} +early_param("memory_corruption_check_size", set_corruption_check_size); + + +void __init setup_bios_corruption_check(void) +{ + u64 addr = PAGE_SIZE; /* assume first page is reserved anyway */ + + if (memory_corruption_check == -1) { + memory_corruption_check = +#ifdef CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK + 1 +#else + 0 +#endif + ; + } + + if (corruption_check_size == 0) + memory_corruption_check = 0; + + if (!memory_corruption_check) + return; + + corruption_check_size = round_up(corruption_check_size, PAGE_SIZE); + + while (addr < corruption_check_size && num_scan_areas < MAX_SCAN_AREAS) { + u64 size; + addr = find_e820_area_size(addr, &size, PAGE_SIZE); + + if (addr == 0) + break; + + if ((addr + size) > corruption_check_size) + size = corruption_check_size - addr; + + if (size == 0) + break; + + e820_update_range(addr, size, E820_RAM, E820_RESERVED); + scan_areas[num_scan_areas].addr = addr; + scan_areas[num_scan_areas].size = size; + num_scan_areas++; + + /* Assume we've already mapped this early memory */ + memset(__va(addr), 0, size); + + addr += size; + } + + printk(KERN_INFO "Scanning %d areas for low memory corruption\n", + num_scan_areas); + update_e820(); +} + + +void check_for_bios_corruption(void) +{ + int i; + int corruption = 0; + + if (!memory_corruption_check) + return; + + for (i = 0; i < num_scan_areas; i++) { + unsigned long *addr = __va(scan_areas[i].addr); + unsigned long size = scan_areas[i].size; + + for (; size; addr++, size -= sizeof(unsigned long)) { + if (!*addr) + continue; + printk(KERN_ERR "Corrupted low memory at %p (%lx phys) = %08lx\n", + addr, __pa(addr), *addr); + corruption = 1; + *addr = 0; + } + } + + WARN_ONCE(corruption, KERN_ERR "Memory corruption detected in low memory\n"); +} + +static void check_corruption(struct work_struct *dummy); +static DECLARE_DELAYED_WORK(bios_check_work, check_corruption); + +static void check_corruption(struct work_struct *dummy) +{ + check_for_bios_corruption(); + schedule_delayed_work(&bios_check_work, + round_jiffies_relative(corruption_check_period*HZ)); +} + +static int start_periodic_check_for_corruption(void) +{ + if (!memory_corruption_check || corruption_check_period == 0) + return 0; + + printk(KERN_INFO "Scanning for low memory corruption every %d seconds\n", + corruption_check_period); + + /* First time we run the checks right away */ + schedule_delayed_work(&bios_check_work, 0); + return 0; +} + +module_init(start_periodic_check_for_corruption); + diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 82ec6075c057..a5c04e88777e 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -4,6 +4,7 @@ obj-y := intel_cacheinfo.o addon_cpuid_features.o obj-y += proc.o capflags.o powerflags.o common.o +obj-y += vmware.o hypervisor.o obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o obj-$(CONFIG_X86_64) += bugs_64.o diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c index 0d9c993aa93e..ef8f831af823 100644 --- a/arch/x86/kernel/cpu/addon_cpuid_features.c +++ b/arch/x86/kernel/cpu/addon_cpuid_features.c @@ -69,7 +69,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) */ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c) { -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_SMP unsigned int eax, ebx, ecx, edx, sub_index; unsigned int ht_mask_width, core_plus_mask_width; unsigned int core_select_mask, core_level_siblings; diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 25581dcb280e..42e0853030cb 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -20,6 +20,7 @@ #include #include #include +#include #ifdef CONFIG_X86_LOCAL_APIC #include #include @@ -35,6 +36,7 @@ #include #include #include +#include #include "cpu.h" @@ -549,6 +551,10 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) this_cpu->c_early_init(c); validate_pat_support(c); + +#ifdef CONFIG_SMP + c->cpu_index = boot_cpu_id; +#endif } void __init early_cpu_init(void) @@ -698,6 +704,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) detect_ht(c); #endif + init_hypervisor(c); /* * On SMP, boot_cpu_data holds the common feature set between * all CPUs; so make sure that we indicate which features are @@ -857,7 +864,7 @@ EXPORT_SYMBOL(_cpu_pda); struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; -char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; +static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; void __cpuinit pda_init(int cpu) { @@ -898,8 +905,8 @@ void __cpuinit pda_init(int cpu) } } -char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + - DEBUG_STKSZ] __page_aligned_bss; +static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + + DEBUG_STKSZ] __page_aligned_bss; extern asmlinkage void ignore_sysret(void); @@ -1134,7 +1141,7 @@ void __cpuinit cpu_init(void) /* * Boot processor to setup the FP and extended state context info. */ - if (!smp_processor_id()) + if (smp_processor_id() == boot_cpu_id) init_thread_xstate(); xsave_init(); diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index d3dcd58b87cd..7f05f44b97e9 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c @@ -115,9 +115,20 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data) u32 i = 0; if (cpu_family == CPU_HW_PSTATE) { - rdmsr(MSR_PSTATE_STATUS, lo, hi); - i = lo & HW_PSTATE_MASK; - data->currpstate = i; + if (data->currpstate == HW_PSTATE_INVALID) { + /* read (initial) hw pstate if not yet set */ + rdmsr(MSR_PSTATE_STATUS, lo, hi); + i = lo & HW_PSTATE_MASK; + + /* + * a workaround for family 11h erratum 311 might cause + * an "out-of-range Pstate if the core is in Pstate-0 + */ + if (i >= data->numps) + data->currpstate = HW_PSTATE_0; + else + data->currpstate = i; + } return 0; } do { @@ -1121,6 +1132,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) } data->cpu = pol->cpu; + data->currpstate = HW_PSTATE_INVALID; if (powernow_k8_cpu_init_acpi(data)) { /* diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h index ab48cfed4d96..65cfb5d7f77f 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h @@ -5,6 +5,19 @@ * http://www.gnu.org/licenses/gpl.html */ + +enum pstate { + HW_PSTATE_INVALID = 0xff, + HW_PSTATE_0 = 0, + HW_PSTATE_1 = 1, + HW_PSTATE_2 = 2, + HW_PSTATE_3 = 3, + HW_PSTATE_4 = 4, + HW_PSTATE_5 = 5, + HW_PSTATE_6 = 6, + HW_PSTATE_7 = 7, +}; + struct powernow_k8_data { unsigned int cpu; @@ -23,7 +36,9 @@ struct powernow_k8_data { u32 exttype; /* extended interface = 1 */ /* keep track of the current fid / vid or pstate */ - u32 currvid, currfid, currpstate; + u32 currvid; + u32 currfid; + enum pstate currpstate; /* the powernow_table includes all frequency and vid/fid pairings: * fid are the lower 8 bits of the index, vid are the upper 8 bits. diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c new file mode 100644 index 000000000000..fb5b86af0b01 --- /dev/null +++ b/arch/x86/kernel/cpu/hypervisor.c @@ -0,0 +1,58 @@ +/* + * Common hypervisor code + * + * Copyright (C) 2008, VMware, Inc. + * Author : Alok N Kataria + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include +#include +#include + +static inline void __cpuinit +detect_hypervisor_vendor(struct cpuinfo_x86 *c) +{ + if (vmware_platform()) { + c->x86_hyper_vendor = X86_HYPER_VENDOR_VMWARE; + } else { + c->x86_hyper_vendor = X86_HYPER_VENDOR_NONE; + } +} + +unsigned long get_hypervisor_tsc_freq(void) +{ + if (boot_cpu_data.x86_hyper_vendor == X86_HYPER_VENDOR_VMWARE) + return vmware_get_tsc_khz(); + return 0; +} + +static inline void __cpuinit +hypervisor_set_feature_bits(struct cpuinfo_x86 *c) +{ + if (boot_cpu_data.x86_hyper_vendor == X86_HYPER_VENDOR_VMWARE) { + vmware_set_feature_bits(c); + return; + } +} + +void __cpuinit init_hypervisor(struct cpuinfo_x86 *c) +{ + detect_hypervisor_vendor(c); + hypervisor_set_feature_bits(c); +} diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index cce0b6118d55..816f27f289b1 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -307,12 +307,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_P4); if (c->x86 == 6) set_cpu_cap(c, X86_FEATURE_P3); +#endif if (cpu_has_bts) ptrace_bts_init_intel(c); -#endif - detect_extended_topology(c); if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { /* diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 3f46afbb1cf1..68b5d8681cbb 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -644,20 +644,17 @@ static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf) return show_shared_cpu_map_func(leaf, 1, buf); } -static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) { - switch(this_leaf->eax.split.type) { - case CACHE_TYPE_DATA: +static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) +{ + switch (this_leaf->eax.split.type) { + case CACHE_TYPE_DATA: return sprintf(buf, "Data\n"); - break; - case CACHE_TYPE_INST: + case CACHE_TYPE_INST: return sprintf(buf, "Instruction\n"); - break; - case CACHE_TYPE_UNIFIED: + case CACHE_TYPE_UNIFIED: return sprintf(buf, "Unified\n"); - break; - default: + default: return sprintf(buf, "Unknown\n"); - break; } } diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c index 4b031a4ac856..1c838032fd37 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_64.c @@ -510,12 +510,9 @@ static void __cpuinit mce_cpu_features(struct cpuinfo_x86 *c) */ void __cpuinit mcheck_init(struct cpuinfo_x86 *c) { - static cpumask_t mce_cpus = CPU_MASK_NONE; - mce_cpu_quirks(c); if (mce_dont_init || - cpu_test_and_set(smp_processor_id(), mce_cpus) || !mce_available(c)) return; diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c index c78c04821ea1..1159e269e596 100644 --- a/arch/x86/kernel/cpu/mtrr/main.c +++ b/arch/x86/kernel/cpu/mtrr/main.c @@ -803,6 +803,7 @@ x86_get_mtrr_mem_range(struct res_range *range, int nr_range, } static struct res_range __initdata range[RANGE_NUM]; +static int __initdata nr_range; #ifdef CONFIG_MTRR_SANITIZER @@ -1206,39 +1207,43 @@ struct mtrr_cleanup_result { #define PSHIFT (PAGE_SHIFT - 10) static struct mtrr_cleanup_result __initdata result[NUM_RESULT]; -static struct res_range __initdata range_new[RANGE_NUM]; static unsigned long __initdata min_loss_pfn[RANGE_NUM]; -static int __init mtrr_cleanup(unsigned address_bits) +static void __init print_out_mtrr_range_state(void) { - unsigned long extra_remove_base, extra_remove_size; - unsigned long base, size, def, dummy; - mtrr_type type; - int nr_range, nr_range_new; - u64 chunk_size, gran_size; - unsigned long range_sums, range_sums_new; - int index_good; - int num_reg_good; int i; + char start_factor = 'K', size_factor = 'K'; + unsigned long start_base, size_base; + mtrr_type type; - /* extra one for all 0 */ - int num[MTRR_NUM_TYPES + 1]; + for (i = 0; i < num_var_ranges; i++) { - if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) - return 0; - rdmsr(MTRRdefType_MSR, def, dummy); - def &= 0xff; - if (def != MTRR_TYPE_UNCACHABLE) - return 0; + size_base = range_state[i].size_pfn << (PAGE_SHIFT - 10); + if (!size_base) + continue; - /* get it and store it aside */ - memset(range_state, 0, sizeof(range_state)); - for (i = 0; i < num_var_ranges; i++) { - mtrr_if->get(i, &base, &size, &type); - range_state[i].base_pfn = base; - range_state[i].size_pfn = size; - range_state[i].type = type; + size_base = to_size_factor(size_base, &size_factor), + start_base = range_state[i].base_pfn << (PAGE_SHIFT - 10); + start_base = to_size_factor(start_base, &start_factor), + type = range_state[i].type; + + printk(KERN_DEBUG "reg %d, base: %ld%cB, range: %ld%cB, type %s\n", + i, start_base, start_factor, + size_base, size_factor, + (type == MTRR_TYPE_UNCACHABLE) ? "UC" : + ((type == MTRR_TYPE_WRPROT) ? "WP" : + ((type == MTRR_TYPE_WRBACK) ? "WB" : "Other")) + ); } +} + +static int __init mtrr_need_cleanup(void) +{ + int i; + mtrr_type type; + unsigned long size; + /* extra one for all 0 */ + int num[MTRR_NUM_TYPES + 1]; /* check entries number */ memset(num, 0, sizeof(num)); @@ -1263,29 +1268,133 @@ static int __init mtrr_cleanup(unsigned address_bits) num_var_ranges - num[MTRR_NUM_TYPES]) return 0; - /* print original var MTRRs at first, for debugging: */ - printk(KERN_DEBUG "original variable MTRRs\n"); - for (i = 0; i < num_var_ranges; i++) { - char start_factor = 'K', size_factor = 'K'; - unsigned long start_base, size_base; + return 1; +} - size_base = range_state[i].size_pfn << (PAGE_SHIFT - 10); - if (!size_base) - continue; +static unsigned long __initdata range_sums; +static void __init mtrr_calc_range_state(u64 chunk_size, u64 gran_size, + unsigned long extra_remove_base, + unsigned long extra_remove_size, + int i) +{ + int num_reg; + static struct res_range range_new[RANGE_NUM]; + static int nr_range_new; + unsigned long range_sums_new; + + /* convert ranges to var ranges state */ + num_reg = x86_setup_var_mtrrs(range, nr_range, + chunk_size, gran_size); + + /* we got new setting in range_state, check it */ + memset(range_new, 0, sizeof(range_new)); + nr_range_new = x86_get_mtrr_mem_range(range_new, 0, + extra_remove_base, extra_remove_size); + range_sums_new = sum_ranges(range_new, nr_range_new); + + result[i].chunk_sizek = chunk_size >> 10; + result[i].gran_sizek = gran_size >> 10; + result[i].num_reg = num_reg; + if (range_sums < range_sums_new) { + result[i].lose_cover_sizek = + (range_sums_new - range_sums) << PSHIFT; + result[i].bad = 1; + } else + result[i].lose_cover_sizek = + (range_sums - range_sums_new) << PSHIFT; - size_base = to_size_factor(size_base, &size_factor), - start_base = range_state[i].base_pfn << (PAGE_SHIFT - 10); - start_base = to_size_factor(start_base, &start_factor), - type = range_state[i].type; + /* double check it */ + if (!result[i].bad && !result[i].lose_cover_sizek) { + if (nr_range_new != nr_range || + memcmp(range, range_new, sizeof(range))) + result[i].bad = 1; + } - printk(KERN_DEBUG "reg %d, base: %ld%cB, range: %ld%cB, type %s\n", - i, start_base, start_factor, - size_base, size_factor, - (type == MTRR_TYPE_UNCACHABLE) ? "UC" : - ((type == MTRR_TYPE_WRPROT) ? "WP" : - ((type == MTRR_TYPE_WRBACK) ? "WB" : "Other")) - ); + if (!result[i].bad && (range_sums - range_sums_new < + min_loss_pfn[num_reg])) { + min_loss_pfn[num_reg] = + range_sums - range_sums_new; } +} + +static void __init mtrr_print_out_one_result(int i) +{ + char gran_factor, chunk_factor, lose_factor; + unsigned long gran_base, chunk_base, lose_base; + + gran_base = to_size_factor(result[i].gran_sizek, &gran_factor), + chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor), + lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor), + printk(KERN_INFO "%sgran_size: %ld%c \tchunk_size: %ld%c \t", + result[i].bad ? "*BAD*" : " ", + gran_base, gran_factor, chunk_base, chunk_factor); + printk(KERN_CONT "num_reg: %d \tlose cover RAM: %s%ld%c\n", + result[i].num_reg, result[i].bad ? "-" : "", + lose_base, lose_factor); +} + +static int __init mtrr_search_optimal_index(void) +{ + int i; + int num_reg_good; + int index_good; + + if (nr_mtrr_spare_reg >= num_var_ranges) + nr_mtrr_spare_reg = num_var_ranges - 1; + num_reg_good = -1; + for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) { + if (!min_loss_pfn[i]) + num_reg_good = i; + } + + index_good = -1; + if (num_reg_good != -1) { + for (i = 0; i < NUM_RESULT; i++) { + if (!result[i].bad && + result[i].num_reg == num_reg_good && + !result[i].lose_cover_sizek) { + index_good = i; + break; + } + } + } + + return index_good; +} + + +static int __init mtrr_cleanup(unsigned address_bits) +{ + unsigned long extra_remove_base, extra_remove_size; + unsigned long base, size, def, dummy; + mtrr_type type; + u64 chunk_size, gran_size; + int index_good; + int i; + + if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) + return 0; + rdmsr(MTRRdefType_MSR, def, dummy); + def &= 0xff; + if (def != MTRR_TYPE_UNCACHABLE) + return 0; + + /* get it and store it aside */ + memset(range_state, 0, sizeof(range_state)); + for (i = 0; i < num_var_ranges; i++) { + mtrr_if->get(i, &base, &size, &type); + range_state[i].base_pfn = base; + range_state[i].size_pfn = size; + range_state[i].type = type; + } + + /* check if we need handle it and can handle it */ + if (!mtrr_need_cleanup()) + return 0; + + /* print original var MTRRs at first, for debugging: */ + printk(KERN_DEBUG "original variable MTRRs\n"); + print_out_mtrr_range_state(); memset(range, 0, sizeof(range)); extra_remove_size = 0; @@ -1309,176 +1418,64 @@ static int __init mtrr_cleanup(unsigned address_bits) range_sums >> (20 - PAGE_SHIFT)); if (mtrr_chunk_size && mtrr_gran_size) { - int num_reg; - char gran_factor, chunk_factor, lose_factor; - unsigned long gran_base, chunk_base, lose_base; - - debug_print++; - /* convert ranges to var ranges state */ - num_reg = x86_setup_var_mtrrs(range, nr_range, mtrr_chunk_size, - mtrr_gran_size); + i = 0; + mtrr_calc_range_state(mtrr_chunk_size, mtrr_gran_size, + extra_remove_base, extra_remove_size, i); - /* we got new setting in range_state, check it */ - memset(range_new, 0, sizeof(range_new)); - nr_range_new = x86_get_mtrr_mem_range(range_new, 0, - extra_remove_base, - extra_remove_size); - range_sums_new = sum_ranges(range_new, nr_range_new); + mtrr_print_out_one_result(i); - i = 0; - result[i].chunk_sizek = mtrr_chunk_size >> 10; - result[i].gran_sizek = mtrr_gran_size >> 10; - result[i].num_reg = num_reg; - if (range_sums < range_sums_new) { - result[i].lose_cover_sizek = - (range_sums_new - range_sums) << PSHIFT; - result[i].bad = 1; - } else - result[i].lose_cover_sizek = - (range_sums - range_sums_new) << PSHIFT; - - gran_base = to_size_factor(result[i].gran_sizek, &gran_factor), - chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor), - lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor), - printk(KERN_INFO "%sgran_size: %ld%c \tchunk_size: %ld%c \t", - result[i].bad?"*BAD*":" ", - gran_base, gran_factor, chunk_base, chunk_factor); - printk(KERN_CONT "num_reg: %d \tlose cover RAM: %s%ld%c\n", - result[i].num_reg, result[i].bad?"-":"", - lose_base, lose_factor); if (!result[i].bad) { set_var_mtrr_all(address_bits); return 1; } printk(KERN_INFO "invalid mtrr_gran_size or mtrr_chunk_size, " "will find optimal one\n"); - debug_print--; - memset(result, 0, sizeof(result[0])); } i = 0; memset(min_loss_pfn, 0xff, sizeof(min_loss_pfn)); memset(result, 0, sizeof(result)); for (gran_size = (1ULL<<16); gran_size < (1ULL<<32); gran_size <<= 1) { - char gran_factor; - unsigned long gran_base; - - if (debug_print) - gran_base = to_size_factor(gran_size >> 10, &gran_factor); for (chunk_size = gran_size; chunk_size < (1ULL<<32); chunk_size <<= 1) { - int num_reg; - if (debug_print) { - char chunk_factor; - unsigned long chunk_base; - - chunk_base = to_size_factor(chunk_size>>10, &chunk_factor), - printk(KERN_INFO "\n"); - printk(KERN_INFO "gran_size: %ld%c chunk_size: %ld%c \n", - gran_base, gran_factor, chunk_base, chunk_factor); - } if (i >= NUM_RESULT) continue; - /* convert ranges to var ranges state */ - num_reg = x86_setup_var_mtrrs(range, nr_range, - chunk_size, gran_size); - - /* we got new setting in range_state, check it */ - memset(range_new, 0, sizeof(range_new)); - nr_range_new = x86_get_mtrr_mem_range(range_new, 0, - extra_remove_base, extra_remove_size); - range_sums_new = sum_ranges(range_new, nr_range_new); - - result[i].chunk_sizek = chunk_size >> 10; - result[i].gran_sizek = gran_size >> 10; - result[i].num_reg = num_reg; - if (range_sums < range_sums_new) { - result[i].lose_cover_sizek = - (range_sums_new - range_sums) << PSHIFT; - result[i].bad = 1; - } else - result[i].lose_cover_sizek = - (range_sums - range_sums_new) << PSHIFT; - - /* double check it */ - if (!result[i].bad && !result[i].lose_cover_sizek) { - if (nr_range_new != nr_range || - memcmp(range, range_new, sizeof(range))) - result[i].bad = 1; + mtrr_calc_range_state(chunk_size, gran_size, + extra_remove_base, extra_remove_size, i); + if (debug_print) { + mtrr_print_out_one_result(i); + printk(KERN_INFO "\n"); } - if (!result[i].bad && (range_sums - range_sums_new < - min_loss_pfn[num_reg])) { - min_loss_pfn[num_reg] = - range_sums - range_sums_new; - } i++; } } - /* print out all */ - for (i = 0; i < NUM_RESULT; i++) { - char gran_factor, chunk_factor, lose_factor; - unsigned long gran_base, chunk_base, lose_base; - - gran_base = to_size_factor(result[i].gran_sizek, &gran_factor), - chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor), - lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor), - printk(KERN_INFO "%sgran_size: %ld%c \tchunk_size: %ld%c \t", - result[i].bad?"*BAD*":" ", - gran_base, gran_factor, chunk_base, chunk_factor); - printk(KERN_CONT "num_reg: %d \tlose cover RAM: %s%ld%c\n", - result[i].num_reg, result[i].bad?"-":"", - lose_base, lose_factor); - } - /* try to find the optimal index */ - if (nr_mtrr_spare_reg >= num_var_ranges) - nr_mtrr_spare_reg = num_var_ranges - 1; - num_reg_good = -1; - for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) { - if (!min_loss_pfn[i]) - num_reg_good = i; - } - - index_good = -1; - if (num_reg_good != -1) { - for (i = 0; i < NUM_RESULT; i++) { - if (!result[i].bad && - result[i].num_reg == num_reg_good && - !result[i].lose_cover_sizek) { - index_good = i; - break; - } - } - } + index_good = mtrr_search_optimal_index(); if (index_good != -1) { - char gran_factor, chunk_factor, lose_factor; - unsigned long gran_base, chunk_base, lose_base; - printk(KERN_INFO "Found optimal setting for mtrr clean up\n"); i = index_good; - gran_base = to_size_factor(result[i].gran_sizek, &gran_factor), - chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor), - lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor), - printk(KERN_INFO "gran_size: %ld%c \tchunk_size: %ld%c \t", - gran_base, gran_factor, chunk_base, chunk_factor); - printk(KERN_CONT "num_reg: %d \tlose RAM: %ld%c\n", - result[i].num_reg, lose_base, lose_factor); + mtrr_print_out_one_result(i); + /* convert ranges to var ranges state */ chunk_size = result[i].chunk_sizek; chunk_size <<= 10; gran_size = result[i].gran_sizek; gran_size <<= 10; - debug_print++; x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size); - debug_print--; set_var_mtrr_all(address_bits); + printk(KERN_DEBUG "New variable MTRRs\n"); + print_out_mtrr_range_state(); return 1; + } else { + /* print out all */ + for (i = 0; i < NUM_RESULT; i++) + mtrr_print_out_one_result(i); } printk(KERN_INFO "mtrr_cleanup: can not find optimal value\n"); @@ -1562,7 +1559,6 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) { unsigned long i, base, size, highest_pfn = 0, def, dummy; mtrr_type type; - int nr_range; u64 total_trim_size; /* extra one for all 0 */ diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c new file mode 100644 index 000000000000..284c399e3234 --- /dev/null +++ b/arch/x86/kernel/cpu/vmware.c @@ -0,0 +1,112 @@ +/* + * VMware Detection code. + * + * Copyright (C) 2008, VMware, Inc. + * Author : Alok N Kataria + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include +#include +#include + +#define CPUID_VMWARE_INFO_LEAF 0x40000000 +#define VMWARE_HYPERVISOR_MAGIC 0x564D5868 +#define VMWARE_HYPERVISOR_PORT 0x5658 + +#define VMWARE_PORT_CMD_GETVERSION 10 +#define VMWARE_PORT_CMD_GETHZ 45 + +#define VMWARE_PORT(cmd, eax, ebx, ecx, edx) \ + __asm__("inl (%%dx)" : \ + "=a"(eax), "=c"(ecx), "=d"(edx), "=b"(ebx) : \ + "0"(VMWARE_HYPERVISOR_MAGIC), \ + "1"(VMWARE_PORT_CMD_##cmd), \ + "2"(VMWARE_HYPERVISOR_PORT), "3"(UINT_MAX) : \ + "memory"); + +static inline int __vmware_platform(void) +{ + uint32_t eax, ebx, ecx, edx; + VMWARE_PORT(GETVERSION, eax, ebx, ecx, edx); + return eax != (uint32_t)-1 && ebx == VMWARE_HYPERVISOR_MAGIC; +} + +static unsigned long __vmware_get_tsc_khz(void) +{ + uint64_t tsc_hz; + uint32_t eax, ebx, ecx, edx; + + VMWARE_PORT(GETHZ, eax, ebx, ecx, edx); + + if (ebx == UINT_MAX) + return 0; + tsc_hz = eax | (((uint64_t)ebx) << 32); + do_div(tsc_hz, 1000); + BUG_ON(tsc_hz >> 32); + return tsc_hz; +} + +/* + * While checking the dmi string infomation, just checking the product + * serial key should be enough, as this will always have a VMware + * specific string when running under VMware hypervisor. + */ +int vmware_platform(void) +{ + if (cpu_has_hypervisor) { + unsigned int eax, ebx, ecx, edx; + char hyper_vendor_id[13]; + + cpuid(CPUID_VMWARE_INFO_LEAF, &eax, &ebx, &ecx, &edx); + memcpy(hyper_vendor_id + 0, &ebx, 4); + memcpy(hyper_vendor_id + 4, &ecx, 4); + memcpy(hyper_vendor_id + 8, &edx, 4); + hyper_vendor_id[12] = '\0'; + if (!strcmp(hyper_vendor_id, "VMwareVMware")) + return 1; + } else if (dmi_available && dmi_name_in_serial("VMware") && + __vmware_platform()) + return 1; + + return 0; +} + +unsigned long vmware_get_tsc_khz(void) +{ + BUG_ON(!vmware_platform()); + return __vmware_get_tsc_khz(); +} + +/* + * VMware hypervisor takes care of exporting a reliable TSC to the guest. + * Still, due to timing difference when running on virtual cpus, the TSC can + * be marked as unstable in some cases. For example, the TSC sync check at + * bootup can fail due to a marginal offset between vcpus' TSCs (though the + * TSCs do not drift from each other). Also, the ACPI PM timer clocksource + * is not suitable as a watchdog when running on a hypervisor because the + * kernel may miss a wrap of the counter if the vcpu is descheduled for a + * long time. To skip these checks at runtime we set these capability bits, + * so that the kernel could just trust the hypervisor with providing a + * reliable virtual TSC that is suitable for timekeeping. + */ +void __cpuinit vmware_set_feature_bits(struct cpuinfo_x86 *c) +{ + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE); +} diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index 268553817909..d84a852e4cd7 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -29,34 +29,17 @@ #include -/* This keeps a track of which one is crashing cpu. */ -static int crashing_cpu; #if defined(CONFIG_SMP) && defined(CONFIG_X86_LOCAL_APIC) -static atomic_t waiting_for_crash_ipi; -static int crash_nmi_callback(struct notifier_block *self, - unsigned long val, void *data) +static void kdump_nmi_callback(int cpu, struct die_args *args) { struct pt_regs *regs; #ifdef CONFIG_X86_32 struct pt_regs fixed_regs; #endif - int cpu; - if (val != DIE_NMI_IPI) - return NOTIFY_OK; - - regs = ((struct die_args *)data)->regs; - cpu = raw_smp_processor_id(); - - /* Don't do anything if this handler is invoked on crashing cpu. - * Otherwise, system will completely hang. Crashing cpu can get - * an NMI if system was initially booted with nmi_watchdog parameter. - */ - if (cpu == crashing_cpu) - return NOTIFY_STOP; - local_irq_disable(); + regs = args->regs; #ifdef CONFIG_X86_32 if (!user_mode_vm(regs)) { @@ -65,54 +48,19 @@ static int crash_nmi_callback(struct notifier_block *self, } #endif crash_save_cpu(regs, cpu); - disable_local_APIC(); - atomic_dec(&waiting_for_crash_ipi); - /* Assume hlt works */ - halt(); - for (;;) - cpu_relax(); - - return 1; -} -static void smp_send_nmi_allbutself(void) -{ - cpumask_t mask = cpu_online_map; - cpu_clear(safe_smp_processor_id(), mask); - if (!cpus_empty(mask)) - send_IPI_mask(mask, NMI_VECTOR); + disable_local_APIC(); } -static struct notifier_block crash_nmi_nb = { - .notifier_call = crash_nmi_callback, -}; - -static void nmi_shootdown_cpus(void) +static void kdump_nmi_shootdown_cpus(void) { - unsigned long msecs; - - atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); - /* Would it be better to replace the trap vector here? */ - if (register_die_notifier(&crash_nmi_nb)) - return; /* return what? */ - /* Ensure the new callback function is set before sending - * out the NMI - */ - wmb(); + nmi_shootdown_cpus(kdump_nmi_callback); - smp_send_nmi_allbutself(); - - msecs = 1000; /* Wait at most a second for the other cpus to stop */ - while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) { - mdelay(1); - msecs--; - } - - /* Leave the nmi callback set */ disable_local_APIC(); } + #else -static void nmi_shootdown_cpus(void) +static void kdump_nmi_shootdown_cpus(void) { /* There are no cpus to shootdown */ } @@ -131,9 +79,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs) /* The kernel is broken so disable interrupts */ local_irq_disable(); - /* Make a note of crashing cpu. Will be used in NMI callback.*/ - crashing_cpu = safe_smp_processor_id(); - nmi_shootdown_cpus(); + kdump_nmi_shootdown_cpus(); lapic_shutdown(); #if defined(CONFIG_X86_IO_APIC) disable_IO_APIC(); diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c index 2b69994fd3a8..d6938d9351cf 100644 --- a/arch/x86/kernel/ds.c +++ b/arch/x86/kernel/ds.c @@ -21,8 +21,6 @@ */ -#ifdef CONFIG_X86_DS - #include #include @@ -211,14 +209,15 @@ static DEFINE_PER_CPU(struct ds_context *, system_context); static inline struct ds_context *ds_get_context(struct task_struct *task) { struct ds_context *context; + unsigned long irq; - spin_lock(&ds_lock); + spin_lock_irqsave(&ds_lock, irq); context = (task ? task->thread.ds_ctx : this_system_context); if (context) context->count++; - spin_unlock(&ds_lock); + spin_unlock_irqrestore(&ds_lock, irq); return context; } @@ -226,18 +225,16 @@ static inline struct ds_context *ds_get_context(struct task_struct *task) /* * Same as ds_get_context, but allocates the context and it's DS * structure, if necessary; returns NULL; if out of memory. - * - * pre: requires ds_lock to be held */ static inline struct ds_context *ds_alloc_context(struct task_struct *task) { struct ds_context **p_context = (task ? &task->thread.ds_ctx : &this_system_context); struct ds_context *context = *p_context; + unsigned long irq; if (!context) { context = kzalloc(sizeof(*context), GFP_KERNEL); - if (!context) return NULL; @@ -247,18 +244,27 @@ static inline struct ds_context *ds_alloc_context(struct task_struct *task) return NULL; } - *p_context = context; + spin_lock_irqsave(&ds_lock, irq); - context->this = p_context; - context->task = task; + if (*p_context) { + kfree(context->ds); + kfree(context); - if (task) - set_tsk_thread_flag(task, TIF_DS_AREA_MSR); + context = *p_context; + } else { + *p_context = context; - if (!task || (task == current)) - wrmsr(MSR_IA32_DS_AREA, (unsigned long)context->ds, 0); + context->this = p_context; + context->task = task; - get_tracer(task); + if (task) + set_tsk_thread_flag(task, TIF_DS_AREA_MSR); + + if (!task || (task == current)) + wrmsrl(MSR_IA32_DS_AREA, + (unsigned long)context->ds); + } + spin_unlock_irqrestore(&ds_lock, irq); } context->count++; @@ -272,10 +278,12 @@ static inline struct ds_context *ds_alloc_context(struct task_struct *task) */ static inline void ds_put_context(struct ds_context *context) { + unsigned long irq; + if (!context) return; - spin_lock(&ds_lock); + spin_lock_irqsave(&ds_lock, irq); if (--context->count) goto out; @@ -297,7 +305,7 @@ static inline void ds_put_context(struct ds_context *context) kfree(context->ds); kfree(context); out: - spin_unlock(&ds_lock); + spin_unlock_irqrestore(&ds_lock, irq); } @@ -368,6 +376,7 @@ static int ds_request(struct task_struct *task, void *base, size_t size, struct ds_context *context; unsigned long buffer, adj; const unsigned long alignment = (1 << 3); + unsigned long irq; int error = 0; if (!ds_cfg.sizeof_ds) @@ -382,25 +391,27 @@ static int ds_request(struct task_struct *task, void *base, size_t size, return -EOPNOTSUPP; - spin_lock(&ds_lock); - - if (!check_tracer(task)) - return -EPERM; - - error = -ENOMEM; context = ds_alloc_context(task); if (!context) + return -ENOMEM; + + spin_lock_irqsave(&ds_lock, irq); + + error = -EPERM; + if (!check_tracer(task)) goto out_unlock; + get_tracer(task); + error = -EALREADY; if (context->owner[qual] == current) - goto out_unlock; + goto out_put_tracer; error = -EPERM; if (context->owner[qual] != NULL) - goto out_unlock; + goto out_put_tracer; context->owner[qual] = current; - spin_unlock(&ds_lock); + spin_unlock_irqrestore(&ds_lock, irq); error = -ENOMEM; @@ -448,10 +459,17 @@ static int ds_request(struct task_struct *task, void *base, size_t size, out_release: context->owner[qual] = NULL; ds_put_context(context); + put_tracer(task); + return error; + + out_put_tracer: + spin_unlock_irqrestore(&ds_lock, irq); + ds_put_context(context); + put_tracer(task); return error; out_unlock: - spin_unlock(&ds_lock); + spin_unlock_irqrestore(&ds_lock, irq); ds_put_context(context); return error; } @@ -801,13 +819,21 @@ static const struct ds_configuration ds_cfg_var = { .sizeof_ds = sizeof(long) * 12, .sizeof_field = sizeof(long), .sizeof_rec[ds_bts] = sizeof(long) * 3, +#ifdef __i386__ .sizeof_rec[ds_pebs] = sizeof(long) * 10 +#else + .sizeof_rec[ds_pebs] = sizeof(long) * 18 +#endif }; static const struct ds_configuration ds_cfg_64 = { .sizeof_ds = 8 * 12, .sizeof_field = 8, .sizeof_rec[ds_bts] = 8 * 3, +#ifdef __i386__ .sizeof_rec[ds_pebs] = 8 * 10 +#else + .sizeof_rec[ds_pebs] = 8 * 18 +#endif }; static inline void @@ -821,17 +847,16 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c) switch (c->x86) { case 0x6: switch (c->x86_model) { + case 0 ... 0xC: + /* sorry, don't know about them */ + break; case 0xD: case 0xE: /* Pentium M */ ds_configure(&ds_cfg_var); break; - case 0xF: /* Core2 */ - case 0x1C: /* Atom */ + default: /* Core2, Atom, ... */ ds_configure(&ds_cfg_64); break; - default: - /* sorry, don't know about them */ - break; } break; case 0xF: @@ -861,4 +886,3 @@ void ds_free(struct ds_context *context) while (leftovers--) ds_put_context(context); } -#endif /* CONFIG_X86_DS */ diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c new file mode 100644 index 000000000000..5962176dfabb --- /dev/null +++ b/arch/x86/kernel/dumpstack.c @@ -0,0 +1,319 @@ +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dumpstack.h" + +int panic_on_unrecovered_nmi; +unsigned int code_bytes = 64; +int kstack_depth_to_print = 3 * STACKSLOTS_PER_LINE; +static int die_counter; + +void printk_address(unsigned long address, int reliable) +{ + printk(" [<%p>] %s%pS\n", (void *) address, + reliable ? "" : "? ", (void *) address); +} + +/* + * x86-64 can have up to three kernel stacks: + * process stack + * interrupt stack + * severe exception (double fault, nmi, stack fault, debug, mce) hardware stack + */ + +static inline int valid_stack_ptr(struct thread_info *tinfo, + void *p, unsigned int size, void *end) +{ + void *t = tinfo; + if (end) { + if (p < end && p >= (end-THREAD_SIZE)) + return 1; + else + return 0; + } + return p > t && p < t + THREAD_SIZE - size; +} + +unsigned long +print_context_stack(struct thread_info *tinfo, + unsigned long *stack, unsigned long bp, + const struct stacktrace_ops *ops, void *data, + unsigned long *end) +{ + struct stack_frame *frame = (struct stack_frame *)bp; + + while (valid_stack_ptr(tinfo, stack, sizeof(*stack), end)) { + unsigned long addr; + + addr = *stack; + if (__kernel_text_address(addr)) { + if ((unsigned long) stack == bp + sizeof(long)) { + ops->address(data, addr, 1); + frame = frame->next_frame; + bp = (unsigned long) frame; + } else { + ops->address(data, addr, bp == 0); + } + } + stack++; + } + return bp; +} + + +static void +print_trace_warning_symbol(void *data, char *msg, unsigned long symbol) +{ + printk(data); + print_symbol(msg, symbol); + printk("\n"); +} + +static void print_trace_warning(void *data, char *msg) +{ + printk("%s%s\n", (char *)data, msg); +} + +static int print_trace_stack(void *data, char *name) +{ + printk("%s <%s> ", (char *)data, name); + return 0; +} + +/* + * Print one address/symbol entries per line. + */ +static void print_trace_address(void *data, unsigned long addr, int reliable) +{ + touch_nmi_watchdog(); + printk(data); + printk_address(addr, reliable); +} + +static const struct stacktrace_ops print_trace_ops = { + .warning = print_trace_warning, + .warning_symbol = print_trace_warning_symbol, + .stack = print_trace_stack, + .address = print_trace_address, +}; + +void +show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, + unsigned long *stack, unsigned long bp, char *log_lvl) +{ + printk("%sCall Trace:\n", log_lvl); + dump_trace(task, regs, stack, bp, &print_trace_ops, log_lvl); +} + +void show_trace(struct task_struct *task, struct pt_regs *regs, + unsigned long *stack, unsigned long bp) +{ + show_trace_log_lvl(task, regs, stack, bp, ""); +} + +void show_stack(struct task_struct *task, unsigned long *sp) +{ + show_stack_log_lvl(task, NULL, sp, 0, ""); +} + +/* + * The architecture-independent dump_stack generator + */ +void dump_stack(void) +{ + unsigned long bp = 0; + unsigned long stack; + +#ifdef CONFIG_FRAME_POINTER + if (!bp) + get_bp(bp); +#endif + + printk("Pid: %d, comm: %.20s %s %s %.*s\n", + current->pid, current->comm, print_tainted(), + init_utsname()->release, + (int)strcspn(init_utsname()->version, " "), + init_utsname()->version); + show_trace(NULL, NULL, &stack, bp); +} +EXPORT_SYMBOL(dump_stack); + +static raw_spinlock_t die_lock = __RAW_SPIN_LOCK_UNLOCKED; +static int die_owner = -1; +static unsigned int die_nest_count; + +unsigned __kprobes long oops_begin(void) +{ + int cpu; + unsigned long flags; + + oops_enter(); + + /* racy, but better than risking deadlock. */ + raw_local_irq_save(flags); + cpu = smp_processor_id(); + if (!__raw_spin_trylock(&die_lock)) { + if (cpu == die_owner) + /* nested oops. should stop eventually */; + else + __raw_spin_lock(&die_lock); + } + die_nest_count++; + die_owner = cpu; + console_verbose(); + bust_spinlocks(1); + return flags; +} + +void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, int signr) +{ + if (regs && kexec_should_crash(current)) + crash_kexec(regs); + + bust_spinlocks(0); + die_owner = -1; + add_taint(TAINT_DIE); + die_nest_count--; + if (!die_nest_count) + /* Nest count reaches zero, release the lock. */ + __raw_spin_unlock(&die_lock); + raw_local_irq_restore(flags); + oops_exit(); + + if (!signr) + return; + if (in_interrupt()) + panic("Fatal exception in interrupt"); + if (panic_on_oops) + panic("Fatal exception"); + do_exit(signr); +} + +int __kprobes __die(const char *str, struct pt_regs *regs, long err) +{ +#ifdef CONFIG_X86_32 + unsigned short ss; + unsigned long sp; +#endif + printk(KERN_EMERG "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter); +#ifdef CONFIG_PREEMPT + printk("PREEMPT "); +#endif +#ifdef CONFIG_SMP + printk("SMP "); +#endif +#ifdef CONFIG_DEBUG_PAGEALLOC + printk("DEBUG_PAGEALLOC"); +#endif + printk("\n"); + sysfs_printk_last_file(); + if (notify_die(DIE_OOPS, str, regs, err, + current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) + return 1; + + show_registers(regs); +#ifdef CONFIG_X86_32 + sp = (unsigned long) (®s->sp); + savesegment(ss, ss); + if (user_mode(regs)) { + sp = regs->sp; + ss = regs->ss & 0xffff; + } + printk(KERN_EMERG "EIP: [<%08lx>] ", regs->ip); + print_symbol("%s", regs->ip); + printk(" SS:ESP %04x:%08lx\n", ss, sp); +#else + /* Executive summary in case the oops scrolled away */ + printk(KERN_ALERT "RIP "); + printk_address(regs->ip, 1); + printk(" RSP <%016lx>\n", regs->sp); +#endif + return 0; +} + +/* + * This is gone through when something in the kernel has done something bad + * and is about to be terminated: + */ +void die(const char *str, struct pt_regs *regs, long err) +{ + unsigned long flags = oops_begin(); + int sig = SIGSEGV; + + if (!user_mode_vm(regs)) + report_bug(regs->ip, regs); + + if (__die(str, regs, err)) + sig = 0; + oops_end(flags, regs, sig); +} + +void notrace __kprobes +die_nmi(char *str, struct pt_regs *regs, int do_panic) +{ + unsigned long flags; + + if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) == NOTIFY_STOP) + return; + + /* + * We are in trouble anyway, lets at least try + * to get a message out. + */ + flags = oops_begin(); + printk(KERN_EMERG "%s", str); + printk(" on CPU%d, ip %08lx, registers:\n", + smp_processor_id(), regs->ip); + show_registers(regs); + oops_end(flags, regs, 0); + if (do_panic || panic_on_oops) + panic("Non maskable interrupt"); + nmi_exit(); + local_irq_enable(); + do_exit(SIGBUS); +} + +static int __init oops_setup(char *s) +{ + if (!s) + return -EINVAL; + if (!strcmp(s, "panic")) + panic_on_oops = 1; + return 0; +} +early_param("oops", oops_setup); + +static int __init kstack_setup(char *s) +{ + if (!s) + return -EINVAL; + kstack_depth_to_print = simple_strtoul(s, NULL, 0); + return 0; +} +early_param("kstack", kstack_setup); + +static int __init code_bytes_setup(char *s) +{ + code_bytes = simple_strtoul(s, NULL, 0); + if (code_bytes > 8192) + code_bytes = 8192; + + return 1; +} +__setup("code_bytes=", code_bytes_setup); diff --git a/arch/x86/kernel/dumpstack.h b/arch/x86/kernel/dumpstack.h new file mode 100644 index 000000000000..3119a801c32b --- /dev/null +++ b/arch/x86/kernel/dumpstack.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs + */ + +#ifndef DUMPSTACK_H +#define DUMPSTACK_H + +#ifdef CONFIG_X86_32 +#define STACKSLOTS_PER_LINE 8 +#define get_bp(bp) asm("movl %%ebp, %0" : "=r" (bp) :) +#else +#define STACKSLOTS_PER_LINE 4 +#define get_bp(bp) asm("movq %%rbp, %0" : "=r" (bp) :) +#endif + +extern unsigned long +print_context_stack(struct thread_info *tinfo, + unsigned long *stack, unsigned long bp, + const struct stacktrace_ops *ops, void *data, + unsigned long *end); + +extern void +show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, + unsigned long *stack, unsigned long bp, char *log_lvl); + +extern void +show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, + unsigned long *sp, unsigned long bp, char *log_lvl); + +extern unsigned int code_bytes; +extern int kstack_depth_to_print; + +/* The form of the top of the frame on the stack */ +struct stack_frame { + struct stack_frame *next_frame; + unsigned long return_address; +}; +#endif diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c index b3614752197b..7b031b106ec8 100644 --- a/arch/x86/kernel/dumpstack_32.c +++ b/arch/x86/kernel/dumpstack_32.c @@ -17,64 +17,7 @@ #include -#define STACKSLOTS_PER_LINE 8 -#define get_bp(bp) asm("movl %%ebp, %0" : "=r" (bp) :) - -int panic_on_unrecovered_nmi; -int kstack_depth_to_print = 3 * STACKSLOTS_PER_LINE; -static unsigned int code_bytes = 64; -static int die_counter; - -void printk_address(unsigned long address, int reliable) -{ - printk(" [<%p>] %s%pS\n", (void *) address, - reliable ? "" : "? ", (void *) address); -} - -static inline int valid_stack_ptr(struct thread_info *tinfo, - void *p, unsigned int size, void *end) -{ - void *t = tinfo; - if (end) { - if (p < end && p >= (end-THREAD_SIZE)) - return 1; - else - return 0; - } - return p > t && p < t + THREAD_SIZE - size; -} - -/* The form of the top of the frame on the stack */ -struct stack_frame { - struct stack_frame *next_frame; - unsigned long return_address; -}; - -static inline unsigned long -print_context_stack(struct thread_info *tinfo, - unsigned long *stack, unsigned long bp, - const struct stacktrace_ops *ops, void *data, - unsigned long *end) -{ - struct stack_frame *frame = (struct stack_frame *)bp; - - while (valid_stack_ptr(tinfo, stack, sizeof(*stack), end)) { - unsigned long addr; - - addr = *stack; - if (__kernel_text_address(addr)) { - if ((unsigned long) stack == bp + sizeof(long)) { - ops->address(data, addr, 1); - frame = frame->next_frame; - bp = (unsigned long) frame; - } else { - ops->address(data, addr, bp == 0); - } - } - stack++; - } - return bp; -} +#include "dumpstack.h" void dump_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack, unsigned long bp, @@ -119,57 +62,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs, } EXPORT_SYMBOL(dump_trace); -static void -print_trace_warning_symbol(void *data, char *msg, unsigned long symbol) -{ - printk(data); - print_symbol(msg, symbol); - printk("\n"); -} - -static void print_trace_warning(void *data, char *msg) -{ - printk("%s%s\n", (char *)data, msg); -} - -static int print_trace_stack(void *data, char *name) -{ - printk("%s <%s> ", (char *)data, name); - return 0; -} - -/* - * Print one address/symbol entries per line. - */ -static void print_trace_address(void *data, unsigned long addr, int reliable) -{ - touch_nmi_watchdog(); - printk(data); - printk_address(addr, reliable); -} - -static const struct stacktrace_ops print_trace_ops = { - .warning = print_trace_warning, - .warning_symbol = print_trace_warning_symbol, - .stack = print_trace_stack, - .address = print_trace_address, -}; - -static void -show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, - unsigned long *stack, unsigned long bp, char *log_lvl) -{ - printk("%sCall Trace:\n", log_lvl); - dump_trace(task, regs, stack, bp, &print_trace_ops, log_lvl); -} - -void show_trace(struct task_struct *task, struct pt_regs *regs, - unsigned long *stack, unsigned long bp) -{ - show_trace_log_lvl(task, regs, stack, bp, ""); -} - -static void +void show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, unsigned long *sp, unsigned long bp, char *log_lvl) { @@ -196,33 +89,6 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, show_trace_log_lvl(task, regs, sp, bp, log_lvl); } -void show_stack(struct task_struct *task, unsigned long *sp) -{ - show_stack_log_lvl(task, NULL, sp, 0, ""); -} - -/* - * The architecture-independent dump_stack generator - */ -void dump_stack(void) -{ - unsigned long bp = 0; - unsigned long stack; - -#ifdef CONFIG_FRAME_POINTER - if (!bp) - get_bp(bp); -#endif - - printk("Pid: %d, comm: %.20s %s %s %.*s\n", - current->pid, current->comm, print_tainted(), - init_utsname()->release, - (int)strcspn(init_utsname()->version, " "), - init_utsname()->version); - show_trace(NULL, NULL, &stack, bp); -} - -EXPORT_SYMBOL(dump_stack); void show_registers(struct pt_regs *regs) { @@ -283,167 +149,3 @@ int is_valid_bugaddr(unsigned long ip) return ud2 == 0x0b0f; } -static raw_spinlock_t die_lock = __RAW_SPIN_LOCK_UNLOCKED; -static int die_owner = -1; -static unsigned int die_nest_count; - -unsigned __kprobes long oops_begin(void) -{ - unsigned long flags; - - oops_enter(); - - if (die_owner != raw_smp_processor_id()) { - console_verbose(); - raw_local_irq_save(flags); - __raw_spin_lock(&die_lock); - die_owner = smp_processor_id(); - die_nest_count = 0; - bust_spinlocks(1); - } else { - raw_local_irq_save(flags); - } - die_nest_count++; - return flags; -} - -void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, int signr) -{ - bust_spinlocks(0); - die_owner = -1; - add_taint(TAINT_DIE); - __raw_spin_unlock(&die_lock); - raw_local_irq_restore(flags); - - if (!regs) - return; - - if (kexec_should_crash(current)) - crash_kexec(regs); - if (in_interrupt()) - panic("Fatal exception in interrupt"); - if (panic_on_oops) - panic("Fatal exception"); - oops_exit(); - do_exit(signr); -} - -int __kprobes __die(const char *str, struct pt_regs *regs, long err) -{ - unsigned short ss; - unsigned long sp; - - printk(KERN_EMERG "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter); -#ifdef CONFIG_PREEMPT - printk("PREEMPT "); -#endif -#ifdef CONFIG_SMP - printk("SMP "); -#endif -#ifdef CONFIG_DEBUG_PAGEALLOC - printk("DEBUG_PAGEALLOC"); -#endif - printk("\n"); - sysfs_printk_last_file(); - if (notify_die(DIE_OOPS, str, regs, err, - current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) - return 1; - - show_registers(regs); - /* Executive summary in case the oops scrolled away */ - sp = (unsigned long) (®s->sp); - savesegment(ss, ss); - if (user_mode(regs)) { - sp = regs->sp; - ss = regs->ss & 0xffff; - } - printk(KERN_EMERG "EIP: [<%08lx>] ", regs->ip); - print_symbol("%s", regs->ip); - printk(" SS:ESP %04x:%08lx\n", ss, sp); - return 0; -} - -/* - * This is gone through when something in the kernel has done something bad - * and is about to be terminated: - */ -void die(const char *str, struct pt_regs *regs, long err) -{ - unsigned long flags = oops_begin(); - - if (die_nest_count < 3) { - report_bug(regs->ip, regs); - - if (__die(str, regs, err)) - regs = NULL; - } else { - printk(KERN_EMERG "Recursive die() failure, output suppressed\n"); - } - - oops_end(flags, regs, SIGSEGV); -} - -static DEFINE_SPINLOCK(nmi_print_lock); - -void notrace __kprobes -die_nmi(char *str, struct pt_regs *regs, int do_panic) -{ - if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) == NOTIFY_STOP) - return; - - spin_lock(&nmi_print_lock); - /* - * We are in trouble anyway, lets at least try - * to get a message out: - */ - bust_spinlocks(1); - printk(KERN_EMERG "%s", str); - printk(" on CPU%d, ip %08lx, registers:\n", - smp_processor_id(), regs->ip); - show_registers(regs); - if (do_panic) - panic("Non maskable interrupt"); - console_silent(); - spin_unlock(&nmi_print_lock); - - /* - * If we are in kernel we are probably nested up pretty bad - * and might aswell get out now while we still can: - */ - if (!user_mode_vm(regs)) { - current->thread.trap_no = 2; - crash_kexec(regs); - } - - bust_spinlocks(0); - do_exit(SIGSEGV); -} - -static int __init oops_setup(char *s) -{ - if (!s) - return -EINVAL; - if (!strcmp(s, "panic")) - panic_on_oops = 1; - return 0; -} -early_param("oops", oops_setup); - -static int __init kstack_setup(char *s) -{ - if (!s) - return -EINVAL; - kstack_depth_to_print = simple_strtoul(s, NULL, 0); - return 0; -} -early_param("kstack", kstack_setup); - -static int __init code_bytes_setup(char *s) -{ - code_bytes = simple_strtoul(s, NULL, 0); - if (code_bytes > 8192) - code_bytes = 8192; - - return 1; -} -__setup("code_bytes=", code_bytes_setup); diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c index 96a5db7da8a7..33ff10287a5d 100644 --- a/arch/x86/kernel/dumpstack_64.c +++ b/arch/x86/kernel/dumpstack_64.c @@ -17,19 +17,7 @@ #include -#define STACKSLOTS_PER_LINE 4 -#define get_bp(bp) asm("movq %%rbp, %0" : "=r" (bp) :) - -int panic_on_unrecovered_nmi; -int kstack_depth_to_print = 3 * STACKSLOTS_PER_LINE; -static unsigned int code_bytes = 64; -static int die_counter; - -void printk_address(unsigned long address, int reliable) -{ - printk(" [<%p>] %s%pS\n", (void *) address, - reliable ? "" : "? ", (void *) address); -} +#include "dumpstack.h" static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack, unsigned *usedp, char **idp) @@ -113,51 +101,6 @@ static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack, * severe exception (double fault, nmi, stack fault, debug, mce) hardware stack */ -static inline int valid_stack_ptr(struct thread_info *tinfo, - void *p, unsigned int size, void *end) -{ - void *t = tinfo; - if (end) { - if (p < end && p >= (end-THREAD_SIZE)) - return 1; - else - return 0; - } - return p > t && p < t + THREAD_SIZE - size; -} - -/* The form of the top of the frame on the stack */ -struct stack_frame { - struct stack_frame *next_frame; - unsigned long return_address; -}; - -static inline unsigned long -print_context_stack(struct thread_info *tinfo, - unsigned long *stack, unsigned long bp, - const struct stacktrace_ops *ops, void *data, - unsigned long *end) -{ - struct stack_frame *frame = (struct stack_frame *)bp; - - while (valid_stack_ptr(tinfo, stack, sizeof(*stack), end)) { - unsigned long addr; - - addr = *stack; - if (__kernel_text_address(addr)) { - if ((unsigned long) stack == bp + sizeof(long)) { - ops->address(data, addr, 1); - frame = frame->next_frame; - bp = (unsigned long) frame; - } else { - ops->address(data, addr, bp == 0); - } - } - stack++; - } - return bp; -} - void dump_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack, unsigned long bp, const struct stacktrace_ops *ops, void *data) @@ -248,57 +191,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs, } EXPORT_SYMBOL(dump_trace); -static void -print_trace_warning_symbol(void *data, char *msg, unsigned long symbol) -{ - printk(data); - print_symbol(msg, symbol); - printk("\n"); -} - -static void print_trace_warning(void *data, char *msg) -{ - printk("%s%s\n", (char *)data, msg); -} - -static int print_trace_stack(void *data, char *name) -{ - printk("%s <%s> ", (char *)data, name); - return 0; -} - -/* - * Print one address/symbol entries per line. - */ -static void print_trace_address(void *data, unsigned long addr, int reliable) -{ - touch_nmi_watchdog(); - printk(data); - printk_address(addr, reliable); -} - -static const struct stacktrace_ops print_trace_ops = { - .warning = print_trace_warning, - .warning_symbol = print_trace_warning_symbol, - .stack = print_trace_stack, - .address = print_trace_address, -}; - -static void -show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, - unsigned long *stack, unsigned long bp, char *log_lvl) -{ - printk("%sCall Trace:\n", log_lvl); - dump_trace(task, regs, stack, bp, &print_trace_ops, log_lvl); -} - -void show_trace(struct task_struct *task, struct pt_regs *regs, - unsigned long *stack, unsigned long bp) -{ - show_trace_log_lvl(task, regs, stack, bp, ""); -} - -static void +void show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, unsigned long *sp, unsigned long bp, char *log_lvl) { @@ -342,33 +235,6 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, show_trace_log_lvl(task, regs, sp, bp, log_lvl); } -void show_stack(struct task_struct *task, unsigned long *sp) -{ - show_stack_log_lvl(task, NULL, sp, 0, ""); -} - -/* - * The architecture-independent dump_stack generator - */ -void dump_stack(void) -{ - unsigned long bp = 0; - unsigned long stack; - -#ifdef CONFIG_FRAME_POINTER - if (!bp) - get_bp(bp); -#endif - - printk("Pid: %d, comm: %.20s %s %s %.*s\n", - current->pid, current->comm, print_tainted(), - init_utsname()->release, - (int)strcspn(init_utsname()->version, " "), - init_utsname()->version); - show_trace(NULL, NULL, &stack, bp); -} -EXPORT_SYMBOL(dump_stack); - void show_registers(struct pt_regs *regs) { int i; @@ -429,147 +295,3 @@ int is_valid_bugaddr(unsigned long ip) return ud2 == 0x0b0f; } -static raw_spinlock_t die_lock = __RAW_SPIN_LOCK_UNLOCKED; -static int die_owner = -1; -static unsigned int die_nest_count; - -unsigned __kprobes long oops_begin(void) -{ - int cpu; - unsigned long flags; - - oops_enter(); - - /* racy, but better than risking deadlock. */ - raw_local_irq_save(flags); - cpu = smp_processor_id(); - if (!__raw_spin_trylock(&die_lock)) { - if (cpu == die_owner) - /* nested oops. should stop eventually */; - else - __raw_spin_lock(&die_lock); - } - die_nest_count++; - die_owner = cpu; - console_verbose(); - bust_spinlocks(1); - return flags; -} - -void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, int signr) -{ - die_owner = -1; - bust_spinlocks(0); - die_nest_count--; - if (!die_nest_count) - /* Nest count reaches zero, release the lock. */ - __raw_spin_unlock(&die_lock); - raw_local_irq_restore(flags); - if (!regs) { - oops_exit(); - return; - } - if (in_interrupt()) - panic("Fatal exception in interrupt"); - if (panic_on_oops) - panic("Fatal exception"); - oops_exit(); - do_exit(signr); -} - -int __kprobes __die(const char *str, struct pt_regs *regs, long err) -{ - printk(KERN_EMERG "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter); -#ifdef CONFIG_PREEMPT - printk("PREEMPT "); -#endif -#ifdef CONFIG_SMP - printk("SMP "); -#endif -#ifdef CONFIG_DEBUG_PAGEALLOC - printk("DEBUG_PAGEALLOC"); -#endif - printk("\n"); - sysfs_printk_last_file(); - if (notify_die(DIE_OOPS, str, regs, err, - current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) - return 1; - - show_registers(regs); - add_taint(TAINT_DIE); - /* Executive summary in case the oops scrolled away */ - printk(KERN_ALERT "RIP "); - printk_address(regs->ip, 1); - printk(" RSP <%016lx>\n", regs->sp); - if (kexec_should_crash(current)) - crash_kexec(regs); - return 0; -} - -void die(const char *str, struct pt_regs *regs, long err) -{ - unsigned long flags = oops_begin(); - - if (!user_mode(regs)) - report_bug(regs->ip, regs); - - if (__die(str, regs, err)) - regs = NULL; - oops_end(flags, regs, SIGSEGV); -} - -notrace __kprobes void -die_nmi(char *str, struct pt_regs *regs, int do_panic) -{ - unsigned long flags; - - if (notify_die(DIE_NMIWATCHDOG, str, regs, 0, 2, SIGINT) == NOTIFY_STOP) - return; - - flags = oops_begin(); - /* - * We are in trouble anyway, lets at least try - * to get a message out. - */ - printk(KERN_EMERG "%s", str); - printk(" on CPU%d, ip %08lx, registers:\n", - smp_processor_id(), regs->ip); - show_registers(regs); - if (kexec_should_crash(current)) - crash_kexec(regs); - if (do_panic || panic_on_oops) - panic("Non maskable interrupt"); - oops_end(flags, NULL, SIGBUS); - nmi_exit(); - local_irq_enable(); - do_exit(SIGBUS); -} - -static int __init oops_setup(char *s) -{ - if (!s) - return -EINVAL; - if (!strcmp(s, "panic")) - panic_on_oops = 1; - return 0; -} -early_param("oops", oops_setup); - -static int __init kstack_setup(char *s) -{ - if (!s) - return -EINVAL; - kstack_depth_to_print = simple_strtoul(s, NULL, 0); - return 0; -} -early_param("kstack", kstack_setup); - -static int __init code_bytes_setup(char *s) -{ - code_bytes = simple_strtoul(s, NULL, 0); - if (code_bytes > 8192) - code_bytes = 8192; - - return 1; -} -__setup("code_bytes=", code_bytes_setup); diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index ce97bf3bed12..65a13943e098 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -677,22 +677,6 @@ struct early_res { }; static struct early_res early_res[MAX_EARLY_RES] __initdata = { { 0, PAGE_SIZE, "BIOS data page" }, /* BIOS data page */ -#if defined(CONFIG_X86_64) && defined(CONFIG_X86_TRAMPOLINE) - { TRAMPOLINE_BASE, TRAMPOLINE_BASE + 2 * PAGE_SIZE, "TRAMPOLINE" }, -#endif -#if defined(CONFIG_X86_32) && defined(CONFIG_SMP) - /* - * But first pinch a few for the stack/trampoline stuff - * FIXME: Don't need the extra page at 4K, but need to fix - * trampoline before removing it. (see the GDT stuff) - */ - { PAGE_SIZE, PAGE_SIZE + PAGE_SIZE, "EX TRAMPOLINE" }, - /* - * Has to be in very low memory so we can execute - * real-mode AP code. - */ - { TRAMPOLINE_BASE, TRAMPOLINE_BASE + PAGE_SIZE, "TRAMPOLINE" }, -#endif {} }; @@ -1290,15 +1274,17 @@ void __init e820_reserve_resources(void) res->start = e820.map[i].addr; res->end = end; - res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; + res->flags = IORESOURCE_MEM; /* * don't register the region that could be conflicted with * pci device BAR resource and insert them later in * pcibios_resource_survey() */ - if (e820.map[i].type != E820_RESERVED || res->start < (1ULL<<20)) + if (e820.map[i].type != E820_RESERVED || res->start < (1ULL<<20)) { + res->flags |= IORESOURCE_BUSY; insert_resource(&iomem_resource, res); + } res++; } @@ -1318,7 +1304,7 @@ void __init e820_reserve_resources_late(void) res = e820_res; for (i = 0; i < e820.nr_map; i++) { if (!res->parent && res->end) - reserve_region_with_split(&iomem_resource, res->start, res->end, res->name); + insert_resource_expand_to_fit(&iomem_resource, res); res++; } } diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 3ce029ffaa55..1b894b72c0f5 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -188,20 +188,6 @@ static void __init ati_bugs_contd(int num, int slot, int func) } #endif -#ifdef CONFIG_DMAR -static void __init intel_g33_dmar(int num, int slot, int func) -{ - struct acpi_table_header *dmar_tbl; - acpi_status status; - - status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); - if (ACPI_SUCCESS(status)) { - printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n"); - dmar_disabled = 1; - } -} -#endif - #define QFLAG_APPLY_ONCE 0x1 #define QFLAG_APPLIED 0x2 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) @@ -225,10 +211,6 @@ static struct chipset early_qrk[] __initdata = { PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, -#ifdef CONFIG_DMAR - { PCI_VENDOR_ID_INTEL, 0x29c0, - PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar }, -#endif {} }; diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c index 34ad997d3834..23b138e31e9c 100644 --- a/arch/x86/kernel/early_printk.c +++ b/arch/x86/kernel/early_printk.c @@ -875,49 +875,6 @@ static struct console early_dbgp_console = { }; #endif -/* Console interface to a host file on AMD's SimNow! */ - -static int simnow_fd; - -enum { - MAGIC1 = 0xBACCD00A, - MAGIC2 = 0xCA110000, - XOPEN = 5, - XWRITE = 4, -}; - -static noinline long simnow(long cmd, long a, long b, long c) -{ - long ret; - - asm volatile("cpuid" : - "=a" (ret) : - "b" (a), "c" (b), "d" (c), "0" (MAGIC1), "D" (cmd + MAGIC2)); - return ret; -} - -static void __init simnow_init(char *str) -{ - char *fn = "klog"; - - if (*str == '=') - fn = ++str; - /* error ignored */ - simnow_fd = simnow(XOPEN, (unsigned long)fn, O_WRONLY|O_APPEND|O_CREAT, 0644); -} - -static void simnow_write(struct console *con, const char *s, unsigned n) -{ - simnow(XWRITE, simnow_fd, (unsigned long)s, n); -} - -static struct console simnow_console = { - .name = "simnow", - .write = simnow_write, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - /* Direct interface for emergencies */ static struct console *early_console = &early_vga_console; static int __initdata early_console_initialized; @@ -960,10 +917,6 @@ static int __init setup_early_printk(char *buf) max_ypos = boot_params.screen_info.orig_video_lines; current_ypos = boot_params.screen_info.orig_y; early_console = &early_vga_console; - } else if (!strncmp(buf, "simnow", 6)) { - simnow_init(buf + 6); - early_console = &simnow_console; - keep_early = 1; #ifdef CONFIG_EARLY_PRINTK_DBGP } else if (!strncmp(buf, "dbgp", 4)) { if (early_dbgp_init(buf+4) < 0) diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S index dd65143941a8..f6402c4ba10d 100644 --- a/arch/x86/kernel/entry_32.S +++ b/arch/x86/kernel/entry_32.S @@ -1051,6 +1051,7 @@ ENTRY(kernel_thread_helper) push %eax CFI_ADJUST_CFA_OFFSET 4 call do_exit + ud2 # padding for call trace CFI_ENDPROC ENDPROC(kernel_thread_helper) @@ -1149,7 +1150,7 @@ ENDPROC(xen_failsafe_callback) #endif /* CONFIG_XEN */ -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(mcount) @@ -1204,7 +1205,7 @@ trace: jmp ftrace_stub END(mcount) #endif /* CONFIG_DYNAMIC_FTRACE */ -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ .section .rodata,"a" #include "syscall_table_32.S" diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index 09e7145484c5..42571baaca32 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -11,15 +11,15 @@ * * NOTE: This code handles signal-recognition, which happens every time * after an interrupt and after each system call. - * - * Normal syscalls and interrupts don't save a full stack frame, this is + * + * Normal syscalls and interrupts don't save a full stack frame, this is * only done for syscall tracing, signals or fork/exec et.al. - * - * A note on terminology: - * - top of stack: Architecture defined interrupt frame from SS to RIP - * at the top of the kernel process stack. + * + * A note on terminology: + * - top of stack: Architecture defined interrupt frame from SS to RIP + * at the top of the kernel process stack. * - partial stack frame: partially saved registers upto R11. - * - full stack frame: Like partial stack frame, but all register saved. + * - full stack frame: Like partial stack frame, but all register saved. * * Some macro usage: * - CFI macros are used to generate dwarf2 unwind information for better @@ -61,7 +61,7 @@ .code64 -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(mcount) retq @@ -138,11 +138,11 @@ trace: jmp ftrace_stub END(mcount) #endif /* CONFIG_DYNAMIC_FTRACE */ -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ #ifndef CONFIG_PREEMPT #define retint_kernel retint_restore_args -#endif +#endif #ifdef CONFIG_PARAVIRT ENTRY(native_usergs_sysret64) @@ -161,14 +161,14 @@ ENTRY(native_usergs_sysret64) .endm /* - * C code is not supposed to know about undefined top of stack. Every time - * a C function with an pt_regs argument is called from the SYSCALL based + * C code is not supposed to know about undefined top of stack. Every time + * a C function with an pt_regs argument is called from the SYSCALL based * fast path FIXUP_TOP_OF_STACK is needed. * RESTORE_TOP_OF_STACK syncs the syscall state after any possible ptregs * manipulation. - */ - - /* %rsp:at FRAMEEND */ + */ + + /* %rsp:at FRAMEEND */ .macro FIXUP_TOP_OF_STACK tmp movq %gs:pda_oldrsp,\tmp movq \tmp,RSP(%rsp) @@ -244,8 +244,8 @@ ENTRY(native_usergs_sysret64) .endm /* * A newly forked process directly context switches into this. - */ -/* rdi: prev */ + */ +/* rdi: prev */ ENTRY(ret_from_fork) CFI_DEFAULT_STACK push kernel_eflags(%rip) @@ -255,8 +255,9 @@ ENTRY(ret_from_fork) call schedule_tail GET_THREAD_INFO(%rcx) testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT),TI_flags(%rcx) + CFI_REMEMBER_STATE jnz rff_trace -rff_action: +rff_action: RESTORE_REST testl $3,CS-ARGOFFSET(%rsp) # from kernel_thread? je int_ret_from_sys_call @@ -264,10 +265,11 @@ rff_action: jnz int_ret_from_sys_call RESTORE_TOP_OF_STACK %rdi,ARGOFFSET jmp ret_from_sys_call + CFI_RESTORE_STATE rff_trace: movq %rsp,%rdi call syscall_trace_leave - GET_THREAD_INFO(%rcx) + GET_THREAD_INFO(%rcx) jmp rff_action CFI_ENDPROC END(ret_from_fork) @@ -278,20 +280,20 @@ END(ret_from_fork) * SYSCALL does not save anything on the stack and does not change the * stack pointer. */ - + /* - * Register setup: + * Register setup: * rax system call number * rdi arg0 - * rcx return address for syscall/sysret, C arg3 + * rcx return address for syscall/sysret, C arg3 * rsi arg1 - * rdx arg2 + * rdx arg2 * r10 arg3 (--> moved to rcx for C) * r8 arg4 * r9 arg5 * r11 eflags for syscall/sysret, temporary for C - * r12-r15,rbp,rbx saved by C code, not touched. - * + * r12-r15,rbp,rbx saved by C code, not touched. + * * Interrupts are off on entry. * Only called from user space. * @@ -301,7 +303,7 @@ END(ret_from_fork) * When user can change the frames always force IRET. That is because * it deals with uncanonical addresses better. SYSRET has trouble * with them due to bugs in both AMD and Intel CPUs. - */ + */ ENTRY(system_call) CFI_STARTPROC simple @@ -317,7 +319,7 @@ ENTRY(system_call) */ ENTRY(system_call_after_swapgs) - movq %rsp,%gs:pda_oldrsp + movq %rsp,%gs:pda_oldrsp movq %gs:pda_kernelstack,%rsp /* * No need to follow this irqs off/on section - it's straight @@ -325,7 +327,7 @@ ENTRY(system_call_after_swapgs) */ ENABLE_INTERRUPTS(CLBR_NONE) SAVE_ARGS 8,1 - movq %rax,ORIG_RAX-ARGOFFSET(%rsp) + movq %rax,ORIG_RAX-ARGOFFSET(%rsp) movq %rcx,RIP-ARGOFFSET(%rsp) CFI_REL_OFFSET rip,RIP-ARGOFFSET GET_THREAD_INFO(%rcx) @@ -339,19 +341,19 @@ system_call_fastpath: movq %rax,RAX-ARGOFFSET(%rsp) /* * Syscall return path ending with SYSRET (fast path) - * Has incomplete stack frame and undefined top of stack. - */ + * Has incomplete stack frame and undefined top of stack. + */ ret_from_sys_call: movl $_TIF_ALLWORK_MASK,%edi /* edi: flagmask */ -sysret_check: +sysret_check: LOCKDEP_SYS_EXIT GET_THREAD_INFO(%rcx) DISABLE_INTERRUPTS(CLBR_NONE) TRACE_IRQS_OFF movl TI_flags(%rcx),%edx andl %edi,%edx - jnz sysret_careful + jnz sysret_careful CFI_REMEMBER_STATE /* * sysretq will re-enable interrupts: @@ -366,7 +368,7 @@ sysret_check: CFI_RESTORE_STATE /* Handle reschedules */ - /* edx: work, edi: workmask */ + /* edx: work, edi: workmask */ sysret_careful: bt $TIF_NEED_RESCHED,%edx jnc sysret_signal @@ -379,7 +381,7 @@ sysret_careful: CFI_ADJUST_CFA_OFFSET -8 jmp sysret_check - /* Handle a signal */ + /* Handle a signal */ sysret_signal: TRACE_IRQS_ON ENABLE_INTERRUPTS(CLBR_NONE) @@ -398,7 +400,7 @@ sysret_signal: DISABLE_INTERRUPTS(CLBR_NONE) TRACE_IRQS_OFF jmp int_with_check - + badsys: movq $-ENOSYS,RAX-ARGOFFSET(%rsp) jmp ret_from_sys_call @@ -437,7 +439,7 @@ sysret_audit: #endif /* CONFIG_AUDITSYSCALL */ /* Do syscall tracing */ -tracesys: +tracesys: #ifdef CONFIG_AUDITSYSCALL testl $(_TIF_WORK_SYSCALL_ENTRY & ~_TIF_SYSCALL_AUDIT),TI_flags(%rcx) jz auditsys @@ -460,8 +462,8 @@ tracesys: call *sys_call_table(,%rax,8) movq %rax,RAX-ARGOFFSET(%rsp) /* Use IRET because user could have changed frame */ - -/* + +/* * Syscall return path ending with IRET. * Has correct top of stack, but partial stack frame. */ @@ -505,18 +507,18 @@ int_very_careful: TRACE_IRQS_ON ENABLE_INTERRUPTS(CLBR_NONE) SAVE_REST - /* Check for syscall exit trace */ + /* Check for syscall exit trace */ testl $_TIF_WORK_SYSCALL_EXIT,%edx jz int_signal pushq %rdi CFI_ADJUST_CFA_OFFSET 8 - leaq 8(%rsp),%rdi # &ptregs -> arg1 + leaq 8(%rsp),%rdi # &ptregs -> arg1 call syscall_trace_leave popq %rdi CFI_ADJUST_CFA_OFFSET -8 andl $~(_TIF_WORK_SYSCALL_EXIT|_TIF_SYSCALL_EMU),%edi jmp int_restore_rest - + int_signal: testl $_TIF_DO_NOTIFY_MASK,%edx jz 1f @@ -531,11 +533,11 @@ int_restore_rest: jmp int_with_check CFI_ENDPROC END(system_call) - -/* + +/* * Certain special system calls that need to save a complete full stack frame. - */ - + */ + .macro PTREGSCALL label,func,arg .globl \label \label: @@ -572,7 +574,7 @@ ENTRY(ptregscall_common) ret CFI_ENDPROC END(ptregscall_common) - + ENTRY(stub_execve) CFI_STARTPROC popq %r11 @@ -588,11 +590,11 @@ ENTRY(stub_execve) jmp int_ret_from_sys_call CFI_ENDPROC END(stub_execve) - + /* * sigreturn is special because it needs to restore all registers on return. * This cannot be done with SYSRET, so use the IRET return path instead. - */ + */ ENTRY(stub_rt_sigreturn) CFI_STARTPROC addq $8, %rsp @@ -685,12 +687,12 @@ exit_intr: GET_THREAD_INFO(%rcx) testl $3,CS-ARGOFFSET(%rsp) je retint_kernel - + /* Interrupt came from user space */ /* * Has a correct top of stack, but a partial stack frame * %rcx: thread info. Interrupts off. - */ + */ retint_with_reschedule: movl $_TIF_WORK_MASK,%edi retint_check: @@ -763,20 +765,20 @@ retint_careful: pushq %rdi CFI_ADJUST_CFA_OFFSET 8 call schedule - popq %rdi + popq %rdi CFI_ADJUST_CFA_OFFSET -8 GET_THREAD_INFO(%rcx) DISABLE_INTERRUPTS(CLBR_NONE) TRACE_IRQS_OFF jmp retint_check - + retint_signal: testl $_TIF_DO_NOTIFY_MASK,%edx jz retint_swapgs TRACE_IRQS_ON ENABLE_INTERRUPTS(CLBR_NONE) SAVE_REST - movq $-1,ORIG_RAX(%rsp) + movq $-1,ORIG_RAX(%rsp) xorl %esi,%esi # oldset movq %rsp,%rdi # &pt_regs call do_notify_resume @@ -798,14 +800,14 @@ ENTRY(retint_kernel) jnc retint_restore_args call preempt_schedule_irq jmp exit_intr -#endif +#endif CFI_ENDPROC END(common_interrupt) - + /* * APIC interrupts. - */ + */ .macro apicinterrupt num,func INTR_FRAME pushq $~(\num) @@ -823,14 +825,14 @@ ENTRY(threshold_interrupt) apicinterrupt THRESHOLD_APIC_VECTOR,mce_threshold_interrupt END(threshold_interrupt) -#ifdef CONFIG_SMP +#ifdef CONFIG_SMP ENTRY(reschedule_interrupt) apicinterrupt RESCHEDULE_VECTOR,smp_reschedule_interrupt END(reschedule_interrupt) .macro INVALIDATE_ENTRY num ENTRY(invalidate_interrupt\num) - apicinterrupt INVALIDATE_TLB_VECTOR_START+\num,smp_invalidate_interrupt + apicinterrupt INVALIDATE_TLB_VECTOR_START+\num,smp_invalidate_interrupt END(invalidate_interrupt\num) .endm @@ -869,22 +871,22 @@ END(error_interrupt) ENTRY(spurious_interrupt) apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt END(spurious_interrupt) - + /* * Exception entry points. - */ + */ .macro zeroentry sym INTR_FRAME PARAVIRT_ADJUST_EXCEPTION_FRAME - pushq $0 /* push error code/oldrax */ + pushq $0 /* push error code/oldrax */ CFI_ADJUST_CFA_OFFSET 8 - pushq %rax /* push real oldrax to the rdi slot */ + pushq %rax /* push real oldrax to the rdi slot */ CFI_ADJUST_CFA_OFFSET 8 CFI_REL_OFFSET rax,0 leaq \sym(%rip),%rax jmp error_entry CFI_ENDPROC - .endm + .endm .macro errorentry sym XCPT_FRAME @@ -998,13 +1000,13 @@ paranoid_schedule\trace: /* * Exception entry point. This expects an error code/orig_rax on the stack - * and the exception handler in %rax. - */ + * and the exception handler in %rax. + */ KPROBE_ENTRY(error_entry) _frame RDI CFI_REL_OFFSET rax,0 /* rdi slot contains rax, oldrax contains error code */ - cld + cld subq $14*8,%rsp CFI_ADJUST_CFA_OFFSET (14*8) movq %rsi,13*8(%rsp) @@ -1015,7 +1017,7 @@ KPROBE_ENTRY(error_entry) CFI_REL_OFFSET rdx,RDX movq %rcx,11*8(%rsp) CFI_REL_OFFSET rcx,RCX - movq %rsi,10*8(%rsp) /* store rax */ + movq %rsi,10*8(%rsp) /* store rax */ CFI_REL_OFFSET rax,RAX movq %r8, 9*8(%rsp) CFI_REL_OFFSET r8,R8 @@ -1025,29 +1027,29 @@ KPROBE_ENTRY(error_entry) CFI_REL_OFFSET r10,R10 movq %r11,6*8(%rsp) CFI_REL_OFFSET r11,R11 - movq %rbx,5*8(%rsp) + movq %rbx,5*8(%rsp) CFI_REL_OFFSET rbx,RBX - movq %rbp,4*8(%rsp) + movq %rbp,4*8(%rsp) CFI_REL_OFFSET rbp,RBP - movq %r12,3*8(%rsp) + movq %r12,3*8(%rsp) CFI_REL_OFFSET r12,R12 - movq %r13,2*8(%rsp) + movq %r13,2*8(%rsp) CFI_REL_OFFSET r13,R13 - movq %r14,1*8(%rsp) + movq %r14,1*8(%rsp) CFI_REL_OFFSET r14,R14 - movq %r15,(%rsp) + movq %r15,(%rsp) CFI_REL_OFFSET r15,R15 - xorl %ebx,%ebx + xorl %ebx,%ebx testl $3,CS(%rsp) je error_kernelspace -error_swapgs: +error_swapgs: SWAPGS error_sti: TRACE_IRQS_OFF - movq %rdi,RDI(%rsp) + movq %rdi,RDI(%rsp) CFI_REL_OFFSET rdi,RDI movq %rsp,%rdi - movq ORIG_RAX(%rsp),%rsi /* get error code */ + movq ORIG_RAX(%rsp),%rsi /* get error code */ movq $-1,ORIG_RAX(%rsp) call *%rax /* ebx: no swapgs flag (1: don't need swapgs, 0: need it) */ @@ -1056,7 +1058,7 @@ error_exit: RESTORE_REST DISABLE_INTERRUPTS(CLBR_NONE) TRACE_IRQS_OFF - GET_THREAD_INFO(%rcx) + GET_THREAD_INFO(%rcx) testl %eax,%eax jne retint_kernel LOCKDEP_SYS_EXIT_IRQ @@ -1072,7 +1074,7 @@ error_kernelspace: /* There are two places in the kernel that can potentially fault with usergs. Handle them here. The exception handlers after iret run with kernel gs again, so don't set the user space flag. - B stepping K8s sometimes report an truncated RIP for IRET + B stepping K8s sometimes report an truncated RIP for IRET exceptions returning to compat mode. Check for these here too. */ leaq irq_return(%rip),%rcx cmpq %rcx,RIP(%rsp) @@ -1084,17 +1086,17 @@ error_kernelspace: je error_swapgs jmp error_sti KPROBE_END(error_entry) - + /* Reload gs selector with exception handling */ - /* edi: new selector */ + /* edi: new selector */ ENTRY(native_load_gs_index) CFI_STARTPROC pushf CFI_ADJUST_CFA_OFFSET 8 DISABLE_INTERRUPTS(CLBR_ANY | ~(CLBR_RDI)) SWAPGS -gs_change: - movl %edi,%gs +gs_change: + movl %edi,%gs 2: mfence /* workaround */ SWAPGS popf @@ -1102,20 +1104,20 @@ gs_change: ret CFI_ENDPROC ENDPROC(native_load_gs_index) - + .section __ex_table,"a" .align 8 .quad gs_change,bad_gs .previous .section .fixup,"ax" /* running with kernelgs */ -bad_gs: +bad_gs: SWAPGS /* switch back to user gs */ xorl %eax,%eax movl %eax,%gs jmp 2b - .previous - + .previous + /* * Create a kernel thread. * @@ -1138,7 +1140,7 @@ ENTRY(kernel_thread) xorl %r8d,%r8d xorl %r9d,%r9d - + # clone now call do_fork movq %rax,RAX(%rsp) @@ -1149,14 +1151,14 @@ ENTRY(kernel_thread) * so internally to the x86_64 port you can rely on kernel_thread() * not to reschedule the child before returning, this avoids the need * of hacks for example to fork off the per-CPU idle tasks. - * [Hopefully no generic code relies on the reschedule -AK] + * [Hopefully no generic code relies on the reschedule -AK] */ RESTORE_ALL UNFAKE_STACK_FRAME ret CFI_ENDPROC ENDPROC(kernel_thread) - + child_rip: pushq $0 # fake return address CFI_STARTPROC @@ -1170,6 +1172,7 @@ child_rip: # exit mov %eax, %edi call do_exit + ud2 # padding for call trace CFI_ENDPROC ENDPROC(child_rip) @@ -1191,10 +1194,10 @@ ENDPROC(child_rip) ENTRY(kernel_execve) CFI_STARTPROC FAKE_STACK_FRAME $0 - SAVE_ALL + SAVE_ALL movq %rsp,%rcx call sys_execve - movq %rax, RAX(%rsp) + movq %rax, RAX(%rsp) RESTORE_REST testq %rax,%rax je int_ret_from_sys_call @@ -1213,7 +1216,7 @@ ENTRY(coprocessor_error) END(coprocessor_error) ENTRY(simd_coprocessor_error) - zeroentry do_simd_coprocessor_error + zeroentry do_simd_coprocessor_error END(simd_coprocessor_error) ENTRY(device_not_available) @@ -1225,12 +1228,12 @@ KPROBE_ENTRY(debug) INTR_FRAME PARAVIRT_ADJUST_EXCEPTION_FRAME pushq $0 - CFI_ADJUST_CFA_OFFSET 8 + CFI_ADJUST_CFA_OFFSET 8 paranoidentry do_debug, DEBUG_STACK paranoidexit KPROBE_END(debug) - /* runs on exception stack */ + /* runs on exception stack */ KPROBE_ENTRY(nmi) INTR_FRAME PARAVIRT_ADJUST_EXCEPTION_FRAME @@ -1264,7 +1267,7 @@ ENTRY(bounds) END(bounds) ENTRY(invalid_op) - zeroentry do_invalid_op + zeroentry do_invalid_op END(invalid_op) ENTRY(coprocessor_segment_overrun) @@ -1319,7 +1322,7 @@ ENTRY(machine_check) INTR_FRAME PARAVIRT_ADJUST_EXCEPTION_FRAME pushq $0 - CFI_ADJUST_CFA_OFFSET 8 + CFI_ADJUST_CFA_OFFSET 8 paranoidentry do_machine_check jmp paranoid_exit1 CFI_ENDPROC diff --git a/arch/x86/kernel/es7000_32.c b/arch/x86/kernel/es7000_32.c index f454c78fcef6..53699c931ad4 100644 --- a/arch/x86/kernel/es7000_32.c +++ b/arch/x86/kernel/es7000_32.c @@ -38,8 +38,11 @@ #include #include #include +#include #include #include +#include +#include /* * ES7000 chipsets @@ -161,6 +164,43 @@ es7000_rename_gsi(int ioapic, int gsi) return gsi; } +static int wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip) +{ + unsigned long vect = 0, psaival = 0; + + if (psai == NULL) + return -1; + + vect = ((unsigned long)__pa(eip)/0x1000) << 16; + psaival = (0x1000000 | vect | cpu); + + while (*psai & 0x1000000) + ; + + *psai = psaival; + + return 0; +} + +static void noop_wait_for_deassert(atomic_t *deassert_not_used) +{ +} + +static int __init es7000_update_genapic(void) +{ + genapic->wakeup_cpu = wakeup_secondary_cpu_via_mip; + + /* MPENTIUMIII */ + if (boot_cpu_data.x86 == 6 && + (boot_cpu_data.x86_model >= 7 || boot_cpu_data.x86_model <= 11)) { + es7000_update_genapic_to_cluster(); + genapic->wait_for_init_deassert = noop_wait_for_deassert; + genapic->wakeup_cpu = wakeup_secondary_cpu_via_mip; + } + + return 0; +} + void __init setup_unisys(void) { @@ -176,6 +216,8 @@ setup_unisys(void) else es7000_plat = ES7000_CLASSIC; ioapic_renumber_irq = es7000_rename_gsi; + + x86_quirks->update_genapic = es7000_update_genapic; } /* @@ -250,31 +292,24 @@ int __init find_unisys_acpi_oem_table(unsigned long *oem_addr) { struct acpi_table_header *header = NULL; int i = 0; - acpi_size tbl_size; - while (ACPI_SUCCESS(acpi_get_table_with_size("OEM1", i++, &header, &tbl_size))) { + while (ACPI_SUCCESS(acpi_get_table("OEM1", i++, &header))) { if (!memcmp((char *) &header->oem_id, "UNISYS", 6)) { struct oem_table *t = (struct oem_table *)header; oem_addrX = t->OEMTableAddr; oem_size = t->OEMTableSize; - early_acpi_os_unmap_memory(header, tbl_size); *oem_addr = (unsigned long)__acpi_map_table(oem_addrX, oem_size); return 0; } - early_acpi_os_unmap_memory(header, tbl_size); } return -1; } void __init unmap_unisys_acpi_oem_table(unsigned long oem_addr) { - if (!oem_addr) - return; - - __acpi_unmap_table((char *)oem_addr, oem_size); } #endif @@ -324,26 +359,6 @@ es7000_mip_write(struct mip_reg *mip_reg) return status; } -int -es7000_start_cpu(int cpu, unsigned long eip) -{ - unsigned long vect = 0, psaival = 0; - - if (psai == NULL) - return -1; - - vect = ((unsigned long)__pa(eip)/0x1000) << 16; - psaival = (0x1000000 | vect | cpu); - - while (*psai & 0x1000000) - ; - - *psai = psaival; - - return 0; - -} - void __init es7000_sw_apic(void) { diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index d073d981a730..50ea0ac8c9bf 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -21,8 +21,7 @@ #include -/* Long is fine, even if it is only 4 bytes ;-) */ -static unsigned long *ftrace_nop; +static unsigned char ftrace_nop[MCOUNT_INSN_SIZE]; union ftrace_code_union { char code[MCOUNT_INSN_SIZE]; @@ -33,17 +32,17 @@ union ftrace_code_union { }; -static int notrace ftrace_calc_offset(long ip, long addr) +static int ftrace_calc_offset(long ip, long addr) { return (int)(addr - ip); } -notrace unsigned char *ftrace_nop_replace(void) +unsigned char *ftrace_nop_replace(void) { - return (char *)ftrace_nop; + return ftrace_nop; } -notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) { static union ftrace_code_union calc; @@ -57,7 +56,7 @@ notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) return calc.code; } -notrace int +int ftrace_modify_code(unsigned long ip, unsigned char *old_code, unsigned char *new_code) { @@ -66,26 +65,31 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code, /* * Note: Due to modules and __init, code can * disappear and change, we need to protect against faulting - * as well as code changing. + * as well as code changing. We do this by using the + * probe_kernel_* functions. * * No real locking needed, this code is run through * kstop_machine, or before SMP starts. */ - if (__copy_from_user_inatomic(replaced, (char __user *)ip, MCOUNT_INSN_SIZE)) - return 1; + /* read the text we want to modify */ + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + return -EFAULT; + + /* Make sure it is what we expect it to be */ if (memcmp(replaced, old_code, MCOUNT_INSN_SIZE) != 0) - return 2; + return -EINVAL; - WARN_ON_ONCE(__copy_to_user_inatomic((char __user *)ip, new_code, - MCOUNT_INSN_SIZE)); + /* replace the text with the new text */ + if (probe_kernel_write((void *)ip, new_code, MCOUNT_INSN_SIZE)) + return -EPERM; sync_core(); return 0; } -notrace int ftrace_update_ftrace_func(ftrace_func_t func) +int ftrace_update_ftrace_func(ftrace_func_t func) { unsigned long ip = (unsigned long)(&ftrace_call); unsigned char old[MCOUNT_INSN_SIZE], *new; @@ -98,13 +102,6 @@ notrace int ftrace_update_ftrace_func(ftrace_func_t func) return ret; } -notrace int ftrace_mcount_set(unsigned long *data) -{ - /* mcount is initialized as a nop */ - *data = 0; - return 0; -} - int __init ftrace_dyn_arch_init(void *data) { extern const unsigned char ftrace_test_p6nop[]; @@ -127,9 +124,6 @@ int __init ftrace_dyn_arch_init(void *data) * TODO: check the cpuid to determine the best nop. */ asm volatile ( - "jmp ftrace_test_jmp\n" - /* This code needs to stay around */ - ".section .text, \"ax\"\n" "ftrace_test_jmp:" "jmp ftrace_test_p6nop\n" "nop\n" @@ -140,8 +134,6 @@ int __init ftrace_dyn_arch_init(void *data) "jmp 1f\n" "ftrace_test_nop5:" ".byte 0x66,0x66,0x66,0x66,0x90\n" - "jmp 1f\n" - ".previous\n" "1:" ".section .fixup, \"ax\"\n" "2: movl $1, %0\n" @@ -156,15 +148,15 @@ int __init ftrace_dyn_arch_init(void *data) switch (faulted) { case 0: pr_info("ftrace: converting mcount calls to 0f 1f 44 00 00\n"); - ftrace_nop = (unsigned long *)ftrace_test_p6nop; + memcpy(ftrace_nop, ftrace_test_p6nop, MCOUNT_INSN_SIZE); break; case 1: pr_info("ftrace: converting mcount calls to 66 66 66 66 90\n"); - ftrace_nop = (unsigned long *)ftrace_test_nop5; + memcpy(ftrace_nop, ftrace_test_nop5, MCOUNT_INSN_SIZE); break; case 2: pr_info("ftrace: converting mcount calls to jmp . + 5\n"); - ftrace_nop = (unsigned long *)ftrace_test_jmp; + memcpy(ftrace_nop, ftrace_test_jmp, MCOUNT_INSN_SIZE); break; } diff --git a/arch/x86/kernel/genapic_64.c b/arch/x86/kernel/genapic_64.c index 6c9bfc9e1e95..2bced78b0b8e 100644 --- a/arch/x86/kernel/genapic_64.c +++ b/arch/x86/kernel/genapic_64.c @@ -21,6 +21,7 @@ #include #include #include +#include extern struct genapic apic_flat; extern struct genapic apic_physflat; @@ -53,6 +54,9 @@ void __init setup_apic_routing(void) genapic = &apic_physflat; printk(KERN_INFO "Setting APIC routing to %s\n", genapic->name); } + + if (x86_quirks->update_genapic) + x86_quirks->update_genapic(); } /* Same for both flat and physical. */ diff --git a/arch/x86/kernel/genx2apic_uv_x.c b/arch/x86/kernel/genx2apic_uv_x.c index 680a06557c5e..dece17289731 100644 --- a/arch/x86/kernel/genx2apic_uv_x.c +++ b/arch/x86/kernel/genx2apic_uv_x.c @@ -10,14 +10,17 @@ #include #include +#include #include #include #include #include #include -#include #include #include +#include +#include +#include #include #include #include @@ -356,6 +359,103 @@ static __init void uv_rtc_init(void) sn_rtc_cycles_per_second = ticks_per_sec; } +/* + * percpu heartbeat timer + */ +static void uv_heartbeat(unsigned long ignored) +{ + struct timer_list *timer = &uv_hub_info->scir.timer; + unsigned char bits = uv_hub_info->scir.state; + + /* flip heartbeat bit */ + bits ^= SCIR_CPU_HEARTBEAT; + + /* is this cpu idle? */ + if (idle_cpu(raw_smp_processor_id())) + bits &= ~SCIR_CPU_ACTIVITY; + else + bits |= SCIR_CPU_ACTIVITY; + + /* update system controller interface reg */ + uv_set_scir_bits(bits); + + /* enable next timer period */ + mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); +} + +static void __cpuinit uv_heartbeat_enable(int cpu) +{ + if (!uv_cpu_hub_info(cpu)->scir.enabled) { + struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; + + uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); + setup_timer(timer, uv_heartbeat, cpu); + timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; + add_timer_on(timer, cpu); + uv_cpu_hub_info(cpu)->scir.enabled = 1; + } + + /* check boot cpu */ + if (!uv_cpu_hub_info(0)->scir.enabled) + uv_heartbeat_enable(0); +} + +#ifdef CONFIG_HOTPLUG_CPU +static void __cpuinit uv_heartbeat_disable(int cpu) +{ + if (uv_cpu_hub_info(cpu)->scir.enabled) { + uv_cpu_hub_info(cpu)->scir.enabled = 0; + del_timer(&uv_cpu_hub_info(cpu)->scir.timer); + } + uv_set_cpu_scir_bits(cpu, 0xff); +} + +/* + * cpu hotplug notifier + */ +static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + long cpu = (long)hcpu; + + switch (action) { + case CPU_ONLINE: + uv_heartbeat_enable(cpu); + break; + case CPU_DOWN_PREPARE: + uv_heartbeat_disable(cpu); + break; + default: + break; + } + return NOTIFY_OK; +} + +static __init void uv_scir_register_cpu_notifier(void) +{ + hotcpu_notifier(uv_scir_cpu_notify, 0); +} + +#else /* !CONFIG_HOTPLUG_CPU */ + +static __init void uv_scir_register_cpu_notifier(void) +{ +} + +static __init int uv_init_heartbeat(void) +{ + int cpu; + + if (is_uv_system()) + for_each_online_cpu(cpu) + uv_heartbeat_enable(cpu); + return 0; +} + +late_initcall(uv_init_heartbeat); + +#endif /* !CONFIG_HOTPLUG_CPU */ + /* * Called on each cpu to initialize the per_cpu UV data area. * ZZZ hotplug not supported yet @@ -398,16 +498,16 @@ void __init uv_system_init(void) printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); - uv_blade_info = alloc_bootmem_pages(bytes); + uv_blade_info = kmalloc(bytes, GFP_KERNEL); get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); - uv_node_to_blade = alloc_bootmem_pages(bytes); + uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); memset(uv_node_to_blade, 255, bytes); bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); - uv_cpu_to_blade = alloc_bootmem_pages(bytes); + uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); memset(uv_cpu_to_blade, 255, bytes); blade = 0; @@ -429,7 +529,7 @@ void __init uv_system_init(void) uv_bios_init(); uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, - &uv_coherency_id, &uv_region_size); + &sn_coherency_id, &sn_region_size); uv_rtc_init(); for_each_present_cpu(cpu) { @@ -440,8 +540,7 @@ void __init uv_system_init(void) uv_blade_info[blade].nr_possible_cpus++; uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; - uv_cpu_hub_info(cpu)->lowmem_remap_top = - lowmem_redir_base + lowmem_redir_size; + uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; uv_cpu_hub_info(cpu)->m_val = m_val; uv_cpu_hub_info(cpu)->n_val = m_val; uv_cpu_hub_info(cpu)->numa_blade_id = blade; @@ -451,7 +550,8 @@ void __init uv_system_init(void) uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1; uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; - uv_cpu_hub_info(cpu)->coherency_domain_number = uv_coherency_id; + uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; + uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu; uv_node_to_blade[nid] = blade; uv_cpu_to_blade[cpu] = blade; max_pnode = max(pnode, max_pnode); @@ -468,4 +568,6 @@ void __init uv_system_init(void) map_mmioh_high(max_pnode); uv_cpu_init(); + uv_scir_register_cpu_notifier(); + proc_mkdir("sgi_uv", NULL); } diff --git a/arch/x86/kernel/head.c b/arch/x86/kernel/head.c index 1dcb0f13897e..3e66bd364a9d 100644 --- a/arch/x86/kernel/head.c +++ b/arch/x86/kernel/head.c @@ -35,7 +35,6 @@ void __init reserve_ebda_region(void) /* start of EBDA area */ ebda_addr = get_bios_ebda(); - printk(KERN_INFO "BIOS EBDA/lowmem at: %08x/%08x\n", ebda_addr, lowmem); /* Fixup: bios puts an EBDA in the top 64K segment */ /* of conventional memory, but does not adjust lowmem. */ diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c index fa1d25dd83e3..ac108d1fe182 100644 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -12,9 +12,12 @@ #include #include #include +#include void __init i386_start_kernel(void) { + reserve_trampoline_memory(); + reserve_early(__pa_symbol(&_text), __pa_symbol(&_end), "TEXT DATA BSS"); #ifdef CONFIG_BLK_DEV_INITRD diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index d16084f90649..388e05a5fc17 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -24,6 +24,7 @@ #include #include #include +#include /* boot cpu pda */ static struct x8664_pda _boot_cpu_pda __read_mostly; @@ -120,6 +121,8 @@ void __init x86_64_start_reservations(char *real_mode_data) { copy_bootdata(__va(real_mode_data)); + reserve_trampoline_memory(); + reserve_early(__pa_symbol(&_text), __pa_symbol(&_end), "TEXT DATA BSS"); #ifdef CONFIG_BLK_DEV_INITRD diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 77017e834cf7..3f0a3edf0a57 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -33,7 +33,9 @@ * HPET address is set in acpi/boot.c, when an ACPI entry exists */ unsigned long hpet_address; -unsigned long hpet_num_timers; +#ifdef CONFIG_PCI_MSI +static unsigned long hpet_num_timers; +#endif static void __iomem *hpet_virt_address; struct hpet_dev { @@ -322,7 +324,7 @@ static int hpet_next_event(unsigned long delta, * what we wrote hit the chip before we compare it to the * counter. */ - WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt); + WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt); return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; } @@ -445,7 +447,7 @@ static int hpet_setup_irq(struct hpet_dev *dev) { if (request_irq(dev->irq, hpet_interrupt_handler, - IRQF_SHARED|IRQF_NOBALANCING, dev->name, dev)) + IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev)) return -1; disable_irq(dev->irq); diff --git a/arch/x86/kernel/i386_ksyms_32.c b/arch/x86/kernel/i386_ksyms_32.c index dd7ebee446af..43cec6bdda63 100644 --- a/arch/x86/kernel/i386_ksyms_32.c +++ b/arch/x86/kernel/i386_ksyms_32.c @@ -5,7 +5,7 @@ #include #include -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER /* mcount is defined in assembly */ EXPORT_SYMBOL(mcount); #endif diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c index 1f20608d4ca8..b0f61f0dcd0a 100644 --- a/arch/x86/kernel/i387.c +++ b/arch/x86/kernel/i387.c @@ -58,7 +58,7 @@ void __cpuinit mxcsr_feature_mask_init(void) stts(); } -void __init init_thread_xstate(void) +void __cpuinit init_thread_xstate(void) { if (!HAVE_HWFP) { xstate_size = sizeof(struct i387_soft_struct); diff --git a/arch/x86/kernel/init_task.c b/arch/x86/kernel/init_task.c index a4f93b4120c1..d39918076bb4 100644 --- a/arch/x86/kernel/init_task.c +++ b/arch/x86/kernel/init_task.c @@ -14,7 +14,6 @@ static struct fs_struct init_fs = INIT_FS; static struct signal_struct init_signals = INIT_SIGNALS(init_signals); static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); struct mm_struct init_mm = INIT_MM(init_mm); -EXPORT_UNUSED_SYMBOL(init_mm); /* will be removed in 2.6.26 */ /* * Initial thread structure. diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c index b764d7429c61..679e7bbbbcd6 100644 --- a/arch/x86/kernel/io_apic.c +++ b/arch/x86/kernel/io_apic.c @@ -1140,6 +1140,20 @@ static void __clear_irq_vector(int irq) cfg->vector = 0; cpus_clear(cfg->domain); + + if (likely(!cfg->move_in_progress)) + return; + cpus_and(mask, cfg->old_domain, cpu_online_map); + for_each_cpu_mask_nr(cpu, mask) { + for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; + vector++) { + if (per_cpu(vector_irq, cpu)[vector] != irq) + continue; + per_cpu(vector_irq, cpu)[vector] = -1; + break; + } + } + cfg->move_in_progress = 0; } void __setup_vector_irq(int cpu) @@ -2202,10 +2216,9 @@ static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) asmlinkage void smp_irq_move_cleanup_interrupt(void) { unsigned vector, me; + ack_APIC_irq(); -#ifdef CONFIG_X86_64 exit_idle(); -#endif irq_enter(); me = smp_processor_id(); @@ -3594,25 +3607,7 @@ int __init io_apic_get_redir_entries (int ioapic) int __init probe_nr_irqs(void) { - int idx; - int nr = 0; -#ifndef CONFIG_XEN - int nr_min = 32; -#else - int nr_min = NR_IRQS; -#endif - - for (idx = 0; idx < nr_ioapics; idx++) - nr += io_apic_get_redir_entries(idx) + 1; - - /* double it for hotplug and msi and nmi */ - nr <<= 1; - - /* something wrong ? */ - if (nr < nr_min) - nr = nr_min; - - return nr; + return NR_IRQS; } /* -------------------------------------------------------------------------- @@ -3759,7 +3754,9 @@ int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) void __init setup_ioapic_dest(void) { int pin, ioapic, irq, irq_entry; + struct irq_desc *desc; struct irq_cfg *cfg; + cpumask_t mask; if (skip_ioapic_setup == 1) return; @@ -3776,16 +3773,30 @@ void __init setup_ioapic_dest(void) * cpu is online. */ cfg = irq_cfg(irq); - if (!cfg->vector) + if (!cfg->vector) { setup_IO_APIC_irq(ioapic, pin, irq, irq_trigger(irq_entry), irq_polarity(irq_entry)); + continue; + + } + + /* + * Honour affinities which have been set in early boot + */ + desc = irq_to_desc(irq); + if (desc->status & + (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) + mask = desc->affinity; + else + mask = TARGET_CPUS; + #ifdef CONFIG_INTR_REMAP - else if (intr_remapping_enabled) - set_ir_ioapic_affinity_irq(irq, TARGET_CPUS); -#endif + if (intr_remapping_enabled) + set_ir_ioapic_affinity_irq(irq, mask); else - set_ioapic_affinity_irq(irq, TARGET_CPUS); +#endif + set_ioapic_affinity_irq(irq, mask); } } diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c index 60eb84eb77a0..1d3d0e71b044 100644 --- a/arch/x86/kernel/irq_64.c +++ b/arch/x86/kernel/irq_64.c @@ -18,7 +18,6 @@ #include #include -#ifdef CONFIG_DEBUG_STACKOVERFLOW /* * Probabilistic stack overflow check: * @@ -28,19 +27,18 @@ */ static inline void stack_overflow_check(struct pt_regs *regs) { +#ifdef CONFIG_DEBUG_STACKOVERFLOW u64 curbase = (u64)task_stack_page(current); - static unsigned long warned = -60*HZ; - - if (regs->sp >= curbase && regs->sp <= curbase + THREAD_SIZE && - regs->sp < curbase + sizeof(struct thread_info) + 128 && - time_after(jiffies, warned + 60*HZ)) { - printk("do_IRQ: %s near stack overflow (cur:%Lx,sp:%lx)\n", - current->comm, curbase, regs->sp); - show_stack(NULL,NULL); - warned = jiffies; - } -} + + WARN_ONCE(regs->sp >= curbase && + regs->sp <= curbase + THREAD_SIZE && + regs->sp < curbase + sizeof(struct thread_info) + + sizeof(struct pt_regs) + 128, + + "do_IRQ: %s near stack overflow (cur:%Lx,sp:%lx)\n", + current->comm, curbase, regs->sp); #endif +} /* * do_IRQ handles all normal device IRQ's (the special @@ -60,9 +58,7 @@ asmlinkage unsigned int do_IRQ(struct pt_regs *regs) irq_enter(); irq = __get_cpu_var(vector_irq)[vector]; -#ifdef CONFIG_DEBUG_STACKOVERFLOW stack_overflow_check(regs); -#endif desc = irq_to_desc(irq); if (likely(desc)) diff --git a/arch/x86/kernel/k8.c b/arch/x86/kernel/k8.c index 304d8bad6559..cbc4332a77b2 100644 --- a/arch/x86/kernel/k8.c +++ b/arch/x86/kernel/k8.c @@ -18,7 +18,6 @@ static u32 *flush_words; struct pci_device_id k8_nb_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, - { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, {} }; EXPORT_SYMBOL(k8_nb_ids); diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index 774ac4991568..e169ae9b6a62 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -128,7 +128,7 @@ static int kvm_register_clock(char *txt) } #ifdef CONFIG_X86_LOCAL_APIC -static void kvm_setup_secondary_clock(void) +static void __cpuinit kvm_setup_secondary_clock(void) { /* * Now that the first cpu already had this clocksource initialized, diff --git a/arch/x86/kernel/machine_kexec_32.c b/arch/x86/kernel/machine_kexec_32.c index 0732adba05ca..37f420018a41 100644 --- a/arch/x86/kernel/machine_kexec_32.c +++ b/arch/x86/kernel/machine_kexec_32.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -25,15 +26,6 @@ #include #include -#define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE))) -static u32 kexec_pgd[1024] PAGE_ALIGNED; -#ifdef CONFIG_X86_PAE -static u32 kexec_pmd0[1024] PAGE_ALIGNED; -static u32 kexec_pmd1[1024] PAGE_ALIGNED; -#endif -static u32 kexec_pte0[1024] PAGE_ALIGNED; -static u32 kexec_pte1[1024] PAGE_ALIGNED; - static void set_idt(void *newidt, __u16 limit) { struct desc_ptr curidt; @@ -76,6 +68,76 @@ static void load_segments(void) #undef __STR } +static void machine_kexec_free_page_tables(struct kimage *image) +{ + free_page((unsigned long)image->arch.pgd); +#ifdef CONFIG_X86_PAE + free_page((unsigned long)image->arch.pmd0); + free_page((unsigned long)image->arch.pmd1); +#endif + free_page((unsigned long)image->arch.pte0); + free_page((unsigned long)image->arch.pte1); +} + +static int machine_kexec_alloc_page_tables(struct kimage *image) +{ + image->arch.pgd = (pgd_t *)get_zeroed_page(GFP_KERNEL); +#ifdef CONFIG_X86_PAE + image->arch.pmd0 = (pmd_t *)get_zeroed_page(GFP_KERNEL); + image->arch.pmd1 = (pmd_t *)get_zeroed_page(GFP_KERNEL); +#endif + image->arch.pte0 = (pte_t *)get_zeroed_page(GFP_KERNEL); + image->arch.pte1 = (pte_t *)get_zeroed_page(GFP_KERNEL); + if (!image->arch.pgd || +#ifdef CONFIG_X86_PAE + !image->arch.pmd0 || !image->arch.pmd1 || +#endif + !image->arch.pte0 || !image->arch.pte1) { + machine_kexec_free_page_tables(image); + return -ENOMEM; + } + return 0; +} + +static void machine_kexec_page_table_set_one( + pgd_t *pgd, pmd_t *pmd, pte_t *pte, + unsigned long vaddr, unsigned long paddr) +{ + pud_t *pud; + + pgd += pgd_index(vaddr); +#ifdef CONFIG_X86_PAE + if (!(pgd_val(*pgd) & _PAGE_PRESENT)) + set_pgd(pgd, __pgd(__pa(pmd) | _PAGE_PRESENT)); +#endif + pud = pud_offset(pgd, vaddr); + pmd = pmd_offset(pud, vaddr); + if (!(pmd_val(*pmd) & _PAGE_PRESENT)) + set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE)); + pte = pte_offset_kernel(pmd, vaddr); + set_pte(pte, pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL_EXEC)); +} + +static void machine_kexec_prepare_page_tables(struct kimage *image) +{ + void *control_page; + pmd_t *pmd = 0; + + control_page = page_address(image->control_code_page); +#ifdef CONFIG_X86_PAE + pmd = image->arch.pmd0; +#endif + machine_kexec_page_table_set_one( + image->arch.pgd, pmd, image->arch.pte0, + (unsigned long)control_page, __pa(control_page)); +#ifdef CONFIG_X86_PAE + pmd = image->arch.pmd1; +#endif + machine_kexec_page_table_set_one( + image->arch.pgd, pmd, image->arch.pte1, + __pa(control_page), __pa(control_page)); +} + /* * A architecture hook called to validate the * proposed image and prepare the control pages @@ -87,12 +149,20 @@ static void load_segments(void) * reboot code buffer to allow us to avoid allocations * later. * - * Make control page executable. + * - Make control page executable. + * - Allocate page tables + * - Setup page tables */ int machine_kexec_prepare(struct kimage *image) { + int error; + if (nx_enabled) set_pages_x(image->control_code_page, 1); + error = machine_kexec_alloc_page_tables(image); + if (error) + return error; + machine_kexec_prepare_page_tables(image); return 0; } @@ -104,6 +174,7 @@ void machine_kexec_cleanup(struct kimage *image) { if (nx_enabled) set_pages_nx(image->control_code_page, 1); + machine_kexec_free_page_tables(image); } /* @@ -150,19 +221,11 @@ void machine_kexec(struct kimage *image) relocate_kernel_ptr = control_page; page_list[PA_CONTROL_PAGE] = __pa(control_page); page_list[VA_CONTROL_PAGE] = (unsigned long)control_page; - page_list[PA_PGD] = __pa(kexec_pgd); - page_list[VA_PGD] = (unsigned long)kexec_pgd; -#ifdef CONFIG_X86_PAE - page_list[PA_PMD_0] = __pa(kexec_pmd0); - page_list[VA_PMD_0] = (unsigned long)kexec_pmd0; - page_list[PA_PMD_1] = __pa(kexec_pmd1); - page_list[VA_PMD_1] = (unsigned long)kexec_pmd1; -#endif - page_list[PA_PTE_0] = __pa(kexec_pte0); - page_list[VA_PTE_0] = (unsigned long)kexec_pte0; - page_list[PA_PTE_1] = __pa(kexec_pte1); - page_list[VA_PTE_1] = (unsigned long)kexec_pte1; - page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) << PAGE_SHIFT); + page_list[PA_PGD] = __pa(image->arch.pgd); + + if (image->type == KEXEC_TYPE_DEFAULT) + page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) + << PAGE_SHIFT); /* The segment registers are funny things, they have both a * visible and an invisible part. Whenever the visible part is diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 7a1f8eeac2c7..c25fdb382292 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c @@ -10,7 +10,7 @@ * This driver allows to upgrade microcode on AMD * family 0x10 and 0x11 processors. * - * Licensed unter the terms of the GNU General Public + * Licensed under the terms of the GNU General Public * License version 2. See file COPYING for details. */ @@ -32,14 +32,14 @@ #include #include #include +#include #include -#include #include #include MODULE_DESCRIPTION("AMD Microcode Update Driver"); -MODULE_AUTHOR("Peter Oruba "); +MODULE_AUTHOR("Peter Oruba"); MODULE_LICENSE("GPL v2"); #define UCODE_MAGIC 0x00414d44 @@ -47,43 +47,38 @@ MODULE_LICENSE("GPL v2"); #define UCODE_UCODE_TYPE 0x00000001 struct equiv_cpu_entry { - unsigned int installed_cpu; - unsigned int fixed_errata_mask; - unsigned int fixed_errata_compare; - unsigned int equiv_cpu; -}; + u32 installed_cpu; + u32 fixed_errata_mask; + u32 fixed_errata_compare; + u16 equiv_cpu; + u16 res; +} __attribute__((packed)); struct microcode_header_amd { - unsigned int data_code; - unsigned int patch_id; - unsigned char mc_patch_data_id[2]; - unsigned char mc_patch_data_len; - unsigned char init_flag; - unsigned int mc_patch_data_checksum; - unsigned int nb_dev_id; - unsigned int sb_dev_id; - unsigned char processor_rev_id[2]; - unsigned char nb_rev_id; - unsigned char sb_rev_id; - unsigned char bios_api_rev; - unsigned char reserved1[3]; - unsigned int match_reg[8]; -}; + u32 data_code; + u32 patch_id; + u16 mc_patch_data_id; + u8 mc_patch_data_len; + u8 init_flag; + u32 mc_patch_data_checksum; + u32 nb_dev_id; + u32 sb_dev_id; + u16 processor_rev_id; + u8 nb_rev_id; + u8 sb_rev_id; + u8 bios_api_rev; + u8 reserved1[3]; + u32 match_reg[8]; +} __attribute__((packed)); struct microcode_amd { struct microcode_header_amd hdr; unsigned int mpb[0]; }; -#define UCODE_MAX_SIZE (2048) -#define DEFAULT_UCODE_DATASIZE (896) -#define MC_HEADER_SIZE (sizeof(struct microcode_header_amd)) -#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) -#define DWSIZE (sizeof(u32)) -/* For now we support a fixed ucode total size only */ -#define get_totalsize(mc) \ - ((((struct microcode_amd *)mc)->hdr.mc_patch_data_len * 28) \ - + MC_HEADER_SIZE) +#define UCODE_MAX_SIZE 2048 +#define UCODE_CONTAINER_SECTION_HDR 8 +#define UCODE_CONTAINER_HEADER_SIZE 12 /* serialize access to the physical write */ static DEFINE_SPINLOCK(microcode_update_lock); @@ -93,31 +88,24 @@ static struct equiv_cpu_entry *equiv_cpu_table; static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) { struct cpuinfo_x86 *c = &cpu_data(cpu); + u32 dummy; memset(csig, 0, sizeof(*csig)); - if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { - printk(KERN_ERR "microcode: CPU%d not a capable AMD processor\n", - cpu); + printk(KERN_WARNING "microcode: CPU%d: AMD CPU family 0x%x not " + "supported\n", cpu, c->x86); return -1; } - - asm volatile("movl %1, %%ecx; rdmsr" - : "=a" (csig->rev) - : "i" (0x0000008B) : "ecx"); - - printk(KERN_INFO "microcode: collect_cpu_info_amd : patch_id=0x%x\n", - csig->rev); - + rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); + printk(KERN_INFO "microcode: CPU%d: patch_level=0x%x\n", cpu, csig->rev); return 0; } static int get_matching_microcode(int cpu, void *mc, int rev) { struct microcode_header_amd *mc_header = mc; - struct pci_dev *nb_pci_dev, *sb_pci_dev; unsigned int current_cpu_id; - unsigned int equiv_cpu_id = 0x00; + u16 equiv_cpu_id = 0; unsigned int i = 0; BUG_ON(equiv_cpu_table == NULL); @@ -132,57 +120,25 @@ static int get_matching_microcode(int cpu, void *mc, int rev) } if (!equiv_cpu_id) { - printk(KERN_ERR "microcode: CPU%d cpu_id " - "not found in equivalent cpu table \n", cpu); + printk(KERN_WARNING "microcode: CPU%d: cpu revision " + "not listed in equivalent cpu table\n", cpu); return 0; } - if ((mc_header->processor_rev_id[0]) != (equiv_cpu_id & 0xff)) { - printk(KERN_ERR - "microcode: CPU%d patch does not match " - "(patch is %x, cpu extended is %x) \n", - cpu, mc_header->processor_rev_id[0], - (equiv_cpu_id & 0xff)); + if (mc_header->processor_rev_id != equiv_cpu_id) { + printk(KERN_ERR "microcode: CPU%d: patch mismatch " + "(processor_rev_id: %x, equiv_cpu_id: %x)\n", + cpu, mc_header->processor_rev_id, equiv_cpu_id); return 0; } - if ((mc_header->processor_rev_id[1]) != ((equiv_cpu_id >> 16) & 0xff)) { - printk(KERN_ERR "microcode: CPU%d patch does not match " - "(patch is %x, cpu base id is %x) \n", - cpu, mc_header->processor_rev_id[1], - ((equiv_cpu_id >> 16) & 0xff)); - + /* ucode might be chipset specific -- currently we don't support this */ + if (mc_header->nb_dev_id || mc_header->sb_dev_id) { + printk(KERN_ERR "microcode: CPU%d: loading of chipset " + "specific code not yet supported\n", cpu); return 0; } - /* ucode may be northbridge specific */ - if (mc_header->nb_dev_id) { - nb_pci_dev = pci_get_device(PCI_VENDOR_ID_AMD, - (mc_header->nb_dev_id & 0xff), - NULL); - if ((!nb_pci_dev) || - (mc_header->nb_rev_id != nb_pci_dev->revision)) { - printk(KERN_ERR "microcode: CPU%d NB mismatch \n", cpu); - pci_dev_put(nb_pci_dev); - return 0; - } - pci_dev_put(nb_pci_dev); - } - - /* ucode may be southbridge specific */ - if (mc_header->sb_dev_id) { - sb_pci_dev = pci_get_device(PCI_VENDOR_ID_AMD, - (mc_header->sb_dev_id & 0xff), - NULL); - if ((!sb_pci_dev) || - (mc_header->sb_rev_id != sb_pci_dev->revision)) { - printk(KERN_ERR "microcode: CPU%d SB mismatch \n", cpu); - pci_dev_put(sb_pci_dev); - return 0; - } - pci_dev_put(sb_pci_dev); - } - if (mc_header->patch_id <= rev) return 0; @@ -192,12 +148,10 @@ static int get_matching_microcode(int cpu, void *mc, int rev) static void apply_microcode_amd(int cpu) { unsigned long flags; - unsigned int eax, edx; - unsigned int rev; + u32 rev, dummy; int cpu_num = raw_smp_processor_id(); struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; struct microcode_amd *mc_amd = uci->mc; - unsigned long addr; /* We should bind the task to the CPU */ BUG_ON(cpu_num != cpu); @@ -206,42 +160,34 @@ static void apply_microcode_amd(int cpu) return; spin_lock_irqsave(µcode_update_lock, flags); - - addr = (unsigned long)&mc_amd->hdr.data_code; - edx = (unsigned int)(((unsigned long)upper_32_bits(addr))); - eax = (unsigned int)(((unsigned long)lower_32_bits(addr))); - - asm volatile("movl %0, %%ecx; wrmsr" : - : "i" (0xc0010020), "a" (eax), "d" (edx) : "ecx"); - + wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); /* get patch id after patching */ - asm volatile("movl %1, %%ecx; rdmsr" - : "=a" (rev) - : "i" (0x0000008B) : "ecx"); - + rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); spin_unlock_irqrestore(µcode_update_lock, flags); /* check current patch id and patch's id for match */ if (rev != mc_amd->hdr.patch_id) { - printk(KERN_ERR "microcode: CPU%d update from revision " - "0x%x to 0x%x failed\n", cpu_num, - mc_amd->hdr.patch_id, rev); + printk(KERN_ERR "microcode: CPU%d: update failed " + "(for patch_level=0x%x)\n", cpu, mc_amd->hdr.patch_id); return; } - printk(KERN_INFO "microcode: CPU%d updated from revision " - "0x%x to 0x%x \n", - cpu_num, uci->cpu_sig.rev, mc_amd->hdr.patch_id); + printk(KERN_INFO "microcode: CPU%d: updated (new patch_level=0x%x)\n", + cpu, rev); uci->cpu_sig.rev = rev; } -static void * get_next_ucode(u8 *buf, unsigned int size, - int (*get_ucode_data)(void *, const void *, size_t), - unsigned int *mc_size) +static int get_ucode_data(void *to, const u8 *from, size_t n) +{ + memcpy(to, from, n); + return 0; +} + +static void *get_next_ucode(const u8 *buf, unsigned int size, + unsigned int *mc_size) { unsigned int total_size; -#define UCODE_CONTAINER_SECTION_HDR 8 u8 section_hdr[UCODE_CONTAINER_SECTION_HDR]; void *mc; @@ -249,39 +195,37 @@ static void * get_next_ucode(u8 *buf, unsigned int size, return NULL; if (section_hdr[0] != UCODE_UCODE_TYPE) { - printk(KERN_ERR "microcode: error! " - "Wrong microcode payload type field\n"); + printk(KERN_ERR "microcode: error: invalid type field in " + "container file section header\n"); return NULL; } total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8)); - printk(KERN_INFO "microcode: size %u, total_size %u\n", - size, total_size); + printk(KERN_DEBUG "microcode: size %u, total_size %u\n", + size, total_size); if (total_size > size || total_size > UCODE_MAX_SIZE) { - printk(KERN_ERR "microcode: error! Bad data in microcode data file\n"); + printk(KERN_ERR "microcode: error: size mismatch\n"); return NULL; } mc = vmalloc(UCODE_MAX_SIZE); if (mc) { memset(mc, 0, UCODE_MAX_SIZE); - if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, total_size)) { + if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, + total_size)) { vfree(mc); mc = NULL; } else *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR; } -#undef UCODE_CONTAINER_SECTION_HDR return mc; } -static int install_equiv_cpu_table(u8 *buf, - int (*get_ucode_data)(void *, const void *, size_t)) +static int install_equiv_cpu_table(const u8 *buf) { -#define UCODE_CONTAINER_HEADER_SIZE 12 u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE]; unsigned int *buf_pos = (unsigned int *)container_hdr; unsigned long size; @@ -292,14 +236,15 @@ static int install_equiv_cpu_table(u8 *buf, size = buf_pos[2]; if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { - printk(KERN_ERR "microcode: error! " - "Wrong microcode equivalnet cpu table\n"); + printk(KERN_ERR "microcode: error: invalid type field in " + "container file section header\n"); return 0; } equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size); if (!equiv_cpu_table) { - printk(KERN_ERR "microcode: error, can't allocate memory for equiv CPU table\n"); + printk(KERN_ERR "microcode: failed to allocate " + "equivalent CPU table\n"); return 0; } @@ -310,7 +255,6 @@ static int install_equiv_cpu_table(u8 *buf, } return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */ -#undef UCODE_CONTAINER_HEADER_SIZE } static void free_equiv_cpu_table(void) @@ -321,18 +265,20 @@ static void free_equiv_cpu_table(void) } } -static int generic_load_microcode(int cpu, void *data, size_t size, - int (*get_ucode_data)(void *, const void *, size_t)) +static int generic_load_microcode(int cpu, const u8 *data, size_t size) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - u8 *ucode_ptr = data, *new_mc = NULL, *mc; + const u8 *ucode_ptr = data; + void *new_mc = NULL; + void *mc; int new_rev = uci->cpu_sig.rev; unsigned int leftover; unsigned long offset; - offset = install_equiv_cpu_table(ucode_ptr, get_ucode_data); + offset = install_equiv_cpu_table(ucode_ptr); if (!offset) { - printk(KERN_ERR "microcode: installing equivalent cpu table failed\n"); + printk(KERN_ERR "microcode: failed to create " + "equivalent cpu table\n"); return -EINVAL; } @@ -343,7 +289,7 @@ static int generic_load_microcode(int cpu, void *data, size_t size, unsigned int uninitialized_var(mc_size); struct microcode_header_amd *mc_header; - mc = get_next_ucode(ucode_ptr, leftover, get_ucode_data, &mc_size); + mc = get_next_ucode(ucode_ptr, leftover, &mc_size); if (!mc) break; @@ -353,7 +299,7 @@ static int generic_load_microcode(int cpu, void *data, size_t size, vfree(new_mc); new_rev = mc_header->patch_id; new_mc = mc; - } else + } else vfree(mc); ucode_ptr += mc_size; @@ -365,9 +311,9 @@ static int generic_load_microcode(int cpu, void *data, size_t size, if (uci->mc) vfree(uci->mc); uci->mc = new_mc; - pr_debug("microcode: CPU%d found a matching microcode update with" - " version 0x%x (current=0x%x)\n", - cpu, new_rev, uci->cpu_sig.rev); + pr_debug("microcode: CPU%d found a matching microcode " + "update with version 0x%x (current=0x%x)\n", + cpu, new_rev, uci->cpu_sig.rev); } else vfree(new_mc); } @@ -377,12 +323,6 @@ static int generic_load_microcode(int cpu, void *data, size_t size, return (int)leftover; } -static int get_ucode_fw(void *to, const void *from, size_t n) -{ - memcpy(to, from, n); - return 0; -} - static int request_microcode_fw(int cpu, struct device *device) { const char *fw_name = "amd-ucode/microcode_amd.bin"; @@ -394,12 +334,11 @@ static int request_microcode_fw(int cpu, struct device *device) ret = request_firmware(&firmware, fw_name, device); if (ret) { - printk(KERN_ERR "microcode: ucode data file %s load failed\n", fw_name); + printk(KERN_ERR "microcode: failed to load file %s\n", fw_name); return ret; } - ret = generic_load_microcode(cpu, (void*)firmware->data, firmware->size, - &get_ucode_fw); + ret = generic_load_microcode(cpu, firmware->data, firmware->size); release_firmware(firmware); @@ -408,8 +347,8 @@ static int request_microcode_fw(int cpu, struct device *device) static int request_microcode_user(int cpu, const void __user *buf, size_t size) { - printk(KERN_WARNING "microcode: AMD microcode update via /dev/cpu/microcode" - "is not supported\n"); + printk(KERN_INFO "microcode: AMD microcode update via " + "/dev/cpu/microcode not supported\n"); return -1; } @@ -433,3 +372,4 @@ struct microcode_ops * __init init_amd_microcode(void) { return µcode_amd_ops; } + diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 936d8d55f230..c9b721ba968c 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -99,7 +99,7 @@ MODULE_LICENSE("GPL"); #define MICROCODE_VERSION "2.00" -struct microcode_ops *microcode_ops; +static struct microcode_ops *microcode_ops; /* no concurrent ->write()s are allowed on /dev/cpu/microcode */ static DEFINE_MUTEX(microcode_mutex); @@ -203,7 +203,7 @@ MODULE_ALIAS_MISCDEV(MICROCODE_MINOR); #endif /* fake device for request_firmware */ -struct platform_device *microcode_pdev; +static struct platform_device *microcode_pdev; static ssize_t reload_store(struct sys_device *dev, struct sysdev_attribute *attr, @@ -272,13 +272,18 @@ static struct attribute_group mc_attr_group = { .name = "microcode", }; -static void microcode_fini_cpu(int cpu) +static void __microcode_fini_cpu(int cpu) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - mutex_lock(µcode_mutex); microcode_ops->microcode_fini_cpu(cpu); uci->valid = 0; +} + +static void microcode_fini_cpu(int cpu) +{ + mutex_lock(µcode_mutex); + __microcode_fini_cpu(cpu); mutex_unlock(µcode_mutex); } @@ -306,12 +311,16 @@ static int microcode_resume_cpu(int cpu) * to this cpu (a bit of paranoia): */ if (microcode_ops->collect_cpu_info(cpu, &nsig)) { - microcode_fini_cpu(cpu); + __microcode_fini_cpu(cpu); + printk(KERN_ERR "failed to collect_cpu_info for resuming cpu #%d\n", + cpu); return -1; } - if (memcmp(&nsig, &uci->cpu_sig, sizeof(nsig))) { - microcode_fini_cpu(cpu); + if ((nsig.sig != uci->cpu_sig.sig) || (nsig.pf != uci->cpu_sig.pf)) { + __microcode_fini_cpu(cpu); + printk(KERN_ERR "cached ucode doesn't match the resuming cpu #%d\n", + cpu); /* Should we look for a new ucode here? */ return 1; } @@ -319,7 +328,7 @@ static int microcode_resume_cpu(int cpu) return 0; } -void microcode_update_cpu(int cpu) +static void microcode_update_cpu(int cpu) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; int err = 0; @@ -480,8 +489,8 @@ static int __init microcode_init(void) printk(KERN_INFO "Microcode Update Driver: v" MICROCODE_VERSION - " " - " \n"); + " ," + " Peter Oruba\n"); return 0; } diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c index 622dc4a21784..b7f4c929e615 100644 --- a/arch/x86/kernel/microcode_intel.c +++ b/arch/x86/kernel/microcode_intel.c @@ -155,6 +155,7 @@ static DEFINE_SPINLOCK(microcode_update_lock); static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { struct cpuinfo_x86 *c = &cpu_data(cpu_num); + unsigned long flags; unsigned int val[2]; memset(csig, 0, sizeof(*csig)); @@ -174,11 +175,16 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) csig->pf = 1 << ((val[1] >> 18) & 7); } + /* serialize access to the physical write to MSR 0x79 */ + spin_lock_irqsave(µcode_update_lock, flags); + wrmsr(MSR_IA32_UCODE_REV, 0, 0); /* see notes above for revision 1.07. Apparent chip bug */ sync_core(); /* get the current revision from MSR 0x8B */ rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev); + spin_unlock_irqrestore(µcode_update_lock, flags); + pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n", csig->sig, csig->pf, csig->rev); @@ -465,7 +471,7 @@ static void microcode_fini_cpu(int cpu) uci->mc = NULL; } -struct microcode_ops microcode_intel_ops = { +static struct microcode_ops microcode_intel_ops = { .request_microcode_user = request_microcode_user, .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index f98f4e1dba09..45e3b69808ba 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -586,23 +586,23 @@ static void __init __get_smp_config(unsigned int early) { struct intel_mp_floating *mpf = mpf_found; - if (x86_quirks->mach_get_smp_config) { - if (x86_quirks->mach_get_smp_config(early)) - return; - } + if (!mpf) + return; + if (acpi_lapic && early) return; + /* - * ACPI supports both logical (e.g. Hyper-Threading) and physical - * processors, where MPS only supports physical. + * MPS doesn't support hyperthreading, aka only have + * thread 0 apic id in MPS table */ - if (acpi_lapic && acpi_ioapic) { - printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " - "information\n"); + if (acpi_lapic && acpi_ioapic) return; - } else if (acpi_lapic) - printk(KERN_INFO "Using ACPI for processor (LAPIC) " - "configuration information\n"); + + if (x86_quirks->mach_get_smp_config) { + if (x86_quirks->mach_get_smp_config(early)) + return; + } printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 2c97f07f1c2c..8bd1bf9622a7 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -131,6 +131,11 @@ static void report_broken_nmi(int cpu, int *prev_nmi_count) atomic_dec(&nmi_active); } +static void __acpi_nmi_disable(void *__unused) +{ + apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED); +} + int __init check_nmi_watchdog(void) { unsigned int *prev_nmi_count; @@ -179,8 +184,12 @@ int __init check_nmi_watchdog(void) kfree(prev_nmi_count); return 0; error: - if (nmi_watchdog == NMI_IO_APIC && !timer_through_8259) - disable_8259A_irq(0); + if (nmi_watchdog == NMI_IO_APIC) { + if (!timer_through_8259) + disable_8259A_irq(0); + on_each_cpu(__acpi_nmi_disable, NULL, 1); + } + #ifdef CONFIG_X86_32 timer_ack = 0; #endif @@ -199,12 +208,17 @@ static int __init setup_nmi_watchdog(char *str) ++str; } - get_option(&str, &nmi); - - if (nmi >= NMI_INVALID) - return 0; + if (!strncmp(str, "lapic", 5)) + nmi_watchdog = NMI_LOCAL_APIC; + else if (!strncmp(str, "ioapic", 6)) + nmi_watchdog = NMI_IO_APIC; + else { + get_option(&str, &nmi); + if (nmi >= NMI_INVALID) + return 0; + nmi_watchdog = nmi; + } - nmi_watchdog = nmi; return 1; } __setup("nmi_watchdog=", setup_nmi_watchdog); @@ -285,11 +299,6 @@ void acpi_nmi_enable(void) on_each_cpu(__acpi_nmi_enable, NULL, 1); } -static void __acpi_nmi_disable(void *__unused) -{ - apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED); -} - /* * Disable timer based NMIs on all CPUs: */ @@ -340,6 +349,8 @@ void stop_apic_nmi_watchdog(void *unused) return; if (nmi_watchdog == NMI_LOCAL_APIC) lapic_watchdog_stop(); + else + __acpi_nmi_disable(NULL); __get_cpu_var(wd_enabled) = 0; atomic_dec(&nmi_active); } @@ -465,6 +476,24 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason) #ifdef CONFIG_SYSCTL +static void enable_ioapic_nmi_watchdog_single(void *unused) +{ + __get_cpu_var(wd_enabled) = 1; + atomic_inc(&nmi_active); + __acpi_nmi_enable(NULL); +} + +static void enable_ioapic_nmi_watchdog(void) +{ + on_each_cpu(enable_ioapic_nmi_watchdog_single, NULL, 1); + touch_nmi_watchdog(); +} + +static void disable_ioapic_nmi_watchdog(void) +{ + on_each_cpu(stop_apic_nmi_watchdog, NULL, 1); +} + static int __init setup_unknown_nmi_panic(char *str) { unknown_nmi_panic = 1; @@ -507,6 +536,11 @@ int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file, enable_lapic_nmi_watchdog(); else disable_lapic_nmi_watchdog(); + } else if (nmi_watchdog == NMI_IO_APIC) { + if (nmi_watchdog_enabled) + enable_ioapic_nmi_watchdog(); + else + disable_ioapic_nmi_watchdog(); } else { printk(KERN_WARNING "NMI watchdog doesn't know what hardware to touch\n"); diff --git a/arch/x86/kernel/numaq_32.c b/arch/x86/kernel/numaq_32.c index 4caff39078e0..0deea37a53cf 100644 --- a/arch/x86/kernel/numaq_32.c +++ b/arch/x86/kernel/numaq_32.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include @@ -235,6 +235,13 @@ static int __init numaq_setup_ioapic_ids(void) return 1; } +static int __init numaq_update_genapic(void) +{ + genapic->wakeup_cpu = wakeup_secondary_cpu_via_nmi; + + return 0; +} + static struct x86_quirks numaq_x86_quirks __initdata = { .arch_pre_time_init = numaq_pre_time_init, .arch_time_init = NULL, @@ -250,6 +257,7 @@ static struct x86_quirks numaq_x86_quirks __initdata = { .mpc_oem_pci_bus = mpc_oem_pci_bus, .smp_read_mpc_oem = smp_read_mpc_oem, .setup_ioapic_ids = numaq_setup_ioapic_ids, + .update_genapic = numaq_update_genapic, }; void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem, diff --git a/arch/x86/kernel/paravirt-spinlocks.c b/arch/x86/kernel/paravirt-spinlocks.c index 0e9f1982b1dd..95777b0faa73 100644 --- a/arch/x86/kernel/paravirt-spinlocks.c +++ b/arch/x86/kernel/paravirt-spinlocks.c @@ -7,7 +7,8 @@ #include -static void default_spin_lock_flags(struct raw_spinlock *lock, unsigned long flags) +static inline void +default_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) { __raw_spin_lock(lock); } diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index e1e731d78f38..d28bbdc35e4e 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c @@ -1567,7 +1567,7 @@ static int __init calgary_parse_options(char *p) ++p; if (*p == '\0') break; - bridge = simple_strtol(p, &endp, 0); + bridge = simple_strtoul(p, &endp, 0); if (p == endp) break; diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 1972266e8ba5..dc572994703d 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -9,6 +9,8 @@ #include #include +static int forbid_dac __read_mostly; + struct dma_mapping_ops *dma_ops; EXPORT_SYMBOL(dma_ops); @@ -291,3 +293,17 @@ void pci_iommu_shutdown(void) } /* Must execute after PCI subsystem */ fs_initcall(pci_iommu_init); + +#ifdef CONFIG_PCI +/* Many VIA bridges seem to corrupt data for DAC. Disable it here */ + +static __devinit void via_no_dac(struct pci_dev *dev) +{ + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) { + printk(KERN_INFO + "PCI: VIA PCI bridge detected. Disabling DAC.\n"); + forbid_dac = 1; + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac); +#endif diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c index e3f75bbcedea..a35eaa379ff6 100644 --- a/arch/x86/kernel/pci-gart_64.c +++ b/arch/x86/kernel/pci-gart_64.c @@ -123,6 +123,8 @@ static void free_iommu(unsigned long offset, int size) spin_lock_irqsave(&iommu_bitmap_lock, flags); iommu_area_free(iommu_gart_bitmap, offset, size); + if (offset >= next_bit) + next_bit = offset + size; spin_unlock_irqrestore(&iommu_bitmap_lock, flags); } @@ -743,10 +745,8 @@ void __init gart_iommu_init(void) unsigned long scratch; long i; - if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) { - printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n"); + if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) return; - } #ifndef CONFIG_AGP_AMD64 no_agp = 1; diff --git a/arch/x86/kernel/pci-swiotlb_64.c b/arch/x86/kernel/pci-swiotlb_64.c index c4ce0332759e..3c539d111abb 100644 --- a/arch/x86/kernel/pci-swiotlb_64.c +++ b/arch/x86/kernel/pci-swiotlb_64.c @@ -18,9 +18,21 @@ swiotlb_map_single_phys(struct device *hwdev, phys_addr_t paddr, size_t size, return swiotlb_map_single(hwdev, phys_to_virt(paddr), size, direction); } +static void *x86_swiotlb_alloc_coherent(struct device *hwdev, size_t size, + dma_addr_t *dma_handle, gfp_t flags) +{ + void *vaddr; + + vaddr = dma_generic_alloc_coherent(hwdev, size, dma_handle, flags); + if (vaddr) + return vaddr; + + return swiotlb_alloc_coherent(hwdev, size, dma_handle, flags); +} + struct dma_mapping_ops swiotlb_dma_ops = { .mapping_error = swiotlb_dma_mapping_error, - .alloc_coherent = swiotlb_alloc_coherent, + .alloc_coherent = x86_swiotlb_alloc_coherent, .free_coherent = swiotlb_free_coherent, .map_single = swiotlb_map_single_phys, .unmap_single = swiotlb_unmap_single, diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index c622772744d8..9bfc3f719d47 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -8,6 +9,7 @@ #include #include #include +#include unsigned long idle_halt; EXPORT_SYMBOL(idle_halt); @@ -122,6 +124,21 @@ void default_idle(void) EXPORT_SYMBOL(default_idle); #endif +void stop_this_cpu(void *dummy) +{ + local_irq_disable(); + /* + * Remove this CPU: + */ + cpu_clear(smp_processor_id(), cpu_online_map); + disable_local_APIC(); + + for (;;) { + if (hlt_works(smp_processor_id())) + halt(); + } +} + static void do_nothing(void *unused) { } diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c index 0a6d8c12e10d..06180dff5b2e 100644 --- a/arch/x86/kernel/ptrace.c +++ b/arch/x86/kernel/ptrace.c @@ -929,17 +929,16 @@ void __cpuinit ptrace_bts_init_intel(struct cpuinfo_x86 *c) switch (c->x86) { case 0x6: switch (c->x86_model) { + case 0 ... 0xC: + /* sorry, don't know about them */ + break; case 0xD: case 0xE: /* Pentium M */ bts_configure(&bts_cfg_pentium_m); break; - case 0xF: /* Core2 */ - case 0x1C: /* Atom */ + default: /* Core2, Atom, ... */ bts_configure(&bts_cfg_core2); break; - default: - /* sorry, don't know about them */ - break; } break; case 0xF: diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index f4c93f1cfc19..61f718df6eec 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -21,6 +21,9 @@ # include #endif +#include + + /* * Power off function, if any */ @@ -29,18 +32,17 @@ EXPORT_SYMBOL(pm_power_off); static const struct desc_ptr no_idt = {}; static int reboot_mode; -/* - * Keyboard reset and triple fault may result in INIT, not RESET, which - * doesn't work when we're in vmx root mode. Try ACPI first. - */ -enum reboot_type reboot_type = BOOT_ACPI; +enum reboot_type reboot_type = BOOT_KBD; int reboot_force; #if defined(CONFIG_X86_32) && defined(CONFIG_SMP) static int reboot_cpu = -1; #endif -/* reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] +/* This is set by the PCI code if either type 1 or type 2 PCI is detected */ +bool port_cf9_safe = false; + +/* reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci] warm Don't set the cold reboot flag cold Set the cold reboot flag bios Reboot by jumping through the BIOS (only for X86_32) @@ -49,6 +51,7 @@ static int reboot_cpu = -1; kbd Use the keyboard controller. cold reset (default) acpi Use the RESET_REG in the FADT efi Use efi reset_system runtime service + pci Use the so-called "PCI reset register", CF9 force Avoid anything that could hang. */ static int __init reboot_setup(char *str) @@ -83,6 +86,7 @@ static int __init reboot_setup(char *str) case 'k': case 't': case 'e': + case 'p': reboot_type = *str; break; @@ -173,6 +177,15 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { DMI_MATCH(DMI_BOARD_NAME, "0KW626"), }, }, + { /* Handle problems with rebooting on Dell Optiplex 330 with 0KP561 */ + .callback = set_bios_reboot, + .ident = "Dell OptiPlex 330", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 330"), + DMI_MATCH(DMI_BOARD_NAME, "0KP561"), + }, + }, { /* Handle problems with rebooting on Dell 2400's */ .callback = set_bios_reboot, .ident = "Dell PowerEdge 2400", @@ -399,12 +412,27 @@ static void native_machine_emergency_restart(void) reboot_type = BOOT_KBD; break; - case BOOT_EFI: if (efi_enabled) - efi.reset_system(reboot_mode ? EFI_RESET_WARM : EFI_RESET_COLD, + efi.reset_system(reboot_mode ? + EFI_RESET_WARM : + EFI_RESET_COLD, EFI_SUCCESS, 0, NULL); + reboot_type = BOOT_KBD; + break; + + case BOOT_CF9: + port_cf9_safe = true; + /* fall through */ + case BOOT_CF9_COND: + if (port_cf9_safe) { + u8 cf9 = inb(0xcf9) & ~6; + outb(cf9|2, 0xcf9); /* Request hard reset */ + udelay(50); + outb(cf9|6, 0xcf9); /* Actually do the reset */ + udelay(50); + } reboot_type = BOOT_KBD; break; } @@ -465,6 +493,11 @@ static void native_machine_restart(char *__unused) static void native_machine_halt(void) { + /* stop other cpus and apics */ + machine_shutdown(); + + /* stop this cpu */ + stop_this_cpu(NULL); } static void native_machine_power_off(void) @@ -518,3 +551,95 @@ void machine_crash_shutdown(struct pt_regs *regs) machine_ops.crash_shutdown(regs); } #endif + + +#if defined(CONFIG_SMP) + +/* This keeps a track of which one is crashing cpu. */ +static int crashing_cpu; +static nmi_shootdown_cb shootdown_callback; + +static atomic_t waiting_for_crash_ipi; + +static int crash_nmi_callback(struct notifier_block *self, + unsigned long val, void *data) +{ + int cpu; + + if (val != DIE_NMI_IPI) + return NOTIFY_OK; + + cpu = raw_smp_processor_id(); + + /* Don't do anything if this handler is invoked on crashing cpu. + * Otherwise, system will completely hang. Crashing cpu can get + * an NMI if system was initially booted with nmi_watchdog parameter. + */ + if (cpu == crashing_cpu) + return NOTIFY_STOP; + local_irq_disable(); + + shootdown_callback(cpu, (struct die_args *)data); + + atomic_dec(&waiting_for_crash_ipi); + /* Assume hlt works */ + halt(); + for (;;) + cpu_relax(); + + return 1; +} + +static void smp_send_nmi_allbutself(void) +{ + cpumask_t mask = cpu_online_map; + cpu_clear(safe_smp_processor_id(), mask); + if (!cpus_empty(mask)) + send_IPI_mask(mask, NMI_VECTOR); +} + +static struct notifier_block crash_nmi_nb = { + .notifier_call = crash_nmi_callback, +}; + +/* Halt all other CPUs, calling the specified function on each of them + * + * This function can be used to halt all other CPUs on crash + * or emergency reboot time. The function passed as parameter + * will be called inside a NMI handler on all CPUs. + */ +void nmi_shootdown_cpus(nmi_shootdown_cb callback) +{ + unsigned long msecs; + local_irq_disable(); + + /* Make a note of crashing cpu. Will be used in NMI callback.*/ + crashing_cpu = safe_smp_processor_id(); + + shootdown_callback = callback; + + atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); + /* Would it be better to replace the trap vector here? */ + if (register_die_notifier(&crash_nmi_nb)) + return; /* return what? */ + /* Ensure the new callback function is set before sending + * out the NMI + */ + wmb(); + + smp_send_nmi_allbutself(); + + msecs = 1000; /* Wait at most a second for the other cpus to stop */ + while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) { + mdelay(1); + msecs--; + } + + /* Leave the nmi callback set */ +} +#else /* !CONFIG_SMP */ +void nmi_shootdown_cpus(nmi_shootdown_cb callback) +{ + /* No other CPUs to shoot down */ +} +#endif diff --git a/arch/x86/kernel/relocate_kernel_32.S b/arch/x86/kernel/relocate_kernel_32.S index 6f50664b2ba5..a160f3119725 100644 --- a/arch/x86/kernel/relocate_kernel_32.S +++ b/arch/x86/kernel/relocate_kernel_32.S @@ -10,15 +10,12 @@ #include #include #include -#include /* * Must be relocatable PIC code callable as a C function */ #define PTR(x) (x << 2) -#define PAGE_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) -#define PAE_PGD_ATTR (_PAGE_PRESENT) /* control_page + KEXEC_CONTROL_CODE_MAX_SIZE * ~ control_page + PAGE_SIZE are used as data storage and stack for @@ -39,7 +36,6 @@ #define CP_PA_BACKUP_PAGES_MAP DATA(0x1c) .text - .align PAGE_SIZE .globl relocate_kernel relocate_kernel: /* Save the CPU context, used for jumping back */ @@ -60,117 +56,6 @@ relocate_kernel: movl %cr4, %eax movl %eax, CR4(%edi) -#ifdef CONFIG_X86_PAE - /* map the control page at its virtual address */ - - movl PTR(VA_PGD)(%ebp), %edi - movl PTR(VA_CONTROL_PAGE)(%ebp), %eax - andl $0xc0000000, %eax - shrl $27, %eax - addl %edi, %eax - - movl PTR(PA_PMD_0)(%ebp), %edx - orl $PAE_PGD_ATTR, %edx - movl %edx, (%eax) - - movl PTR(VA_PMD_0)(%ebp), %edi - movl PTR(VA_CONTROL_PAGE)(%ebp), %eax - andl $0x3fe00000, %eax - shrl $18, %eax - addl %edi, %eax - - movl PTR(PA_PTE_0)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) - - movl PTR(VA_PTE_0)(%ebp), %edi - movl PTR(VA_CONTROL_PAGE)(%ebp), %eax - andl $0x001ff000, %eax - shrl $9, %eax - addl %edi, %eax - - movl PTR(PA_CONTROL_PAGE)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) - - /* identity map the control page at its physical address */ - - movl PTR(VA_PGD)(%ebp), %edi - movl PTR(PA_CONTROL_PAGE)(%ebp), %eax - andl $0xc0000000, %eax - shrl $27, %eax - addl %edi, %eax - - movl PTR(PA_PMD_1)(%ebp), %edx - orl $PAE_PGD_ATTR, %edx - movl %edx, (%eax) - - movl PTR(VA_PMD_1)(%ebp), %edi - movl PTR(PA_CONTROL_PAGE)(%ebp), %eax - andl $0x3fe00000, %eax - shrl $18, %eax - addl %edi, %eax - - movl PTR(PA_PTE_1)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) - - movl PTR(VA_PTE_1)(%ebp), %edi - movl PTR(PA_CONTROL_PAGE)(%ebp), %eax - andl $0x001ff000, %eax - shrl $9, %eax - addl %edi, %eax - - movl PTR(PA_CONTROL_PAGE)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) -#else - /* map the control page at its virtual address */ - - movl PTR(VA_PGD)(%ebp), %edi - movl PTR(VA_CONTROL_PAGE)(%ebp), %eax - andl $0xffc00000, %eax - shrl $20, %eax - addl %edi, %eax - - movl PTR(PA_PTE_0)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) - - movl PTR(VA_PTE_0)(%ebp), %edi - movl PTR(VA_CONTROL_PAGE)(%ebp), %eax - andl $0x003ff000, %eax - shrl $10, %eax - addl %edi, %eax - - movl PTR(PA_CONTROL_PAGE)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) - - /* identity map the control page at its physical address */ - - movl PTR(VA_PGD)(%ebp), %edi - movl PTR(PA_CONTROL_PAGE)(%ebp), %eax - andl $0xffc00000, %eax - shrl $20, %eax - addl %edi, %eax - - movl PTR(PA_PTE_1)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) - - movl PTR(VA_PTE_1)(%ebp), %edi - movl PTR(PA_CONTROL_PAGE)(%ebp), %eax - andl $0x003ff000, %eax - shrl $10, %eax - addl %edi, %eax - - movl PTR(PA_CONTROL_PAGE)(%ebp), %edx - orl $PAGE_ATTR, %edx - movl %edx, (%eax) -#endif - -relocate_new_kernel: /* read the arguments and say goodbye to the stack */ movl 20+4(%esp), %ebx /* page_list */ movl 20+8(%esp), %ebp /* list of pages */ diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 0fa6790c1dd3..a31223828597 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -98,6 +98,7 @@ #include #include +#include #include #include @@ -448,6 +449,7 @@ static void __init reserve_early_setup_data(void) * @size: Size of the crashkernel memory to reserve. * Returns the base address on success, and -1ULL on failure. */ +static unsigned long long __init find_and_reserve_crashkernel(unsigned long long size) { const unsigned long long alignment = 16<<20; /* 16M */ @@ -583,161 +585,24 @@ static int __init setup_elfcorehdr(char *arg) early_param("elfcorehdr", setup_elfcorehdr); #endif -static struct x86_quirks default_x86_quirks __initdata; - -struct x86_quirks *x86_quirks __initdata = &default_x86_quirks; - -/* - * Some BIOSes seem to corrupt the low 64k of memory during events - * like suspend/resume and unplugging an HDMI cable. Reserve all - * remaining free memory in that area and fill it with a distinct - * pattern. - */ -#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION -#define MAX_SCAN_AREAS 8 - -static int __read_mostly memory_corruption_check = -1; - -static unsigned __read_mostly corruption_check_size = 64*1024; -static unsigned __read_mostly corruption_check_period = 60; /* seconds */ - -static struct e820entry scan_areas[MAX_SCAN_AREAS]; -static int num_scan_areas; - - -static int set_corruption_check(char *arg) +static int __init default_update_genapic(void) { - char *end; - - memory_corruption_check = simple_strtol(arg, &end, 10); - - return (*end == 0) ? 0 : -EINVAL; -} -early_param("memory_corruption_check", set_corruption_check); - -static int set_corruption_check_period(char *arg) -{ - char *end; - - corruption_check_period = simple_strtoul(arg, &end, 10); - - return (*end == 0) ? 0 : -EINVAL; -} -early_param("memory_corruption_check_period", set_corruption_check_period); - -static int set_corruption_check_size(char *arg) -{ - char *end; - unsigned size; - - size = memparse(arg, &end); - - if (*end == '\0') - corruption_check_size = size; - - return (size == corruption_check_size) ? 0 : -EINVAL; -} -early_param("memory_corruption_check_size", set_corruption_check_size); - - -static void __init setup_bios_corruption_check(void) -{ - u64 addr = PAGE_SIZE; /* assume first page is reserved anyway */ - - if (memory_corruption_check == -1) { - memory_corruption_check = -#ifdef CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK - 1 -#else - 0 +#ifdef CONFIG_X86_SMP +# if defined(CONFIG_X86_GENERICARCH) || defined(CONFIG_X86_64) + genapic->wakeup_cpu = wakeup_secondary_cpu_via_init; +# endif #endif - ; - } - - if (corruption_check_size == 0) - memory_corruption_check = 0; - - if (!memory_corruption_check) - return; - - corruption_check_size = round_up(corruption_check_size, PAGE_SIZE); - - while(addr < corruption_check_size && num_scan_areas < MAX_SCAN_AREAS) { - u64 size; - addr = find_e820_area_size(addr, &size, PAGE_SIZE); - - if (addr == 0) - break; - if ((addr + size) > corruption_check_size) - size = corruption_check_size - addr; - - if (size == 0) - break; - - e820_update_range(addr, size, E820_RAM, E820_RESERVED); - scan_areas[num_scan_areas].addr = addr; - scan_areas[num_scan_areas].size = size; - num_scan_areas++; - - /* Assume we've already mapped this early memory */ - memset(__va(addr), 0, size); - - addr += size; - } - - printk(KERN_INFO "Scanning %d areas for low memory corruption\n", - num_scan_areas); - update_e820(); -} - -static struct timer_list periodic_check_timer; - -void check_for_bios_corruption(void) -{ - int i; - int corruption = 0; - - if (!memory_corruption_check) - return; - - for(i = 0; i < num_scan_areas; i++) { - unsigned long *addr = __va(scan_areas[i].addr); - unsigned long size = scan_areas[i].size; - - for(; size; addr++, size -= sizeof(unsigned long)) { - if (!*addr) - continue; - printk(KERN_ERR "Corrupted low memory at %p (%lx phys) = %08lx\n", - addr, __pa(addr), *addr); - corruption = 1; - *addr = 0; - } - } - - WARN(corruption, KERN_ERR "Memory corruption detected in low memory\n"); -} - -static void periodic_check_for_corruption(unsigned long data) -{ - check_for_bios_corruption(); - mod_timer(&periodic_check_timer, round_jiffies(jiffies + corruption_check_period*HZ)); + return 0; } -void start_periodic_check_for_corruption(void) -{ - if (!memory_corruption_check || corruption_check_period == 0) - return; - - printk(KERN_INFO "Scanning for low memory corruption every %d seconds\n", - corruption_check_period); +static struct x86_quirks default_x86_quirks __initdata = { + .update_genapic = default_update_genapic, +}; - init_timer(&periodic_check_timer); - periodic_check_timer.function = &periodic_check_for_corruption; - periodic_check_for_corruption(0); -} -#endif +struct x86_quirks *x86_quirks __initdata = &default_x86_quirks; +#ifdef CONFIG_X86_RESERVE_LOW_64K static int __init dmi_low_memory_corruption(const struct dmi_system_id *d) { printk(KERN_NOTICE @@ -749,6 +614,7 @@ static int __init dmi_low_memory_corruption(const struct dmi_system_id *d) return 0; } +#endif /* List of systems that have known low memory corruption BIOS problems */ static struct dmi_system_id __initdata bad_bios_dmi_table[] = { @@ -764,7 +630,7 @@ static struct dmi_system_id __initdata bad_bios_dmi_table[] = { .callback = dmi_low_memory_corruption, .ident = "Phoenix BIOS", .matches = { - DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"), + DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies"), }, }, #endif @@ -794,6 +660,9 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Command line: %s\n", boot_command_line); #endif + /* VMI may relocate the fixmap; do this before touching ioremap area */ + vmi_init(); + early_cpu_init(); early_ioremap_init(); @@ -880,13 +749,8 @@ void __init setup_arch(char **cmdline_p) check_efer(); #endif -#if defined(CONFIG_VMI) && defined(CONFIG_X86_32) - /* - * Must be before kernel pagetables are setup - * or fixmap area is touched. - */ - vmi_init(); -#endif + /* Must be before kernel pagetables are setup */ + vmi_activate(); /* after early param, so could get panic from serial */ reserve_early_setup_data(); @@ -909,6 +773,12 @@ void __init setup_arch(char **cmdline_p) dmi_check_system(bad_bios_dmi_table); + /* + * VMware detection requires dmi to be available, so this + * needs to be done after dmi_scan_machine, for the BP. + */ + init_hypervisor(&boot_cpu_data); + #ifdef CONFIG_X86_32 probe_roms(); #endif diff --git a/arch/x86/kernel/sigframe.h b/arch/x86/kernel/sigframe.h deleted file mode 100644 index cc673aa55ce4..000000000000 --- a/arch/x86/kernel/sigframe.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifdef CONFIG_X86_32 -struct sigframe { - char __user *pretcode; - int sig; - struct sigcontext sc; - /* - * fpstate is unused. fpstate is moved/allocated after - * retcode[] below. This movement allows to have the FP state and the - * future state extensions (xsave) stay together. - * And at the same time retaining the unused fpstate, prevents changing - * the offset of extramask[] in the sigframe and thus prevent any - * legacy application accessing/modifying it. - */ - struct _fpstate fpstate_unused; - unsigned long extramask[_NSIG_WORDS-1]; - char retcode[8]; - /* fp state follows here */ -}; - -struct rt_sigframe { - char __user *pretcode; - int sig; - struct siginfo __user *pinfo; - void __user *puc; - struct siginfo info; - struct ucontext uc; - char retcode[8]; - /* fp state follows here */ -}; -#else -struct rt_sigframe { - char __user *pretcode; - struct ucontext uc; - struct siginfo info; - /* fp state follows here */ -}; - -int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs); -int ia32_setup_frame(int sig, struct k_sigaction *ka, - sigset_t *set, struct pt_regs *regs); -#endif diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c new file mode 100644 index 000000000000..89bb7668041d --- /dev/null +++ b/arch/x86/kernel/signal.c @@ -0,0 +1,909 @@ +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs + * + * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson + * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes + * 2000-2002 x86-64 support by Andi Kleen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_X86_64 +#include +#include +#include +#endif /* CONFIG_X86_64 */ + +#include +#include + +#include + +#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) + +#define __FIX_EFLAGS (X86_EFLAGS_AC | X86_EFLAGS_OF | \ + X86_EFLAGS_DF | X86_EFLAGS_TF | X86_EFLAGS_SF | \ + X86_EFLAGS_ZF | X86_EFLAGS_AF | X86_EFLAGS_PF | \ + X86_EFLAGS_CF) + +#ifdef CONFIG_X86_32 +# define FIX_EFLAGS (__FIX_EFLAGS | X86_EFLAGS_RF) +#else +# define FIX_EFLAGS __FIX_EFLAGS +#endif + +#define COPY(x) { \ + err |= __get_user(regs->x, &sc->x); \ +} + +#define COPY_SEG(seg) { \ + unsigned short tmp; \ + err |= __get_user(tmp, &sc->seg); \ + regs->seg = tmp; \ +} + +#define COPY_SEG_CPL3(seg) { \ + unsigned short tmp; \ + err |= __get_user(tmp, &sc->seg); \ + regs->seg = tmp | 3; \ +} + +#define GET_SEG(seg) { \ + unsigned short tmp; \ + err |= __get_user(tmp, &sc->seg); \ + loadsegment(seg, tmp); \ +} + +static int +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, + unsigned long *pax) +{ + void __user *buf; + unsigned int tmpflags; + unsigned int err = 0; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + +#ifdef CONFIG_X86_32 + GET_SEG(gs); + COPY_SEG(fs); + COPY_SEG(es); + COPY_SEG(ds); +#endif /* CONFIG_X86_32 */ + + COPY(di); COPY(si); COPY(bp); COPY(sp); COPY(bx); + COPY(dx); COPY(cx); COPY(ip); + +#ifdef CONFIG_X86_64 + COPY(r8); + COPY(r9); + COPY(r10); + COPY(r11); + COPY(r12); + COPY(r13); + COPY(r14); + COPY(r15); +#endif /* CONFIG_X86_64 */ + +#ifdef CONFIG_X86_32 + COPY_SEG_CPL3(cs); + COPY_SEG_CPL3(ss); +#else /* !CONFIG_X86_32 */ + /* Kernel saves and restores only the CS segment register on signals, + * which is the bare minimum needed to allow mixed 32/64-bit code. + * App's signal handler can save/restore other segments if needed. */ + COPY_SEG_CPL3(cs); +#endif /* CONFIG_X86_32 */ + + err |= __get_user(tmpflags, &sc->flags); + regs->flags = (regs->flags & ~FIX_EFLAGS) | (tmpflags & FIX_EFLAGS); + regs->orig_ax = -1; /* disable syscall checks */ + + err |= __get_user(buf, &sc->fpstate); + err |= restore_i387_xstate(buf); + + err |= __get_user(*pax, &sc->ax); + return err; +} + +static int +setup_sigcontext(struct sigcontext __user *sc, void __user *fpstate, + struct pt_regs *regs, unsigned long mask) +{ + int err = 0; + +#ifdef CONFIG_X86_32 + { + unsigned int tmp; + + savesegment(gs, tmp); + err |= __put_user(tmp, (unsigned int __user *)&sc->gs); + } + err |= __put_user(regs->fs, (unsigned int __user *)&sc->fs); + err |= __put_user(regs->es, (unsigned int __user *)&sc->es); + err |= __put_user(regs->ds, (unsigned int __user *)&sc->ds); +#endif /* CONFIG_X86_32 */ + + err |= __put_user(regs->di, &sc->di); + err |= __put_user(regs->si, &sc->si); + err |= __put_user(regs->bp, &sc->bp); + err |= __put_user(regs->sp, &sc->sp); + err |= __put_user(regs->bx, &sc->bx); + err |= __put_user(regs->dx, &sc->dx); + err |= __put_user(regs->cx, &sc->cx); + err |= __put_user(regs->ax, &sc->ax); +#ifdef CONFIG_X86_64 + err |= __put_user(regs->r8, &sc->r8); + err |= __put_user(regs->r9, &sc->r9); + err |= __put_user(regs->r10, &sc->r10); + err |= __put_user(regs->r11, &sc->r11); + err |= __put_user(regs->r12, &sc->r12); + err |= __put_user(regs->r13, &sc->r13); + err |= __put_user(regs->r14, &sc->r14); + err |= __put_user(regs->r15, &sc->r15); +#endif /* CONFIG_X86_64 */ + + err |= __put_user(current->thread.trap_no, &sc->trapno); + err |= __put_user(current->thread.error_code, &sc->err); + err |= __put_user(regs->ip, &sc->ip); +#ifdef CONFIG_X86_32 + err |= __put_user(regs->cs, (unsigned int __user *)&sc->cs); + err |= __put_user(regs->flags, &sc->flags); + err |= __put_user(regs->sp, &sc->sp_at_signal); + err |= __put_user(regs->ss, (unsigned int __user *)&sc->ss); +#else /* !CONFIG_X86_32 */ + err |= __put_user(regs->flags, &sc->flags); + err |= __put_user(regs->cs, &sc->cs); + err |= __put_user(0, &sc->gs); + err |= __put_user(0, &sc->fs); +#endif /* CONFIG_X86_32 */ + + err |= __put_user(fpstate, &sc->fpstate); + + /* non-iBCS2 extensions.. */ + err |= __put_user(mask, &sc->oldmask); + err |= __put_user(current->thread.cr2, &sc->cr2); + + return err; +} + +/* + * Set up a signal frame. + */ +#ifdef CONFIG_X86_32 +static const struct { + u16 poplmovl; + u32 val; + u16 int80; +} __attribute__((packed)) retcode = { + 0xb858, /* popl %eax; movl $..., %eax */ + __NR_sigreturn, + 0x80cd, /* int $0x80 */ +}; + +static const struct { + u8 movl; + u32 val; + u16 int80; + u8 pad; +} __attribute__((packed)) rt_retcode = { + 0xb8, /* movl $..., %eax */ + __NR_rt_sigreturn, + 0x80cd, /* int $0x80 */ + 0 +}; + +/* + * Determine which stack to use.. + */ +static inline void __user * +get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size, + void **fpstate) +{ + unsigned long sp; + + /* Default to using normal stack */ + sp = regs->sp; + + /* + * If we are on the alternate signal stack and would overflow it, don't. + * Return an always-bogus address instead so we will die with SIGSEGV. + */ + if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size))) + return (void __user *) -1L; + + /* This is the X/Open sanctioned signal stack switching. */ + if (ka->sa.sa_flags & SA_ONSTACK) { + if (sas_ss_flags(sp) == 0) + sp = current->sas_ss_sp + current->sas_ss_size; + } else { + /* This is the legacy signal stack switching. */ + if ((regs->ss & 0xffff) != __USER_DS && + !(ka->sa.sa_flags & SA_RESTORER) && + ka->sa.sa_restorer) + sp = (unsigned long) ka->sa.sa_restorer; + } + + if (used_math()) { + sp = sp - sig_xstate_size; + *fpstate = (struct _fpstate *) sp; + if (save_i387_xstate(*fpstate) < 0) + return (void __user *)-1L; + } + + sp -= frame_size; + /* + * Align the stack pointer according to the i386 ABI, + * i.e. so that on function entry ((sp + 4) & 15) == 0. + */ + sp = ((sp + 4) & -16ul) - 4; + + return (void __user *) sp; +} + +static int +__setup_frame(int sig, struct k_sigaction *ka, sigset_t *set, + struct pt_regs *regs) +{ + struct sigframe __user *frame; + void __user *restorer; + int err = 0; + void __user *fpstate = NULL; + + frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + if (__put_user(sig, &frame->sig)) + return -EFAULT; + + if (setup_sigcontext(&frame->sc, fpstate, regs, set->sig[0])) + return -EFAULT; + + if (_NSIG_WORDS > 1) { + if (__copy_to_user(&frame->extramask, &set->sig[1], + sizeof(frame->extramask))) + return -EFAULT; + } + + if (current->mm->context.vdso) + restorer = VDSO32_SYMBOL(current->mm->context.vdso, sigreturn); + else + restorer = &frame->retcode; + if (ka->sa.sa_flags & SA_RESTORER) + restorer = ka->sa.sa_restorer; + + /* Set up to return from userspace. */ + err |= __put_user(restorer, &frame->pretcode); + + /* + * This is popl %eax ; movl $__NR_sigreturn, %eax ; int $0x80 + * + * WE DO NOT USE IT ANY MORE! It's only left here for historical + * reasons and because gdb uses it as a signature to notice + * signal handler stack frames. + */ + err |= __put_user(*((u64 *)&retcode), (u64 *)frame->retcode); + + if (err) + return -EFAULT; + + /* Set up registers for signal handler */ + regs->sp = (unsigned long)frame; + regs->ip = (unsigned long)ka->sa.sa_handler; + regs->ax = (unsigned long)sig; + regs->dx = 0; + regs->cx = 0; + + regs->ds = __USER_DS; + regs->es = __USER_DS; + regs->ss = __USER_DS; + regs->cs = __USER_CS; + + return 0; +} + +static int __setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + void __user *restorer; + int err = 0; + void __user *fpstate = NULL; + + frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + err |= __put_user(sig, &frame->sig); + err |= __put_user(&frame->info, &frame->pinfo); + err |= __put_user(&frame->uc, &frame->puc); + err |= copy_siginfo_to_user(&frame->info, info); + if (err) + return -EFAULT; + + /* Create the ucontext. */ + if (cpu_has_xsave) + err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags); + else + err |= __put_user(0, &frame->uc.uc_flags); + err |= __put_user(0, &frame->uc.uc_link); + err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); + err |= __put_user(sas_ss_flags(regs->sp), + &frame->uc.uc_stack.ss_flags); + err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); + err |= setup_sigcontext(&frame->uc.uc_mcontext, fpstate, + regs, set->sig[0]); + err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); + if (err) + return -EFAULT; + + /* Set up to return from userspace. */ + restorer = VDSO32_SYMBOL(current->mm->context.vdso, rt_sigreturn); + if (ka->sa.sa_flags & SA_RESTORER) + restorer = ka->sa.sa_restorer; + err |= __put_user(restorer, &frame->pretcode); + + /* + * This is movl $__NR_rt_sigreturn, %ax ; int $0x80 + * + * WE DO NOT USE IT ANY MORE! It's only left here for historical + * reasons and because gdb uses it as a signature to notice + * signal handler stack frames. + */ + err |= __put_user(*((u64 *)&rt_retcode), (u64 *)frame->retcode); + + if (err) + return -EFAULT; + + /* Set up registers for signal handler */ + regs->sp = (unsigned long)frame; + regs->ip = (unsigned long)ka->sa.sa_handler; + regs->ax = (unsigned long)sig; + regs->dx = (unsigned long)&frame->info; + regs->cx = (unsigned long)&frame->uc; + + regs->ds = __USER_DS; + regs->es = __USER_DS; + regs->ss = __USER_DS; + regs->cs = __USER_CS; + + return 0; +} +#else /* !CONFIG_X86_32 */ +/* + * Determine which stack to use.. + */ +static void __user * +get_stack(struct k_sigaction *ka, unsigned long sp, unsigned long size) +{ + /* Default to using normal stack - redzone*/ + sp -= 128; + + /* This is the X/Open sanctioned signal stack switching. */ + if (ka->sa.sa_flags & SA_ONSTACK) { + if (sas_ss_flags(sp) == 0) + sp = current->sas_ss_sp + current->sas_ss_size; + } + + return (void __user *)round_down(sp - size, 64); +} + +static int __setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + void __user *fp = NULL; + int err = 0; + struct task_struct *me = current; + + if (used_math()) { + fp = get_stack(ka, regs->sp, sig_xstate_size); + frame = (void __user *)round_down( + (unsigned long)fp - sizeof(struct rt_sigframe), 16) - 8; + + if (save_i387_xstate(fp) < 0) + return -EFAULT; + } else + frame = get_stack(ka, regs->sp, sizeof(struct rt_sigframe)) - 8; + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + if (ka->sa.sa_flags & SA_SIGINFO) { + if (copy_siginfo_to_user(&frame->info, info)) + return -EFAULT; + } + + /* Create the ucontext. */ + if (cpu_has_xsave) + err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags); + else + err |= __put_user(0, &frame->uc.uc_flags); + err |= __put_user(0, &frame->uc.uc_link); + err |= __put_user(me->sas_ss_sp, &frame->uc.uc_stack.ss_sp); + err |= __put_user(sas_ss_flags(regs->sp), + &frame->uc.uc_stack.ss_flags); + err |= __put_user(me->sas_ss_size, &frame->uc.uc_stack.ss_size); + err |= setup_sigcontext(&frame->uc.uc_mcontext, fp, regs, set->sig[0]); + err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); + + /* Set up to return from userspace. If provided, use a stub + already in userspace. */ + /* x86-64 should always use SA_RESTORER. */ + if (ka->sa.sa_flags & SA_RESTORER) { + err |= __put_user(ka->sa.sa_restorer, &frame->pretcode); + } else { + /* could use a vstub here */ + return -EFAULT; + } + + if (err) + return -EFAULT; + + /* Set up registers for signal handler */ + regs->di = sig; + /* In case the signal handler was declared without prototypes */ + regs->ax = 0; + + /* This also works for non SA_SIGINFO handlers because they expect the + next argument after the signal number on the stack. */ + regs->si = (unsigned long)&frame->info; + regs->dx = (unsigned long)&frame->uc; + regs->ip = (unsigned long) ka->sa.sa_handler; + + regs->sp = (unsigned long)frame; + + /* Set up the CS register to run signal handlers in 64-bit mode, + even if the handler happens to be interrupting 32-bit code. */ + regs->cs = __USER_CS; + + return 0; +} +#endif /* CONFIG_X86_32 */ + +#ifdef CONFIG_X86_32 +/* + * Atomically swap in the new signal mask, and wait for a signal. + */ +asmlinkage int +sys_sigsuspend(int history0, int history1, old_sigset_t mask) +{ + mask &= _BLOCKABLE; + spin_lock_irq(¤t->sighand->siglock); + current->saved_sigmask = current->blocked; + siginitset(¤t->blocked, mask); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + current->state = TASK_INTERRUPTIBLE; + schedule(); + set_restore_sigmask(); + + return -ERESTARTNOHAND; +} + +asmlinkage int +sys_sigaction(int sig, const struct old_sigaction __user *act, + struct old_sigaction __user *oact) +{ + struct k_sigaction new_ka, old_ka; + int ret; + + if (act) { + old_sigset_t mask; + + if (!access_ok(VERIFY_READ, act, sizeof(*act)) || + __get_user(new_ka.sa.sa_handler, &act->sa_handler) || + __get_user(new_ka.sa.sa_restorer, &act->sa_restorer)) + return -EFAULT; + + __get_user(new_ka.sa.sa_flags, &act->sa_flags); + __get_user(mask, &act->sa_mask); + siginitset(&new_ka.sa.sa_mask, mask); + } + + ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); + + if (!ret && oact) { + if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || + __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || + __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer)) + return -EFAULT; + + __put_user(old_ka.sa.sa_flags, &oact->sa_flags); + __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); + } + + return ret; +} +#endif /* CONFIG_X86_32 */ + +#ifdef CONFIG_X86_32 +asmlinkage int sys_sigaltstack(unsigned long bx) +{ + /* + * This is needed to make gcc realize it doesn't own the + * "struct pt_regs" + */ + struct pt_regs *regs = (struct pt_regs *)&bx; + const stack_t __user *uss = (const stack_t __user *)bx; + stack_t __user *uoss = (stack_t __user *)regs->cx; + + return do_sigaltstack(uss, uoss, regs->sp); +} +#else /* !CONFIG_X86_32 */ +asmlinkage long +sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, + struct pt_regs *regs) +{ + return do_sigaltstack(uss, uoss, regs->sp); +} +#endif /* CONFIG_X86_32 */ + +/* + * Do a signal return; undo the signal stack. + */ +#ifdef CONFIG_X86_32 +asmlinkage unsigned long sys_sigreturn(unsigned long __unused) +{ + struct sigframe __user *frame; + struct pt_regs *regs; + unsigned long ax; + sigset_t set; + + regs = (struct pt_regs *) &__unused; + frame = (struct sigframe __user *)(regs->sp - 8); + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__get_user(set.sig[0], &frame->sc.oldmask) || (_NSIG_WORDS > 1 + && __copy_from_user(&set.sig[1], &frame->extramask, + sizeof(frame->extramask)))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + spin_lock_irq(¤t->sighand->siglock); + current->blocked = set; + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + if (restore_sigcontext(regs, &frame->sc, &ax)) + goto badframe; + return ax; + +badframe: + signal_fault(regs, frame, "sigreturn"); + + return 0; +} +#endif /* CONFIG_X86_32 */ + +static long do_rt_sigreturn(struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + unsigned long ax; + sigset_t set; + + frame = (struct rt_sigframe __user *)(regs->sp - sizeof(long)); + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) + goto badframe; + + sigdelsetmask(&set, ~_BLOCKABLE); + spin_lock_irq(¤t->sighand->siglock); + current->blocked = set; + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &ax)) + goto badframe; + + if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT) + goto badframe; + + return ax; + +badframe: + signal_fault(regs, frame, "rt_sigreturn"); + return 0; +} + +#ifdef CONFIG_X86_32 +asmlinkage int sys_rt_sigreturn(struct pt_regs regs) +{ + return do_rt_sigreturn(®s); +} +#else /* !CONFIG_X86_32 */ +asmlinkage long sys_rt_sigreturn(struct pt_regs *regs) +{ + return do_rt_sigreturn(regs); +} +#endif /* CONFIG_X86_32 */ + +/* + * OK, we're invoking a handler: + */ +static int signr_convert(int sig) +{ +#ifdef CONFIG_X86_32 + struct thread_info *info = current_thread_info(); + + if (info->exec_domain && info->exec_domain->signal_invmap && sig < 32) + return info->exec_domain->signal_invmap[sig]; +#endif /* CONFIG_X86_32 */ + return sig; +} + +#ifdef CONFIG_X86_32 + +#define is_ia32 1 +#define ia32_setup_frame __setup_frame +#define ia32_setup_rt_frame __setup_rt_frame + +#else /* !CONFIG_X86_32 */ + +#ifdef CONFIG_IA32_EMULATION +#define is_ia32 test_thread_flag(TIF_IA32) +#else /* !CONFIG_IA32_EMULATION */ +#define is_ia32 0 +#endif /* CONFIG_IA32_EMULATION */ + +int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs); +int ia32_setup_frame(int sig, struct k_sigaction *ka, + sigset_t *set, struct pt_regs *regs); + +#endif /* CONFIG_X86_32 */ + +static int +setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) +{ + int usig = signr_convert(sig); + int ret; + + /* Set up the stack frame */ + if (is_ia32) { + if (ka->sa.sa_flags & SA_SIGINFO) + ret = ia32_setup_rt_frame(usig, ka, info, set, regs); + else + ret = ia32_setup_frame(usig, ka, set, regs); + } else + ret = __setup_rt_frame(sig, ka, info, set, regs); + + if (ret) { + force_sigsegv(sig, current); + return -EFAULT; + } + + return ret; +} + +static int +handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, + sigset_t *oldset, struct pt_regs *regs) +{ + int ret; + + /* Are we from a system call? */ + if (syscall_get_nr(current, regs) >= 0) { + /* If so, check system call restarting.. */ + switch (syscall_get_error(current, regs)) { + case -ERESTART_RESTARTBLOCK: + case -ERESTARTNOHAND: + regs->ax = -EINTR; + break; + + case -ERESTARTSYS: + if (!(ka->sa.sa_flags & SA_RESTART)) { + regs->ax = -EINTR; + break; + } + /* fallthrough */ + case -ERESTARTNOINTR: + regs->ax = regs->orig_ax; + regs->ip -= 2; + break; + } + } + + /* + * If TF is set due to a debugger (TIF_FORCED_TF), clear the TF + * flag so that register information in the sigcontext is correct. + */ + if (unlikely(regs->flags & X86_EFLAGS_TF) && + likely(test_and_clear_thread_flag(TIF_FORCED_TF))) + regs->flags &= ~X86_EFLAGS_TF; + + ret = setup_rt_frame(sig, ka, info, oldset, regs); + + if (ret) + return ret; + +#ifdef CONFIG_X86_64 + /* + * This has nothing to do with segment registers, + * despite the name. This magic affects uaccess.h + * macros' behavior. Reset it to the normal setting. + */ + set_fs(USER_DS); +#endif + + /* + * Clear the direction flag as per the ABI for function entry. + */ + regs->flags &= ~X86_EFLAGS_DF; + + /* + * Clear TF when entering the signal handler, but + * notify any tracer that was single-stepping it. + * The tracer may want to single-step inside the + * handler too. + */ + regs->flags &= ~X86_EFLAGS_TF; + + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(¤t->blocked, sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + tracehook_signal_handler(sig, info, ka, regs, + test_thread_flag(TIF_SINGLESTEP)); + + return 0; +} + +#ifdef CONFIG_X86_32 +#define NR_restart_syscall __NR_restart_syscall +#else /* !CONFIG_X86_32 */ +#define NR_restart_syscall \ + test_thread_flag(TIF_IA32) ? __NR_ia32_restart_syscall : __NR_restart_syscall +#endif /* CONFIG_X86_32 */ + +/* + * Note that 'init' is a special process: it doesn't get signals it doesn't + * want to handle. Thus you cannot kill init even with a SIGKILL even by + * mistake. + */ +static void do_signal(struct pt_regs *regs) +{ + struct k_sigaction ka; + siginfo_t info; + int signr; + sigset_t *oldset; + + /* + * We want the common case to go fast, which is why we may in certain + * cases get here from kernel mode. Just return without doing anything + * if so. + * X86_32: vm86 regs switched out by assembly code before reaching + * here, so testing against kernel CS suffices. + */ + if (!user_mode(regs)) + return; + + if (current_thread_info()->status & TS_RESTORE_SIGMASK) + oldset = ¤t->saved_sigmask; + else + oldset = ¤t->blocked; + + signr = get_signal_to_deliver(&info, &ka, regs, NULL); + if (signr > 0) { + /* + * Re-enable any watchpoints before delivering the + * signal to user space. The processor register will + * have been cleared if the watchpoint triggered + * inside the kernel. + */ + if (current->thread.debugreg7) + set_debugreg(current->thread.debugreg7, 7); + + /* Whee! Actually deliver the signal. */ + if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { + /* + * A signal was successfully delivered; the saved + * sigmask will have been stored in the signal frame, + * and will be restored by sigreturn, so we can simply + * clear the TS_RESTORE_SIGMASK flag. + */ + current_thread_info()->status &= ~TS_RESTORE_SIGMASK; + } + return; + } + + /* Did we come from a system call? */ + if (syscall_get_nr(current, regs) >= 0) { + /* Restart the system call - no handlers present */ + switch (syscall_get_error(current, regs)) { + case -ERESTARTNOHAND: + case -ERESTARTSYS: + case -ERESTARTNOINTR: + regs->ax = regs->orig_ax; + regs->ip -= 2; + break; + + case -ERESTART_RESTARTBLOCK: + regs->ax = NR_restart_syscall; + regs->ip -= 2; + break; + } + } + + /* + * If there's no signal to deliver, we just put the saved sigmask + * back. + */ + if (current_thread_info()->status & TS_RESTORE_SIGMASK) { + current_thread_info()->status &= ~TS_RESTORE_SIGMASK; + sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); + } +} + +/* + * notification of userspace execution resumption + * - triggered by the TIF_WORK_MASK flags + */ +void +do_notify_resume(struct pt_regs *regs, void *unused, __u32 thread_info_flags) +{ +#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) + /* notify userspace of pending MCEs */ + if (thread_info_flags & _TIF_MCE_NOTIFY) + mce_notify_user(); +#endif /* CONFIG_X86_64 && CONFIG_X86_MCE */ + + /* deal with pending signal delivery */ + if (thread_info_flags & _TIF_SIGPENDING) + do_signal(regs); + + if (thread_info_flags & _TIF_NOTIFY_RESUME) { + clear_thread_flag(TIF_NOTIFY_RESUME); + tracehook_notify_resume(regs); + } + +#ifdef CONFIG_X86_32 + clear_thread_flag(TIF_IRET); +#endif /* CONFIG_X86_32 */ +} + +void signal_fault(struct pt_regs *regs, void __user *frame, char *where) +{ + struct task_struct *me = current; + + if (show_unhandled_signals && printk_ratelimit()) { + printk("%s" + "%s[%d] bad frame in %s frame:%p ip:%lx sp:%lx orax:%lx", + task_pid_nr(current) > 1 ? KERN_INFO : KERN_EMERG, + me->comm, me->pid, where, frame, + regs->ip, regs->sp, regs->orig_ax); + print_vma_addr(" in ", regs->ip); + printk(KERN_CONT "\n"); + } + + force_sig(SIGSEGV, me); +} diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c deleted file mode 100644 index d6dd057d0f22..000000000000 --- a/arch/x86/kernel/signal_32.c +++ /dev/null @@ -1,716 +0,0 @@ -/* - * Copyright (C) 1991, 1992 Linus Torvalds - * - * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson - * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes - */ -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "sigframe.h" - -#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) - -#define __FIX_EFLAGS (X86_EFLAGS_AC | X86_EFLAGS_OF | \ - X86_EFLAGS_DF | X86_EFLAGS_TF | X86_EFLAGS_SF | \ - X86_EFLAGS_ZF | X86_EFLAGS_AF | X86_EFLAGS_PF | \ - X86_EFLAGS_CF) - -#ifdef CONFIG_X86_32 -# define FIX_EFLAGS (__FIX_EFLAGS | X86_EFLAGS_RF) -#else -# define FIX_EFLAGS __FIX_EFLAGS -#endif - -/* - * Atomically swap in the new signal mask, and wait for a signal. - */ -asmlinkage int -sys_sigsuspend(int history0, int history1, old_sigset_t mask) -{ - mask &= _BLOCKABLE; - spin_lock_irq(¤t->sighand->siglock); - current->saved_sigmask = current->blocked; - siginitset(¤t->blocked, mask); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - current->state = TASK_INTERRUPTIBLE; - schedule(); - set_restore_sigmask(); - - return -ERESTARTNOHAND; -} - -asmlinkage int -sys_sigaction(int sig, const struct old_sigaction __user *act, - struct old_sigaction __user *oact) -{ - struct k_sigaction new_ka, old_ka; - int ret; - - if (act) { - old_sigset_t mask; - - if (!access_ok(VERIFY_READ, act, sizeof(*act)) || - __get_user(new_ka.sa.sa_handler, &act->sa_handler) || - __get_user(new_ka.sa.sa_restorer, &act->sa_restorer)) - return -EFAULT; - - __get_user(new_ka.sa.sa_flags, &act->sa_flags); - __get_user(mask, &act->sa_mask); - siginitset(&new_ka.sa.sa_mask, mask); - } - - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || - __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || - __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer)) - return -EFAULT; - - __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); - } - - return ret; -} - -asmlinkage int sys_sigaltstack(unsigned long bx) -{ - /* - * This is needed to make gcc realize it doesn't own the - * "struct pt_regs" - */ - struct pt_regs *regs = (struct pt_regs *)&bx; - const stack_t __user *uss = (const stack_t __user *)bx; - stack_t __user *uoss = (stack_t __user *)regs->cx; - - return do_sigaltstack(uss, uoss, regs->sp); -} - -#define COPY(x) { \ - err |= __get_user(regs->x, &sc->x); \ -} - -#define COPY_SEG(seg) { \ - unsigned short tmp; \ - err |= __get_user(tmp, &sc->seg); \ - regs->seg = tmp; \ -} - -#define COPY_SEG_STRICT(seg) { \ - unsigned short tmp; \ - err |= __get_user(tmp, &sc->seg); \ - regs->seg = tmp | 3; \ -} - -#define GET_SEG(seg) { \ - unsigned short tmp; \ - err |= __get_user(tmp, &sc->seg); \ - loadsegment(seg, tmp); \ -} - -/* - * Do a signal return; undo the signal stack. - */ -static int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, - unsigned long *pax) -{ - void __user *buf; - unsigned int tmpflags; - unsigned int err = 0; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - GET_SEG(gs); - COPY_SEG(fs); - COPY_SEG(es); - COPY_SEG(ds); - COPY(di); COPY(si); COPY(bp); COPY(sp); COPY(bx); - COPY(dx); COPY(cx); COPY(ip); - COPY_SEG_STRICT(cs); - COPY_SEG_STRICT(ss); - - err |= __get_user(tmpflags, &sc->flags); - regs->flags = (regs->flags & ~FIX_EFLAGS) | (tmpflags & FIX_EFLAGS); - regs->orig_ax = -1; /* disable syscall checks */ - - err |= __get_user(buf, &sc->fpstate); - err |= restore_i387_xstate(buf); - - err |= __get_user(*pax, &sc->ax); - return err; -} - -asmlinkage unsigned long sys_sigreturn(unsigned long __unused) -{ - struct sigframe __user *frame; - struct pt_regs *regs; - unsigned long ax; - sigset_t set; - - regs = (struct pt_regs *) &__unused; - frame = (struct sigframe __user *)(regs->sp - 8); - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__get_user(set.sig[0], &frame->sc.oldmask) || (_NSIG_WORDS > 1 - && __copy_from_user(&set.sig[1], &frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (restore_sigcontext(regs, &frame->sc, &ax)) - goto badframe; - return ax; - -badframe: - if (show_unhandled_signals && printk_ratelimit()) { - printk("%s%s[%d] bad frame in sigreturn frame:" - "%p ip:%lx sp:%lx oeax:%lx", - task_pid_nr(current) > 1 ? KERN_INFO : KERN_EMERG, - current->comm, task_pid_nr(current), frame, regs->ip, - regs->sp, regs->orig_ax); - print_vma_addr(" in ", regs->ip); - printk(KERN_CONT "\n"); - } - - force_sig(SIGSEGV, current); - - return 0; -} - -static long do_rt_sigreturn(struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - unsigned long ax; - sigset_t set; - - frame = (struct rt_sigframe __user *)(regs->sp - sizeof(long)); - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &ax)) - goto badframe; - - if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT) - goto badframe; - - return ax; - -badframe: - signal_fault(regs, frame, "rt_sigreturn"); - return 0; -} - -asmlinkage int sys_rt_sigreturn(unsigned long __unused) -{ - struct pt_regs *regs = (struct pt_regs *)&__unused; - - return do_rt_sigreturn(regs); -} - -/* - * Set up a signal frame. - */ -static int -setup_sigcontext(struct sigcontext __user *sc, void __user *fpstate, - struct pt_regs *regs, unsigned long mask) -{ - int tmp, err = 0; - - err |= __put_user(regs->fs, (unsigned int __user *)&sc->fs); - savesegment(gs, tmp); - err |= __put_user(tmp, (unsigned int __user *)&sc->gs); - - err |= __put_user(regs->es, (unsigned int __user *)&sc->es); - err |= __put_user(regs->ds, (unsigned int __user *)&sc->ds); - err |= __put_user(regs->di, &sc->di); - err |= __put_user(regs->si, &sc->si); - err |= __put_user(regs->bp, &sc->bp); - err |= __put_user(regs->sp, &sc->sp); - err |= __put_user(regs->bx, &sc->bx); - err |= __put_user(regs->dx, &sc->dx); - err |= __put_user(regs->cx, &sc->cx); - err |= __put_user(regs->ax, &sc->ax); - err |= __put_user(current->thread.trap_no, &sc->trapno); - err |= __put_user(current->thread.error_code, &sc->err); - err |= __put_user(regs->ip, &sc->ip); - err |= __put_user(regs->cs, (unsigned int __user *)&sc->cs); - err |= __put_user(regs->flags, &sc->flags); - err |= __put_user(regs->sp, &sc->sp_at_signal); - err |= __put_user(regs->ss, (unsigned int __user *)&sc->ss); - - tmp = save_i387_xstate(fpstate); - if (tmp < 0) - err = 1; - else - err |= __put_user(tmp ? fpstate : NULL, &sc->fpstate); - - /* non-iBCS2 extensions.. */ - err |= __put_user(mask, &sc->oldmask); - err |= __put_user(current->thread.cr2, &sc->cr2); - - return err; -} - -/* - * Determine which stack to use.. - */ -static inline void __user * -get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size, - void **fpstate) -{ - unsigned long sp; - - /* Default to using normal stack */ - sp = regs->sp; - - /* - * If we are on the alternate signal stack and would overflow it, don't. - * Return an always-bogus address instead so we will die with SIGSEGV. - */ - if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size))) - return (void __user *) -1L; - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (sas_ss_flags(sp) == 0) - sp = current->sas_ss_sp + current->sas_ss_size; - } else { - /* This is the legacy signal stack switching. */ - if ((regs->ss & 0xffff) != __USER_DS && - !(ka->sa.sa_flags & SA_RESTORER) && - ka->sa.sa_restorer) - sp = (unsigned long) ka->sa.sa_restorer; - } - - if (used_math()) { - sp = sp - sig_xstate_size; - *fpstate = (struct _fpstate *) sp; - } - - sp -= frame_size; - /* - * Align the stack pointer according to the i386 ABI, - * i.e. so that on function entry ((sp + 4) & 15) == 0. - */ - sp = ((sp + 4) & -16ul) - 4; - - return (void __user *) sp; -} - -static int -__setup_frame(int sig, struct k_sigaction *ka, sigset_t *set, - struct pt_regs *regs) -{ - struct sigframe __user *frame; - void __user *restorer; - int err = 0; - void __user *fpstate = NULL; - - frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - if (__put_user(sig, &frame->sig)) - return -EFAULT; - - if (setup_sigcontext(&frame->sc, fpstate, regs, set->sig[0])) - return -EFAULT; - - if (_NSIG_WORDS > 1) { - if (__copy_to_user(&frame->extramask, &set->sig[1], - sizeof(frame->extramask))) - return -EFAULT; - } - - if (current->mm->context.vdso) - restorer = VDSO32_SYMBOL(current->mm->context.vdso, sigreturn); - else - restorer = &frame->retcode; - if (ka->sa.sa_flags & SA_RESTORER) - restorer = ka->sa.sa_restorer; - - /* Set up to return from userspace. */ - err |= __put_user(restorer, &frame->pretcode); - - /* - * This is popl %eax ; movl $__NR_sigreturn, %eax ; int $0x80 - * - * WE DO NOT USE IT ANY MORE! It's only left here for historical - * reasons and because gdb uses it as a signature to notice - * signal handler stack frames. - */ - err |= __put_user(0xb858, (short __user *)(frame->retcode+0)); - err |= __put_user(__NR_sigreturn, (int __user *)(frame->retcode+2)); - err |= __put_user(0x80cd, (short __user *)(frame->retcode+6)); - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - regs->sp = (unsigned long)frame; - regs->ip = (unsigned long)ka->sa.sa_handler; - regs->ax = (unsigned long)sig; - regs->dx = 0; - regs->cx = 0; - - regs->ds = __USER_DS; - regs->es = __USER_DS; - regs->ss = __USER_DS; - regs->cs = __USER_CS; - - return 0; -} - -static int __setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - void __user *restorer; - int err = 0; - void __user *fpstate = NULL; - - frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - err |= __put_user(sig, &frame->sig); - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, info); - if (err) - return -EFAULT; - - /* Create the ucontext. */ - if (cpu_has_xsave) - err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags); - else - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); - err |= __put_user(sas_ss_flags(regs->sp), - &frame->uc.uc_stack.ss_flags); - err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); - err |= setup_sigcontext(&frame->uc.uc_mcontext, fpstate, - regs, set->sig[0]); - err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - if (err) - return -EFAULT; - - /* Set up to return from userspace. */ - restorer = VDSO32_SYMBOL(current->mm->context.vdso, rt_sigreturn); - if (ka->sa.sa_flags & SA_RESTORER) - restorer = ka->sa.sa_restorer; - err |= __put_user(restorer, &frame->pretcode); - - /* - * This is movl $__NR_rt_sigreturn, %ax ; int $0x80 - * - * WE DO NOT USE IT ANY MORE! It's only left here for historical - * reasons and because gdb uses it as a signature to notice - * signal handler stack frames. - */ - err |= __put_user(0xb8, (char __user *)(frame->retcode+0)); - err |= __put_user(__NR_rt_sigreturn, (int __user *)(frame->retcode+1)); - err |= __put_user(0x80cd, (short __user *)(frame->retcode+5)); - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - regs->sp = (unsigned long)frame; - regs->ip = (unsigned long)ka->sa.sa_handler; - regs->ax = (unsigned long)sig; - regs->dx = (unsigned long)&frame->info; - regs->cx = (unsigned long)&frame->uc; - - regs->ds = __USER_DS; - regs->es = __USER_DS; - regs->ss = __USER_DS; - regs->cs = __USER_CS; - - return 0; -} - -/* - * OK, we're invoking a handler: - */ -static int signr_convert(int sig) -{ - struct thread_info *info = current_thread_info(); - - if (info->exec_domain && info->exec_domain->signal_invmap && sig < 32) - return info->exec_domain->signal_invmap[sig]; - return sig; -} - -#define is_ia32 1 -#define ia32_setup_frame __setup_frame -#define ia32_setup_rt_frame __setup_rt_frame - -static int -setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - int usig = signr_convert(sig); - int ret; - - /* Set up the stack frame */ - if (is_ia32) { - if (ka->sa.sa_flags & SA_SIGINFO) - ret = ia32_setup_rt_frame(usig, ka, info, set, regs); - else - ret = ia32_setup_frame(usig, ka, set, regs); - } else - ret = __setup_rt_frame(sig, ka, info, set, regs); - - if (ret) { - force_sigsegv(sig, current); - return -EFAULT; - } - - return ret; -} - -static int -handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, - sigset_t *oldset, struct pt_regs *regs) -{ - int ret; - - /* Are we from a system call? */ - if (syscall_get_nr(current, regs) >= 0) { - /* If so, check system call restarting.. */ - switch (syscall_get_error(current, regs)) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->ax = -EINTR; - break; - - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->ax = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - regs->ax = regs->orig_ax; - regs->ip -= 2; - break; - } - } - - /* - * If TF is set due to a debugger (TIF_FORCED_TF), clear the TF - * flag so that register information in the sigcontext is correct. - */ - if (unlikely(regs->flags & X86_EFLAGS_TF) && - likely(test_and_clear_thread_flag(TIF_FORCED_TF))) - regs->flags &= ~X86_EFLAGS_TF; - - ret = setup_rt_frame(sig, ka, info, oldset, regs); - - if (ret) - return ret; - -#ifdef CONFIG_X86_64 - /* - * This has nothing to do with segment registers, - * despite the name. This magic affects uaccess.h - * macros' behavior. Reset it to the normal setting. - */ - set_fs(USER_DS); -#endif - - /* - * Clear the direction flag as per the ABI for function entry. - */ - regs->flags &= ~X86_EFLAGS_DF; - - /* - * Clear TF when entering the signal handler, but - * notify any tracer that was single-stepping it. - * The tracer may want to single-step inside the - * handler too. - */ - regs->flags &= ~X86_EFLAGS_TF; - - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - tracehook_signal_handler(sig, info, ka, regs, - test_thread_flag(TIF_SINGLESTEP)); - - return 0; -} - -#define NR_restart_syscall __NR_restart_syscall -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - */ -static void do_signal(struct pt_regs *regs) -{ - struct k_sigaction ka; - siginfo_t info; - int signr; - sigset_t *oldset; - - /* - * We want the common case to go fast, which is why we may in certain - * cases get here from kernel mode. Just return without doing anything - * if so. - * X86_32: vm86 regs switched out by assembly code before reaching - * here, so testing against kernel CS suffices. - */ - if (!user_mode(regs)) - return; - - if (current_thread_info()->status & TS_RESTORE_SIGMASK) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* - * Re-enable any watchpoints before delivering the - * signal to user space. The processor register will - * have been cleared if the watchpoint triggered - * inside the kernel. - */ - if (current->thread.debugreg7) - set_debugreg(current->thread.debugreg7, 7); - - /* Whee! Actually deliver the signal. */ - if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { - /* - * A signal was successfully delivered; the saved - * sigmask will have been stored in the signal frame, - * and will be restored by sigreturn, so we can simply - * clear the TS_RESTORE_SIGMASK flag. - */ - current_thread_info()->status &= ~TS_RESTORE_SIGMASK; - } - return; - } - - /* Did we come from a system call? */ - if (syscall_get_nr(current, regs) >= 0) { - /* Restart the system call - no handlers present */ - switch (syscall_get_error(current, regs)) { - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->ax = regs->orig_ax; - regs->ip -= 2; - break; - - case -ERESTART_RESTARTBLOCK: - regs->ax = NR_restart_syscall; - regs->ip -= 2; - break; - } - } - - /* - * If there's no signal to deliver, we just put the saved sigmask - * back. - */ - if (current_thread_info()->status & TS_RESTORE_SIGMASK) { - current_thread_info()->status &= ~TS_RESTORE_SIGMASK; - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} - -/* - * notification of userspace execution resumption - * - triggered by the TIF_WORK_MASK flags - */ -void -do_notify_resume(struct pt_regs *regs, void *unused, __u32 thread_info_flags) -{ -#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) - /* notify userspace of pending MCEs */ - if (thread_info_flags & _TIF_MCE_NOTIFY) - mce_notify_user(); -#endif /* CONFIG_X86_64 && CONFIG_X86_MCE */ - - /* deal with pending signal delivery */ - if (thread_info_flags & _TIF_SIGPENDING) - do_signal(regs); - - if (thread_info_flags & _TIF_NOTIFY_RESUME) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - } - -#ifdef CONFIG_X86_32 - clear_thread_flag(TIF_IRET); -#endif /* CONFIG_X86_32 */ -} - -void signal_fault(struct pt_regs *regs, void __user *frame, char *where) -{ - struct task_struct *me = current; - - if (show_unhandled_signals && printk_ratelimit()) { - printk(KERN_INFO - "%s[%d] bad frame in %s frame:%p ip:%lx sp:%lx orax:%lx", - me->comm, me->pid, where, frame, - regs->ip, regs->sp, regs->orig_ax); - print_vma_addr(" in ", regs->ip); - printk(KERN_CONT "\n"); - } - - force_sig(SIGSEGV, me); -} diff --git a/arch/x86/kernel/signal_64.c b/arch/x86/kernel/signal_64.c deleted file mode 100644 index a5c9627f4db9..000000000000 --- a/arch/x86/kernel/signal_64.c +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs - * - * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson - * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes - * 2000-2002 x86-64 support by Andi Kleen - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include "sigframe.h" - -#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) - -#define __FIX_EFLAGS (X86_EFLAGS_AC | X86_EFLAGS_OF | \ - X86_EFLAGS_DF | X86_EFLAGS_TF | X86_EFLAGS_SF | \ - X86_EFLAGS_ZF | X86_EFLAGS_AF | X86_EFLAGS_PF | \ - X86_EFLAGS_CF) - -#ifdef CONFIG_X86_32 -# define FIX_EFLAGS (__FIX_EFLAGS | X86_EFLAGS_RF) -#else -# define FIX_EFLAGS __FIX_EFLAGS -#endif - -asmlinkage long -sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, - struct pt_regs *regs) -{ - return do_sigaltstack(uss, uoss, regs->sp); -} - -#define COPY(x) { \ - err |= __get_user(regs->x, &sc->x); \ -} - -#define COPY_SEG_STRICT(seg) { \ - unsigned short tmp; \ - err |= __get_user(tmp, &sc->seg); \ - regs->seg = tmp | 3; \ -} - -/* - * Do a signal return; undo the signal stack. - */ -static int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, - unsigned long *pax) -{ - void __user *buf; - unsigned int tmpflags; - unsigned int err = 0; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - COPY(di); COPY(si); COPY(bp); COPY(sp); COPY(bx); - COPY(dx); COPY(cx); COPY(ip); - COPY(r8); - COPY(r9); - COPY(r10); - COPY(r11); - COPY(r12); - COPY(r13); - COPY(r14); - COPY(r15); - - /* Kernel saves and restores only the CS segment register on signals, - * which is the bare minimum needed to allow mixed 32/64-bit code. - * App's signal handler can save/restore other segments if needed. */ - COPY_SEG_STRICT(cs); - - err |= __get_user(tmpflags, &sc->flags); - regs->flags = (regs->flags & ~FIX_EFLAGS) | (tmpflags & FIX_EFLAGS); - regs->orig_ax = -1; /* disable syscall checks */ - - err |= __get_user(buf, &sc->fpstate); - err |= restore_i387_xstate(buf); - - err |= __get_user(*pax, &sc->ax); - return err; -} - -static long do_rt_sigreturn(struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - unsigned long ax; - sigset_t set; - - frame = (struct rt_sigframe __user *)(regs->sp - sizeof(long)); - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &ax)) - goto badframe; - - if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT) - goto badframe; - - return ax; - -badframe: - signal_fault(regs, frame, "rt_sigreturn"); - return 0; -} - -asmlinkage long sys_rt_sigreturn(struct pt_regs *regs) -{ - return do_rt_sigreturn(regs); -} - -/* - * Set up a signal frame. - */ - -static inline int -setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, - unsigned long mask, struct task_struct *me) -{ - int err = 0; - - err |= __put_user(regs->cs, &sc->cs); - err |= __put_user(0, &sc->gs); - err |= __put_user(0, &sc->fs); - - err |= __put_user(regs->di, &sc->di); - err |= __put_user(regs->si, &sc->si); - err |= __put_user(regs->bp, &sc->bp); - err |= __put_user(regs->sp, &sc->sp); - err |= __put_user(regs->bx, &sc->bx); - err |= __put_user(regs->dx, &sc->dx); - err |= __put_user(regs->cx, &sc->cx); - err |= __put_user(regs->ax, &sc->ax); - err |= __put_user(regs->r8, &sc->r8); - err |= __put_user(regs->r9, &sc->r9); - err |= __put_user(regs->r10, &sc->r10); - err |= __put_user(regs->r11, &sc->r11); - err |= __put_user(regs->r12, &sc->r12); - err |= __put_user(regs->r13, &sc->r13); - err |= __put_user(regs->r14, &sc->r14); - err |= __put_user(regs->r15, &sc->r15); - err |= __put_user(me->thread.trap_no, &sc->trapno); - err |= __put_user(me->thread.error_code, &sc->err); - err |= __put_user(regs->ip, &sc->ip); - err |= __put_user(regs->flags, &sc->flags); - err |= __put_user(mask, &sc->oldmask); - err |= __put_user(me->thread.cr2, &sc->cr2); - - return err; -} - -/* - * Determine which stack to use.. - */ - -static void __user * -get_stack(struct k_sigaction *ka, struct pt_regs *regs, unsigned long size) -{ - unsigned long sp; - - /* Default to using normal stack - redzone*/ - sp = regs->sp - 128; - - /* This is the X/Open sanctioned signal stack switching. */ - if (ka->sa.sa_flags & SA_ONSTACK) { - if (sas_ss_flags(sp) == 0) - sp = current->sas_ss_sp + current->sas_ss_size; - } - - return (void __user *)round_down(sp - size, 64); -} - -static int __setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - void __user *fp = NULL; - int err = 0; - struct task_struct *me = current; - - if (used_math()) { - fp = get_stack(ka, regs, sig_xstate_size); - frame = (void __user *)round_down( - (unsigned long)fp - sizeof(struct rt_sigframe), 16) - 8; - - if (save_i387_xstate(fp) < 0) - return -EFAULT; - } else - frame = get_stack(ka, regs, sizeof(struct rt_sigframe)) - 8; - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - if (ka->sa.sa_flags & SA_SIGINFO) { - if (copy_siginfo_to_user(&frame->info, info)) - return -EFAULT; - } - - /* Create the ucontext. */ - if (cpu_has_xsave) - err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags); - else - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __put_user(me->sas_ss_sp, &frame->uc.uc_stack.ss_sp); - err |= __put_user(sas_ss_flags(regs->sp), - &frame->uc.uc_stack.ss_flags); - err |= __put_user(me->sas_ss_size, &frame->uc.uc_stack.ss_size); - err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0], me); - err |= __put_user(fp, &frame->uc.uc_mcontext.fpstate); - if (sizeof(*set) == 16) { - __put_user(set->sig[0], &frame->uc.uc_sigmask.sig[0]); - __put_user(set->sig[1], &frame->uc.uc_sigmask.sig[1]); - } else - err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - - /* Set up to return from userspace. If provided, use a stub - already in userspace. */ - /* x86-64 should always use SA_RESTORER. */ - if (ka->sa.sa_flags & SA_RESTORER) { - err |= __put_user(ka->sa.sa_restorer, &frame->pretcode); - } else { - /* could use a vstub here */ - return -EFAULT; - } - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - regs->di = sig; - /* In case the signal handler was declared without prototypes */ - regs->ax = 0; - - /* This also works for non SA_SIGINFO handlers because they expect the - next argument after the signal number on the stack. */ - regs->si = (unsigned long)&frame->info; - regs->dx = (unsigned long)&frame->uc; - regs->ip = (unsigned long) ka->sa.sa_handler; - - regs->sp = (unsigned long)frame; - - /* Set up the CS register to run signal handlers in 64-bit mode, - even if the handler happens to be interrupting 32-bit code. */ - regs->cs = __USER_CS; - - return 0; -} - -/* - * OK, we're invoking a handler - */ -static int signr_convert(int sig) -{ - return sig; -} - -#ifdef CONFIG_IA32_EMULATION -#define is_ia32 test_thread_flag(TIF_IA32) -#else -#define is_ia32 0 -#endif - -static int -setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) -{ - int usig = signr_convert(sig); - int ret; - - /* Set up the stack frame */ - if (is_ia32) { - if (ka->sa.sa_flags & SA_SIGINFO) - ret = ia32_setup_rt_frame(usig, ka, info, set, regs); - else - ret = ia32_setup_frame(usig, ka, set, regs); - } else - ret = __setup_rt_frame(sig, ka, info, set, regs); - - if (ret) { - force_sigsegv(sig, current); - return -EFAULT; - } - - return ret; -} - -static int -handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, - sigset_t *oldset, struct pt_regs *regs) -{ - int ret; - - /* Are we from a system call? */ - if (syscall_get_nr(current, regs) >= 0) { - /* If so, check system call restarting.. */ - switch (syscall_get_error(current, regs)) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->ax = -EINTR; - break; - - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->ax = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - regs->ax = regs->orig_ax; - regs->ip -= 2; - break; - } - } - - /* - * If TF is set due to a debugger (TIF_FORCED_TF), clear the TF - * flag so that register information in the sigcontext is correct. - */ - if (unlikely(regs->flags & X86_EFLAGS_TF) && - likely(test_and_clear_thread_flag(TIF_FORCED_TF))) - regs->flags &= ~X86_EFLAGS_TF; - - ret = setup_rt_frame(sig, ka, info, oldset, regs); - - if (ret) - return ret; - -#ifdef CONFIG_X86_64 - /* - * This has nothing to do with segment registers, - * despite the name. This magic affects uaccess.h - * macros' behavior. Reset it to the normal setting. - */ - set_fs(USER_DS); -#endif - - /* - * Clear the direction flag as per the ABI for function entry. - */ - regs->flags &= ~X86_EFLAGS_DF; - - /* - * Clear TF when entering the signal handler, but - * notify any tracer that was single-stepping it. - * The tracer may want to single-step inside the - * handler too. - */ - regs->flags &= ~X86_EFLAGS_TF; - - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - tracehook_signal_handler(sig, info, ka, regs, - test_thread_flag(TIF_SINGLESTEP)); - - return 0; -} - -#define NR_restart_syscall \ - test_thread_flag(TIF_IA32) ? __NR_ia32_restart_syscall : __NR_restart_syscall -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - */ -static void do_signal(struct pt_regs *regs) -{ - struct k_sigaction ka; - siginfo_t info; - int signr; - sigset_t *oldset; - - /* - * We want the common case to go fast, which is why we may in certain - * cases get here from kernel mode. Just return without doing anything - * if so. - * X86_32: vm86 regs switched out by assembly code before reaching - * here, so testing against kernel CS suffices. - */ - if (!user_mode(regs)) - return; - - if (current_thread_info()->status & TS_RESTORE_SIGMASK) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* - * Re-enable any watchpoints before delivering the - * signal to user space. The processor register will - * have been cleared if the watchpoint triggered - * inside the kernel. - */ - if (current->thread.debugreg7) - set_debugreg(current->thread.debugreg7, 7); - - /* Whee! Actually deliver the signal. */ - if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { - /* - * A signal was successfully delivered; the saved - * sigmask will have been stored in the signal frame, - * and will be restored by sigreturn, so we can simply - * clear the TS_RESTORE_SIGMASK flag. - */ - current_thread_info()->status &= ~TS_RESTORE_SIGMASK; - } - return; - } - - /* Did we come from a system call? */ - if (syscall_get_nr(current, regs) >= 0) { - /* Restart the system call - no handlers present */ - switch (syscall_get_error(current, regs)) { - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->ax = regs->orig_ax; - regs->ip -= 2; - break; - - case -ERESTART_RESTARTBLOCK: - regs->ax = NR_restart_syscall; - regs->ip -= 2; - break; - } - } - - /* - * If there's no signal to deliver, we just put the saved sigmask - * back. - */ - if (current_thread_info()->status & TS_RESTORE_SIGMASK) { - current_thread_info()->status &= ~TS_RESTORE_SIGMASK; - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} - -/* - * notification of userspace execution resumption - * - triggered by the TIF_WORK_MASK flags - */ -void -do_notify_resume(struct pt_regs *regs, void *unused, __u32 thread_info_flags) -{ -#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) - /* notify userspace of pending MCEs */ - if (thread_info_flags & _TIF_MCE_NOTIFY) - mce_notify_user(); -#endif /* CONFIG_X86_64 && CONFIG_X86_MCE */ - - /* deal with pending signal delivery */ - if (thread_info_flags & _TIF_SIGPENDING) - do_signal(regs); - - if (thread_info_flags & _TIF_NOTIFY_RESUME) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - } - -#ifdef CONFIG_X86_32 - clear_thread_flag(TIF_IRET); -#endif /* CONFIG_X86_32 */ -} - -void signal_fault(struct pt_regs *regs, void __user *frame, char *where) -{ - struct task_struct *me = current; - - if (show_unhandled_signals && printk_ratelimit()) { - printk(KERN_INFO - "%s[%d] bad frame in %s frame:%p ip:%lx sp:%lx orax:%lx", - me->comm, me->pid, where, frame, - regs->ip, regs->sp, regs->orig_ax); - print_vma_addr(" in ", regs->ip); - printk(KERN_CONT "\n"); - } - - force_sig(SIGSEGV, me); -} diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c index 18f9b19f5f8f..3f92b134ab90 100644 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -140,19 +140,6 @@ void native_send_call_func_ipi(cpumask_t mask) send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } -static void stop_this_cpu(void *dummy) -{ - local_irq_disable(); - /* - * Remove this CPU: - */ - cpu_clear(smp_processor_id(), cpu_online_map); - disable_local_APIC(); - if (hlt_works(smp_processor_id())) - for (;;) halt(); - for (;;); -} - /* * this function calls the 'stop' function on all other CPUs in the system. */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 7b1093397319..7a430c4d1551 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -62,6 +62,7 @@ #include #include #include +#include #include #include @@ -294,9 +295,7 @@ static void __cpuinit start_secondary(void *unused) * fragile that we want to limit the things done here to the * most necessary things. */ -#ifdef CONFIG_VMI vmi_bringup(); -#endif cpu_init(); preempt_disable(); smp_callin(); @@ -536,7 +535,7 @@ static void impress_friends(void) pr_debug("Before bogocount - setting activated=1.\n"); } -static inline void __inquire_remote_apic(int apicid) +void __inquire_remote_apic(int apicid) { unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; char *names[] = { "ID", "VERSION", "SPIV" }; @@ -575,14 +574,13 @@ static inline void __inquire_remote_apic(int apicid) } } -#ifdef WAKE_SECONDARY_VIA_NMI /* * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this * won't ... remember to clear down the APIC, etc later. */ -static int __devinit -wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) +int __devinit +wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) { unsigned long send_status, accept_status = 0; int maxlvt; @@ -599,7 +597,7 @@ wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) * Give the other CPU some time to accept the IPI. */ udelay(200); - if (APIC_INTEGRATED(apic_version[phys_apicid])) { + if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { maxlvt = lapic_get_maxlvt(); if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ apic_write(APIC_ESR, 0); @@ -614,11 +612,9 @@ wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) return (send_status | accept_status); } -#endif /* WAKE_SECONDARY_VIA_NMI */ -#ifdef WAKE_SECONDARY_VIA_INIT -static int __devinit -wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) +int __devinit +wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) { unsigned long send_status, accept_status = 0; int maxlvt, num_starts, j; @@ -737,7 +733,6 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) return (send_status | accept_status); } -#endif /* WAKE_SECONDARY_VIA_INIT */ struct create_idle { struct work_struct work; @@ -1086,8 +1081,10 @@ static int __init smp_sanity_check(unsigned max_cpus) #endif if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { - printk(KERN_WARNING "weird, boot CPU (#%d) not listed" - "by the BIOS.\n", hard_smp_processor_id()); + printk(KERN_WARNING + "weird, boot CPU (#%d) not listed by the BIOS.\n", + hard_smp_processor_id()); + physid_set(hard_smp_processor_id(), phys_cpu_present_map); } diff --git a/arch/x86/kernel/time_64.c b/arch/x86/kernel/time_64.c index cb19d650c216..1b7711b31037 100644 --- a/arch/x86/kernel/time_64.c +++ b/arch/x86/kernel/time_64.c @@ -49,7 +49,7 @@ unsigned long profile_pc(struct pt_regs *regs) } EXPORT_SYMBOL(profile_pc); -irqreturn_t timer_interrupt(int irq, void *dev_id) +static irqreturn_t timer_interrupt(int irq, void *dev_id) { add_pda(irq0_irqs, 1); @@ -80,6 +80,8 @@ unsigned long __init calibrate_cpu(void) break; no_ctr_free = (i == 4); if (no_ctr_free) { + WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... " + "cpu_khz value may be incorrect.\n"); i = 3; rdmsrl(MSR_K7_EVNTSEL3, evntsel3); wrmsrl(MSR_K7_EVNTSEL3, 0); diff --git a/arch/x86/kernel/tlb_32.c b/arch/x86/kernel/tlb_32.c index e00534b33534..4290d918b58a 100644 --- a/arch/x86/kernel/tlb_32.c +++ b/arch/x86/kernel/tlb_32.c @@ -34,9 +34,8 @@ static DEFINE_SPINLOCK(tlbstate_lock); */ void leave_mm(int cpu) { - if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) - BUG(); - cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask); + BUG_ON(x86_read_percpu(cpu_tlbstate.state) == TLBSTATE_OK); + cpu_clear(cpu, x86_read_percpu(cpu_tlbstate.active_mm)->cpu_vm_mask); load_cr3(swapper_pg_dir); } EXPORT_SYMBOL_GPL(leave_mm); @@ -104,8 +103,8 @@ void smp_invalidate_interrupt(struct pt_regs *regs) * BUG(); */ - if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) { - if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) { + if (flush_mm == x86_read_percpu(cpu_tlbstate.active_mm)) { + if (x86_read_percpu(cpu_tlbstate.state) == TLBSTATE_OK) { if (flush_va == TLB_FLUSH_ALL) local_flush_tlb(); else @@ -154,6 +153,12 @@ void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm, flush_mm = mm; flush_va = va; cpus_or(flush_cpumask, cpumask, flush_cpumask); + + /* + * Make the above memory operations globally visible before + * sending the IPI. + */ + smp_mb(); /* * We have to send the IPI only to * CPUs affected. @@ -232,7 +237,7 @@ static void do_flush_tlb_all(void *info) unsigned long cpu = smp_processor_id(); __flush_tlb_all(); - if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY) + if (x86_read_percpu(cpu_tlbstate.state) == TLBSTATE_LAZY) leave_mm(cpu); } diff --git a/arch/x86/kernel/tlb_64.c b/arch/x86/kernel/tlb_64.c index dcbf7a1159ea..8f919ca69494 100644 --- a/arch/x86/kernel/tlb_64.c +++ b/arch/x86/kernel/tlb_64.c @@ -182,6 +182,11 @@ void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm, f->flush_va = va; cpus_or(f->flush_cpumask, cpumask, f->flush_cpumask); + /* + * Make the above memory operations globally visible before + * sending the IPI. + */ + smp_mb(); /* * We have to send the IPI only to * CPUs affected. diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c index 04431f34fd16..6a00e5faaa74 100644 --- a/arch/x86/kernel/tlb_uv.c +++ b/arch/x86/kernel/tlb_uv.c @@ -566,14 +566,10 @@ static int __init uv_ptc_init(void) if (!is_uv_system()) return 0; - if (!proc_mkdir("sgi_uv", NULL)) - return -EINVAL; - proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL); if (!proc_uv_ptc) { printk(KERN_ERR "unable to create %s proc entry\n", UV_PTC_BASENAME); - remove_proc_entry("sgi_uv", NULL); return -EINVAL; } proc_uv_ptc->proc_fops = &proc_uv_ptc_operations; diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c index 1106fac6024d..808031a5ba19 100644 --- a/arch/x86/kernel/trampoline.c +++ b/arch/x86/kernel/trampoline.c @@ -1,10 +1,26 @@ #include #include +#include /* ready for x86_64 and x86 */ unsigned char *trampoline_base = __va(TRAMPOLINE_BASE); +void __init reserve_trampoline_memory(void) +{ +#ifdef CONFIG_X86_32 + /* + * But first pinch a few for the stack/trampoline stuff + * FIXME: Don't need the extra page at 4K, but need to fix + * trampoline before removing it. (see the GDT stuff) + */ + reserve_early(PAGE_SIZE, PAGE_SIZE + PAGE_SIZE, "EX TRAMPOLINE"); +#endif + /* Has to be in very low memory so we can execute real-mode AP code. */ + reserve_early(TRAMPOLINE_BASE, TRAMPOLINE_BASE + TRAMPOLINE_SIZE, + "TRAMPOLINE"); +} + /* * Currently trivial. Write the real->protected mode * bootstrap into the page concerned. The caller @@ -12,7 +28,6 @@ unsigned char *trampoline_base = __va(TRAMPOLINE_BASE); */ unsigned long setup_trampoline(void) { - memcpy(trampoline_base, trampoline_data, - trampoline_end - trampoline_data); + memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE); return virt_to_phys(trampoline_base); } diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 04d242ab0161..c320c29255c2 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -664,7 +664,7 @@ void math_error(void __user *ip) { struct task_struct *task; siginfo_t info; - unsigned short cwd, swd; + unsigned short cwd, swd, err; /* * Save the info for the exception handler and clear the error. @@ -675,7 +675,6 @@ void math_error(void __user *ip) task->thread.error_code = 0; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_code = __SI_FAULT; info.si_addr = ip; /* * (~cwd & swd) will mask out exceptions that are not set to unmasked @@ -689,34 +688,31 @@ void math_error(void __user *ip) */ cwd = get_fpu_cwd(task); swd = get_fpu_swd(task); - switch (swd & ~cwd & 0x3f) { - case 0x000: /* No unmasked exception */ -#ifdef CONFIG_X86_32 + + err = swd & ~cwd & 0x3f; + +#if CONFIG_X86_32 + if (!err) return; #endif - default: /* Multiple exceptions */ - break; - case 0x001: /* Invalid Op */ + + if (err & 0x001) { /* Invalid op */ /* * swd & 0x240 == 0x040: Stack Underflow * swd & 0x240 == 0x240: Stack Overflow * User must clear the SF bit (0x40) if set */ info.si_code = FPE_FLTINV; - break; - case 0x002: /* Denormalize */ - case 0x010: /* Underflow */ - info.si_code = FPE_FLTUND; - break; - case 0x004: /* Zero Divide */ + } else if (err & 0x004) { /* Divide by Zero */ info.si_code = FPE_FLTDIV; - break; - case 0x008: /* Overflow */ + } else if (err & 0x008) { /* Overflow */ info.si_code = FPE_FLTOVF; - break; - case 0x020: /* Precision */ + } else if (err & 0x012) { /* Denormal, Underflow */ + info.si_code = FPE_FLTUND; + } else if (err & 0x020) { /* Precision */ info.si_code = FPE_FLTRES; - break; + } else { + info.si_code = __SI_FAULT|SI_KERNEL; /* WTF? */ } force_sig_info(SIGFPE, &info, task); } diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 161bb850fc47..599e58168631 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -15,6 +15,7 @@ #include #include #include +#include unsigned int cpu_khz; /* TSC clocks / usec, not used here */ EXPORT_SYMBOL(cpu_khz); @@ -31,6 +32,7 @@ static int tsc_unstable; erroneous rdtsc usage on !cpu_has_tsc processors */ static int tsc_disabled = -1; +static int tsc_clocksource_reliable; /* * Scheduler clock - returns current time in nanosec units. */ @@ -55,7 +57,7 @@ u64 native_sched_clock(void) rdtscll(this_offset); /* return the value in ns */ - return cycles_2_ns(this_offset); + return __cycles_2_ns(this_offset); } /* We need to define a real function for sched_clock, to override the @@ -98,6 +100,15 @@ int __init notsc_setup(char *str) __setup("notsc", notsc_setup); +static int __init tsc_setup(char *str) +{ + if (!strcmp(str, "reliable")) + tsc_clocksource_reliable = 1; + return 1; +} + +__setup("tsc=", tsc_setup); + #define MAX_RETRIES 5 #define SMI_TRESHOLD 50000 @@ -352,9 +363,15 @@ unsigned long native_calibrate_tsc(void) { u64 tsc1, tsc2, delta, ref1, ref2; unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; - unsigned long flags, latch, ms, fast_calibrate; + unsigned long flags, latch, ms, fast_calibrate, tsc_khz; int hpet = is_hpet_enabled(), i, loopmin; + tsc_khz = get_hypervisor_tsc_freq(); + if (tsc_khz) { + printk(KERN_INFO "TSC: Frequency read from the hypervisor\n"); + return tsc_khz; + } + local_irq_save(flags); fast_calibrate = quick_pit_calibrate(); local_irq_restore(flags); @@ -731,24 +748,21 @@ static struct dmi_system_id __initdata bad_tsc_dmi_table[] = { {} }; -/* - * Geode_LX - the OLPC CPU has a possibly a very reliable TSC - */ +static void __init check_system_tsc_reliable(void) +{ #ifdef CONFIG_MGEODE_LX -/* RTSC counts during suspend */ + /* RTSC counts during suspend */ #define RTSC_SUSP 0x100 - -static void __init check_geode_tsc_reliable(void) -{ unsigned long res_low, res_high; rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); + /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */ if (res_low & RTSC_SUSP) - clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; -} -#else -static inline void check_geode_tsc_reliable(void) { } + tsc_clocksource_reliable = 1; #endif + if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) + tsc_clocksource_reliable = 1; +} /* * Make an educated guess if the TSC is trustworthy and synchronized @@ -759,7 +773,7 @@ __cpuinit int unsynchronized_tsc(void) if (!cpu_has_tsc || tsc_unstable) return 1; -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_SMP if (apic_is_clustered_box()) return 1; #endif @@ -783,6 +797,8 @@ static void __init init_tsc_clocksource(void) { clocksource_tsc.mult = clocksource_khz2mult(tsc_khz, clocksource_tsc.shift); + if (tsc_clocksource_reliable) + clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; /* lower the rating if we already know its unstable: */ if (check_tsc_unstable()) { clocksource_tsc.rating = 0; @@ -813,10 +829,6 @@ void __init tsc_init(void) cpu_khz = calibrate_cpu(); #endif - lpj = ((u64)tsc_khz * 1000); - do_div(lpj, HZ); - lpj_fine = lpj; - printk("Detected %lu.%03lu MHz processor.\n", (unsigned long)cpu_khz / 1000, (unsigned long)cpu_khz % 1000); @@ -836,6 +848,10 @@ void __init tsc_init(void) /* now allow native_sched_clock() to use rdtsc */ tsc_disabled = 0; + lpj = ((u64)tsc_khz * 1000); + do_div(lpj, HZ); + lpj_fine = lpj; + use_tsc_delay(); /* Check and install the TSC clocksource */ dmi_check_system(bad_tsc_dmi_table); @@ -843,7 +859,7 @@ void __init tsc_init(void) if (unsynchronized_tsc()) mark_tsc_unstable("TSCs unsynchronized"); - check_geode_tsc_reliable(); + check_system_tsc_reliable(); init_tsc_clocksource(); } diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c index 9ffb01c31c40..bf36328f6ef9 100644 --- a/arch/x86/kernel/tsc_sync.c +++ b/arch/x86/kernel/tsc_sync.c @@ -46,7 +46,9 @@ static __cpuinit void check_tsc_warp(void) cycles_t start, now, prev, end; int i; + rdtsc_barrier(); start = get_cycles(); + rdtsc_barrier(); /* * The measurement runs for 20 msecs: */ @@ -61,7 +63,9 @@ static __cpuinit void check_tsc_warp(void) */ __raw_spin_lock(&sync_lock); prev = last_tsc; + rdtsc_barrier(); now = get_cycles(); + rdtsc_barrier(); last_tsc = now; __raw_spin_unlock(&sync_lock); @@ -108,6 +112,12 @@ void __cpuinit check_tsc_sync_source(int cpu) if (unsynchronized_tsc()) return; + if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { + printk(KERN_INFO + "Skipping synchronization checks as TSC is reliable.\n"); + return; + } + printk(KERN_INFO "checking TSC synchronization [CPU#%d -> CPU#%d]:", smp_processor_id(), cpu); @@ -161,7 +171,7 @@ void __cpuinit check_tsc_sync_target(void) { int cpus = 2; - if (unsynchronized_tsc()) + if (unsynchronized_tsc() || boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) return; /* diff --git a/arch/x86/kernel/vmi_32.c b/arch/x86/kernel/vmi_32.c index 8b6c393ab9fd..23206ba16874 100644 --- a/arch/x86/kernel/vmi_32.c +++ b/arch/x86/kernel/vmi_32.c @@ -266,109 +266,6 @@ static void vmi_nop(void) { } -#ifdef CONFIG_DEBUG_PAGE_TYPE - -#ifdef CONFIG_X86_PAE -#define MAX_BOOT_PTS (2048+4+1) -#else -#define MAX_BOOT_PTS (1024+1) -#endif - -/* - * During boot, mem_map is not yet available in paging_init, so stash - * all the boot page allocations here. - */ -static struct { - u32 pfn; - int type; -} boot_page_allocations[MAX_BOOT_PTS]; -static int num_boot_page_allocations; -static int boot_allocations_applied; - -void vmi_apply_boot_page_allocations(void) -{ - int i; - BUG_ON(!mem_map); - for (i = 0; i < num_boot_page_allocations; i++) { - struct page *page = pfn_to_page(boot_page_allocations[i].pfn); - page->type = boot_page_allocations[i].type; - page->type = boot_page_allocations[i].type & - ~(VMI_PAGE_ZEROED | VMI_PAGE_CLONE); - } - boot_allocations_applied = 1; -} - -static void record_page_type(u32 pfn, int type) -{ - BUG_ON(num_boot_page_allocations >= MAX_BOOT_PTS); - boot_page_allocations[num_boot_page_allocations].pfn = pfn; - boot_page_allocations[num_boot_page_allocations].type = type; - num_boot_page_allocations++; -} - -static void check_zeroed_page(u32 pfn, int type, struct page *page) -{ - u32 *ptr; - int i; - int limit = PAGE_SIZE / sizeof(int); - - if (page_address(page)) - ptr = (u32 *)page_address(page); - else - ptr = (u32 *)__va(pfn << PAGE_SHIFT); - /* - * When cloning the root in non-PAE mode, only the userspace - * pdes need to be zeroed. - */ - if (type & VMI_PAGE_CLONE) - limit = KERNEL_PGD_BOUNDARY; - for (i = 0; i < limit; i++) - BUG_ON(ptr[i]); -} - -/* - * We stash the page type into struct page so we can verify the page - * types are used properly. - */ -static void vmi_set_page_type(u32 pfn, int type) -{ - /* PAE can have multiple roots per page - don't track */ - if (PTRS_PER_PMD > 1 && (type & VMI_PAGE_PDP)) - return; - - if (boot_allocations_applied) { - struct page *page = pfn_to_page(pfn); - if (type != VMI_PAGE_NORMAL) - BUG_ON(page->type); - else - BUG_ON(page->type == VMI_PAGE_NORMAL); - page->type = type & ~(VMI_PAGE_ZEROED | VMI_PAGE_CLONE); - if (type & VMI_PAGE_ZEROED) - check_zeroed_page(pfn, type, page); - } else { - record_page_type(pfn, type); - } -} - -static void vmi_check_page_type(u32 pfn, int type) -{ - /* PAE can have multiple roots per page - skip checks */ - if (PTRS_PER_PMD > 1 && (type & VMI_PAGE_PDP)) - return; - - type &= ~(VMI_PAGE_ZEROED | VMI_PAGE_CLONE); - if (boot_allocations_applied) { - struct page *page = pfn_to_page(pfn); - BUG_ON((page->type ^ type) & VMI_PAGE_PAE); - BUG_ON(type == VMI_PAGE_NORMAL && page->type); - BUG_ON((type & page->type) == 0); - } -} -#else -#define vmi_set_page_type(p,t) do { } while (0) -#define vmi_check_page_type(p,t) do { } while (0) -#endif - #ifdef CONFIG_HIGHPTE static void *vmi_kmap_atomic_pte(struct page *page, enum km_type type) { @@ -395,7 +292,6 @@ static void *vmi_kmap_atomic_pte(struct page *page, enum km_type type) static void vmi_allocate_pte(struct mm_struct *mm, unsigned long pfn) { - vmi_set_page_type(pfn, VMI_PAGE_L1); vmi_ops.allocate_page(pfn, VMI_PAGE_L1, 0, 0, 0); } @@ -406,27 +302,22 @@ static void vmi_allocate_pmd(struct mm_struct *mm, unsigned long pfn) * It is called only for swapper_pg_dir, which already has * data on it. */ - vmi_set_page_type(pfn, VMI_PAGE_L2); vmi_ops.allocate_page(pfn, VMI_PAGE_L2, 0, 0, 0); } static void vmi_allocate_pmd_clone(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count) { - vmi_set_page_type(pfn, VMI_PAGE_L2 | VMI_PAGE_CLONE); - vmi_check_page_type(clonepfn, VMI_PAGE_L2); vmi_ops.allocate_page(pfn, VMI_PAGE_L2 | VMI_PAGE_CLONE, clonepfn, start, count); } static void vmi_release_pte(unsigned long pfn) { vmi_ops.release_page(pfn, VMI_PAGE_L1); - vmi_set_page_type(pfn, VMI_PAGE_NORMAL); } static void vmi_release_pmd(unsigned long pfn) { vmi_ops.release_page(pfn, VMI_PAGE_L2); - vmi_set_page_type(pfn, VMI_PAGE_NORMAL); } /* @@ -450,26 +341,22 @@ static void vmi_release_pmd(unsigned long pfn) static void vmi_update_pte(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { - vmi_check_page_type(__pa(ptep) >> PAGE_SHIFT, VMI_PAGE_PTE); vmi_ops.update_pte(ptep, vmi_flags_addr(mm, addr, VMI_PAGE_PT, 0)); } static void vmi_update_pte_defer(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { - vmi_check_page_type(__pa(ptep) >> PAGE_SHIFT, VMI_PAGE_PTE); vmi_ops.update_pte(ptep, vmi_flags_addr_defer(mm, addr, VMI_PAGE_PT, 0)); } static void vmi_set_pte(pte_t *ptep, pte_t pte) { /* XXX because of set_pmd_pte, this can be called on PT or PD layers */ - vmi_check_page_type(__pa(ptep) >> PAGE_SHIFT, VMI_PAGE_PTE | VMI_PAGE_PD); vmi_ops.set_pte(pte, ptep, VMI_PAGE_PT); } static void vmi_set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) { - vmi_check_page_type(__pa(ptep) >> PAGE_SHIFT, VMI_PAGE_PTE); vmi_ops.set_pte(pte, ptep, vmi_flags_addr(mm, addr, VMI_PAGE_PT, 0)); } @@ -477,10 +364,8 @@ static void vmi_set_pmd(pmd_t *pmdp, pmd_t pmdval) { #ifdef CONFIG_X86_PAE const pte_t pte = { .pte = pmdval.pmd }; - vmi_check_page_type(__pa(pmdp) >> PAGE_SHIFT, VMI_PAGE_PMD); #else const pte_t pte = { pmdval.pud.pgd.pgd }; - vmi_check_page_type(__pa(pmdp) >> PAGE_SHIFT, VMI_PAGE_PGD); #endif vmi_ops.set_pte(pte, (pte_t *)pmdp, VMI_PAGE_PD); } @@ -502,7 +387,6 @@ static void vmi_set_pte_atomic(pte_t *ptep, pte_t pteval) static void vmi_set_pte_present(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) { - vmi_check_page_type(__pa(ptep) >> PAGE_SHIFT, VMI_PAGE_PTE); vmi_ops.set_pte(pte, ptep, vmi_flags_addr_defer(mm, addr, VMI_PAGE_PT, 1)); } @@ -510,21 +394,18 @@ static void vmi_set_pud(pud_t *pudp, pud_t pudval) { /* Um, eww */ const pte_t pte = { .pte = pudval.pgd.pgd }; - vmi_check_page_type(__pa(pudp) >> PAGE_SHIFT, VMI_PAGE_PGD); vmi_ops.set_pte(pte, (pte_t *)pudp, VMI_PAGE_PDP); } static void vmi_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { const pte_t pte = { .pte = 0 }; - vmi_check_page_type(__pa(ptep) >> PAGE_SHIFT, VMI_PAGE_PTE); vmi_ops.set_pte(pte, ptep, vmi_flags_addr(mm, addr, VMI_PAGE_PT, 0)); } static void vmi_pmd_clear(pmd_t *pmd) { const pte_t pte = { .pte = 0 }; - vmi_check_page_type(__pa(pmd) >> PAGE_SHIFT, VMI_PAGE_PMD); vmi_ops.set_pte(pte, (pte_t *)pmd, VMI_PAGE_PD); } #endif @@ -960,8 +841,6 @@ static inline int __init activate_vmi(void) void __init vmi_init(void) { - unsigned long flags; - if (!vmi_rom) probe_vmi_rom(); else @@ -973,13 +852,21 @@ void __init vmi_init(void) reserve_top_address(-vmi_rom->virtual_top); - local_irq_save(flags); - activate_vmi(); - #ifdef CONFIG_X86_IO_APIC /* This is virtual hardware; timer routing is wired correctly */ no_timer_check = 1; #endif +} + +void vmi_activate(void) +{ + unsigned long flags; + + if (!vmi_rom) + return; + + local_irq_save(flags); + activate_vmi(); local_irq_restore(flags & X86_EFLAGS_IF); } diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c index 7766d36983fc..a688f3bfaec2 100644 --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c @@ -78,7 +78,7 @@ static unsigned __init_or_module vsmp_patch(u8 type, u16 clobbers, void *ibuf, static void __init set_vsmp_pv_ops(void) { - void *address; + void __iomem *address; unsigned int cap, ctl, cfg; /* set vSMP magic bits to indicate vSMP capable kernel */ diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c index 0b8b6690a86d..ebf2f12900f5 100644 --- a/arch/x86/kernel/vsyscall_64.c +++ b/arch/x86/kernel/vsyscall_64.c @@ -128,7 +128,16 @@ static __always_inline void do_vgettimeofday(struct timeval * tv) gettimeofday(tv,NULL); return; } + + /* + * Surround the RDTSC by barriers, to make sure it's not + * speculated to outside the seqlock critical section and + * does not cause time warps: + */ + rdtsc_barrier(); now = vread(); + rdtsc_barrier(); + base = __vsyscall_gtod_data.clock.cycle_last; mask = __vsyscall_gtod_data.clock.mask; mult = __vsyscall_gtod_data.clock.mult; diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c index b545f371b5f5..695e426aa354 100644 --- a/arch/x86/kernel/x8664_ksyms_64.c +++ b/arch/x86/kernel/x8664_ksyms_64.c @@ -12,7 +12,7 @@ #include #include -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER /* mcount is defined in assembly */ EXPORT_SYMBOL(mcount); #endif diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c index b13acb75e822..15c3e6999182 100644 --- a/arch/x86/kernel/xsave.c +++ b/arch/x86/kernel/xsave.c @@ -310,7 +310,7 @@ static void __init setup_xstate_init(void) /* * Enable and initialize the xsave feature. */ -void __init xsave_cntxt_init(void) +void __ref xsave_cntxt_init(void) { unsigned int eax, ebx, ecx, edx; diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig index ce3251ce5504..b81125f0bdee 100644 --- a/arch/x86/kvm/Kconfig +++ b/arch/x86/kvm/Kconfig @@ -20,6 +20,8 @@ if VIRTUALIZATION config KVM tristate "Kernel-based Virtual Machine (KVM) support" depends on HAVE_KVM + # for device assignment: + depends on PCI select PREEMPT_NOTIFIERS select MMU_NOTIFIER select ANON_INODES diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c index 11c6725fb798..59ebd37ad79e 100644 --- a/arch/x86/kvm/i8254.c +++ b/arch/x86/kvm/i8254.c @@ -545,6 +545,14 @@ struct kvm_pit *kvm_create_pit(struct kvm *kvm) if (!pit) return NULL; + mutex_lock(&kvm->lock); + pit->irq_source_id = kvm_request_irq_source_id(kvm); + mutex_unlock(&kvm->lock); + if (pit->irq_source_id < 0) { + kfree(pit); + return NULL; + } + mutex_init(&pit->pit_state.lock); mutex_lock(&pit->pit_state.lock); spin_lock_init(&pit->pit_state.inject_lock); @@ -587,6 +595,7 @@ void kvm_free_pit(struct kvm *kvm) mutex_lock(&kvm->arch.vpit->pit_state.lock); timer = &kvm->arch.vpit->pit_state.pit_timer.timer; hrtimer_cancel(timer); + kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id); mutex_unlock(&kvm->arch.vpit->pit_state.lock); kfree(kvm->arch.vpit); } @@ -595,8 +604,8 @@ void kvm_free_pit(struct kvm *kvm) static void __inject_pit_timer_intr(struct kvm *kvm) { mutex_lock(&kvm->lock); - kvm_set_irq(kvm, 0, 1); - kvm_set_irq(kvm, 0, 0); + kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1); + kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0); mutex_unlock(&kvm->lock); } diff --git a/arch/x86/kvm/i8254.h b/arch/x86/kvm/i8254.h index e436d4983aa1..4178022b97aa 100644 --- a/arch/x86/kvm/i8254.h +++ b/arch/x86/kvm/i8254.h @@ -44,6 +44,7 @@ struct kvm_pit { struct kvm_io_device speaker_dev; struct kvm *kvm; struct kvm_kpit_state pit_state; + int irq_source_id; }; #define KVM_PIT_BASE_ADDRESS 0x40 diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 99c239c5c0ac..410ddbc1aa2e 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -314,7 +314,7 @@ static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) if (r) goto out; r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, - rmap_desc_cache, 1); + rmap_desc_cache, 4); if (r) goto out; r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); @@ -1038,13 +1038,13 @@ static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) } rmap_write_protect(vcpu->kvm, sp->gfn); + kvm_unlink_unsync_page(vcpu->kvm, sp); if (vcpu->arch.mmu.sync_page(vcpu, sp)) { kvm_mmu_zap_page(vcpu->kvm, sp); return 1; } kvm_mmu_flush_tlb(vcpu); - kvm_unlink_unsync_page(vcpu->kvm, sp); return 0; } @@ -2634,6 +2634,7 @@ static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) { kvm_x86_ops->tlb_flush(vcpu); + set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests); return 1; } diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h index 613ec9aa674a..84eee43bbe74 100644 --- a/arch/x86/kvm/paging_tmpl.h +++ b/arch/x86/kvm/paging_tmpl.h @@ -331,6 +331,7 @@ static int FNAME(shadow_walk_entry)(struct kvm_shadow_walk *_sw, r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 2], &curr_pte, sizeof(curr_pte)); if (r || curr_pte != gw->ptes[level - 2]) { + kvm_mmu_put_page(shadow_page, sptep); kvm_release_pfn_clean(sw->pfn); sw->sptep = NULL; return 1; diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 2643b430d83a..a4018b01e1f9 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3149,7 +3149,9 @@ static void vmx_intr_assist(struct kvm_vcpu *vcpu) if (cpu_has_virtual_nmis()) { if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { - if (vmx_nmi_enabled(vcpu)) { + if (vcpu->arch.interrupt.pending) { + enable_nmi_window(vcpu); + } else if (vmx_nmi_enabled(vcpu)) { vcpu->arch.nmi_pending = false; vcpu->arch.nmi_injected = true; } else { @@ -3564,7 +3566,8 @@ static int __init vmx_init(void) bypass_guest_pf = 0; kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | VMX_EPT_WRITABLE_MASK | - VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); + VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT | + VMX_EPT_IGMT_BIT); kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, VMX_EPT_EXECUTABLE_MASK); kvm_enable_tdp(); diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h index 3e010d21fdd7..ec5edc339da6 100644 --- a/arch/x86/kvm/vmx.h +++ b/arch/x86/kvm/vmx.h @@ -352,6 +352,7 @@ enum vmcs_field { #define VMX_EPT_READABLE_MASK 0x1ull #define VMX_EPT_WRITABLE_MASK 0x2ull #define VMX_EPT_EXECUTABLE_MASK 0x4ull +#define VMX_EPT_IGMT_BIT (1ull << 6) #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4f0677d1eae8..f1f8ff2f1fa2 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1742,7 +1742,8 @@ long kvm_arch_vm_ioctl(struct file *filp, goto out; if (irqchip_in_kernel(kvm)) { mutex_lock(&kvm->lock); - kvm_set_irq(kvm, irq_event.irq, irq_event.level); + kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, + irq_event.irq, irq_event.level); mutex_unlock(&kvm->lock); r = 0; } @@ -4013,6 +4014,9 @@ struct kvm *kvm_arch_create_vm(void) INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); + /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ + set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); + return kvm; } diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index 48ee4f9435f4..a5d8e1ace1cf 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -367,10 +367,9 @@ static void lguest_cpuid(unsigned int *ax, unsigned int *bx, * lazily after a task switch, and Linux uses that gratefully, but wouldn't a * name like "FPUTRAP bit" be a little less cryptic? * - * We store cr0 (and cr3) locally, because the Host never changes it. The - * Guest sometimes wants to read it and we'd prefer not to bother the Host - * unnecessarily. */ -static unsigned long current_cr0, current_cr3; + * We store cr0 locally because the Host never changes it. The Guest sometimes + * wants to read it and we'd prefer not to bother the Host unnecessarily. */ +static unsigned long current_cr0; static void lguest_write_cr0(unsigned long val) { lazy_hcall(LHCALL_TS, val & X86_CR0_TS, 0, 0); @@ -399,17 +398,23 @@ static unsigned long lguest_read_cr2(void) return lguest_data.cr2; } +/* See lguest_set_pte() below. */ +static bool cr3_changed = false; + /* cr3 is the current toplevel pagetable page: the principle is the same as - * cr0. Keep a local copy, and tell the Host when it changes. */ + * cr0. Keep a local copy, and tell the Host when it changes. The only + * difference is that our local copy is in lguest_data because the Host needs + * to set it upon our initial hypercall. */ static void lguest_write_cr3(unsigned long cr3) { + lguest_data.pgdir = cr3; lazy_hcall(LHCALL_NEW_PGTABLE, cr3, 0, 0); - current_cr3 = cr3; + cr3_changed = true; } static unsigned long lguest_read_cr3(void) { - return current_cr3; + return lguest_data.pgdir; } /* cr4 is used to enable and disable PGE, but we don't care. */ @@ -498,13 +503,13 @@ static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval) * to forget all of them. Fortunately, this is very rare. * * ... except in early boot when the kernel sets up the initial pagetables, - * which makes booting astonishingly slow. So we don't even tell the Host - * anything changed until we've done the first page table switch. */ + * which makes booting astonishingly slow: 1.83 seconds! So we don't even tell + * the Host anything changed until we've done the first page table switch, + * which brings boot back to 0.25 seconds. */ static void lguest_set_pte(pte_t *ptep, pte_t pteval) { *ptep = pteval; - /* Don't bother with hypercall before initial setup. */ - if (current_cr3) + if (cr3_changed) lazy_hcall(LHCALL_FLUSH_TLB, 1, 0, 0); } @@ -521,7 +526,7 @@ static void lguest_set_pte(pte_t *ptep, pte_t pteval) static void lguest_flush_tlb_single(unsigned long addr) { /* Simply set it to zero: if it was not, it will fault back in. */ - lazy_hcall(LHCALL_SET_PTE, current_cr3, addr, 0); + lazy_hcall(LHCALL_SET_PTE, lguest_data.pgdir, addr, 0); } /* This is what happens after the Guest has removed a large number of entries. @@ -581,6 +586,9 @@ static void __init lguest_init_IRQ(void) for (i = 0; i < LGUEST_IRQS; i++) { int vector = FIRST_EXTERNAL_VECTOR + i; + /* Some systems map "vectors" to interrupts weirdly. Lguest has + * a straightforward 1 to 1 mapping, so force that here. */ + __get_cpu_var(vector_irq)[vector] = i; if (vector != SYSCALL_VECTOR) { set_intr_gate(vector, interrupt[vector]); set_irq_chip_and_handler_name(i, &lguest_irq_controller, diff --git a/arch/x86/mach-generic/bigsmp.c b/arch/x86/mach-generic/bigsmp.c index 3c3b471ea496..3624a364b7f3 100644 --- a/arch/x86/mach-generic/bigsmp.c +++ b/arch/x86/mach-generic/bigsmp.c @@ -17,6 +17,7 @@ #include #include #include +#include static int dmi_bigsmp; /* can be set by dmi scanners */ diff --git a/arch/x86/mach-generic/default.c b/arch/x86/mach-generic/default.c index 9e835a11a13a..e63a4a76d8cd 100644 --- a/arch/x86/mach-generic/default.c +++ b/arch/x86/mach-generic/default.c @@ -16,6 +16,7 @@ #include #include #include +#include /* should be called last. */ static int probe_default(void) diff --git a/arch/x86/mach-generic/es7000.c b/arch/x86/mach-generic/es7000.c index 28459cab3ddb..7b4e6d0d1690 100644 --- a/arch/x86/mach-generic/es7000.c +++ b/arch/x86/mach-generic/es7000.c @@ -16,7 +16,19 @@ #include #include #include -#include +#include + +void __init es7000_update_genapic_to_cluster(void) +{ + genapic->target_cpus = target_cpus_cluster; + genapic->int_delivery_mode = INT_DELIVERY_MODE_CLUSTER; + genapic->int_dest_mode = INT_DEST_MODE_CLUSTER; + genapic->no_balance_irq = NO_BALANCE_IRQ_CLUSTER; + + genapic->init_apic_ldr = init_apic_ldr_cluster; + + genapic->cpu_mask_to_apicid = cpu_mask_to_apicid_cluster; +} static int probe_es7000(void) { diff --git a/arch/x86/mach-generic/probe.c b/arch/x86/mach-generic/probe.c index 5a7e4619e1c4..c346d9d0226f 100644 --- a/arch/x86/mach-generic/probe.c +++ b/arch/x86/mach-generic/probe.c @@ -15,6 +15,7 @@ #include #include #include +#include extern struct genapic apic_numaq; extern struct genapic apic_summit; @@ -57,6 +58,9 @@ static int __init parse_apic(char *arg) } } + if (x86_quirks->update_genapic) + x86_quirks->update_genapic(); + /* Parsed again by __setup for debug/verbose */ return 0; } @@ -72,12 +76,15 @@ void __init generic_bigsmp_probe(void) * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support */ - if (!cmdline_apic && genapic == &apic_default) + if (!cmdline_apic && genapic == &apic_default) { if (apic_bigsmp.probe()) { genapic = &apic_bigsmp; + if (x86_quirks->update_genapic) + x86_quirks->update_genapic(); printk(KERN_INFO "Overriding APIC driver with %s\n", genapic->name); } + } #endif } @@ -94,6 +101,9 @@ void __init generic_apic_probe(void) /* Not visible without early console */ if (!apic_probe[i]) panic("Didn't find an APIC driver"); + + if (x86_quirks->update_genapic) + x86_quirks->update_genapic(); } printk(KERN_INFO "Using APIC driver %s\n", genapic->name); } @@ -108,6 +118,8 @@ int __init mps_oem_check(struct mp_config_table *mpc, char *oem, if (apic_probe[i]->mps_oem_check(mpc, oem, productid)) { if (!cmdline_apic) { genapic = apic_probe[i]; + if (x86_quirks->update_genapic) + x86_quirks->update_genapic(); printk(KERN_INFO "Switched to APIC driver `%s'.\n", genapic->name); } @@ -124,6 +136,8 @@ int __init acpi_madt_oem_check(char *oem_id, char *oem_table_id) if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) { if (!cmdline_apic) { genapic = apic_probe[i]; + if (x86_quirks->update_genapic) + x86_quirks->update_genapic(); printk(KERN_INFO "Switched to APIC driver `%s'.\n", genapic->name); } diff --git a/arch/x86/mach-generic/summit.c b/arch/x86/mach-generic/summit.c index 6272b5e69da6..2c6d234e0009 100644 --- a/arch/x86/mach-generic/summit.c +++ b/arch/x86/mach-generic/summit.c @@ -16,6 +16,7 @@ #include #include #include +#include static int probe_summit(void) { diff --git a/arch/x86/mach-voyager/setup.c b/arch/x86/mach-voyager/setup.c index 6bbdd633864c..a580b9562e76 100644 --- a/arch/x86/mach-voyager/setup.c +++ b/arch/x86/mach-voyager/setup.c @@ -27,7 +27,7 @@ static struct irqaction irq2 = { void __init intr_init_hook(void) { #ifdef CONFIG_SMP - smp_intr_init(); + voyager_smp_intr_init(); #endif setup_irq(2, &irq2); diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c index 0f6e8a6523ae..52145007bd7e 100644 --- a/arch/x86/mach-voyager/voyager_smp.c +++ b/arch/x86/mach-voyager/voyager_smp.c @@ -7,6 +7,7 @@ * This file provides all the same external entries as smp.c but uses * the voyager hal to provide the functionality */ +#include #include #include #include @@ -90,6 +91,7 @@ static void ack_vic_irq(unsigned int irq); static void vic_enable_cpi(void); static void do_boot_cpu(__u8 cpuid); static void do_quad_bootstrap(void); +static void initialize_secondary(void); int hard_smp_processor_id(void); int safe_smp_processor_id(void); @@ -344,6 +346,12 @@ static void do_quad_bootstrap(void) } } +void prefill_possible_map(void) +{ + /* This is empty on voyager because we need a much + * earlier detection which is done in find_smp_config */ +} + /* Set up all the basic stuff: read the SMP config and make all the * SMP information reflect only the boot cpu. All others will be * brought on-line later. */ @@ -413,6 +421,7 @@ void __init smp_store_cpu_info(int id) struct cpuinfo_x86 *c = &cpu_data(id); *c = boot_cpu_data; + c->cpu_index = id; identify_secondary_cpu(c); } @@ -650,6 +659,8 @@ void __init smp_boot_cpus(void) smp_tune_scheduling(); */ smp_store_cpu_info(boot_cpu_id); + /* setup the jump vector */ + initial_code = (unsigned long)initialize_secondary; printk("CPU%d: ", boot_cpu_id); print_cpu_info(&cpu_data(boot_cpu_id)); @@ -702,7 +713,7 @@ void __init smp_boot_cpus(void) /* Reload the secondary CPUs task structure (this function does not * return ) */ -void __init initialize_secondary(void) +static void __init initialize_secondary(void) { #if 0 // AC kernels only @@ -1248,7 +1259,7 @@ static void handle_vic_irq(unsigned int irq, struct irq_desc *desc) #define QIC_SET_GATE(cpi, vector) \ set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector)) -void __init smp_intr_init(void) +void __init voyager_smp_intr_init(void) { int i; @@ -1780,6 +1791,17 @@ void __init smp_setup_processor_id(void) x86_write_percpu(cpu_number, hard_smp_processor_id()); } +static void voyager_send_call_func(cpumask_t callmask) +{ + __u32 mask = cpus_addr(callmask)[0] & ~(1 << smp_processor_id()); + send_CPI(mask, VIC_CALL_FUNCTION_CPI); +} + +static void voyager_send_call_func_single(int cpu) +{ + send_CPI(1 << cpu, VIC_CALL_FUNCTION_SINGLE_CPI); +} + struct smp_ops smp_ops = { .smp_prepare_boot_cpu = voyager_smp_prepare_boot_cpu, .smp_prepare_cpus = voyager_smp_prepare_cpus, @@ -1789,6 +1811,6 @@ struct smp_ops smp_ops = { .smp_send_stop = voyager_smp_send_stop, .smp_send_reschedule = voyager_smp_send_reschedule, - .send_call_func_ipi = native_send_call_func_ipi, - .send_call_func_single_ipi = native_send_call_func_single_ipi, + .send_call_func_ipi = voyager_send_call_func, + .send_call_func_single_ipi = voyager_send_call_func_single, }; diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index 59f89b434b45..fea4565ff576 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -1,7 +1,7 @@ obj-y := init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \ pat.o pgtable.o gup.o -obj-$(CONFIG_X86_32) += pgtable_32.o +obj-$(CONFIG_X86_32) += pgtable_32.o iomap_32.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_X86_PTDUMP) += dump_pagetables.o diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 31e8730fa246..20ef272c412c 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -413,6 +413,7 @@ static noinline void pgtable_bad(unsigned long address, struct pt_regs *regs, unsigned long error_code) { unsigned long flags = oops_begin(); + int sig = SIGKILL; struct task_struct *tsk; printk(KERN_ALERT "%s: Corrupted page table at address %lx\n", @@ -423,8 +424,8 @@ static noinline void pgtable_bad(unsigned long address, struct pt_regs *regs, tsk->thread.trap_no = 14; tsk->thread.error_code = error_code; if (__die("Bad pagetable", regs, error_code)) - regs = NULL; - oops_end(flags, regs, SIGKILL); + sig = 0; + oops_end(flags, regs, sig); } #endif @@ -590,6 +591,7 @@ void __kprobes do_page_fault(struct pt_regs *regs, unsigned long error_code) int fault; #ifdef CONFIG_X86_64 unsigned long flags; + int sig; #endif tsk = current; @@ -849,11 +851,12 @@ no_context: bust_spinlocks(0); do_exit(SIGKILL); #else + sig = SIGKILL; if (__die("Oops", regs, error_code)) - regs = NULL; + sig = 0; /* Executive summary in case the body of the oops scrolled away */ printk(KERN_EMERG "CR2: %016lx\n", address); - oops_end(flags, regs, SIGKILL); + oops_end(flags, regs, sig); #endif /* diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index 4ba373c5b8c8..be54176e9eb2 100644 --- a/arch/x86/mm/gup.c +++ b/arch/x86/mm/gup.c @@ -233,7 +233,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, len = (unsigned long) nr_pages << PAGE_SHIFT; end = start + len; if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ, - start, len))) + (void __user *)start, len))) goto slow_irqon; /* diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index 8396868e82c5..800e1d94c1b5 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -67,7 +67,7 @@ static unsigned long __meminitdata table_top; static int __initdata after_init_bootmem; -static __init void *alloc_low_page(unsigned long *phys) +static __init void *alloc_low_page(void) { unsigned long pfn = table_end++; void *adr; @@ -77,7 +77,6 @@ static __init void *alloc_low_page(unsigned long *phys) adr = __va(pfn * PAGE_SIZE); memset(adr, 0, PAGE_SIZE); - *phys = pfn * PAGE_SIZE; return adr; } @@ -92,16 +91,17 @@ static pmd_t * __init one_md_table_init(pgd_t *pgd) pmd_t *pmd_table; #ifdef CONFIG_X86_PAE - unsigned long phys; if (!(pgd_val(*pgd) & _PAGE_PRESENT)) { if (after_init_bootmem) pmd_table = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE); else - pmd_table = (pmd_t *)alloc_low_page(&phys); + pmd_table = (pmd_t *)alloc_low_page(); paravirt_alloc_pmd(&init_mm, __pa(pmd_table) >> PAGE_SHIFT); set_pgd(pgd, __pgd(__pa(pmd_table) | _PAGE_PRESENT)); pud = pud_offset(pgd, 0); BUG_ON(pmd_table != pmd_offset(pud, 0)); + + return pmd_table; } #endif pud = pud_offset(pgd, 0); @@ -126,10 +126,8 @@ static pte_t * __init one_page_table_init(pmd_t *pmd) if (!page_table) page_table = (pte_t *)alloc_bootmem_low_pages(PAGE_SIZE); - } else { - unsigned long phys; - page_table = (pte_t *)alloc_low_page(&phys); - } + } else + page_table = (pte_t *)alloc_low_page(); paravirt_alloc_pte(&init_mm, __pa(page_table) >> PAGE_SHIFT); set_pmd(pmd, __pmd(__pa(page_table) | _PAGE_TABLE)); @@ -334,7 +332,6 @@ int devmem_is_allowed(unsigned long pagenr) return 0; } -#ifdef CONFIG_HIGHMEM pte_t *kmap_pte; pgprot_t kmap_prot; @@ -357,6 +354,7 @@ static void __init kmap_init(void) kmap_prot = PAGE_KERNEL; } +#ifdef CONFIG_HIGHMEM static void __init permanent_kmaps_init(pgd_t *pgd_base) { unsigned long vaddr; @@ -436,7 +434,6 @@ static void __init set_highmem_pages_init(void) #endif /* !CONFIG_NUMA */ #else -# define kmap_init() do { } while (0) # define permanent_kmaps_init(pgd_base) do { } while (0) # define set_highmem_pages_init() do { } while (0) #endif /* CONFIG_HIGHMEM */ @@ -970,8 +967,6 @@ void __init mem_init(void) int codesize, reservedpages, datasize, initsize; int tmp; - start_periodic_check_for_corruption(); - #ifdef CONFIG_FLATMEM BUG_ON(!mem_map); #endif @@ -1041,11 +1036,25 @@ void __init mem_init(void) (unsigned long)&_text, (unsigned long)&_etext, ((unsigned long)&_etext - (unsigned long)&_text) >> 10); + /* + * Check boundaries twice: Some fundamental inconsistencies can + * be detected at build time already. + */ +#define __FIXADDR_TOP (-PAGE_SIZE) +#ifdef CONFIG_HIGHMEM + BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP*PAGE_SIZE > FIXADDR_START); + BUILD_BUG_ON(VMALLOC_END > PKMAP_BASE); +#endif +#define high_memory (-128UL << 20) + BUILD_BUG_ON(VMALLOC_START >= VMALLOC_END); +#undef high_memory +#undef __FIXADDR_TOP + #ifdef CONFIG_HIGHMEM BUG_ON(PKMAP_BASE + LAST_PKMAP*PAGE_SIZE > FIXADDR_START); BUG_ON(VMALLOC_END > PKMAP_BASE); #endif - BUG_ON(VMALLOC_START > VMALLOC_END); + BUG_ON(VMALLOC_START >= VMALLOC_END); BUG_ON((unsigned long)high_memory > VMALLOC_START); if (boot_cpu_data.wp_works_ok < 0) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index b8e461d49412..9f7a0d24d42a 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -350,8 +350,10 @@ phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end, * pagetable pages as RO. So assume someone who pre-setup * these mappings are more intelligent. */ - if (pte_val(*pte)) + if (pte_val(*pte)) { + pages++; continue; + } if (0) printk(" pte=%p addr=%lx pte=%016lx\n", @@ -418,8 +420,10 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end, * not differ with respect to page frame and * attributes. */ - if (page_size_mask & (1 << PG_LEVEL_2M)) + if (page_size_mask & (1 << PG_LEVEL_2M)) { + pages++; continue; + } new_prot = pte_pgprot(pte_clrhuge(*(pte_t *)pmd)); } @@ -499,8 +503,10 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end, * not differ with respect to page frame and * attributes. */ - if (page_size_mask & (1 << PG_LEVEL_1G)) + if (page_size_mask & (1 << PG_LEVEL_1G)) { + pages++; continue; + } prot = pte_pgprot(pte_clrhuge(*(pte_t *)pud)); } @@ -665,12 +671,13 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, unsigned long last_map_addr = 0; unsigned long page_size_mask = 0; unsigned long start_pfn, end_pfn; + unsigned long pos; struct map_range mr[NR_RANGE_MR]; int nr_range, i; int use_pse, use_gbpages; - printk(KERN_INFO "init_memory_mapping\n"); + printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end); /* * Find space for the kernel direct mapping tables. @@ -704,35 +711,50 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, /* head if not big page alignment ?*/ start_pfn = start >> PAGE_SHIFT; - end_pfn = ((start + (PMD_SIZE - 1)) >> PMD_SHIFT) + pos = start_pfn << PAGE_SHIFT; + end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); + pos = end_pfn << PAGE_SHIFT; + } /* big page (2M) range*/ - start_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT) + start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); - end_pfn = ((start + (PUD_SIZE - 1))>>PUD_SHIFT) + end_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); - if (end_pfn > ((end>>PUD_SHIFT)<<(PUD_SHIFT - PAGE_SHIFT))) - end_pfn = ((end>>PUD_SHIFT)<<(PUD_SHIFT - PAGE_SHIFT)); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, - page_size_mask & (1< ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT))) + end_pfn = ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT)); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, + page_size_mask & (1<>PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, + start_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) + << (PUD_SHIFT - PAGE_SHIFT); + end_pfn = (end >> PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, page_size_mask & ((1<>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, - page_size_mask & (1<>PMD_SHIFT) + << (PMD_SHIFT - PAGE_SHIFT); + end_pfn = (end >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, + page_size_mask & (1<>PAGE_SHIFT; end_pfn = end>>PAGE_SHIFT; nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); @@ -831,12 +853,12 @@ int arch_add_memory(int nid, u64 start, u64 size) unsigned long nr_pages = size >> PAGE_SHIFT; int ret; - last_mapped_pfn = init_memory_mapping(start, start + size-1); + last_mapped_pfn = init_memory_mapping(start, start + size); if (last_mapped_pfn > max_pfn_mapped) max_pfn_mapped = last_mapped_pfn; ret = __add_pages(zone, start_pfn, nr_pages); - WARN_ON(1); + WARN_ON_ONCE(ret); return ret; } @@ -878,8 +900,7 @@ static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel, void __init mem_init(void) { long codesize, reservedpages, datasize, initsize; - - start_periodic_check_for_corruption(); + unsigned long absent_pages; pci_iommu_alloc(); @@ -893,8 +914,9 @@ void __init mem_init(void) #else totalram_pages = free_all_bootmem(); #endif - reservedpages = max_pfn - totalram_pages - - absent_pages_in_range(0, max_pfn); + + absent_pages = absent_pages_in_range(0, max_pfn); + reservedpages = max_pfn - totalram_pages - absent_pages; after_bootmem = 1; codesize = (unsigned long) &_etext - (unsigned long) &_text; @@ -911,10 +933,11 @@ void __init mem_init(void) VSYSCALL_END - VSYSCALL_START); printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " - "%ldk reserved, %ldk data, %ldk init)\n", + "%ldk absent, %ldk reserved, %ldk data, %ldk init)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), max_pfn << (PAGE_SHIFT-10), codesize >> 10, + absent_pages << (PAGE_SHIFT-10), reservedpages << (PAGE_SHIFT-10), datasize >> 10, initsize >> 10); diff --git a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c new file mode 100644 index 000000000000..d0151d8ce452 --- /dev/null +++ b/arch/x86/mm/iomap_32.c @@ -0,0 +1,59 @@ +/* + * Copyright © 2008 Ingo Molnar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include +#include + +/* Map 'pfn' using fixed map 'type' and protections 'prot' + */ +void * +iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) +{ + enum fixed_addresses idx; + unsigned long vaddr; + + pagefault_disable(); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); + set_pte(kmap_pte-idx, pfn_pte(pfn, prot)); + arch_flush_lazy_mmu_mode(); + + return (void*) vaddr; +} +EXPORT_SYMBOL_GPL(iomap_atomic_prot_pfn); + +void +iounmap_atomic(void *kvaddr, enum km_type type) +{ + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; + enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); + + /* + * Force other mappings to Oops if they'll try to access this pte + * without first remap it. Keeping stale mappings around is a bad idea + * also, in case the page changes cacheability attributes or becomes + * a protected page in a hypervisor. + */ + if (vaddr == __fix_to_virt(FIX_KMAP_BEGIN+idx)) + kpte_clear_flush(kmap_pte-idx, vaddr); + + arch_flush_lazy_mmu_mode(); + pagefault_enable(); +} +EXPORT_SYMBOL_GPL(iounmap_atomic); diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index ae71e11eb3e5..bd85d42819e1 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -223,7 +223,8 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr, * Check if the request spans more than any BAR in the iomem resource * tree. */ - WARN_ON(iomem_map_sanity_check(phys_addr, size)); + WARN_ONCE(iomem_map_sanity_check(phys_addr, size), + KERN_INFO "Info: mapping multiple BARs. Your kernel is fine."); /* * Don't allow anybody to remap normal RAM that we're using.. @@ -387,7 +388,7 @@ static void __iomem *ioremap_default(resource_size_t phys_addr, unsigned long size) { unsigned long flags; - void *ret; + void __iomem *ret; int err; /* @@ -399,11 +400,11 @@ static void __iomem *ioremap_default(resource_size_t phys_addr, if (err < 0) return NULL; - ret = (void *) __ioremap_caller(phys_addr, size, flags, - __builtin_return_address(0)); + ret = __ioremap_caller(phys_addr, size, flags, + __builtin_return_address(0)); free_memtype(phys_addr, phys_addr + size); - return (void __iomem *)ret; + return ret; } void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size, @@ -622,7 +623,7 @@ static inline void __init early_clear_fixmap(enum fixed_addresses idx) __early_set_fixmap(idx, 0, __pgprot(0)); } -static void *prev_map[FIX_BTMAPS_SLOTS] __initdata; +static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata; static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata; static int __init check_early_ioremap_leak(void) { @@ -645,7 +646,7 @@ static int __init check_early_ioremap_leak(void) } late_initcall(check_early_ioremap_leak); -static void __init *__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) +static void __init __iomem *__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) { unsigned long offset, last_addr; unsigned int nrpages; @@ -713,23 +714,23 @@ static void __init *__early_ioremap(unsigned long phys_addr, unsigned long size, if (early_ioremap_debug) printk(KERN_CONT "%08lx + %08lx\n", offset, fix_to_virt(idx0)); - prev_map[slot] = (void *) (offset + fix_to_virt(idx0)); + prev_map[slot] = (void __iomem *)(offset + fix_to_virt(idx0)); return prev_map[slot]; } /* Remap an IO device */ -void __init *early_ioremap(unsigned long phys_addr, unsigned long size) +void __init __iomem *early_ioremap(unsigned long phys_addr, unsigned long size) { return __early_ioremap(phys_addr, size, PAGE_KERNEL_IO); } /* Remap memory */ -void __init *early_memremap(unsigned long phys_addr, unsigned long size) +void __init __iomem *early_memremap(unsigned long phys_addr, unsigned long size) { return __early_ioremap(phys_addr, size, PAGE_KERNEL); } -void __init early_iounmap(void *addr, unsigned long size) +void __init early_iounmap(void __iomem *addr, unsigned long size) { unsigned long virt_addr; unsigned long offset; @@ -779,7 +780,7 @@ void __init early_iounmap(void *addr, unsigned long size) --idx; --nrpages; } - prev_map[slot] = 0; + prev_map[slot] = NULL; } void __this_fixmap_does_not_exist(void) diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c index 847c164725f4..8518c678d83f 100644 --- a/arch/x86/mm/numa_32.c +++ b/arch/x86/mm/numa_32.c @@ -222,6 +222,41 @@ static void __init remap_numa_kva(void) } } +#ifdef CONFIG_HIBERNATION +/** + * resume_map_numa_kva - add KVA mapping to the temporary page tables created + * during resume from hibernation + * @pgd_base - temporary resume page directory + */ +void resume_map_numa_kva(pgd_t *pgd_base) +{ + int node; + + for_each_online_node(node) { + unsigned long start_va, start_pfn, size, pfn; + + start_va = (unsigned long)node_remap_start_vaddr[node]; + start_pfn = node_remap_start_pfn[node]; + size = node_remap_size[node]; + + printk(KERN_DEBUG "%s: node %d\n", __FUNCTION__, node); + + for (pfn = 0; pfn < size; pfn += PTRS_PER_PTE) { + unsigned long vaddr = start_va + (pfn << PAGE_SHIFT); + pgd_t *pgd = pgd_base + pgd_index(vaddr); + pud_t *pud = pud_offset(pgd, vaddr); + pmd_t *pmd = pmd_offset(pud, vaddr); + + set_pmd(pmd, pfn_pmd(start_pfn + pfn, + PAGE_KERNEL_LARGE_EXEC)); + + printk(KERN_DEBUG "%s: %08lx -> pfn %08lx\n", + __FUNCTION__, vaddr, start_pfn + pfn); + } + } +} +#endif + static unsigned long calculate_numa_remap_pages(void) { int nid; diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index f1dc1b75d166..e89d24815f26 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -67,18 +67,18 @@ static void split_page_count(int level) void arch_report_meminfo(struct seq_file *m) { - seq_printf(m, "DirectMap4k: %8lu kB\n", + seq_printf(m, "DirectMap4k: %8lu kB\n", direct_pages_count[PG_LEVEL_4K] << 2); #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) - seq_printf(m, "DirectMap2M: %8lu kB\n", + seq_printf(m, "DirectMap2M: %8lu kB\n", direct_pages_count[PG_LEVEL_2M] << 11); #else - seq_printf(m, "DirectMap4M: %8lu kB\n", + seq_printf(m, "DirectMap4M: %8lu kB\n", direct_pages_count[PG_LEVEL_2M] << 12); #endif #ifdef CONFIG_X86_64 if (direct_gbpages) - seq_printf(m, "DirectMap1G: %8lu kB\n", + seq_printf(m, "DirectMap1G: %8lu kB\n", direct_pages_count[PG_LEVEL_1G] << 20); #endif } diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index 738fd0f24958..541bcc944a5b 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -481,12 +481,16 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size) return 1; } #else +/* This check is needed to avoid cache aliasing when PAT is enabled */ static inline int range_is_allowed(unsigned long pfn, unsigned long size) { u64 from = ((u64)pfn) << PAGE_SHIFT; u64 to = from + size; u64 cursor = from; + if (!pat_enabled) + return 1; + while (cursor < to) { if (!devmem_is_allowed(pfn)) { printk(KERN_INFO @@ -592,6 +596,242 @@ void unmap_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot) free_memtype(addr, addr + size); } +/* + * Internal interface to reserve a range of physical memory with prot. + * Reserved non RAM regions only and after successful reserve_memtype, + * this func also keeps identity mapping (if any) in sync with this new prot. + */ +static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t vma_prot) +{ + int is_ram = 0; + int id_sz, ret; + unsigned long flags; + unsigned long want_flags = (pgprot_val(vma_prot) & _PAGE_CACHE_MASK); + + is_ram = pagerange_is_ram(paddr, paddr + size); + + if (is_ram != 0) { + /* + * For mapping RAM pages, drivers need to call + * set_memory_[uc|wc|wb] directly, for reserve and free, before + * setting up the PTE. + */ + WARN_ON_ONCE(1); + return 0; + } + + ret = reserve_memtype(paddr, paddr + size, want_flags, &flags); + if (ret) + return ret; + + if (flags != want_flags) { + free_memtype(paddr, paddr + size); + printk(KERN_ERR + "%s:%d map pfn expected mapping type %s for %Lx-%Lx, got %s\n", + current->comm, current->pid, + cattr_name(want_flags), + (unsigned long long)paddr, + (unsigned long long)(paddr + size), + cattr_name(flags)); + return -EINVAL; + } + + /* Need to keep identity mapping in sync */ + if (paddr >= __pa(high_memory)) + return 0; + + id_sz = (__pa(high_memory) < paddr + size) ? + __pa(high_memory) - paddr : + size; + + if (ioremap_change_attr((unsigned long)__va(paddr), id_sz, flags) < 0) { + free_memtype(paddr, paddr + size); + printk(KERN_ERR + "%s:%d reserve_pfn_range ioremap_change_attr failed %s " + "for %Lx-%Lx\n", + current->comm, current->pid, + cattr_name(flags), + (unsigned long long)paddr, + (unsigned long long)(paddr + size)); + return -EINVAL; + } + return 0; +} + +/* + * Internal interface to free a range of physical memory. + * Frees non RAM regions only. + */ +static void free_pfn_range(u64 paddr, unsigned long size) +{ + int is_ram; + + is_ram = pagerange_is_ram(paddr, paddr + size); + if (is_ram == 0) + free_memtype(paddr, paddr + size); +} + +/* + * track_pfn_vma_copy is called when vma that is covering the pfnmap gets + * copied through copy_page_range(). + * + * If the vma has a linear pfn mapping for the entire range, we get the prot + * from pte and reserve the entire vma range with single reserve_pfn_range call. + * Otherwise, we reserve the entire vma range, my ging through the PTEs page + * by page to get physical address and protection. + */ +int track_pfn_vma_copy(struct vm_area_struct *vma) +{ + int retval = 0; + unsigned long i, j; + u64 paddr; + unsigned long prot; + unsigned long vma_start = vma->vm_start; + unsigned long vma_end = vma->vm_end; + unsigned long vma_size = vma_end - vma_start; + + if (!pat_enabled) + return 0; + + if (is_linear_pfn_mapping(vma)) { + /* + * reserve the whole chunk covered by vma. We need the + * starting address and protection from pte. + */ + if (follow_phys(vma, vma_start, 0, &prot, &paddr)) { + WARN_ON_ONCE(1); + return -EINVAL; + } + return reserve_pfn_range(paddr, vma_size, __pgprot(prot)); + } + + /* reserve entire vma page by page, using pfn and prot from pte */ + for (i = 0; i < vma_size; i += PAGE_SIZE) { + if (follow_phys(vma, vma_start + i, 0, &prot, &paddr)) + continue; + + retval = reserve_pfn_range(paddr, PAGE_SIZE, __pgprot(prot)); + if (retval) + goto cleanup_ret; + } + return 0; + +cleanup_ret: + /* Reserve error: Cleanup partial reservation and return error */ + for (j = 0; j < i; j += PAGE_SIZE) { + if (follow_phys(vma, vma_start + j, 0, &prot, &paddr)) + continue; + + free_pfn_range(paddr, PAGE_SIZE); + } + + return retval; +} + +/* + * track_pfn_vma_new is called when a _new_ pfn mapping is being established + * for physical range indicated by pfn and size. + * + * prot is passed in as a parameter for the new mapping. If the vma has a + * linear pfn mapping for the entire range reserve the entire vma range with + * single reserve_pfn_range call. + * Otherwise, we look t the pfn and size and reserve only the specified range + * page by page. + * + * Note that this function can be called with caller trying to map only a + * subrange/page inside the vma. + */ +int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot, + unsigned long pfn, unsigned long size) +{ + int retval = 0; + unsigned long i, j; + u64 base_paddr; + u64 paddr; + unsigned long vma_start = vma->vm_start; + unsigned long vma_end = vma->vm_end; + unsigned long vma_size = vma_end - vma_start; + + if (!pat_enabled) + return 0; + + if (is_linear_pfn_mapping(vma)) { + /* reserve the whole chunk starting from vm_pgoff */ + paddr = (u64)vma->vm_pgoff << PAGE_SHIFT; + return reserve_pfn_range(paddr, vma_size, prot); + } + + /* reserve page by page using pfn and size */ + base_paddr = (u64)pfn << PAGE_SHIFT; + for (i = 0; i < size; i += PAGE_SIZE) { + paddr = base_paddr + i; + retval = reserve_pfn_range(paddr, PAGE_SIZE, prot); + if (retval) + goto cleanup_ret; + } + return 0; + +cleanup_ret: + /* Reserve error: Cleanup partial reservation and return error */ + for (j = 0; j < i; j += PAGE_SIZE) { + paddr = base_paddr + j; + free_pfn_range(paddr, PAGE_SIZE); + } + + return retval; +} + +/* + * untrack_pfn_vma is called while unmapping a pfnmap for a region. + * untrack can be called for a specific region indicated by pfn and size or + * can be for the entire vma (in which case size can be zero). + */ +void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn, + unsigned long size) +{ + unsigned long i; + u64 paddr; + unsigned long prot; + unsigned long vma_start = vma->vm_start; + unsigned long vma_end = vma->vm_end; + unsigned long vma_size = vma_end - vma_start; + + if (!pat_enabled) + return; + + if (is_linear_pfn_mapping(vma)) { + /* free the whole chunk starting from vm_pgoff */ + paddr = (u64)vma->vm_pgoff << PAGE_SHIFT; + free_pfn_range(paddr, vma_size); + return; + } + + if (size != 0 && size != vma_size) { + /* free page by page, using pfn and size */ + paddr = (u64)pfn << PAGE_SHIFT; + for (i = 0; i < size; i += PAGE_SIZE) { + paddr = paddr + i; + free_pfn_range(paddr, PAGE_SIZE); + } + } else { + /* free entire vma, page by page, using the pfn from pte */ + for (i = 0; i < vma_size; i += PAGE_SIZE) { + if (follow_phys(vma, vma_start + i, 0, &prot, &paddr)) + continue; + + free_pfn_range(paddr, PAGE_SIZE); + } + } +} + +pgprot_t pgprot_writecombine(pgprot_t prot) +{ + if (pat_enabled) + return __pgprot(pgprot_val(prot) | _PAGE_CACHE_WC); + else + return pgprot_noncached(prot); +} + #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_X86_PAT) /* get Nth element of the linked list */ diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index 022cd41ea9b4..202864ad49a7 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c @@ -401,14 +401,13 @@ static int __init ppro_init(char **cpu_type) *cpu_type = "i386/pii"; break; case 6 ... 8: + case 10 ... 11: *cpu_type = "i386/piii"; break; case 9: + case 13: *cpu_type = "i386/p6_mobile"; break; - case 10 ... 13: - *cpu_type = "i386/p6"; - break; case 14: *cpu_type = "i386/core"; break; diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c index 0620d6d45f7d..e9f80c744cf3 100644 --- a/arch/x86/oprofile/op_model_ppro.c +++ b/arch/x86/oprofile/op_model_ppro.c @@ -27,8 +27,7 @@ static int num_counters = 2; static int counter_width = 32; #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) -#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) -#define CTR_OVERFLOWED(n) (!((n) & (1U<<(counter_width-1)))) +#define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1)))) #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0) #define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0) @@ -70,7 +69,7 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs) int i; if (!reset_value) { - reset_value = kmalloc(sizeof(unsigned) * num_counters, + reset_value = kmalloc(sizeof(reset_value[0]) * num_counters, GFP_ATOMIC); if (!reset_value) return; @@ -124,14 +123,14 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs) static int ppro_check_ctrs(struct pt_regs * const regs, struct op_msrs const * const msrs) { - unsigned int low, high; + u64 val; int i; for (i = 0 ; i < num_counters; ++i) { if (!reset_value[i]) continue; - CTR_READ(low, high, msrs, i); - if (CTR_OVERFLOWED(low)) { + rdmsrl(msrs->counters[i].addr, val); + if (CTR_OVERFLOWED(val)) { oprofile_add_sample(regs, i); wrmsrl(msrs->counters[i].addr, -reset_value[i]); } @@ -157,6 +156,8 @@ static void ppro_start(struct op_msrs const * const msrs) unsigned int low, high; int i; + if (!reset_value) + return; for (i = 0; i < num_counters; ++i) { if (reset_value[i]) { CTRL_READ(low, high, msrs, i); @@ -172,6 +173,8 @@ static void ppro_stop(struct op_msrs const * const msrs) unsigned int low, high; int i; + if (!reset_value) + return; for (i = 0; i < num_counters; ++i) { if (!reset_value[i]) continue; diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c index 9915293500fb..9a5af6c8fbe9 100644 --- a/arch/x86/pci/direct.c +++ b/arch/x86/pci/direct.c @@ -173,7 +173,7 @@ static int pci_conf2_write(unsigned int seg, unsigned int bus, #undef PCI_CONF2_ADDRESS -static struct pci_raw_ops pci_direct_conf2 = { +struct pci_raw_ops pci_direct_conf2 = { .read = pci_conf2_read, .write = pci_conf2_write, }; @@ -289,6 +289,7 @@ int __init pci_direct_probe(void) if (pci_check_type1()) { raw_pci_ops = &pci_direct_conf1; + port_cf9_safe = true; return 1; } release_resource(region); @@ -305,6 +306,7 @@ int __init pci_direct_probe(void) if (pci_check_type2()) { raw_pci_ops = &pci_direct_conf2; + port_cf9_safe = true; return 2; } diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 3c27a809393b..2051dc96b8e9 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -496,21 +496,24 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, pci_siemens_interrupt_controller); /* - * Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config - * have 4096 bytes. Even if the device is capable, that doesn't mean we can - * access it. Maybe we don't have a way to generate extended config space - * accesses. So check it + * Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have + * 4096 bytes configuration space for each function of their processor + * configuration space. */ -static void fam10h_pci_cfg_space_size(struct pci_dev *dev) +static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev) { dev->cfg_size = pci_cfg_space_size_ext(dev); } - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size); /* * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from diff --git a/arch/x86/pci/pci.h b/arch/x86/pci/pci.h index 15b9cf6be729..1959018aac02 100644 --- a/arch/x86/pci/pci.h +++ b/arch/x86/pci/pci.h @@ -96,6 +96,7 @@ extern struct pci_raw_ops *raw_pci_ops; extern struct pci_raw_ops *raw_pci_ext_ops; extern struct pci_raw_ops pci_direct_conf1; +extern bool port_cf9_safe; /* arch_initcall level */ extern int pci_direct_probe(void); diff --git a/arch/x86/power/hibernate_32.c b/arch/x86/power/hibernate_32.c index f2b6e3f11bfc..81197c62d5b3 100644 --- a/arch/x86/power/hibernate_32.c +++ b/arch/x86/power/hibernate_32.c @@ -12,6 +12,7 @@ #include #include #include +#include /* Defined in hibernate_asm_32.S */ extern int restore_image(void); @@ -127,6 +128,9 @@ static int resume_physical_mapping_init(pgd_t *pgd_base) } } } + + resume_map_numa_kva(pgd_base); + return 0; } diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile index 313947940a1a..6dcefba7836f 100644 --- a/arch/x86/xen/Makefile +++ b/arch/x86/xen/Makefile @@ -1,4 +1,4 @@ -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER # Do not profile debug and lowlevel utilities CFLAGS_REMOVE_spinlock.o = -pg CFLAGS_REMOVE_time.o = -pg diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index b61534c7a4c4..bea215230b20 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -793,7 +794,7 @@ static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) ret = 0; - switch(msr) { + switch (msr) { #ifdef CONFIG_X86_64 unsigned which; u64 base; @@ -863,15 +864,16 @@ static void xen_alloc_ptpage(struct mm_struct *mm, unsigned long pfn, unsigned l if (PagePinned(virt_to_page(mm->pgd))) { SetPagePinned(page); + vm_unmap_aliases(); if (!PageHighMem(page)) { make_lowmem_page_readonly(__va(PFN_PHYS((unsigned long)pfn))); if (level == PT_PTE && USE_SPLIT_PTLOCKS) pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn); - } else + } else { /* make sure there are no stray mappings of this page */ kmap_flush_unused(); - vm_unmap_aliases(); + } } } @@ -1452,7 +1454,7 @@ static __init void xen_map_identity_early(pmd_t *pmd, unsigned long max_pfn) ident_pte = 0; pfn = 0; - for(pmdidx = 0; pmdidx < PTRS_PER_PMD && pfn < max_pfn; pmdidx++) { + for (pmdidx = 0; pmdidx < PTRS_PER_PMD && pfn < max_pfn; pmdidx++) { pte_t *pte_page; /* Reuse or allocate a page of ptes */ @@ -1470,7 +1472,7 @@ static __init void xen_map_identity_early(pmd_t *pmd, unsigned long max_pfn) } /* Install mappings */ - for(pteidx = 0; pteidx < PTRS_PER_PTE; pteidx++, pfn++) { + for (pteidx = 0; pteidx < PTRS_PER_PTE; pteidx++, pfn++) { pte_t pte; if (pfn > max_pfn_mapped) @@ -1484,7 +1486,7 @@ static __init void xen_map_identity_early(pmd_t *pmd, unsigned long max_pfn) } } - for(pteidx = 0; pteidx < ident_pte; pteidx += PTRS_PER_PTE) + for (pteidx = 0; pteidx < ident_pte; pteidx += PTRS_PER_PTE) set_page_prot(&level1_ident_pgt[pteidx], PAGE_KERNEL_RO); set_page_prot(pmd, PAGE_KERNEL_RO); @@ -1498,7 +1500,7 @@ static void convert_pfn_mfn(void *v) /* All levels are converted the same way, so just treat them as ptes. */ - for(i = 0; i < PTRS_PER_PTE; i++) + for (i = 0; i < PTRS_PER_PTE; i++) pte[i] = xen_make_pte(pte[i].pte); } @@ -1513,7 +1515,8 @@ static void convert_pfn_mfn(void *v) * of the physical mapping once some sort of allocator has been set * up. */ -static __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn) +static __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, + unsigned long max_pfn) { pud_t *l3; pmd_t *l2; @@ -1576,7 +1579,8 @@ static __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pf #else /* !CONFIG_X86_64 */ static pmd_t level2_kernel_pgt[PTRS_PER_PMD] __page_aligned_bss; -static __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn) +static __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd, + unsigned long max_pfn) { pmd_t *kernel_pmd; diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index d4d52f5a1cf7..773d68d3e912 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -154,13 +154,13 @@ void xen_setup_mfn_list_list(void) { unsigned pfn, idx; - for(pfn = 0; pfn < MAX_DOMAIN_PAGES; pfn += P2M_ENTRIES_PER_PAGE) { + for (pfn = 0; pfn < MAX_DOMAIN_PAGES; pfn += P2M_ENTRIES_PER_PAGE) { unsigned topidx = p2m_top_index(pfn); p2m_top_mfn[topidx] = virt_to_mfn(p2m_top[topidx]); } - for(idx = 0; idx < ARRAY_SIZE(p2m_top_mfn_list); idx++) { + for (idx = 0; idx < ARRAY_SIZE(p2m_top_mfn_list); idx++) { unsigned topidx = idx * P2M_ENTRIES_PER_PAGE; p2m_top_mfn_list[idx] = virt_to_mfn(&p2m_top_mfn[topidx]); } @@ -179,7 +179,7 @@ void __init xen_build_dynamic_phys_to_machine(void) unsigned long max_pfn = min(MAX_DOMAIN_PAGES, xen_start_info->nr_pages); unsigned pfn; - for(pfn = 0; pfn < max_pfn; pfn += P2M_ENTRIES_PER_PAGE) { + for (pfn = 0; pfn < max_pfn; pfn += P2M_ENTRIES_PER_PAGE) { unsigned topidx = p2m_top_index(pfn); p2m_top[topidx] = &mfn_list[pfn]; @@ -207,7 +207,7 @@ static void alloc_p2m(unsigned long **pp, unsigned long *mfnp) p = (void *)__get_free_page(GFP_KERNEL | __GFP_NOFAIL); BUG_ON(p == NULL); - for(i = 0; i < P2M_ENTRIES_PER_PAGE; i++) + for (i = 0; i < P2M_ENTRIES_PER_PAGE; i++) p[i] = INVALID_P2M_ENTRY; if (cmpxchg(pp, p2m_missing, p) != p2m_missing) @@ -246,11 +246,21 @@ xmaddr_t arbitrary_virt_to_machine(void *vaddr) { unsigned long address = (unsigned long)vaddr; unsigned int level; - pte_t *pte = lookup_address(address, &level); - unsigned offset = address & ~PAGE_MASK; + pte_t *pte; + unsigned offset; - BUG_ON(pte == NULL); + /* + * if the PFN is in the linear mapped vaddr range, we can just use + * the (quick) virt_to_machine() p2m lookup + */ + if (virt_addr_valid(vaddr)) + return virt_to_machine(vaddr); + /* otherwise we have to do a (slower) full page-table walk */ + + pte = lookup_address(address, &level); + BUG_ON(pte == NULL); + offset = address & ~PAGE_MASK; return XMADDR(((phys_addr_t)pte_mfn(*pte) << PAGE_SHIFT) + offset); } @@ -397,7 +407,8 @@ out: preempt_enable(); } -pte_t xen_ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, pte_t *ptep) +pte_t xen_ptep_modify_prot_start(struct mm_struct *mm, + unsigned long addr, pte_t *ptep) { /* Just return the pte as-is. We preserve the bits on commit */ return *ptep; @@ -410,7 +421,7 @@ void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, xen_mc_batch(); - u.ptr = virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD; + u.ptr = arbitrary_virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD; u.val = pte_val_ma(pte); xen_extend_mmu_update(&u); @@ -651,12 +662,11 @@ void xen_set_pgd(pgd_t *ptr, pgd_t val) * For 64-bit, we must skip the Xen hole in the middle of the address * space, just after the big x86-64 virtual hole. */ -static int xen_pgd_walk(struct mm_struct *mm, - int (*func)(struct mm_struct *mm, struct page *, - enum pt_level), - unsigned long limit) +static int __xen_pgd_walk(struct mm_struct *mm, pgd_t *pgd, + int (*func)(struct mm_struct *mm, struct page *, + enum pt_level), + unsigned long limit) { - pgd_t *pgd = mm->pgd; int flush = 0; unsigned hole_low, hole_high; unsigned pgdidx_limit, pudidx_limit, pmdidx_limit; @@ -743,6 +753,14 @@ out: return flush; } +static int xen_pgd_walk(struct mm_struct *mm, + int (*func)(struct mm_struct *mm, struct page *, + enum pt_level), + unsigned long limit) +{ + return __xen_pgd_walk(mm, mm->pgd, func, limit); +} + /* If we're using split pte locks, then take the page's lock and return a pointer to it. Otherwise return NULL. */ static spinlock_t *xen_pte_lock(struct page *page, struct mm_struct *mm) @@ -840,13 +858,16 @@ static int xen_pin_page(struct mm_struct *mm, struct page *page, read-only, and can be pinned. */ static void __xen_pgd_pin(struct mm_struct *mm, pgd_t *pgd) { + vm_unmap_aliases(); + xen_mc_batch(); - if (xen_pgd_walk(mm, xen_pin_page, USER_LIMIT)) { - /* re-enable interrupts for kmap_flush_unused */ + if (__xen_pgd_walk(mm, pgd, xen_pin_page, USER_LIMIT)) { + /* re-enable interrupts for flushing */ xen_mc_issue(0); + kmap_flush_unused(); - vm_unmap_aliases(); + xen_mc_batch(); } @@ -858,13 +879,14 @@ static void __xen_pgd_pin(struct mm_struct *mm, pgd_t *pgd) if (user_pgd) { xen_pin_page(mm, virt_to_page(user_pgd), PT_PGD); - xen_do_pin(MMUEXT_PIN_L4_TABLE, PFN_DOWN(__pa(user_pgd))); + xen_do_pin(MMUEXT_PIN_L4_TABLE, + PFN_DOWN(__pa(user_pgd))); } } #else /* CONFIG_X86_32 */ #ifdef CONFIG_X86_PAE /* Need to make sure unshared kernel PMD is pinnable */ - xen_pin_page(mm, virt_to_page(pgd_page(pgd[pgd_index(TASK_SIZE)])), + xen_pin_page(mm, pgd_page(pgd[pgd_index(TASK_SIZE)]), PT_PMD); #endif xen_do_pin(MMUEXT_PIN_L3_TABLE, PFN_DOWN(__pa(pgd))); @@ -973,7 +995,8 @@ static void __xen_pgd_unpin(struct mm_struct *mm, pgd_t *pgd) pgd_t *user_pgd = xen_get_user_pgd(pgd); if (user_pgd) { - xen_do_pin(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(user_pgd))); + xen_do_pin(MMUEXT_UNPIN_TABLE, + PFN_DOWN(__pa(user_pgd))); xen_unpin_page(mm, virt_to_page(user_pgd), PT_PGD); } } @@ -981,11 +1004,11 @@ static void __xen_pgd_unpin(struct mm_struct *mm, pgd_t *pgd) #ifdef CONFIG_X86_PAE /* Need to make sure unshared kernel PMD is unpinned */ - xen_unpin_page(mm, virt_to_page(pgd_page(pgd[pgd_index(TASK_SIZE)])), + xen_unpin_page(mm, pgd_page(pgd[pgd_index(TASK_SIZE)]), PT_PMD); #endif - xen_pgd_walk(mm, xen_unpin_page, USER_LIMIT); + __xen_pgd_walk(mm, pgd, xen_unpin_page, USER_LIMIT); xen_mc_issue(0); } diff --git a/arch/x86/xen/multicalls.c b/arch/x86/xen/multicalls.c index 8ea8a0d0b0de..c738644b5435 100644 --- a/arch/x86/xen/multicalls.c +++ b/arch/x86/xen/multicalls.c @@ -154,7 +154,7 @@ void xen_mc_flush(void) ret, smp_processor_id()); dump_stack(); for (i = 0; i < b->mcidx; i++) { - printk(" call %2d/%d: op=%lu arg=[%lx] result=%ld\n", + printk(KERN_DEBUG " call %2d/%d: op=%lu arg=[%lx] result=%ld\n", i+1, b->mcidx, b->debug[i].op, b->debug[i].args[0], diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index d67901083888..15c6c68db6a2 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -28,6 +28,9 @@ /* These are code, but not functions. Defined in entry.S */ extern const char xen_hypervisor_callback[]; extern const char xen_failsafe_callback[]; +extern void xen_sysenter_target(void); +extern void xen_syscall_target(void); +extern void xen_syscall32_target(void); /** @@ -110,7 +113,6 @@ static __cpuinit int register_callback(unsigned type, const void *func) void __cpuinit xen_enable_sysenter(void) { - extern void xen_sysenter_target(void); int ret; unsigned sysenter_feature; @@ -132,8 +134,6 @@ void __cpuinit xen_enable_syscall(void) { #ifdef CONFIG_X86_64 int ret; - extern void xen_syscall_target(void); - extern void xen_syscall32_target(void); ret = register_callback(CALLBACKTYPE_syscall, xen_syscall_target); if (ret != 0) { @@ -160,7 +160,8 @@ void __init xen_arch_setup(void) HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_writable_pagetables); if (!xen_feature(XENFEAT_auto_translated_physmap)) - HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_pae_extended_cr3); + HYPERVISOR_vm_assist(VMASST_CMD_enable, + VMASST_TYPE_pae_extended_cr3); if (register_callback(CALLBACKTYPE_event, xen_hypervisor_callback) || register_callback(CALLBACKTYPE_failsafe, xen_failsafe_callback)) diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index d77da613b1d2..acd9b6705e02 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -362,7 +362,7 @@ static void xen_cpu_die(unsigned int cpu) alternatives_smp_switch(0); } -static void xen_play_dead(void) +static void __cpuinit xen_play_dead(void) /* used only with CPU_HOTPLUG */ { play_dead_common(); HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL); diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index d7422dc2a55c..9e1afae8461f 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -49,7 +49,7 @@ bool xen_vcpu_stolen(int vcpu); void xen_mark_init_mm_pinned(void); -void __init xen_setup_vcpu_info_placement(void); +void xen_setup_vcpu_info_placement(void); #ifdef CONFIG_SMP void xen_smp_init(void); diff --git a/block/blk-barrier.c b/block/blk-barrier.c index 5c99ff8d2db8..6e72d661ae42 100644 --- a/block/blk-barrier.c +++ b/block/blk-barrier.c @@ -161,7 +161,7 @@ static inline struct request *start_ordered(struct request_queue *q, /* * Prep proxy barrier request. */ - blkdev_dequeue_request(rq); + elv_dequeue_request(q, rq); q->orig_bar_rq = rq; rq = &q->bar_rq; blk_rq_init(q, rq); @@ -219,7 +219,7 @@ int blk_do_ordered(struct request_queue *q, struct request **rqp) * This can happen when the queue switches to * ORDERED_NONE while this request is on it. */ - blkdev_dequeue_request(rq); + elv_dequeue_request(q, rq); if (__blk_end_request(rq, -EOPNOTSUPP, blk_rq_bytes(rq))) BUG(); diff --git a/block/blk-core.c b/block/blk-core.c index c3df30cfb3fc..c36aa98fafa3 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -592,7 +592,7 @@ blk_init_queue_node(request_fn_proc *rfn, spinlock_t *lock, int node_id) 1 << QUEUE_FLAG_STACKABLE); q->queue_lock = lock; - blk_queue_segment_boundary(q, 0xffffffff); + blk_queue_segment_boundary(q, BLK_SEG_BOUNDARY_MASK); blk_queue_make_request(q, __make_request); blk_queue_max_segment_size(q, MAX_SEGMENT_SIZE); @@ -1636,6 +1636,28 @@ int blk_insert_cloned_request(struct request_queue *q, struct request *rq) } EXPORT_SYMBOL_GPL(blk_insert_cloned_request); +/** + * blkdev_dequeue_request - dequeue request and start timeout timer + * @req: request to dequeue + * + * Dequeue @req and start timeout timer on it. This hands off the + * request to the driver. + * + * Block internal functions which don't want to start timer should + * call elv_dequeue_request(). + */ +void blkdev_dequeue_request(struct request *req) +{ + elv_dequeue_request(req->q, req); + + /* + * We are now handing the request to the hardware, add the + * timeout handler. + */ + blk_add_timer(req); +} +EXPORT_SYMBOL(blkdev_dequeue_request); + /** * __end_that_request_first - end I/O on a request * @req: the request being processed @@ -1770,17 +1792,17 @@ static void end_that_request_last(struct request *req, int error) { struct gendisk *disk = req->rq_disk; - blk_delete_timer(req); - if (blk_rq_tagged(req)) blk_queue_end_tag(req->q, req); if (blk_queued_rq(req)) - blkdev_dequeue_request(req); + elv_dequeue_request(req->q, req); if (unlikely(laptop_mode) && blk_fs_request(req)) laptop_io_completion(); + blk_delete_timer(req); + /* * Account IO completion. bar_rq isn't accounted as a normal * IO on queueing nor completion. Accounting the containing diff --git a/block/blk-map.c b/block/blk-map.c index 4849fa36161e..2990447f45e9 100644 --- a/block/blk-map.c +++ b/block/blk-map.c @@ -217,8 +217,14 @@ int blk_rq_map_user_iov(struct request_queue *q, struct request *rq, return PTR_ERR(bio); if (bio->bi_size != len) { + /* + * Grab an extra reference to this bio, as bio_unmap_user() + * expects to be able to drop it twice as it happens on the + * normal IO completion path + */ + bio_get(bio); bio_endio(bio, 0); - bio_unmap_user(bio); + __blk_rq_unmap_user(bio); return -EINVAL; } diff --git a/block/blk-merge.c b/block/blk-merge.c index 8681cd6f9911..b92f5b0866b0 100644 --- a/block/blk-merge.c +++ b/block/blk-merge.c @@ -222,27 +222,6 @@ new_segment: } EXPORT_SYMBOL(blk_rq_map_sg); -static inline int ll_new_mergeable(struct request_queue *q, - struct request *req, - struct bio *bio) -{ - int nr_phys_segs = bio_phys_segments(q, bio); - - if (req->nr_phys_segments + nr_phys_segs > q->max_phys_segments) { - req->cmd_flags |= REQ_NOMERGE; - if (req == q->last_merge) - q->last_merge = NULL; - return 0; - } - - /* - * A hw segment is just getting larger, bump just the phys - * counter. - */ - req->nr_phys_segments += nr_phys_segs; - return 1; -} - static inline int ll_new_hw_segment(struct request_queue *q, struct request *req, struct bio *bio) diff --git a/block/blk-settings.c b/block/blk-settings.c index 41392fbe19ff..afa55e14e278 100644 --- a/block/blk-settings.c +++ b/block/blk-settings.c @@ -125,6 +125,9 @@ void blk_queue_make_request(struct request_queue *q, make_request_fn *mfn) q->nr_requests = BLKDEV_MAX_RQ; blk_queue_max_phys_segments(q, MAX_PHYS_SEGMENTS); blk_queue_max_hw_segments(q, MAX_HW_SEGMENTS); + blk_queue_segment_boundary(q, BLK_SEG_BOUNDARY_MASK); + blk_queue_max_segment_size(q, MAX_SEGMENT_SIZE); + q->make_request_fn = mfn; q->backing_dev_info.ra_pages = (VM_MAX_READAHEAD * 1024) / PAGE_CACHE_SIZE; @@ -314,6 +317,7 @@ void blk_queue_stack_limits(struct request_queue *t, struct request_queue *b) /* zero is "infinity" */ t->max_sectors = min_not_zero(t->max_sectors, b->max_sectors); t->max_hw_sectors = min_not_zero(t->max_hw_sectors, b->max_hw_sectors); + t->seg_boundary_mask = min_not_zero(t->seg_boundary_mask, b->seg_boundary_mask); t->max_phys_segments = min(t->max_phys_segments, b->max_phys_segments); t->max_hw_segments = min(t->max_hw_segments, b->max_hw_segments); diff --git a/block/blk-timeout.c b/block/blk-timeout.c index 972a63f848fb..69185ea9fae2 100644 --- a/block/blk-timeout.c +++ b/block/blk-timeout.c @@ -75,14 +75,7 @@ void blk_delete_timer(struct request *req) { struct request_queue *q = req->q; - /* - * Nothing to detach - */ - if (!q->rq_timed_out_fn || !req->deadline) - return; - list_del_init(&req->timeout_list); - if (list_empty(&q->timeout_list)) del_timer(&q->timeout); } @@ -142,7 +135,7 @@ void blk_rq_timed_out_timer(unsigned long data) } if (next_set && !list_empty(&q->timeout_list)) - mod_timer(&q->timeout, round_jiffies(next)); + mod_timer(&q->timeout, round_jiffies_up(next)); spin_unlock_irqrestore(q->queue_lock, flags); } @@ -198,17 +191,10 @@ void blk_add_timer(struct request *req) /* * If the timer isn't already pending or this timeout is earlier - * than an existing one, modify the timer. Round to next nearest + * than an existing one, modify the timer. Round up to next nearest * second. */ - expiry = round_jiffies(req->deadline); - - /* - * We use ->deadline == 0 to detect whether a timer was added or - * not, so just increase to next jiffy for that specific case - */ - if (unlikely(!req->deadline)) - req->deadline = 1; + expiry = round_jiffies_up(req->deadline); if (!timer_pending(&q->timeout) || time_before(expiry, q->timeout.expires)) diff --git a/block/bsg.c b/block/bsg.c index e8bd2475682a..e73e50daf3d0 100644 --- a/block/bsg.c +++ b/block/bsg.c @@ -202,6 +202,8 @@ static int blk_fill_sgv4_hdr_rq(struct request_queue *q, struct request *rq, rq->timeout = q->sg_timeout; if (!rq->timeout) rq->timeout = BLK_DEFAULT_SG_TIMEOUT; + if (rq->timeout < BLK_MIN_SG_TIMEOUT) + rq->timeout = BLK_MIN_SG_TIMEOUT; return 0; } diff --git a/block/compat_ioctl.c b/block/compat_ioctl.c index 3d3e7a46f38c..67eb93cff699 100644 --- a/block/compat_ioctl.c +++ b/block/compat_ioctl.c @@ -677,6 +677,29 @@ static int compat_blkdev_driver_ioctl(struct block_device *bdev, fmode_t mode, case DVD_WRITE_STRUCT: case DVD_AUTH: arg = (unsigned long)compat_ptr(arg); + /* These intepret arg as an unsigned long, not as a pointer, + * so we must not do compat_ptr() conversion. */ + case HDIO_SET_MULTCOUNT: + case HDIO_SET_UNMASKINTR: + case HDIO_SET_KEEPSETTINGS: + case HDIO_SET_32BIT: + case HDIO_SET_NOWERR: + case HDIO_SET_DMA: + case HDIO_SET_PIO_MODE: + case HDIO_SET_NICE: + case HDIO_SET_WCACHE: + case HDIO_SET_ACOUSTIC: + case HDIO_SET_BUSSTATE: + case HDIO_SET_ADDRESS: + case CDROMEJECT_SW: + case CDROM_SET_OPTIONS: + case CDROM_CLEAR_OPTIONS: + case CDROM_SELECT_SPEED: + case CDROM_SELECT_DISC: + case CDROM_MEDIA_CHANGED: + case CDROM_DRIVE_STATUS: + case CDROM_LOCKDOOR: + case CDROM_DEBUG: break; default: /* unknown ioctl number */ @@ -699,8 +722,14 @@ long compat_blkdev_ioctl(struct file *file, unsigned cmd, unsigned long arg) struct backing_dev_info *bdi; loff_t size; + /* + * O_NDELAY can be altered using fcntl(.., F_SETFL, ..), so we have + * to updated it before every ioctl. + */ if (file->f_flags & O_NDELAY) - mode |= FMODE_NDELAY_NOW; + mode |= FMODE_NDELAY; + else + mode &= ~FMODE_NDELAY; switch (cmd) { case HDIO_GETGEO: diff --git a/block/elevator.c b/block/elevator.c index 59173a69ebdf..a6951f76ba0c 100644 --- a/block/elevator.c +++ b/block/elevator.c @@ -773,12 +773,6 @@ struct request *elv_next_request(struct request_queue *q) */ rq->cmd_flags |= REQ_STARTED; blk_add_trace_rq(q, rq, BLK_TA_ISSUE); - - /* - * We are now handing the request to the hardware, - * add the timeout handler - */ - blk_add_timer(rq); } if (!q->boundary_rq || q->boundary_rq == rq) { @@ -851,7 +845,6 @@ void elv_dequeue_request(struct request_queue *q, struct request *rq) if (blk_account_rq(rq)) q->in_flight++; } -EXPORT_SYMBOL(elv_dequeue_request); int elv_queue_empty(struct request_queue *q) { diff --git a/block/genhd.c b/block/genhd.c index 4e5e7493f676..2f7feda61e35 100644 --- a/block/genhd.c +++ b/block/genhd.c @@ -768,6 +768,8 @@ static int __init genhd_device_init(void) bdev_map = kobj_map_init(base_probe, &block_class_lock); blk_dev_init(); + register_blkdev(BLOCK_EXT_MAJOR, "blkext"); + #ifndef CONFIG_SYSFS_DEPRECATED /* create top-level block dir */ block_depr = kobject_create_and_add("block", NULL); @@ -1100,6 +1102,7 @@ struct gendisk *alloc_disk_node(int minors, int node_id) kfree(disk); return NULL; } + disk->node_id = node_id; if (disk_expand_part_tbl(disk, 0)) { free_part_stats(&disk->part0); kfree(disk); @@ -1114,7 +1117,6 @@ struct gendisk *alloc_disk_node(int minors, int node_id) device_initialize(disk_to_dev(disk)); INIT_WORK(&disk->async_notify, media_change_notify_thread); - disk->node_id = node_id; } return disk; } diff --git a/block/ioctl.c b/block/ioctl.c index c832d639b6e2..d03985b04d67 100644 --- a/block/ioctl.c +++ b/block/ioctl.c @@ -18,7 +18,6 @@ static int blkpg_ioctl(struct block_device *bdev, struct blkpg_ioctl_arg __user struct disk_part_iter piter; long long start, length; int partno; - int err; if (!capable(CAP_SYS_ADMIN)) return -EACCES; @@ -61,10 +60,10 @@ static int blkpg_ioctl(struct block_device *bdev, struct blkpg_ioctl_arg __user disk_part_iter_exit(&piter); /* all seems OK */ - err = add_partition(disk, partno, start, length, - ADDPART_FLAG_NONE); + part = add_partition(disk, partno, start, length, + ADDPART_FLAG_NONE); mutex_unlock(&bdev->bd_mutex); - return err; + return IS_ERR(part) ? PTR_ERR(part) : 0; case BLKPG_DEL_PARTITION: part = disk_get_part(disk, partno); if (!part) diff --git a/block/scsi_ioctl.c b/block/scsi_ioctl.c index 5963cf91a3a0..d0bb92cbefb9 100644 --- a/block/scsi_ioctl.c +++ b/block/scsi_ioctl.c @@ -208,6 +208,8 @@ static int blk_fill_sghdr_rq(struct request_queue *q, struct request *rq, rq->timeout = q->sg_timeout; if (!rq->timeout) rq->timeout = BLK_DEFAULT_SG_TIMEOUT; + if (rq->timeout < BLK_MIN_SG_TIMEOUT) + rq->timeout = BLK_MIN_SG_TIMEOUT; return 0; } diff --git a/crypto/Kconfig b/crypto/Kconfig index 39dbd8e4dde1..dc20a34ba5ef 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -31,35 +31,63 @@ config CRYPTO_FIPS config CRYPTO_ALGAPI tristate + select CRYPTO_ALGAPI2 help This option provides the API for cryptographic algorithms. +config CRYPTO_ALGAPI2 + tristate + config CRYPTO_AEAD tristate + select CRYPTO_AEAD2 select CRYPTO_ALGAPI +config CRYPTO_AEAD2 + tristate + select CRYPTO_ALGAPI2 + config CRYPTO_BLKCIPHER tristate + select CRYPTO_BLKCIPHER2 select CRYPTO_ALGAPI - select CRYPTO_RNG + +config CRYPTO_BLKCIPHER2 + tristate + select CRYPTO_ALGAPI2 + select CRYPTO_RNG2 config CRYPTO_HASH tristate + select CRYPTO_HASH2 select CRYPTO_ALGAPI +config CRYPTO_HASH2 + tristate + select CRYPTO_ALGAPI2 + config CRYPTO_RNG tristate + select CRYPTO_RNG2 select CRYPTO_ALGAPI +config CRYPTO_RNG2 + tristate + select CRYPTO_ALGAPI2 + config CRYPTO_MANAGER tristate "Cryptographic algorithm manager" - select CRYPTO_AEAD - select CRYPTO_HASH - select CRYPTO_BLKCIPHER + select CRYPTO_MANAGER2 help Create default cryptographic template instantiations such as cbc(aes). +config CRYPTO_MANAGER2 + def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) + select CRYPTO_AEAD2 + select CRYPTO_HASH2 + select CRYPTO_BLKCIPHER2 + config CRYPTO_GF128MUL tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" depends on EXPERIMENTAL diff --git a/crypto/Makefile b/crypto/Makefile index 5862b807334e..cd4a4ed078ff 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -9,24 +9,24 @@ obj-$(CONFIG_CRYPTO_FIPS) += fips.o crypto_algapi-$(CONFIG_PROC_FS) += proc.o crypto_algapi-objs := algapi.o scatterwalk.o $(crypto_algapi-y) -obj-$(CONFIG_CRYPTO_ALGAPI) += crypto_algapi.o +obj-$(CONFIG_CRYPTO_ALGAPI2) += crypto_algapi.o -obj-$(CONFIG_CRYPTO_AEAD) += aead.o +obj-$(CONFIG_CRYPTO_AEAD2) += aead.o crypto_blkcipher-objs := ablkcipher.o crypto_blkcipher-objs += blkcipher.o -obj-$(CONFIG_CRYPTO_BLKCIPHER) += crypto_blkcipher.o -obj-$(CONFIG_CRYPTO_BLKCIPHER) += chainiv.o -obj-$(CONFIG_CRYPTO_BLKCIPHER) += eseqiv.o +obj-$(CONFIG_CRYPTO_BLKCIPHER2) += crypto_blkcipher.o +obj-$(CONFIG_CRYPTO_BLKCIPHER2) += chainiv.o +obj-$(CONFIG_CRYPTO_BLKCIPHER2) += eseqiv.o obj-$(CONFIG_CRYPTO_SEQIV) += seqiv.o crypto_hash-objs := hash.o crypto_hash-objs += ahash.o -obj-$(CONFIG_CRYPTO_HASH) += crypto_hash.o +obj-$(CONFIG_CRYPTO_HASH2) += crypto_hash.o cryptomgr-objs := algboss.o testmgr.o -obj-$(CONFIG_CRYPTO_MANAGER) += cryptomgr.o +obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o obj-$(CONFIG_CRYPTO_HMAC) += hmac.o obj-$(CONFIG_CRYPTO_XCBC) += xcbc.o obj-$(CONFIG_CRYPTO_NULL) += crypto_null.o @@ -73,8 +73,8 @@ obj-$(CONFIG_CRYPTO_MICHAEL_MIC) += michael_mic.o obj-$(CONFIG_CRYPTO_CRC32C) += crc32c.o obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o obj-$(CONFIG_CRYPTO_LZO) += lzo.o -obj-$(CONFIG_CRYPTO_RNG) += rng.o -obj-$(CONFIG_CRYPTO_RNG) += krng.o +obj-$(CONFIG_CRYPTO_RNG2) += rng.o +obj-$(CONFIG_CRYPTO_RNG2) += krng.o obj-$(CONFIG_CRYPTO_ANSI_CPRNG) += ansi_cprng.o obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index c029d3eb9ef0..595b78672b36 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -53,10 +53,17 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, int xor_src_cnt; dma_addr_t dma_dest; - dma_dest = dma_map_page(dma->dev, dest, offset, len, DMA_FROM_DEVICE); - for (i = 0; i < src_cnt; i++) + /* map the dest bidrectional in case it is re-used as a source */ + dma_dest = dma_map_page(dma->dev, dest, offset, len, DMA_BIDIRECTIONAL); + for (i = 0; i < src_cnt; i++) { + /* only map the dest once */ + if (unlikely(src_list[i] == dest)) { + dma_src[i] = dma_dest; + continue; + } dma_src[i] = dma_map_page(dma->dev, src_list[i], offset, len, DMA_TO_DEVICE); + } while (src_cnt) { async_flags = flags; diff --git a/drivers/Kconfig b/drivers/Kconfig index d38f43f593d4..2f557f570ade 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -68,6 +68,8 @@ source "drivers/ssb/Kconfig" source "drivers/mfd/Kconfig" +source "drivers/regulator/Kconfig" + source "drivers/media/Kconfig" source "drivers/video/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 2503f7b99b2f..fceb71a741c3 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MAC) += macintosh/ obj-$(CONFIG_ATA_OVER_ETH) += block/aoe/ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ +obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC) += usb/musb/ obj-$(CONFIG_PCI) += usb/ @@ -101,4 +102,3 @@ obj-$(CONFIG_SSB) += ssb/ obj-$(CONFIG_VIRTIO) += virtio/ obj-$(CONFIG_REGULATOR) += regulator/ obj-$(CONFIG_STAGING) += staging/ -obj-$(CONFIG_UWB) += uwb/ diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index f4f632917509..b0243fd55ac0 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -312,9 +312,13 @@ config ACPI_DEBUG bool "Debug Statements" default n help - The ACPI driver can optionally report errors with a great deal - of verbosity. Saying Y enables these statements. This will increase - your kernel size by around 50K. + The ACPI subsystem can produce debug output. Saying Y enables this + output and increases the kernel size by around 50K. + + Use the acpi.debug_layer and acpi.debug_level kernel command-line + parameters documented in Documentation/acpi/debug.txt and + Documentation/kernel-parameters.txt to control the type and + amount of debug output. config ACPI_DEBUG_FUNC_TRACE bool "Additionally enable ACPI function tracing" @@ -324,14 +328,6 @@ config ACPI_DEBUG_FUNC_TRACE ACPI Debug Statements slow down ACPI processing. Function trace is about half of the penalty and is rarely useful. -config ACPI_EC - bool - default y - help - This driver is required on some systems for the proper operation of - the battery and thermal drivers. If you are compiling for a - mobile system, say Y. - config ACPI_PCI_SLOT tristate "PCI slot detection driver" default n @@ -341,10 +337,6 @@ config ACPI_PCI_SLOT help you correlate PCI bus addresses with the physical geography of your slots. If you are unsure, say N. -config ACPI_POWER - bool - default y - config ACPI_SYSTEM bool default y diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index d91c027ece8f..3c0c93300f12 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -39,19 +39,23 @@ obj-y += sleep/ obj-y += bus.o glue.o obj-y += scan.o # Keep EC driver first. Initialization of others depend on it. -obj-$(CONFIG_ACPI_EC) += ec.o +obj-y += ec.o obj-$(CONFIG_ACPI_AC) += ac.o obj-$(CONFIG_ACPI_BATTERY) += battery.o obj-$(CONFIG_ACPI_BUTTON) += button.o obj-$(CONFIG_ACPI_FAN) += fan.o obj-$(CONFIG_ACPI_DOCK) += dock.o obj-$(CONFIG_ACPI_VIDEO) += video.o +ifdef CONFIG_ACPI_VIDEO +obj-y += video_detect.o +endif + obj-y += pci_root.o pci_link.o pci_irq.o pci_bind.o obj-$(CONFIG_ACPI_PCI_SLOT) += pci_slot.o obj-$(CONFIG_ACPI_PROCESSOR) += processor.o obj-$(CONFIG_ACPI_CONTAINER) += container.o obj-$(CONFIG_ACPI_THERMAL) += thermal.o -obj-$(CONFIG_ACPI_POWER) += power.o +obj-y += power.o obj-$(CONFIG_ACPI_SYSTEM) += system.o event.o obj-$(CONFIG_ACPI_DEBUG) += debug.o obj-$(CONFIG_ACPI_NUMA) += numa.o diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c index d72a1b6c8a94..9b917dac7732 100644 --- a/drivers/acpi/ac.c +++ b/drivers/acpi/ac.c @@ -37,7 +37,6 @@ #include #include -#define ACPI_AC_COMPONENT 0x00020000 #define ACPI_AC_CLASS "ac_adapter" #define ACPI_AC_DEVICE_NAME "AC Adapter" #define ACPI_AC_FILE_STATE "state" @@ -242,7 +241,7 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data) acpi_ac_get_state(ac); acpi_bus_generate_proc_event(device, event, (u32) ac->state); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, + dev_name(&device->dev), event, (u32) ac->state); #ifdef CONFIG_ACPI_SYSFS_POWER kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE); diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c index 71d21c51c45f..63a17b55b39b 100644 --- a/drivers/acpi/acpi_memhotplug.c +++ b/drivers/acpi/acpi_memhotplug.c @@ -32,7 +32,6 @@ #include #include -#define ACPI_MEMORY_DEVICE_COMPONENT 0x08000000UL #define ACPI_MEMORY_DEVICE_CLASS "memory" #define ACPI_MEMORY_DEVICE_HID "PNP0C80" #define ACPI_MEMORY_DEVICE_NAME "Hotplug Mem Device" diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index b2133e89ad9a..1423b0c0cd2e 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -46,7 +46,6 @@ #define ACPI_BATTERY_VALUE_UNKNOWN 0xFFFFFFFF -#define ACPI_BATTERY_COMPONENT 0x00040000 #define ACPI_BATTERY_CLASS "battery" #define ACPI_BATTERY_DEVICE_NAME "Battery" #define ACPI_BATTERY_NOTIFY_STATUS 0x80 @@ -782,7 +781,7 @@ static void acpi_battery_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_proc_event(device, event, acpi_battery_present(battery)); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, + dev_name(&device->dev), event, acpi_battery_present(battery)); #ifdef CONFIG_ACPI_SYSFS_POWER /* acpi_batter_update could remove power_supply object */ diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/blacklist.c index ea92bac42c53..09c69806c1fc 100644 --- a/drivers/acpi/blacklist.c +++ b/drivers/acpi/blacklist.c @@ -176,16 +176,6 @@ static int __init dmi_enable_osi_linux(const struct dmi_system_id *d) acpi_dmi_osi_linux(1, d); /* enable */ return 0; } -static int __init dmi_disable_osi_linux(const struct dmi_system_id *d) -{ - acpi_dmi_osi_linux(0, d); /* disable */ - return 0; -} -static int __init dmi_unknown_osi_linux(const struct dmi_system_id *d) -{ - acpi_dmi_osi_linux(-1, d); /* unknown */ - return 0; -} static int __init dmi_disable_osi_vista(const struct dmi_system_id *d) { printk(KERN_NOTICE PREFIX "DMI detected: %s\n", d->ident); @@ -193,295 +183,21 @@ static int __init dmi_disable_osi_vista(const struct dmi_system_id *d) return 0; } -/* - * Most BIOS that invoke OSI(Linux) do nothing with it. - * But some cause Linux to break. - * Only a couple use it to make Linux run better. - * - * Thus, Linux should continue to disable OSI(Linux) by default, - * should continue to discourage BIOS writers from using it, and - * should whitelist the few existing systems that require it. - * - * If it appears clear a vendor isn't using OSI(Linux) - * for anything constructive, blacklist them by name to disable - * unnecessary dmesg warnings on all of their products. - */ - static struct dmi_system_id acpi_osi_dmi_table[] __initdata = { - /* - * Disable OSI(Linux) warnings on all "Acer, inc." - * - * _OSI(Linux) disables the latest Windows BIOS code: - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3100"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5050"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5100"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5580"), - * DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 3010"), - * _OSI(Linux) effect unknown: - * DMI_MATCH(DMI_PRODUCT_NAME, "Ferrari 5000"), - */ - /* - * note that dmi_check_system() uses strstr() - * to match sub-strings rather than !strcmp(), - * so "Acer" below matches "Acer, inc." above. - */ - /* - * Disable OSI(Linux) warnings on all "Acer" - * - * _OSI(Linux) effect unknown: - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5610"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 7720Z"), - * DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 5520"), - * DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 6460"), - * DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 7510"), - * - * _OSI(Linux) is a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5315"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Extensa 5220"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Acer", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Acer"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "Apple Computer, Inc." - * Disable OSI(Linux) warnings on all "Apple Inc." - * - * _OSI(Linux) confirmed to be a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "MacBook1,1"), - * DMI_MATCH(DMI_PRODUCT_NAME, "MacBook2,1"), - * DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro2,2"), - * DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro3,1"), - * _OSI(Linux) effect unknown: - * DMI_MATCH(DMI_PRODUCT_NAME, "MacPro2,1"), - * DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro1,1"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Apple", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Apple"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "BenQ" - * - * _OSI(Linux) confirmed to be a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "Joybook S31"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "BenQ", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "BenQ"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "Clevo Co." - * - * _OSI(Linux) confirmed to be a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "M570RU"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Clevo", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), - }, - }, - /* - * Disable OSI(Linux) warnings on all "COMPAL" - * - * _OSI(Linux) confirmed to be a NOP: - * DMI_MATCH(DMI_BOARD_NAME, "HEL8X"), - * _OSI(Linux) unknown effect: - * DMI_MATCH(DMI_BOARD_NAME, "IFL91"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Compal", - .matches = { - DMI_MATCH(DMI_BIOS_VENDOR, "COMPAL"), - }, - }, - { /* OSI(Linux) touches USB, unknown side-effect */ - .callback = dmi_disable_osi_linux, - .ident = "Dell Dimension 5150", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Dell DM051"), - }, - }, - { /* OSI(Linux) is a NOP */ - .callback = dmi_disable_osi_linux, - .ident = "Dell i1501", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1501"), - }, - }, - { /* OSI(Linux) effect unknown */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell Latitude D830", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Latitude D830"), - }, - }, - { /* OSI(Linux) effect unknown */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell OptiPlex GX620", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex GX620"), - }, - }, - { /* OSI(Linux) causes some USB initialization to not run */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell OptiPlex 755", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 755"), - }, - }, - { /* OSI(Linux) effect unknown */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell PE 1900", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1900"), - }, - }, - { /* OSI(Linux) is a NOP */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell PE 1950", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"), - }, - }, - { /* OSI(Linux) is a NOP */ - .callback = dmi_disable_osi_linux, - .ident = "Dell PE R200", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R200"), - }, - }, - { /* OSI(Linux) touches USB */ - .callback = dmi_disable_osi_linux, - .ident = "Dell PR 390", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Precision WorkStation 390"), - }, - }, - { /* OSI(Linux) touches USB */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell PR 390", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Precision WorkStation 690"), - }, - }, - { /* OSI(Linux) unknown - ASL looks benign, but may effect dock/SMM */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell PR M4300", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Precision M4300"), - }, - }, - { /* OSI(Linux) is a NOP */ - .callback = dmi_disable_osi_linux, - .ident = "Dell Vostro 1000", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 1000"), - }, - }, - { /* OSI(Linux) effect unknown */ - .callback = dmi_unknown_osi_linux, - .ident = "Dell PE SC440", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge SC440"), - }, - }, - { /* OSI(Linux) effect unknown */ - .callback = dmi_unknown_osi_linux, - .ident = "Dialogue Flybook V5", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dialogue Technology Corporation"), - DMI_MATCH(DMI_PRODUCT_NAME, "Flybook V5"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "FUJITSU SIEMENS" - * - * _OSI(Linux) disables latest Windows BIOS code: - * DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Pa 2510"), - * _OSI(Linux) confirmed to be a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Pi 1536"), - * DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Pi 1556"), - * DMI_MATCH(DMI_PRODUCT_NAME, "AMILO Xi 1546"), - * DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Mobile V5505"), - * _OSI(Linux) unknown effect: - * DMI_MATCH(DMI_PRODUCT_NAME, "Amilo M1425"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Amilo Si 1520"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Fujitsu Siemens", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), - }, - }, { .callback = dmi_disable_osi_vista, .ident = "Fujitsu Siemens", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), - DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Mobile V5505"), + DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Mobile V5505"), }, }, + /* - * Disable OSI(Linux) warnings on all "Hewlett-Packard" - * - * _OSI(Linux) confirmed to be a NOP: - * .ident = "HP Pavilion tx 1000" - * DMI_MATCH(DMI_BOARD_NAME, "30BF"), - * .ident = "HP Pavilion dv2000" - * DMI_MATCH(DMI_BOARD_NAME, "30B5"), - * .ident = "HP Pavilion dv5000", - * DMI_MATCH(DMI_BOARD_NAME, "30A7"), - * .ident = "HP Pavilion dv6300 30BC", - * DMI_MATCH(DMI_BOARD_NAME, "30BC"), - * .ident = "HP Pavilion dv6000", - * DMI_MATCH(DMI_BOARD_NAME, "30B7"), - * DMI_MATCH(DMI_BOARD_NAME, "30B8"), - * .ident = "HP Pavilion dv9000", - * DMI_MATCH(DMI_BOARD_NAME, "30B9"), - * .ident = "HP Pavilion dv9500", - * DMI_MATCH(DMI_BOARD_NAME, "30CB"), - * .ident = "HP/Compaq Presario C500", - * DMI_MATCH(DMI_BOARD_NAME, "30C6"), - * .ident = "HP/Compaq Presario F500", - * DMI_MATCH(DMI_BOARD_NAME, "30D3"), - * _OSI(Linux) unknown effect: - * .ident = "HP Pavilion dv6500", - * DMI_MATCH(DMI_BOARD_NAME, "30D0"), + * BIOS invocation of _OSI(Linux) is almost always a BIOS bug. + * Linux ignores it, except for the machines enumerated below. */ - { - .callback = dmi_disable_osi_linux, - .ident = "Hewlett-Packard", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), - }, - }, + /* * Lenovo has a mix of systems OSI(Linux) situations * and thus we can not wildcard the vendor. @@ -519,113 +235,6 @@ static struct dmi_system_id acpi_osi_dmi_table[] __initdata = { DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X61"), }, }, - { - .callback = dmi_disable_osi_linux, - .ident = "Lenovo 3000 V100", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_MATCH(DMI_PRODUCT_VERSION, "LENOVO3000 V100"), - }, - }, - { - .callback = dmi_disable_osi_linux, - .ident = "Lenovo 3000 N100", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_MATCH(DMI_PRODUCT_VERSION, "3000 N100"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "LG Electronics" - * - * _OSI(Linux) confirmed to be a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "P1-J150B"), - * with DMI_MATCH(DMI_BOARD_NAME, "ROCKY"), - * - * unknown: - * DMI_MATCH(DMI_PRODUCT_NAME, "S1-MDGDG"), - * with DMI_MATCH(DMI_BOARD_NAME, "ROCKY"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "LG", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "LG Electronics"), - }, - }, - /* NEC - OSI(Linux) effect unknown */ - { - .callback = dmi_unknown_osi_linux, - .ident = "NEC VERSA M360", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "NEC Computers SAS"), - DMI_MATCH(DMI_PRODUCT_NAME, "NEC VERSA M360"), - }, - }, - /* Panasonic */ - { - .callback = dmi_unknown_osi_linux, - .ident = "Panasonic", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Matsushita"), - /* Toughbook CF-52 */ - DMI_MATCH(DMI_PRODUCT_NAME, "CF-52CCABVBG"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "Samsung Electronics" - * - * OSI(Linux) disables PNP0C32 and other BIOS code for Windows: - * DMI_MATCH(DMI_PRODUCT_NAME, "R40P/R41P"), - * DMI_MATCH(DMI_PRODUCT_NAME, "R59P/R60P/R61P"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Samsung", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."), - }, - }, - /* - * Disable OSI(Linux) warnings on all "Sony Corporation" - * - * _OSI(Linux) is a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "VGN-NR11S_S"), - * DMI_MATCH(DMI_PRODUCT_NAME, "VGN-SZ38GP_C"), - * DMI_MATCH(DMI_PRODUCT_NAME, "VGN-SZ650N"), - * DMI_MATCH(DMI_PRODUCT_NAME, "VGN-TZ21MN_N"), - * _OSI(Linux) unknown effect: - * DMI_MATCH(DMI_PRODUCT_NAME, "VGN-FZ11M"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Sony", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), - }, - }, - /* - * Disable OSI(Linux) warnings on all "TOSHIBA" - * - * _OSI(Linux) breaks sound (bugzilla 7787): - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite P100"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite P105"), - * _OSI(Linux) is a NOP: - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite A100"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite A210"), - * _OSI(Linux) unknown effect: - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite A135"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite A200"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite P205"), - * DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U305"), - */ - { - .callback = dmi_disable_osi_linux, - .ident = "Toshiba", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), - }, - }, {} }; diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index c797c6473f31..7edf6d913c13 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -688,6 +688,14 @@ void __init acpi_early_init(void) if (acpi_disabled) return; + /* + * ACPI CA initializes acpi_dbg_level to non-zero, which means + * we get debug output merely by turning on CONFIG_ACPI_DEBUG. + * Turn it off so we don't get output unless the user specifies + * acpi.debug_level. + */ + acpi_dbg_level = 0; + printk(KERN_INFO PREFIX "Core revision %08x\n", ACPI_CA_VERSION); /* enable workarounds, unless strict ACPI spec. compliance */ @@ -774,7 +782,7 @@ static int __init acpi_bus_init(void) "Unable to initialize ACPI OS objects\n"); goto error1; } -#ifdef CONFIG_ACPI_EC + /* * ACPI 2.0 requires the EC driver to be loaded and work before * the EC device is found in the namespace (i.e. before acpi_initialize_objects() @@ -785,7 +793,6 @@ static int __init acpi_bus_init(void) */ status = acpi_ec_ecdt_probe(); /* Ignore result. Not having an ECDT is not fatal. */ -#endif status = acpi_initialize_objects(ACPI_FULL_INITIALIZATION); if (ACPI_FAILURE(status)) { diff --git a/drivers/acpi/button.c b/drivers/acpi/button.c index 9d568d417eaa..171fd914f435 100644 --- a/drivers/acpi/button.c +++ b/drivers/acpi/button.c @@ -33,7 +33,6 @@ #include #include -#define ACPI_BUTTON_COMPONENT 0x00080000 #define ACPI_BUTTON_CLASS "button" #define ACPI_BUTTON_FILE_INFO "info" #define ACPI_BUTTON_FILE_STATE "state" @@ -262,6 +261,7 @@ static int acpi_lid_send_state(struct acpi_button *button) return -ENODEV; /* input layer checks if event is redundant */ input_report_switch(button->input, SW_LID, !state); + input_sync(button->input); return 0; } @@ -285,8 +285,8 @@ static void acpi_button_notify(acpi_handle handle, u32 event, void *data) input_report_key(input, keycode, 1); input_sync(input); input_report_key(input, keycode, 0); + input_sync(input); } - input_sync(input); acpi_bus_generate_proc_event(button->device, event, ++button->pushed); @@ -478,7 +478,7 @@ static int acpi_button_add(struct acpi_device *device) device->wakeup.gpe_number, ACPI_GPE_TYPE_WAKE_RUN); acpi_enable_gpe(device->wakeup.gpe_device, - device->wakeup.gpe_number, ACPI_NOT_ISR); + device->wakeup.gpe_number); device->wakeup.state.enabled = 1; } diff --git a/drivers/acpi/cm_sbs.c b/drivers/acpi/cm_sbs.c index 4441e84b28a9..307963bd1043 100644 --- a/drivers/acpi/cm_sbs.c +++ b/drivers/acpi/cm_sbs.c @@ -34,7 +34,6 @@ ACPI_MODULE_NAME("cm_sbs"); #define ACPI_AC_CLASS "ac_adapter" #define ACPI_BATTERY_CLASS "battery" -#define ACPI_SBS_COMPONENT 0x00080000 #define _COMPONENT ACPI_SBS_COMPONENT static struct proc_dir_entry *acpi_ac_dir; static struct proc_dir_entry *acpi_battery_dir; @@ -105,9 +104,3 @@ void acpi_unlock_battery_dir(struct proc_dir_entry *acpi_battery_dir_param) return; } EXPORT_SYMBOL(acpi_unlock_battery_dir); - -static int __init acpi_cm_sbs_init(void) -{ - return 0; -} -subsys_initcall(acpi_cm_sbs_init); diff --git a/drivers/acpi/container.c b/drivers/acpi/container.c index 134818b265a9..17020c12623c 100644 --- a/drivers/acpi/container.c +++ b/drivers/acpi/container.c @@ -41,7 +41,6 @@ #define INSTALL_NOTIFY_HANDLER 1 #define UNINSTALL_NOTIFY_HANDLER 2 -#define ACPI_CONTAINER_COMPONENT 0x01000000 #define _COMPONENT ACPI_CONTAINER_COMPONENT ACPI_MODULE_NAME("container"); diff --git a/drivers/acpi/debug.c b/drivers/acpi/debug.c index abf36b4b1d1d..c48396892008 100644 --- a/drivers/acpi/debug.c +++ b/drivers/acpi/debug.c @@ -44,6 +44,21 @@ static const struct acpi_dlayer acpi_debug_layers[] = { ACPI_DEBUG_INIT(ACPI_CA_DISASSEMBLER), ACPI_DEBUG_INIT(ACPI_COMPILER), ACPI_DEBUG_INIT(ACPI_TOOLS), + + ACPI_DEBUG_INIT(ACPI_BUS_COMPONENT), + ACPI_DEBUG_INIT(ACPI_AC_COMPONENT), + ACPI_DEBUG_INIT(ACPI_BATTERY_COMPONENT), + ACPI_DEBUG_INIT(ACPI_BUTTON_COMPONENT), + ACPI_DEBUG_INIT(ACPI_SBS_COMPONENT), + ACPI_DEBUG_INIT(ACPI_FAN_COMPONENT), + ACPI_DEBUG_INIT(ACPI_PCI_COMPONENT), + ACPI_DEBUG_INIT(ACPI_POWER_COMPONENT), + ACPI_DEBUG_INIT(ACPI_CONTAINER_COMPONENT), + ACPI_DEBUG_INIT(ACPI_SYSTEM_COMPONENT), + ACPI_DEBUG_INIT(ACPI_THERMAL_COMPONENT), + ACPI_DEBUG_INIT(ACPI_MEMORY_DEVICE_COMPONENT), + ACPI_DEBUG_INIT(ACPI_VIDEO_COMPONENT), + ACPI_DEBUG_INIT(ACPI_PROCESSOR_COMPONENT), }; static const struct acpi_dlevel acpi_debug_levels[] = { diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index ef42316f89f5..30f3ef236ecb 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -70,7 +70,7 @@ enum ec_command { #define ACPI_EC_UDELAY_GLK 1000 /* Wait 1ms max. to get global lock */ #define ACPI_EC_UDELAY 100 /* Wait 100us before polling EC again */ -#define ACPI_EC_STORM_THRESHOLD 20 /* number of false interrupts +#define ACPI_EC_STORM_THRESHOLD 8 /* number of false interrupts per one transaction */ enum { @@ -100,8 +100,11 @@ struct transaction { u8 *rdata; unsigned short irq_count; u8 command; + u8 wi; + u8 ri; u8 wlen; u8 rlen; + bool done; }; static struct acpi_ec { @@ -178,34 +181,46 @@ static int ec_transaction_done(struct acpi_ec *ec) unsigned long flags; int ret = 0; spin_lock_irqsave(&ec->curr_lock, flags); - if (!ec->curr || (!ec->curr->wlen && !ec->curr->rlen)) + if (!ec->curr || ec->curr->done) ret = 1; spin_unlock_irqrestore(&ec->curr_lock, flags); return ret; } +static void start_transaction(struct acpi_ec *ec) +{ + ec->curr->irq_count = ec->curr->wi = ec->curr->ri = 0; + ec->curr->done = false; + acpi_ec_write_cmd(ec, ec->curr->command); +} + static void gpe_transaction(struct acpi_ec *ec, u8 status) { unsigned long flags; spin_lock_irqsave(&ec->curr_lock, flags); if (!ec->curr) goto unlock; - if (ec->curr->wlen > 0) { - if ((status & ACPI_EC_FLAG_IBF) == 0) { - acpi_ec_write_data(ec, *(ec->curr->wdata++)); - --ec->curr->wlen; - } else - /* false interrupt, state didn't change */ - ++ec->curr->irq_count; - - } else if (ec->curr->rlen > 0) { + if (ec->curr->wlen > ec->curr->wi) { + if ((status & ACPI_EC_FLAG_IBF) == 0) + acpi_ec_write_data(ec, + ec->curr->wdata[ec->curr->wi++]); + else + goto err; + } else if (ec->curr->rlen > ec->curr->ri) { if ((status & ACPI_EC_FLAG_OBF) == 1) { - *(ec->curr->rdata++) = acpi_ec_read_data(ec); - --ec->curr->rlen; + ec->curr->rdata[ec->curr->ri++] = acpi_ec_read_data(ec); + if (ec->curr->rlen == ec->curr->ri) + ec->curr->done = true; } else - /* false interrupt, state didn't change */ - ++ec->curr->irq_count; - } + goto err; + } else if (ec->curr->wlen == ec->curr->wi && + (status & ACPI_EC_FLAG_IBF) == 0) + ec->curr->done = true; + goto unlock; +err: + /* false interrupt, state didn't change */ + if (in_interrupt()) + ++ec->curr->irq_count; unlock: spin_unlock_irqrestore(&ec->curr_lock, flags); } @@ -215,6 +230,15 @@ static int acpi_ec_wait(struct acpi_ec *ec) if (wait_event_timeout(ec->wait, ec_transaction_done(ec), msecs_to_jiffies(ACPI_EC_DELAY))) return 0; + /* try restart command if we get any false interrupts */ + if (ec->curr->irq_count && + (acpi_ec_read_status(ec) & ACPI_EC_FLAG_IBF) == 0) { + pr_debug(PREFIX "controller reset, restart transaction\n"); + start_transaction(ec); + if (wait_event_timeout(ec->wait, ec_transaction_done(ec), + msecs_to_jiffies(ACPI_EC_DELAY))) + return 0; + } /* missing GPEs, switch back to poll mode */ if (printk_ratelimit()) pr_info(PREFIX "missing confirmations, " @@ -239,10 +263,10 @@ static int ec_check_sci(struct acpi_ec *ec, u8 state) static int ec_poll(struct acpi_ec *ec) { unsigned long delay = jiffies + msecs_to_jiffies(ACPI_EC_DELAY); - msleep(1); + udelay(ACPI_EC_UDELAY); while (time_before(jiffies, delay)) { gpe_transaction(ec, acpi_ec_read_status(ec)); - msleep(1); + udelay(ACPI_EC_UDELAY); if (ec_transaction_done(ec)) return 0; } @@ -259,14 +283,13 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec, /* disable GPE during transaction if storm is detected */ if (test_bit(EC_FLAGS_GPE_STORM, &ec->flags)) { clear_bit(EC_FLAGS_GPE_MODE, &ec->flags); - acpi_disable_gpe(NULL, ec->gpe, ACPI_NOT_ISR); + acpi_disable_gpe(NULL, ec->gpe); } /* start transaction */ spin_lock_irqsave(&ec->curr_lock, tmp); /* following two actions should be kept atomic */ - t->irq_count = 0; ec->curr = t; - acpi_ec_write_cmd(ec, ec->curr->command); + start_transaction(ec); if (ec->curr->command == ACPI_EC_COMMAND_QUERY) clear_bit(EC_FLAGS_QUERY_PENDING, &ec->flags); spin_unlock_irqrestore(&ec->curr_lock, tmp); @@ -283,10 +306,11 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec, /* check if we received SCI during transaction */ ec_check_sci(ec, acpi_ec_read_status(ec)); /* it is safe to enable GPE outside of transaction */ - acpi_enable_gpe(NULL, ec->gpe, ACPI_NOT_ISR); + acpi_enable_gpe(NULL, ec->gpe); } else if (test_bit(EC_FLAGS_GPE_MODE, &ec->flags) && t->irq_count > ACPI_EC_STORM_THRESHOLD) { - pr_debug(PREFIX "GPE storm detected\n"); + pr_info(PREFIX "GPE storm detected, " + "transactions will use polling mode\n"); set_bit(EC_FLAGS_GPE_STORM, &ec->flags); } return ret; @@ -558,17 +582,26 @@ static u32 acpi_ec_gpe_handler(void *data) pr_debug(PREFIX "~~~> interrupt\n"); status = acpi_ec_read_status(ec); - gpe_transaction(ec, status); - if (ec_transaction_done(ec) && (status & ACPI_EC_FLAG_IBF) == 0) - wake_up(&ec->wait); + if (test_bit(EC_FLAGS_GPE_MODE, &ec->flags)) { + gpe_transaction(ec, status); + if (ec_transaction_done(ec) && + (status & ACPI_EC_FLAG_IBF) == 0) + wake_up(&ec->wait); + } ec_check_sci(ec, status); if (!test_bit(EC_FLAGS_GPE_MODE, &ec->flags) && !test_bit(EC_FLAGS_NO_GPE, &ec->flags)) { /* this is non-query, must be confirmation */ - if (printk_ratelimit()) - pr_info(PREFIX "non-query interrupt received," + if (!test_bit(EC_FLAGS_GPE_STORM, &ec->flags)) { + if (printk_ratelimit()) + pr_info(PREFIX "non-query interrupt received," + " switching to interrupt mode\n"); + } else { + /* hush, STORM switches the mode every transaction */ + pr_debug(PREFIX "non-query interrupt received," " switching to interrupt mode\n"); + } set_bit(EC_FLAGS_GPE_MODE, &ec->flags); } return ACPI_INTERRUPT_HANDLED; @@ -736,7 +769,7 @@ static acpi_status ec_parse_device(acpi_handle handle, u32 Level, void *context, void **retval) { acpi_status status; - unsigned long long tmp; + unsigned long long tmp = 0; struct acpi_ec *ec = context; status = acpi_walk_resources(handle, METHOD_NAME__CRS, @@ -751,6 +784,7 @@ ec_parse_device(acpi_handle handle, u32 Level, void *context, void **retval) return status; ec->gpe = tmp; /* Use the global lock for all EC transactions? */ + tmp = 0; acpi_evaluate_integer(handle, "_GLK", NULL, &tmp); ec->global_lock = tmp; ec->handle = handle; @@ -868,7 +902,7 @@ static int ec_install_handlers(struct acpi_ec *ec) if (ACPI_FAILURE(status)) return -ENODEV; acpi_set_gpe_type(NULL, ec->gpe, ACPI_GPE_TYPE_RUNTIME); - acpi_enable_gpe(NULL, ec->gpe, ACPI_NOT_ISR); + acpi_enable_gpe(NULL, ec->gpe); status = acpi_install_address_space_handler(ec->handle, ACPI_ADR_SPACE_EC, &acpi_ec_space_handler, @@ -1007,7 +1041,7 @@ static int acpi_ec_suspend(struct acpi_device *device, pm_message_t state) /* Stop using GPE */ set_bit(EC_FLAGS_NO_GPE, &ec->flags); clear_bit(EC_FLAGS_GPE_MODE, &ec->flags); - acpi_disable_gpe(NULL, ec->gpe, ACPI_NOT_ISR); + acpi_disable_gpe(NULL, ec->gpe); return 0; } @@ -1016,7 +1050,7 @@ static int acpi_ec_resume(struct acpi_device *device) struct acpi_ec *ec = acpi_driver_data(device); /* Enable use of GPE back */ clear_bit(EC_FLAGS_NO_GPE, &ec->flags); - acpi_enable_gpe(NULL, ec->gpe, ACPI_NOT_ISR); + acpi_enable_gpe(NULL, ec->gpe); return 0; } diff --git a/drivers/acpi/events/evgpe.c b/drivers/acpi/events/evgpe.c index c5e53aae86f7..f45c74fe745e 100644 --- a/drivers/acpi/events/evgpe.c +++ b/drivers/acpi/events/evgpe.c @@ -289,8 +289,6 @@ acpi_status acpi_ev_disable_gpe(struct acpi_gpe_event_info *gpe_event_info) */ status = acpi_hw_low_disable_gpe(gpe_event_info); return_ACPI_STATUS(status); - - return_ACPI_STATUS(AE_OK); } /******************************************************************************* diff --git a/drivers/acpi/events/evxfevnt.c b/drivers/acpi/events/evxfevnt.c index 73bfd6bf962f..41554f736b68 100644 --- a/drivers/acpi/events/evxfevnt.c +++ b/drivers/acpi/events/evxfevnt.c @@ -248,21 +248,15 @@ ACPI_EXPORT_SYMBOL(acpi_set_gpe_type) * DESCRIPTION: Enable an ACPI event (general purpose) * ******************************************************************************/ -acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags) +acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number) { acpi_status status = AE_OK; + acpi_cpu_flags flags; struct acpi_gpe_event_info *gpe_event_info; ACPI_FUNCTION_TRACE(acpi_enable_gpe); - /* Use semaphore lock if not executing at interrupt level */ - - if (flags & ACPI_NOT_ISR) { - status = acpi_ut_acquire_mutex(ACPI_MTX_EVENTS); - if (ACPI_FAILURE(status)) { - return_ACPI_STATUS(status); - } - } + flags = acpi_os_acquire_lock(acpi_gbl_gpe_lock); /* Ensure that we have a valid GPE number */ @@ -277,9 +271,7 @@ acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags) status = acpi_ev_enable_gpe(gpe_event_info, TRUE); unlock_and_exit: - if (flags & ACPI_NOT_ISR) { - (void)acpi_ut_release_mutex(ACPI_MTX_EVENTS); - } + acpi_os_release_lock(acpi_gbl_gpe_lock, flags); return_ACPI_STATUS(status); } @@ -299,22 +291,15 @@ ACPI_EXPORT_SYMBOL(acpi_enable_gpe) * DESCRIPTION: Disable an ACPI event (general purpose) * ******************************************************************************/ -acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags) +acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number) { acpi_status status = AE_OK; + acpi_cpu_flags flags; struct acpi_gpe_event_info *gpe_event_info; ACPI_FUNCTION_TRACE(acpi_disable_gpe); - /* Use semaphore lock if not executing at interrupt level */ - - if (flags & ACPI_NOT_ISR) { - status = acpi_ut_acquire_mutex(ACPI_MTX_EVENTS); - if (ACPI_FAILURE(status)) { - return_ACPI_STATUS(status); - } - } - + flags = acpi_os_acquire_lock(acpi_gbl_gpe_lock); /* Ensure that we have a valid GPE number */ gpe_event_info = acpi_ev_get_gpe_event_info(gpe_device, gpe_number); @@ -325,10 +310,8 @@ acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags) status = acpi_ev_disable_gpe(gpe_event_info); - unlock_and_exit: - if (flags & ACPI_NOT_ISR) { - (void)acpi_ut_release_mutex(ACPI_MTX_EVENTS); - } +unlock_and_exit: + acpi_os_release_lock(acpi_gbl_gpe_lock, flags); return_ACPI_STATUS(status); } @@ -521,6 +504,9 @@ acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status) if (value) *event_status |= ACPI_EVENT_FLAG_SET; + if (acpi_gbl_fixed_event_handlers[event].handler) + *event_status |= ACPI_EVENT_FLAG_HANDLE; + return_ACPI_STATUS(status); } @@ -571,6 +557,9 @@ acpi_get_gpe_status(acpi_handle gpe_device, status = acpi_hw_get_gpe_status(gpe_event_info, event_status); + if (gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK) + *event_status |= ACPI_EVENT_FLAG_HANDLE; + unlock_and_exit: if (flags & ACPI_NOT_ISR) { (void)acpi_ut_release_mutex(ACPI_MTX_EVENTS); diff --git a/drivers/acpi/fan.c b/drivers/acpi/fan.c index 60d54d1f6b19..eaaee1660bdf 100644 --- a/drivers/acpi/fan.c +++ b/drivers/acpi/fan.c @@ -34,7 +34,6 @@ #include #include -#define ACPI_FAN_COMPONENT 0x00200000 #define ACPI_FAN_CLASS "fan" #define ACPI_FAN_FILE_STATE "state" diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c index 24649ada08df..adec3d15810a 100644 --- a/drivers/acpi/glue.c +++ b/drivers/acpi/glue.c @@ -140,6 +140,46 @@ struct device *acpi_get_physical_device(acpi_handle handle) EXPORT_SYMBOL(acpi_get_physical_device); +/* ToDo: When a PCI bridge is found, return the PCI device behind the bridge + * This should work in general, but did not on a Lenovo T61 for the + * graphics card. But this must be fixed when the PCI device is + * bound and the kernel device struct is attached to the acpi device + * Note: A success call will increase reference count by one + * Do call put_device(dev) on the returned device then + */ +struct device *acpi_get_physical_pci_device(acpi_handle handle) +{ + struct device *dev; + long long device_id; + acpi_status status; + + status = + acpi_evaluate_integer(handle, "_ADR", NULL, &device_id); + + if (ACPI_FAILURE(status)) + return NULL; + + /* We need to attempt to determine whether the _ADR refers to a + PCI device or not. There's no terribly good way to do this, + so the best we can hope for is to assume that there'll never + be a device in the host bridge */ + if (device_id >= 0x10000) { + /* It looks like a PCI device. Does it exist? */ + dev = acpi_get_physical_device(handle); + } else { + /* It doesn't look like a PCI device. Does its parent + exist? */ + acpi_handle phandle; + if (acpi_get_parent(handle, &phandle)) + return NULL; + dev = acpi_get_physical_device(phandle); + } + if (!dev) + return NULL; + return dev; +} +EXPORT_SYMBOL(acpi_get_physical_pci_device); + static int acpi_bind_one(struct device *dev, acpi_handle handle) { struct acpi_device *acpi_dev; diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 4be252145cb4..c8111424dcb8 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -97,54 +96,44 @@ static DEFINE_SPINLOCK(acpi_res_lock); static char osi_additional_string[OSI_STRING_LENGTH_MAX]; /* - * "Ode to _OSI(Linux)" + * The story of _OSI(Linux) * - * osi_linux -- Control response to BIOS _OSI(Linux) query. + * From pre-history through Linux-2.6.22, + * Linux responded TRUE upon a BIOS OSI(Linux) query. * - * As Linux evolves, the features that it supports change. - * So an OSI string such as "Linux" is not specific enough - * to be useful across multiple versions of Linux. It - * doesn't identify any particular feature, interface, - * or even any particular version of Linux... + * Unfortunately, reference BIOS writers got wind of this + * and put OSI(Linux) in their example code, quickly exposing + * this string as ill-conceived and opening the door to + * an un-bounded number of BIOS incompatibilities. * - * Unfortunately, Linux-2.6.22 and earlier responded "yes" - * to a BIOS _OSI(Linux) query. When - * a reference mobile BIOS started using it, its use - * started to spread to many vendor platforms. - * As it is not supportable, we need to halt that spread. + * For example, OSI(Linux) was used on resume to re-POST a + * video card on one system, because Linux at that time + * could not do a speedy restore in its native driver. + * But then upon gaining quick native restore capability, + * Linux has no way to tell the BIOS to skip the time-consuming + * POST -- putting Linux at a permanent performance disadvantage. + * On another system, the BIOS writer used OSI(Linux) + * to infer native OS support for IPMI! On other systems, + * OSI(Linux) simply got in the way of Linux claiming to + * be compatible with other operating systems, exposing + * BIOS issues such as skipped device initialization. * - * Today, most BIOS references to _OSI(Linux) are noise -- - * they have no functional effect and are just dead code - * carried over from the reference BIOS. - * - * The next most common case is that _OSI(Linux) harms Linux, - * usually by causing the BIOS to follow paths that are - * not tested during Windows validation. - * - * Finally, there is a short list of platforms - * where OSI(Linux) benefits Linux. - * - * In Linux-2.6.23, OSI(Linux) is first disabled by default. - * DMI is used to disable the dmesg warning about OSI(Linux) - * on platforms where it is known to have no effect. - * But a dmesg warning remains for systems where - * we do not know if OSI(Linux) is good or bad for the system. - * DMI is also used to enable OSI(Linux) for the machines - * that are known to need it. + * So "Linux" turned out to be a really poor chose of + * OSI string, and from Linux-2.6.23 onward we respond FALSE. * * BIOS writers should NOT query _OSI(Linux) on future systems. - * It will be ignored by default, and to get Linux to - * not ignore it will require a kernel source update to - * add a DMI entry, or a boot-time "acpi_osi=Linux" invocation. + * Linux will complain on the console when it sees it, and return FALSE. + * To get Linux to return TRUE for your system will require + * a kernel source update to add a DMI entry, + * or boot with "acpi_osi=Linux" */ -#define OSI_LINUX_ENABLE 0 static struct osi_linux { unsigned int enable:1; unsigned int dmi:1; unsigned int cmdline:1; unsigned int known:1; -} osi_linux = { OSI_LINUX_ENABLE, 0, 0, 0}; +} osi_linux = { 0, 0, 0, 0}; static void __init acpi_request_region (struct acpi_generic_address *addr, unsigned int length, char *desc) @@ -1296,34 +1285,6 @@ acpi_status acpi_os_release_object(acpi_cache_t * cache, void *object) return (AE_OK); } -/** - * acpi_dmi_dump - dump DMI slots needed for blacklist entry - * - * Returns 0 on success - */ -static int acpi_dmi_dump(void) -{ - - if (!dmi_available) - return -1; - - printk(KERN_NOTICE PREFIX "DMI System Vendor: %s\n", - dmi_get_system_info(DMI_SYS_VENDOR)); - printk(KERN_NOTICE PREFIX "DMI Product Name: %s\n", - dmi_get_system_info(DMI_PRODUCT_NAME)); - printk(KERN_NOTICE PREFIX "DMI Product Version: %s\n", - dmi_get_system_info(DMI_PRODUCT_VERSION)); - printk(KERN_NOTICE PREFIX "DMI Board Name: %s\n", - dmi_get_system_info(DMI_BOARD_NAME)); - printk(KERN_NOTICE PREFIX "DMI BIOS Vendor: %s\n", - dmi_get_system_info(DMI_BIOS_VENDOR)); - printk(KERN_NOTICE PREFIX "DMI BIOS Date: %s\n", - dmi_get_system_info(DMI_BIOS_DATE)); - - return 0; -} - - /****************************************************************************** * * FUNCTION: acpi_os_validate_interface @@ -1350,21 +1311,6 @@ acpi_os_validate_interface (char *interface) osi_linux.cmdline ? " via cmdline" : osi_linux.dmi ? " via DMI" : ""); - if (!osi_linux.dmi) { - if (acpi_dmi_dump()) - printk(KERN_NOTICE PREFIX - "[please extract dmidecode output]\n"); - printk(KERN_NOTICE PREFIX - "Please send DMI info above to " - "linux-acpi@vger.kernel.org\n"); - } - if (!osi_linux.known && !osi_linux.cmdline) { - printk(KERN_NOTICE PREFIX - "If \"acpi_osi=%sLinux\" works better, " - "please notify linux-acpi@vger.kernel.org\n", - osi_linux.enable ? "!" : ""); - } - if (osi_linux.enable) return AE_OK; } diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c index fcfdef7b4fdd..e52ad91ce2dc 100644 --- a/drivers/acpi/pci_link.c +++ b/drivers/acpi/pci_link.c @@ -531,7 +531,7 @@ int __init acpi_irq_penalty_init(void) return 0; } -static int acpi_irq_balance; /* 0: static, 1: balance */ +static int acpi_irq_balance = -1; /* 0: static, 1: balance */ static int acpi_pci_link_allocate(struct acpi_pci_link *link) { @@ -950,10 +950,17 @@ device_initcall(irqrouter_init_sysfs); static int __init acpi_pci_link_init(void) { - if (acpi_noirq) return 0; + if (acpi_irq_balance == -1) { + /* no command line switch: enable balancing in IOAPIC mode */ + if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) + acpi_irq_balance = 1; + else + acpi_irq_balance = 0; + } + acpi_link.count = 0; INIT_LIST_HEAD(&acpi_link.entries); diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 1b8f67d21d53..642554b1b60c 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -376,15 +376,9 @@ static int acpi_pci_root_remove(struct acpi_device *device, int type) static int __init acpi_pci_root_init(void) { - if (acpi_pci_disabled) return 0; - /* DEBUG: - acpi_dbg_layer = ACPI_PCI_COMPONENT; - acpi_dbg_level = 0xFFFFFFFF; - */ - if (acpi_bus_register_driver(&acpi_pci_root_driver) < 0) return -ENODEV; diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c index a1718e56103b..bb7d50dd2818 100644 --- a/drivers/acpi/power.c +++ b/drivers/acpi/power.c @@ -44,9 +44,8 @@ #include #include -#define _COMPONENT ACPI_POWER_COMPONENT +#define _COMPONENT ACPI_POWER_COMPONENT ACPI_MODULE_NAME("power"); -#define ACPI_POWER_COMPONENT 0x00800000 #define ACPI_POWER_CLASS "power_resource" #define ACPI_POWER_DEVICE_NAME "Power Resource" #define ACPI_POWER_FILE_INFO "info" @@ -153,7 +152,8 @@ static int acpi_power_get_state(acpi_handle handle, int *state) ACPI_POWER_RESOURCE_STATE_OFF; ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] is %s\n", - acpi_ut_get_node_name(handle), state ? "on" : "off")); + acpi_ut_get_node_name(handle), + *state ? "on" : "off")); return 0; } @@ -516,11 +516,6 @@ int acpi_power_transition(struct acpi_device *device, int state) cl = &device->power.states[device->power.state].resources; tl = &device->power.states[state].resources; - if (!cl->count && !tl->count) { - result = -ENODEV; - goto end; - } - /* TBD: Resources must be ordered. */ /* diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 24a362f8034c..34948362f41d 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -59,7 +59,6 @@ #include #include -#define ACPI_PROCESSOR_COMPONENT 0x01000000 #define ACPI_PROCESSOR_CLASS "processor" #define ACPI_PROCESSOR_DEVICE_NAME "Processor" #define ACPI_PROCESSOR_FILE_INFO "info" @@ -89,6 +88,7 @@ static int acpi_processor_handle_eject(struct acpi_processor *pr); static const struct acpi_device_id processor_device_ids[] = { + {ACPI_PROCESSOR_OBJECT_HID, 0}, {ACPI_PROCESSOR_HID, 0}, {"", 0}, }; @@ -409,7 +409,7 @@ static int acpi_processor_remove_fs(struct acpi_device *device) /* Use the acpiid in MADT to map cpus in case of SMP */ #ifndef CONFIG_SMP -static int get_cpu_id(acpi_handle handle, u32 acpi_id) {return -1;} +static int get_cpu_id(acpi_handle handle, int type, u32 acpi_id) { return -1; } #else static struct acpi_table_madt *madt; @@ -428,27 +428,35 @@ static int map_lapic_id(struct acpi_subtable_header *entry, } static int map_lsapic_id(struct acpi_subtable_header *entry, - u32 acpi_id, int *apic_id) + int device_declaration, u32 acpi_id, int *apic_id) { struct acpi_madt_local_sapic *lsapic = (struct acpi_madt_local_sapic *)entry; + u32 tmp = (lsapic->id << 8) | lsapic->eid; + /* Only check enabled APICs*/ - if (lsapic->lapic_flags & ACPI_MADT_ENABLED) { - /* First check against id */ - if (lsapic->processor_id == acpi_id) { - *apic_id = (lsapic->id << 8) | lsapic->eid; - return 1; - /* Check against optional uid */ - } else if (entry->length >= 16 && - lsapic->uid == acpi_id) { - *apic_id = lsapic->uid; - return 1; - } - } + if (!(lsapic->lapic_flags & ACPI_MADT_ENABLED)) + return 0; + + /* Device statement declaration type */ + if (device_declaration) { + if (entry->length < 16) + printk(KERN_ERR PREFIX + "Invalid LSAPIC with Device type processor (SAPIC ID %#x)\n", + tmp); + else if (lsapic->uid == acpi_id) + goto found; + /* Processor statement declaration type */ + } else if (lsapic->processor_id == acpi_id) + goto found; + return 0; +found: + *apic_id = tmp; + return 1; } -static int map_madt_entry(u32 acpi_id) +static int map_madt_entry(int type, u32 acpi_id) { unsigned long madt_end, entry; int apic_id = -1; @@ -469,7 +477,7 @@ static int map_madt_entry(u32 acpi_id) if (map_lapic_id(header, acpi_id, &apic_id)) break; } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { - if (map_lsapic_id(header, acpi_id, &apic_id)) + if (map_lsapic_id(header, type, acpi_id, &apic_id)) break; } entry += header->length; @@ -477,7 +485,7 @@ static int map_madt_entry(u32 acpi_id) return apic_id; } -static int map_mat_entry(acpi_handle handle, u32 acpi_id) +static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id) { struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; union acpi_object *obj; @@ -500,7 +508,7 @@ static int map_mat_entry(acpi_handle handle, u32 acpi_id) if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) { map_lapic_id(header, acpi_id, &apic_id); } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { - map_lsapic_id(header, acpi_id, &apic_id); + map_lsapic_id(header, type, acpi_id, &apic_id); } exit: @@ -509,14 +517,14 @@ exit: return apic_id; } -static int get_cpu_id(acpi_handle handle, u32 acpi_id) +static int get_cpu_id(acpi_handle handle, int type, u32 acpi_id) { int i; int apic_id = -1; - apic_id = map_mat_entry(handle, acpi_id); + apic_id = map_mat_entry(handle, type, acpi_id); if (apic_id == -1) - apic_id = map_madt_entry(acpi_id); + apic_id = map_madt_entry(type, acpi_id); if (apic_id == -1) return apic_id; @@ -532,15 +540,16 @@ static int get_cpu_id(acpi_handle handle, u32 acpi_id) Driver Interface -------------------------------------------------------------------------- */ -static int acpi_processor_get_info(struct acpi_processor *pr, unsigned has_uid) +static int acpi_processor_get_info(struct acpi_device *device) { acpi_status status = 0; union acpi_object object = { 0 }; struct acpi_buffer buffer = { sizeof(union acpi_object), &object }; - int cpu_index; + struct acpi_processor *pr; + int cpu_index, device_declaration = 0; static int cpu0_initialized; - + pr = acpi_driver_data(device); if (!pr) return -EINVAL; @@ -561,22 +570,23 @@ static int acpi_processor_get_info(struct acpi_processor *pr, unsigned has_uid) ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No bus mastering arbitration control\n")); - /* Check if it is a Device with HID and UID */ - if (has_uid) { + if (!strcmp(acpi_device_hid(device), ACPI_PROCESSOR_HID)) { + /* + * Declared with "Device" statement; match _UID. + * Note that we don't handle string _UIDs yet. + */ unsigned long long value; status = acpi_evaluate_integer(pr->handle, METHOD_NAME__UID, NULL, &value); if (ACPI_FAILURE(status)) { - printk(KERN_ERR PREFIX "Evaluating processor _UID\n"); + printk(KERN_ERR PREFIX + "Evaluating processor _UID [%#x]\n", status); return -ENODEV; } + device_declaration = 1; pr->acpi_id = value; } else { - /* - * Evalute the processor object. Note that it is common on SMP to - * have the first (boot) processor with a valid PBLK address while - * all others have a NULL address. - */ + /* Declared with "Processor" statement; match ProcessorID */ status = acpi_evaluate_object(pr->handle, NULL, NULL, &buffer); if (ACPI_FAILURE(status)) { printk(KERN_ERR PREFIX "Evaluating processor object\n"); @@ -584,12 +594,13 @@ static int acpi_processor_get_info(struct acpi_processor *pr, unsigned has_uid) } /* - * TBD: Synch processor ID (via LAPIC/LSAPIC structures) on SMP. - * >>> 'acpi_get_processor_id(acpi_id, &id)' in arch/xxx/acpi.c - */ + * TBD: Synch processor ID (via LAPIC/LSAPIC structures) on SMP. + * >>> 'acpi_get_processor_id(acpi_id, &id)' in + * arch/xxx/acpi.c + */ pr->acpi_id = object.processor.proc_id; } - cpu_index = get_cpu_id(pr->handle, pr->acpi_id); + cpu_index = get_cpu_id(pr->handle, device_declaration, pr->acpi_id); /* Handle UP system running SMP kernel, with no LAPIC in MADT */ if (!cpu0_initialized && (cpu_index == -1) && @@ -661,7 +672,7 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) pr = acpi_driver_data(device); - result = acpi_processor_get_info(pr, device->flags.unique_id); + result = acpi_processor_get_info(device); if (result) { /* Processor is physically not present */ return 0; @@ -761,20 +772,20 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_proc_event(device, event, pr->performance_platform_limit); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, + dev_name(&device->dev), event, pr->performance_platform_limit); break; case ACPI_PROCESSOR_NOTIFY_POWER: acpi_processor_cst_has_changed(pr); acpi_bus_generate_proc_event(device, event, 0); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, 0); + dev_name(&device->dev), event, 0); break; case ACPI_PROCESSOR_NOTIFY_THROTTLING: acpi_processor_tstate_has_changed(pr); acpi_bus_generate_proc_event(device, event, 0); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, 0); + dev_name(&device->dev), event, 0); default: ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Unsupported event [0x%x]\n", event)); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 81b40ed5379e..5f8d746a9b81 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -59,7 +59,6 @@ #include #include -#define ACPI_PROCESSOR_COMPONENT 0x01000000 #define ACPI_PROCESSOR_CLASS "processor" #define _COMPONENT ACPI_PROCESSOR_COMPONENT ACPI_MODULE_NAME("processor_idle"); diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c index dc98f7a6f2c4..0d7b772bef50 100644 --- a/drivers/acpi/processor_perflib.c +++ b/drivers/acpi/processor_perflib.c @@ -38,12 +38,15 @@ #include #endif + +#ifdef CONFIG_X86 #include +#endif #include +#include #include -#define ACPI_PROCESSOR_COMPONENT 0x01000000 #define ACPI_PROCESSOR_CLASS "processor" #define ACPI_PROCESSOR_FILE_PERFORMANCE "performance" #define _COMPONENT ACPI_PROCESSOR_COMPONENT @@ -360,11 +363,13 @@ static int acpi_processor_get_performance_info(struct acpi_processor *pr) * the BIOS is older than the CPU and does not know its frequencies */ update_bios: +#ifdef CONFIG_X86 if (ACPI_SUCCESS(acpi_get_handle(pr->handle, "_PPC", &handle))){ if(boot_cpu_has(X86_FEATURE_EST)) printk(KERN_WARNING FW_BUG "BIOS needs update for CPU " "frequency support\n"); } +#endif return result; } diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c index ef34b18f95ca..b1eb376fae45 100644 --- a/drivers/acpi/processor_thermal.c +++ b/drivers/acpi/processor_thermal.c @@ -40,7 +40,6 @@ #include #include -#define ACPI_PROCESSOR_COMPONENT 0x01000000 #define ACPI_PROCESSOR_CLASS "processor" #define _COMPONENT ACPI_PROCESSOR_COMPONENT ACPI_MODULE_NAME("processor_thermal"); diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c index 3da2df93d924..a0c38c94a8a0 100644 --- a/drivers/acpi/processor_throttling.c +++ b/drivers/acpi/processor_throttling.c @@ -38,9 +38,9 @@ #include #include +#include #include -#define ACPI_PROCESSOR_COMPONENT 0x01000000 #define ACPI_PROCESSOR_CLASS "processor" #define _COMPONENT ACPI_PROCESSOR_COMPONENT ACPI_MODULE_NAME("processor_throttling"); diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c index 755baf2ca70a..a6b662c00b67 100644 --- a/drivers/acpi/reboot.c +++ b/drivers/acpi/reboot.c @@ -15,28 +15,9 @@ void acpi_reboot(void) rr = &acpi_gbl_FADT.reset_register; - /* - * Is the ACPI reset register supported? - * - * According to ACPI 3.0, FADT.flags.RESET_REG_SUP indicates - * whether the ACPI reset mechanism is supported. - * - * However, some boxes have this bit clear, yet a valid - * ACPI_RESET_REG & RESET_VALUE, and ACPI reboot is the only - * mechanism that works for them after S3. - * - * This suggests that other operating systems may not be checking - * the RESET_REG_SUP bit, and are using other means to decide - * whether to use the ACPI reboot mechanism or not. - * - * So when acpi reboot is requested, - * only the reset_register is checked. If the following - * conditions are met, it indicates that the reset register is supported. - * a. reset_register is not zero - * b. the access width is eight - * c. the bit_offset is zero - */ - if (!(rr->address) || rr->bit_width != 8 || rr->bit_offset != 0) + /* Is the reset register supported? */ + if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) || + rr->bit_width != 8 || rr->bit_offset != 0) return; reset_value = acpi_gbl_FADT.reset_value; diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index a9dda8e0f9f9..39b7233c3485 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -109,8 +109,7 @@ static int acpi_bus_hot_remove_device(void *context) return 0; ACPI_DEBUG_PRINT((ACPI_DB_INFO, - "Hot-removing device %s...\n", device->dev.bus_id)); - + "Hot-removing device %s...\n", dev_name(&device->dev))); if (acpi_bus_trim(device, 1)) { printk(KERN_ERR PREFIX @@ -460,7 +459,7 @@ static int acpi_device_register(struct acpi_device *device, acpi_device_bus_id->instance_no = 0; list_add_tail(&acpi_device_bus_id->node, &acpi_bus_id_list); } - sprintf(device->dev.bus_id, "%s:%02x", acpi_device_bus_id->bus_id, acpi_device_bus_id->instance_no); + dev_set_name(&device->dev, "%s:%02x", acpi_device_bus_id->bus_id, acpi_device_bus_id->instance_no); if (device->parent) { list_add_tail(&device->node, &device->parent->children); @@ -484,7 +483,8 @@ static int acpi_device_register(struct acpi_device *device, result = acpi_device_setup_files(device); if(result) - printk(KERN_ERR PREFIX "Error creating sysfs interface for device %s\n", device->dev.bus_id); + printk(KERN_ERR PREFIX "Error creating sysfs interface for device %s\n", + dev_name(&device->dev)); device->removal_type = ACPI_BUS_REMOVAL_NORMAL; return 0; @@ -751,16 +751,6 @@ static int acpi_bus_get_wakeup_device_flags(struct acpi_device *device) if (!acpi_match_device_ids(device, button_device_ids)) device->wakeup.flags.run_wake = 1; - /* - * Don't set Power button GPE as run_wake - * if Fixed Power button is used - */ - if (!strcmp(device->pnp.hardware_id, "PNP0C0C") && - !(acpi_gbl_FADT.flags & ACPI_FADT_POWER_BUTTON)) { - device->wakeup.flags.run_wake = 0; - device->wakeup.flags.valid = 0; - } - end: if (ACPI_FAILURE(status)) device->flags.wake_capable = 0; @@ -919,36 +909,6 @@ static void acpi_device_get_busid(struct acpi_device *device, } } -static int -acpi_video_bus_match(struct acpi_device *device) -{ - acpi_handle h_dummy; - - if (!device) - return -EINVAL; - - /* Since there is no HID, CID for ACPI Video drivers, we have - * to check well known required nodes for each feature we support. - */ - - /* Does this device able to support video switching ? */ - if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOD", &h_dummy)) && - ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOS", &h_dummy))) - return 0; - - /* Does this device able to retrieve a video ROM ? */ - if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_ROM", &h_dummy))) - return 0; - - /* Does this device able to configure which video head to be POSTed ? */ - if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_VPO", &h_dummy)) && - ACPI_SUCCESS(acpi_get_handle(device->handle, "_GPD", &h_dummy)) && - ACPI_SUCCESS(acpi_get_handle(device->handle, "_SPD", &h_dummy))) - return 0; - - return -ENODEV; -} - /* * acpi_bay_match - see if a device is an ejectable driver bay * @@ -1031,7 +991,7 @@ static void acpi_device_set_id(struct acpi_device *device, will get autoloaded and the device might still match against another driver. */ - if (ACPI_SUCCESS(acpi_video_bus_match(device))) + if (acpi_is_video_device(device)) cid_add = ACPI_VIDEO_HID; else if (ACPI_SUCCESS(acpi_bay_match(device))) cid_add = ACPI_BAY_HID; @@ -1043,7 +1003,7 @@ static void acpi_device_set_id(struct acpi_device *device, hid = ACPI_POWER_HID; break; case ACPI_BUS_TYPE_PROCESSOR: - hid = ACPI_PROCESSOR_HID; + hid = ACPI_PROCESSOR_OBJECT_HID; break; case ACPI_BUS_TYPE_SYSTEM: hid = ACPI_SYSTEM_HID; diff --git a/drivers/acpi/sleep/main.c b/drivers/acpi/sleep/main.c index 26571bafb158..28a691cc625e 100644 --- a/drivers/acpi/sleep/main.c +++ b/drivers/acpi/sleep/main.c @@ -90,6 +90,18 @@ void __init acpi_old_suspend_ordering(void) old_suspend_ordering = true; } +/* + * According to the ACPI specification the BIOS should make sure that ACPI is + * enabled and SCI_EN bit is set on wake-up from S1 - S3 sleep states. Still, + * some BIOSes don't do that and therefore we use acpi_enable() to enable ACPI + * on such systems during resume. Unfortunately that doesn't help in + * particularly pathological cases in which SCI_EN has to be set directly on + * resume, although the specification states very clearly that this flag is + * owned by the hardware. The set_sci_en_on_resume variable will be set in such + * cases. + */ +static bool set_sci_en_on_resume; + /** * acpi_pm_disable_gpes - Disable the GPEs. */ @@ -163,6 +175,8 @@ static void acpi_pm_end(void) acpi_target_sleep_state = ACPI_STATE_S0; acpi_sleep_tts_switch(acpi_target_sleep_state); } +#else /* !CONFIG_ACPI_SLEEP */ +#define acpi_target_sleep_state ACPI_STATE_S0 #endif /* CONFIG_ACPI_SLEEP */ #ifdef CONFIG_SUSPEND @@ -233,7 +247,11 @@ static int acpi_suspend_enter(suspend_state_t pm_state) } /* If ACPI is not enabled by the BIOS, we need to enable it here. */ - acpi_enable(); + if (set_sci_en_on_resume) + acpi_set_register(ACPI_BITREG_SCI_ENABLE, 1); + else + acpi_enable(); + /* Reprogram control registers and execute _BFS */ acpi_leave_sleep_state_prep(acpi_state); @@ -321,6 +339,12 @@ static int __init init_old_suspend_ordering(const struct dmi_system_id *d) return 0; } +static int __init init_set_sci_en_on_resume(const struct dmi_system_id *d) +{ + set_sci_en_on_resume = true; + return 0; +} + static struct dmi_system_id __initdata acpisleep_dmi_table[] = { { .callback = init_old_suspend_ordering, @@ -338,6 +362,22 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "HP xw4600 Workstation"), }, }, + { + .callback = init_set_sci_en_on_resume, + .ident = "Apple MacBook 1,1", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Computer, Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBook1,1"), + }, + }, + { + .callback = init_set_sci_en_on_resume, + .ident = "Apple MacMini 1,1", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Computer, Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), + }, + }, {}, }; #endif /* CONFIG_SUSPEND */ diff --git a/drivers/acpi/sleep/proc.c b/drivers/acpi/sleep/proc.c index 631ee2ee2ca0..4dbc2271acf5 100644 --- a/drivers/acpi/sleep/proc.c +++ b/drivers/acpi/sleep/proc.c @@ -367,7 +367,7 @@ acpi_system_wakeup_device_seq_show(struct seq_file *seq, void *offset) if (ldev) seq_printf(seq, "%s:%s", ldev->bus ? ldev->bus->name : "no-bus", - ldev->bus_id); + dev_name(ldev)); seq_printf(seq, "\n"); put_device(ldev); diff --git a/drivers/acpi/sleep/wakeup.c b/drivers/acpi/sleep/wakeup.c index 38655eb132dc..dea4c23df764 100644 --- a/drivers/acpi/sleep/wakeup.c +++ b/drivers/acpi/sleep/wakeup.c @@ -88,7 +88,7 @@ void acpi_enable_wakeup_device(u8 sleep_state) spin_unlock(&acpi_device_lock); if (!dev->wakeup.flags.run_wake) acpi_enable_gpe(dev->wakeup.gpe_device, - dev->wakeup.gpe_number, ACPI_ISR); + dev->wakeup.gpe_number); spin_lock(&acpi_device_lock); } spin_unlock(&acpi_device_lock); @@ -122,7 +122,7 @@ void acpi_disable_wakeup_device(u8 sleep_state) ACPI_GPE_TYPE_WAKE_RUN); /* Re-enable it, since set_gpe_type will disable it */ acpi_enable_gpe(dev->wakeup.gpe_device, - dev->wakeup.gpe_number, ACPI_NOT_ISR); + dev->wakeup.gpe_number); spin_lock(&acpi_device_lock); } continue; @@ -133,7 +133,7 @@ void acpi_disable_wakeup_device(u8 sleep_state) /* Never disable run-wake GPE */ if (!dev->wakeup.flags.run_wake) { acpi_disable_gpe(dev->wakeup.gpe_device, - dev->wakeup.gpe_number, ACPI_NOT_ISR); + dev->wakeup.gpe_number); acpi_clear_gpe(dev->wakeup.gpe_device, dev->wakeup.gpe_number, ACPI_NOT_ISR); } @@ -162,7 +162,7 @@ static int __init acpi_wakeup_device_init(void) dev->wakeup.gpe_number, ACPI_GPE_TYPE_WAKE_RUN); acpi_enable_gpe(dev->wakeup.gpe_device, - dev->wakeup.gpe_number, ACPI_NOT_ISR); + dev->wakeup.gpe_number); dev->wakeup.state.enabled = 1; spin_lock(&acpi_device_lock); } diff --git a/drivers/acpi/system.c b/drivers/acpi/system.c index 1d74171b7940..6e4107f82403 100644 --- a/drivers/acpi/system.c +++ b/drivers/acpi/system.c @@ -78,9 +78,15 @@ static ssize_t acpi_table_show(struct kobject *kobj, container_of(bin_attr, struct acpi_table_attr, attr); struct acpi_table_header *table_header = NULL; acpi_status status; + char name[ACPI_NAME_SIZE]; + + if (strncmp(table_attr->name, "NULL", 4)) + memcpy(name, table_attr->name, ACPI_NAME_SIZE); + else + memcpy(name, "\0\0\0\0", 4); status = - acpi_get_table(table_attr->name, table_attr->instance, + acpi_get_table(name, table_attr->instance, &table_header); if (ACPI_FAILURE(status)) return -ENODEV; @@ -95,21 +101,24 @@ static void acpi_table_attr_init(struct acpi_table_attr *table_attr, struct acpi_table_header *header = NULL; struct acpi_table_attr *attr = NULL; - memcpy(table_attr->name, table_header->signature, ACPI_NAME_SIZE); + if (table_header->signature[0] != '\0') + memcpy(table_attr->name, table_header->signature, + ACPI_NAME_SIZE); + else + memcpy(table_attr->name, "NULL", 4); list_for_each_entry(attr, &acpi_table_attr_list, node) { - if (!memcmp(table_header->signature, attr->name, - ACPI_NAME_SIZE)) + if (!memcmp(table_attr->name, attr->name, ACPI_NAME_SIZE)) if (table_attr->instance < attr->instance) table_attr->instance = attr->instance; } table_attr->instance++; if (table_attr->instance > 1 || (table_attr->instance == 1 && - !acpi_get_table(table_header-> - signature, 2, - &header))) - sprintf(table_attr->name + 4, "%d", table_attr->instance); + !acpi_get_table + (table_header->signature, 2, &header))) + sprintf(table_attr->name + ACPI_NAME_SIZE, "%d", + table_attr->instance); table_attr->attr.size = 0; table_attr->attr.read = acpi_table_show; @@ -167,7 +176,6 @@ static int acpi_system_sysfs_init(void) #define COUNT_ERROR 2 /* other */ #define NUM_COUNTERS_EXTRA 3 -#define ACPI_EVENT_VALID 0x01 struct event_counter { u32 count; u32 flags; @@ -312,12 +320,6 @@ static int get_status(u32 index, acpi_event_status *status, acpi_handle *handle) } else if (index < (num_gpes + ACPI_NUM_FIXED_EVENTS)) result = acpi_get_event_status(index - num_gpes, status); - /* - * sleep/power button GPE/Fixed Event is enabled after acpi_system_init, - * check the status at runtime and mark it as valid once it's enabled - */ - if (!result && (*status & ACPI_EVENT_FLAG_ENABLED)) - all_counters[index].flags |= ACPI_EVENT_VALID; end: return result; } @@ -346,12 +348,14 @@ static ssize_t counter_show(struct kobject *kobj, if (result) goto end; - if (!(all_counters[index].flags & ACPI_EVENT_VALID)) - size += sprintf(buf + size, " invalid"); + if (!(status & ACPI_EVENT_FLAG_HANDLE)) + size += sprintf(buf + size, " invalid"); else if (status & ACPI_EVENT_FLAG_ENABLED) - size += sprintf(buf + size, " enable"); + size += sprintf(buf + size, " enabled"); + else if (status & ACPI_EVENT_FLAG_WAKE_ENABLED) + size += sprintf(buf + size, " wake_enabled"); else - size += sprintf(buf + size, " disable"); + size += sprintf(buf + size, " disabled"); end: size += sprintf(buf + size, "\n"); @@ -385,7 +389,7 @@ static ssize_t counter_set(struct kobject *kobj, if (result) goto end; - if (!(all_counters[index].flags & ACPI_EVENT_VALID)) { + if (!(status & ACPI_EVENT_FLAG_HANDLE)) { printk(KERN_WARNING PREFIX "Can not change Invalid GPE/Fixed Event status\n"); return -EINVAL; @@ -394,10 +398,10 @@ static ssize_t counter_set(struct kobject *kobj, if (index < num_gpes) { if (!strcmp(buf, "disable\n") && (status & ACPI_EVENT_FLAG_ENABLED)) - result = acpi_disable_gpe(handle, index, ACPI_NOT_ISR); + result = acpi_disable_gpe(handle, index); else if (!strcmp(buf, "enable\n") && !(status & ACPI_EVENT_FLAG_ENABLED)) - result = acpi_enable_gpe(handle, index, ACPI_NOT_ISR); + result = acpi_enable_gpe(handle, index); else if (!strcmp(buf, "clear\n") && (status & ACPI_EVENT_FLAG_SET)) result = acpi_clear_gpe(handle, index, ACPI_NOT_ISR); diff --git a/drivers/acpi/tables/tbfadt.c b/drivers/acpi/tables/tbfadt.c index 2c7885e7ffba..2817158fb6a1 100644 --- a/drivers/acpi/tables/tbfadt.c +++ b/drivers/acpi/tables/tbfadt.c @@ -304,7 +304,7 @@ static void acpi_tb_convert_fadt(void) * The ACPI 1.0 reserved fields that will be zeroed are the bytes located at * offset 45, 55, 95, and the word located at offset 109, 110. */ - if (acpi_gbl_FADT.header.revision < 3) { + if (acpi_gbl_FADT.header.revision < FADT2_REVISION_ID) { acpi_gbl_FADT.preferred_profile = 0; acpi_gbl_FADT.pstate_control = 0; acpi_gbl_FADT.cst_control = 0; diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index ad6cae938f0b..073ff09218a9 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -47,7 +47,6 @@ #include #include -#define ACPI_THERMAL_COMPONENT 0x04000000 #define ACPI_THERMAL_CLASS "thermal_zone" #define ACPI_THERMAL_DEVICE_NAME "Thermal Zone" #define ACPI_THERMAL_FILE_STATE "state" @@ -576,7 +575,7 @@ static int acpi_thermal_critical(struct acpi_thermal *tz) acpi_bus_generate_proc_event(tz->device, ACPI_THERMAL_NOTIFY_CRITICAL, tz->trips.critical.flags.enabled); acpi_bus_generate_netlink_event(tz->device->pnp.device_class, - tz->device->dev.bus_id, + dev_name(&tz->device->dev), ACPI_THERMAL_NOTIFY_CRITICAL, tz->trips.critical.flags.enabled); @@ -605,7 +604,7 @@ static int acpi_thermal_hot(struct acpi_thermal *tz) acpi_bus_generate_proc_event(tz->device, ACPI_THERMAL_NOTIFY_HOT, tz->trips.hot.flags.enabled); acpi_bus_generate_netlink_event(tz->device->pnp.device_class, - tz->device->dev.bus_id, + dev_name(&tz->device->dev), ACPI_THERMAL_NOTIFY_HOT, tz->trips.hot.flags.enabled); @@ -1592,14 +1591,14 @@ static void acpi_thermal_notify(acpi_handle handle, u32 event, void *data) acpi_thermal_check(tz); acpi_bus_generate_proc_event(device, event, 0); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, 0); + dev_name(&device->dev), event, 0); break; case ACPI_THERMAL_NOTIFY_DEVICES: acpi_thermal_trips_update(tz, ACPI_TRIPS_REFRESH_DEVICES); acpi_thermal_check(tz); acpi_bus_generate_proc_event(device, event, 0); acpi_bus_generate_netlink_event(device->pnp.device_class, - device->dev.bus_id, event, 0); + dev_name(&device->dev), event, 0); break; default: ACPI_DEBUG_PRINT((ACPI_DB_INFO, diff --git a/drivers/acpi/toshiba_acpi.c b/drivers/acpi/toshiba_acpi.c index 2a632f8b7a05..40e60fc2e596 100644 --- a/drivers/acpi/toshiba_acpi.c +++ b/drivers/acpi/toshiba_acpi.c @@ -371,6 +371,7 @@ static void bt_poll_rfkill(struct input_polled_dev *poll_dev) RFKILL_STATE_HARD_BLOCKED); input_report_switch(poll_dev->input, SW_RFKILL_ALL, new_rfk_state); + input_sync(poll_dev->input); } } @@ -823,33 +824,36 @@ static int __init toshiba_acpi_init(void) toshiba_acpi_exit(); return -ENOMEM; } - } - /* Register input device for kill switch */ - toshiba_acpi.poll_dev = input_allocate_polled_device(); - if (!toshiba_acpi.poll_dev) { - printk(MY_ERR "unable to allocate kill-switch input device\n"); - toshiba_acpi_exit(); - return -ENOMEM; - } - toshiba_acpi.poll_dev->private = &toshiba_acpi; - toshiba_acpi.poll_dev->poll = bt_poll_rfkill; - toshiba_acpi.poll_dev->poll_interval = 1000; /* msecs */ - - toshiba_acpi.poll_dev->input->name = toshiba_acpi.rfk_name; - toshiba_acpi.poll_dev->input->id.bustype = BUS_HOST; - toshiba_acpi.poll_dev->input->id.vendor = 0x0930; /* Toshiba USB ID */ - set_bit(EV_SW, toshiba_acpi.poll_dev->input->evbit); - set_bit(SW_RFKILL_ALL, toshiba_acpi.poll_dev->input->swbit); - input_report_switch(toshiba_acpi.poll_dev->input, SW_RFKILL_ALL, TRUE); - - ret = input_register_polled_device(toshiba_acpi.poll_dev); - if (ret) { - printk(MY_ERR "unable to register kill-switch input device\n"); - rfkill_free(toshiba_acpi.rfk_dev); - toshiba_acpi.rfk_dev = NULL; - toshiba_acpi_exit(); - return ret; + /* Register input device for kill switch */ + toshiba_acpi.poll_dev = input_allocate_polled_device(); + if (!toshiba_acpi.poll_dev) { + printk(MY_ERR + "unable to allocate kill-switch input device\n"); + toshiba_acpi_exit(); + return -ENOMEM; + } + toshiba_acpi.poll_dev->private = &toshiba_acpi; + toshiba_acpi.poll_dev->poll = bt_poll_rfkill; + toshiba_acpi.poll_dev->poll_interval = 1000; /* msecs */ + + toshiba_acpi.poll_dev->input->name = toshiba_acpi.rfk_name; + toshiba_acpi.poll_dev->input->id.bustype = BUS_HOST; + /* Toshiba USB ID */ + toshiba_acpi.poll_dev->input->id.vendor = 0x0930; + set_bit(EV_SW, toshiba_acpi.poll_dev->input->evbit); + set_bit(SW_RFKILL_ALL, toshiba_acpi.poll_dev->input->swbit); + input_report_switch(toshiba_acpi.poll_dev->input, + SW_RFKILL_ALL, TRUE); + input_sync(toshiba_acpi.poll_dev->input); + + ret = input_register_polled_device(toshiba_acpi.poll_dev); + if (ret) { + printk(MY_ERR + "unable to register kill-switch input device\n"); + toshiba_acpi_exit(); + return ret; + } } return 0; diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c index e827be36ee8d..f844941089bb 100644 --- a/drivers/acpi/utils.c +++ b/drivers/acpi/utils.c @@ -259,34 +259,26 @@ acpi_evaluate_integer(acpi_handle handle, struct acpi_object_list *arguments, unsigned long long *data) { acpi_status status = AE_OK; - union acpi_object *element; + union acpi_object element; struct acpi_buffer buffer = { 0, NULL }; - if (!data) return AE_BAD_PARAMETER; - element = kzalloc(sizeof(union acpi_object), irqs_disabled() ? GFP_ATOMIC: GFP_KERNEL); - if (!element) - return AE_NO_MEMORY; - buffer.length = sizeof(union acpi_object); - buffer.pointer = element; + buffer.pointer = &element; status = acpi_evaluate_object(handle, pathname, arguments, &buffer); if (ACPI_FAILURE(status)) { acpi_util_eval_error(handle, pathname, status); - kfree(element); return status; } - if (element->type != ACPI_TYPE_INTEGER) { + if (element.type != ACPI_TYPE_INTEGER) { acpi_util_eval_error(handle, pathname, AE_BAD_DATA); - kfree(element); return AE_BAD_DATA; } - *data = element->integer.value; - kfree(element); + *data = element.integer.value; ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Return value [%llu]\n", *data)); diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index a29b0ccac65a..baa441929720 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -41,7 +41,6 @@ #include #include -#define ACPI_VIDEO_COMPONENT 0x08000000 #define ACPI_VIDEO_CLASS "video" #define ACPI_VIDEO_BUS_NAME "Video Bus" #define ACPI_VIDEO_DEVICE_NAME "Video Device" @@ -739,7 +738,8 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device) device->cap._DSS = 1; } - max_level = acpi_video_init_brightness(device); + if (acpi_video_backlight_support()) + max_level = acpi_video_init_brightness(device); if (device->cap._BCL && device->cap._BCM && max_level > 0) { int result; @@ -785,18 +785,21 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device) printk(KERN_ERR PREFIX "Create sysfs link\n"); } - if (device->cap._DCS && device->cap._DSS){ - static int count = 0; - char *name; - name = kzalloc(MAX_NAME_LEN, GFP_KERNEL); - if (!name) - return; - sprintf(name, "acpi_video%d", count++); - device->output_dev = video_output_register(name, - NULL, device, &acpi_output_properties); - kfree(name); + + if (acpi_video_display_switch_support()) { + + if (device->cap._DCS && device->cap._DSS) { + static int count; + char *name; + name = kzalloc(MAX_NAME_LEN, GFP_KERNEL); + if (!name) + return; + sprintf(name, "acpi_video%d", count++); + device->output_dev = video_output_register(name, + NULL, device, &acpi_output_properties); + kfree(name); + } } - return; } /* @@ -842,11 +845,16 @@ static void acpi_video_bus_find_cap(struct acpi_video_bus *video) static int acpi_video_bus_check(struct acpi_video_bus *video) { acpi_status status = -ENOENT; - + struct device *dev; if (!video) return -EINVAL; + dev = acpi_get_physical_pci_device(video->device->handle); + if (!dev) + return -ENODEV; + put_device(dev); + /* Since there is no HID, CID and so on for VGA driver, we have * to check well known required nodes. */ @@ -2094,12 +2102,6 @@ static int __init acpi_video_init(void) { int result = 0; - - /* - acpi_dbg_level = 0xFFFFFFFF; - acpi_dbg_layer = 0x08000000; - */ - acpi_video_dir = proc_mkdir(ACPI_VIDEO_CLASS, acpi_root_dir); if (!acpi_video_dir) return -ENODEV; diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c new file mode 100644 index 000000000000..f022eb6f5637 --- /dev/null +++ b/drivers/acpi/video_detect.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2008 SuSE Linux Products GmbH + * Thomas Renninger + * + * May be copied or modified under the terms of the GNU General Public License + * + * video_detect.c: + * Provides acpi_is_video_device() for early scanning of ACPI devices in scan.c + * There a Linux specific (Spec does not provide a HID for video devices) is + * assinged + * + * After PCI devices are glued with ACPI devices + * acpi_get_physical_pci_device() can be called to identify ACPI graphics + * devices for which a real graphics card is plugged in + * + * Now acpi_video_get_capabilities() can be called to check which + * capabilities the graphics cards plugged in support. The check for general + * video capabilities will be triggered by the first caller of + * acpi_video_get_capabilities(NULL); which will happen when the first + * backlight (or display output) switching supporting driver calls: + * acpi_video_backlight_support(); + * + * Depending on whether ACPI graphics extensions (cmp. ACPI spec Appendix B) + * are available, video.ko should be used to handle the device. + * + * Otherwise vendor specific drivers like thinkpad_acpi, asus_acpi, + * sony_acpi,... can take care about backlight brightness and display output + * switching. + * + * If CONFIG_ACPI_VIDEO is neither set as "compiled in" (y) nor as a module (m) + * this file will not be compiled, acpi_video_get_capabilities() and + * acpi_video_backlight_support() will always return 0 and vendor specific + * drivers always can handle backlight. + * + */ + +#include +#include + +ACPI_MODULE_NAME("video"); +#define _COMPONENT ACPI_VIDEO_COMPONENT + +static long acpi_video_support; +static bool acpi_video_caps_checked; + +static acpi_status +acpi_backlight_cap_match(acpi_handle handle, u32 level, void *context, + void **retyurn_value) +{ + long *cap = context; + acpi_handle h_dummy; + + if (ACPI_SUCCESS(acpi_get_handle(handle, "_BCM", &h_dummy)) && + ACPI_SUCCESS(acpi_get_handle(handle, "_BCL", &h_dummy))) { + ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found generic backlight " + "support\n")); + *cap |= ACPI_VIDEO_BACKLIGHT; + /* We have backlight support, no need to scan further */ + return AE_CTRL_TERMINATE; + } + return 0; +} + +/* Returns true if the device is a video device which can be handled by + * video.ko. + * The device will get a Linux specific CID added in scan.c to + * identify the device as an ACPI graphics device + * Be aware that the graphics device may not be physically present + * Use acpi_video_get_capabilities() to detect general ACPI video + * capabilities of present cards + */ +long acpi_is_video_device(struct acpi_device *device) +{ + acpi_handle h_dummy; + long video_caps = 0; + + if (!device) + return 0; + + /* Does this device able to support video switching ? */ + if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOD", &h_dummy)) && + ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOS", &h_dummy))) + video_caps |= ACPI_VIDEO_OUTPUT_SWITCHING; + + /* Does this device able to retrieve a video ROM ? */ + if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_ROM", &h_dummy))) + video_caps |= ACPI_VIDEO_ROM_AVAILABLE; + + /* Does this device able to configure which video head to be POSTed ? */ + if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_VPO", &h_dummy)) && + ACPI_SUCCESS(acpi_get_handle(device->handle, "_GPD", &h_dummy)) && + ACPI_SUCCESS(acpi_get_handle(device->handle, "_SPD", &h_dummy))) + video_caps |= ACPI_VIDEO_DEVICE_POSTING; + + /* Only check for backlight functionality if one of the above hit. */ + if (video_caps) + acpi_walk_namespace(ACPI_TYPE_DEVICE, device->handle, + ACPI_UINT32_MAX, acpi_backlight_cap_match, + &video_caps, NULL); + + return video_caps; +} +EXPORT_SYMBOL(acpi_is_video_device); + +static acpi_status +find_video(acpi_handle handle, u32 lvl, void *context, void **rv) +{ + long *cap = context; + struct device *dev; + struct acpi_device *acpi_dev; + + const struct acpi_device_id video_ids[] = { + {ACPI_VIDEO_HID, 0}, + {"", 0}, + }; + if (acpi_bus_get_device(handle, &acpi_dev)) + return AE_OK; + + if (!acpi_match_device_ids(acpi_dev, video_ids)) { + dev = acpi_get_physical_pci_device(handle); + if (!dev) + return AE_OK; + put_device(dev); + *cap |= acpi_is_video_device(acpi_dev); + } + return AE_OK; +} + +/* + * Returns the video capabilities of a specific ACPI graphics device + * + * if NULL is passed as argument all ACPI devices are enumerated and + * all graphics capabilities of physically present devices are + * summerized and returned. This is cached and done only once. + */ +long acpi_video_get_capabilities(acpi_handle graphics_handle) +{ + long caps = 0; + struct acpi_device *tmp_dev; + acpi_status status; + + if (acpi_video_caps_checked && graphics_handle == NULL) + return acpi_video_support; + + if (!graphics_handle) { + /* Only do the global walk through all graphics devices once */ + acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, + ACPI_UINT32_MAX, find_video, + &caps, NULL); + /* There might be boot param flags set already... */ + acpi_video_support |= caps; + acpi_video_caps_checked = 1; + /* Add blacklists here. Be careful to use the right *DMI* bits + * to still be able to override logic via boot params, e.g.: + * + * if (dmi_name_in_vendors("XY")) { + * acpi_video_support |= + * ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR; + * acpi_video_support |= + * ACPI_VIDEO_BACKLIGHT_DMI_VENDOR; + *} + */ + } else { + status = acpi_bus_get_device(graphics_handle, &tmp_dev); + if (ACPI_FAILURE(status)) { + ACPI_EXCEPTION((AE_INFO, status, "Invalid device")); + return 0; + } + acpi_walk_namespace(ACPI_TYPE_DEVICE, graphics_handle, + ACPI_UINT32_MAX, find_video, + &caps, NULL); + } + ACPI_DEBUG_PRINT((ACPI_DB_INFO, "We have 0x%lX video support %s %s\n", + graphics_handle ? caps : acpi_video_support, + graphics_handle ? "on device " : "in general", + graphics_handle ? acpi_device_bid(tmp_dev) : "")); + return caps; +} +EXPORT_SYMBOL(acpi_video_get_capabilities); + +/* Returns true if video.ko can do backlight switching */ +int acpi_video_backlight_support(void) +{ + /* + * We must check whether the ACPI graphics device is physically plugged + * in. Therefore this must be called after binding PCI and ACPI devices + */ + if (!acpi_video_caps_checked) + acpi_video_get_capabilities(NULL); + + /* First check for boot param -> highest prio */ + if (acpi_video_support & ACPI_VIDEO_BACKLIGHT_FORCE_VENDOR) + return 0; + else if (acpi_video_support & ACPI_VIDEO_BACKLIGHT_FORCE_VIDEO) + return 1; + + /* Then check for DMI blacklist -> second highest prio */ + if (acpi_video_support & ACPI_VIDEO_BACKLIGHT_DMI_VENDOR) + return 0; + else if (acpi_video_support & ACPI_VIDEO_BACKLIGHT_DMI_VIDEO) + return 1; + + /* Then go the default way */ + return acpi_video_support & ACPI_VIDEO_BACKLIGHT; +} +EXPORT_SYMBOL(acpi_video_backlight_support); + +/* + * Returns true if video.ko can do display output switching. + * This does not work well/at all with binary graphics drivers + * which disable system io ranges and do it on their own. + */ +int acpi_video_display_switch_support(void) +{ + if (!acpi_video_caps_checked) + acpi_video_get_capabilities(NULL); + + if (acpi_video_support & ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VENDOR) + return 0; + else if (acpi_video_support & ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO) + return 1; + + if (acpi_video_support & ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR) + return 0; + else if (acpi_video_support & ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO) + return 1; + + return acpi_video_support & ACPI_VIDEO_OUTPUT_SWITCHING; +} +EXPORT_SYMBOL(acpi_video_display_switch_support); + +/* + * Use acpi_display_output=vendor/video or acpi_backlight=vendor/video + * To force that backlight or display output switching is processed by vendor + * specific acpi drivers or video.ko driver. + */ +int __init acpi_backlight(char *str) +{ + if (str == NULL || *str == '\0') + return 1; + else { + if (!strcmp("vendor", str)) + acpi_video_support |= + ACPI_VIDEO_BACKLIGHT_FORCE_VENDOR; + if (!strcmp("video", str)) + acpi_video_support |= + ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO; + } + return 1; +} +__setup("acpi_backlight=", acpi_backlight); + +int __init acpi_display_output(char *str) +{ + if (str == NULL || *str == '\0') + return 1; + else { + if (!strcmp("vendor", str)) + acpi_video_support |= + ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VENDOR; + if (!strcmp("video", str)) + acpi_video_support |= + ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO; + } + return 1; +} +__setup("acpi_display_output=", acpi_display_output); diff --git a/drivers/acpi/wmi.c b/drivers/acpi/wmi.c index 47cd7baf9b1b..8a8b377712c9 100644 --- a/drivers/acpi/wmi.c +++ b/drivers/acpi/wmi.c @@ -660,7 +660,7 @@ static void acpi_wmi_notify(acpi_handle handle, u32 event, void *data) wblock->handler(event, wblock->handler_data); acpi_bus_generate_netlink_event( - device->pnp.device_class, device->dev.bus_id, + device->pnp.device_class, dev_name(&device->dev), event, 0); break; } diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 78fbec8ceda0..421b7c71e72d 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -153,7 +153,7 @@ config SATA_PROMISE If unsure, say N. config SATA_SX4 - tristate "Promise SATA SX4 support" + tristate "Promise SATA SX4 support (Experimental)" depends on PCI && EXPERIMENTAL help This option enables support for Promise Serial ATA SX4. @@ -219,8 +219,8 @@ config PATA_ACPI otherwise unsupported hardware. config PATA_ALI - tristate "ALi PATA support (Experimental)" - depends on PCI && EXPERIMENTAL + tristate "ALi PATA support" + depends on PCI help This option enables support for the ALi ATA interfaces found on the many ALi chipsets. @@ -263,7 +263,7 @@ config PATA_ATIIXP If unsure, say N. config PATA_CMD640_PCI - tristate "CMD640 PCI PATA support (Very Experimental)" + tristate "CMD640 PCI PATA support (Experimental)" depends on PCI && EXPERIMENTAL help This option enables support for the CMD640 PCI IDE @@ -291,8 +291,8 @@ config PATA_CS5520 If unsure, say N. config PATA_CS5530 - tristate "CS5530 PATA support (Experimental)" - depends on PCI && EXPERIMENTAL + tristate "CS5530 PATA support" + depends on PCI help This option enables support for the Cyrix/NatSemi/AMD CS5530 companion chip used with the MediaGX/Geode processor family. @@ -309,8 +309,8 @@ config PATA_CS5535 If unsure, say N. config PATA_CS5536 - tristate "CS5536 PATA support (Experimental)" - depends on PCI && X86 && !X86_64 && EXPERIMENTAL + tristate "CS5536 PATA support" + depends on PCI && X86 && !X86_64 help This option enables support for the AMD CS5536 companion chip used with the Geode LX processor family. @@ -363,7 +363,7 @@ config PATA_HPT37X If unsure, say N. config PATA_HPT3X2N - tristate "HPT 372N/302N PATA support (Very Experimental)" + tristate "HPT 372N/302N PATA support (Experimental)" depends on PCI && EXPERIMENTAL help This option enables support for the N variant HPT PATA @@ -389,8 +389,8 @@ config PATA_HPT3X3_DMA problems with DMA on this chipset. config PATA_ISAPNP - tristate "ISA Plug and Play PATA support (Experimental)" - depends on EXPERIMENTAL && ISAPNP + tristate "ISA Plug and Play PATA support" + depends on ISAPNP help This option enables support for ISA plug & play ATA controllers such as those found on old soundcards. @@ -498,8 +498,8 @@ config PATA_NINJA32 If unsure, say N. config PATA_NS87410 - tristate "Nat Semi NS87410 PATA support (Experimental)" - depends on PCI && EXPERIMENTAL + tristate "Nat Semi NS87410 PATA support" + depends on PCI help This option enables support for the National Semiconductor NS87410 PCI-IDE controller. @@ -507,8 +507,8 @@ config PATA_NS87410 If unsure, say N. config PATA_NS87415 - tristate "Nat Semi NS87415 PATA support (Experimental)" - depends on PCI && EXPERIMENTAL + tristate "Nat Semi NS87415 PATA support" + depends on PCI help This option enables support for the National Semiconductor NS87415 PCI-IDE controller. @@ -544,8 +544,8 @@ config PATA_PCMCIA If unsure, say N. config PATA_PDC_OLD - tristate "Older Promise PATA controller support (Experimental)" - depends on PCI && EXPERIMENTAL + tristate "Older Promise PATA controller support" + depends on PCI help This option enables support for the Promise 20246, 20262, 20263, 20265 and 20267 adapters. @@ -559,7 +559,7 @@ config PATA_QDI Support for QDI 6500 and 6580 PATA controllers on VESA local bus. config PATA_RADISYS - tristate "RADISYS 82600 PATA support (Very Experimental)" + tristate "RADISYS 82600 PATA support (Experimental)" depends on PCI && EXPERIMENTAL help This option enables support for the RADISYS 82600 @@ -586,8 +586,8 @@ config PATA_RZ1000 If unsure, say N. config PATA_SC1200 - tristate "SC1200 PATA support (Very Experimental)" - depends on PCI && EXPERIMENTAL + tristate "SC1200 PATA support" + depends on PCI help This option enables support for the NatSemi/AMD SC1200 SoC companion chip used with the Geode processor family. @@ -620,8 +620,8 @@ config PATA_SIL680 If unsure, say N. config PATA_SIS - tristate "SiS PATA support (Experimental)" - depends on PCI && EXPERIMENTAL + tristate "SiS PATA support" + depends on PCI help This option enables support for SiS PATA controllers diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index aeadd00411a1..a67b8e7c712d 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -49,6 +49,17 @@ #define DRV_NAME "ahci" #define DRV_VERSION "3.0" +/* Enclosure Management Control */ +#define EM_CTRL_MSG_TYPE 0x000f0000 + +/* Enclosure Management LED Message Type */ +#define EM_MSG_LED_HBA_PORT 0x0000000f +#define EM_MSG_LED_PMP_SLOT 0x0000ff00 +#define EM_MSG_LED_VALUE 0xffff0000 +#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 +#define EM_MSG_LED_VALUE_OFF 0xfff80000 +#define EM_MSG_LED_VALUE_ON 0x00010000 + static int ahci_skip_host_reset; module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); @@ -588,6 +599,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ + /* Promise */ + { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ + /* Generic, PCI class code for AHCI */ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, @@ -1220,18 +1234,20 @@ static void ahci_sw_activity_blink(unsigned long arg) struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; unsigned long led_message = emp->led_state; u32 activity_led_state; + unsigned long flags; - led_message &= 0xffff0000; + led_message &= EM_MSG_LED_VALUE; led_message |= ap->port_no | (link->pmp << 8); /* check to see if we've had activity. If so, * toggle state of LED and reset timer. If not, * turn LED to desired idle state. */ + spin_lock_irqsave(ap->lock, flags); if (emp->saved_activity != emp->activity) { emp->saved_activity = emp->activity; /* get the current LED state */ - activity_led_state = led_message & 0x00010000; + activity_led_state = led_message & EM_MSG_LED_VALUE_ON; if (activity_led_state) activity_led_state = 0; @@ -1239,17 +1255,18 @@ static void ahci_sw_activity_blink(unsigned long arg) activity_led_state = 1; /* clear old state */ - led_message &= 0xfff8ffff; + led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; /* toggle state */ led_message |= (activity_led_state << 16); mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); } else { /* switch to idle */ - led_message &= 0xfff8ffff; + led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; if (emp->blink_policy == BLINK_OFF) led_message |= (1 << 16); } + spin_unlock_irqrestore(ap->lock, flags); ahci_transmit_led_message(ap, led_message, 4); } @@ -1294,7 +1311,7 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, struct ahci_em_priv *emp; /* get the slot number from the message */ - pmp = (state & 0x0000ff00) >> 8; + pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; if (pmp < MAX_SLOTS) emp = &pp->em_priv[pmp]; else @@ -1319,7 +1336,7 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, message[0] |= (4 << 8); /* ignore 0:4 of byte zero, fill in port info yourself */ - message[1] = ((state & 0xfffffff0) | ap->port_no); + message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); /* write message to EM_LOC */ writel(message[0], mmio + hpriv->em_loc); @@ -1362,7 +1379,7 @@ static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, state = simple_strtoul(buf, NULL, 0); /* get the slot number from the message */ - pmp = (state & 0x0000ff00) >> 8; + pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; if (pmp < MAX_SLOTS) emp = &pp->em_priv[pmp]; else @@ -1373,7 +1390,7 @@ static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, * activity led through em_message */ if (emp->blink_policy) - state &= 0xfff8ffff; + state &= ~EM_MSG_LED_VALUE_ACTIVITY; return ahci_transmit_led_message(ap, state, size); } @@ -1392,16 +1409,16 @@ static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); /* set the LED to OFF */ - port_led_state &= 0xfff80000; + port_led_state &= EM_MSG_LED_VALUE_OFF; port_led_state |= (ap->port_no | (link->pmp << 8)); ahci_transmit_led_message(ap, port_led_state, 4); } else { link->flags |= ATA_LFLAG_SW_ACTIVITY; if (val == BLINK_OFF) { /* set LED to ON for idle */ - port_led_state &= 0xfff80000; + port_led_state &= EM_MSG_LED_VALUE_OFF; port_led_state |= (ap->port_no | (link->pmp << 8)); - port_led_state |= 0x00010000; /* check this */ + port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ ahci_transmit_led_message(ap, port_led_state, 4); } } @@ -2612,7 +2629,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) u32 em_loc = readl(mmio + HOST_EM_LOC); u32 em_ctl = readl(mmio + HOST_EM_CTL); - messages = (em_ctl & 0x000f0000) >> 16; + messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; /* we only support LED message type right now */ if ((messages & 0x01) && (ahci_em_messages == 1)) { diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c index 75a406f5e694..5c33767e66de 100644 --- a/drivers/ata/ata_generic.c +++ b/drivers/ata/ata_generic.c @@ -1,6 +1,6 @@ /* * ata_generic.c - Generic PATA/SATA controller driver. - * Copyright 2005 Red Hat Inc , all rights reserved. + * Copyright 2005 Red Hat Inc, all rights reserved. * * Elements from ide/pci/generic.c * Copyright (C) 2001-2002 Andre Hedrick diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index e9e32ed6b1a3..c11936e13dd3 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c @@ -14,7 +14,7 @@ * * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer * Copyright (C) 1998-2000 Andre Hedrick - * Copyright (C) 2003 Red Hat Inc + * Copyright (C) 2003 Red Hat Inc * * * This program is free software; you can redistribute it and/or modify @@ -738,7 +738,6 @@ static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) * do_pata_set_dmamode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Drive in question - * @udma: udma mode, 0 - 6 * @isich: set if the chip is an ICH device * * Set UDMA mode for device, in host controller PCI config space. @@ -1067,6 +1066,28 @@ static int piix_broken_suspend(void) if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) return 1; + /* TECRA M4 sometimes forgets its identify and reports bogus + * DMI information. As the bogus information is a bit + * generic, match as many entries as possible. This manual + * matching is necessary because dmi_system_id.matches is + * limited to four entries. + */ + if (dmi_get_system_info(DMI_SYS_VENDOR) && + dmi_get_system_info(DMI_PRODUCT_NAME) && + dmi_get_system_info(DMI_PRODUCT_VERSION) && + dmi_get_system_info(DMI_PRODUCT_SERIAL) && + dmi_get_system_info(DMI_BOARD_VENDOR) && + dmi_get_system_info(DMI_BOARD_NAME) && + dmi_get_system_info(DMI_BOARD_VERSION) && + !strcmp(dmi_get_system_info(DMI_SYS_VENDOR), "TOSHIBA") && + !strcmp(dmi_get_system_info(DMI_PRODUCT_NAME), "000000") && + !strcmp(dmi_get_system_info(DMI_PRODUCT_VERSION), "000000") && + !strcmp(dmi_get_system_info(DMI_PRODUCT_SERIAL), "000000") && + !strcmp(dmi_get_system_info(DMI_BOARD_VENDOR), "TOSHIBA") && + !strcmp(dmi_get_system_info(DMI_BOARD_NAME), "Portable PC") && + !strcmp(dmi_get_system_info(DMI_BOARD_VERSION), "Version A0")) + return 1; + return 0; } diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 8cb0b360bfd8..bc6695e3c848 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -612,7 +612,7 @@ u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev) if (tf->flags & ATA_TFLAG_LBA48) { block |= (u64)tf->hob_lbah << 40; block |= (u64)tf->hob_lbam << 32; - block |= tf->hob_lbal << 24; + block |= (u64)tf->hob_lbal << 24; } else block |= (tf->device & 0xf) << 24; @@ -1268,7 +1268,7 @@ u64 ata_tf_to_lba48(const struct ata_taskfile *tf) sectors |= ((u64)(tf->hob_lbah & 0xff)) << 40; sectors |= ((u64)(tf->hob_lbam & 0xff)) << 32; - sectors |= (tf->hob_lbal & 0xff) << 24; + sectors |= ((u64)(tf->hob_lbal & 0xff)) << 24; sectors |= (tf->lbah & 0xff) << 16; sectors |= (tf->lbam & 0xff) << 8; sectors |= (tf->lbal & 0xff); @@ -1602,7 +1602,6 @@ unsigned long ata_id_xfermask(const u16 *id) /** * ata_pio_queue_task - Queue port_task * @ap: The ata_port to queue port_task for - * @fn: workqueue function to be scheduled * @data: data for @fn to use * @delay: delay time in msecs for workqueue function * @@ -1713,6 +1712,8 @@ unsigned ata_exec_internal_sg(struct ata_device *dev, else tag = 0; + if (test_and_set_bit(tag, &ap->qc_allocated)) + BUG(); qc = __ata_qc_from_tag(ap, tag); qc->tag = tag; @@ -2159,6 +2160,10 @@ retry: static inline u8 ata_dev_knobble(struct ata_device *dev) { struct ata_port *ap = dev->link->ap; + + if (ata_dev_blacklisted(dev) & ATA_HORKAGE_BRIDGE_OK) + return 0; + return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id))); } @@ -2487,6 +2492,13 @@ int ata_dev_configure(struct ata_device *dev) } } + if ((dev->horkage & ATA_HORKAGE_FIRMWARE_WARN) && print_info) { + ata_dev_printk(dev, KERN_WARNING, "WARNING: device requires " + "firmware update to be fully functional.\n"); + ata_dev_printk(dev, KERN_WARNING, " contact the vendor " + "or visit http://ata.wiki.kernel.org.\n"); + } + return 0; err_out_nosup: @@ -4021,6 +4033,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { /* Weird ATAPI devices */ { "TORiSAN DVD-ROM DRD-N216", NULL, ATA_HORKAGE_MAX_SEC_128 }, + { "QUANTUM DAT DAT72-000", NULL, ATA_HORKAGE_ATAPI_MOD16_DMA }, /* Devices we expect to fail diagnostics */ @@ -4036,6 +4049,73 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { { "ST380817AS", "3.42", ATA_HORKAGE_NONCQ }, { "ST3160023AS", "3.42", ATA_HORKAGE_NONCQ }, + /* Seagate NCQ + FLUSH CACHE firmware bug */ + { "ST31500341AS", "SD15", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31500341AS", "SD16", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31500341AS", "SD17", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31500341AS", "SD18", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31500341AS", "SD19", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + + { "ST31000333AS", "SD15", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31000333AS", "SD16", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31000333AS", "SD17", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31000333AS", "SD18", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST31000333AS", "SD19", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + + { "ST3640623AS", "SD15", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640623AS", "SD16", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640623AS", "SD17", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640623AS", "SD18", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640623AS", "SD19", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + + { "ST3640323AS", "SD15", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640323AS", "SD16", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640323AS", "SD17", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640323AS", "SD18", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3640323AS", "SD19", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + + { "ST3320813AS", "SD15", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320813AS", "SD16", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320813AS", "SD17", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320813AS", "SD18", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320813AS", "SD19", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + + { "ST3320613AS", "SD15", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320613AS", "SD16", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320613AS", "SD17", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320613AS", "SD18", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + { "ST3320613AS", "SD19", ATA_HORKAGE_NONCQ | + ATA_HORKAGE_FIRMWARE_WARN }, + /* Blacklist entries taken from Silicon Image 3124/3132 Windows driver .inf file - also several Linux problem reports */ { "HTS541060G9SA00", "MB3OC60D", ATA_HORKAGE_NONCQ, }, @@ -4063,6 +4143,9 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { { "TSSTcorp CDDVDW SH-S202N", "SB00", ATA_HORKAGE_IVB, }, { "TSSTcorp CDDVDW SH-S202N", "SB01", ATA_HORKAGE_IVB, }, + /* Devices that do not need bridging limits applied */ + { "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, }, + /* End Marker */ { } }; @@ -4156,29 +4239,33 @@ static int cable_is_40wire(struct ata_port *ap) struct ata_link *link; struct ata_device *dev; - /* If the controller thinks we are 40 wire, we are */ + /* If the controller thinks we are 40 wire, we are. */ if (ap->cbl == ATA_CBL_PATA40) return 1; - /* If the controller thinks we are 80 wire, we are */ + + /* If the controller thinks we are 80 wire, we are. */ if (ap->cbl == ATA_CBL_PATA80 || ap->cbl == ATA_CBL_SATA) return 0; - /* If the system is known to be 40 wire short cable (eg laptop), - then we allow 80 wire modes even if the drive isn't sure */ + + /* If the system is known to be 40 wire short cable (eg + * laptop), then we allow 80 wire modes even if the drive + * isn't sure. + */ if (ap->cbl == ATA_CBL_PATA40_SHORT) return 0; - /* If the controller doesn't know we scan - - - Note: We look for all 40 wire detects at this point. - Any 80 wire detect is taken to be 80 wire cable - because - - In many setups only the one drive (slave if present) - will give a valid detect - - If you have a non detect capable drive you don't - want it to colour the choice - */ + + /* If the controller doesn't know, we scan. + * + * Note: We look for all 40 wire detects at this point. Any + * 80 wire detect is taken to be 80 wire cable because + * - in many setups only the one drive (slave if present) will + * give a valid detect + * - if you have a non detect capable drive you don't want it + * to colour the choice + */ ata_port_for_each_link(link, ap) { ata_link_for_each_dev(dev, link) { - if (!ata_is_40wire(dev)) + if (ata_dev_enabled(dev) && !ata_is_40wire(dev)) return 0; } } @@ -4434,7 +4521,8 @@ int atapi_check_dma(struct ata_queued_cmd *qc) /* Don't allow DMA if it isn't multiple of 16 bytes. Quite a * few ATAPI devices choke on such DMA requests. */ - if (unlikely(qc->nbytes & 15)) + if (!(qc->dev->horkage & ATA_HORKAGE_ATAPI_MOD16_DMA) && + unlikely(qc->nbytes & 15)) return 1; if (ap->ops->check_atapi_dma) @@ -4551,27 +4639,55 @@ void swap_buf_le16(u16 *buf, unsigned int buf_words) } /** - * ata_qc_new_init - Request an available ATA command, and initialize it + * ata_qc_new - Request an available ATA command, for queueing + * @ap: Port associated with device @dev * @dev: Device from whom we request an available command structure * * LOCKING: * None. */ -struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag) +static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap) { - struct ata_port *ap = dev->link->ap; - struct ata_queued_cmd *qc; + struct ata_queued_cmd *qc = NULL; + unsigned int i; + /* no command while frozen */ if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) return NULL; - qc = __ata_qc_from_tag(ap, tag); + /* the last tag is reserved for internal command. */ + for (i = 0; i < ATA_MAX_QUEUE - 1; i++) + if (!test_and_set_bit(i, &ap->qc_allocated)) { + qc = __ata_qc_from_tag(ap, i); + break; + } + + if (qc) + qc->tag = i; + + return qc; +} + +/** + * ata_qc_new_init - Request an available ATA command, and initialize it + * @dev: Device from whom we request an available command structure + * @tag: command tag + * + * LOCKING: + * None. + */ + +struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev) +{ + struct ata_port *ap = dev->link->ap; + struct ata_queued_cmd *qc; + + qc = ata_qc_new(ap); if (qc) { qc->scsicmd = NULL; qc->ap = ap; qc->dev = dev; - qc->tag = tag; ata_qc_reinit(qc); } @@ -4579,6 +4695,31 @@ struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag) return qc; } +/** + * ata_qc_free - free unused ata_queued_cmd + * @qc: Command to complete + * + * Designed to free unused ata_queued_cmd object + * in case something prevents using it. + * + * LOCKING: + * spin_lock_irqsave(host lock) + */ +void ata_qc_free(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + unsigned int tag; + + WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */ + + qc->flags = 0; + tag = qc->tag; + if (likely(ata_tag_valid(tag))) { + qc->tag = ATA_TAG_POISON; + clear_bit(tag, &ap->qc_allocated); + } +} + void __ata_qc_complete(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; @@ -4643,7 +4784,6 @@ static void ata_verify_xfer(struct ata_queued_cmd *qc) /** * ata_qc_complete - Complete an active ATA command * @qc: Command to complete - * @err_mask: ATA Status register contents * * Indicate to the mid and upper layers that an ATA * command has completed, with either an ok or not-ok status. @@ -5924,7 +6064,7 @@ static void ata_port_detach(struct ata_port *ap) * to us. Restore SControl and disable all existing devices. */ __ata_port_for_each_link(link, ap) { - sata_scr_write(link, SCR_CONTROL, link->saved_scontrol); + sata_scr_write(link, SCR_CONTROL, link->saved_scontrol & 0xff0); ata_link_for_each_dev(dev, link) ata_dev_disable(dev); } diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index 5d687d7cffae..32da9a93ce44 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -603,13 +603,13 @@ void ata_scsi_error(struct Scsi_Host *host) ata_link_for_each_dev(dev, link) { int devno = dev->devno; + if (!ata_dev_enabled(dev)) + continue; + ehc->saved_xfer_mode[devno] = dev->xfer_mode; if (ata_ncq_enabled(dev)) ehc->saved_ncq_enabled |= 1 << devno; } - - /* set last reset timestamp to some time in the past */ - ehc->last_reset = jiffies - 60 * HZ; } ap->pflags |= ATA_PFLAG_EH_IN_PROGRESS; @@ -1161,6 +1161,7 @@ void ata_eh_detach_dev(struct ata_device *dev) { struct ata_link *link = dev->link; struct ata_port *ap = link->ap; + struct ata_eh_context *ehc = &link->eh_context; unsigned long flags; ata_dev_disable(dev); @@ -1174,9 +1175,11 @@ void ata_eh_detach_dev(struct ata_device *dev) ap->pflags |= ATA_PFLAG_SCSI_HOTPLUG; } - /* clear per-dev EH actions */ + /* clear per-dev EH info */ ata_eh_clear_action(link, dev, &link->eh_info, ATA_EH_PERDEV_MASK); ata_eh_clear_action(link, dev, &link->eh_context.i, ATA_EH_PERDEV_MASK); + ehc->saved_xfer_mode[dev->devno] = 0; + ehc->saved_ncq_enabled &= ~(1 << dev->devno); spin_unlock_irqrestore(ap->lock, flags); } @@ -2275,17 +2278,21 @@ int ata_eh_reset(struct ata_link *link, int classify, if (link->flags & ATA_LFLAG_NO_SRST) softreset = NULL; - now = jiffies; - deadline = ata_deadline(ehc->last_reset, ATA_EH_RESET_COOL_DOWN); - if (time_before(now, deadline)) - schedule_timeout_uninterruptible(deadline - now); + /* make sure each reset attemp is at least COOL_DOWN apart */ + if (ehc->i.flags & ATA_EHI_DID_RESET) { + now = jiffies; + WARN_ON(time_after(ehc->last_reset, now)); + deadline = ata_deadline(ehc->last_reset, + ATA_EH_RESET_COOL_DOWN); + if (time_before(now, deadline)) + schedule_timeout_uninterruptible(deadline - now); + } spin_lock_irqsave(ap->lock, flags); ap->pflags |= ATA_PFLAG_RESETTING; spin_unlock_irqrestore(ap->lock, flags); ata_eh_about_to_do(link, NULL, ATA_EH_RESET); - ehc->last_reset = jiffies; ata_link_for_each_dev(dev, link) { /* If we issue an SRST then an ATA drive (not ATAPI) @@ -2373,7 +2380,6 @@ int ata_eh_reset(struct ata_link *link, int classify, /* * Perform reset */ - ehc->last_reset = jiffies; if (ata_is_host_link(link)) ata_eh_freeze_port(ap); @@ -2385,6 +2391,7 @@ int ata_eh_reset(struct ata_link *link, int classify, reset == softreset ? "soft" : "hard"); /* mark that this EH session started with reset */ + ehc->last_reset = jiffies; if (reset == hardreset) ehc->i.flags |= ATA_EHI_DID_HARDRESET; else @@ -2529,7 +2536,7 @@ int ata_eh_reset(struct ata_link *link, int classify, ata_eh_done(link, NULL, ATA_EH_RESET); if (slave) ata_eh_done(slave, NULL, ATA_EH_RESET); - ehc->last_reset = jiffies; + ehc->last_reset = jiffies; /* update to completion time */ ehc->i.action |= ATA_EH_REVALIDATE; rc = 0; @@ -2787,6 +2794,9 @@ int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev) /* if data transfer is verified, clear DUBIOUS_XFER on ering top */ ata_link_for_each_dev(dev, link) { + if (!ata_dev_enabled(dev)) + continue; + if (!(dev->flags & ATA_DFLAG_DUBIOUS_XFER)) { struct ata_ering_entry *ent; @@ -2808,6 +2818,9 @@ int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev) u8 saved_xfer_mode = ehc->saved_xfer_mode[dev->devno]; u8 saved_ncq = !!(ehc->saved_ncq_enabled & (1 << dev->devno)); + if (!ata_dev_enabled(dev)) + continue; + if (dev->xfer_mode != saved_xfer_mode || ata_ncq_enabled(dev) != saved_ncq) dev->flags |= ATA_DFLAG_DUBIOUS_XFER; diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 4b95c4387e9e..47c7afcb36f2 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -190,7 +190,7 @@ static ssize_t ata_scsi_park_show(struct device *device, struct ata_port *ap; struct ata_link *link; struct ata_device *dev; - unsigned long flags; + unsigned long flags, now; unsigned int uninitialized_var(msecs); int rc = 0; @@ -208,10 +208,11 @@ static ssize_t ata_scsi_park_show(struct device *device, } link = dev->link; + now = jiffies; if (ap->pflags & ATA_PFLAG_EH_IN_PROGRESS && link->eh_context.unloaded_mask & (1 << dev->devno) && - time_after(dev->unpark_deadline, jiffies)) - msecs = jiffies_to_msecs(dev->unpark_deadline - jiffies); + time_after(dev->unpark_deadline, now)) + msecs = jiffies_to_msecs(dev->unpark_deadline - now); else msecs = 0; @@ -708,11 +709,7 @@ static struct ata_queued_cmd *ata_scsi_qc_new(struct ata_device *dev, { struct ata_queued_cmd *qc; - if (cmd->request->tag != -1) - qc = ata_qc_new_init(dev, cmd->request->tag); - else - qc = ata_qc_new_init(dev, 0); - + qc = ata_qc_new_init(dev); if (qc) { qc->scsicmd = cmd; qc->scsidone = done; @@ -1107,8 +1104,7 @@ static int ata_scsi_dev_config(struct scsi_device *sdev, depth = min(sdev->host->can_queue, ata_id_queue_depth(dev->id)); depth = min(ATA_MAX_QUEUE - 1, depth); - scsi_set_tag_type(sdev, MSG_SIMPLE_TAG); - scsi_activate_tcq(sdev, depth); + scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, depth); } return 0; @@ -1948,11 +1944,6 @@ static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf) hdr[1] |= (1 << 7); memcpy(rbuf, hdr, sizeof(hdr)); - - /* if ncq, set tags supported */ - if (ata_id_has_ncq(args->id)) - rbuf[7] |= (1 << 1); - memcpy(&rbuf[8], "ATA ", 8); ata_id_string(args->id, &rbuf[16], ATA_ID_PROD, 16); ata_id_string(args->id, &rbuf[32], ATA_ID_FW_REV, 4); diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 4b4739486327..9033d164c4ec 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c @@ -1227,10 +1227,19 @@ fsm_start: /* ATA PIO protocol */ if (unlikely((status & ATA_DRQ) == 0)) { /* handle BSY=0, DRQ=0 as error */ - if (likely(status & (ATA_ERR | ATA_DF))) + if (likely(status & (ATA_ERR | ATA_DF))) { /* device stops HSM for abort/error */ qc->err_mask |= AC_ERR_DEV; - else { + + /* If diagnostic failed and this is + * IDENTIFY, it's likely a phantom + * device. Mark hint. + */ + if (qc->dev->horkage & + ATA_HORKAGE_DIAGNOSTIC) + qc->err_mask |= + AC_ERR_NODEV_HINT; + } else { /* HSM violation. Let EH handle this. * Phantom devices also trigger this * condition. Mark hint. diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index d3831d39bdaa..fe2839e58774 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h @@ -74,7 +74,7 @@ extern struct ata_link *ata_dev_phys_link(struct ata_device *dev); extern void ata_force_cbl(struct ata_port *ap); extern u64 ata_tf_to_lba(const struct ata_taskfile *tf); extern u64 ata_tf_to_lba48(const struct ata_taskfile *tf); -extern struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag); +extern struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev); extern int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev, u64 block, u32 n_block, unsigned int tf_flags, unsigned int tag); @@ -103,6 +103,7 @@ extern int ata_dev_configure(struct ata_device *dev); extern int sata_down_spd_limit(struct ata_link *link); extern int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel); extern void ata_sg_clean(struct ata_queued_cmd *qc); +extern void ata_qc_free(struct ata_queued_cmd *qc); extern void ata_qc_issue(struct ata_queued_cmd *qc); extern void __ata_qc_complete(struct ata_queued_cmd *qc); extern int atapi_check_dma(struct ata_queued_cmd *qc); @@ -118,22 +119,6 @@ extern struct ata_port *ata_port_alloc(struct ata_host *host); extern void ata_dev_enable_pm(struct ata_device *dev, enum link_pm policy); extern void ata_lpm_schedule(struct ata_port *ap, enum link_pm); -/** - * ata_qc_free - free unused ata_queued_cmd - * @qc: Command to complete - * - * Designed to free unused ata_queued_cmd object - * in case something prevents using it. - * - * LOCKING: - * spin_lock_irqsave(host lock) - */ -static inline void ata_qc_free(struct ata_queued_cmd *qc) -{ - qc->flags = 0; - qc->tag = ATA_TAG_POISON; -} - /* libata-acpi.c */ #ifdef CONFIG_ATA_ACPI extern void ata_acpi_associate_sata_port(struct ata_port *ap); diff --git a/drivers/ata/pata_acpi.c b/drivers/ata/pata_acpi.c index eb919c16a03e..e2e332d8ff95 100644 --- a/drivers/ata/pata_acpi.c +++ b/drivers/ata/pata_acpi.c @@ -1,7 +1,7 @@ /* * ACPI PATA driver * - * (c) 2007 Red Hat + * (c) 2007 Red Hat */ #include diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c index 5ca70fa1f587..73c466e452ca 100644 --- a/drivers/ata/pata_ali.c +++ b/drivers/ata/pata_ali.c @@ -1,7 +1,6 @@ /* * pata_ali.c - ALI 15x3 PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * based in part upon * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02 diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c index 57dd00f463d3..0ec9c7d9fe9d 100644 --- a/drivers/ata/pata_amd.c +++ b/drivers/ata/pata_amd.c @@ -1,7 +1,6 @@ /* * pata_amd.c - AMD PATA for new ATA layer * (C) 2005-2006 Red Hat Inc - * Alan Cox * * Based on pata-sil680. Errata information is taken from data sheets * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c index 0f513bc11193..6b3092c75ffe 100644 --- a/drivers/ata/pata_artop.c +++ b/drivers/ata/pata_artop.c @@ -1,7 +1,7 @@ /* * pata_artop.c - ARTOP ATA controller driver * - * (C) 2006 Red Hat + * (C) 2006 Red Hat * (C) 2007 Bartlomiej Zolnierkiewicz * * Based in part on drivers/ide/pci/aec62xx.c diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c index e8a0d99d7356..0e2cde8f9973 100644 --- a/drivers/ata/pata_atiixp.c +++ b/drivers/ata/pata_atiixp.c @@ -1,7 +1,6 @@ /* * pata_atiixp.c - ATI PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * Based on * diff --git a/drivers/ata/pata_cmd640.c b/drivers/ata/pata_cmd640.c index 2de30b990278..34a394264c3d 100644 --- a/drivers/ata/pata_cmd640.c +++ b/drivers/ata/pata_cmd640.c @@ -1,7 +1,6 @@ /* * pata_cmd640.c - CMD640 PCI PATA for new ATA layer * (C) 2007 Red Hat Inc - * Alan Cox * * Based upon * linux/drivers/ide/pci/cmd640.c Version 1.02 Sep 01, 1996 diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c index ddd09b7d98c9..3167d8fed2f2 100644 --- a/drivers/ata/pata_cmd64x.c +++ b/drivers/ata/pata_cmd64x.c @@ -1,7 +1,7 @@ /* * pata_cmd64x.c - CMD64x PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox + * Alan Cox * * Based upon * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c index 0c4b271a9d5a..bba453381f44 100644 --- a/drivers/ata/pata_cs5530.c +++ b/drivers/ata/pata_cs5530.c @@ -1,7 +1,6 @@ /* * pata-cs5530.c - CS5530 PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * based upon cs5530.c by Mark Lord. * diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c index f1b6556f0483..8b236af84c2e 100644 --- a/drivers/ata/pata_cs5535.c +++ b/drivers/ata/pata_cs5535.c @@ -1,7 +1,7 @@ /* * pata-cs5535.c - CS5535 PATA for new ATA layer * (C) 2005-2006 Red Hat Inc - * Alan Cox + * Alan Cox * * based upon cs5535.c from AMD as cleaned up and * made readable and Linux style by Wolfgang Zuleger + * Alan Cox * * Based heavily on * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002 diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c index 9fba82976ba6..ac6392ea35b0 100644 --- a/drivers/ata/pata_efar.c +++ b/drivers/ata/pata_efar.c @@ -1,7 +1,7 @@ /* * pata_efar.c - EFAR PIIX clone controller driver * - * (C) 2005 Red Hat + * (C) 2005 Red Hat * * Some parts based on ata_piix.c by Jeff Garzik and others. * diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c index f2b83eabc7c7..e0c4f05d7d57 100644 --- a/drivers/ata/pata_hpt366.c +++ b/drivers/ata/pata_hpt366.c @@ -183,7 +183,9 @@ static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask) mask &= ~(0xF8 << ATA_SHIFT_UDMA); if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4)) mask &= ~(0xF0 << ATA_SHIFT_UDMA); - } + } else if (adev->class == ATA_DEV_ATAPI) + mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); + return ata_bmdma_mode_filter(adev, mask); } @@ -211,11 +213,15 @@ static u32 hpt36x_find_mode(struct ata_port *ap, int speed) static int hpt36x_cable_detect(struct ata_port *ap) { - u8 ata66; struct pci_dev *pdev = to_pci_dev(ap->host->dev); + u8 ata66; + /* + * Each channel of pata_hpt366 occupies separate PCI function + * as the primary channel and bit1 indicates the cable type. + */ pci_read_config_byte(pdev, 0x5A, &ata66); - if (ata66 & (1 << ap->port_no)) + if (ata66 & 2) return ATA_CBL_PATA40; return ATA_CBL_PATA80; } @@ -382,10 +388,10 @@ static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id) /* PCI clocking determines the ATA timing values to use */ /* info_hpt366 is safe against re-entry so we can scribble on it */ switch((reg1 & 0x700) >> 8) { - case 5: + case 9: hpriv = &hpt366_40; break; - case 9: + case 5: hpriv = &hpt366_25; break; default: diff --git a/drivers/ata/pata_isapnp.c b/drivers/ata/pata_isapnp.c index 6a111baab523..15cdb9148aab 100644 --- a/drivers/ata/pata_isapnp.c +++ b/drivers/ata/pata_isapnp.c @@ -1,7 +1,7 @@ /* * pata-isapnp.c - ISA PnP PATA controller driver. - * Copyright 2005/2006 Red Hat Inc , all rights reserved. + * Copyright 2005/2006 Red Hat Inc, all rights reserved. * * Based in part on ide-pnp.c by Andrey Panin */ diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c index 0221c9a46769..860ede526282 100644 --- a/drivers/ata/pata_it821x.c +++ b/drivers/ata/pata_it821x.c @@ -1,7 +1,7 @@ /* * pata_it821x.c - IT821x PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox + * Alan Cox * (C) 2007 Bartlomiej Zolnierkiewicz * * based upon @@ -10,7 +10,7 @@ * * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 * - * Copyright (C) 2004 Red Hat + * Copyright (C) 2004 Red Hat * * May be copied or modified under the terms of the GNU General Public License * Based in part on the ITE vendor provided SCSI driver. @@ -557,9 +557,8 @@ static unsigned int it821x_read_id(struct ata_device *adev, if (strstr(model_num, "Integrated Technology Express")) { /* Set feature bits the firmware neglects */ id[49] |= 0x0300; /* LBA, DMA */ - id[82] |= 0x0400; /* LBA48 */ id[83] &= 0x7FFF; - id[83] |= 0x4000; /* Word 83 is valid */ + id[83] |= 0x4400; /* Word 83 is valid and LBA48 */ id[86] |= 0x0400; /* LBA48 on */ id[ATA_ID_MAJOR_VER] |= 0x1F; } diff --git a/drivers/ata/pata_jmicron.c b/drivers/ata/pata_jmicron.c index 73b7596816b4..38cf1ab2d289 100644 --- a/drivers/ata/pata_jmicron.c +++ b/drivers/ata/pata_jmicron.c @@ -4,7 +4,7 @@ * driven by AHCI in the usual configuration although * this driver can handle other setups if we need it. * - * (c) 2006 Red Hat + * (c) 2006 Red Hat */ #include diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c index bc037ffce200..930c2208640b 100644 --- a/drivers/ata/pata_legacy.c +++ b/drivers/ata/pata_legacy.c @@ -1,6 +1,6 @@ /* * pata-legacy.c - Legacy port PATA/SATA controller driver. - * Copyright 2005/2006 Red Hat , all rights reserved. + * Copyright 2005/2006 Red Hat, all rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/ata/pata_marvell.c b/drivers/ata/pata_marvell.c index 0d87eec84966..76e399bf8c1b 100644 --- a/drivers/ata/pata_marvell.c +++ b/drivers/ata/pata_marvell.c @@ -5,7 +5,7 @@ * isn't making full use of the device functionality but it is * easy to get working. * - * (c) 2006 Red Hat + * (c) 2006 Red Hat */ #include diff --git a/drivers/ata/pata_mpiix.c b/drivers/ata/pata_mpiix.c index 7d7e3fdab71f..7c8faa48b5f3 100644 --- a/drivers/ata/pata_mpiix.c +++ b/drivers/ata/pata_mpiix.c @@ -1,7 +1,7 @@ /* * pata_mpiix.c - Intel MPIIX PATA for new ATA layer * (C) 2005-2006 Red Hat Inc - * Alan Cox + * Alan Cox * * The MPIIX is different enough to the PIIX4 and friends that we give it * a separate driver. The old ide/pci code handles this by just not tuning diff --git a/drivers/ata/pata_netcell.c b/drivers/ata/pata_netcell.c index d9719c8b9dbe..9dc05e1656a8 100644 --- a/drivers/ata/pata_netcell.c +++ b/drivers/ata/pata_netcell.c @@ -1,7 +1,7 @@ /* * pata_netcell.c - Netcell PATA driver * - * (c) 2006 Red Hat + * (c) 2006 Red Hat */ #include diff --git a/drivers/ata/pata_ninja32.c b/drivers/ata/pata_ninja32.c index 565e67cd13fa..4dd9a3b031e4 100644 --- a/drivers/ata/pata_ninja32.c +++ b/drivers/ata/pata_ninja32.c @@ -1,7 +1,6 @@ /* * pata_ninja32.c - Ninja32 PATA for new ATA layer * (C) 2007 Red Hat Inc - * Alan Cox * * Note: The controller like many controllers has shared timings for * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back @@ -45,7 +44,7 @@ #include #define DRV_NAME "pata_ninja32" -#define DRV_VERSION "0.0.1" +#define DRV_VERSION "0.1.3" /** @@ -89,6 +88,17 @@ static struct ata_port_operations ninja32_port_ops = { .set_piomode = ninja32_set_piomode, }; +static void ninja32_program(void __iomem *base) +{ + iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ + iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */ + iowrite8(0x01, base + 0x03); /* Unknown */ + iowrite8(0x20, base + 0x04); /* WAIT0 */ + iowrite8(0x8f, base + 0x05); /* Unknown */ + iowrite8(0xa4, base + 0x1c); /* Unknown */ + iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */ +} + static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) { struct ata_host *host; @@ -120,7 +130,8 @@ static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) return rc; pci_set_master(dev); - /* Set up the register mappings */ + /* Set up the register mappings. We use the I/O mapping as only the + older chips also have MMIO on BAR 1 */ base = host->iomap[0]; if (!base) return -ENOMEM; @@ -134,21 +145,35 @@ static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) ap->ioaddr.bmdma_addr = base; ata_sff_std_ports(&ap->ioaddr); - iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ - iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */ - iowrite8(0x01, base + 0x03); /* Unknown */ - iowrite8(0x20, base + 0x04); /* WAIT0 */ - iowrite8(0x8f, base + 0x05); /* Unknown */ - iowrite8(0xa4, base + 0x1c); /* Unknown */ - iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */ + ninja32_program(base); /* FIXME: Should we disable them at remove ? */ return ata_host_activate(host, dev->irq, ata_sff_interrupt, IRQF_SHARED, &ninja32_sht); } +#ifdef CONFIG_PM + +static int ninja32_reinit_one(struct pci_dev *pdev) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + int rc; + + rc = ata_pci_device_do_resume(pdev); + if (rc) + return rc; + ninja32_program(host->iomap[0]); + ata_host_resume(host); + return 0; +} +#endif + static const struct pci_device_id ninja32[] = { + { 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { }, }; @@ -156,7 +181,11 @@ static struct pci_driver ninja32_pci_driver = { .name = DRV_NAME, .id_table = ninja32, .probe = ninja32_init_one, - .remove = ata_pci_remove_one + .remove = ata_pci_remove_one, +#ifdef CONFIG_PM + .suspend = ata_pci_device_suspend, + .resume = ninja32_reinit_one, +#endif }; static int __init ninja32_init(void) diff --git a/drivers/ata/pata_ns87410.c b/drivers/ata/pata_ns87410.c index be756b7ef07e..40d411c460de 100644 --- a/drivers/ata/pata_ns87410.c +++ b/drivers/ata/pata_ns87410.c @@ -1,7 +1,6 @@ /* * pata_ns87410.c - National Semiconductor 87410 PATA for new ATA layer * (C) 2006 Red Hat Inc - * Alan Cox * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/ata/pata_ns87415.c b/drivers/ata/pata_ns87415.c index e0aa7eaaee0a..89bf5f865d6a 100644 --- a/drivers/ata/pata_ns87415.c +++ b/drivers/ata/pata_ns87415.c @@ -1,7 +1,7 @@ /* * pata_ns87415.c - NS87415 (non PARISC) PATA * - * (C) 2005 Red Hat + * (C) 2005 Red Hat * * This is a fairly generic MWDMA controller. It has some limitations * as it requires timing reloads on PIO/DMA transitions but it is otherwise diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c index df64f2443001..c0dbc46a348e 100644 --- a/drivers/ata/pata_oldpiix.c +++ b/drivers/ata/pata_oldpiix.c @@ -1,7 +1,7 @@ /* * pata_oldpiix.c - Intel PATA/SATA controllers * - * (C) 2005 Red Hat + * (C) 2005 Red Hat * * Some parts based on ata_piix.c by Jeff Garzik and others. * diff --git a/drivers/ata/pata_opti.c b/drivers/ata/pata_opti.c index fb2cf661b0e8..e4fa4d565e96 100644 --- a/drivers/ata/pata_opti.c +++ b/drivers/ata/pata_opti.c @@ -1,7 +1,6 @@ /* * pata_opti.c - ATI PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * Based on * linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002 diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c index 4cd744456313..93bb6e91973f 100644 --- a/drivers/ata/pata_optidma.c +++ b/drivers/ata/pata_optidma.c @@ -1,7 +1,6 @@ /* * pata_optidma.c - Opti DMA PATA for new ATA layer * (C) 2006 Red Hat Inc - * Alan Cox * * The Opti DMA controllers are related to the older PIO PCI controllers * and indeed the VLB ones. The main differences are that the timing diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c index 02b596b9cf6a..64b2e2281ee7 100644 --- a/drivers/ata/pata_pcmcia.c +++ b/drivers/ata/pata_pcmcia.c @@ -1,6 +1,6 @@ /* * pata_pcmcia.c - PCMCIA PATA controller driver. - * Copyright 2005-2006 Red Hat Inc , all rights reserved. + * Copyright 2005-2006 Red Hat Inc, all rights reserved. * PCMCIA ident update Copyright 2006 Marcin Juszkiewicz * * @@ -416,6 +416,7 @@ static struct pcmcia_device_id pcmcia_devices[] = { PCMCIA_DEVICE_PROD_ID1("STI Flash", 0xe4a13209), PCMCIA_DEVICE_PROD_ID12("STI", "Flash 5.0", 0xbf2df18d, 0x8cb57a0e), PCMCIA_MFC_DEVICE_PROD_ID12(1, "SanDisk", "ConnectPlus", 0x7a954bd9, 0x74be00c6), + PCMCIA_DEVICE_PROD_ID2("Flash Card", 0x5a362506), PCMCIA_DEVICE_NULL, }; diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c index d2673060bc8d..799a6a098712 100644 --- a/drivers/ata/pata_pdc202xx_old.c +++ b/drivers/ata/pata_pdc202xx_old.c @@ -1,7 +1,7 @@ /* * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox + * Alan Cox * (C) 2007 Bartlomiej Zolnierkiewicz * * Based in part on linux/drivers/ide/pci/pdc202xx_old.c diff --git a/drivers/ata/pata_platform.c b/drivers/ata/pata_platform.c index 8f65ad61b8af..77e4e3b17f54 100644 --- a/drivers/ata/pata_platform.c +++ b/drivers/ata/pata_platform.c @@ -5,7 +5,7 @@ * * Based on pata_pcmcia: * - * Copyright 2005-2006 Red Hat Inc , all rights reserved. + * Copyright 2005-2006 Red Hat Inc, all rights reserved. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/drivers/ata/pata_qdi.c b/drivers/ata/pata_qdi.c index 63b7a1c165a5..3080f371222c 100644 --- a/drivers/ata/pata_qdi.c +++ b/drivers/ata/pata_qdi.c @@ -1,6 +1,6 @@ /* * pata_qdi.c - QDI VLB ATA controllers - * (C) 2006 Red Hat + * (C) 2006 Red Hat * * This driver mostly exists as a proof of concept for non PCI devices under * libata. While the QDI6580 was 'neat' in 1993 it is no longer terribly diff --git a/drivers/ata/pata_radisys.c b/drivers/ata/pata_radisys.c index 1c0d9fa7ee54..0b0aa452de14 100644 --- a/drivers/ata/pata_radisys.c +++ b/drivers/ata/pata_radisys.c @@ -1,7 +1,7 @@ /* * pata_radisys.c - Intel PATA/SATA controllers * - * (C) 2006 Red Hat + * (C) 2006 Red Hat * * Some parts based on ata_piix.c by Jeff Garzik and others. * diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c index f8b3ffc8ae9e..c2e6fb9f2ef9 100644 --- a/drivers/ata/pata_rb532_cf.c +++ b/drivers/ata/pata_rb532_cf.c @@ -39,9 +39,11 @@ #define RB500_CF_MAXPORTS 1 #define RB500_CF_IO_DELAY 400 -#define RB500_CF_REG_CMD 0x0800 +#define RB500_CF_REG_BASE 0x0800 +#define RB500_CF_REG_ERR 0x080D #define RB500_CF_REG_CTRL 0x080E -#define RB500_CF_REG_DATA 0x0C00 +/* 32bit buffered data register offset */ +#define RB500_CF_REG_DBUF32 0x0C00 struct rb532_cf_info { void __iomem *iobase; @@ -72,11 +74,12 @@ static void rb532_pata_exec_command(struct ata_port *ap, rb532_pata_finish_io(ap); } -static void rb532_pata_data_xfer(struct ata_device *adev, unsigned char *buf, +static unsigned int rb532_pata_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) { struct ata_port *ap = adev->link->ap; void __iomem *ioaddr = ap->ioaddr.data_addr; + int retlen = buflen; if (write_data) { for (; buflen > 0; buflen--, buf++) @@ -87,6 +90,7 @@ static void rb532_pata_data_xfer(struct ata_device *adev, unsigned char *buf, } rb532_pata_finish_io(adev->link->ap); + return retlen; } static void rb532_pata_freeze(struct ata_port *ap) @@ -146,13 +150,14 @@ static void rb532_pata_setup_ports(struct ata_host *ah) ap->pio_mask = 0x1f; /* PIO4 */ ap->flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO; - ap->ioaddr.cmd_addr = info->iobase + RB500_CF_REG_CMD; + ap->ioaddr.cmd_addr = info->iobase + RB500_CF_REG_BASE; ap->ioaddr.ctl_addr = info->iobase + RB500_CF_REG_CTRL; ap->ioaddr.altstatus_addr = info->iobase + RB500_CF_REG_CTRL; ata_sff_std_ports(&ap->ioaddr); - ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DATA; + ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DBUF32; + ap->ioaddr.error_addr = info->iobase + RB500_CF_REG_ERR; } static __devinit int rb532_pata_driver_probe(struct platform_device *pdev) diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c index 0278fd2b8fb1..9a4bdca54616 100644 --- a/drivers/ata/pata_sc1200.c +++ b/drivers/ata/pata_sc1200.c @@ -1,5 +1,5 @@ /* - * New ATA layer SC1200 driver Alan Cox + * New ATA layer SC1200 driver Alan Cox * * TODO: Mode selection filtering * TODO: Can't enable second channel until ATA core has serialize diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c index 16673d168573..cf3707e516a2 100644 --- a/drivers/ata/pata_scc.c +++ b/drivers/ata/pata_scc.c @@ -8,7 +8,7 @@ * Copyright 2003-2005 Jeff Garzik * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer * Copyright (C) 1998-2000 Andre Hedrick - * Copyright (C) 2003 Red Hat Inc + * Copyright (C) 2003 Red Hat Inc * * and drivers/ata/ahci.c: * Copyright 2004-2005 Red Hat, Inc. diff --git a/drivers/ata/pata_sch.c b/drivers/ata/pata_sch.c index c8cc027789fe..6aeeeeb34124 100644 --- a/drivers/ata/pata_sch.c +++ b/drivers/ata/pata_sch.c @@ -83,7 +83,7 @@ static struct ata_port_operations sch_pata_ops = { }; static struct ata_port_info sch_port_info = { - .flags = 0, + .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, /* pio0-4 */ .mwdma_mask = ATA_MWDMA2, /* mwdma0-2 */ .udma_mask = ATA_UDMA5, /* udma0-5 */ diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c index ffd26d0dc50d..72e41c9f969b 100644 --- a/drivers/ata/pata_serverworks.c +++ b/drivers/ata/pata_serverworks.c @@ -1,7 +1,6 @@ /* * pata_serverworks.c - Serverworks PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * based upon * diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c index a598bb36aafc..83580a59db58 100644 --- a/drivers/ata/pata_sil680.c +++ b/drivers/ata/pata_sil680.c @@ -1,7 +1,6 @@ /* * pata_sil680.c - SIL680 PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * based upon * diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c index 26345d7b531c..e4be55e047f6 100644 --- a/drivers/ata/pata_sis.c +++ b/drivers/ata/pata_sis.c @@ -1,7 +1,7 @@ /* * pata_sis.c - SiS ATA driver * - * (C) 2005 Red Hat + * (C) 2005 Red Hat * (C) 2007 Bartlomiej Zolnierkiewicz * * Based upon linux/drivers/ide/pci/sis5513.c @@ -56,7 +56,6 @@ static const struct sis_laptop sis_laptop[] = { { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ - { 0x5513, 0x1039, 0x5513 }, /* Targa Visionary 1000 */ /* end marker */ { 0, } }; diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c index 69877bd81815..1b0e7b6d8ef5 100644 --- a/drivers/ata/pata_sl82c105.c +++ b/drivers/ata/pata_sl82c105.c @@ -1,7 +1,6 @@ /* * pata_sl82c105.c - SL82C105 PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox * * Based in part on linux/drivers/ide/pci/sl82c105.c * SL82C105/Winbond 553 IDE driver diff --git a/drivers/ata/pata_triflex.c b/drivers/ata/pata_triflex.c index b181261f2743..ef9597517cdd 100644 --- a/drivers/ata/pata_triflex.c +++ b/drivers/ata/pata_triflex.c @@ -1,7 +1,7 @@ /* * pata_triflex.c - Compaq PATA for new ATA layer * (C) 2005 Red Hat Inc - * Alan Cox + * Alan Cox * * based upon * diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c index 8fdb2ce73210..681169c9c640 100644 --- a/drivers/ata/pata_via.c +++ b/drivers/ata/pata_via.c @@ -1,7 +1,6 @@ /* * pata_via.c - VIA PATA for new ATA layer * (C) 2005-2006 Red Hat Inc - * Alan Cox * * Documentation * Most chipset documentation available under NDA only diff --git a/drivers/ata/pata_winbond.c b/drivers/ata/pata_winbond.c index a7606b044a61..319e164a3d74 100644 --- a/drivers/ata/pata_winbond.c +++ b/drivers/ata/pata_winbond.c @@ -1,6 +1,6 @@ /* * pata_winbond.c - Winbond VLB ATA controllers - * (C) 2006 Red Hat + * (C) 2006 Red Hat * * Support for the Winbond 83759A when operating in advanced mode. * Multichip mode is not currently supported. diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index fae3841de0d8..6f1460614325 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c @@ -307,10 +307,10 @@ static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); static void nv_nf2_freeze(struct ata_port *ap); static void nv_nf2_thaw(struct ata_port *ap); +static int nv_nf2_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline); static void nv_ck804_freeze(struct ata_port *ap); static void nv_ck804_thaw(struct ata_port *ap); -static int nv_hardreset(struct ata_link *link, unsigned int *class, - unsigned long deadline); static int nv_adma_slave_config(struct scsi_device *sdev); static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc); static void nv_adma_qc_prep(struct ata_queued_cmd *qc); @@ -405,17 +405,8 @@ static struct scsi_host_template nv_swncq_sht = { .slave_configure = nv_swncq_slave_config, }; -/* OSDL bz3352 reports that some nv controllers can't determine device - * signature reliably and nv_hardreset is implemented to work around - * the problem. This was reported on nf3 and it's unclear whether any - * other controllers are affected. However, the workaround has been - * applied to all variants and there isn't much to gain by trying to - * find out exactly which ones are affected at this point especially - * because NV has moved over to ahci for newer controllers. - */ static struct ata_port_operations nv_common_ops = { .inherits = &ata_bmdma_port_ops, - .hardreset = nv_hardreset, .scr_read = nv_scr_read, .scr_write = nv_scr_write, }; @@ -429,12 +420,22 @@ static struct ata_port_operations nv_generic_ops = { .hardreset = ATA_OP_NULL, }; +/* OSDL bz3352 reports that nf2/3 controllers can't determine device + * signature reliably. Also, the following thread reports detection + * failure on cold boot with the standard debouncing timing. + * + * http://thread.gmane.org/gmane.linux.ide/34098 + * + * Debounce with hotplug timing and request follow-up SRST. + */ static struct ata_port_operations nv_nf2_ops = { .inherits = &nv_common_ops, .freeze = nv_nf2_freeze, .thaw = nv_nf2_thaw, + .hardreset = nv_nf2_hardreset, }; +/* CK804 finally gets hardreset right */ static struct ata_port_operations nv_ck804_ops = { .inherits = &nv_common_ops, .freeze = nv_ck804_freeze, @@ -443,7 +444,7 @@ static struct ata_port_operations nv_ck804_ops = { }; static struct ata_port_operations nv_adma_ops = { - .inherits = &nv_common_ops, + .inherits = &nv_ck804_ops, .check_atapi_dma = nv_adma_check_atapi_dma, .sff_tf_read = nv_adma_tf_read, @@ -467,7 +468,7 @@ static struct ata_port_operations nv_adma_ops = { }; static struct ata_port_operations nv_swncq_ops = { - .inherits = &nv_common_ops, + .inherits = &nv_generic_ops, .qc_defer = ata_std_qc_defer, .qc_prep = nv_swncq_qc_prep, @@ -1553,6 +1554,17 @@ static void nv_nf2_thaw(struct ata_port *ap) iowrite8(mask, scr_addr + NV_INT_ENABLE); } +static int nv_nf2_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline) +{ + bool online; + int rc; + + rc = sata_link_hardreset(link, sata_deb_timing_hotplug, deadline, + &online, NULL); + return online ? -EAGAIN : rc; +} + static void nv_ck804_freeze(struct ata_port *ap) { void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; @@ -1605,21 +1617,6 @@ static void nv_mcp55_thaw(struct ata_port *ap) ata_sff_thaw(ap); } -static int nv_hardreset(struct ata_link *link, unsigned int *class, - unsigned long deadline) -{ - int rc; - - /* SATA hardreset fails to retrieve proper device signature on - * some controllers. Request follow up SRST. For more info, - * see http://bugzilla.kernel.org/show_bug.cgi?id=3352 - */ - rc = sata_sff_hardreset(link, class, deadline); - if (rc) - return rc; - return -EAGAIN; -} - static void nv_adma_error_handler(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c index 750d8cdc00cd..ba9a2570a742 100644 --- a/drivers/ata/sata_promise.c +++ b/drivers/ata/sata_promise.c @@ -153,6 +153,10 @@ static void pdc_freeze(struct ata_port *ap); static void pdc_sata_freeze(struct ata_port *ap); static void pdc_thaw(struct ata_port *ap); static void pdc_sata_thaw(struct ata_port *ap); +static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, + unsigned long deadline); +static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline); static void pdc_error_handler(struct ata_port *ap); static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); static int pdc_pata_cable_detect(struct ata_port *ap); @@ -186,6 +190,7 @@ static struct ata_port_operations pdc_sata_ops = { .scr_read = pdc_sata_scr_read, .scr_write = pdc_sata_scr_write, .port_start = pdc_sata_port_start, + .hardreset = pdc_sata_hardreset, }; /* First-generation chips need a more restrictive ->check_atapi_dma op */ @@ -200,6 +205,7 @@ static struct ata_port_operations pdc_pata_ops = { .freeze = pdc_freeze, .thaw = pdc_thaw, .port_start = pdc_common_port_start, + .softreset = pdc_pata_softreset, }; static const struct ata_port_info pdc_port_info[] = { @@ -693,6 +699,20 @@ static void pdc_sata_thaw(struct ata_port *ap) readl(host_mmio + hotplug_offset); /* flush */ } +static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, + unsigned long deadline) +{ + pdc_reset_port(link->ap); + return ata_sff_softreset(link, class, deadline); +} + +static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline) +{ + pdc_reset_port(link->ap); + return sata_sff_hardreset(link, class, deadline); +} + static void pdc_error_handler(struct ata_port *ap) { if (!(ap->pflags & ATA_PFLAG_FROZEN)) diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index 4621807a1a6a..ccee930f1e12 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c @@ -1329,6 +1329,11 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) } } + /* Set max read request size to 4096. This slightly increases + * write throughput for pci-e variants. + */ + pcie_set_readrq(pdev, 4096); + sil24_init_controller(host); pci_set_master(pdev); diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c index 5b72e734300a..c18935f0bda2 100644 --- a/drivers/ata/sata_via.c +++ b/drivers/ata/sata_via.c @@ -44,11 +44,16 @@ #include #define DRV_NAME "sata_via" -#define DRV_VERSION "2.3" +#define DRV_VERSION "2.4" +/* + * vt8251 is different from other sata controllers of VIA. It has two + * channels, each channel has both Master and Slave slot. + */ enum board_ids_enum { vt6420, vt6421, + vt8251, }; enum { @@ -70,6 +75,8 @@ enum { static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); +static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val); +static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val); static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); static void svia_noop_freeze(struct ata_port *ap); static int vt6420_prereset(struct ata_link *link, unsigned long deadline); @@ -79,12 +86,12 @@ static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev); static const struct pci_device_id svia_pci_tbl[] = { { PCI_VDEVICE(VIA, 0x5337), vt6420 }, - { PCI_VDEVICE(VIA, 0x0591), vt6420 }, - { PCI_VDEVICE(VIA, 0x3149), vt6420 }, - { PCI_VDEVICE(VIA, 0x3249), vt6421 }, - { PCI_VDEVICE(VIA, 0x5287), vt6420 }, + { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */ + { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */ + { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */ { PCI_VDEVICE(VIA, 0x5372), vt6420 }, { PCI_VDEVICE(VIA, 0x7372), vt6420 }, + { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */ { } /* terminate list */ }; @@ -128,6 +135,13 @@ static struct ata_port_operations vt6421_sata_ops = { .scr_write = svia_scr_write, }; +static struct ata_port_operations vt8251_ops = { + .inherits = &svia_base_ops, + .hardreset = sata_std_hardreset, + .scr_read = vt8251_scr_read, + .scr_write = vt8251_scr_write, +}; + static const struct ata_port_info vt6420_port_info = { .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, .pio_mask = 0x1f, @@ -152,6 +166,15 @@ static struct ata_port_info vt6421_pport_info = { .port_ops = &vt6421_pata_ops, }; +static struct ata_port_info vt8251_port_info = { + .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS | + ATA_FLAG_NO_LEGACY, + .pio_mask = 0x1f, + .mwdma_mask = 0x07, + .udma_mask = ATA_UDMA6, + .port_ops = &vt8251_ops, +}; + MODULE_AUTHOR("Jeff Garzik"); MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers"); MODULE_LICENSE("GPL"); @@ -174,6 +197,83 @@ static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) return 0; } +static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val) +{ + static const u8 ipm_tbl[] = { 1, 2, 6, 0 }; + struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); + int slot = 2 * link->ap->port_no + link->pmp; + u32 v = 0; + u8 raw; + + switch (scr) { + case SCR_STATUS: + pci_read_config_byte(pdev, 0xA0 + slot, &raw); + + /* read the DET field, bit0 and 1 of the config byte */ + v |= raw & 0x03; + + /* read the SPD field, bit4 of the configure byte */ + if (raw & (1 << 4)) + v |= 0x02 << 4; + else + v |= 0x01 << 4; + + /* read the IPM field, bit2 and 3 of the config byte */ + v |= ipm_tbl[(raw >> 2) & 0x3]; + break; + + case SCR_ERROR: + /* devices other than 5287 uses 0xA8 as base */ + WARN_ON(pdev->device != 0x5287); + pci_read_config_dword(pdev, 0xB0 + slot * 4, &v); + break; + + case SCR_CONTROL: + pci_read_config_byte(pdev, 0xA4 + slot, &raw); + + /* read the DET field, bit0 and bit1 */ + v |= ((raw & 0x02) << 1) | (raw & 0x01); + + /* read the IPM field, bit2 and bit3 */ + v |= ((raw >> 2) & 0x03) << 8; + break; + + default: + return -EINVAL; + } + + *val = v; + return 0; +} + +static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val) +{ + struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); + int slot = 2 * link->ap->port_no + link->pmp; + u32 v = 0; + + switch (scr) { + case SCR_ERROR: + /* devices other than 5287 uses 0xA8 as base */ + WARN_ON(pdev->device != 0x5287); + pci_write_config_dword(pdev, 0xB0 + slot * 4, val); + return 0; + + case SCR_CONTROL: + /* set the DET field */ + v |= ((val & 0x4) >> 1) | (val & 0x1); + + /* set the IPM field */ + v |= ((val >> 8) & 0x3) << 2; + + pci_write_config_byte(pdev, 0xA4 + slot, v); + return 0; + + default: + return -EINVAL; + } +} + /** * svia_tf_load - send taskfile registers to host controller * @ap: Port to which output is sent @@ -396,6 +496,30 @@ static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) return 0; } +static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) +{ + const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL }; + struct ata_host *host; + int i, rc; + + rc = ata_pci_sff_prepare_host(pdev, ppi, &host); + if (rc) + return rc; + *r_host = host; + + rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); + if (rc) { + dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n"); + return rc; + } + + /* 8251 hosts four sata ports as M/S of the two channels */ + for (i = 0; i < host->n_ports; i++) + ata_slave_link_init(host->ports[i]); + + return 0; +} + static void svia_configure(struct pci_dev *pdev) { u8 tmp8; @@ -451,10 +575,10 @@ static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if (rc) return rc; - if (board_id == vt6420) - bar_sizes = &svia_bar_sizes[0]; - else + if (board_id == vt6421) bar_sizes = &vt6421_bar_sizes[0]; + else + bar_sizes = &svia_bar_sizes[0]; for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++) if ((pci_resource_start(pdev, i) == 0) || @@ -467,10 +591,19 @@ static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) return -ENODEV; } - if (board_id == vt6420) + switch (board_id) { + case vt6420: rc = vt6420_prepare_host(pdev, &host); - else + break; + case vt6421: rc = vt6421_prepare_host(pdev, &host); + break; + case vt8251: + rc = vt8251_prepare_host(pdev, &host); + break; + default: + rc = -EINVAL; + } if (rc) return rc; diff --git a/drivers/atm/horizon.c b/drivers/atm/horizon.c index 615412364e99..6b969f8c684f 100644 --- a/drivers/atm/horizon.c +++ b/drivers/atm/horizon.c @@ -2705,7 +2705,7 @@ static int __devinit hrz_probe(struct pci_dev *pci_dev, const struct pci_device_ /* XXX DEV_LABEL is a guess */ if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) { - return -EINVAL; + err = -EINVAL; goto out_disable; } diff --git a/drivers/base/sys.c b/drivers/base/sys.c index 75dd6e22faff..c98c31ec2f75 100644 --- a/drivers/base/sys.c +++ b/drivers/base/sys.c @@ -355,7 +355,7 @@ static void __sysdev_resume(struct sys_device *dev) * sysdev_suspend - Suspend all system devices. * @state: Power state to enter. * - * We perform an almost identical operation as sys_device_shutdown() + * We perform an almost identical operation as sysdev_shutdown() * above, though calling ->suspend() instead. Interrupts are disabled * when this called. Devices are responsible for both saving state and * quiescing or powering down the device. @@ -437,7 +437,7 @@ aux_driver: /** * sysdev_resume - Bring system devices back to life. * - * Similar to sys_device_suspend(), but we iterate the list forwards + * Similar to sysdev_suspend(), but we iterate the list forwards * to guarantee that parent devices are resumed before their children. * * Note: Interrupts are disabled when called. @@ -488,7 +488,8 @@ ssize_t sysdev_store_ulong(struct sys_device *sysdev, if (end == buf) return -EINVAL; *(unsigned long *)(ea->var) = new; - return end - buf; + /* Always return full write size even if we didn't consume all */ + return size; } EXPORT_SYMBOL_GPL(sysdev_store_ulong); @@ -511,7 +512,8 @@ ssize_t sysdev_store_int(struct sys_device *sysdev, if (end == buf || new > INT_MAX || new < INT_MIN) return -EINVAL; *(int *)(ea->var) = new; - return end - buf; + /* Always return full write size even if we didn't consume all */ + return size; } EXPORT_SYMBOL_GPL(sysdev_store_int); diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 61ad8d639ba3..0344a8a8321d 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -21,7 +21,8 @@ config BLK_DEV_FD ---help--- If you want to use the floppy disk drive(s) of your PC under Linux, say Y. Information about this driver, especially important for IBM - Thinkpad users, is contained in . + Thinkpad users, is contained in + . That file also contains the location of the Floppy driver FAQ as well as location of the fdutils package used to configure additional parameters of the driver at run time. @@ -76,7 +77,7 @@ config PARIDE your computer's parallel port. Most of them are actually IDE devices using a parallel port IDE adapter. This option enables the PARIDE subsystem which contains drivers for many of these external drives. - Read for more information. + Read for more information. If you have said Y to the "Parallel-port support" configuration option, you may share a single port between your printer and other @@ -114,9 +115,9 @@ config BLK_CPQ_DA help This is the driver for Compaq Smart Array controllers. Everyone using these boards should say Y here. See the file - for the current list of boards - supported by this driver, and for further information on the use of - this driver. + for the current list of + boards supported by this driver, and for further information on the + use of this driver. config BLK_CPQ_CISS_DA tristate "Compaq Smart Array 5xxx support" @@ -124,7 +125,7 @@ config BLK_CPQ_CISS_DA help This is the driver for Compaq Smart Array 5xxx controllers. Everyone using these boards should say Y here. - See for the current list of + See for the current list of boards supported by this driver, and for further information on the use of this driver. @@ -135,7 +136,7 @@ config CISS_SCSI_TAPE help When enabled (Y), this option allows SCSI tape drives and SCSI medium changers (tape robots) to be accessed via a Compaq 5xxx array - controller. (See for more details.) + controller. (See for more details.) "SCSI support" and "SCSI tape support" must also be enabled for this option to work. @@ -149,8 +150,8 @@ config BLK_DEV_DAC960 help This driver adds support for the Mylex DAC960, AcceleRAID, and eXtremeRAID PCI RAID controllers. See the file - for further information about - this driver. + for further information + about this driver. To compile this driver as a module, choose M here: the module will be called DAC960. @@ -278,9 +279,9 @@ config BLK_DEV_NBD userland (making server and client physically the same computer, communicating using the loopback network device). - Read for more information, especially - about where to find the server code, which runs in user space and - does not need special kernel support. + Read for more information, + especially about where to find the server code, which runs in user + space and does not need special kernel support. Note that this has nothing to do with the network file systems NFS or Coda; you can say N here even if you intend to use NFS or Coda. @@ -321,8 +322,8 @@ config BLK_DEV_RAM store a copy of a minimal root file system off of a floppy into RAM during the initial install of Linux. - Note that the kernel command line option "ramdisk=XX" is now - obsolete. For details, read . + Note that the kernel command line option "ramdisk=XX" is now obsolete. + For details, read . To compile this driver as a module, choose M here: the module will be called rd. diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 4023885353e0..9f7c543cc04b 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -96,6 +96,8 @@ static const struct pci_device_id cciss_pci_device_id[] = { {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, + {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, + {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, {0,} @@ -133,6 +135,8 @@ static struct board_type products[] = { {0x3245103C, "Smart Array P410i", &SA5_access}, {0x3247103C, "Smart Array P411", &SA5_access}, {0x3249103C, "Smart Array P812", &SA5_access}, + {0x324A103C, "Smart Array P712m", &SA5_access}, + {0x324B103C, "Smart Array P711m", &SA5_access}, {0xFFFF103C, "Unknown Smart Array", &SA5_access}, }; @@ -1366,6 +1370,7 @@ static void cciss_add_disk(ctlr_info_t *h, struct gendisk *disk, disk->first_minor = drv_index << NWD_SHIFT; disk->fops = &cciss_fops; disk->private_data = &h->drv[drv_index]; + disk->driverfs_dev = &h->pdev->dev; /* Set up queue information */ blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask); @@ -1688,6 +1693,11 @@ static int rebuild_lun_table(ctlr_info_t *h, int first_time) for (i = 0; i <= h->highest_lun; i++) { int j; drv_found = 0; + + /* skip holes in the array from already deleted drives */ + if (h->drv[i].raid_level == -1) + continue; + for (j = 0; j < num_luns; j++) { memcpy(&lunid, &ld_buff->LUN[j][0], 4); lunid = le32_to_cpu(lunid); @@ -2842,7 +2852,7 @@ static void do_cciss_request(struct request_queue *q) h->maxSG = seg; #ifdef CCISS_DEBUG - printk(KERN_DEBUG "cciss: Submitting %d sectors in %d segments\n", + printk(KERN_DEBUG "cciss: Submitting %lu sectors in %d segments\n", creq->nr_sectors, seg); #endif /* CCISS_DEBUG */ @@ -3192,7 +3202,7 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev) c->paddr = pci_resource_start(pdev, 0); /* addressing mode bits already removed */ #ifdef CCISS_DEBUG - printk("address 0 = %x\n", c->paddr); + printk("address 0 = %lx\n", c->paddr); #endif /* CCISS_DEBUG */ c->vaddr = remap_pci_mem(c->paddr, 0x250); @@ -3219,7 +3229,8 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev) #endif /* CCISS_DEBUG */ cfg_base_addr_index = find_PCI_BAR_index(pdev, cfg_base_addr); #ifdef CCISS_DEBUG - printk("cfg base address index = %x\n", cfg_base_addr_index); + printk("cfg base address index = %llx\n", + (unsigned long long)cfg_base_addr_index); #endif /* CCISS_DEBUG */ if (cfg_base_addr_index == -1) { printk(KERN_WARNING "cciss: Cannot find cfg_base_addr_index\n"); @@ -3229,7 +3240,7 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev) cfg_offset = readl(c->vaddr + SA5_CTMEM_OFFSET); #ifdef CCISS_DEBUG - printk("cfg offset = %x\n", cfg_offset); + printk("cfg offset = %llx\n", (unsigned long long)cfg_offset); #endif /* CCISS_DEBUG */ c->cfgtable = remap_pci_mem(pci_resource_start(pdev, cfg_base_addr_index) + @@ -3404,7 +3415,8 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, int i; int j = 0; int rc; - int dac; + int dac, return_code; + InquiryData_struct *inq_buff = NULL; i = alloc_cciss_hba(); if (i < 0) @@ -3510,6 +3522,25 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, /* Turn the interrupts on so we can service requests */ hba[i]->access.set_intr_mask(hba[i], CCISS_INTR_ON); + /* Get the firmware version */ + inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL); + if (inq_buff == NULL) { + printk(KERN_ERR "cciss: out of memory\n"); + goto clean4; + } + + return_code = sendcmd_withirq(CISS_INQUIRY, i, inq_buff, + sizeof(InquiryData_struct), 0, 0 , 0, TYPE_CMD); + if (return_code == IO_OK) { + hba[i]->firm_ver[0] = inq_buff->data_byte[32]; + hba[i]->firm_ver[1] = inq_buff->data_byte[33]; + hba[i]->firm_ver[2] = inq_buff->data_byte[34]; + hba[i]->firm_ver[3] = inq_buff->data_byte[35]; + } else { /* send command failed */ + printk(KERN_WARNING "cciss: unable to determine firmware" + " version of controller\n"); + } + cciss_procinit(i); hba[i]->cciss_max_sectors = 2048; @@ -3520,6 +3551,7 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, return 1; clean4: + kfree(inq_buff); #ifdef CONFIG_CISS_SCSI_TAPE kfree(hba[i]->scsi_rejects.complete); #endif diff --git a/drivers/block/cpqarray.c b/drivers/block/cpqarray.c index 47d233c6d0b3..5d39df14ed90 100644 --- a/drivers/block/cpqarray.c +++ b/drivers/block/cpqarray.c @@ -567,7 +567,12 @@ static int __init cpqarray_init(void) num_cntlrs_reg++; } - return(num_cntlrs_reg); + if (num_cntlrs_reg) + return 0; + else { + pci_unregister_driver(&cpqarray_pci_driver); + return -ENODEV; + } } /* Function to find the first free pointer into our hba[] array */ diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 14db747a636e..cf29cc4e6ab7 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -4124,7 +4124,7 @@ static int __init floppy_setup(char *str) printk("\n"); } else DPRINT("botched floppy option\n"); - DPRINT("Read Documentation/floppy.txt\n"); + DPRINT("Read Documentation/blockdev/floppy.txt\n"); return 0; } diff --git a/drivers/block/loop.c b/drivers/block/loop.c index 3f09cd8bcc38..5c4ee70d5cf3 100644 --- a/drivers/block/loop.c +++ b/drivers/block/loop.c @@ -40,8 +40,7 @@ * Heinz Mauelshagen , Feb 2002 * * Support for falling back on the write file operation when the address space - * operations prepare_write and/or commit_write are not available on the - * backing filesystem. + * operations write_begin is not available on the backing filesystem. * Anton Altaparmakov, 16 Feb 2005 * * Still To Fix: @@ -765,7 +764,7 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode, */ if (!file->f_op->splice_read) goto out_putf; - if (aops->prepare_write || aops->write_begin) + if (aops->write_begin) lo_flags |= LO_FLAGS_USE_AOPS; if (!(lo_flags & LO_FLAGS_USE_AOPS) && !file->f_op->write) lo_flags |= LO_FLAGS_READ_ONLY; diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c index f20bf359b84f..dc7a8c352da2 100644 --- a/drivers/block/pktcdvd.c +++ b/drivers/block/pktcdvd.c @@ -302,7 +302,7 @@ static struct kobj_type kobj_pkt_type_wqueue = { static void pkt_sysfs_dev_new(struct pktcdvd_device *pd) { if (class_pktcdvd) { - pd->dev = device_create(class_pktcdvd, NULL, pd->pkt_dev, NULL, + pd->dev = device_create(class_pktcdvd, NULL, MKDEV(0, 0), NULL, "%s", pd->name); if (IS_ERR(pd->dev)) pd->dev = NULL; @@ -2790,7 +2790,7 @@ static int pkt_new_dev(struct pktcdvd_device *pd, dev_t dev) return 0; out_mem: - blkdev_put(bdev, FMODE_READ|FMODE_WRITE); + blkdev_put(bdev, FMODE_READ | FMODE_NDELAY); /* This is safe: open() is still holding a reference. */ module_put(THIS_MODULE); return ret; @@ -2975,7 +2975,7 @@ static int pkt_remove_dev(dev_t pkt_dev) pkt_debugfs_dev_remove(pd); pkt_sysfs_dev_remove(pd); - blkdev_put(pd->bdev, FMODE_READ|FMODE_WRITE); + blkdev_put(pd->bdev, FMODE_READ | FMODE_NDELAY); remove_proc_entry(pd->name, pkt_proc); DPRINTK(DRIVER_NAME": writer %s unmapped\n", pd->name); diff --git a/drivers/block/ub.c b/drivers/block/ub.c index fccac18d3111..048d71d244d7 100644 --- a/drivers/block/ub.c +++ b/drivers/block/ub.c @@ -1546,8 +1546,6 @@ static void ub_top_sense_done(struct ub_dev *sc, struct ub_scsi_cmd *scmd) /* * Reset management - * XXX Move usb_reset_device to khubd. Hogging kevent is not a good thing. - * XXX Make usb_sync_reset asynchronous. */ static void ub_reset_enter(struct ub_dev *sc, int try) @@ -1632,6 +1630,22 @@ static void ub_reset_task(struct work_struct *work) spin_unlock_irqrestore(sc->lock, flags); } +/* + * XXX Reset brackets are too much hassle to implement, so just stub them + * in order to prevent forced unbinding (which deadlocks solid when our + * ->disconnect method waits for the reset to complete and this kills keventd). + * + * XXX Tell Alan to move usb_unlock_device inside of usb_reset_device, + * or else the post_reset is invoked, and restats I/O on a locked device. + */ +static int ub_pre_reset(struct usb_interface *iface) { + return 0; +} + +static int ub_post_reset(struct usb_interface *iface) { + return 0; +} + /* * This is called from a process context. */ @@ -2446,6 +2460,8 @@ static struct usb_driver ub_driver = { .probe = ub_probe, .disconnect = ub_disconnect, .id_table = ub_usb_ids, + .pre_reset = ub_pre_reset, + .post_reset = ub_post_reset, }; static int __init ub_init(void) diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index b220c686089d..2d19f0cc47f2 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c @@ -338,12 +338,18 @@ wait: static int xlvbd_init_blk_queue(struct gendisk *gd, u16 sector_size) { struct request_queue *rq; + elevator_t *old_e; rq = blk_init_queue(do_blkif_request, &blkif_io_lock); if (rq == NULL) return -1; - elevator_init(rq, "noop"); + old_e = rq->elevator; + if (IS_ERR_VALUE(elevator_init(rq, "noop"))) + printk(KERN_WARNING + "blkfront: Switch elevator failed, use default\n"); + else + elevator_exit(old_e); /* Hard sector size and max sectors impersonate the equiv. hardware. */ blk_queue_hardsect_size(rq, sector_size); diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c index ecab9e67d47a..29e1dfafb7c6 100644 --- a/drivers/block/xsysace.c +++ b/drivers/block/xsysace.c @@ -194,7 +194,7 @@ struct ace_device { int in_irq; /* Details of hardware device */ - unsigned long physaddr; + resource_size_t physaddr; void __iomem *baseaddr; int irq; int bus_width; /* 0 := 8 bit; 1 := 16 bit */ @@ -628,8 +628,8 @@ static void ace_fsm_dostate(struct ace_device *ace) /* Okay, it's a data request, set it up for transfer */ dev_dbg(ace->dev, - "request: sec=%lx hcnt=%lx, ccnt=%x, dir=%i\n", - req->sector, req->hard_nr_sectors, + "request: sec=%llx hcnt=%lx, ccnt=%x, dir=%i\n", + (unsigned long long) req->sector, req->hard_nr_sectors, req->current_nr_sectors, rq_data_dir(req)); ace->req = req; @@ -935,7 +935,8 @@ static int __devinit ace_setup(struct ace_device *ace) int rc; dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); - dev_dbg(ace->dev, "physaddr=0x%lx irq=%i\n", ace->physaddr, ace->irq); + dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", + (unsigned long long)ace->physaddr, ace->irq); spin_lock_init(&ace->lock); init_completion(&ace->id_completion); @@ -1017,8 +1018,8 @@ static int __devinit ace_setup(struct ace_device *ace) /* Print the identification */ dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); - dev_dbg(ace->dev, "physaddr 0x%lx, mapped to 0x%p, irq=%i\n", - ace->physaddr, ace->baseaddr, ace->irq); + dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", + (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); ace->media_change = 1; ace_revalidate_disk(ace->gd); @@ -1035,8 +1036,8 @@ err_alloc_disk: err_blk_initq: iounmap(ace->baseaddr); err_ioremap: - dev_info(ace->dev, "xsysace: error initializing device at 0x%lx\n", - ace->physaddr); + dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", + (unsigned long long) ace->physaddr); return -ENOMEM; } @@ -1059,7 +1060,7 @@ static void __devexit ace_teardown(struct ace_device *ace) } static int __devinit -ace_alloc(struct device *dev, int id, unsigned long physaddr, +ace_alloc(struct device *dev, int id, resource_size_t physaddr, int irq, int bus_width) { struct ace_device *ace; @@ -1119,7 +1120,7 @@ static void __devexit ace_free(struct device *dev) static int __devinit ace_probe(struct platform_device *dev) { - unsigned long physaddr = 0; + resource_size_t physaddr = 0; int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ int id = dev->id; int irq = NO_IRQ; @@ -1165,7 +1166,7 @@ static int __devinit ace_of_probe(struct of_device *op, const struct of_device_id *match) { struct resource res; - unsigned long physaddr; + resource_size_t physaddr; const u32 *id; int irq, bus_width, rc; diff --git a/drivers/bluetooth/bluecard_cs.c b/drivers/bluetooth/bluecard_cs.c index e6ee21d99d92..b0e569ba730d 100644 --- a/drivers/bluetooth/bluecard_cs.c +++ b/drivers/bluetooth/bluecard_cs.c @@ -867,7 +867,7 @@ static int bluecard_probe(struct pcmcia_device *link) link->io.Attributes1 = IO_DATA_PATH_WIDTH_8; link->io.NumPorts1 = 8; - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT; + link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT; link->irq.IRQInfo1 = IRQ_LEVEL_ID; link->irq.Handler = bluecard_interrupt; diff --git a/drivers/bluetooth/bpa10x.c b/drivers/bluetooth/bpa10x.c index 32f3a8ed8d3d..b936d8ce2728 100644 --- a/drivers/bluetooth/bpa10x.c +++ b/drivers/bluetooth/bpa10x.c @@ -443,8 +443,8 @@ static void bpa10x_destruct(struct hci_dev *hdev) BT_DBG("%s", hdev->name); - kfree(data->rx_skb[0]); - kfree(data->rx_skb[1]); + kfree_skb(data->rx_skb[0]); + kfree_skb(data->rx_skb[1]); kfree(data); } diff --git a/drivers/bluetooth/bt3c_cs.c b/drivers/bluetooth/bt3c_cs.c index 2cbe70b66470..b3e4d07a4ac2 100644 --- a/drivers/bluetooth/bt3c_cs.c +++ b/drivers/bluetooth/bt3c_cs.c @@ -343,6 +343,7 @@ static irqreturn_t bt3c_interrupt(int irq, void *dev_inst) bt3c_info_t *info = dev_inst; unsigned int iobase; int iir; + irqreturn_t r = IRQ_NONE; BUG_ON(!info->hdev); @@ -374,11 +375,12 @@ static irqreturn_t bt3c_interrupt(int irq, void *dev_inst) outb(iir, iobase + CONTROL); } + r = IRQ_HANDLED; } spin_unlock(&(info->lock)); - return IRQ_HANDLED; + return r; } @@ -657,7 +659,7 @@ static int bt3c_probe(struct pcmcia_device *link) link->io.Attributes1 = IO_DATA_PATH_WIDTH_8; link->io.NumPorts1 = 8; - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT; + link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT; link->irq.IRQInfo1 = IRQ_LEVEL_ID; link->irq.Handler = bt3c_interrupt; diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c index 58630cc1eff2..cda6c7cc944b 100644 --- a/drivers/bluetooth/btsdio.c +++ b/drivers/bluetooth/btsdio.c @@ -152,7 +152,7 @@ static int btsdio_rx_packet(struct btsdio_data *data) err = sdio_readsb(data->func, skb->data, REG_RDAT, len - 4); if (err < 0) { - kfree(skb); + kfree_skb(skb); return err; } diff --git a/drivers/bluetooth/btuart_cs.c b/drivers/bluetooth/btuart_cs.c index 8e556b7ff9f6..efd689a062eb 100644 --- a/drivers/bluetooth/btuart_cs.c +++ b/drivers/bluetooth/btuart_cs.c @@ -293,6 +293,7 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst) unsigned int iobase; int boguscount = 0; int iir, lsr; + irqreturn_t r = IRQ_NONE; BUG_ON(!info->hdev); @@ -302,6 +303,7 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst) iir = inb(iobase + UART_IIR) & UART_IIR_ID; while (iir) { + r = IRQ_HANDLED; /* Clear interrupt */ lsr = inb(iobase + UART_LSR); @@ -335,7 +337,7 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst) spin_unlock(&(info->lock)); - return IRQ_HANDLED; + return r; } @@ -586,7 +588,7 @@ static int btuart_probe(struct pcmcia_device *link) link->io.Attributes1 = IO_DATA_PATH_WIDTH_8; link->io.NumPorts1 = 8; - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT; + link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT; link->irq.IRQInfo1 = IRQ_LEVEL_ID; link->irq.Handler = btuart_interrupt; diff --git a/drivers/bluetooth/dtl1_cs.c b/drivers/bluetooth/dtl1_cs.c index e6e6b037695a..901bdd95655f 100644 --- a/drivers/bluetooth/dtl1_cs.c +++ b/drivers/bluetooth/dtl1_cs.c @@ -297,6 +297,7 @@ static irqreturn_t dtl1_interrupt(int irq, void *dev_inst) unsigned char msr; int boguscount = 0; int iir, lsr; + irqreturn_t r = IRQ_NONE; BUG_ON(!info->hdev); @@ -307,6 +308,7 @@ static irqreturn_t dtl1_interrupt(int irq, void *dev_inst) iir = inb(iobase + UART_IIR) & UART_IIR_ID; while (iir) { + r = IRQ_HANDLED; /* Clear interrupt */ lsr = inb(iobase + UART_LSR); @@ -343,11 +345,12 @@ static irqreturn_t dtl1_interrupt(int irq, void *dev_inst) info->ri_latch = msr & UART_MSR_RI; clear_bit(XMIT_WAITING, &(info->tx_state)); dtl1_write_wakeup(info); + r = IRQ_HANDLED; } spin_unlock(&(info->lock)); - return IRQ_HANDLED; + return r; } @@ -568,7 +571,7 @@ static int dtl1_probe(struct pcmcia_device *link) link->io.Attributes1 = IO_DATA_PATH_WIDTH_8; link->io.NumPorts1 = 8; - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT; + link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT; link->irq.IRQInfo1 = IRQ_LEVEL_ID; link->irq.Handler = dtl1_interrupt; diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c index d16b02423d61..7d2e91cccb13 100644 --- a/drivers/cdrom/cdrom.c +++ b/drivers/cdrom/cdrom.c @@ -2081,10 +2081,6 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf, if (!q) return -ENXIO; - rq = blk_get_request(q, READ, GFP_KERNEL); - if (!rq) - return -ENOMEM; - cdi->last_sense = 0; while (nframes) { @@ -2096,9 +2092,17 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf, len = nr * CD_FRAMESIZE_RAW; + rq = blk_get_request(q, READ, GFP_KERNEL); + if (!rq) { + ret = -ENOMEM; + break; + } + ret = blk_rq_map_user(q, rq, NULL, ubuf, len, GFP_KERNEL); - if (ret) + if (ret) { + blk_put_request(rq); break; + } rq->cmd[0] = GPCMD_READ_CD; rq->cmd[1] = 1 << 2; @@ -2124,6 +2128,7 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf, if (blk_rq_unmap_user(bio)) ret = -EFAULT; + blk_put_request(rq); if (ret) break; @@ -2133,7 +2138,6 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf, ubuf += len; } - blk_put_request(rq); return ret; } diff --git a/drivers/cdrom/gdrom.c b/drivers/cdrom/gdrom.c index 9aaa86b232b1..2eecb779437b 100644 --- a/drivers/cdrom/gdrom.c +++ b/drivers/cdrom/gdrom.c @@ -495,9 +495,10 @@ static int gdrom_bdops_open(struct block_device *bdev, fmode_t mode) return cdrom_open(gd.cd_info, bdev, mode); } -static int gdrom_bdops_release(struct block_device *bdev, fmode_t mode) +static int gdrom_bdops_release(struct gendisk *disk, fmode_t mode) { - return cdrom_release(gd.cd_info, mode); + cdrom_release(gd.cd_info, mode); + return 0; } static int gdrom_bdops_mediachanged(struct gendisk *disk) diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 122254155ae1..43d6ba83a191 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -124,7 +124,7 @@ config COMPUTONE which give you many serial ports. You would need something like this to connect more than two modems to your Linux box, for instance in order to become a dial-in server. If you have a card like that, say - Y here and read . + Y here and read . To compile this driver as module, choose M here: the module will be called ip2. @@ -136,7 +136,7 @@ config ROCKETPORT This driver supports Comtrol RocketPort and RocketModem PCI boards. These boards provide 2, 4, 8, 16, or 32 high-speed serial ports or modems. For information about the RocketPort/RocketModem boards - and this driver read . + and this driver read . To compile this driver as a module, choose M here: the module will be called rocket. @@ -154,7 +154,7 @@ config CYCLADES your Linux box, for instance in order to become a dial-in server. For information about the Cyclades-Z card, read - . + . To compile this driver as a module, choose M here: the module will be called cyclades. @@ -183,7 +183,7 @@ config DIGIEPCA box, for instance in order to become a dial-in server. This driver supports the original PC (ISA) boards as well as PCI, and EISA. If you have a card like this, say Y here and read the file - . + . To compile this driver as a module, choose M here: the module will be called epca. @@ -289,7 +289,7 @@ config RISCOM8 which gives you many serial ports. You would need something like this to connect more than two modems to your Linux box, for instance in order to become a dial-in server. If you have a card like that, - say Y here and read the file . + say Y here and read the file . Also it's possible to say M here and compile this driver as kernel loadable module; the module will be called riscom8. @@ -304,8 +304,8 @@ config SPECIALIX your Linux box, for instance in order to become a dial-in server. If you have a card like that, say Y here and read the file - . Also it's possible to say M here - and compile this driver as kernel loadable module which will be + . Also it's possible to say + M here and compile this driver as kernel loadable module which will be called specialix. config SX @@ -313,7 +313,7 @@ config SX depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA) help This is a driver for the SX and SI multiport serial cards. - Please read the file for details. + Please read the file for details. This driver can only be built as a module ( = code which can be inserted in and removed from the running kernel whenever you want). @@ -344,8 +344,8 @@ config STALDRV like this to connect more than two modems to your Linux box, for instance in order to become a dial-in server. If you say Y here, you will be asked for your specific card model in the next - questions. Make sure to read in - this case. If you have never heard about all this, it's safe to + questions. Make sure to read + in this case. If you have never heard about all this, it's safe to say N. config STALLION @@ -354,7 +354,7 @@ config STALLION help If you have an EasyIO or EasyConnection 8/32 multiport Stallion card, then this is for you; say Y. Make sure to read - . + . To compile this driver as a module, choose M here: the module will be called stallion. @@ -365,7 +365,7 @@ config ISTALLION help If you have an EasyConnection 8/64, ONboard, Brumby or Stallion serial multiport card, say Y here. Make sure to read - . + . To compile this driver as a module, choose M here: the module will be called istallion. @@ -812,28 +812,6 @@ config JS_RTC To compile this driver as a module, choose M here: the module will be called js-rtc. -config SGI_DS1286 - tristate "SGI DS1286 RTC support" - depends on SGI_HAS_DS1286 - help - If you say Y here and create a character special file /dev/rtc with - major number 10 and minor number 135 using mknod ("man mknod"), you - will get access to the real time clock built into your computer. - Every SGI has such a clock built in. It reports status information - via the file /proc/rtc and its behaviour is set by various ioctls on - /dev/rtc. - -config SGI_IP27_RTC - bool "SGI M48T35 RTC support" - depends on SGI_IP27 - help - If you say Y here and create a character special file /dev/rtc with - major number 10 and minor number 135 using mknod ("man mknod"), you - will get access to the real time clock built into your computer. - Every SGI has such a clock built in. It reports status information - via the file /proc/rtc and its behaviour is set by various ioctls on - /dev/rtc. - config GEN_RTC tristate "Generic /dev/rtc emulation" depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32 diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 1a4247dccac4..438f71317c5c 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -74,8 +74,6 @@ obj-$(CONFIG_RTC) += rtc.o obj-$(CONFIG_HPET) += hpet.o obj-$(CONFIG_GEN_RTC) += genrtc.o obj-$(CONFIG_EFI_RTC) += efirtc.o -obj-$(CONFIG_SGI_DS1286) += ds1286.o -obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o obj-$(CONFIG_DS1302) += ds1302.o obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/ ifeq ($(CONFIG_GENERIC_NVRAM),y) diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c index 0f004b65ec03..03f95ec08f59 100644 --- a/drivers/char/agp/uninorth-agp.c +++ b/drivers/char/agp/uninorth-agp.c @@ -27,7 +27,7 @@ static int uninorth_rev; static int is_u3; -static char __devinitdata *aperture = NULL; +static char *aperture = NULL; static int uninorth_fetch_size(void) { diff --git a/drivers/char/cp437.uni b/drivers/char/cp437.uni index 1f06889a96b9..bc6163484f62 100644 --- a/drivers/char/cp437.uni +++ b/drivers/char/cp437.uni @@ -27,7 +27,7 @@ 0x0c U+2640 0x0d U+266a 0x0e U+266b -0x0f U+263c +0x0f U+263c U+00a4 0x10 U+25b6 U+25ba 0x11 U+25c0 U+25c4 0x12 U+2195 @@ -55,7 +55,7 @@ 0x24 U+0024 0x25 U+0025 0x26 U+0026 -0x27 U+0027 +0x27 U+0027 U+00b4 0x28 U+0028 0x29 U+0029 0x2a U+002a @@ -84,7 +84,7 @@ 0x41 U+0041 U+00c0 U+00c1 U+00c2 U+00c3 0x42 U+0042 0x43 U+0043 U+00a9 -0x44 U+0044 +0x44 U+0044 U+00d0 0x45 U+0045 U+00c8 U+00ca U+00cb 0x46 U+0046 0x47 U+0047 @@ -140,7 +140,7 @@ 0x79 U+0079 U+00fd 0x7a U+007a 0x7b U+007b -0x7c U+007c U+00a5 +0x7c U+007c U+00a6 0x7d U+007d 0x7e U+007e # @@ -263,10 +263,10 @@ 0xe8 U+03a6 U+00d8 0xe9 U+0398 0xea U+03a9 U+2126 -0xeb U+03b4 +0xeb U+03b4 U+00f0 0xec U+221e 0xed U+03c6 U+00f8 -0xee U+03b5 +0xee U+03b5 U+2208 0xef U+2229 0xf0 U+2261 0xf1 U+00b1 diff --git a/drivers/char/ds1286.c b/drivers/char/ds1286.c deleted file mode 100644 index 0a826d7be10e..000000000000 --- a/drivers/char/ds1286.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * DS1286 Real Time Clock interface for Linux - * - * Copyright (C) 1998, 1999, 2000 Ralf Baechle - * - * Based on code written by Paul Gortmaker. - * - * This driver allows use of the real time clock (built into nearly all - * computers) from user space. It exports the /dev/rtc interface supporting - * various ioctl() and also the /proc/rtc pseudo-file for status - * information. - * - * The ioctls can be used to set the interrupt behaviour and generation rate - * from the RTC via IRQ 8. Then the /dev/rtc interface can be used to make - * use of these timer interrupts, be they interval or alarm based. - * - * The /dev/rtc interface will block on reads until an interrupt has been - * received. If a RTC interrupt has already happened, it will output an - * unsigned long and then block. The output value contains the interrupt - * status in the low byte and the number of interrupts since the last read - * in the remaining high bytes. The /dev/rtc interface can also be used with - * the select(2) call. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define DS1286_VERSION "1.0" - -/* - * We sponge a minor off of the misc major. No need slurping - * up another valuable major dev number for this. If you add - * an ioctl, make sure you don't conflict with SPARC's RTC - * ioctls. - */ - -static DECLARE_WAIT_QUEUE_HEAD(ds1286_wait); - -static ssize_t ds1286_read(struct file *file, char *buf, - size_t count, loff_t *ppos); - -static int ds1286_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg); - -static unsigned int ds1286_poll(struct file *file, poll_table *wait); - -static void ds1286_get_alm_time (struct rtc_time *alm_tm); -static void ds1286_get_time(struct rtc_time *rtc_tm); -static int ds1286_set_time(struct rtc_time *rtc_tm); - -static inline unsigned char ds1286_is_updating(void); - -static DEFINE_SPINLOCK(ds1286_lock); - -static int ds1286_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data); - -/* - * Bits in rtc_status. (7 bits of room for future expansion) - */ - -#define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */ -#define RTC_TIMER_ON 0x02 /* missed irq timer active */ - -static unsigned char ds1286_status; /* bitmapped status byte. */ - -static unsigned char days_in_mo[] = { - 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 -}; - -/* - * Now all the various file operations that we export. - */ - -static ssize_t ds1286_read(struct file *file, char *buf, - size_t count, loff_t *ppos) -{ - return -EIO; -} - -static int ds1286_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - struct rtc_time wtime; - - switch (cmd) { - case RTC_AIE_OFF: /* Mask alarm int. enab. bit */ - { - unsigned long flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = rtc_read(RTC_CMD); - val |= RTC_TDM; - rtc_write(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_AIE_ON: /* Allow alarm interrupts. */ - { - unsigned long flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = rtc_read(RTC_CMD); - val &= ~RTC_TDM; - rtc_write(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_WIE_OFF: /* Mask watchdog int. enab. bit */ - { - unsigned long flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = rtc_read(RTC_CMD); - val |= RTC_WAM; - rtc_write(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_WIE_ON: /* Allow watchdog interrupts. */ - { - unsigned long flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = rtc_read(RTC_CMD); - val &= ~RTC_WAM; - rtc_write(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_ALM_READ: /* Read the present alarm time */ - { - /* - * This returns a struct rtc_time. Reading >= 0xc0 - * means "don't care" or "match all". Only the tm_hour, - * tm_min, and tm_sec values are filled in. - */ - - memset(&wtime, 0, sizeof(wtime)); - ds1286_get_alm_time(&wtime); - break; - } - case RTC_ALM_SET: /* Store a time into the alarm */ - { - /* - * This expects a struct rtc_time. Writing 0xff means - * "don't care" or "match all". Only the tm_hour, - * tm_min and tm_sec are used. - */ - unsigned char hrs, min, sec; - struct rtc_time alm_tm; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - if (copy_from_user(&alm_tm, (struct rtc_time*)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - hrs = alm_tm.tm_hour; - min = alm_tm.tm_min; - sec = alm_tm.tm_sec; - - if (hrs >= 24) - hrs = 0xff; - - if (min >= 60) - min = 0xff; - - if (sec != 0) - return -EINVAL; - - min = bin2bcd(min); - min = bin2bcd(hrs); - - spin_lock(&ds1286_lock); - rtc_write(hrs, RTC_HOURS_ALARM); - rtc_write(min, RTC_MINUTES_ALARM); - spin_unlock(&ds1286_lock); - - return 0; - } - case RTC_RD_TIME: /* Read the time/date from RTC */ - { - memset(&wtime, 0, sizeof(wtime)); - ds1286_get_time(&wtime); - break; - } - case RTC_SET_TIME: /* Set the RTC */ - { - struct rtc_time rtc_tm; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - return ds1286_set_time(&rtc_tm); - } - default: - return -EINVAL; - } - return copy_to_user((void *)arg, &wtime, sizeof wtime) ? -EFAULT : 0; -} - -/* - * We enforce only one user at a time here with the open/close. - * Also clear the previous interrupt data on an open, and clean - * up things on a close. - */ - -static int ds1286_open(struct inode *inode, struct file *file) -{ - lock_kernel(); - spin_lock_irq(&ds1286_lock); - - if (ds1286_status & RTC_IS_OPEN) - goto out_busy; - - ds1286_status |= RTC_IS_OPEN; - - spin_unlock_irq(&ds1286_lock); - unlock_kernel(); - return 0; - -out_busy: - spin_lock_irq(&ds1286_lock); - unlock_kernel(); - return -EBUSY; -} - -static int ds1286_release(struct inode *inode, struct file *file) -{ - ds1286_status &= ~RTC_IS_OPEN; - - return 0; -} - -static unsigned int ds1286_poll(struct file *file, poll_table *wait) -{ - poll_wait(file, &ds1286_wait, wait); - - return 0; -} - -/* - * The various file operations we support. - */ - -static const struct file_operations ds1286_fops = { - .llseek = no_llseek, - .read = ds1286_read, - .poll = ds1286_poll, - .ioctl = ds1286_ioctl, - .open = ds1286_open, - .release = ds1286_release, -}; - -static struct miscdevice ds1286_dev= -{ - .minor = RTC_MINOR, - .name = "rtc", - .fops = &ds1286_fops, -}; - -static int __init ds1286_init(void) -{ - int err; - - printk(KERN_INFO "DS1286 Real Time Clock Driver v%s\n", DS1286_VERSION); - - err = misc_register(&ds1286_dev); - if (err) - goto out; - - if (!create_proc_read_entry("driver/rtc", 0, 0, ds1286_read_proc, NULL)) { - err = -ENOMEM; - - goto out_deregister; - } - - return 0; - -out_deregister: - misc_deregister(&ds1286_dev); - -out: - return err; -} - -static void __exit ds1286_exit(void) -{ - remove_proc_entry("driver/rtc", NULL); - misc_deregister(&ds1286_dev); -} - -static char *days[] = { - "***", "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" -}; - -/* - * Info exported via "/proc/rtc". - */ -static int ds1286_proc_output(char *buf) -{ - char *p, *s; - struct rtc_time tm; - unsigned char hundredth, month, cmd, amode; - - p = buf; - - ds1286_get_time(&tm); - hundredth = rtc_read(RTC_HUNDREDTH_SECOND); - hundredth = bcd2bin(hundredth); - - p += sprintf(p, - "rtc_time\t: %02d:%02d:%02d.%02d\n" - "rtc_date\t: %04d-%02d-%02d\n", - tm.tm_hour, tm.tm_min, tm.tm_sec, hundredth, - tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday); - - /* - * We implicitly assume 24hr mode here. Alarm values >= 0xc0 will - * match any value for that particular field. Values that are - * greater than a valid time, but less than 0xc0 shouldn't appear. - */ - ds1286_get_alm_time(&tm); - p += sprintf(p, "alarm\t\t: %s ", days[tm.tm_wday]); - if (tm.tm_hour <= 24) - p += sprintf(p, "%02d:", tm.tm_hour); - else - p += sprintf(p, "**:"); - - if (tm.tm_min <= 59) - p += sprintf(p, "%02d\n", tm.tm_min); - else - p += sprintf(p, "**\n"); - - month = rtc_read(RTC_MONTH); - p += sprintf(p, - "oscillator\t: %s\n" - "square_wave\t: %s\n", - (month & RTC_EOSC) ? "disabled" : "enabled", - (month & RTC_ESQW) ? "disabled" : "enabled"); - - amode = ((rtc_read(RTC_MINUTES_ALARM) & 0x80) >> 5) | - ((rtc_read(RTC_HOURS_ALARM) & 0x80) >> 6) | - ((rtc_read(RTC_DAY_ALARM) & 0x80) >> 7); - if (amode == 7) s = "each minute"; - else if (amode == 3) s = "minutes match"; - else if (amode == 1) s = "hours and minutes match"; - else if (amode == 0) s = "days, hours and minutes match"; - else s = "invalid"; - p += sprintf(p, "alarm_mode\t: %s\n", s); - - cmd = rtc_read(RTC_CMD); - p += sprintf(p, - "alarm_enable\t: %s\n" - "wdog_alarm\t: %s\n" - "alarm_mask\t: %s\n" - "wdog_alarm_mask\t: %s\n" - "interrupt_mode\t: %s\n" - "INTB_mode\t: %s_active\n" - "interrupt_pins\t: %s\n", - (cmd & RTC_TDF) ? "yes" : "no", - (cmd & RTC_WAF) ? "yes" : "no", - (cmd & RTC_TDM) ? "disabled" : "enabled", - (cmd & RTC_WAM) ? "disabled" : "enabled", - (cmd & RTC_PU_LVL) ? "pulse" : "level", - (cmd & RTC_IBH_LO) ? "low" : "high", - (cmd & RTC_IPSW) ? "unswapped" : "swapped"); - - return p - buf; -} - -static int ds1286_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - int len = ds1286_proc_output (page); - if (len <= off+count) *eof = 1; - *start = page + off; - len -= off; - if (len>count) - len = count; - if (len<0) - len = 0; - - return len; -} - -/* - * Returns true if a clock update is in progress - */ -static inline unsigned char ds1286_is_updating(void) -{ - return rtc_read(RTC_CMD) & RTC_TE; -} - - -static void ds1286_get_time(struct rtc_time *rtc_tm) -{ - unsigned char save_control; - unsigned long flags; - - /* - * read RTC once any update in progress is done. The update - * can take just over 2ms. We wait 10 to 20ms. There is no need to - * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP. - * If you need to know *exactly* when a second has started, enable - * periodic update complete interrupts, (via ioctl) and then - * immediately read /dev/rtc which will block until you get the IRQ. - * Once the read clears, read the RTC time (again via ioctl). Easy. - */ - - if (ds1286_is_updating() != 0) - msleep(20); - - /* - * Only the values that we read from the RTC are set. We leave - * tm_wday, tm_yday and tm_isdst untouched. Even though the - * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated - * by the RTC when initially set to a non-zero value. - */ - spin_lock_irqsave(&ds1286_lock, flags); - save_control = rtc_read(RTC_CMD); - rtc_write((save_control|RTC_TE), RTC_CMD); - - rtc_tm->tm_sec = rtc_read(RTC_SECONDS); - rtc_tm->tm_min = rtc_read(RTC_MINUTES); - rtc_tm->tm_hour = rtc_read(RTC_HOURS) & 0x3f; - rtc_tm->tm_mday = rtc_read(RTC_DATE); - rtc_tm->tm_mon = rtc_read(RTC_MONTH) & 0x1f; - rtc_tm->tm_year = rtc_read(RTC_YEAR); - - rtc_write(save_control, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); - rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); - rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); - rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); - rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); - rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); - - /* - * Account for differences between how the RTC uses the values - * and how they are defined in a struct rtc_time; - */ - if (rtc_tm->tm_year < 45) - rtc_tm->tm_year += 30; - if ((rtc_tm->tm_year += 40) < 70) - rtc_tm->tm_year += 100; - - rtc_tm->tm_mon--; -} - -static int ds1286_set_time(struct rtc_time *rtc_tm) -{ - unsigned char mon, day, hrs, min, sec, leap_yr; - unsigned char save_control; - unsigned int yrs; - unsigned long flags; - - - yrs = rtc_tm->tm_year + 1900; - mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */ - day = rtc_tm->tm_mday; - hrs = rtc_tm->tm_hour; - min = rtc_tm->tm_min; - sec = rtc_tm->tm_sec; - - if (yrs < 1970) - return -EINVAL; - - leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); - - if ((mon > 12) || (day == 0)) - return -EINVAL; - - if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) - return -EINVAL; - - if ((hrs >= 24) || (min >= 60) || (sec >= 60)) - return -EINVAL; - - if ((yrs -= 1940) > 255) /* They are unsigned */ - return -EINVAL; - - if (yrs >= 100) - yrs -= 100; - - sec = bin2bcd(sec); - min = bin2bcd(min); - hrs = bin2bcd(hrs); - day = bin2bcd(day); - mon = bin2bcd(mon); - yrs = bin2bcd(yrs); - - spin_lock_irqsave(&ds1286_lock, flags); - save_control = rtc_read(RTC_CMD); - rtc_write((save_control|RTC_TE), RTC_CMD); - - rtc_write(yrs, RTC_YEAR); - rtc_write(mon, RTC_MONTH); - rtc_write(day, RTC_DATE); - rtc_write(hrs, RTC_HOURS); - rtc_write(min, RTC_MINUTES); - rtc_write(sec, RTC_SECONDS); - rtc_write(0, RTC_HUNDREDTH_SECOND); - - rtc_write(save_control, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; -} - -static void ds1286_get_alm_time(struct rtc_time *alm_tm) -{ - unsigned char cmd; - unsigned long flags; - - /* - * Only the values that we read from the RTC are set. That - * means only tm_wday, tm_hour, tm_min. - */ - spin_lock_irqsave(&ds1286_lock, flags); - alm_tm->tm_min = rtc_read(RTC_MINUTES_ALARM) & 0x7f; - alm_tm->tm_hour = rtc_read(RTC_HOURS_ALARM) & 0x1f; - alm_tm->tm_wday = rtc_read(RTC_DAY_ALARM) & 0x07; - cmd = rtc_read(RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - alm_tm->tm_min = bcd2bin(alm_tm->tm_min); - alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); - alm_tm->tm_sec = 0; -} - -module_init(ds1286_init); -module_exit(ds1286_exit); - -MODULE_AUTHOR("Ralf Baechle"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_MISCDEV(RTC_MINOR); diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c index 408f5f92cb4e..53fdc7ff3870 100644 --- a/drivers/char/hpet.c +++ b/drivers/char/hpet.c @@ -427,9 +427,6 @@ static int hpet_release(struct inode *inode, struct file *file) if (irq) free_irq(irq, devp); - if (file->f_flags & FASYNC) - hpet_fasync(-1, file, 0); - file->private_data = NULL; return 0; } diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c index c422e870dc52..cd0ba51f7c80 100644 --- a/drivers/char/hw_random/amd-rng.c +++ b/drivers/char/hw_random/amd-rng.c @@ -11,7 +11,7 @@ * derived from * * Hardware driver for the AMD 768 Random Number Generator (RNG) - * (c) Copyright 2001 Red Hat Inc + * (c) Copyright 2001 Red Hat Inc * * derived from * diff --git a/drivers/char/hw_random/geode-rng.c b/drivers/char/hw_random/geode-rng.c index fed4ef5569f5..64d513f68368 100644 --- a/drivers/char/hw_random/geode-rng.c +++ b/drivers/char/hw_random/geode-rng.c @@ -11,7 +11,7 @@ * derived from * * Hardware driver for the AMD 768 Random Number Generator (RNG) - * (c) Copyright 2001 Red Hat Inc + * (c) Copyright 2001 Red Hat Inc * * derived from * diff --git a/drivers/char/hw_random/intel-rng.c b/drivers/char/hw_random/intel-rng.c index 8a2fce0756ec..5dcbe603eca2 100644 --- a/drivers/char/hw_random/intel-rng.c +++ b/drivers/char/hw_random/intel-rng.c @@ -11,7 +11,7 @@ * derived from * * Hardware driver for the AMD 768 Random Number Generator (RNG) - * (c) Copyright 2001 Red Hat Inc + * (c) Copyright 2001 Red Hat Inc * * derived from * diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c index 128202e18fc9..4e9573c1d39e 100644 --- a/drivers/char/hw_random/via-rng.c +++ b/drivers/char/hw_random/via-rng.c @@ -11,7 +11,7 @@ * derived from * * Hardware driver for the AMD 768 Random Number Generator (RNG) - * (c) Copyright 2001 Red Hat Inc + * (c) Copyright 2001 Red Hat Inc * * derived from * diff --git a/drivers/char/ip27-rtc.c b/drivers/char/ip27-rtc.c deleted file mode 100644 index 2abd881b4cbc..000000000000 --- a/drivers/char/ip27-rtc.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip - * - * Real Time Clock interface for Linux - * - * TODO: Implement periodic interrupts. - * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Written by Ulf Carlsson (ulfc@engr.sgi.com) - * - * Based on code written by Paul Gortmaker. - * - * This driver allows use of the real time clock (built into - * nearly all computers) from user space. It exports the /dev/rtc - * interface supporting various ioctl() and also the /proc/rtc - * pseudo-file for status information. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#define RTC_VERSION "1.09b" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static long rtc_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg); - -static int rtc_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data); - -static void get_rtc_time(struct rtc_time *rtc_tm); - -/* - * Bits in rtc_status. (6 bits of room for future expansion) - */ - -#define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */ -#define RTC_TIMER_ON 0x02 /* missed irq timer active */ - -static unsigned char rtc_status; /* bitmapped status byte. */ -static unsigned long rtc_freq; /* Current periodic IRQ rate */ -static struct m48t35_rtc *rtc; - -/* - * If this driver ever becomes modularised, it will be really nice - * to make the epoch retain its value across module reload... - */ - -static unsigned long epoch = 1970; /* year corresponding to 0x00 */ - -static const unsigned char days_in_mo[] = -{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - -static long rtc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -{ - - struct rtc_time wtime; - - switch (cmd) { - case RTC_RD_TIME: /* Read the time/date from RTC */ - { - get_rtc_time(&wtime); - break; - } - case RTC_SET_TIME: /* Set the RTC */ - { - struct rtc_time rtc_tm; - unsigned char mon, day, hrs, min, sec, leap_yr; - unsigned int yrs; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - yrs = rtc_tm.tm_year + 1900; - mon = rtc_tm.tm_mon + 1; /* tm_mon starts at zero */ - day = rtc_tm.tm_mday; - hrs = rtc_tm.tm_hour; - min = rtc_tm.tm_min; - sec = rtc_tm.tm_sec; - - if (yrs < 1970) - return -EINVAL; - - leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); - - if ((mon > 12) || (day == 0)) - return -EINVAL; - - if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) - return -EINVAL; - - if ((hrs >= 24) || (min >= 60) || (sec >= 60)) - return -EINVAL; - - if ((yrs -= epoch) > 255) /* They are unsigned */ - return -EINVAL; - - if (yrs > 169) - return -EINVAL; - - if (yrs >= 100) - yrs -= 100; - - sec = bin2bcd(sec); - min = bin2bcd(min); - hrs = bin2bcd(hrs); - day = bin2bcd(day); - mon = bin2bcd(mon); - yrs = bin2bcd(yrs); - - spin_lock_irq(&rtc_lock); - rtc->control |= M48T35_RTC_SET; - rtc->year = yrs; - rtc->month = mon; - rtc->date = day; - rtc->hour = hrs; - rtc->min = min; - rtc->sec = sec; - rtc->control &= ~M48T35_RTC_SET; - spin_unlock_irq(&rtc_lock); - - return 0; - } - default: - return -EINVAL; - } - return copy_to_user((void *)arg, &wtime, sizeof wtime) ? -EFAULT : 0; -} - -/* - * We enforce only one user at a time here with the open/close. - * Also clear the previous interrupt data on an open, and clean - * up things on a close. - */ - -static int rtc_open(struct inode *inode, struct file *file) -{ - lock_kernel(); - spin_lock_irq(&rtc_lock); - - if (rtc_status & RTC_IS_OPEN) { - spin_unlock_irq(&rtc_lock); - unlock_kernel(); - return -EBUSY; - } - - rtc_status |= RTC_IS_OPEN; - spin_unlock_irq(&rtc_lock); - unlock_kernel(); - - return 0; -} - -static int rtc_release(struct inode *inode, struct file *file) -{ - /* - * Turn off all interrupts once the device is no longer - * in use, and clear the data. - */ - - spin_lock_irq(&rtc_lock); - rtc_status &= ~RTC_IS_OPEN; - spin_unlock_irq(&rtc_lock); - - return 0; -} - -/* - * The various file operations we support. - */ - -static const struct file_operations rtc_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = rtc_ioctl, - .open = rtc_open, - .release = rtc_release, -}; - -static struct miscdevice rtc_dev= -{ - RTC_MINOR, - "rtc", - &rtc_fops -}; - -static int __init rtc_init(void) -{ - rtc = (struct m48t35_rtc *) - (KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + IOC3_BYTEBUS_DEV0); - - printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION); - if (misc_register(&rtc_dev)) { - printk(KERN_ERR "rtc: cannot register misc device.\n"); - return -ENODEV; - } - if (!create_proc_read_entry("driver/rtc", 0, NULL, rtc_read_proc, NULL)) { - printk(KERN_ERR "rtc: cannot create /proc/rtc.\n"); - misc_deregister(&rtc_dev); - return -ENOENT; - } - - rtc_freq = 1024; - - return 0; -} - -static void __exit rtc_exit (void) -{ - /* interrupts and timer disabled at this point by rtc_release */ - - remove_proc_entry ("rtc", NULL); - misc_deregister(&rtc_dev); -} - -module_init(rtc_init); -module_exit(rtc_exit); - -/* - * Info exported via "/proc/rtc". - */ - -static int rtc_get_status(char *buf) -{ - char *p; - struct rtc_time tm; - - /* - * Just emulate the standard /proc/rtc - */ - - p = buf; - - get_rtc_time(&tm); - - /* - * There is no way to tell if the luser has the RTC set for local - * time or for Universal Standard Time (GMT). Probably local though. - */ - p += sprintf(p, - "rtc_time\t: %02d:%02d:%02d\n" - "rtc_date\t: %04d-%02d-%02d\n" - "rtc_epoch\t: %04lu\n" - "24hr\t\t: yes\n", - tm.tm_hour, tm.tm_min, tm.tm_sec, - tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, epoch); - - return p - buf; -} - -static int rtc_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - int len = rtc_get_status(page); - if (len <= off+count) *eof = 1; - *start = page + off; - len -= off; - if (len>count) len = count; - if (len<0) len = 0; - return len; -} - -static void get_rtc_time(struct rtc_time *rtc_tm) -{ - /* - * Do we need to wait for the last update to finish? - */ - - /* - * Only the values that we read from the RTC are set. We leave - * tm_wday, tm_yday and tm_isdst untouched. Even though the - * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated - * by the RTC when initially set to a non-zero value. - */ - spin_lock_irq(&rtc_lock); - rtc->control |= M48T35_RTC_READ; - rtc_tm->tm_sec = rtc->sec; - rtc_tm->tm_min = rtc->min; - rtc_tm->tm_hour = rtc->hour; - rtc_tm->tm_mday = rtc->date; - rtc_tm->tm_mon = rtc->month; - rtc_tm->tm_year = rtc->year; - rtc->control &= ~M48T35_RTC_READ; - spin_unlock_irq(&rtc_lock); - - rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); - rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); - rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); - rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); - rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); - rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); - - /* - * Account for differences between how the RTC uses the values - * and how they are defined in a struct rtc_time; - */ - if ((rtc_tm->tm_year += (epoch - 1900)) <= 69) - rtc_tm->tm_year += 100; - - rtc_tm->tm_mon--; -} diff --git a/drivers/char/ipmi/ipmi_devintf.c b/drivers/char/ipmi/ipmi_devintf.c index 835a33c8d5f5..41fc11dc921c 100644 --- a/drivers/char/ipmi/ipmi_devintf.c +++ b/drivers/char/ipmi/ipmi_devintf.c @@ -162,8 +162,6 @@ static int ipmi_release(struct inode *inode, struct file *file) if (rv) return rv; - ipmi_fasync (-1, file, 0); - /* FIXME - free the messages in the list. */ kfree(priv); @@ -957,3 +955,4 @@ module_exit(cleanup_ipmi); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Corey Minyard "); MODULE_DESCRIPTION("Linux device interface for the IPMI message handler."); +MODULE_ALIAS("platform:ipmi_si"); diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index 8a59aaa21be5..7a88dfd4427b 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -422,9 +422,11 @@ struct ipmi_smi { /** * The driver model view of the IPMI messaging driver. */ -static struct device_driver ipmidriver = { - .name = "ipmi", - .bus = &platform_bus_type +static struct platform_driver ipmidriver = { + .driver = { + .name = "ipmi", + .bus = &platform_bus_type + } }; static DEFINE_MUTEX(ipmidriver_mutex); @@ -2384,9 +2386,9 @@ static int ipmi_bmc_register(ipmi_smi_t intf, int ifnum, * representing the interfaced BMC already */ if (bmc->guid_set) - old_bmc = ipmi_find_bmc_guid(&ipmidriver, bmc->guid); + old_bmc = ipmi_find_bmc_guid(&ipmidriver.driver, bmc->guid); else - old_bmc = ipmi_find_bmc_prod_dev_id(&ipmidriver, + old_bmc = ipmi_find_bmc_prod_dev_id(&ipmidriver.driver, bmc->id.product_id, bmc->id.device_id); @@ -2416,7 +2418,7 @@ static int ipmi_bmc_register(ipmi_smi_t intf, int ifnum, snprintf(name, sizeof(name), "ipmi_bmc.%4.4x", bmc->id.product_id); - while (ipmi_find_bmc_prod_dev_id(&ipmidriver, + while (ipmi_find_bmc_prod_dev_id(&ipmidriver.driver, bmc->id.product_id, bmc->id.device_id)) { if (!warn_printed) { @@ -2446,7 +2448,7 @@ static int ipmi_bmc_register(ipmi_smi_t intf, int ifnum, " Unable to allocate platform device\n"); return -ENOMEM; } - bmc->dev->dev.driver = &ipmidriver; + bmc->dev->dev.driver = &ipmidriver.driver; dev_set_drvdata(&bmc->dev->dev, bmc); kref_init(&bmc->refcount); @@ -4247,7 +4249,7 @@ static int ipmi_init_msghandler(void) if (initialized) return 0; - rv = driver_register(&ipmidriver); + rv = driver_register(&ipmidriver.driver); if (rv) { printk(KERN_ERR PFX "Could not register IPMI driver\n"); return rv; @@ -4308,7 +4310,7 @@ static __exit void cleanup_ipmi(void) remove_proc_entry(proc_ipmi_root->name, NULL); #endif /* CONFIG_PROC_FS */ - driver_unregister(&ipmidriver); + driver_unregister(&ipmidriver.driver); initialized = 0; diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index 3123bf57ad91..3000135f2ead 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -114,9 +114,11 @@ static char *si_to_str[] = { "kcs", "smic", "bt" }; #define DEVICE_NAME "ipmi_si" -static struct device_driver ipmi_driver = { - .name = DEVICE_NAME, - .bus = &platform_bus_type +static struct platform_driver ipmi_driver = { + .driver = { + .name = DEVICE_NAME, + .bus = &platform_bus_type + } }; @@ -2868,7 +2870,7 @@ static int try_smi_init(struct smi_info *new_smi) goto out_err; } new_smi->dev = &new_smi->pdev->dev; - new_smi->dev->driver = &ipmi_driver; + new_smi->dev->driver = &ipmi_driver.driver; rv = platform_device_add(new_smi->pdev); if (rv) { @@ -2983,7 +2985,7 @@ static __devinit int init_ipmi_si(void) initialized = 1; /* Register the device drivers. */ - rv = driver_register(&ipmi_driver); + rv = driver_register(&ipmi_driver.driver); if (rv) { printk(KERN_ERR "init_ipmi_si: Unable to register driver: %d\n", @@ -3052,7 +3054,7 @@ static __devinit int init_ipmi_si(void) #ifdef CONFIG_PPC_OF of_unregister_platform_driver(&ipmi_of_platform_driver); #endif - driver_unregister(&ipmi_driver); + driver_unregister(&ipmi_driver.driver); printk(KERN_WARNING "ipmi_si: Unable to find any System Interface(s)\n"); return -ENODEV; @@ -3151,7 +3153,7 @@ static __exit void cleanup_ipmi_si(void) cleanup_one_si(e); mutex_unlock(&smi_infos_lock); - driver_unregister(&ipmi_driver); + driver_unregister(&ipmi_driver.driver); } module_exit(cleanup_ipmi_si); diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_watchdog.c index 235fab0bdf79..a4d57e31f713 100644 --- a/drivers/char/ipmi/ipmi_watchdog.c +++ b/drivers/char/ipmi/ipmi_watchdog.c @@ -870,7 +870,6 @@ static int ipmi_close(struct inode *ino, struct file *filep) clear_bit(0, &ipmi_wdog_open); } - ipmi_fasync(-1, filep, 0); expect_close = 0; return 0; diff --git a/drivers/char/isicom.c b/drivers/char/isicom.c index 7d30ee1d3fca..04e4549299ba 100644 --- a/drivers/char/isicom.c +++ b/drivers/char/isicom.c @@ -7,12 +7,14 @@ * Original driver code supplied by Multi-Tech * * Changes - * 1/9/98 alan@redhat.com Merge to 2.0.x kernel tree + * 1/9/98 alan@lxorguk.ukuu.org.uk + * Merge to 2.0.x kernel tree * Obtain and use official major/minors * Loader switched to a misc device * (fixed range check bug as a side effect) * Printk clean up - * 9/12/98 alan@redhat.com Rough port to 2.1.x + * 9/12/98 alan@lxorguk.ukuu.org.uk + * Rough port to 2.1.x * * 10/6/99 sameer Merged the ISA and PCI drivers to * a new unified driver. diff --git a/drivers/char/istallion.c b/drivers/char/istallion.c index 44e5d60f517e..4b10770fa937 100644 --- a/drivers/char/istallion.c +++ b/drivers/char/istallion.c @@ -3739,7 +3739,7 @@ static int stli_getbrdnr(void) * do is go probing around in the usual places hoping we can find it. */ -static int stli_findeisabrds(void) +static int __init stli_findeisabrds(void) { struct stlibrd *brdp; unsigned int iobase, eid, i; @@ -3935,7 +3935,7 @@ static struct stlibrd *stli_allocbrd(void) * can find. */ -static int stli_initbrds(void) +static int __init stli_initbrds(void) { struct stlibrd *brdp, *nxtbrdp; struct stlconf conf; diff --git a/drivers/char/mxser.c b/drivers/char/mxser.c index 8beef50f95a0..047766915411 100644 --- a/drivers/char/mxser.c +++ b/drivers/char/mxser.c @@ -14,7 +14,8 @@ * (at your option) any later version. * * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox - * . The original 1.8 code is available on www.moxa.com. + * . The original 1.8 code is available on + * www.moxa.com. * - Fixed x86_64 cleanness */ diff --git a/drivers/char/pcmcia/synclink_cs.c b/drivers/char/pcmcia/synclink_cs.c index 9a626e50b793..4d64a02612a4 100644 --- a/drivers/char/pcmcia/synclink_cs.c +++ b/drivers/char/pcmcia/synclink_cs.c @@ -554,7 +554,7 @@ static int mgslpc_probe(struct pcmcia_device *link) /* Initialize the struct pcmcia_device structure */ /* Interrupt setup */ - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE; + link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING; link->irq.IRQInfo1 = IRQ_LEVEL_ID; link->irq.Handler = NULL; diff --git a/drivers/char/random.c b/drivers/char/random.c index 705a839f1796..675076f5fca8 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -1139,18 +1139,12 @@ static int random_fasync(int fd, struct file *filp, int on) return fasync_helper(fd, filp, on, &fasync); } -static int random_release(struct inode *inode, struct file *filp) -{ - return fasync_helper(-1, filp, 0, &fasync); -} - const struct file_operations random_fops = { .read = random_read, .write = random_write, .poll = random_poll, .unlocked_ioctl = random_ioctl, .fasync = random_fasync, - .release = random_release, }; const struct file_operations urandom_fops = { @@ -1158,7 +1152,6 @@ const struct file_operations urandom_fops = { .write = random_write, .unlocked_ioctl = random_ioctl, .fasync = random_fasync, - .release = random_release, }; /*************************************************************** diff --git a/drivers/char/rtc.c b/drivers/char/rtc.c index 32dc89720d58..20d6efb6324e 100644 --- a/drivers/char/rtc.c +++ b/drivers/char/rtc.c @@ -788,8 +788,6 @@ static int rtc_release(struct inode *inode, struct file *file) } spin_unlock_irq(&rtc_lock); - if (file->f_flags & FASYNC) - rtc_fasync(-1, file, 0); no_irq: #endif diff --git a/drivers/char/serial167.c b/drivers/char/serial167.c index 3b23270eaa65..a8f15e6be594 100644 --- a/drivers/char/serial167.c +++ b/drivers/char/serial167.c @@ -418,7 +418,7 @@ static irqreturn_t cd2401_rxerr_interrupt(int irq, void *dev_id) TTY_OVERRUN); /* If the flip buffer itself is - overflowing, we still loose + overflowing, we still lose the next incoming character. */ if (tty_buffer_request_room(tty, 1) != diff --git a/drivers/char/sonypi.c b/drivers/char/sonypi.c index 85e0eb76eeab..f4374437a033 100644 --- a/drivers/char/sonypi.c +++ b/drivers/char/sonypi.c @@ -523,7 +523,7 @@ static int acpi_driver_registered; static int sonypi_ec_write(u8 addr, u8 value) { -#ifdef CONFIG_ACPI_EC +#ifdef CONFIG_ACPI if (SONYPI_ACPI_ACTIVE) return ec_write(addr, value); #endif @@ -539,7 +539,7 @@ static int sonypi_ec_write(u8 addr, u8 value) static int sonypi_ec_read(u8 addr, u8 *value) { -#ifdef CONFIG_ACPI_EC +#ifdef CONFIG_ACPI if (SONYPI_ACPI_ACTIVE) return ec_read(addr, value); #endif @@ -898,7 +898,6 @@ static int sonypi_misc_fasync(int fd, struct file *filp, int on) static int sonypi_misc_release(struct inode *inode, struct file *file) { - sonypi_misc_fasync(-1, file, 0); mutex_lock(&sonypi_device.lock); sonypi_device.open_count--; mutex_unlock(&sonypi_device.lock); diff --git a/drivers/char/specialix.c b/drivers/char/specialix.c index 242fd46fda22..a16b94f12eb2 100644 --- a/drivers/char/specialix.c +++ b/drivers/char/specialix.c @@ -72,7 +72,7 @@ /* * There is a bunch of documentation about the card, jumpers, config * settings, restrictions, cables, device names and numbers in - * Documentation/specialix.txt + * Documentation/serial/specialix.txt */ #include diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c index 59f472143f08..1412a8d1e58d 100644 --- a/drivers/char/tty_io.c +++ b/drivers/char/tty_io.c @@ -1795,12 +1795,15 @@ retry_open: } #endif if (device == MKDEV(TTYAUX_MAJOR, 1)) { - driver = tty_driver_kref_get(console_device(&index)); - if (driver) { - /* Don't let /dev/console block */ - filp->f_flags |= O_NONBLOCK; - noctty = 1; - goto got_driver; + struct tty_driver *console_driver = console_device(&index); + if (console_driver) { + driver = tty_driver_kref_get(console_driver); + if (driver) { + /* Don't let /dev/console block */ + filp->f_flags |= O_NONBLOCK; + noctty = 1; + goto got_driver; + } } mutex_unlock(&tty_mutex); return -ENODEV; diff --git a/drivers/char/vt.c b/drivers/char/vt.c index d8f83e26e4a4..008176edbd64 100644 --- a/drivers/char/vt.c +++ b/drivers/char/vt.c @@ -1644,7 +1644,10 @@ static void reset_terminal(struct vc_data *vc, int do_clear) vc->vc_tab_stop[1] = vc->vc_tab_stop[2] = vc->vc_tab_stop[3] = - vc->vc_tab_stop[4] = 0x01010101; + vc->vc_tab_stop[4] = + vc->vc_tab_stop[5] = + vc->vc_tab_stop[6] = + vc->vc_tab_stop[7] = 0x01010101; vc->vc_bell_pitch = DEFAULT_BELL_PITCH; vc->vc_bell_duration = DEFAULT_BELL_DURATION; @@ -1935,7 +1938,10 @@ static void do_con_trol(struct tty_struct *tty, struct vc_data *vc, int c) vc->vc_tab_stop[1] = vc->vc_tab_stop[2] = vc->vc_tab_stop[3] = - vc->vc_tab_stop[4] = 0; + vc->vc_tab_stop[4] = + vc->vc_tab_stop[5] = + vc->vc_tab_stop[6] = + vc->vc_tab_stop[7] = 0; } return; case 'm': @@ -2268,7 +2274,7 @@ rescan_last_byte: continue; /* nothing to display */ } /* Glyph not found */ - if ((!(vc->vc_utf && !vc->vc_disp_ctrl) || c < 128) && !(c & ~charmask)) { + if ((!(vc->vc_utf && !vc->vc_disp_ctrl) && c < 128) && !(c & ~charmask)) { /* In legacy mode use the glyph we get by a 1:1 mapping. This would make absolutely no sense with Unicode in mind, but do this for ASCII characters since a font may lack diff --git a/drivers/char/xilinx_hwicap/buffer_icap.c b/drivers/char/xilinx_hwicap/buffer_icap.c index aa7f7962a9a0..05d897764f02 100644 --- a/drivers/char/xilinx_hwicap/buffer_icap.c +++ b/drivers/char/xilinx_hwicap/buffer_icap.c @@ -21,9 +21,6 @@ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * * (c) Copyright 2003-2008 Xilinx Inc. * All rights reserved. * diff --git a/drivers/char/xilinx_hwicap/buffer_icap.h b/drivers/char/xilinx_hwicap/buffer_icap.h index 8b0252bf06e2..d4f419ee87ab 100644 --- a/drivers/char/xilinx_hwicap/buffer_icap.h +++ b/drivers/char/xilinx_hwicap/buffer_icap.h @@ -21,9 +21,6 @@ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * * (c) Copyright 2003-2008 Xilinx Inc. * All rights reserved. * diff --git a/drivers/char/xilinx_hwicap/fifo_icap.c b/drivers/char/xilinx_hwicap/fifo_icap.c index 776b50528478..02225eb19cf6 100644 --- a/drivers/char/xilinx_hwicap/fifo_icap.c +++ b/drivers/char/xilinx_hwicap/fifo_icap.c @@ -21,9 +21,6 @@ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * * (c) Copyright 2007-2008 Xilinx Inc. * All rights reserved. * diff --git a/drivers/char/xilinx_hwicap/fifo_icap.h b/drivers/char/xilinx_hwicap/fifo_icap.h index 62bda453c90b..4c9dd9a3b62a 100644 --- a/drivers/char/xilinx_hwicap/fifo_icap.h +++ b/drivers/char/xilinx_hwicap/fifo_icap.h @@ -21,9 +21,6 @@ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * * (c) Copyright 2007-2008 Xilinx Inc. * All rights reserved. * diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.c b/drivers/char/xilinx_hwicap/xilinx_hwicap.c index ed132fe55d3d..f40ab699860f 100644 --- a/drivers/char/xilinx_hwicap/xilinx_hwicap.c +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.c @@ -21,9 +21,6 @@ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * * (c) Copyright 2002 Xilinx Inc., Systems Engineering Group * (c) Copyright 2004 Xilinx Inc., Systems Engineering Group * (c) Copyright 2007-2008 Xilinx Inc. @@ -626,7 +623,7 @@ static int __devinit hwicap_setup(struct device *dev, int id, if (!request_mem_region(drvdata->mem_start, drvdata->mem_size, DRIVER_NAME)) { dev_err(dev, "Couldn't lock memory region at %Lx\n", - regs_res->start); + (unsigned long long) regs_res->start); retval = -EBUSY; goto failed1; } @@ -645,9 +642,10 @@ static int __devinit hwicap_setup(struct device *dev, int id, mutex_init(&drvdata->sem); drvdata->is_open = 0; - dev_info(dev, "ioremap %lx to %p with size %Lx\n", - (unsigned long int)drvdata->mem_start, - drvdata->base_address, drvdata->mem_size); + dev_info(dev, "ioremap %llx to %p with size %llx\n", + (unsigned long long) drvdata->mem_start, + drvdata->base_address, + (unsigned long long) drvdata->mem_size); cdev_init(&drvdata->cdev, &hwicap_fops); drvdata->cdev.owner = THIS_MODULE; diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.h b/drivers/char/xilinx_hwicap/xilinx_hwicap.h index 24d0d9b938fb..8cca11981c5f 100644 --- a/drivers/char/xilinx_hwicap/xilinx_hwicap.h +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.h @@ -21,9 +21,6 @@ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE. * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * * (c) Copyright 2003-2007 Xilinx Inc. * All rights reserved. * diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index 5bed73329ef8..8504a2108557 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -65,12 +65,14 @@ static void cpuidle_idle_call(void) return; } +#if 0 + /* shows regressions, re-enable for 2.6.29 */ /* * run any timers that can be run now, at this point * before calculating the idle duration etc. */ hrtimer_peek_ahead_timers(); - +#endif /* ask the governor for the next state */ next_state = cpuidle_curr_governor->select(dev); if (need_resched()) diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index b6ad3ac5916e..24607669a52b 100644 --- a/drivers/crypto/talitos.c +++ b/drivers/crypto/talitos.c @@ -1357,7 +1357,7 @@ static int hw_supports(struct device *dev, __be32 desc_hdr_template) return ret; } -static int __devexit talitos_remove(struct of_device *ofdev) +static int talitos_remove(struct of_device *ofdev) { struct device *dev = &ofdev->dev; struct talitos_private *priv = dev_get_drvdata(dev); @@ -1622,7 +1622,7 @@ static struct of_platform_driver talitos_driver = { .name = "talitos", .match_table = talitos_match, .probe = talitos_probe, - .remove = __devexit_p(talitos_remove), + .remove = talitos_remove, }; static int __init talitos_init(void) diff --git a/drivers/dca/dca-core.c b/drivers/dca/dca-core.c index ec249d2db633..d883e1b8bb8c 100644 --- a/drivers/dca/dca-core.c +++ b/drivers/dca/dca-core.c @@ -270,6 +270,6 @@ static void __exit dca_exit(void) dca_sysfs_exit(); } -module_init(dca_init); +subsys_initcall(dca_init); module_exit(dca_exit); diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index dc003a3a787d..657996517374 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -388,7 +388,10 @@ int dma_async_device_register(struct dma_device *device) init_completion(&device->done); kref_init(&device->refcount); + + mutex_lock(&dma_list_mutex); device->dev_id = id++; + mutex_unlock(&dma_list_mutex); /* represent channels in sysfs. Probably want devs too */ list_for_each_entry(chan, &device->channels, device_node) { @@ -399,8 +402,8 @@ int dma_async_device_register(struct dma_device *device) chan->chan_id = chancnt++; chan->dev.class = &dma_devclass; chan->dev.parent = device->dev; - snprintf(chan->dev.bus_id, BUS_ID_SIZE, "dma%dchan%d", - device->dev_id, chan->chan_id); + dev_set_name(&chan->dev, "dma%dchan%d", + device->dev_id, chan->chan_id); rc = device_register(&chan->dev); if (rc) { diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index d1e381e35a9e..ed9636bfb54a 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -20,11 +20,11 @@ static unsigned int test_buf_size = 16384; module_param(test_buf_size, uint, S_IRUGO); MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); -static char test_channel[BUS_ID_SIZE]; +static char test_channel[20]; module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO); MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); -static char test_device[BUS_ID_SIZE]; +static char test_device[20]; module_param_string(device, test_device, sizeof(test_device), S_IRUGO); MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); @@ -80,14 +80,14 @@ static bool dmatest_match_channel(struct dma_chan *chan) { if (test_channel[0] == '\0') return true; - return strcmp(chan->dev.bus_id, test_channel) == 0; + return strcmp(dev_name(&chan->dev), test_channel) == 0; } static bool dmatest_match_device(struct dma_device *device) { if (test_device[0] == '\0') return true; - return strcmp(device->dev->bus_id, test_device) == 0; + return strcmp(dev_name(device->dev), test_device) == 0; } static unsigned long dmatest_random(void) @@ -332,7 +332,7 @@ static enum dma_state_client dmatest_add_channel(struct dma_chan *chan) dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); if (!dtc) { - pr_warning("dmatest: No memory for %s\n", chan->dev.bus_id); + pr_warning("dmatest: No memory for %s\n", dev_name(&chan->dev)); return DMA_NAK; } @@ -343,16 +343,16 @@ static enum dma_state_client dmatest_add_channel(struct dma_chan *chan) thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); if (!thread) { pr_warning("dmatest: No memory for %s-test%u\n", - chan->dev.bus_id, i); + dev_name(&chan->dev), i); break; } thread->chan = dtc->chan; smp_wmb(); thread->task = kthread_run(dmatest_func, thread, "%s-test%u", - chan->dev.bus_id, i); + dev_name(&chan->dev), i); if (IS_ERR(thread->task)) { pr_warning("dmatest: Failed to run thread %s-test%u\n", - chan->dev.bus_id, i); + dev_name(&chan->dev), i); kfree(thread); break; } @@ -362,7 +362,7 @@ static enum dma_state_client dmatest_add_channel(struct dma_chan *chan) list_add_tail(&thread->node, &dtc->threads); } - pr_info("dmatest: Started %u threads using %s\n", i, chan->dev.bus_id); + pr_info("dmatest: Started %u threads using %s\n", i, dev_name(&chan->dev)); list_add_tail(&dtc->node, &dmatest_channels); nr_channels++; @@ -379,7 +379,7 @@ static enum dma_state_client dmatest_remove_channel(struct dma_chan *chan) list_del(&dtc->node); dmatest_cleanup_channel(dtc); pr_debug("dmatest: lost channel %s\n", - chan->dev.bus_id); + dev_name(&chan->dev)); return DMA_ACK; } } @@ -418,7 +418,7 @@ dmatest_event(struct dma_client *client, struct dma_chan *chan, default: pr_info("dmatest: Unhandled event %u (%s)\n", - state, chan->dev.bus_id); + state, dev_name(&chan->dev)); break; } diff --git a/drivers/dma/ioat_dma.c b/drivers/dma/ioat_dma.c index 43b8cefad2c6..6607fdd00b1c 100644 --- a/drivers/dma/ioat_dma.c +++ b/drivers/dma/ioat_dma.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "ioatdma.h" #include "ioatdma_registers.h" #include "ioatdma_hw.h" @@ -171,8 +172,10 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); -#if CONFIG_I7300_IDLE_IOAT_CHANNEL - device->common.chancnt--; +#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL + if (i7300_idle_platform_probe(NULL, NULL) == 0) { + device->common.chancnt--; + } #endif for (i = 0; i < device->common.chancnt; i++) { ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL); @@ -522,7 +525,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) } hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - if (new->async_tx.callback) { + if (first->async_tx.callback) { hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; if (first != new) { /* move callback into to last desc */ @@ -614,7 +617,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) } hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - if (new->async_tx.callback) { + if (first->async_tx.callback) { hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; if (first != new) { /* move callback into to last desc */ @@ -804,6 +807,12 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) struct ioat_desc_sw *desc, *_desc; int in_use_descs = 0; + /* Before freeing channel resources first check + * if they have been previously allocated for this channel. + */ + if (ioat_chan->desccount == 0) + return; + tasklet_disable(&ioat_chan->cleanup_task); ioat_dma_memcpy_cleanup(ioat_chan); @@ -866,6 +875,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) ioat_chan->last_completion = ioat_chan->completion_addr = 0; ioat_chan->pending = 0; ioat_chan->dmacount = 0; + ioat_chan->desccount = 0; ioat_chan->watchdog_completion = 0; ioat_chan->last_compl_desc_addr_hw = 0; ioat_chan->watchdog_tcp_cookie = @@ -1331,10 +1341,12 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) */ #define IOAT_TEST_SIZE 2000 +DECLARE_COMPLETION(test_completion); static void ioat_dma_test_callback(void *dma_async_param) { printk(KERN_ERR "ioatdma: ioat_dma_test_callback(%p)\n", dma_async_param); + complete(&test_completion); } /** @@ -1400,7 +1412,8 @@ static int ioat_dma_self_test(struct ioatdma_device *device) goto free_resources; } device->common.device_issue_pending(dma_chan); - msleep(1); + + wait_for_completion_timeout(&test_completion, msecs_to_jiffies(3000)); if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 71fba82462cb..6be317262200 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -85,18 +85,28 @@ iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, enum dma_ctrl_flags flags = desc->async_tx.flags; u32 src_cnt; dma_addr_t addr; + dma_addr_t dest; + src_cnt = unmap->unmap_src_cnt; + dest = iop_desc_get_dest_addr(unmap, iop_chan); if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - addr = iop_desc_get_dest_addr(unmap, iop_chan); - dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE); + enum dma_data_direction dir; + + if (src_cnt > 1) /* is xor? */ + dir = DMA_BIDIRECTIONAL; + else + dir = DMA_FROM_DEVICE; + + dma_unmap_page(dev, dest, len, dir); } if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - src_cnt = unmap->unmap_src_cnt; while (src_cnt--) { addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt); + if (addr == dest) + continue; dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); } @@ -411,6 +421,7 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) int slot_cnt; int slots_per_op; dma_cookie_t cookie; + dma_addr_t next_dma; grp_start = sw_desc->group_head; slot_cnt = grp_start->slot_cnt; @@ -425,12 +436,12 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) &old_chain_tail->chain_node); /* fix up the hardware chain */ - iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys); + next_dma = grp_start->async_tx.phys; + iop_desc_set_next_desc(old_chain_tail, next_dma); + BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */ - /* 1/ don't add pre-chained descriptors - * 2/ dummy read to flush next_desc write - */ - BUG_ON(iop_desc_get_next_desc(sw_desc)); + /* check for pre-chained descriptors */ + iop_paranoia(iop_desc_get_next_desc(sw_desc)); /* increment the pending count by the number of slots * memcpy operations have a 1:1 (slot:operation) relation diff --git a/drivers/dma/iovlock.c b/drivers/dma/iovlock.c index e763d723e4cf..9f6fe46a9b87 100644 --- a/drivers/dma/iovlock.c +++ b/drivers/dma/iovlock.c @@ -55,7 +55,6 @@ struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len) int nr_iovecs = 0; int iovec_len_used = 0; int iovec_pages_used = 0; - long err; /* don't pin down non-user-based iovecs */ if (segment_eq(get_fs(), KERNEL_DS)) @@ -72,23 +71,21 @@ struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len) local_list = kmalloc(sizeof(*local_list) + (nr_iovecs * sizeof (struct dma_page_list)) + (iovec_pages_used * sizeof (struct page*)), GFP_KERNEL); - if (!local_list) { - err = -ENOMEM; + if (!local_list) goto out; - } /* list of pages starts right after the page list array */ pages = (struct page **) &local_list->page_list[nr_iovecs]; + local_list->nr_iovecs = 0; + for (i = 0; i < nr_iovecs; i++) { struct dma_page_list *page_list = &local_list->page_list[i]; len -= iov[i].iov_len; - if (!access_ok(VERIFY_WRITE, iov[i].iov_base, iov[i].iov_len)) { - err = -EFAULT; + if (!access_ok(VERIFY_WRITE, iov[i].iov_base, iov[i].iov_len)) goto unpin; - } page_list->nr_pages = num_pages_spanned(&iov[i]); page_list->base_address = iov[i].iov_base; @@ -109,10 +106,8 @@ struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len) NULL); up_read(¤t->mm->mmap_sem); - if (ret != page_list->nr_pages) { - err = -ENOMEM; + if (ret != page_list->nr_pages) goto unpin; - } local_list->nr_iovecs = i + 1; } @@ -122,7 +117,7 @@ struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len) unpin: dma_unpin_iovec_pages(local_list); out: - return ERR_PTR(err); + return NULL; } void dma_unpin_iovec_pages(struct dma_pinned_list *pinned_list) diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 0328da020a10..bcda17426411 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -311,17 +311,26 @@ mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, enum dma_ctrl_flags flags = desc->async_tx.flags; u32 src_cnt; dma_addr_t addr; + dma_addr_t dest; + src_cnt = unmap->unmap_src_cnt; + dest = mv_desc_get_dest_addr(unmap); if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - addr = mv_desc_get_dest_addr(unmap); - dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE); + enum dma_data_direction dir; + + if (src_cnt > 1) /* is xor ? */ + dir = DMA_BIDIRECTIONAL; + else + dir = DMA_FROM_DEVICE; + dma_unmap_page(dev, dest, len, dir); } if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - src_cnt = unmap->unmap_src_cnt; while (src_cnt--) { addr = mv_desc_get_src_addr(unmap, src_cnt); + if (addr == dest) + continue; dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); } diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 5a11e3cbcae2..e0dbd388757f 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -102,6 +102,13 @@ config EDAC_I3000 Support for error detection and correction on the Intel 3000 and 3010 server chipsets. +config EDAC_X38 + tristate "Intel X38" + depends on EDAC_MM_EDAC && PCI && X86 + help + Support for error detection and correction on the Intel + X38 server chipsets. + config EDAC_I82860 tristate "Intel 82860" depends on EDAC_MM_EDAC && PCI && X86_32 diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index e5e9104b5520..62c2d9bad8dc 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_EDAC_I82443BXGX) += i82443bxgx_edac.o obj-$(CONFIG_EDAC_I82875P) += i82875p_edac.o obj-$(CONFIG_EDAC_I82975X) += i82975x_edac.o obj-$(CONFIG_EDAC_I3000) += i3000_edac.o +obj-$(CONFIG_EDAC_X38) += x38_edac.o obj-$(CONFIG_EDAC_I82860) += i82860_edac.o obj-$(CONFIG_EDAC_R82600) += r82600_edac.o obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o diff --git a/drivers/edac/cell_edac.c b/drivers/edac/cell_edac.c index 887072f5dc8b..cd2e3b8087e7 100644 --- a/drivers/edac/cell_edac.c +++ b/drivers/edac/cell_edac.c @@ -9,6 +9,7 @@ */ #undef DEBUG +#include #include #include #include @@ -164,6 +165,8 @@ static int __devinit cell_edac_probe(struct platform_device *pdev) if (regs == NULL) return -ENODEV; + edac_op_state = EDAC_OPSTATE_POLL; + /* Get channel population */ reg = in_be64(®s->mic_mnt_cfg); dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016lx\n", reg); diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c index f0d9b415db50..d335086f4a26 100644 --- a/drivers/edac/i5000_edac.c +++ b/drivers/edac/i5000_edac.c @@ -1381,6 +1381,7 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx) if (mci == NULL) return -ENOMEM; + kobject_get(&mci->edac_mci_kobj); debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); mci->dev = &pdev->dev; /* record ptr to the generic device */ @@ -1453,6 +1454,7 @@ fail1: i5000_put_devices(mci); fail0: + kobject_put(&mci->edac_mci_kobj); edac_mc_free(mci); return -ENODEV; } @@ -1498,7 +1500,7 @@ static void __devexit i5000_remove_one(struct pci_dev *pdev) /* retrieve references to resources, and free those resources */ i5000_put_devices(mci); - + kobject_put(&mci->edac_mci_kobj); edac_mc_free(mci); } diff --git a/drivers/edac/i82875p_edac.c b/drivers/edac/i82875p_edac.c index e43bdc43a1bf..ebb037b78758 100644 --- a/drivers/edac/i82875p_edac.c +++ b/drivers/edac/i82875p_edac.c @@ -182,8 +182,6 @@ static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has * already registered driver */ -static int i82875p_registered = 1; - static struct edac_pci_ctl_info *i82875p_pci; static void i82875p_get_error_info(struct mem_ctl_info *mci, @@ -295,6 +293,7 @@ static int i82875p_setup_overfl_dev(struct pci_dev *pdev, "%s(): pci_bus_add_device() Failed\n", __func__); } + pci_bus_assign_resources(dev->bus); } *ovrfl_pdev = dev; @@ -409,6 +408,9 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx) goto fail0; } + /* Keeps mci available after edac_mc_del_mc() till edac_mc_free() */ + kobject_get(&mci->edac_mci_kobj); + debugf3("%s(): init mci\n", __func__); mci->dev = &pdev->dev; mci->mtype_cap = MEM_FLAG_DDR; @@ -451,6 +453,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx) return 0; fail1: + kobject_put(&mci->edac_mci_kobj); edac_mc_free(mci); fail0: @@ -578,12 +581,11 @@ static void __exit i82875p_exit(void) { debugf3("%s()\n", __func__); + i82875p_remove_one(mci_pdev); + pci_dev_put(mci_pdev); + pci_unregister_driver(&i82875p_driver); - if (!i82875p_registered) { - i82875p_remove_one(mci_pdev); - pci_dev_put(mci_pdev); - } } module_init(i82875p_init); diff --git a/drivers/edac/x38_edac.c b/drivers/edac/x38_edac.c new file mode 100644 index 000000000000..2406c2ce2844 --- /dev/null +++ b/drivers/edac/x38_edac.c @@ -0,0 +1,524 @@ +/* + * Intel X38 Memory Controller kernel module + * Copyright (C) 2008 Cluster Computing, Inc. + * + * This file may be distributed under the terms of the + * GNU General Public License. + * + * This file is based on i3200_edac.c + * + */ + +#include +#include +#include +#include +#include +#include +#include "edac_core.h" + +#define X38_REVISION "1.1" + +#define EDAC_MOD_STR "x38_edac" + +#define PCI_DEVICE_ID_INTEL_X38_HB 0x29e0 + +#define X38_RANKS 8 +#define X38_RANKS_PER_CHANNEL 4 +#define X38_CHANNELS 2 + +/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */ + +#define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */ +#define X38_MCHBAR_HIGH 0x4b +#define X38_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */ +#define X38_MMR_WINDOW_SIZE 16384 + +#define X38_TOM 0xa0 /* Top of Memory (16b) + * + * 15:10 reserved + * 9:0 total populated physical memory + */ +#define X38_TOM_MASK 0x3ff /* bits 9:0 */ +#define X38_TOM_SHIFT 26 /* 64MiB grain */ + +#define X38_ERRSTS 0xc8 /* Error Status Register (16b) + * + * 15 reserved + * 14 Isochronous TBWRR Run Behind FIFO Full + * (ITCV) + * 13 Isochronous TBWRR Run Behind FIFO Put + * (ITSTV) + * 12 reserved + * 11 MCH Thermal Sensor Event + * for SMI/SCI/SERR (GTSE) + * 10 reserved + * 9 LOCK to non-DRAM Memory Flag (LCKF) + * 8 reserved + * 7 DRAM Throttle Flag (DTF) + * 6:2 reserved + * 1 Multi-bit DRAM ECC Error Flag (DMERR) + * 0 Single-bit DRAM ECC Error Flag (DSERR) + */ +#define X38_ERRSTS_UE 0x0002 +#define X38_ERRSTS_CE 0x0001 +#define X38_ERRSTS_BITS (X38_ERRSTS_UE | X38_ERRSTS_CE) + + +/* Intel MMIO register space - device 0 function 0 - MMR space */ + +#define X38_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4) + * + * 15:10 reserved + * 9:0 Channel 0 DRAM Rank Boundary Address + */ +#define X38_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */ +#define X38_DRB_MASK 0x3ff /* bits 9:0 */ +#define X38_DRB_SHIFT 26 /* 64MiB grain */ + +#define X38_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b) + * + * 63:48 Error Column Address (ERRCOL) + * 47:32 Error Row Address (ERRROW) + * 31:29 Error Bank Address (ERRBANK) + * 28:27 Error Rank Address (ERRRANK) + * 26:24 reserved + * 23:16 Error Syndrome (ERRSYND) + * 15: 2 reserved + * 1 Multiple Bit Error Status (MERRSTS) + * 0 Correctable Error Status (CERRSTS) + */ +#define X38_C1ECCERRLOG 0x680 /* Channel 1 ECC Error Log (64b) */ +#define X38_ECCERRLOG_CE 0x1 +#define X38_ECCERRLOG_UE 0x2 +#define X38_ECCERRLOG_RANK_BITS 0x18000000 +#define X38_ECCERRLOG_SYNDROME_BITS 0xff0000 + +#define X38_CAPID0 0xe0 /* see P.94 of spec for details */ + +static int x38_channel_num; + +static int how_many_channel(struct pci_dev *pdev) +{ + unsigned char capid0_8b; /* 8th byte of CAPID0 */ + + pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b); + if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */ + debugf0("In single channel mode.\n"); + x38_channel_num = 1; + } else { + debugf0("In dual channel mode.\n"); + x38_channel_num = 2; + } + + return x38_channel_num; +} + +static unsigned long eccerrlog_syndrome(u64 log) +{ + return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16; +} + +static int eccerrlog_row(int channel, u64 log) +{ + return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) | + (channel * X38_RANKS_PER_CHANNEL); +} + +enum x38_chips { + X38 = 0, +}; + +struct x38_dev_info { + const char *ctl_name; +}; + +struct x38_error_info { + u16 errsts; + u16 errsts2; + u64 eccerrlog[X38_CHANNELS]; +}; + +static const struct x38_dev_info x38_devs[] = { + [X38] = { + .ctl_name = "x38"}, +}; + +static struct pci_dev *mci_pdev; +static int x38_registered = 1; + + +static void x38_clear_error_info(struct mem_ctl_info *mci) +{ + struct pci_dev *pdev; + + pdev = to_pci_dev(mci->dev); + + /* + * Clear any error bits. + * (Yes, we really clear bits by writing 1 to them.) + */ + pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS, + X38_ERRSTS_BITS); +} + +static u64 x38_readq(const void __iomem *addr) +{ + return readl(addr) | (((u64)readl(addr + 4)) << 32); +} + +static void x38_get_and_clear_error_info(struct mem_ctl_info *mci, + struct x38_error_info *info) +{ + struct pci_dev *pdev; + void __iomem *window = mci->pvt_info; + + pdev = to_pci_dev(mci->dev); + + /* + * This is a mess because there is no atomic way to read all the + * registers at once and the registers can transition from CE being + * overwritten by UE. + */ + pci_read_config_word(pdev, X38_ERRSTS, &info->errsts); + if (!(info->errsts & X38_ERRSTS_BITS)) + return; + + info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG); + if (x38_channel_num == 2) + info->eccerrlog[1] = x38_readq(window + X38_C1ECCERRLOG); + + pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2); + + /* + * If the error is the same for both reads then the first set + * of reads is valid. If there is a change then there is a CE + * with no info and the second set of reads is valid and + * should be UE info. + */ + if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) { + info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG); + if (x38_channel_num == 2) + info->eccerrlog[1] = + x38_readq(window + X38_C1ECCERRLOG); + } + + x38_clear_error_info(mci); +} + +static void x38_process_error_info(struct mem_ctl_info *mci, + struct x38_error_info *info) +{ + int channel; + u64 log; + + if (!(info->errsts & X38_ERRSTS_BITS)) + return; + + if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) { + edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); + info->errsts = info->errsts2; + } + + for (channel = 0; channel < x38_channel_num; channel++) { + log = info->eccerrlog[channel]; + if (log & X38_ECCERRLOG_UE) { + edac_mc_handle_ue(mci, 0, 0, + eccerrlog_row(channel, log), "x38 UE"); + } else if (log & X38_ECCERRLOG_CE) { + edac_mc_handle_ce(mci, 0, 0, + eccerrlog_syndrome(log), + eccerrlog_row(channel, log), 0, "x38 CE"); + } + } +} + +static void x38_check(struct mem_ctl_info *mci) +{ + struct x38_error_info info; + + debugf1("MC%d: %s()\n", mci->mc_idx, __func__); + x38_get_and_clear_error_info(mci, &info); + x38_process_error_info(mci, &info); +} + + +void __iomem *x38_map_mchbar(struct pci_dev *pdev) +{ + union { + u64 mchbar; + struct { + u32 mchbar_low; + u32 mchbar_high; + }; + } u; + void __iomem *window; + + pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low); + pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1); + pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high); + u.mchbar &= X38_MCHBAR_MASK; + + if (u.mchbar != (resource_size_t)u.mchbar) { + printk(KERN_ERR + "x38: mmio space beyond accessible range (0x%llx)\n", + (unsigned long long)u.mchbar); + return NULL; + } + + window = ioremap_nocache(u.mchbar, X38_MMR_WINDOW_SIZE); + if (!window) + printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n", + (unsigned long long)u.mchbar); + + return window; +} + + +static void x38_get_drbs(void __iomem *window, + u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL]) +{ + int i; + + for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) { + drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK; + drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK; + } +} + +static bool x38_is_stacked(struct pci_dev *pdev, + u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL]) +{ + u16 tom; + + pci_read_config_word(pdev, X38_TOM, &tom); + tom &= X38_TOM_MASK; + + return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom; +} + +static unsigned long drb_to_nr_pages( + u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL], + bool stacked, int channel, int rank) +{ + int n; + + n = drbs[channel][rank]; + if (rank > 0) + n -= drbs[channel][rank - 1]; + if (stacked && (channel == 1) && drbs[channel][rank] == + drbs[channel][X38_RANKS_PER_CHANNEL - 1]) { + n -= drbs[0][X38_RANKS_PER_CHANNEL - 1]; + } + + n <<= (X38_DRB_SHIFT - PAGE_SHIFT); + return n; +} + +static int x38_probe1(struct pci_dev *pdev, int dev_idx) +{ + int rc; + int i; + struct mem_ctl_info *mci = NULL; + unsigned long last_page; + u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL]; + bool stacked; + void __iomem *window; + + debugf0("MC: %s()\n", __func__); + + window = x38_map_mchbar(pdev); + if (!window) + return -ENODEV; + + x38_get_drbs(window, drbs); + + how_many_channel(pdev); + + /* FIXME: unconventional pvt_info usage */ + mci = edac_mc_alloc(0, X38_RANKS, x38_channel_num, 0); + if (!mci) + return -ENOMEM; + + debugf3("MC: %s(): init mci\n", __func__); + + mci->dev = &pdev->dev; + mci->mtype_cap = MEM_FLAG_DDR2; + + mci->edac_ctl_cap = EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_SECDED; + + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = X38_REVISION; + mci->ctl_name = x38_devs[dev_idx].ctl_name; + mci->dev_name = pci_name(pdev); + mci->edac_check = x38_check; + mci->ctl_page_to_phys = NULL; + mci->pvt_info = window; + + stacked = x38_is_stacked(pdev, drbs); + + /* + * The dram rank boundary (DRB) reg values are boundary addresses + * for each DRAM rank with a granularity of 64MB. DRB regs are + * cumulative; the last one will contain the total memory + * contained in all ranks. + */ + last_page = -1UL; + for (i = 0; i < mci->nr_csrows; i++) { + unsigned long nr_pages; + struct csrow_info *csrow = &mci->csrows[i]; + + nr_pages = drb_to_nr_pages(drbs, stacked, + i / X38_RANKS_PER_CHANNEL, + i % X38_RANKS_PER_CHANNEL); + + if (nr_pages == 0) { + csrow->mtype = MEM_EMPTY; + continue; + } + + csrow->first_page = last_page + 1; + last_page += nr_pages; + csrow->last_page = last_page; + csrow->nr_pages = nr_pages; + + csrow->grain = nr_pages << PAGE_SHIFT; + csrow->mtype = MEM_DDR2; + csrow->dtype = DEV_UNKNOWN; + csrow->edac_mode = EDAC_UNKNOWN; + } + + x38_clear_error_info(mci); + + rc = -ENODEV; + if (edac_mc_add_mc(mci)) { + debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__); + goto fail; + } + + /* get this far and it's successful */ + debugf3("MC: %s(): success\n", __func__); + return 0; + +fail: + iounmap(window); + if (mci) + edac_mc_free(mci); + + return rc; +} + +static int __devinit x38_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + int rc; + + debugf0("MC: %s()\n", __func__); + + if (pci_enable_device(pdev) < 0) + return -EIO; + + rc = x38_probe1(pdev, ent->driver_data); + if (!mci_pdev) + mci_pdev = pci_dev_get(pdev); + + return rc; +} + +static void __devexit x38_remove_one(struct pci_dev *pdev) +{ + struct mem_ctl_info *mci; + + debugf0("%s()\n", __func__); + + mci = edac_mc_del_mc(&pdev->dev); + if (!mci) + return; + + iounmap(mci->pvt_info); + + edac_mc_free(mci); +} + +static const struct pci_device_id x38_pci_tbl[] __devinitdata = { + { + PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0, + X38}, + { + 0, + } /* 0 terminated list. */ +}; + +MODULE_DEVICE_TABLE(pci, x38_pci_tbl); + +static struct pci_driver x38_driver = { + .name = EDAC_MOD_STR, + .probe = x38_init_one, + .remove = __devexit_p(x38_remove_one), + .id_table = x38_pci_tbl, +}; + +static int __init x38_init(void) +{ + int pci_rc; + + debugf3("MC: %s()\n", __func__); + + /* Ensure that the OPSTATE is set correctly for POLL or NMI */ + opstate_init(); + + pci_rc = pci_register_driver(&x38_driver); + if (pci_rc < 0) + goto fail0; + + if (!mci_pdev) { + x38_registered = 0; + mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_X38_HB, NULL); + if (!mci_pdev) { + debugf0("x38 pci_get_device fail\n"); + pci_rc = -ENODEV; + goto fail1; + } + + pci_rc = x38_init_one(mci_pdev, x38_pci_tbl); + if (pci_rc < 0) { + debugf0("x38 init fail\n"); + pci_rc = -ENODEV; + goto fail1; + } + } + + return 0; + +fail1: + pci_unregister_driver(&x38_driver); + +fail0: + if (mci_pdev) + pci_dev_put(mci_pdev); + + return pci_rc; +} + +static void __exit x38_exit(void) +{ + debugf3("MC: %s()\n", __func__); + + pci_unregister_driver(&x38_driver); + if (!x38_registered) { + x38_remove_one(mci_pdev); + pci_dev_put(mci_pdev); + } +} + +module_init(x38_init); +module_exit(x38_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake"); +MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers"); + +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); diff --git a/drivers/firewire/fw-device.c b/drivers/firewire/fw-device.c index 3fccdd484100..6b9be42c7b98 100644 --- a/drivers/firewire/fw-device.c +++ b/drivers/firewire/fw-device.c @@ -587,8 +587,7 @@ static void create_units(struct fw_device *device) unit->device.bus = &fw_bus_type; unit->device.type = &fw_unit_type; unit->device.parent = &device->device; - snprintf(unit->device.bus_id, sizeof(unit->device.bus_id), - "%s.%d", device->device.bus_id, i++); + dev_set_name(&unit->device, "%s.%d", dev_name(&device->device), i++); init_fw_attribute_group(&unit->device, fw_unit_attributes, @@ -711,8 +710,7 @@ static void fw_device_init(struct work_struct *work) device->device.type = &fw_device_type; device->device.parent = device->card->device; device->device.devt = MKDEV(fw_cdev_major, minor); - snprintf(device->device.bus_id, sizeof(device->device.bus_id), - "fw%d", minor); + dev_set_name(&device->device, "fw%d", minor); init_fw_attribute_group(&device->device, fw_device_attributes, @@ -741,13 +739,13 @@ static void fw_device_init(struct work_struct *work) if (device->config_rom_retries) fw_notify("created device %s: GUID %08x%08x, S%d00, " "%d config ROM retries\n", - device->device.bus_id, + dev_name(&device->device), device->config_rom[3], device->config_rom[4], 1 << device->max_speed, device->config_rom_retries); else fw_notify("created device %s: GUID %08x%08x, S%d00\n", - device->device.bus_id, + dev_name(&device->device), device->config_rom[3], device->config_rom[4], 1 << device->max_speed); device->config_rom_retries = 0; @@ -883,12 +881,12 @@ static void fw_device_refresh(struct work_struct *work) FW_DEVICE_RUNNING) == FW_DEVICE_SHUTDOWN) goto gone; - fw_notify("refreshed device %s\n", device->device.bus_id); + fw_notify("refreshed device %s\n", dev_name(&device->device)); device->config_rom_retries = 0; goto out; give_up: - fw_notify("giving up on refresh of device %s\n", device->device.bus_id); + fw_notify("giving up on refresh of device %s\n", dev_name(&device->device)); gone: atomic_set(&device->state, FW_DEVICE_SHUTDOWN); fw_device_shutdown(work); diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c index 251416f2148f..ab9c01e462ef 100644 --- a/drivers/firewire/fw-ohci.c +++ b/drivers/firewire/fw-ohci.c @@ -476,6 +476,7 @@ static int ar_context_add_page(struct ar_context *ctx) if (ab == NULL) return -ENOMEM; + ab->next = NULL; memset(&ab->descriptor, 0, sizeof(ab->descriptor)); ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | DESCRIPTOR_STATUS | @@ -496,6 +497,21 @@ static int ar_context_add_page(struct ar_context *ctx) return 0; } +static void ar_context_release(struct ar_context *ctx) +{ + struct ar_buffer *ab, *ab_next; + size_t offset; + dma_addr_t ab_bus; + + for (ab = ctx->current_buffer; ab; ab = ab_next) { + ab_next = ab->next; + offset = offsetof(struct ar_buffer, data); + ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; + dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE, + ab, ab_bus); + } +} + #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) #define cond_le32_to_cpu(v) \ (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v)) @@ -958,6 +974,7 @@ at_context_queue_packet(struct context *ctx, struct fw_packet *packet) packet->ack = RCODE_SEND_ERROR; return -1; } + packet->payload_bus = payload_bus; d[2].req_count = cpu_to_le16(packet->payload_length); d[2].data_address = cpu_to_le32(payload_bus); @@ -1009,7 +1026,6 @@ static int handle_at_packet(struct context *context, struct driver_data *driver_data; struct fw_packet *packet; struct fw_ohci *ohci = context->ohci; - dma_addr_t payload_bus; int evt; if (last->transfer_status == 0) @@ -1022,9 +1038,8 @@ static int handle_at_packet(struct context *context, /* This packet was cancelled, just continue. */ return 1; - payload_bus = le32_to_cpu(last->data_address); - if (payload_bus != 0) - dma_unmap_single(ohci->card.device, payload_bus, + if (packet->payload_bus) + dma_unmap_single(ohci->card.device, packet->payload_bus, packet->payload_length, DMA_TO_DEVICE); evt = le16_to_cpu(last->transfer_status) & 0x1f; @@ -1681,6 +1696,10 @@ static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) if (packet->ack != 0) goto out; + if (packet->payload_bus) + dma_unmap_single(ohci->card.device, packet->payload_bus, + packet->payload_length, DMA_TO_DEVICE); + log_ar_at_event('T', packet->speed, packet->header, 0x20); driver_data->packet = NULL; packet->ack = RCODE_CANCELLED; @@ -2349,8 +2368,8 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); if (ohci == NULL) { - fw_error("Could not malloc fw_ohci data.\n"); - return -ENOMEM; + err = -ENOMEM; + goto fail; } fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); @@ -2359,7 +2378,7 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) err = pci_enable_device(dev); if (err) { - fw_error("Failed to enable OHCI hardware.\n"); + fw_error("Failed to enable OHCI hardware\n"); goto fail_free; } @@ -2427,9 +2446,8 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) ohci->ir_context_list = kzalloc(size, GFP_KERNEL); if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { - fw_error("Out of memory for it/ir contexts.\n"); err = -ENOMEM; - goto fail_registers; + goto fail_contexts; } /* self-id dma buffer allocation */ @@ -2438,9 +2456,8 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) &ohci->self_id_bus, GFP_KERNEL); if (ohci->self_id_cpu == NULL) { - fw_error("Out of memory for self ID buffer.\n"); err = -ENOMEM; - goto fail_registers; + goto fail_contexts; } bus_options = reg_read(ohci, OHCI1394_BusOptions); @@ -2454,15 +2471,19 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) goto fail_self_id; fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", - dev->dev.bus_id, version >> 16, version & 0xff); + dev_name(&dev->dev), version >> 16, version & 0xff); return 0; fail_self_id: dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, ohci->self_id_cpu, ohci->self_id_bus); - fail_registers: - kfree(ohci->it_context_list); + fail_contexts: kfree(ohci->ir_context_list); + kfree(ohci->it_context_list); + context_release(&ohci->at_response_ctx); + context_release(&ohci->at_request_ctx); + ar_context_release(&ohci->ar_response_ctx); + ar_context_release(&ohci->ar_request_ctx); pci_iounmap(dev, ohci->registers); fail_iomem: pci_release_region(dev, 0); @@ -2471,6 +2492,9 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) fail_free: kfree(&ohci->card); ohci_pmac_off(dev); + fail: + if (err == -ENOMEM) + fw_error("Out of memory\n"); return err; } @@ -2491,8 +2515,19 @@ static void pci_remove(struct pci_dev *dev) software_reset(ohci); free_irq(dev->irq, ohci); + + if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) + dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, + ohci->next_config_rom, ohci->next_config_rom_bus); + if (ohci->config_rom) + dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, + ohci->config_rom, ohci->config_rom_bus); dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, ohci->self_id_cpu, ohci->self_id_bus); + ar_context_release(&ohci->ar_request_ctx); + ar_context_release(&ohci->ar_response_ctx); + context_release(&ohci->at_request_ctx); + context_release(&ohci->at_response_ctx); kfree(ohci->it_context_list); kfree(ohci->ir_context_list); pci_iounmap(dev, ohci->registers); diff --git a/drivers/firewire/fw-sbp2.c b/drivers/firewire/fw-sbp2.c index ef0b9b419c27..e54403ee59e7 100644 --- a/drivers/firewire/fw-sbp2.c +++ b/drivers/firewire/fw-sbp2.c @@ -173,6 +173,9 @@ struct sbp2_target { int blocked; /* ditto */ }; +/* Impossible login_id, to detect logout attempt before successful login */ +#define INVALID_LOGIN_ID 0x10000 + /* * Per section 7.4.8 of the SBP-2 spec, a mgt_ORB_timeout value can be * provided in the config rom. Most devices do provide a value, which @@ -367,6 +370,11 @@ static const struct { .model = 0x000021, .workarounds = SBP2_WORKAROUND_FIX_CAPACITY, }, + /* iPod mini */ { + .firmware_revision = 0x0a2700, + .model = 0x000022, + .workarounds = SBP2_WORKAROUND_FIX_CAPACITY, + }, /* iPod mini */ { .firmware_revision = 0x0a2700, .model = 0x000023, @@ -788,9 +796,20 @@ static void sbp2_release_target(struct kref *kref) scsi_remove_device(sdev); scsi_device_put(sdev); } - sbp2_send_management_orb(lu, tgt->node_id, lu->generation, - SBP2_LOGOUT_REQUEST, lu->login_id, NULL); - + if (lu->login_id != INVALID_LOGIN_ID) { + int generation, node_id; + /* + * tgt->node_id may be obsolete here if we failed + * during initial login or after a bus reset where + * the topology changed. + */ + generation = device->generation; + smp_rmb(); /* node_id vs. generation */ + node_id = device->node_id; + sbp2_send_management_orb(lu, node_id, generation, + SBP2_LOGOUT_REQUEST, + lu->login_id, NULL); + } fw_core_remove_address_handler(&lu->address_handler); list_del(&lu->link); kfree(lu); @@ -805,19 +824,20 @@ static void sbp2_release_target(struct kref *kref) static struct workqueue_struct *sbp2_wq; +static void sbp2_target_put(struct sbp2_target *tgt) +{ + kref_put(&tgt->kref, sbp2_release_target); +} + /* * Always get the target's kref when scheduling work on one its units. * Each workqueue job is responsible to call sbp2_target_put() upon return. */ static void sbp2_queue_work(struct sbp2_logical_unit *lu, unsigned long delay) { - if (queue_delayed_work(sbp2_wq, &lu->work, delay)) - kref_get(&lu->tgt->kref); -} - -static void sbp2_target_put(struct sbp2_target *tgt) -{ - kref_put(&tgt->kref, sbp2_release_target); + kref_get(&lu->tgt->kref); + if (!queue_delayed_work(sbp2_wq, &lu->work, delay)) + sbp2_target_put(lu->tgt); } /* @@ -978,6 +998,7 @@ static int sbp2_add_logical_unit(struct sbp2_target *tgt, int lun_entry) lu->tgt = tgt; lu->lun = lun_entry & 0xffff; + lu->login_id = INVALID_LOGIN_ID; lu->retries = 0; lu->has_sdev = false; lu->blocked = false; @@ -1119,7 +1140,7 @@ static int sbp2_probe(struct device *dev) tgt->unit = unit; kref_init(&tgt->kref); INIT_LIST_HEAD(&tgt->lu_list); - tgt->bus_id = unit->device.bus_id; + tgt->bus_id = dev_name(&unit->device); tgt->guid = (u64)device->config_rom[3] << 32 | device->config_rom[4]; if (fw_device_enable_phys_dma(device) < 0) @@ -1147,7 +1168,7 @@ static int sbp2_probe(struct device *dev) /* Do the login in a workqueue so we can easily reschedule retries. */ list_for_each_entry(lu, &tgt->lu_list, link) - sbp2_queue_work(lu, 0); + sbp2_queue_work(lu, DIV_ROUND_UP(HZ, 5)); return 0; fail_tgt_put: diff --git a/drivers/firewire/fw-topology.c b/drivers/firewire/fw-topology.c index c1b81077c4a8..5e204713002d 100644 --- a/drivers/firewire/fw-topology.c +++ b/drivers/firewire/fw-topology.c @@ -413,7 +413,7 @@ static void update_tree(struct fw_card *card, struct fw_node *root) { struct list_head list0, list1; - struct fw_node *node0, *node1; + struct fw_node *node0, *node1, *next1; int i, event; INIT_LIST_HEAD(&list0); @@ -485,7 +485,9 @@ update_tree(struct fw_card *card, struct fw_node *root) } node0 = fw_node(node0->link.next); - node1 = fw_node(node1->link.next); + next1 = fw_node(node1->link.next); + fw_node_put(node1); + node1 = next1; } } diff --git a/drivers/firewire/fw-transaction.c b/drivers/firewire/fw-transaction.c index 022ac4fabb67..2884f876397b 100644 --- a/drivers/firewire/fw-transaction.c +++ b/drivers/firewire/fw-transaction.c @@ -207,6 +207,7 @@ fw_fill_request(struct fw_packet *packet, int tcode, int tlabel, packet->speed = speed; packet->generation = generation; packet->ack = 0; + packet->payload_bus = 0; } /** @@ -581,6 +582,8 @@ fw_fill_response(struct fw_packet *response, u32 *request_header, BUG(); return; } + + response->payload_bus = 0; } EXPORT_SYMBOL(fw_fill_response); diff --git a/drivers/firewire/fw-transaction.h b/drivers/firewire/fw-transaction.h index 027f58ce81ad..839466f0a795 100644 --- a/drivers/firewire/fw-transaction.h +++ b/drivers/firewire/fw-transaction.h @@ -27,6 +27,7 @@ #include #include #include +#include #include #define TCODE_IS_READ_REQUEST(tcode) (((tcode) & ~1) == 4) @@ -153,6 +154,7 @@ struct fw_packet { size_t header_length; void *payload; size_t payload_length; + dma_addr_t payload_bus; u32 timestamp; /* @@ -248,7 +250,7 @@ struct fw_card { struct fw_node *local_node; struct fw_node *root_node; struct fw_node *irm_node; - int color; + u8 color; /* must be u8 to match the definition in struct fw_node */ int gap_count; bool beta_repeaters_present; diff --git a/drivers/firmware/dmi_scan.c b/drivers/firmware/dmi_scan.c index 3e526b6d00cb..4a597d8c2f70 100644 --- a/drivers/firmware/dmi_scan.c +++ b/drivers/firmware/dmi_scan.c @@ -81,9 +81,9 @@ static void dmi_table(u8 *buf, int len, int num, const struct dmi_header *dm = (const struct dmi_header *)data; /* - * We want to know the total length (formated area and strings) - * before decoding to make sure we won't run off the table in - * dmi_decode or dmi_string + * We want to know the total length (formatted area and + * strings) before decoding to make sure we won't run off the + * table in dmi_decode or dmi_string */ data += dm->length; while ((data - buf < len - 1) && (data[0] || data[1])) @@ -467,6 +467,17 @@ const char *dmi_get_system_info(int field) } EXPORT_SYMBOL(dmi_get_system_info); +/** + * dmi_name_in_serial - Check if string is in the DMI product serial + * information. + */ +int dmi_name_in_serial(const char *str) +{ + int f = DMI_PRODUCT_SERIAL; + if (dmi_ident[f] && strstr(dmi_ident[f], str)) + return 1; + return 0; +} /** * dmi_name_in_vendors - Check if string is anywhere in the DMI vendor information. diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 7f2ee27fe76b..48f49d93d249 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -65,6 +65,14 @@ config GPIO_SYSFS # put expanders in the right section, in alphabetical order +comment "Memory mapped GPIO expanders:" + +config GPIO_XILINX + bool "Xilinx GPIO support" + depends on PPC_OF + help + Say yes here to support the Xilinx FPGA GPIO device + comment "I2C GPIO expanders:" config GPIO_MAX732X diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 6aafdeb9ad03..49ac64e515e6 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -10,4 +10,5 @@ obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o obj-$(CONFIG_GPIO_PCA953X) += pca953x.o obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o +obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index faa1cc66e9cf..82020abc329e 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1134,7 +1134,7 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) continue; is_out = test_bit(FLAG_IS_OUT, &gdesc->flags); - seq_printf(s, " gpio-%-3d (%-12s) %s %s", + seq_printf(s, " gpio-%-3d (%-20.20s) %s %s", gpio, gdesc->label, is_out ? "out" : "in ", chip->get diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c new file mode 100644 index 000000000000..3c1177abebd3 --- /dev/null +++ b/drivers/gpio/xilinx_gpio.c @@ -0,0 +1,235 @@ +/* + * Xilinx gpio driver + * + * Copyright 2008 Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Register Offset Definitions */ +#define XGPIO_DATA_OFFSET (0x0) /* Data register */ +#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ + +struct xgpio_instance { + struct of_mm_gpio_chip mmchip; + u32 gpio_state; /* GPIO state shadow register */ + u32 gpio_dir; /* GPIO direction shadow register */ + spinlock_t gpio_lock; /* Lock used for synchronization */ +}; + +/** + * xgpio_get - Read the specified signal of the GPIO device. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * + * This function reads the specified signal of the GPIO device. It returns 0 if + * the signal clear, 1 if signal is set or negative value on error. + */ +static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + + return (in_be32(mm_gc->regs + XGPIO_DATA_OFFSET) >> gpio) & 1; +} + +/** + * xgpio_set - Write the specified signal of the GPIO device. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * @val: Value to be written to specified signal. + * + * This function writes the specified value in to the specified signal of the + * GPIO device. + */ +static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + unsigned long flags; + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct xgpio_instance *chip = + container_of(mm_gc, struct xgpio_instance, mmchip); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + /* Write to GPIO signal and set its direction to output */ + if (val) + chip->gpio_state |= 1 << gpio; + else + chip->gpio_state &= ~(1 << gpio); + out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state); + + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_dir_in - Set the direction of the specified GPIO signal as input. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * + * This function sets the direction of specified GPIO signal as input. + * It returns 0 if direction of GPIO signals is set as input otherwise it + * returns negative error value. + */ +static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) +{ + unsigned long flags; + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct xgpio_instance *chip = + container_of(mm_gc, struct xgpio_instance, mmchip); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + /* Set the GPIO bit in shadow register and set direction as input */ + chip->gpio_dir |= (1 << gpio); + out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir); + + spin_unlock_irqrestore(&chip->gpio_lock, flags); + + return 0; +} + +/** + * xgpio_dir_out - Set the direction of the specified GPIO signal as output. + * @gc: Pointer to gpio_chip device structure. + * @gpio: GPIO signal number. + * @val: Value to be written to specified signal. + * + * This function sets the direction of specified GPIO signal as output. If all + * GPIO signals of GPIO chip is configured as input then it returns + * error otherwise it returns 0. + */ +static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) +{ + unsigned long flags; + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct xgpio_instance *chip = + container_of(mm_gc, struct xgpio_instance, mmchip); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + /* Write state of GPIO signal */ + if (val) + chip->gpio_state |= 1 << gpio; + else + chip->gpio_state &= ~(1 << gpio); + out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state); + + /* Clear the GPIO bit in shadow register and set direction as output */ + chip->gpio_dir &= (~(1 << gpio)); + out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir); + + spin_unlock_irqrestore(&chip->gpio_lock, flags); + + return 0; +} + +/** + * xgpio_save_regs - Set initial values of GPIO pins + * @mm_gc: pointer to memory mapped GPIO chip structure + */ +static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) +{ + struct xgpio_instance *chip = + container_of(mm_gc, struct xgpio_instance, mmchip); + + out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state); + out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir); +} + +/** + * xgpio_of_probe - Probe method for the GPIO device. + * @np: pointer to device tree node + * + * This function probes the GPIO device in the device tree. It initializes the + * driver data structure. It returns 0, if the driver is bound to the GPIO + * device, or a negative value if there is an error. + */ +static int __devinit xgpio_of_probe(struct device_node *np) +{ + struct xgpio_instance *chip; + struct of_gpio_chip *ofchip; + int status = 0; + const u32 *tree_info; + + chip = kzalloc(sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + ofchip = &chip->mmchip.of_gc; + + /* Update GPIO state shadow register with default value */ + tree_info = of_get_property(np, "xlnx,dout-default", NULL); + if (tree_info) + chip->gpio_state = *tree_info; + + /* Update GPIO direction shadow register with default value */ + chip->gpio_dir = 0xFFFFFFFF; /* By default, all pins are inputs */ + tree_info = of_get_property(np, "xlnx,tri-default", NULL); + if (tree_info) + chip->gpio_dir = *tree_info; + + /* Check device node and parent device node for device width */ + ofchip->gc.ngpio = 32; /* By default assume full GPIO controller */ + tree_info = of_get_property(np, "xlnx,gpio-width", NULL); + if (!tree_info) + tree_info = of_get_property(np->parent, + "xlnx,gpio-width", NULL); + if (tree_info) + ofchip->gc.ngpio = *tree_info; + + spin_lock_init(&chip->gpio_lock); + + ofchip->gpio_cells = 2; + ofchip->gc.direction_input = xgpio_dir_in; + ofchip->gc.direction_output = xgpio_dir_out; + ofchip->gc.get = xgpio_get; + ofchip->gc.set = xgpio_set; + + chip->mmchip.save_regs = xgpio_save_regs; + + /* Call the OF gpio helper to setup and register the GPIO device */ + status = of_mm_gpiochip_add(np, &chip->mmchip); + if (status) { + kfree(chip); + pr_err("%s: error in probe function with status %d\n", + np->full_name, status); + return status; + } + pr_info("XGpio: %s: registered\n", np->full_name); + return 0; +} + +static struct of_device_id xgpio_of_match[] __devinitdata = { + { .compatible = "xlnx,xps-gpio-1.00.a", }, + { /* end of list */ }, +}; + +static int __init xgpio_init(void) +{ + struct device_node *np; + + for_each_matching_node(np, xgpio_of_match) + xgpio_of_probe(np); + + return 0; +} + +/* Make sure we get initialized before anyone else tries to use us */ +subsys_initcall(xgpio_init); +/* No exit call at the moment as we cannot unregister of GPIO chips */ + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 96f416afc3f6..996097acb5e7 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -266,11 +266,19 @@ int drm_init(struct drm_driver *driver) for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) { pid = (struct pci_device_id *)&driver->pci_driver.id_table[i]; + /* Loop around setting up a DRM device for each PCI device + * matching our ID and device class. If we had the internal + * function that pci_get_subsys and pci_get_class used, we'd + * be able to just pass pid in instead of doing a two-stage + * thing. + */ pdev = NULL; - /* pass back in pdev to account for multiple identical cards */ while ((pdev = pci_get_subsys(pid->vendor, pid->device, pid->subvendor, pid->subdevice, pdev)) != NULL) { + if ((pdev->class & pid->class_mask) != pid->class) + continue; + /* stealth mode requires a manual probe */ pci_dev_get(pdev); drm_get_dev(pdev, pid, driver); @@ -297,6 +305,8 @@ static void drm_cleanup(struct drm_device * dev) return; } + drm_vblank_cleanup(dev); + drm_lastclose(dev); if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index 0d46627663b1..78eeed5caaff 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -406,8 +406,6 @@ int drm_release(struct inode *inode, struct file *filp) if (dev->driver->driver_features & DRIVER_GEM) drm_gem_release(dev, file_priv); - drm_fasync(-1, filp, 0); - mutex_lock(&dev->ctxlist_mutex); if (!list_empty(&dev->ctxlist)) { struct drm_ctx_list *pos, *n; diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 212a94f715b2..1e787f894b3c 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -94,7 +94,7 @@ static void vblank_disable_fn(unsigned long arg) } } -static void drm_vblank_cleanup(struct drm_device *dev) +void drm_vblank_cleanup(struct drm_device *dev) { /* Bail if the driver didn't call drm_vblank_init() */ if (dev->num_crtcs == 0) @@ -278,10 +278,6 @@ int drm_irq_uninstall(struct drm_device * dev) free_irq(dev->pdev->irq, dev); - drm_vblank_cleanup(dev); - - dev->locked_tasklet_func = NULL; - return 0; } EXPORT_SYMBOL(drm_irq_uninstall); @@ -699,81 +695,3 @@ void drm_handle_vblank(struct drm_device *dev, int crtc) drm_vbl_send_signals(dev, crtc); } EXPORT_SYMBOL(drm_handle_vblank); - -/** - * Tasklet wrapper function. - * - * \param data DRM device in disguise. - * - * Attempts to grab the HW lock and calls the driver callback on success. On - * failure, leave the lock marked as contended so the callback can be called - * from drm_unlock(). - */ -static void drm_locked_tasklet_func(unsigned long data) -{ - struct drm_device *dev = (struct drm_device *)data; - unsigned long irqflags; - void (*tasklet_func)(struct drm_device *); - - spin_lock_irqsave(&dev->tasklet_lock, irqflags); - tasklet_func = dev->locked_tasklet_func; - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - - if (!tasklet_func || - !drm_lock_take(&dev->lock, - DRM_KERNEL_CONTEXT)) { - return; - } - - dev->lock.lock_time = jiffies; - atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); - - spin_lock_irqsave(&dev->tasklet_lock, irqflags); - tasklet_func = dev->locked_tasklet_func; - dev->locked_tasklet_func = NULL; - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - - if (tasklet_func != NULL) - tasklet_func(dev); - - drm_lock_free(&dev->lock, - DRM_KERNEL_CONTEXT); -} - -/** - * Schedule a tasklet to call back a driver hook with the HW lock held. - * - * \param dev DRM device. - * \param func Driver callback. - * - * This is intended for triggering actions that require the HW lock from an - * interrupt handler. The lock will be grabbed ASAP after the interrupt handler - * completes. Note that the callback may be called from interrupt or process - * context, it must not make any assumptions about this. Also, the HW lock will - * be held with the kernel context or any client context. - */ -void drm_locked_tasklet(struct drm_device *dev, void (*func)(struct drm_device *)) -{ - unsigned long irqflags; - static DECLARE_TASKLET(drm_tasklet, drm_locked_tasklet_func, 0); - - if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ) || - test_bit(TASKLET_STATE_SCHED, &drm_tasklet.state)) - return; - - spin_lock_irqsave(&dev->tasklet_lock, irqflags); - - if (dev->locked_tasklet_func) { - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - return; - } - - dev->locked_tasklet_func = func; - - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - - drm_tasklet.data = (unsigned long)dev; - - tasklet_hi_schedule(&drm_tasklet); -} -EXPORT_SYMBOL(drm_locked_tasklet); diff --git a/drivers/gpu/drm/drm_lock.c b/drivers/gpu/drm/drm_lock.c index 888159e03d26..1cfa72031f8f 100644 --- a/drivers/gpu/drm/drm_lock.c +++ b/drivers/gpu/drm/drm_lock.c @@ -154,8 +154,6 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv) int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_lock *lock = data; - unsigned long irqflags; - void (*tasklet_func)(struct drm_device *); if (lock->context == DRM_KERNEL_CONTEXT) { DRM_ERROR("Process %d using kernel context %d\n", @@ -163,13 +161,6 @@ int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv) return -EINVAL; } - spin_lock_irqsave(&dev->tasklet_lock, irqflags); - tasklet_func = dev->locked_tasklet_func; - dev->locked_tasklet_func = NULL; - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - if (tasklet_func != NULL) - tasklet_func(dev); - atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]); /* kernel_context_switch isn't used by any of the x86 drm diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c index 141e33004a76..66c96ec66672 100644 --- a/drivers/gpu/drm/drm_stub.c +++ b/drivers/gpu/drm/drm_stub.c @@ -92,7 +92,6 @@ static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev, spin_lock_init(&dev->count_lock); spin_lock_init(&dev->drw_lock); - spin_lock_init(&dev->tasklet_lock); spin_lock_init(&dev->lock.spinlock); init_timer(&dev->timer); mutex_init(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5ba78e4fd2b5..d8fb5d8ee7ea 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -3,13 +3,14 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. ccflags-y := -Iinclude/drm -i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_opregion.o \ +i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ i915_suspend.o \ i915_gem.o \ i915_gem_debug.o \ i915_gem_proc.o \ i915_gem_tiling.o +i915-$(CONFIG_ACPI) += i915_opregion.o i915-$(CONFIG_COMPAT) += i915_ioc32.o obj-$(CONFIG_DRM_I915) += i915.o diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 01de536e0211..afa8a12cd009 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -154,6 +154,9 @@ static int i915_dma_cleanup(struct drm_device * dev) if (I915_NEED_GFX_HWS(dev)) i915_free_hws(dev); + dev_priv->sarea = NULL; + dev_priv->sarea_priv = NULL; + return 0; } @@ -442,7 +445,7 @@ static void i915_emit_breadcrumb(struct drm_device *dev) BEGIN_LP_RING(4); OUT_RING(MI_STORE_DWORD_INDEX); - OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); + OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); OUT_RING(dev_priv->counter); OUT_RING(0); ADVANCE_LP_RING(); @@ -573,7 +576,7 @@ static int i915_dispatch_flip(struct drm_device * dev) BEGIN_LP_RING(4); OUT_RING(MI_STORE_DWORD_INDEX); - OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); + OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); OUT_RING(dev_priv->counter); OUT_RING(0); ADVANCE_LP_RING(); @@ -608,7 +611,6 @@ static int i915_batchbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv; drm_i915_batchbuffer_t *batch = data; @@ -634,7 +636,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data, mutex_unlock(&dev->struct_mutex); if (sarea_priv) - sarea_priv->last_dispatch = (int)hw_status[5]; + sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); return ret; } @@ -642,7 +644,6 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv; drm_i915_cmdbuffer_t *cmdbuf = data; @@ -670,7 +671,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, } if (sarea_priv) - sarea_priv->last_dispatch = (int)hw_status[5]; + sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); return 0; } @@ -716,7 +717,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = dev->pci_device; break; case I915_PARAM_HAS_GEM: - value = 1; + value = dev_priv->has_gem; break; default: DRM_ERROR("Unknown parameter %d\n", param->param); @@ -829,6 +830,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) dev_priv->regs = ioremap(base, size); +#ifdef CONFIG_HIGHMEM64G + /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */ + dev_priv->has_gem = 0; +#else + /* enable GEM by default */ + dev_priv->has_gem = 1; +#endif + i915_gem_load(dev); /* Init HWS */ @@ -846,16 +855,23 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) * and the registers being closely associated. * * According to chipset errata, on the 965GM, MSI interrupts may - * be lost or delayed + * be lost or delayed, but we use them anyways to avoid + * stuck interrupts on some machines. */ - if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev)) - if (pci_enable_msi(dev->pdev)) - DRM_ERROR("failed to enable MSI\n"); + if (!IS_I945G(dev) && !IS_I945GM(dev)) + pci_enable_msi(dev->pdev); intel_opregion_init(dev); spin_lock_init(&dev_priv->user_irq_lock); + ret = drm_vblank_init(dev, I915_NUM_PIPE); + + if (ret) { + (void) i915_driver_unload(dev); + return ret; + } + return ret; } @@ -960,6 +976,7 @@ struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), + DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), }; int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f20ffe17df71..b3cc4731aa7c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -31,6 +31,7 @@ #define _I915_DRV_H_ #include "i915_reg.h" +#include /* General customization: */ @@ -46,6 +47,8 @@ enum pipe { PIPE_B, }; +#define I915_NUM_PIPE 2 + /* Interface history: * * 1.1: Original. @@ -87,13 +90,6 @@ struct mem_block { struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ }; -typedef struct _drm_i915_vbl_swap { - struct list_head head; - drm_drawable_t drw_id; - unsigned int pipe; - unsigned int sequence; -} drm_i915_vbl_swap_t; - struct opregion_header; struct opregion_acpi; struct opregion_swsci; @@ -110,6 +106,8 @@ struct intel_opregion { typedef struct drm_i915_private { struct drm_device *dev; + int has_gem; + void __iomem *regs; drm_local_map_t *sarea; @@ -138,6 +136,7 @@ typedef struct drm_i915_private { int user_irq_refcount; /** Cached value of IMR to avoid reads in updating the bitfield */ u32 irq_mask_reg; + u32 pipestat[2]; int tex_lru_log_granularity; int allow_batchbuffer; @@ -145,10 +144,6 @@ typedef struct drm_i915_private { unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; int vblank_pipe; - spinlock_t swaps_lock; - drm_i915_vbl_swap_t vbl_swaps; - unsigned int swaps_pending; - struct intel_opregion opregion; /* Register state */ @@ -156,6 +151,8 @@ typedef struct drm_i915_private { u32 saveDSPACNTR; u32 saveDSPBCNTR; u32 saveDSPARB; + u32 saveRENDERSTANDBY; + u32 saveHWS; u32 savePIPEACONF; u32 savePIPEBCONF; u32 savePIPEASRC; @@ -240,16 +237,19 @@ typedef struct drm_i915_private { u8 saveDACDATA[256*3]; /* 256 3-byte colors */ u8 saveCR[37]; - /** Work task for vblank-related ring access */ - struct work_struct vblank_work; - struct { struct drm_mm gtt_space; + struct io_mapping *gtt_mapping; + /** * List of objects currently involved in rendering from the * ringbuffer. * + * Includes buffers having the contents of their GPU caches + * flushed, not necessarily primitives. last_rendering_seqno + * represents when the rendering involved will be completed. + * * A reference is held on the buffer while on this list. */ struct list_head active_list; @@ -259,6 +259,8 @@ typedef struct drm_i915_private { * still have a write_domain which needs to be flushed before * unbinding. * + * last_rendering_seqno is 0 while an object is in this list. + * * A reference is held on the buffer while on this list. */ struct list_head flushing_list; @@ -267,6 +269,8 @@ typedef struct drm_i915_private { * LRU list of objects which are not in the ringbuffer and * are ready to unbind, but are still in the GTT. * + * last_rendering_seqno is 0 while an object is in this list. + * * A reference is not held on the buffer while on this list, * as merely being GTT-bound shouldn't prevent its being * freed, and we'll pull it off the list in the free path. @@ -377,8 +381,8 @@ struct drm_i915_gem_object { uint32_t agp_type; /** - * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when - * GEM_DOMAIN_CPU is not in the object's read domain. + * If present, while GEM_DOMAIN_CPU is in the read domain this array + * flags which individual pages are valid. */ uint8_t *page_cpu_valid; }; @@ -400,9 +404,6 @@ struct drm_i915_gem_request { /** Time at which this request was emitted, in jiffies. */ unsigned long emitted_jiffies; - /** Cache domains that were flushed at the start of the request. */ - uint32_t flush_domains; - struct list_head list; }; @@ -441,7 +442,6 @@ extern int i915_irq_wait(struct drm_device *dev, void *data, void i915_user_irq_get(struct drm_device *dev); void i915_user_irq_put(struct drm_device *dev); -extern void i915_vblank_work_handler(struct work_struct *work); extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); extern void i915_driver_irq_preinstall(struct drm_device * dev); extern int i915_driver_irq_postinstall(struct drm_device *dev); @@ -457,6 +457,13 @@ extern int i915_vblank_swap(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); +void +i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); + +void +i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); + + /* i915_mem.c */ extern int i915_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -502,6 +509,8 @@ int i915_gem_set_tiling(struct drm_device *dev, void *data, struct drm_file *file_priv); int i915_gem_get_tiling(struct drm_device *dev, void *data, struct drm_file *file_priv); +int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); void i915_gem_load(struct drm_device *dev); int i915_gem_proc_init(struct drm_minor *minor); void i915_gem_proc_cleanup(struct drm_minor *minor); @@ -539,11 +548,18 @@ extern int i915_restore_state(struct drm_device *dev); extern int i915_save_state(struct drm_device *dev); extern int i915_restore_state(struct drm_device *dev); +#ifdef CONFIG_ACPI /* i915_opregion.c */ extern int intel_opregion_init(struct drm_device *dev); extern void intel_opregion_free(struct drm_device *dev); extern void opregion_asle_intr(struct drm_device *dev); extern void opregion_enable_asle(struct drm_device *dev); +#else +static inline int intel_opregion_init(struct drm_device *dev) { return 0; } +static inline void intel_opregion_free(struct drm_device *dev) { return; } +static inline void opregion_asle_intr(struct drm_device *dev) { return; } +static inline void opregion_enable_asle(struct drm_device *dev) { return; } +#endif /** * Lock test for when it's just for synchronization of ring access. @@ -610,8 +626,9 @@ extern void opregion_enable_asle(struct drm_device *dev); * The area from dword 0x20 to 0x3ff is available for driver usage. */ #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) -#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5) +#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) #define I915_GEM_HWS_INDEX 0x20 +#define I915_BREADCRUMB_INDEX 0x21 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 17ae330ff269..24fe8c10b4b2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -31,21 +31,23 @@ #include "i915_drv.h" #include -static int -i915_gem_object_set_domain(struct drm_gem_object *obj, - uint32_t read_domains, - uint32_t write_domain); -static int -i915_gem_object_set_domain_range(struct drm_gem_object *obj, - uint64_t offset, - uint64_t size, - uint32_t read_domains, - uint32_t write_domain); -static int -i915_gem_set_domain(struct drm_gem_object *obj, - struct drm_file *file_priv, - uint32_t read_domains, - uint32_t write_domain); +#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) + +static void +i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, + uint32_t read_domains, + uint32_t write_domain); +static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); +static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); +static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); +static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, + int write); +static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, + int write); +static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, + uint64_t offset, + uint64_t size); +static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); static int i915_gem_object_get_page_list(struct drm_gem_object *obj); static void i915_gem_object_free_page_list(struct drm_gem_object *obj); static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); @@ -79,6 +81,22 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data, return 0; } +int +i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_i915_gem_get_aperture *args = data; + + if (!(dev->driver->driver_features & DRIVER_GEM)) + return -ENODEV; + + args->aper_size = dev->gtt_total; + args->aper_available_size = (args->aper_size - + atomic_read(&dev->pin_memory)); + + return 0; +} + /** * Creates a new mm object and returns a handle to it. @@ -144,8 +162,8 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data, mutex_lock(&dev->struct_mutex); - ret = i915_gem_object_set_domain_range(obj, args->offset, args->size, - I915_GEM_DOMAIN_CPU, 0); + ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, + args->size); if (ret != 0) { drm_gem_object_unreference(obj); mutex_unlock(&dev->struct_mutex); @@ -171,35 +189,50 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data, return 0; } -/* - * Try to write quickly with an atomic kmap. Return true on success. - * - * If this fails (which includes a partial write), we'll redo the whole - * thing with the slow version. - * - * This is a workaround for the low performance of iounmap (approximate - * 10% cpu cost on normal 3D workloads). kmap_atomic on HIGHMEM kernels - * happens to let us map card memory without taking IPIs. When the vmap - * rework lands we should be able to dump this hack. +/* This is the fast write path which cannot handle + * page faults in the source data */ -static inline int fast_user_write(unsigned long pfn, char __user *user_data, - int l, int o) + +static inline int +fast_user_write(struct io_mapping *mapping, + loff_t page_base, int page_offset, + char __user *user_data, + int length) { -#ifdef CONFIG_HIGHMEM - unsigned long unwritten; char *vaddr_atomic; + unsigned long unwritten; - vaddr_atomic = kmap_atomic_pfn(pfn, KM_USER0); -#if WATCH_PWRITE - DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n", - i, o, l, pfn, vaddr_atomic); -#endif - unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + o, user_data, l); - kunmap_atomic(vaddr_atomic, KM_USER0); - return !unwritten; -#else + vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); + unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, + user_data, length); + io_mapping_unmap_atomic(vaddr_atomic); + if (unwritten) + return -EFAULT; + return 0; +} + +/* Here's the write path which can sleep for + * page faults + */ + +static inline int +slow_user_write(struct io_mapping *mapping, + loff_t page_base, int page_offset, + char __user *user_data, + int length) +{ + char __iomem *vaddr; + unsigned long unwritten; + + vaddr = io_mapping_map_wc(mapping, page_base); + if (vaddr == NULL) + return -EFAULT; + unwritten = __copy_from_user(vaddr + page_offset, + user_data, length); + io_mapping_unmap(vaddr); + if (unwritten) + return -EFAULT; return 0; -#endif } static int @@ -208,10 +241,12 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj, struct drm_file *file_priv) { struct drm_i915_gem_object *obj_priv = obj->driver_private; + drm_i915_private_t *dev_priv = dev->dev_private; ssize_t remain; - loff_t offset; + loff_t offset, page_base; char __user *user_data; - int ret = 0; + int page_offset, page_length; + int ret; user_data = (char __user *) (uintptr_t) args->data_ptr; remain = args->size; @@ -225,8 +260,7 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj, mutex_unlock(&dev->struct_mutex); return ret; } - ret = i915_gem_set_domain(obj, file_priv, - I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); + ret = i915_gem_object_set_to_gtt_domain(obj, 1); if (ret) goto fail; @@ -235,57 +269,37 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj, obj_priv->dirty = 1; while (remain > 0) { - unsigned long pfn; - int i, o, l; - /* Operation in this page * - * i = page number - * o = offset within page - * l = bytes to copy + * page_base = page offset within aperture + * page_offset = offset within page + * page_length = bytes to copy for this page */ - i = offset >> PAGE_SHIFT; - o = offset & (PAGE_SIZE-1); - l = remain; - if ((o + l) > PAGE_SIZE) - l = PAGE_SIZE - o; - - pfn = (dev->agp->base >> PAGE_SHIFT) + i; - - if (!fast_user_write(pfn, user_data, l, o)) { - unsigned long unwritten; - char __iomem *vaddr; - - vaddr = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE); -#if WATCH_PWRITE - DRM_INFO("pwrite slow i %d o %d l %d " - "pfn %ld vaddr %p\n", - i, o, l, pfn, vaddr); -#endif - if (vaddr == NULL) { - ret = -EFAULT; - goto fail; - } - unwritten = __copy_from_user(vaddr + o, user_data, l); -#if WATCH_PWRITE - DRM_INFO("unwritten %ld\n", unwritten); -#endif - iounmap(vaddr); - if (unwritten) { - ret = -EFAULT; + page_base = (offset & ~(PAGE_SIZE-1)); + page_offset = offset & (PAGE_SIZE-1); + page_length = remain; + if ((page_offset + remain) > PAGE_SIZE) + page_length = PAGE_SIZE - page_offset; + + ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, + page_offset, user_data, page_length); + + /* If we get a fault while copying data, then (presumably) our + * source page isn't available. In this case, use the + * non-atomic function + */ + if (ret) { + ret = slow_user_write (dev_priv->mm.gtt_mapping, + page_base, page_offset, + user_data, page_length); + if (ret) goto fail; - } } - remain -= l; - user_data += l; - offset += l; + remain -= page_length; + user_data += page_length; + offset += page_length; } -#if WATCH_PWRITE && 1 - i915_gem_clflush_object(obj); - i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0); - i915_gem_clflush_object(obj); -#endif fail: i915_gem_object_unpin(obj); @@ -305,8 +319,7 @@ i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj, mutex_lock(&dev->struct_mutex); - ret = i915_gem_set_domain(obj, file_priv, - I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); + ret = i915_gem_object_set_to_cpu_domain(obj, 1); if (ret) { mutex_unlock(&dev->struct_mutex); return ret; @@ -382,7 +395,8 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, } /** - * Called when user space prepares to use an object + * Called when user space prepares to use an object with the CPU, either + * through the mmap ioctl's mapping or a GTT mapping. */ int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, @@ -390,11 +404,26 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, { struct drm_i915_gem_set_domain *args = data; struct drm_gem_object *obj; + uint32_t read_domains = args->read_domains; + uint32_t write_domain = args->write_domain; int ret; if (!(dev->driver->driver_features & DRIVER_GEM)) return -ENODEV; + /* Only handle setting domains to types used by the CPU. */ + if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) + return -EINVAL; + + if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) + return -EINVAL; + + /* Having something in the write domain implies it's in the read + * domain, and only that read domain. Enforce that in the request. + */ + if (write_domain != 0 && read_domains != write_domain) + return -EINVAL; + obj = drm_gem_object_lookup(dev, file_priv, args->handle); if (obj == NULL) return -EBADF; @@ -402,10 +431,21 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, mutex_lock(&dev->struct_mutex); #if WATCH_BUF DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n", - obj, obj->size, args->read_domains, args->write_domain); + obj, obj->size, read_domains, write_domain); #endif - ret = i915_gem_set_domain(obj, file_priv, - args->read_domains, args->write_domain); + if (read_domains & I915_GEM_DOMAIN_GTT) { + ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); + + /* Silently promote "you're not bound, there was nothing to do" + * to success, since the client was just asking us to + * make sure everything was done. + */ + if (ret == -EINVAL) + ret = 0; + } else { + ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); + } + drm_gem_object_unreference(obj); mutex_unlock(&dev->struct_mutex); return ret; @@ -440,10 +480,9 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, obj_priv = obj->driver_private; /* Pinned buffers may be scanout, so flush the cache */ - if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) { - i915_gem_clflush_object(obj); - drm_agp_chipset_flush(dev); - } + if (obj_priv->pin_count) + i915_gem_object_flush_cpu_write_domain(obj); + drm_gem_object_unreference(obj); mutex_unlock(&dev->struct_mutex); return ret; @@ -517,7 +556,7 @@ i915_gem_object_free_page_list(struct drm_gem_object *obj) } static void -i915_gem_object_move_to_active(struct drm_gem_object *obj) +i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) { struct drm_device *dev = obj->dev; drm_i915_private_t *dev_priv = dev->dev_private; @@ -531,8 +570,20 @@ i915_gem_object_move_to_active(struct drm_gem_object *obj) /* Move from whatever list we were on to the tail of execution. */ list_move_tail(&obj_priv->list, &dev_priv->mm.active_list); + obj_priv->last_rendering_seqno = seqno; } +static void +i915_gem_object_move_to_flushing(struct drm_gem_object *obj) +{ + struct drm_device *dev = obj->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj_priv = obj->driver_private; + + BUG_ON(!obj_priv->active); + list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); + obj_priv->last_rendering_seqno = 0; +} static void i915_gem_object_move_to_inactive(struct drm_gem_object *obj) @@ -547,6 +598,7 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj) else list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); + obj_priv->last_rendering_seqno = 0; if (obj_priv->active) { obj_priv->active = 0; drm_gem_object_unreference(obj); @@ -595,10 +647,28 @@ i915_add_request(struct drm_device *dev, uint32_t flush_domains) request->seqno = seqno; request->emitted_jiffies = jiffies; - request->flush_domains = flush_domains; was_empty = list_empty(&dev_priv->mm.request_list); list_add_tail(&request->list, &dev_priv->mm.request_list); + /* Associate any objects on the flushing list matching the write + * domain we're flushing with our flush. + */ + if (flush_domains != 0) { + struct drm_i915_gem_object *obj_priv, *next; + + list_for_each_entry_safe(obj_priv, next, + &dev_priv->mm.flushing_list, list) { + struct drm_gem_object *obj = obj_priv->obj; + + if ((obj->write_domain & flush_domains) == + obj->write_domain) { + obj->write_domain = 0; + i915_gem_object_move_to_active(obj, seqno); + } + } + + } + if (was_empty && !dev_priv->mm.suspended) schedule_delayed_work(&dev_priv->mm.retire_work, HZ); return seqno; @@ -661,30 +731,10 @@ i915_gem_retire_request(struct drm_device *dev, __func__, request->seqno, obj); #endif - if (obj->write_domain != 0) { - list_move_tail(&obj_priv->list, - &dev_priv->mm.flushing_list); - } else { + if (obj->write_domain != 0) + i915_gem_object_move_to_flushing(obj); + else i915_gem_object_move_to_inactive(obj); - } - } - - if (request->flush_domains != 0) { - struct drm_i915_gem_object *obj_priv, *next; - - /* Clear the write domain and activity from any buffers - * that are just waiting for a flush matching the one retired. - */ - list_for_each_entry_safe(obj_priv, next, - &dev_priv->mm.flushing_list, list) { - struct drm_gem_object *obj = obj_priv->obj; - - if (obj->write_domain & request->flush_domains) { - obj->write_domain = 0; - i915_gem_object_move_to_inactive(obj); - } - } - } } @@ -877,25 +927,10 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj) struct drm_i915_gem_object *obj_priv = obj->driver_private; int ret; - /* If there are writes queued to the buffer, flush and - * create a new seqno to wait for. + /* This function only exists to support waiting for existing rendering, + * not for emitting required flushes. */ - if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) { - uint32_t write_domain = obj->write_domain; -#if WATCH_BUF - DRM_INFO("%s: flushing object %p from write domain %08x\n", - __func__, obj, write_domain); -#endif - i915_gem_flush(dev, 0, write_domain); - - i915_gem_object_move_to_active(obj); - obj_priv->last_rendering_seqno = i915_add_request(dev, - write_domain); - BUG_ON(obj_priv->last_rendering_seqno == 0); -#if WATCH_LRU - DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj); -#endif - } + BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); /* If there is rendering queued on the buffer being evicted, wait for * it. @@ -935,24 +970,16 @@ i915_gem_object_unbind(struct drm_gem_object *obj) return -EINVAL; } - /* Wait for any rendering to complete - */ - ret = i915_gem_object_wait_rendering(obj); - if (ret) { - DRM_ERROR("wait_rendering failed: %d\n", ret); - return ret; - } - /* Move the object to the CPU domain to ensure that * any possible CPU writes while it's not in the GTT * are flushed when we go to remap it. This will * also ensure that all pending GPU writes are finished * before we unbind. */ - ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU, - I915_GEM_DOMAIN_CPU); + ret = i915_gem_object_set_to_cpu_domain(obj, 1); if (ret) { - DRM_ERROR("set_domain failed: %d\n", ret); + if (ret != -ERESTARTSYS) + DRM_ERROR("set_domain failed: %d\n", ret); return ret; } @@ -1067,6 +1094,21 @@ i915_gem_evict_something(struct drm_device *dev) return ret; } +static int +i915_gem_evict_everything(struct drm_device *dev) +{ + int ret; + + for (;;) { + ret = i915_gem_evict_something(dev); + if (ret != 0) + break; + } + if (ret == -ENOMEM) + return 0; + return ret; +} + static int i915_gem_object_get_page_list(struct drm_gem_object *obj) { @@ -1153,7 +1195,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) ret = i915_gem_evict_something(dev); if (ret != 0) { - DRM_ERROR("Failed to evict a buffer %d\n", ret); + if (ret != -ERESTARTSYS) + DRM_ERROR("Failed to evict a buffer %d\n", ret); return ret; } goto search_free; @@ -1213,6 +1256,143 @@ i915_gem_clflush_object(struct drm_gem_object *obj) drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE); } +/** Flushes any GPU write domain for the object if it's dirty. */ +static void +i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) +{ + struct drm_device *dev = obj->dev; + uint32_t seqno; + + if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) + return; + + /* Queue the GPU write cache flushing we need. */ + i915_gem_flush(dev, 0, obj->write_domain); + seqno = i915_add_request(dev, obj->write_domain); + obj->write_domain = 0; + i915_gem_object_move_to_active(obj, seqno); +} + +/** Flushes the GTT write domain for the object if it's dirty. */ +static void +i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) +{ + if (obj->write_domain != I915_GEM_DOMAIN_GTT) + return; + + /* No actual flushing is required for the GTT write domain. Writes + * to it immediately go to main memory as far as we know, so there's + * no chipset flush. It also doesn't land in render cache. + */ + obj->write_domain = 0; +} + +/** Flushes the CPU write domain for the object if it's dirty. */ +static void +i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) +{ + struct drm_device *dev = obj->dev; + + if (obj->write_domain != I915_GEM_DOMAIN_CPU) + return; + + i915_gem_clflush_object(obj); + drm_agp_chipset_flush(dev); + obj->write_domain = 0; +} + +/** + * Moves a single object to the GTT read, and possibly write domain. + * + * This function returns when the move is complete, including waiting on + * flushes to occur. + */ +static int +i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) +{ + struct drm_i915_gem_object *obj_priv = obj->driver_private; + int ret; + + /* Not valid to be called on unbound objects. */ + if (obj_priv->gtt_space == NULL) + return -EINVAL; + + i915_gem_object_flush_gpu_write_domain(obj); + /* Wait on any GPU rendering and flushing to occur. */ + ret = i915_gem_object_wait_rendering(obj); + if (ret != 0) + return ret; + + /* If we're writing through the GTT domain, then CPU and GPU caches + * will need to be invalidated at next use. + */ + if (write) + obj->read_domains &= I915_GEM_DOMAIN_GTT; + + i915_gem_object_flush_cpu_write_domain(obj); + + /* It should now be out of any other write domains, and we can update + * the domain values for our changes. + */ + BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); + obj->read_domains |= I915_GEM_DOMAIN_GTT; + if (write) { + obj->write_domain = I915_GEM_DOMAIN_GTT; + obj_priv->dirty = 1; + } + + return 0; +} + +/** + * Moves a single object to the CPU read, and possibly write domain. + * + * This function returns when the move is complete, including waiting on + * flushes to occur. + */ +static int +i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) +{ + struct drm_device *dev = obj->dev; + int ret; + + i915_gem_object_flush_gpu_write_domain(obj); + /* Wait on any GPU rendering and flushing to occur. */ + ret = i915_gem_object_wait_rendering(obj); + if (ret != 0) + return ret; + + i915_gem_object_flush_gtt_write_domain(obj); + + /* If we have a partially-valid cache of the object in the CPU, + * finish invalidating it and free the per-page flags. + */ + i915_gem_object_set_to_full_cpu_read_domain(obj); + + /* Flush the CPU cache if it's still invalid. */ + if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { + i915_gem_clflush_object(obj); + drm_agp_chipset_flush(dev); + + obj->read_domains |= I915_GEM_DOMAIN_CPU; + } + + /* It should now be out of any other write domains, and we can update + * the domain values for our changes. + */ + BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); + + /* If we're writing through the CPU, then the GPU read domains will + * need to be invalidated at next use. + */ + if (write) { + obj->read_domains &= I915_GEM_DOMAIN_CPU; + obj->write_domain = I915_GEM_DOMAIN_CPU; + } + + return 0; +} + /* * Set the next domain for the specified object. This * may not actually perform the necessary flushing/invaliding though, @@ -1324,16 +1504,18 @@ i915_gem_clflush_object(struct drm_gem_object *obj) * MI_FLUSH * drm_agp_chipset_flush */ -static int -i915_gem_object_set_domain(struct drm_gem_object *obj, - uint32_t read_domains, - uint32_t write_domain) +static void +i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, + uint32_t read_domains, + uint32_t write_domain) { struct drm_device *dev = obj->dev; struct drm_i915_gem_object *obj_priv = obj->driver_private; uint32_t invalidate_domains = 0; uint32_t flush_domains = 0; - int ret; + + BUG_ON(read_domains & I915_GEM_DOMAIN_CPU); + BUG_ON(write_domain == I915_GEM_DOMAIN_CPU); #if WATCH_BUF DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", @@ -1370,34 +1552,11 @@ i915_gem_object_set_domain(struct drm_gem_object *obj, DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", __func__, flush_domains, invalidate_domains); #endif - /* - * If we're invaliding the CPU cache and flushing a GPU cache, - * then pause for rendering so that the GPU caches will be - * flushed before the cpu cache is invalidated - */ - if ((invalidate_domains & I915_GEM_DOMAIN_CPU) && - (flush_domains & ~(I915_GEM_DOMAIN_CPU | - I915_GEM_DOMAIN_GTT))) { - ret = i915_gem_object_wait_rendering(obj); - if (ret) - return ret; - } i915_gem_clflush_object(obj); } if ((write_domain | flush_domains) != 0) obj->write_domain = write_domain; - - /* If we're invalidating the CPU domain, clear the per-page CPU - * domain list as well. - */ - if (obj_priv->page_cpu_valid != NULL && - (write_domain != 0 || - read_domains & I915_GEM_DOMAIN_CPU)) { - drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE, - DRM_MEM_DRIVER); - obj_priv->page_cpu_valid = NULL; - } obj->read_domains = read_domains; dev->invalidate_domains |= invalidate_domains; @@ -1408,49 +1567,94 @@ i915_gem_object_set_domain(struct drm_gem_object *obj, obj->read_domains, obj->write_domain, dev->invalidate_domains, dev->flush_domains); #endif - return 0; } /** - * Set the read/write domain on a range of the object. + * Moves the object from a partially CPU read to a full one. * - * Currently only implemented for CPU reads, otherwise drops to normal - * i915_gem_object_set_domain(). + * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), + * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). */ -static int -i915_gem_object_set_domain_range(struct drm_gem_object *obj, - uint64_t offset, - uint64_t size, - uint32_t read_domains, - uint32_t write_domain) +static void +i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) { + struct drm_device *dev = obj->dev; struct drm_i915_gem_object *obj_priv = obj->driver_private; - int ret, i; - if (obj->read_domains & I915_GEM_DOMAIN_CPU) - return 0; + if (!obj_priv->page_cpu_valid) + return; - if (read_domains != I915_GEM_DOMAIN_CPU || - write_domain != 0) - return i915_gem_object_set_domain(obj, - read_domains, write_domain); + /* If we're partially in the CPU read domain, finish moving it in. + */ + if (obj->read_domains & I915_GEM_DOMAIN_CPU) { + int i; - /* Wait on any GPU rendering to the object to be flushed. */ - if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) { - ret = i915_gem_object_wait_rendering(obj); - if (ret) - return ret; + for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { + if (obj_priv->page_cpu_valid[i]) + continue; + drm_clflush_pages(obj_priv->page_list + i, 1); + } + drm_agp_chipset_flush(dev); } + /* Free the page_cpu_valid mappings which are now stale, whether + * or not we've got I915_GEM_DOMAIN_CPU. + */ + drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE, + DRM_MEM_DRIVER); + obj_priv->page_cpu_valid = NULL; +} + +/** + * Set the CPU read domain on a range of the object. + * + * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's + * not entirely valid. The page_cpu_valid member of the object flags which + * pages have been flushed, and will be respected by + * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping + * of the whole object. + * + * This function returns when the move is complete, including waiting on + * flushes to occur. + */ +static int +i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, + uint64_t offset, uint64_t size) +{ + struct drm_i915_gem_object *obj_priv = obj->driver_private; + int i, ret; + + if (offset == 0 && size == obj->size) + return i915_gem_object_set_to_cpu_domain(obj, 0); + + i915_gem_object_flush_gpu_write_domain(obj); + /* Wait on any GPU rendering and flushing to occur. */ + ret = i915_gem_object_wait_rendering(obj); + if (ret != 0) + return ret; + i915_gem_object_flush_gtt_write_domain(obj); + + /* If we're already fully in the CPU read domain, we're done. */ + if (obj_priv->page_cpu_valid == NULL && + (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) + return 0; + + /* Otherwise, create/clear the per-page CPU read domain flag if we're + * newly adding I915_GEM_DOMAIN_CPU + */ if (obj_priv->page_cpu_valid == NULL) { obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE, DRM_MEM_DRIVER); - } + if (obj_priv->page_cpu_valid == NULL) + return -ENOMEM; + } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) + memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); /* Flush the cache on any pages that are still invalid from the CPU's * perspective. */ - for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) { + for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; + i++) { if (obj_priv->page_cpu_valid[i]) continue; @@ -1459,39 +1663,14 @@ i915_gem_object_set_domain_range(struct drm_gem_object *obj, obj_priv->page_cpu_valid[i] = 1; } - return 0; -} - -/** - * Once all of the objects have been set in the proper domain, - * perform the necessary flush and invalidate operations. - * - * Returns the write domains flushed, for use in flush tracking. - */ -static uint32_t -i915_gem_dev_set_domain(struct drm_device *dev) -{ - uint32_t flush_domains = dev->flush_domains; - - /* - * Now that all the buffers are synced to the proper domains, - * flush and invalidate the collected domains + /* It should now be out of any other write domains, and we can update + * the domain values for our changes. */ - if (dev->invalidate_domains | dev->flush_domains) { -#if WATCH_EXEC - DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", - __func__, - dev->invalidate_domains, - dev->flush_domains); -#endif - i915_gem_flush(dev, - dev->invalidate_domains, - dev->flush_domains); - dev->invalidate_domains = 0; - dev->flush_domains = 0; - } + BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); - return flush_domains; + obj->read_domains |= I915_GEM_DOMAIN_CPU; + + return 0; } /** @@ -1503,12 +1682,12 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, struct drm_i915_gem_exec_object *entry) { struct drm_device *dev = obj->dev; + drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_gem_relocation_entry reloc; struct drm_i915_gem_relocation_entry __user *relocs; struct drm_i915_gem_object *obj_priv = obj->driver_private; int i, ret; - uint32_t last_reloc_offset = -1; - void __iomem *reloc_page = NULL; + void __iomem *reloc_page; /* Choose the GTT offset for our buffer and put it there. */ ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); @@ -1572,6 +1751,18 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, return -EINVAL; } + if (reloc.write_domain & I915_GEM_DOMAIN_CPU || + reloc.read_domains & I915_GEM_DOMAIN_CPU) { + DRM_ERROR("reloc with read/write CPU domains: " + "obj %p target %d offset %d " + "read %08x write %08x", + obj, reloc.target_handle, + (int) reloc.offset, + reloc.read_domains, + reloc.write_domain); + return -EINVAL; + } + if (reloc.write_domain && target_obj->pending_write_domain && reloc.write_domain != target_obj->pending_write_domain) { DRM_ERROR("Write domain conflict: " @@ -1612,45 +1803,22 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, continue; } - /* Now that we're going to actually write some data in, - * make sure that any rendering using this buffer's contents - * is completed. - */ - i915_gem_object_wait_rendering(obj); - - /* As we're writing through the gtt, flush - * any CPU writes before we write the relocations - */ - if (obj->write_domain & I915_GEM_DOMAIN_CPU) { - i915_gem_clflush_object(obj); - drm_agp_chipset_flush(dev); - obj->write_domain = 0; + ret = i915_gem_object_set_to_gtt_domain(obj, 1); + if (ret != 0) { + drm_gem_object_unreference(target_obj); + i915_gem_object_unpin(obj); + return -EINVAL; } /* Map the page containing the relocation we're going to * perform. */ reloc_offset = obj_priv->gtt_offset + reloc.offset; - if (reloc_page == NULL || - (last_reloc_offset & ~(PAGE_SIZE - 1)) != - (reloc_offset & ~(PAGE_SIZE - 1))) { - if (reloc_page != NULL) - iounmap(reloc_page); - - reloc_page = ioremap_wc(dev->agp->base + - (reloc_offset & - ~(PAGE_SIZE - 1)), - PAGE_SIZE); - last_reloc_offset = reloc_offset; - if (reloc_page == NULL) { - drm_gem_object_unreference(target_obj); - i915_gem_object_unpin(obj); - return -ENOMEM; - } - } - + reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, + (reloc_offset & + ~(PAGE_SIZE - 1))); reloc_entry = (uint32_t __iomem *)(reloc_page + - (reloc_offset & (PAGE_SIZE - 1))); + (reloc_offset & (PAGE_SIZE - 1))); reloc_val = target_obj_priv->gtt_offset + reloc.delta; #if WATCH_BUF @@ -1659,6 +1827,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, readl(reloc_entry), reloc_val); #endif writel(reloc_val, reloc_entry); + io_mapping_unmap_atomic(reloc_page); /* Write the updated presumed offset for this entry back out * to the user. @@ -1674,9 +1843,6 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, drm_gem_object_unreference(target_obj); } - if (reloc_page != NULL) - iounmap(reloc_page); - #if WATCH_BUF if (0) i915_gem_dump_object(obj, 128, __func__, ~0); @@ -1783,6 +1949,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, int ret, i, pinned = 0; uint64_t exec_offset; uint32_t seqno, flush_domains; + int pin_tries; #if WATCH_EXEC DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", @@ -1831,14 +1998,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, return -EBUSY; } - /* Zero the gloabl flush/invalidate flags. These - * will be modified as each object is bound to the - * gtt - */ - dev->invalidate_domains = 0; - dev->flush_domains = 0; - - /* Look up object handles and perform the relocations */ + /* Look up object handles */ for (i = 0; i < args->buffer_count; i++) { object_list[i] = drm_gem_object_lookup(dev, file_priv, exec_list[i].handle); @@ -1848,17 +2008,39 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, ret = -EBADF; goto err; } + } - object_list[i]->pending_read_domains = 0; - object_list[i]->pending_write_domain = 0; - ret = i915_gem_object_pin_and_relocate(object_list[i], - file_priv, - &exec_list[i]); - if (ret) { - DRM_ERROR("object bind and relocate failed %d\n", ret); + /* Pin and relocate */ + for (pin_tries = 0; ; pin_tries++) { + ret = 0; + for (i = 0; i < args->buffer_count; i++) { + object_list[i]->pending_read_domains = 0; + object_list[i]->pending_write_domain = 0; + ret = i915_gem_object_pin_and_relocate(object_list[i], + file_priv, + &exec_list[i]); + if (ret) + break; + pinned = i + 1; + } + /* success */ + if (ret == 0) + break; + + /* error other than GTT full, or we've already tried again */ + if (ret != -ENOMEM || pin_tries >= 1) { + DRM_ERROR("Failed to pin buffers %d\n", ret); goto err; } - pinned = i + 1; + + /* unpin all of our buffers */ + for (i = 0; i < pinned; i++) + i915_gem_object_unpin(object_list[i]); + + /* evict everyone we can from the aperture */ + ret = i915_gem_evict_everything(dev); + if (ret) + goto err; } /* Set the pending read domains for the batch buffer to COMMAND */ @@ -1868,32 +2050,37 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, i915_verify_inactive(dev, __FILE__, __LINE__); + /* Zero the global flush/invalidate flags. These + * will be modified as new domains are computed + * for each object + */ + dev->invalidate_domains = 0; + dev->flush_domains = 0; + for (i = 0; i < args->buffer_count; i++) { struct drm_gem_object *obj = object_list[i]; - struct drm_i915_gem_object *obj_priv = obj->driver_private; - - if (obj_priv->gtt_space == NULL) { - /* We evicted the buffer in the process of validating - * our set of buffers in. We could try to recover by - * kicking them everything out and trying again from - * the start. - */ - ret = -ENOMEM; - goto err; - } - /* make sure all previous memory operations have passed */ - ret = i915_gem_object_set_domain(obj, - obj->pending_read_domains, - obj->pending_write_domain); - if (ret) - goto err; + /* Compute new gpu domains and update invalidate/flush */ + i915_gem_object_set_to_gpu_domain(obj, + obj->pending_read_domains, + obj->pending_write_domain); } i915_verify_inactive(dev, __FILE__, __LINE__); - /* Flush/invalidate caches and chipset buffer */ - flush_domains = i915_gem_dev_set_domain(dev); + if (dev->invalidate_domains | dev->flush_domains) { +#if WATCH_EXEC + DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", + __func__, + dev->invalidate_domains, + dev->flush_domains); +#endif + i915_gem_flush(dev, + dev->invalidate_domains, + dev->flush_domains); + if (dev->flush_domains) + (void)i915_add_request(dev, dev->flush_domains); + } i915_verify_inactive(dev, __FILE__, __LINE__); @@ -1913,8 +2100,6 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, ~0); #endif - (void)i915_add_request(dev, flush_domains); - /* Exec the batchbuffer */ ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset); if (ret) { @@ -1942,10 +2127,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, i915_file_priv->mm.last_gem_seqno = seqno; for (i = 0; i < args->buffer_count; i++) { struct drm_gem_object *obj = object_list[i]; - struct drm_i915_gem_object *obj_priv = obj->driver_private; - i915_gem_object_move_to_active(obj); - obj_priv->last_rendering_seqno = seqno; + i915_gem_object_move_to_active(obj, seqno); #if WATCH_LRU DRM_INFO("%s: move to exec list %p\n", __func__, obj); #endif @@ -2076,11 +2259,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data, /* XXX - flush the CPU caches for pinned objects * as the X server doesn't manage domains yet */ - if (obj->write_domain & I915_GEM_DOMAIN_CPU) { - i915_gem_clflush_object(obj); - drm_agp_chipset_flush(dev); - obj->write_domain = 0; - } + i915_gem_object_flush_cpu_write_domain(obj); args->offset = obj_priv->gtt_offset; drm_gem_object_unreference(obj); mutex_unlock(&dev->struct_mutex); @@ -2130,7 +2309,14 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, } obj_priv = obj->driver_private; - args->busy = obj_priv->active; + /* Don't count being on the flushing list against the object being + * done. Otherwise, a buffer left on the flushing list but not getting + * flushed (because nobody's flushing that domain) won't ever return + * unbusy and get reused by libdrm's bo cache. The other expected + * consumer of this interface, OpenGL's occlusion queries, also specs + * that the objects get unbusy "eventually" without any interference. + */ + args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; drm_gem_object_unreference(obj); mutex_unlock(&dev->struct_mutex); @@ -2182,29 +2368,6 @@ void i915_gem_free_object(struct drm_gem_object *obj) drm_free(obj->driver_private, 1, DRM_MEM_DRIVER); } -static int -i915_gem_set_domain(struct drm_gem_object *obj, - struct drm_file *file_priv, - uint32_t read_domains, - uint32_t write_domain) -{ - struct drm_device *dev = obj->dev; - int ret; - uint32_t flush_domains; - - BUG_ON(!mutex_is_locked(&dev->struct_mutex)); - - ret = i915_gem_object_set_domain(obj, read_domains, write_domain); - if (ret) - return ret; - flush_domains = i915_gem_dev_set_domain(obj->dev); - - if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) - (void) i915_add_request(dev, flush_domains); - - return 0; -} - /** Unbinds all objects that are on the given buffer list. */ static int i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) @@ -2299,29 +2462,52 @@ i915_gem_idle(struct drm_device *dev) i915_gem_retire_requests(dev); - /* Active and flushing should now be empty as we've - * waited for a sequence higher than any pending execbuffer - */ - BUG_ON(!list_empty(&dev_priv->mm.active_list)); - BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); + if (!dev_priv->mm.wedged) { + /* Active and flushing should now be empty as we've + * waited for a sequence higher than any pending execbuffer + */ + WARN_ON(!list_empty(&dev_priv->mm.active_list)); + WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); + /* Request should now be empty as we've also waited + * for the last request in the list + */ + WARN_ON(!list_empty(&dev_priv->mm.request_list)); + } - /* Request should now be empty as we've also waited - * for the last request in the list + /* Empty the active and flushing lists to inactive. If there's + * anything left at this point, it means that we're wedged and + * nothing good's going to happen by leaving them there. So strip + * the GPU domains and just stuff them onto inactive. */ - BUG_ON(!list_empty(&dev_priv->mm.request_list)); + while (!list_empty(&dev_priv->mm.active_list)) { + struct drm_i915_gem_object *obj_priv; + + obj_priv = list_first_entry(&dev_priv->mm.active_list, + struct drm_i915_gem_object, + list); + obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; + i915_gem_object_move_to_inactive(obj_priv->obj); + } + + while (!list_empty(&dev_priv->mm.flushing_list)) { + struct drm_i915_gem_object *obj_priv; - /* Move all buffers out of the GTT. */ + obj_priv = list_first_entry(&dev_priv->mm.flushing_list, + struct drm_i915_gem_object, + list); + obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; + i915_gem_object_move_to_inactive(obj_priv->obj); + } + + + /* Move all inactive buffers out of the GTT. */ ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); + WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); if (ret) { mutex_unlock(&dev->struct_mutex); return ret; } - BUG_ON(!list_empty(&dev_priv->mm.active_list)); - BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); - BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); - BUG_ON(!list_empty(&dev_priv->mm.request_list)); - i915_gem_cleanup_ringbuffer(dev); mutex_unlock(&dev->struct_mutex); @@ -2518,6 +2704,10 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data, if (ret != 0) return ret; + dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base, + dev->agp->agp_info.aper_size + * 1024 * 1024); + mutex_lock(&dev->struct_mutex); BUG_ON(!list_empty(&dev_priv->mm.active_list)); BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); @@ -2535,11 +2725,13 @@ int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { + drm_i915_private_t *dev_priv = dev->dev_private; int ret; ret = i915_gem_idle(dev); drm_irq_uninstall(dev); + io_mapping_free(dev_priv->mm.gtt_mapping); return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem_proc.c b/drivers/gpu/drm/i915/i915_gem_proc.c index 93de15b4c9a7..e8d5abe1250e 100644 --- a/drivers/gpu/drm/i915/i915_gem_proc.c +++ b/drivers/gpu/drm/i915/i915_gem_proc.c @@ -166,10 +166,9 @@ static int i915_gem_request_info(char *buf, char **start, off_t offset, list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) { - DRM_PROC_PRINT(" %d @ %d %08x\n", + DRM_PROC_PRINT(" %d @ %d\n", gem_request->seqno, - (int) (jiffies - gem_request->emitted_jiffies), - gem_request->flush_domains); + (int) (jiffies - gem_request->emitted_jiffies)); } if (len > request + offset) return request; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index e8b85ac4ca04..a8cb69469c64 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -119,9 +119,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) dcc & DCC_CHANNEL_XOR_DISABLE) { swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; - } else if (IS_I965GM(dev) || IS_GM45(dev)) { - /* GM965 only does bit 11-based channel - * randomization + } else if ((IS_I965GM(dev) || IS_GM45(dev)) && + (dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { + /* GM965/GM45 does either bit 11 or bit 17 + * swizzling. */ swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; swizzle_y = I915_BIT_6_SWIZZLE_9_11; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 26f48932a51e..69b9a42da95e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -33,11 +33,23 @@ #define MAX_NOPID ((u32)~0) -/** These are the interrupts used by the driver */ -#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \ - I915_ASLE_INTERRUPT | \ - I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) +/** + * Interrupts that are always left unmasked. + * + * Since pipe events are edge-triggered from the PIPESTAT register to IIR, + * we leave them always unmasked in IMR and then control enabling them through + * PIPESTAT alone. + */ +#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ + I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) + +/** Interrupts that we mask and unmask at runtime. */ +#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) + +/** These are all of the interrupts used by the driver */ +#define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \ + I915_INTERRUPT_ENABLE_VAR) void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) @@ -59,6 +71,41 @@ i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) } } +static inline u32 +i915_pipestat(int pipe) +{ + if (pipe == 0) + return PIPEASTAT; + if (pipe == 1) + return PIPEBSTAT; + BUG(); +} + +void +i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) +{ + if ((dev_priv->pipestat[pipe] & mask) != mask) { + u32 reg = i915_pipestat(pipe); + + dev_priv->pipestat[pipe] |= mask; + /* Enable the interrupt, clear any pending status */ + I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); + (void) I915_READ(reg); + } +} + +void +i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) +{ + if ((dev_priv->pipestat[pipe] & mask) != 0) { + u32 reg = i915_pipestat(pipe); + + dev_priv->pipestat[pipe] &= ~mask; + I915_WRITE(reg, dev_priv->pipestat[pipe]); + (void) I915_READ(reg); + } +} + /** * i915_pipe_enabled - check if a pipe is enabled * @dev: DRM device @@ -80,211 +127,6 @@ i915_pipe_enabled(struct drm_device *dev, int pipe) return 0; } -/** - * Emit blits for scheduled buffer swaps. - * - * This function will be called with the HW lock held. - * Because this function must grab the ring mutex (dev->struct_mutex), - * it can no longer run at soft irq time. We'll fix this when we do - * the DRI2 swap buffer work. - */ -static void i915_vblank_tasklet(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long irqflags; - struct list_head *list, *tmp, hits, *hit; - int nhits, nrects, slice[2], upper[2], lower[2], i; - unsigned counter[2]; - struct drm_drawable_info *drw; - drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 cpp = dev_priv->cpp; - u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | - XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB) - : XY_SRC_COPY_BLT_CMD; - u32 src_pitch = sarea_priv->pitch * cpp; - u32 dst_pitch = sarea_priv->pitch * cpp; - u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); - RING_LOCALS; - - mutex_lock(&dev->struct_mutex); - - if (IS_I965G(dev) && sarea_priv->front_tiled) { - cmd |= XY_SRC_COPY_BLT_DST_TILED; - dst_pitch >>= 2; - } - if (IS_I965G(dev) && sarea_priv->back_tiled) { - cmd |= XY_SRC_COPY_BLT_SRC_TILED; - src_pitch >>= 2; - } - - counter[0] = drm_vblank_count(dev, 0); - counter[1] = drm_vblank_count(dev, 1); - - DRM_DEBUG("\n"); - - INIT_LIST_HEAD(&hits); - - nhits = nrects = 0; - - spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); - - /* Find buffer swaps scheduled for this vertical blank */ - list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { - drm_i915_vbl_swap_t *vbl_swap = - list_entry(list, drm_i915_vbl_swap_t, head); - int pipe = vbl_swap->pipe; - - if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) - continue; - - list_del(list); - dev_priv->swaps_pending--; - drm_vblank_put(dev, pipe); - - spin_unlock(&dev_priv->swaps_lock); - spin_lock(&dev->drw_lock); - - drw = drm_get_drawable_info(dev, vbl_swap->drw_id); - - list_for_each(hit, &hits) { - drm_i915_vbl_swap_t *swap_cmp = - list_entry(hit, drm_i915_vbl_swap_t, head); - struct drm_drawable_info *drw_cmp = - drm_get_drawable_info(dev, swap_cmp->drw_id); - - /* Make sure both drawables are still - * around and have some rectangles before - * we look inside to order them for the - * blts below. - */ - if (drw_cmp && drw_cmp->num_rects > 0 && - drw && drw->num_rects > 0 && - drw_cmp->rects[0].y1 > drw->rects[0].y1) { - list_add_tail(list, hit); - break; - } - } - - spin_unlock(&dev->drw_lock); - - /* List of hits was empty, or we reached the end of it */ - if (hit == &hits) - list_add_tail(list, hits.prev); - - nhits++; - - spin_lock(&dev_priv->swaps_lock); - } - - if (nhits == 0) { - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); - mutex_unlock(&dev->struct_mutex); - return; - } - - spin_unlock(&dev_priv->swaps_lock); - - i915_kernel_lost_context(dev); - - if (IS_I965G(dev)) { - BEGIN_LP_RING(4); - - OUT_RING(GFX_OP_DRAWRECT_INFO_I965); - OUT_RING(0); - OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16)); - OUT_RING(0); - ADVANCE_LP_RING(); - } else { - BEGIN_LP_RING(6); - - OUT_RING(GFX_OP_DRAWRECT_INFO); - OUT_RING(0); - OUT_RING(0); - OUT_RING(sarea_priv->width | sarea_priv->height << 16); - OUT_RING(sarea_priv->width | sarea_priv->height << 16); - OUT_RING(0); - - ADVANCE_LP_RING(); - } - - sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT; - - upper[0] = upper[1] = 0; - slice[0] = max(sarea_priv->pipeA_h / nhits, 1); - slice[1] = max(sarea_priv->pipeB_h / nhits, 1); - lower[0] = sarea_priv->pipeA_y + slice[0]; - lower[1] = sarea_priv->pipeB_y + slice[0]; - - spin_lock(&dev->drw_lock); - - /* Emit blits for buffer swaps, partitioning both outputs into as many - * slices as there are buffer swaps scheduled in order to avoid tearing - * (based on the assumption that a single buffer swap would always - * complete before scanout starts). - */ - for (i = 0; i++ < nhits; - upper[0] = lower[0], lower[0] += slice[0], - upper[1] = lower[1], lower[1] += slice[1]) { - if (i == nhits) - lower[0] = lower[1] = sarea_priv->height; - - list_for_each(hit, &hits) { - drm_i915_vbl_swap_t *swap_hit = - list_entry(hit, drm_i915_vbl_swap_t, head); - struct drm_clip_rect *rect; - int num_rects, pipe; - unsigned short top, bottom; - - drw = drm_get_drawable_info(dev, swap_hit->drw_id); - - /* The drawable may have been destroyed since - * the vblank swap was queued - */ - if (!drw) - continue; - - rect = drw->rects; - pipe = swap_hit->pipe; - top = upper[pipe]; - bottom = lower[pipe]; - - for (num_rects = drw->num_rects; num_rects--; rect++) { - int y1 = max(rect->y1, top); - int y2 = min(rect->y2, bottom); - - if (y1 >= y2) - continue; - - BEGIN_LP_RING(8); - - OUT_RING(cmd); - OUT_RING(ropcpp | dst_pitch); - OUT_RING((y1 << 16) | rect->x1); - OUT_RING((y2 << 16) | rect->x2); - OUT_RING(sarea_priv->front_offset); - OUT_RING((y1 << 16) | rect->x1); - OUT_RING(src_pitch); - OUT_RING(sarea_priv->back_offset); - - ADVANCE_LP_RING(); - } - } - } - - spin_unlock_irqrestore(&dev->drw_lock, irqflags); - mutex_unlock(&dev->struct_mutex); - - list_for_each_safe(hit, tmp, &hits) { - drm_i915_vbl_swap_t *swap_hit = - list_entry(hit, drm_i915_vbl_swap_t, head); - - list_del(hit); - - drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER); - } -} - /* Called from drm generic code, passed a 'crtc', which * we use as a pipe index */ @@ -322,121 +164,106 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) return count; } -void -i915_vblank_work_handler(struct work_struct *work) -{ - drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, - vblank_work); - struct drm_device *dev = dev_priv->dev; - unsigned long irqflags; - - if (dev->lock.hw_lock == NULL) { - i915_vblank_tasklet(dev); - return; - } - - spin_lock_irqsave(&dev->tasklet_lock, irqflags); - dev->locked_tasklet_func = i915_vblank_tasklet; - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - - /* Try to get the lock now, if this fails, the lock - * holder will execute the tasklet during unlock - */ - if (!drm_lock_take(&dev->lock, DRM_KERNEL_CONTEXT)) - return; - - dev->lock.lock_time = jiffies; - atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); - - spin_lock_irqsave(&dev->tasklet_lock, irqflags); - dev->locked_tasklet_func = NULL; - spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); - - i915_vblank_tasklet(dev); - drm_lock_free(&dev->lock, DRM_KERNEL_CONTEXT); -} - irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) { struct drm_device *dev = (struct drm_device *) arg; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 iir; + u32 iir, new_iir; u32 pipea_stats, pipeb_stats; + u32 vblank_status; + u32 vblank_enable; int vblank = 0; + unsigned long irqflags; + int irq_received; + int ret = IRQ_NONE; atomic_inc(&dev_priv->irq_received); - if (dev->pdev->msi_enabled) - I915_WRITE(IMR, ~0); iir = I915_READ(IIR); - if (iir == 0) { - if (dev->pdev->msi_enabled) { - I915_WRITE(IMR, dev_priv->irq_mask_reg); - (void) I915_READ(IMR); - } - return IRQ_NONE; + if (IS_I965G(dev)) { + vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; + vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; + } else { + vblank_status = I915_VBLANK_INTERRUPT_STATUS; + vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; } - /* - * Clear the PIPE(A|B)STAT regs before the IIR otherwise - * we may get extra interrupts. - */ - if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { + for (;;) { + irq_received = iir != 0; + + /* Can't rely on pipestat interrupt bit in iir as it might + * have been cleared after the pipestat interrupt was received. + * It doesn't set the bit in iir again, but it still produces + * interrupts (for non-MSI). + */ + spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); pipea_stats = I915_READ(PIPEASTAT); - if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)) - pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | - PIPE_VBLANK_INTERRUPT_ENABLE); - else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| - PIPE_VBLANK_INTERRUPT_STATUS)) { + pipeb_stats = I915_READ(PIPEBSTAT); + /* + * Clear the PIPE(A|B)STAT regs before the IIR + */ + if (pipea_stats & 0x8000ffff) { + I915_WRITE(PIPEASTAT, pipea_stats); + irq_received = 1; + } + + if (pipeb_stats & 0x8000ffff) { + I915_WRITE(PIPEBSTAT, pipeb_stats); + irq_received = 1; + } + spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); + + if (!irq_received) + break; + + ret = IRQ_HANDLED; + + I915_WRITE(IIR, iir); + new_iir = I915_READ(IIR); /* Flush posted writes */ + + if (dev_priv->sarea_priv) + dev_priv->sarea_priv->last_dispatch = + READ_BREADCRUMB(dev_priv); + + if (iir & I915_USER_INTERRUPT) { + dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); + DRM_WAKEUP(&dev_priv->irq_queue); + } + + if (pipea_stats & vblank_status) { vblank++; drm_handle_vblank(dev, 0); } - I915_WRITE(PIPEASTAT, pipea_stats); - } - if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { - pipeb_stats = I915_READ(PIPEBSTAT); - /* Ack the event */ - I915_WRITE(PIPEBSTAT, pipeb_stats); - - /* The vblank interrupt gets enabled even if we didn't ask for - it, so make sure it's shut down again */ - if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)) - pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | - PIPE_VBLANK_INTERRUPT_ENABLE); - else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| - PIPE_VBLANK_INTERRUPT_STATUS)) { + if (pipeb_stats & vblank_status) { vblank++; drm_handle_vblank(dev, 1); } - if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) + if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || + (iir & I915_ASLE_INTERRUPT)) opregion_asle_intr(dev); - I915_WRITE(PIPEBSTAT, pipeb_stats); - } - - I915_WRITE(IIR, iir); - if (dev->pdev->msi_enabled) - I915_WRITE(IMR, dev_priv->irq_mask_reg); - (void) I915_READ(IIR); /* Flush posted writes */ - - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->last_dispatch = - READ_BREADCRUMB(dev_priv); - if (iir & I915_USER_INTERRUPT) { - dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); - DRM_WAKEUP(&dev_priv->irq_queue); + /* With MSI, interrupts are only generated when iir + * transitions from zero to nonzero. If another bit got + * set while we were handling the existing iir bits, then + * we would never get another interrupt. + * + * This is fine on non-MSI as well, as if we hit this path + * we avoid exiting the interrupt handler only to generate + * another one. + * + * Note that for MSI this could cause a stray interrupt report + * if an interrupt landed in the time between writing IIR and + * the posting read. This should be rare enough to never + * trigger the 99% of 100,000 interrupts test for disabling + * stray interrupts. + */ + iir = new_iir; } - if (iir & I915_ASLE_INTERRUPT) - opregion_asle_intr(dev); - - if (vblank && dev_priv->swaps_pending > 0) - schedule_work(&dev_priv->vblank_work); - - return IRQ_HANDLED; + return ret; } static int i915_emit_irq(struct drm_device * dev) @@ -454,12 +281,10 @@ static int i915_emit_irq(struct drm_device * dev) if (dev_priv->sarea_priv) dev_priv->sarea_priv->last_enqueue = dev_priv->counter; - BEGIN_LP_RING(6); + BEGIN_LP_RING(4); OUT_RING(MI_STORE_DWORD_INDEX); - OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); + OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); OUT_RING(dev_priv->counter); - OUT_RING(0); - OUT_RING(0); OUT_RING(MI_USER_INTERRUPT); ADVANCE_LP_RING(); @@ -574,48 +399,16 @@ int i915_irq_wait(struct drm_device *dev, void *data, int i915_enable_vblank(struct drm_device *dev, int pipe) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 pipestat_reg = 0; - u32 pipestat; - u32 interrupt = 0; unsigned long irqflags; - switch (pipe) { - case 0: - pipestat_reg = PIPEASTAT; - interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; - break; - case 1: - pipestat_reg = PIPEBSTAT; - interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; - break; - default: - DRM_ERROR("tried to enable vblank on non-existent pipe %d\n", - pipe); - return 0; - } - spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); - /* Enabling vblank events in IMR comes before PIPESTAT write, or - * there's a race where the PIPESTAT vblank bit gets set to 1, so - * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in - * ISR flashes to 1, but the IIR bit doesn't get set to 1 because - * IMR masks it. It doesn't ever get set after we clear the masking - * in IMR because the ISR bit is edge, not level-triggered, on the - * OR of PIPESTAT bits. - */ - i915_enable_irq(dev_priv, interrupt); - pipestat = I915_READ(pipestat_reg); if (IS_I965G(dev)) - pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE; + i915_enable_pipestat(dev_priv, pipe, + PIPE_START_VBLANK_INTERRUPT_ENABLE); else - pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE; - /* Clear any stale interrupt status */ - pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | - PIPE_VBLANK_INTERRUPT_STATUS); - I915_WRITE(pipestat_reg, pipestat); - (void) I915_READ(pipestat_reg); /* Posting read */ + i915_enable_pipestat(dev_priv, pipe, + PIPE_VBLANK_INTERRUPT_ENABLE); spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); - return 0; } @@ -625,37 +418,12 @@ int i915_enable_vblank(struct drm_device *dev, int pipe) void i915_disable_vblank(struct drm_device *dev, int pipe) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 pipestat_reg = 0; - u32 pipestat; - u32 interrupt = 0; unsigned long irqflags; - switch (pipe) { - case 0: - pipestat_reg = PIPEASTAT; - interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; - break; - case 1: - pipestat_reg = PIPEBSTAT; - interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; - break; - default: - DRM_ERROR("tried to disable vblank on non-existent pipe %d\n", - pipe); - return; - break; - } - spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); - i915_disable_irq(dev_priv, interrupt); - pipestat = I915_READ(pipestat_reg); - pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | - PIPE_VBLANK_INTERRUPT_ENABLE); - /* Clear any stale interrupt status */ - pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | - PIPE_VBLANK_INTERRUPT_STATUS); - I915_WRITE(pipestat_reg, pipestat); - (void) I915_READ(pipestat_reg); /* Posting read */ + i915_disable_pipestat(dev_priv, pipe, + PIPE_VBLANK_INTERRUPT_ENABLE | + PIPE_START_VBLANK_INTERRUPT_ENABLE); spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); } @@ -696,123 +464,21 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data, int i915_vblank_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_vblank_swap_t *swap = data; - drm_i915_vbl_swap_t *vbl_swap, *vbl_old; - unsigned int pipe, seqtype, curseq; - unsigned long irqflags; - struct list_head *list; - int ret; - - if (!dev_priv || !dev_priv->sarea_priv) { - DRM_ERROR("%s called with no initialization\n", __func__); - return -EINVAL; - } - - if (dev_priv->sarea_priv->rotation) { - DRM_DEBUG("Rotation not supported\n"); - return -EINVAL; - } - - if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | - _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) { - DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); - return -EINVAL; - } - - pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; - - seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); - - if (!(dev_priv->vblank_pipe & (1 << pipe))) { - DRM_ERROR("Invalid pipe %d\n", pipe); - return -EINVAL; - } - - spin_lock_irqsave(&dev->drw_lock, irqflags); - - if (!drm_get_drawable_info(dev, swap->drawable)) { - spin_unlock_irqrestore(&dev->drw_lock, irqflags); - DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); - return -EINVAL; - } - - spin_unlock_irqrestore(&dev->drw_lock, irqflags); - - /* - * We take the ref here and put it when the swap actually completes - * in the tasklet. + /* The delayed swap mechanism was fundamentally racy, and has been + * removed. The model was that the client requested a delayed flip/swap + * from the kernel, then waited for vblank before continuing to perform + * rendering. The problem was that the kernel might wake the client + * up before it dispatched the vblank swap (since the lock has to be + * held while touching the ringbuffer), in which case the client would + * clear and start the next frame before the swap occurred, and + * flicker would occur in addition to likely missing the vblank. + * + * In the absence of this ioctl, userland falls back to a correct path + * of waiting for a vblank, then dispatching the swap on its own. + * Context switching to userland and back is plenty fast enough for + * meeting the requirements of vblank swapping. */ - ret = drm_vblank_get(dev, pipe); - if (ret) - return ret; - curseq = drm_vblank_count(dev, pipe); - - if (seqtype == _DRM_VBLANK_RELATIVE) - swap->sequence += curseq; - - if ((curseq - swap->sequence) <= (1<<23)) { - if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) { - swap->sequence = curseq + 1; - } else { - DRM_DEBUG("Missed target sequence\n"); - drm_vblank_put(dev, pipe); - return -EINVAL; - } - } - - vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER); - - if (!vbl_swap) { - DRM_ERROR("Failed to allocate memory to queue swap\n"); - drm_vblank_put(dev, pipe); - return -ENOMEM; - } - - vbl_swap->drw_id = swap->drawable; - vbl_swap->pipe = pipe; - vbl_swap->sequence = swap->sequence; - - spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); - - list_for_each(list, &dev_priv->vbl_swaps.head) { - vbl_old = list_entry(list, drm_i915_vbl_swap_t, head); - - if (vbl_old->drw_id == swap->drawable && - vbl_old->pipe == pipe && - vbl_old->sequence == swap->sequence) { - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); - drm_vblank_put(dev, pipe); - drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); - DRM_DEBUG("Already scheduled\n"); - return 0; - } - } - - if (dev_priv->swaps_pending >= 10) { - DRM_DEBUG("Too many swaps queued\n"); - DRM_DEBUG(" pipe 0: %d pipe 1: %d\n", - drm_vblank_count(dev, 0), - drm_vblank_count(dev, 1)); - - list_for_each(list, &dev_priv->vbl_swaps.head) { - vbl_old = list_entry(list, drm_i915_vbl_swap_t, head); - DRM_DEBUG("\tdrw %x pipe %d seq %x\n", - vbl_old->drw_id, vbl_old->pipe, - vbl_old->sequence); - } - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); - drm_vblank_put(dev, pipe); - drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); - return -EBUSY; - } - - list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head); - dev_priv->swaps_pending++; - - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); - - return 0; + return -EINVAL; } /* drm_dma.h hooks @@ -822,37 +488,35 @@ void i915_driver_irq_preinstall(struct drm_device * dev) drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; I915_WRITE(HWSTAM, 0xeffe); + I915_WRITE(PIPEASTAT, 0); + I915_WRITE(PIPEBSTAT, 0); I915_WRITE(IMR, 0xffffffff); I915_WRITE(IER, 0x0); + (void) I915_READ(IER); } int i915_driver_irq_postinstall(struct drm_device *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - int ret, num_pipes = 2; - - spin_lock_init(&dev_priv->swaps_lock); - INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); - INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_handler); - dev_priv->swaps_pending = 0; - - /* Set initial unmasked IRQs to just the selected vblank pipes. */ - dev_priv->irq_mask_reg = ~0; - - ret = drm_vblank_init(dev, num_pipes); - if (ret) - return ret; dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; - dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; - dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ - dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK; + /* Unmask the interrupts that we always want on. */ + dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; + + dev_priv->pipestat[0] = 0; + dev_priv->pipestat[1] = 0; + + /* Disable pipe interrupt enables, clear pending pipe status */ + I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); + I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); + /* Clear pending interrupt status */ + I915_WRITE(IIR, I915_READ(IIR)); - I915_WRITE(IMR, dev_priv->irq_mask_reg); I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); + I915_WRITE(IMR, dev_priv->irq_mask_reg); (void) I915_READ(IER); opregion_enable_asle(dev); @@ -864,7 +528,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev) void i915_driver_irq_uninstall(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 temp; if (!dev_priv) return; @@ -872,13 +535,12 @@ void i915_driver_irq_uninstall(struct drm_device * dev) dev_priv->vblank_pipe = 0; I915_WRITE(HWSTAM, 0xffffffff); + I915_WRITE(PIPEASTAT, 0); + I915_WRITE(PIPEBSTAT, 0); I915_WRITE(IMR, 0xffffffff); I915_WRITE(IER, 0x0); - temp = I915_READ(PIPEASTAT); - I915_WRITE(PIPEASTAT, temp); - temp = I915_READ(PIPEBSTAT); - I915_WRITE(PIPEBSTAT, temp); - temp = I915_READ(IIR); - I915_WRITE(IIR, temp); + I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); + I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); + I915_WRITE(IIR, I915_READ(IIR)); } diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c index 1787a0c7e3ab..13ae731a33db 100644 --- a/drivers/gpu/drm/i915/i915_opregion.c +++ b/drivers/gpu/drm/i915/i915_opregion.c @@ -235,17 +235,15 @@ void opregion_enable_asle(struct drm_device *dev) struct opregion_asle *asle = dev_priv->opregion.asle; if (asle) { - u32 pipeb_stats = I915_READ(PIPEBSTAT); if (IS_MOBILE(dev)) { - /* Many devices trigger events with a write to the - legacy backlight controller, so we need to ensure - that it's able to generate interrupts */ - I915_WRITE(PIPEBSTAT, pipeb_stats |= - I915_LEGACY_BLC_EVENT_ENABLE); - i915_enable_irq(dev_priv, I915_ASLE_INTERRUPT | - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); - } else - i915_enable_irq(dev_priv, I915_ASLE_INTERRUPT); + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); + i915_enable_pipestat(dev_priv, 1, + I915_LEGACY_BLC_EVENT_ENABLE); + spin_unlock_irqrestore(&dev_priv->user_irq_lock, + irqflags); + } asle->tche = ASLE_ALS_EN | ASLE_BLC_EN | ASLE_PFIT_EN | ASLE_PFMB_EN; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5c2d9f206d05..9d24aaeb8a45 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -522,11 +522,15 @@ #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) #define DCC_ADDRESSING_MODE_MASK (3 << 0) #define DCC_CHANNEL_XOR_DISABLE (1 << 10) +#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) /** 965 MCH register controlling DRAM channel configuration */ #define C0DRB3 0x10206 #define C1DRB3 0x10606 +/** GM965 GM45 render standby register */ +#define MCHBAR_RENDER_STANDBY 0x111B8 + /* * Overlay regs */ diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 603fe742ccd4..5d84027ee8f3 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -240,6 +240,13 @@ int i915_save_state(struct drm_device *dev) pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); + /* Render Standby */ + if (IS_I965G(dev) && IS_MOBILE(dev)) + dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); + + /* Hardware status page */ + dev_priv->saveHWS = I915_READ(HWS_PGA); + /* Display arbitration control */ dev_priv->saveDSPARB = I915_READ(DSPARB); @@ -365,6 +372,14 @@ int i915_restore_state(struct drm_device *dev) pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); + /* Render Standby */ + if (IS_I965G(dev) && IS_MOBILE(dev)) + I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); + + /* Hardware status page */ + I915_WRITE(HWS_PGA, dev_priv->saveHWS); + + /* Display arbitration */ I915_WRITE(DSPARB, dev_priv->saveDSPARB); /* Pipe & plane A info */ diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c index c1d12dbfa8d8..b49c5ff29585 100644 --- a/drivers/gpu/drm/mga/mga_dma.c +++ b/drivers/gpu/drm/mga/mga_dma.c @@ -396,6 +396,7 @@ int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf) int mga_driver_load(struct drm_device * dev, unsigned long flags) { drm_mga_private_t *dev_priv; + int ret; dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); if (!dev_priv) @@ -415,6 +416,13 @@ int mga_driver_load(struct drm_device * dev, unsigned long flags) dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; + ret = drm_vblank_init(dev, 1); + + if (ret) { + (void) mga_driver_unload(dev); + return ret; + } + return 0; } diff --git a/drivers/gpu/drm/mga/mga_irq.c b/drivers/gpu/drm/mga/mga_irq.c index bab42f41188b..daa6041a483a 100644 --- a/drivers/gpu/drm/mga/mga_irq.c +++ b/drivers/gpu/drm/mga/mga_irq.c @@ -152,11 +152,6 @@ void mga_driver_irq_preinstall(struct drm_device * dev) int mga_driver_irq_postinstall(struct drm_device *dev) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - int ret; - - ret = drm_vblank_init(dev, 1); - if (ret) - return ret; DRM_INIT_WAITQUEUE(&dev_priv->fence_queue); diff --git a/drivers/gpu/drm/r128/r128_drv.c b/drivers/gpu/drm/r128/r128_drv.c index 3265d53ba91f..601f4c0e5da5 100644 --- a/drivers/gpu/drm/r128/r128_drv.c +++ b/drivers/gpu/drm/r128/r128_drv.c @@ -45,6 +45,7 @@ static struct drm_driver driver = { DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, .dev_priv_size = sizeof(drm_r128_buf_priv_t), + .load = r128_driver_load, .preclose = r128_driver_preclose, .lastclose = r128_driver_lastclose, .get_vblank_counter = r128_get_vblank_counter, @@ -84,6 +85,11 @@ static struct drm_driver driver = { .patchlevel = DRIVER_PATCHLEVEL, }; +int r128_driver_load(struct drm_device * dev, unsigned long flags) +{ + return drm_vblank_init(dev, 1); +} + static int __init r128_init(void) { driver.num_ioctls = r128_max_ioctl; diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h index 5898b274279d..797a26c42dab 100644 --- a/drivers/gpu/drm/r128/r128_drv.h +++ b/drivers/gpu/drm/r128/r128_drv.h @@ -159,6 +159,7 @@ extern void r128_driver_irq_preinstall(struct drm_device * dev); extern int r128_driver_irq_postinstall(struct drm_device *dev); extern void r128_driver_irq_uninstall(struct drm_device * dev); extern void r128_driver_lastclose(struct drm_device * dev); +extern int r128_driver_load(struct drm_device * dev, unsigned long flags); extern void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv); diff --git a/drivers/gpu/drm/r128/r128_irq.c b/drivers/gpu/drm/r128/r128_irq.c index d7349012a680..69810fb8ac49 100644 --- a/drivers/gpu/drm/r128/r128_irq.c +++ b/drivers/gpu/drm/r128/r128_irq.c @@ -102,7 +102,7 @@ void r128_driver_irq_preinstall(struct drm_device * dev) int r128_driver_irq_postinstall(struct drm_device *dev) { - return drm_vblank_init(dev, 1); + return 0; } void r128_driver_irq_uninstall(struct drm_device * dev) diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 59a2132a8f57..dcebb4bee7aa 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -653,15 +653,16 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); /* Turn on bus mastering */ - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { - /* rs400, rs690/rs740 */ - tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; + /* rs600/rs690/rs740 */ + tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; RADEON_WRITE(RADEON_BUS_CNTL, tmp); - } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || - ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) { - /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { + /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; RADEON_WRITE(RADEON_BUS_CNTL, tmp); } /* PCIE cards appears to not need this */ @@ -1750,6 +1751,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) else dev_priv->flags |= RADEON_IS_PCI; + ret = drm_addmap(dev, drm_get_resource_start(dev, 2), + drm_get_resource_len(dev, 2), _DRM_REGISTERS, + _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); + if (ret != 0) + return ret; + + ret = drm_vblank_init(dev, 2); + if (ret) { + radeon_driver_unload(dev); + return ret; + } + DRM_DEBUG("%s card detected\n", ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); return ret; @@ -1766,12 +1779,6 @@ int radeon_driver_firstopen(struct drm_device *dev) dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; - ret = drm_addmap(dev, drm_get_resource_start(dev, 2), - drm_get_resource_len(dev, 2), _DRM_REGISTERS, - _DRM_READ_ONLY, &dev_priv->mmio); - if (ret != 0) - return ret; - dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); ret = drm_addmap(dev, dev_priv->fb_aper_offset, drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, @@ -1787,6 +1794,9 @@ int radeon_driver_unload(struct drm_device *dev) drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); + + drm_rmmap(dev, dev_priv->mmio); + drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); dev->dev_private = NULL; diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 4dbb813910c3..3bbb871b25d5 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -287,7 +287,6 @@ typedef struct drm_radeon_private { unsigned long gart_textures_offset; drm_local_map_t *sarea; - drm_local_map_t *mmio; drm_local_map_t *cp_ring; drm_local_map_t *ring_rptr; drm_local_map_t *gart_textures; @@ -300,7 +299,6 @@ typedef struct drm_radeon_private { atomic_t swi_emitted; int vblank_crtc; uint32_t irq_enable_reg; - int irq_enabled; uint32_t r500_disp_irq_reg; struct radeon_surface surfaces[RADEON_MAX_SURFACES]; @@ -318,6 +316,7 @@ typedef struct drm_radeon_private { int num_gb_pipes; int track_flush; + drm_local_map_t *mmio; } drm_radeon_private_t; typedef struct drm_radeon_buf_priv { @@ -447,12 +446,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, * handling, not bus mastering itself. */ #define RADEON_BUS_CNTL 0x0030 -/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ +/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ # define RADEON_BUS_MASTER_DIS (1 << 6) -/* rs400, rs690/rs740 */ -# define RS400_BUS_MASTER_DIS (1 << 14) -# define RS400_MSI_REARM (1 << 20) -/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ +/* rs600/rs690/rs740 */ +# define RS600_BUS_MASTER_DIS (1 << 14) +# define RS600_MSI_REARM (1 << 20) +/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ #define RADEON_BUS_CNTL1 0x0034 # define RADEON_PMI_BM_DIS (1 << 2) @@ -937,7 +936,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -# define RS480_MSI_REARM (1 << 3) +# define RS400_MSI_REARM (1 << 3) #define RADEON_AIC_STAT 0x01d4 #define RADEON_AIC_PT_BASE 0x01d8 #define RADEON_AIC_LO_ADDR 0x01dc diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c index 5079f7054a2f..99be11418ac2 100644 --- a/drivers/gpu/drm/radeon/radeon_irq.c +++ b/drivers/gpu/drm/radeon/radeon_irq.c @@ -44,7 +44,8 @@ void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state) else dev_priv->irq_enable_reg &= ~mask; - RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); + if (!dev->irq_enabled) + RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); } static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) @@ -56,7 +57,8 @@ static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) else dev_priv->r500_disp_irq_reg &= ~mask; - RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); + if (!dev->irq_enabled) + RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); } int radeon_enable_vblank(struct drm_device *dev, int crtc) @@ -337,15 +339,10 @@ int radeon_driver_irq_postinstall(struct drm_device *dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; - int ret; atomic_set(&dev_priv->swi_emitted, 0); DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); - ret = drm_vblank_init(dev, 2); - if (ret) - return ret; - dev->max_vblank_count = 0x001fffff; radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); @@ -360,8 +357,6 @@ void radeon_driver_irq_uninstall(struct drm_device * dev) if (!dev_priv) return; - dev_priv->irq_enabled = 0; - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) RADEON_WRITE(R500_DxMODE_INT_MASK, 0); /* Disable *all* interrupts */ diff --git a/drivers/gpu/drm/via/via_irq.c b/drivers/gpu/drm/via/via_irq.c index 665d319b927b..c248c1d37268 100644 --- a/drivers/gpu/drm/via/via_irq.c +++ b/drivers/gpu/drm/via/via_irq.c @@ -314,7 +314,6 @@ int via_driver_irq_postinstall(struct drm_device *dev) if (!dev_priv) return -EINVAL; - drm_vblank_init(dev, 1); status = VIA_READ(VIA_REG_INTERRUPT); VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL | dev_priv->irq_enable_mask); diff --git a/drivers/gpu/drm/via/via_map.c b/drivers/gpu/drm/via/via_map.c index a967556be014..2c4f0b485792 100644 --- a/drivers/gpu/drm/via/via_map.c +++ b/drivers/gpu/drm/via/via_map.c @@ -107,8 +107,17 @@ int via_driver_load(struct drm_device *dev, unsigned long chipset) ret = drm_sman_init(&dev_priv->sman, 2, 12, 8); if (ret) { drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); + return ret; } - return ret; + + ret = drm_vblank_init(dev, 1); + if (ret) { + drm_sman_takedown(&dev_priv->sman); + drm_free(dev_priv, sizeof(drm_via_private_t), DRM_MEM_DRIVER); + return ret; + } + + return 0; } int via_driver_unload(struct drm_device *dev) diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig index f5999a91614e..b4fd8ca701a4 100644 --- a/drivers/hid/Kconfig +++ b/drivers/hid/Kconfig @@ -247,7 +247,6 @@ config HID_SUNPLUS config THRUSTMASTER_FF tristate "ThrustMaster devices support" - default m depends on USB_HID select INPUT_FF_MEMLESS help @@ -256,7 +255,6 @@ config THRUSTMASTER_FF config ZEROPLUS_FF tristate "Zeroplus based game controller support" - default m depends on USB_HID select INPUT_FF_MEMLESS help diff --git a/drivers/hid/hid-apple.c b/drivers/hid/hid-apple.c index fd7f896b34f7..aa28aed0e46c 100644 --- a/drivers/hid/hid-apple.c +++ b/drivers/hid/hid-apple.c @@ -55,10 +55,11 @@ struct apple_key_translation { static struct apple_key_translation apple_fn_keys[] = { { KEY_BACKSPACE, KEY_DELETE }, + { KEY_ENTER, KEY_INSERT }, { KEY_F1, KEY_BRIGHTNESSDOWN, APPLE_FLAG_FKEY }, { KEY_F2, KEY_BRIGHTNESSUP, APPLE_FLAG_FKEY }, - { KEY_F3, KEY_FN_F5, APPLE_FLAG_FKEY }, /* Exposé */ - { KEY_F4, KEY_FN_F4, APPLE_FLAG_FKEY }, /* Dashboard */ + { KEY_F3, KEY_SCALE, APPLE_FLAG_FKEY }, + { KEY_F4, KEY_DASHBOARD, APPLE_FLAG_FKEY }, { KEY_F5, KEY_KBDILLUMDOWN, APPLE_FLAG_FKEY }, { KEY_F6, KEY_KBDILLUMUP, APPLE_FLAG_FKEY }, { KEY_F7, KEY_PREVIOUSSONG, APPLE_FLAG_FKEY }, @@ -312,13 +313,6 @@ static int apple_probe(struct hid_device *hdev, unsigned int connect_mask = HID_CONNECT_DEFAULT; int ret; - /* return something else or move to hid layer? device will reside - allocated */ - if (id->bus == BUS_USB && (quirks & APPLE_IGNORE_MOUSE) && - to_usb_interface(hdev->dev.parent)->cur_altsetting-> - desc.bInterfaceProtocol == USB_INTERFACE_PROTOCOL_MOUSE) - return -ENODEV; - asc = kzalloc(sizeof(*asc), GFP_KERNEL); if (asc == NULL) { dev_err(&hdev->dev, "can't alloc apple descriptor\n"); @@ -367,38 +361,32 @@ static const struct hid_device_id apple_devices[] = { .driver_data = APPLE_MIGHTYMOUSE | APPLE_INVERT_HWHEEL }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ISO), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ANSI), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ISO), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE | APPLE_ISO_KEYBOARD }, + APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_JIS), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_ANSI), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_ISO), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE | APPLE_ISO_KEYBOARD }, + APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_JIS), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE | APPLE_RDESC_JIS }, + APPLE_RDESC_JIS }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_ANSI), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_ISO), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE | APPLE_ISO_KEYBOARD }, + APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_JIS), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE | APPLE_RDESC_JIS}, + APPLE_RDESC_JIS }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ANSI), .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ISO), @@ -406,41 +394,41 @@ static const struct hid_device_id apple_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_JIS), .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ISO), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_JIS), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE | APPLE_RDESC_JIS }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI), + APPLE_RDESC_JIS }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO), + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | APPLE_ISO_KEYBOARD }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS), + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS), .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_ANSI), - .driver_data = APPLE_HAS_FN | APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_ISO), - .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_JIS), - .driver_data = APPLE_HAS_FN | APPLE_IGNORE_MOUSE | APPLE_RDESC_JIS }, + .driver_data = APPLE_HAS_FN | APPLE_RDESC_JIS }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_ANSI), - .driver_data = APPLE_HAS_FN | APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_ISO), - .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_JIS), - .driver_data = APPLE_HAS_FN | APPLE_IGNORE_MOUSE | APPLE_RDESC_JIS }, + .driver_data = APPLE_HAS_FN | APPLE_RDESC_JIS }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_ANSI), + .driver_data = APPLE_HAS_FN }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_ISO), + .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_JIS), + .driver_data = APPLE_HAS_FN | APPLE_RDESC_JIS }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY), - .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN | - APPLE_IGNORE_MOUSE }, + .driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN }, /* Apple wireless Mighty Mouse */ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, 0x030c), diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index 721a36d97582..40df3e1b4bd1 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -1241,18 +1241,20 @@ static const struct hid_device_id hid_blacklist[] = { { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_JIS) }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI) }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO) }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_ANSI) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_ANSI) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING3_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) }, - { HID_USB_DEVICE(USB_VENDOR_ID_AVERMEDIA, USB_DEVICE_ID_AVER_FM_MR800) }, { HID_USB_DEVICE(USB_VENDOR_ID_BELKIN, USB_DEVICE_ID_FLIP_KVM) }, { HID_USB_DEVICE(USB_VENDOR_ID_BRIGHT, USB_DEVICE_ID_BRIGHT_ABNT2) }, { HID_USB_DEVICE(USB_VENDOR_ID_CHERRY, USB_DEVICE_ID_CHERRY_CYMOTION) }, @@ -1263,7 +1265,12 @@ static const struct hid_device_id hid_blacklist[] = { { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_W7658) }, { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_SK8115) }, { HID_USB_DEVICE(USB_VENDOR_ID_EZKEY, USB_DEVICE_ID_BTC_8193) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GENERIC_13BA, USB_DEVICE_ID_GENERIC_13BA_KBD_MOUSE) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0003) }, { HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE_2) }, { HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER) }, @@ -1275,8 +1282,6 @@ static const struct hid_device_id hid_blacklist[] = { { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KBD) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_ELITE_KBD) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_CORDLESS_DESKTOP_LX500) }, - { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_LX3) }, - { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_V150) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_EXTREME_3D) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WHEEL) }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_RUMBLEPAD) }, @@ -1295,6 +1300,7 @@ static const struct hid_device_id hid_blacklist[] = { { HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) }, { HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE) }, { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER) }, + { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE) }, { HID_USB_DEVICE(USB_VENDOR_ID_SUNPLUS, USB_DEVICE_ID_SUNPLUS_WDESKTOP) }, { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, 0x030c) }, @@ -1406,6 +1412,8 @@ static const struct hid_device_id hid_ignore_list[] = { { HID_USB_DEVICE(USB_VENDOR_ID_AIRCABLE, USB_DEVICE_ID_AIRCABLE1) }, { HID_USB_DEVICE(USB_VENDOR_ID_ALCOR, USB_DEVICE_ID_ALCOR_USBRS232) }, { HID_USB_DEVICE(USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM)}, + { HID_USB_DEVICE(USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM2)}, + { HID_USB_DEVICE(USB_VENDOR_ID_AVERMEDIA, USB_DEVICE_ID_AVER_FM_MR800) }, { HID_USB_DEVICE(USB_VENDOR_ID_BERKSHIRE, USB_DEVICE_ID_BERKSHIRE_PCWD) }, { HID_USB_DEVICE(USB_VENDOR_ID_CIDC, 0x0103) }, { HID_USB_DEVICE(USB_VENDOR_ID_CYGNAL, USB_DEVICE_ID_CYGNAL_RADIO_SI470X) }, @@ -1415,7 +1423,6 @@ static const struct hid_device_id hid_ignore_list[] = { { HID_USB_DEVICE(USB_VENDOR_ID_DELORME, USB_DEVICE_ID_DELORME_EARTHMATE) }, { HID_USB_DEVICE(USB_VENDOR_ID_DELORME, USB_DEVICE_ID_DELORME_EM_LT20) }, { HID_USB_DEVICE(USB_VENDOR_ID_ESSENTIAL_REALITY, USB_DEVICE_ID_ESSENTIAL_REALITY_P5) }, - { HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR) }, { HID_USB_DEVICE(USB_VENDOR_ID_GENERAL_TOUCH, 0x0001) }, { HID_USB_DEVICE(USB_VENDOR_ID_GENERAL_TOUCH, 0x0002) }, { HID_USB_DEVICE(USB_VENDOR_ID_GENERAL_TOUCH, 0x0003) }, @@ -1431,7 +1438,6 @@ static const struct hid_device_id hid_ignore_list[] = { { HID_USB_DEVICE(USB_VENDOR_ID_GOTOP, USB_DEVICE_ID_SUPER_Q2) }, { HID_USB_DEVICE(USB_VENDOR_ID_GOTOP, USB_DEVICE_ID_GOGOPEN) }, { HID_USB_DEVICE(USB_VENDOR_ID_GOTOP, USB_DEVICE_ID_PENPOWER) }, - { HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0003) }, { HID_USB_DEVICE(USB_VENDOR_ID_GRETAGMACBETH, USB_DEVICE_ID_GRETAGMACBETH_HUEY) }, { HID_USB_DEVICE(USB_VENDOR_ID_GRIFFIN, USB_DEVICE_ID_POWERMATE) }, { HID_USB_DEVICE(USB_VENDOR_ID_GRIFFIN, USB_DEVICE_ID_SOUNDKNOB) }, @@ -1483,6 +1489,7 @@ static const struct hid_device_id hid_ignore_list[] = { { HID_USB_DEVICE(USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_1007) }, { HID_USB_DEVICE(USB_VENDOR_ID_IMATION, USB_DEVICE_ID_DISC_STAKKA) }, { HID_USB_DEVICE(USB_VENDOR_ID_KBGEAR, USB_DEVICE_ID_KBGEAR_JAMSTUDIO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_KWORLD, USB_DEVICE_ID_KWORLD_RADIO_FM700) }, { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_GPEN_560) }, { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CASSY) }, { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POCKETCASSY) }, @@ -1541,6 +1548,40 @@ static const struct hid_device_id hid_ignore_list[] = { { } }; +/** + * hid_mouse_ignore_list - mouse devices which should not be handled by the hid layer + * + * There are composite devices for which we want to ignore only a certain + * interface. This is a list of devices for which only the mouse interface will + * be ignored. This allows a dedicated driver to take care of the interface. + */ +static const struct hid_device_id hid_mouse_ignore_list[] = { + /* appletouch driver */ + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER3_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_ANSI) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_ISO) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING2_JIS) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) }, + { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) }, + { } +}; + static bool hid_ignore(struct hid_device *hdev) { switch (hdev->vendor) { @@ -1557,6 +1598,10 @@ static bool hid_ignore(struct hid_device *hdev) break; } + if (hdev->type == HID_TYPE_USBMOUSE && + hid_match_id(hdev, hid_mouse_ignore_list)) + return true; + return !!hid_match_id(hdev, hid_ignore_list); } @@ -1689,7 +1734,7 @@ static int __init hid_init(void) goto err_bus; #ifdef CONFIG_HID_COMPAT - hid_compat_wq = create_workqueue("hid_compat"); + hid_compat_wq = create_singlethread_workqueue("hid_compat"); if (!hid_compat_wq) { hidraw_exit(); goto err; diff --git a/drivers/hid/hid-dell.c b/drivers/hid/hid-dell.c index 1a0d0dfc62fc..f5474300b83a 100644 --- a/drivers/hid/hid-dell.c +++ b/drivers/hid/hid-dell.c @@ -48,6 +48,7 @@ err_free: static const struct hid_device_id dell_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_W7658) }, { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_SK8115) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GENERIC_13BA, USB_DEVICE_ID_GENERIC_13BA_KBD_MOUSE) }, { } }; MODULE_DEVICE_TABLE(hid, dell_devices); diff --git a/drivers/hid/hid-gyration.c b/drivers/hid/hid-gyration.c index ac5120f542cc..04a0afec52ac 100644 --- a/drivers/hid/hid-gyration.c +++ b/drivers/hid/hid-gyration.c @@ -4,9 +4,9 @@ * Copyright (c) 1999 Andreas Gal * Copyright (c) 2000-2005 Vojtech Pavlik * Copyright (c) 2005 Michael Haboustak for Concept2, Inc - * Copyright (c) 2006-2007 Jiri Kosina * Copyright (c) 2007 Paul Walmsley * Copyright (c) 2008 Jiri Slaby + * Copyright (c) 2006-2008 Jiri Kosina */ /* @@ -40,6 +40,7 @@ static int gyration_input_mapping(struct hid_device *hdev, struct hid_input *hi, case 0x025: gy_map_key_clear(KEY_PVR); break; case 0x046: gy_map_key_clear(KEY_MEDIA); break; case 0x047: gy_map_key_clear(KEY_MP3); break; + case 0x048: gy_map_key_clear(KEY_MEDIA); break; case 0x049: gy_map_key_clear(KEY_CAMERA); break; case 0x04a: gy_map_key_clear(KEY_VIDEO); break; @@ -68,6 +69,7 @@ static int gyration_event(struct hid_device *hdev, struct hid_field *field, static const struct hid_device_id gyration_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE) }, + { HID_USB_DEVICE(USB_VENDOR_ID_GYRATION, USB_DEVICE_ID_GYRATION_REMOTE_2) }, { } }; MODULE_DEVICE_TABLE(hid, gyration_devices); diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index d9a1ba920c23..39289699c32f 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -82,6 +82,9 @@ #define USB_DEVICE_ID_APPLE_WELLSPRING2_ANSI 0x0230 #define USB_DEVICE_ID_APPLE_WELLSPRING2_ISO 0x0231 #define USB_DEVICE_ID_APPLE_WELLSPRING2_JIS 0x0232 +#define USB_DEVICE_ID_APPLE_WELLSPRING3_ANSI 0x0236 +#define USB_DEVICE_ID_APPLE_WELLSPRING3_ISO 0x0237 +#define USB_DEVICE_ID_APPLE_WELLSPRING3_JIS 0x0238 #define USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY 0x030a #define USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY 0x030b #define USB_DEVICE_ID_APPLE_ATV_IRCONTROL 0x8241 @@ -89,6 +92,7 @@ #define USB_VENDOR_ID_ASUS 0x0b05 #define USB_DEVICE_ID_ASUS_LCM 0x1726 +#define USB_DEVICE_ID_ASUS_LCM2 0x175b #define USB_VENDOR_ID_ATEN 0x0557 #define USB_DEVICE_ID_ATEN_UC100KM 0x2004 @@ -159,9 +163,13 @@ #define USB_VENDOR_ID_GAMERON 0x0810 #define USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR 0x0001 +#define USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR 0x0002 #define USB_VENDOR_ID_GENERAL_TOUCH 0x0dfc +#define USB_VENDOR_ID_GENERIC_13BA 0x13ba +#define USB_DEVICE_ID_GENERIC_13BA_KBD_MOUSE 0x0017 + #define USB_VENDOR_ID_GLAB 0x06c2 #define USB_DEVICE_ID_4_PHIDGETSERVO_30 0x0038 #define USB_DEVICE_ID_1_PHIDGETSERVO_30 0x0039 @@ -236,6 +244,7 @@ #define USB_VENDOR_ID_GYRATION 0x0c16 #define USB_DEVICE_ID_GYRATION_REMOTE 0x0002 +#define USB_DEVICE_ID_GYRATION_REMOTE_2 0x0003 #define USB_VENDOR_ID_HAPP 0x078b #define USB_DEVICE_ID_UGCI_DRIVING 0x0010 @@ -248,6 +257,9 @@ #define USB_VENDOR_ID_KBGEAR 0x084e #define USB_DEVICE_ID_KBGEAR_JAMSTUDIO 0x1001 +#define USB_VENDOR_ID_KWORLD 0x1b80 +#define USB_DEVICE_ID_KWORLD_RADIO_FM700 0xd700 + #define USB_VENDOR_ID_LABTEC 0x1020 #define USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD 0x0006 @@ -268,8 +280,6 @@ #define USB_DEVICE_ID_LD_MACHINETEST 0x2040 #define USB_VENDOR_ID_LOGITECH 0x046d -#define USB_DEVICE_ID_LOGITECH_LX3 0xc044 -#define USB_DEVICE_ID_LOGITECH_V150 0xc047 #define USB_DEVICE_ID_LOGITECH_RECEIVER 0xc101 #define USB_DEVICE_ID_LOGITECH_HARMONY_FIRST 0xc110 #define USB_DEVICE_ID_LOGITECH_HARMONY_LAST 0xc14f @@ -350,6 +360,7 @@ #define USB_DEVICE_ID_SAMSUNG_IR_REMOTE 0x0001 #define USB_VENDOR_ID_SONY 0x054c +#define USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE 0x024b #define USB_DEVICE_ID_SONY_PS3_CONTROLLER 0x0268 #define USB_VENDOR_ID_SOUNDGRAPH 0x15c2 diff --git a/drivers/hid/hid-lg.c b/drivers/hid/hid-lg.c index 406d8c82abf1..2bae340eafe2 100644 --- a/drivers/hid/hid-lg.c +++ b/drivers/hid/hid-lg.c @@ -287,11 +287,6 @@ static const struct hid_device_id lg_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_CORDLESS_DESKTOP_LX500), .driver_data = LG_IGNORE_DOUBLED_WHEEL | LG_EXPANDED_KEYMAP }, - { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_LX3), - .driver_data = LG_INVERT_HWHEEL }, - { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_V150), - .driver_data = LG_INVERT_HWHEEL }, - { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_EXTREME_3D), .driver_data = LG_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WHEEL), diff --git a/drivers/hid/hid-pl.c b/drivers/hid/hid-pl.c index acd815586182..46941f979b9d 100644 --- a/drivers/hid/hid-pl.c +++ b/drivers/hid/hid-pl.c @@ -178,6 +178,8 @@ err: static const struct hid_device_id pl_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR), .driver_data = 1 }, /* Twin USB Joystick */ + { HID_USB_DEVICE(USB_VENDOR_ID_GAMERON, USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR), + .driver_data = 1 }, /* Twin USB Joystick */ { HID_USB_DEVICE(USB_VENDOR_ID_GREENASIA, 0x0003), }, /* GreenAsia Inc. USB Joystick */ { } }; diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c index 3af8095a7de1..86e563b8d644 100644 --- a/drivers/hid/hid-sony.c +++ b/drivers/hid/hid-sony.c @@ -4,9 +4,9 @@ * Copyright (c) 1999 Andreas Gal * Copyright (c) 2000-2005 Vojtech Pavlik * Copyright (c) 2005 Michael Haboustak for Concept2, Inc - * Copyright (c) 2006-2007 Jiri Kosina * Copyright (c) 2007 Paul Walmsley * Copyright (c) 2008 Jiri Slaby + * Copyright (c) 2006-2008 Jiri Kosina */ /* @@ -23,6 +23,26 @@ #include "hid-ids.h" +#define VAIO_RDESC_CONSTANT 0x0001 + +struct sony_sc { + unsigned long quirks; +}; + +/* Sony Vaio VGX has wrongly mouse pointer declared as constant */ +static void sony_report_fixup(struct hid_device *hdev, __u8 *rdesc, + unsigned int rsize) +{ + struct sony_sc *sc = hid_get_drvdata(hdev); + + if ((sc->quirks & VAIO_RDESC_CONSTANT) && + rsize >= 56 && rdesc[54] == 0x81 && rdesc[55] == 0x07) { + dev_info(&hdev->dev, "Fixing up Sony Vaio VGX report " + "descriptor\n"); + rdesc[55] = 0x06; + } +} + /* * Sending HID_REQ_GET_REPORT changes the operation mode of the ps3 controller * to "operational". Without this, the ps3 controller will not report any @@ -56,6 +76,17 @@ static int sony_set_operational(struct hid_device *hdev) static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) { int ret; + unsigned long quirks = id->driver_data; + struct sony_sc *sc; + + sc = kzalloc(sizeof(*sc), GFP_KERNEL); + if (sc == NULL) { + dev_err(&hdev->dev, "can't alloc apple descriptor\n"); + return -ENOMEM; + } + + sc->quirks = quirks; + hid_set_drvdata(hdev, sc); ret = hid_parse(hdev); if (ret) { @@ -78,11 +109,20 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) err_stop: hid_hw_stop(hdev); err_free: + kfree(sc); return ret; } +static void sony_remove(struct hid_device *hdev) +{ + hid_hw_stop(hdev); + kfree(hid_get_drvdata(hdev)); +} + static const struct hid_device_id sony_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER) }, + { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE), + .driver_data = VAIO_RDESC_CONSTANT }, { } }; MODULE_DEVICE_TABLE(hid, sony_devices); @@ -91,6 +131,8 @@ static struct hid_driver sony_driver = { .name = "sony", .id_table = sony_devices, .probe = sony_probe, + .remove = sony_remove, + .report_fixup = sony_report_fixup, }; static int sony_init(void) diff --git a/drivers/hid/hidraw.c b/drivers/hid/hidraw.c index af3edb98df43..7685ae6808c4 100644 --- a/drivers/hid/hidraw.c +++ b/drivers/hid/hidraw.c @@ -38,7 +38,7 @@ static int hidraw_major; static struct cdev hidraw_cdev; static struct class *hidraw_class; static struct hidraw *hidraw_table[HIDRAW_MAX_DEVICES]; -static DEFINE_SPINLOCK(minors_lock); +static DEFINE_MUTEX(minors_lock); static ssize_t hidraw_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos) { @@ -159,13 +159,13 @@ static int hidraw_open(struct inode *inode, struct file *file) struct hidraw_list *list; int err = 0; - lock_kernel(); if (!(list = kzalloc(sizeof(struct hidraw_list), GFP_KERNEL))) { err = -ENOMEM; goto out; } - spin_lock(&minors_lock); + lock_kernel(); + mutex_lock(&minors_lock); if (!hidraw_table[minor]) { printk(KERN_EMERG "hidraw device with minor %d doesn't exist\n", minor); @@ -180,13 +180,16 @@ static int hidraw_open(struct inode *inode, struct file *file) file->private_data = list; dev = hidraw_table[minor]; - if (!dev->open++) - dev->hid->ll_driver->open(dev->hid); + if (!dev->open++) { + err = dev->hid->ll_driver->open(dev->hid); + if (err < 0) + dev->open--; + } out_unlock: - spin_unlock(&minors_lock); -out: + mutex_unlock(&minors_lock); unlock_kernel(); +out: return err; } @@ -264,6 +267,7 @@ static long hidraw_ioctl(struct file *file, unsigned int cmd, default: ret = -ENOTTY; } + unlock_kernel(); return ret; } @@ -309,7 +313,7 @@ int hidraw_connect(struct hid_device *hid) result = -EINVAL; - spin_lock(&minors_lock); + mutex_lock(&minors_lock); for (minor = 0; minor < HIDRAW_MAX_DEVICES; minor++) { if (hidraw_table[minor]) @@ -319,9 +323,8 @@ int hidraw_connect(struct hid_device *hid) break; } - spin_unlock(&minors_lock); - if (result) { + mutex_unlock(&minors_lock); kfree(dev); goto out; } @@ -330,14 +333,14 @@ int hidraw_connect(struct hid_device *hid) NULL, "%s%d", "hidraw", minor); if (IS_ERR(dev->dev)) { - spin_lock(&minors_lock); hidraw_table[minor] = NULL; - spin_unlock(&minors_lock); + mutex_unlock(&minors_lock); result = PTR_ERR(dev->dev); kfree(dev); goto out; } + mutex_unlock(&minors_lock); init_waitqueue_head(&dev->wait); INIT_LIST_HEAD(&dev->list); @@ -359,9 +362,9 @@ void hidraw_disconnect(struct hid_device *hid) hidraw->exist = 0; - spin_lock(&minors_lock); + mutex_lock(&minors_lock); hidraw_table[hidraw->minor] = NULL; - spin_unlock(&minors_lock); + mutex_unlock(&minors_lock); device_destroy(hidraw_class, MKDEV(hidraw_major, hidraw->minor)); @@ -403,7 +406,7 @@ out: return result; } -void __exit hidraw_exit(void) +void hidraw_exit(void) { dev_t dev_id = MKDEV(hidraw_major, 0); diff --git a/drivers/hid/usbhid/hid-core.c b/drivers/hid/usbhid/hid-core.c index 705a43cdeea4..606369ea24ca 100644 --- a/drivers/hid/usbhid/hid-core.c +++ b/drivers/hid/usbhid/hid-core.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -776,20 +777,11 @@ static int usbhid_start(struct hid_device *hid) struct usb_interface *intf = to_usb_interface(hid->dev.parent); struct usb_host_interface *interface = intf->cur_altsetting; struct usb_device *dev = interface_to_usbdev(intf); - struct usbhid_device *usbhid; + struct usbhid_device *usbhid = hid->driver_data; unsigned int n, insize = 0; int ret; - WARN_ON(hid->driver_data); - - usbhid = kzalloc(sizeof(struct usbhid_device), GFP_KERNEL); - if (usbhid == NULL) { - ret = -ENOMEM; - goto err; - } - - hid->driver_data = usbhid; - usbhid->hid = hid; + clear_bit(HID_DISCONNECTED, &usbhid->iofl); usbhid->bufsize = HID_MIN_BUFFER_SIZE; hid_find_max_report(hid, HID_INPUT_REPORT, &usbhid->bufsize); @@ -856,12 +848,6 @@ static int usbhid_start(struct hid_device *hid) } } - if (!usbhid->urbin) { - err_hid("couldn't find an input interrupt endpoint"); - ret = -ENODEV; - goto fail; - } - init_waitqueue_head(&usbhid->wait); INIT_WORK(&usbhid->reset_work, hid_reset); setup_timer(&usbhid->io_retry, hid_retry_timeout, (unsigned long) hid); @@ -888,15 +874,18 @@ static int usbhid_start(struct hid_device *hid) usbhid_init_reports(hid); hid_dump_device(hid); + set_bit(HID_STARTED, &usbhid->iofl); + return 0; fail: usb_free_urb(usbhid->urbin); usb_free_urb(usbhid->urbout); usb_free_urb(usbhid->urbctrl); + usbhid->urbin = NULL; + usbhid->urbout = NULL; + usbhid->urbctrl = NULL; hid_free_buffers(dev, hid); - kfree(usbhid); -err: return ret; } @@ -907,6 +896,7 @@ static void usbhid_stop(struct hid_device *hid) if (WARN_ON(!usbhid)) return; + clear_bit(HID_STARTED, &usbhid->iofl); spin_lock_irq(&usbhid->inlock); /* Sync with error handler */ set_bit(HID_DISCONNECTED, &usbhid->iofl); spin_unlock_irq(&usbhid->inlock); @@ -929,10 +919,11 @@ static void usbhid_stop(struct hid_device *hid) usb_free_urb(usbhid->urbin); usb_free_urb(usbhid->urbctrl); usb_free_urb(usbhid->urbout); + usbhid->urbin = NULL; /* don't mess up next start */ + usbhid->urbctrl = NULL; + usbhid->urbout = NULL; hid_free_buffers(hid_to_usb_dev(hid), hid); - kfree(usbhid); - hid->driver_data = NULL; } static struct hid_ll_driver usb_hid_driver = { @@ -946,14 +937,26 @@ static struct hid_ll_driver usb_hid_driver = { static int hid_probe(struct usb_interface *intf, const struct usb_device_id *id) { + struct usb_host_interface *interface = intf->cur_altsetting; struct usb_device *dev = interface_to_usbdev(intf); + struct usbhid_device *usbhid; struct hid_device *hid; + unsigned int n, has_in = 0; size_t len; int ret; dbg_hid("HID probe called for ifnum %d\n", intf->altsetting->desc.bInterfaceNumber); + for (n = 0; n < interface->desc.bNumEndpoints; n++) + if (usb_endpoint_is_int_in(&interface->endpoint[n].desc)) + has_in++; + if (!has_in) { + dev_err(&intf->dev, "couldn't find an input interrupt " + "endpoint\n"); + return -ENODEV; + } + hid = hid_allocate_device(); if (IS_ERR(hid)) return PTR_ERR(hid); @@ -972,6 +975,9 @@ static int hid_probe(struct usb_interface *intf, const struct usb_device_id *id) hid->vendor = le16_to_cpu(dev->descriptor.idVendor); hid->product = le16_to_cpu(dev->descriptor.idProduct); hid->name[0] = 0; + if (intf->cur_altsetting->desc.bInterfaceProtocol == + USB_INTERFACE_PROTOCOL_MOUSE) + hid->type = HID_TYPE_USBMOUSE; if (dev->manufacturer) strlcpy(hid->name, dev->manufacturer, sizeof(hid->name)); @@ -997,14 +1003,25 @@ static int hid_probe(struct usb_interface *intf, const struct usb_device_id *id) if (usb_string(dev, dev->descriptor.iSerialNumber, hid->uniq, 64) <= 0) hid->uniq[0] = 0; + usbhid = kzalloc(sizeof(*usbhid), GFP_KERNEL); + if (usbhid == NULL) { + ret = -ENOMEM; + goto err; + } + + hid->driver_data = usbhid; + usbhid->hid = hid; + ret = hid_add_device(hid); if (ret) { if (ret != -ENODEV) dev_err(&intf->dev, "can't add hid device: %d\n", ret); - goto err; + goto err_free; } return 0; +err_free: + kfree(usbhid); err: hid_destroy_device(hid); return ret; @@ -1013,11 +1030,14 @@ err: static void hid_disconnect(struct usb_interface *intf) { struct hid_device *hid = usb_get_intfdata(intf); + struct usbhid_device *usbhid; if (WARN_ON(!hid)) return; + usbhid = hid->driver_data; hid_destroy_device(hid); + kfree(usbhid); } static int hid_suspend(struct usb_interface *intf, pm_message_t message) @@ -1025,10 +1045,13 @@ static int hid_suspend(struct usb_interface *intf, pm_message_t message) struct hid_device *hid = usb_get_intfdata (intf); struct usbhid_device *usbhid = hid->driver_data; + if (!test_bit(HID_STARTED, &usbhid->iofl)) + return 0; + spin_lock_irq(&usbhid->inlock); /* Sync with error handler */ set_bit(HID_SUSPENDED, &usbhid->iofl); spin_unlock_irq(&usbhid->inlock); - del_timer(&usbhid->io_retry); + del_timer_sync(&usbhid->io_retry); usb_kill_urb(usbhid->urbin); dev_dbg(&intf->dev, "suspend\n"); return 0; @@ -1040,6 +1063,9 @@ static int hid_resume(struct usb_interface *intf) struct usbhid_device *usbhid = hid->driver_data; int status; + if (!test_bit(HID_STARTED, &usbhid->iofl)) + return 0; + clear_bit(HID_SUSPENDED, &usbhid->iofl); usbhid->retry_delay = 0; status = hid_start_in(hid); diff --git a/drivers/hid/usbhid/hiddev.c b/drivers/hid/usbhid/hiddev.c index babd65dd46ad..83e851a5ed30 100644 --- a/drivers/hid/usbhid/hiddev.c +++ b/drivers/hid/usbhid/hiddev.c @@ -242,8 +242,6 @@ static int hiddev_release(struct inode * inode, struct file * file) struct hiddev_list *list = file->private_data; unsigned long flags; - hiddev_fasync(-1, file, 0); - spin_lock_irqsave(&list->hiddev->list_lock, flags); list_del(&list->node); spin_unlock_irqrestore(&list->hiddev->list_lock, flags); @@ -436,8 +434,7 @@ static noinline int hiddev_ioctl_usage(struct hiddev *hiddev, unsigned int cmd, if (copy_to_user(user_arg, uref, sizeof(*uref))) goto fault; - kfree(uref_multi); - return 0; + goto goodreturn; default: if (cmd != HIDIOCGUSAGE && diff --git a/drivers/hid/usbhid/usbhid.h b/drivers/hid/usbhid/usbhid.h index abedb13c623e..332abcdf9956 100644 --- a/drivers/hid/usbhid/usbhid.h +++ b/drivers/hid/usbhid/usbhid.h @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 6de1e0ffd391..c709e821f04b 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -159,6 +159,16 @@ config SENSORS_ADM9240 This driver can also be built as a module. If so, the module will be called adm9240. +config SENSORS_ADT7462 + tristate "Analog Devices ADT7462" + depends on I2C && EXPERIMENTAL + help + If you say yes here you get support for the Analog Devices + ADT7462 temperature monitoring chips. + + This driver can also be built as a module. If so, the module + will be called adt7462. + config SENSORS_ADT7470 tristate "Analog Devices ADT7470" depends on I2C && EXPERIMENTAL @@ -825,6 +835,25 @@ config SENSORS_HDAPS Say Y here if you have an applicable laptop and want to experience the awesome power of hdaps. +config SENSORS_LIS3LV02D + tristate "STMicroeletronics LIS3LV02Dx three-axis digital accelerometer" + depends on ACPI && INPUT + default n + help + This driver provides support for the LIS3LV02Dx accelerometer. In + particular, it can be found in a number of HP laptops, which have the + "Mobile Data Protection System 3D" or "3D DriveGuard" feature. On such + systems the driver should load automatically (via ACPI). The + accelerometer might also be found in other systems, connected via SPI + or I2C. The accelerometer data is readable via + /sys/devices/platform/lis3lv02d. + + This driver also provides an absolute input class device, allowing + the laptop to act as a pinball machine-esque joystick. + + This driver can also be built as a module. If so, the module + will be called lis3lv02d. + config SENSORS_APPLESMC tristate "Apple SMC (Motion sensor, light sensor, keyboard backlight)" depends on INPUT && X86 diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 042d5a78622e..58fc5be5355d 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SENSORS_ADM1029) += adm1029.o obj-$(CONFIG_SENSORS_ADM1031) += adm1031.o obj-$(CONFIG_SENSORS_ADM9240) += adm9240.o obj-$(CONFIG_SENSORS_ADS7828) += ads7828.o +obj-$(CONFIG_SENSORS_ADT7462) += adt7462.o obj-$(CONFIG_SENSORS_ADT7470) += adt7470.o obj-$(CONFIG_SENSORS_ADT7473) += adt7473.o obj-$(CONFIG_SENSORS_APPLESMC) += applesmc.o @@ -48,6 +49,7 @@ obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o obj-$(CONFIG_SENSORS_IBMPEX) += ibmpex.o obj-$(CONFIG_SENSORS_IT87) += it87.o obj-$(CONFIG_SENSORS_K8TEMP) += k8temp.o +obj-$(CONFIG_SENSORS_LIS3LV02D) += lis3lv02d.o obj-$(CONFIG_SENSORS_LM63) += lm63.o obj-$(CONFIG_SENSORS_LM70) += lm70.o obj-$(CONFIG_SENSORS_LM75) += lm75.o diff --git a/drivers/hwmon/adt7462.c b/drivers/hwmon/adt7462.c new file mode 100644 index 000000000000..66107b4dc12a --- /dev/null +++ b/drivers/hwmon/adt7462.c @@ -0,0 +1,2002 @@ +/* + * A hwmon driver for the Analog Devices ADT7462 + * Copyright (C) 2008 IBM + * + * Author: Darrick J. Wong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { 0x58, 0x5C, I2C_CLIENT_END }; + +/* Insmod parameters */ +I2C_CLIENT_INSMOD_1(adt7462); + +/* ADT7462 registers */ +#define ADT7462_REG_DEVICE 0x3D +#define ADT7462_REG_VENDOR 0x3E +#define ADT7462_REG_REVISION 0x3F + +#define ADT7462_REG_MIN_TEMP_BASE_ADDR 0x44 +#define ADT7462_REG_MIN_TEMP_MAX_ADDR 0x47 +#define ADT7462_REG_MAX_TEMP_BASE_ADDR 0x48 +#define ADT7462_REG_MAX_TEMP_MAX_ADDR 0x4B +#define ADT7462_REG_TEMP_BASE_ADDR 0x88 +#define ADT7462_REG_TEMP_MAX_ADDR 0x8F + +#define ADT7462_REG_FAN_BASE_ADDR 0x98 +#define ADT7462_REG_FAN_MAX_ADDR 0x9F +#define ADT7462_REG_FAN2_BASE_ADDR 0xA2 +#define ADT7462_REG_FAN2_MAX_ADDR 0xA9 +#define ADT7462_REG_FAN_ENABLE 0x07 +#define ADT7462_REG_FAN_MIN_BASE_ADDR 0x78 +#define ADT7462_REG_FAN_MIN_MAX_ADDR 0x7F + +#define ADT7462_REG_CFG2 0x02 +#define ADT7462_FSPD_MASK 0x20 + +#define ADT7462_REG_PWM_BASE_ADDR 0xAA +#define ADT7462_REG_PWM_MAX_ADDR 0xAD +#define ADT7462_REG_PWM_MIN_BASE_ADDR 0x28 +#define ADT7462_REG_PWM_MIN_MAX_ADDR 0x2B +#define ADT7462_REG_PWM_MAX 0x2C +#define ADT7462_REG_PWM_TEMP_MIN_BASE_ADDR 0x5C +#define ADT7462_REG_PWM_TEMP_MIN_MAX_ADDR 0x5F +#define ADT7462_REG_PWM_TEMP_RANGE_BASE_ADDR 0x60 +#define ADT7462_REG_PWM_TEMP_RANGE_MAX_ADDR 0x63 +#define ADT7462_PWM_HYST_MASK 0x0F +#define ADT7462_PWM_RANGE_MASK 0xF0 +#define ADT7462_PWM_RANGE_SHIFT 4 +#define ADT7462_REG_PWM_CFG_BASE_ADDR 0x21 +#define ADT7462_REG_PWM_CFG_MAX_ADDR 0x24 +#define ADT7462_PWM_CHANNEL_MASK 0xE0 +#define ADT7462_PWM_CHANNEL_SHIFT 5 + +#define ADT7462_REG_PIN_CFG_BASE_ADDR 0x10 +#define ADT7462_REG_PIN_CFG_MAX_ADDR 0x13 +#define ADT7462_PIN7_INPUT 0x01 /* cfg0 */ +#define ADT7462_DIODE3_INPUT 0x20 +#define ADT7462_DIODE1_INPUT 0x40 +#define ADT7462_VID_INPUT 0x80 +#define ADT7462_PIN22_INPUT 0x04 /* cfg1 */ +#define ADT7462_PIN21_INPUT 0x08 +#define ADT7462_PIN19_INPUT 0x10 +#define ADT7462_PIN15_INPUT 0x20 +#define ADT7462_PIN13_INPUT 0x40 +#define ADT7462_PIN8_INPUT 0x80 +#define ADT7462_PIN23_MASK 0x03 +#define ADT7462_PIN23_SHIFT 0 +#define ADT7462_PIN26_MASK 0x0C /* cfg2 */ +#define ADT7462_PIN26_SHIFT 2 +#define ADT7462_PIN25_MASK 0x30 +#define ADT7462_PIN25_SHIFT 4 +#define ADT7462_PIN24_MASK 0xC0 +#define ADT7462_PIN24_SHIFT 6 +#define ADT7462_PIN26_VOLT_INPUT 0x08 +#define ADT7462_PIN25_VOLT_INPUT 0x20 +#define ADT7462_PIN28_SHIFT 6 /* cfg3 */ +#define ADT7462_PIN28_VOLT 0x5 + +#define ADT7462_REG_ALARM1 0xB8 +#define ADT7462_LT_ALARM 0x02 +#define ADT7462_R1T_ALARM 0x04 +#define ADT7462_R2T_ALARM 0x08 +#define ADT7462_R3T_ALARM 0x10 +#define ADT7462_REG_ALARM2 0xBB +#define ADT7462_V0_ALARM 0x01 +#define ADT7462_V1_ALARM 0x02 +#define ADT7462_V2_ALARM 0x04 +#define ADT7462_V3_ALARM 0x08 +#define ADT7462_V4_ALARM 0x10 +#define ADT7462_V5_ALARM 0x20 +#define ADT7462_V6_ALARM 0x40 +#define ADT7462_V7_ALARM 0x80 +#define ADT7462_REG_ALARM3 0xBC +#define ADT7462_V8_ALARM 0x08 +#define ADT7462_V9_ALARM 0x10 +#define ADT7462_V10_ALARM 0x20 +#define ADT7462_V11_ALARM 0x40 +#define ADT7462_V12_ALARM 0x80 +#define ADT7462_REG_ALARM4 0xBD +#define ADT7462_F0_ALARM 0x01 +#define ADT7462_F1_ALARM 0x02 +#define ADT7462_F2_ALARM 0x04 +#define ADT7462_F3_ALARM 0x08 +#define ADT7462_F4_ALARM 0x10 +#define ADT7462_F5_ALARM 0x20 +#define ADT7462_F6_ALARM 0x40 +#define ADT7462_F7_ALARM 0x80 +#define ADT7462_ALARM1 0x0000 +#define ADT7462_ALARM2 0x0100 +#define ADT7462_ALARM3 0x0200 +#define ADT7462_ALARM4 0x0300 +#define ADT7462_ALARM_REG_SHIFT 8 +#define ADT7462_ALARM_FLAG_MASK 0x0F + +#define ADT7462_TEMP_COUNT 4 +#define ADT7462_TEMP_REG(x) (ADT7462_REG_TEMP_BASE_ADDR + (x * 2)) +#define ADT7462_TEMP_MIN_REG(x) (ADT7462_REG_MIN_TEMP_BASE_ADDR + (x)) +#define ADT7462_TEMP_MAX_REG(x) (ADT7462_REG_MAX_TEMP_BASE_ADDR + (x)) +#define TEMP_FRAC_OFFSET 6 + +#define ADT7462_FAN_COUNT 8 +#define ADT7462_REG_FAN_MIN(x) (ADT7462_REG_FAN_MIN_BASE_ADDR + (x)) + +#define ADT7462_PWM_COUNT 4 +#define ADT7462_REG_PWM(x) (ADT7462_REG_PWM_BASE_ADDR + (x)) +#define ADT7462_REG_PWM_MIN(x) (ADT7462_REG_PWM_MIN_BASE_ADDR + (x)) +#define ADT7462_REG_PWM_TMIN(x) \ + (ADT7462_REG_PWM_TEMP_MIN_BASE_ADDR + (x)) +#define ADT7462_REG_PWM_TRANGE(x) \ + (ADT7462_REG_PWM_TEMP_RANGE_BASE_ADDR + (x)) + +#define ADT7462_PIN_CFG_REG_COUNT 4 +#define ADT7462_REG_PIN_CFG(x) (ADT7462_REG_PIN_CFG_BASE_ADDR + (x)) +#define ADT7462_REG_PWM_CFG(x) (ADT7462_REG_PWM_CFG_BASE_ADDR + (x)) + +#define ADT7462_ALARM_REG_COUNT 4 + +/* + * The chip can measure 13 different voltage sources: + * + * 1. +12V1 (pin 7) + * 2. Vccp1/+2.5V/+1.8V/+1.5V (pin 23) + * 3. +12V3 (pin 22) + * 4. +5V (pin 21) + * 5. +1.25V/+0.9V (pin 19) + * 6. +2.5V/+1.8V (pin 15) + * 7. +3.3v (pin 13) + * 8. +12V2 (pin 8) + * 9. Vbatt/FSB_Vtt (pin 26) + * A. +3.3V/+1.2V1 (pin 25) + * B. Vccp2/+2.5V/+1.8V/+1.5V (pin 24) + * C. +1.5V ICH (only if BOTH pin 28/29 are set to +1.5V) + * D. +1.5V 3GPIO (only if BOTH pin 28/29 are set to +1.5V) + * + * Each of these 13 has a factor to convert raw to voltage. Even better, + * the pins can be connected to other sensors (tach/gpio/hot/etc), which + * makes the bookkeeping tricky. + * + * Some, but not all, of these voltages have low/high limits. + */ +#define ADT7462_VOLT_COUNT 12 + +#define ADT7462_VENDOR 0x41 +#define ADT7462_DEVICE 0x62 +/* datasheet only mentions a revision 4 */ +#define ADT7462_REVISION 0x04 + +/* How often do we reread sensors values? (In jiffies) */ +#define SENSOR_REFRESH_INTERVAL (2 * HZ) + +/* How often do we reread sensor limit values? (In jiffies) */ +#define LIMIT_REFRESH_INTERVAL (60 * HZ) + +/* datasheet says to divide this number by the fan reading to get fan rpm */ +#define FAN_PERIOD_TO_RPM(x) ((90000 * 60) / (x)) +#define FAN_RPM_TO_PERIOD FAN_PERIOD_TO_RPM +#define FAN_PERIOD_INVALID 65535 +#define FAN_DATA_VALID(x) ((x) && (x) != FAN_PERIOD_INVALID) + +#define MASK_AND_SHIFT(value, prefix) \ + (((value) & prefix##_MASK) >> prefix##_SHIFT) + +#define ROUND_DIV(x, divisor) (((x) + ((divisor) / 2)) / (divisor)) + +struct adt7462_data { + struct device *hwmon_dev; + struct attribute_group attrs; + struct mutex lock; + char sensors_valid; + char limits_valid; + unsigned long sensors_last_updated; /* In jiffies */ + unsigned long limits_last_updated; /* In jiffies */ + + u8 temp[ADT7462_TEMP_COUNT]; + /* bits 6-7 are quarter pieces of temp */ + u8 temp_frac[ADT7462_TEMP_COUNT]; + u8 temp_min[ADT7462_TEMP_COUNT]; + u8 temp_max[ADT7462_TEMP_COUNT]; + u16 fan[ADT7462_FAN_COUNT]; + u8 fan_enabled; + u8 fan_min[ADT7462_FAN_COUNT]; + u8 cfg2; + u8 pwm[ADT7462_PWM_COUNT]; + u8 pin_cfg[ADT7462_PIN_CFG_REG_COUNT]; + u8 voltages[ADT7462_VOLT_COUNT]; + u8 volt_max[ADT7462_VOLT_COUNT]; + u8 volt_min[ADT7462_VOLT_COUNT]; + u8 pwm_min[ADT7462_PWM_COUNT]; + u8 pwm_tmin[ADT7462_PWM_COUNT]; + u8 pwm_trange[ADT7462_PWM_COUNT]; + u8 pwm_max; /* only one per chip */ + u8 pwm_cfg[ADT7462_PWM_COUNT]; + u8 alarms[ADT7462_ALARM_REG_COUNT]; +}; + +static int adt7462_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int adt7462_detect(struct i2c_client *client, int kind, + struct i2c_board_info *info); +static int adt7462_remove(struct i2c_client *client); + +static const struct i2c_device_id adt7462_id[] = { + { "adt7462", adt7462 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, adt7462_id); + +static struct i2c_driver adt7462_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "adt7462", + }, + .probe = adt7462_probe, + .remove = adt7462_remove, + .id_table = adt7462_id, + .detect = adt7462_detect, + .address_data = &addr_data, +}; + +/* + * 16-bit registers on the ADT7462 are low-byte first. The data sheet says + * that the low byte must be read before the high byte. + */ +static inline int adt7462_read_word_data(struct i2c_client *client, u8 reg) +{ + u16 foo; + foo = i2c_smbus_read_byte_data(client, reg); + foo |= ((u16)i2c_smbus_read_byte_data(client, reg + 1) << 8); + return foo; +} + +/* For some reason these registers are not contiguous. */ +static int ADT7462_REG_FAN(int fan) +{ + if (fan < 4) + return ADT7462_REG_FAN_BASE_ADDR + (2 * fan); + return ADT7462_REG_FAN2_BASE_ADDR + (2 * (fan - 4)); +} + +/* Voltage registers are scattered everywhere */ +static int ADT7462_REG_VOLT_MAX(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT)) + return 0x7C; + break; + case 1: + return 0x69; + case 2: + if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT)) + return 0x7F; + break; + case 3: + if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT)) + return 0x7E; + break; + case 4: + if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) + return 0x4B; + break; + case 5: + if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) + return 0x49; + break; + case 6: + if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT)) + return 0x68; + break; + case 7: + if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT)) + return 0x7D; + break; + case 8: + if (!(data->pin_cfg[2] & ADT7462_PIN26_VOLT_INPUT)) + return 0x6C; + break; + case 9: + if (!(data->pin_cfg[2] & ADT7462_PIN25_VOLT_INPUT)) + return 0x6B; + break; + case 10: + return 0x6A; + case 11: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 0x50; + break; + case 12: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 0x4C; + break; + } + return -ENODEV; +} + +static int ADT7462_REG_VOLT_MIN(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT)) + return 0x6D; + break; + case 1: + return 0x72; + case 2: + if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT)) + return 0x6F; + break; + case 3: + if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT)) + return 0x71; + break; + case 4: + if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) + return 0x47; + break; + case 5: + if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) + return 0x45; + break; + case 6: + if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT)) + return 0x70; + break; + case 7: + if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT)) + return 0x6E; + break; + case 8: + if (!(data->pin_cfg[2] & ADT7462_PIN26_VOLT_INPUT)) + return 0x75; + break; + case 9: + if (!(data->pin_cfg[2] & ADT7462_PIN25_VOLT_INPUT)) + return 0x74; + break; + case 10: + return 0x73; + case 11: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 0x76; + break; + case 12: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 0x77; + break; + } + return -ENODEV; +} + +static int ADT7462_REG_VOLT(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT)) + return 0xA3; + break; + case 1: + return 0x90; + case 2: + if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT)) + return 0xA9; + break; + case 3: + if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT)) + return 0xA7; + break; + case 4: + if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) + return 0x8F; + break; + case 5: + if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) + return 0x8B; + break; + case 6: + if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT)) + return 0x96; + break; + case 7: + if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT)) + return 0xA5; + break; + case 8: + if (!(data->pin_cfg[2] & ADT7462_PIN26_VOLT_INPUT)) + return 0x93; + break; + case 9: + if (!(data->pin_cfg[2] & ADT7462_PIN25_VOLT_INPUT)) + return 0x92; + break; + case 10: + return 0x91; + case 11: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 0x94; + break; + case 12: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 0x95; + break; + } + return -ENODEV; +} + +/* Provide labels for sysfs */ +static const char *voltage_label(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT)) + return "+12V1"; + break; + case 1: + switch (MASK_AND_SHIFT(data->pin_cfg[1], ADT7462_PIN23)) { + case 0: + return "Vccp1"; + case 1: + return "+2.5V"; + case 2: + return "+1.8V"; + case 3: + return "+1.5V"; + } + case 2: + if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT)) + return "+12V3"; + break; + case 3: + if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT)) + return "+5V"; + break; + case 4: + if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) { + if (data->pin_cfg[1] & ADT7462_PIN19_INPUT) + return "+0.9V"; + return "+1.25V"; + } + break; + case 5: + if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) { + if (data->pin_cfg[1] & ADT7462_PIN19_INPUT) + return "+1.8V"; + return "+2.5V"; + } + break; + case 6: + if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT)) + return "+3.3V"; + break; + case 7: + if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT)) + return "+12V2"; + break; + case 8: + switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN26)) { + case 0: + return "Vbatt"; + case 1: + return "FSB_Vtt"; + } + break; + case 9: + switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN25)) { + case 0: + return "+3.3V"; + case 1: + return "+1.2V1"; + } + break; + case 10: + switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN24)) { + case 0: + return "Vccp2"; + case 1: + return "+2.5V"; + case 2: + return "+1.8V"; + case 3: + return "+1.5"; + } + case 11: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return "+1.5V ICH"; + break; + case 12: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return "+1.5V 3GPIO"; + break; + } + return "N/A"; +} + +/* Multipliers are actually in uV, not mV. */ +static int voltage_multiplier(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT)) + return 62500; + break; + case 1: + switch (MASK_AND_SHIFT(data->pin_cfg[1], ADT7462_PIN23)) { + case 0: + if (data->pin_cfg[0] & ADT7462_VID_INPUT) + return 12500; + return 6250; + case 1: + return 13000; + case 2: + return 9400; + case 3: + return 7800; + } + case 2: + if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT)) + return 62500; + break; + case 3: + if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT)) + return 26000; + break; + case 4: + if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) { + if (data->pin_cfg[1] & ADT7462_PIN19_INPUT) + return 4690; + return 6500; + } + break; + case 5: + if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) { + if (data->pin_cfg[1] & ADT7462_PIN15_INPUT) + return 9400; + return 13000; + } + break; + case 6: + if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT)) + return 17200; + break; + case 7: + if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT)) + return 62500; + break; + case 8: + switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN26)) { + case 0: + return 15600; + case 1: + return 6250; + } + break; + case 9: + switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN25)) { + case 0: + return 17200; + case 1: + return 6250; + } + break; + case 10: + switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN24)) { + case 0: + return 6250; + case 1: + return 13000; + case 2: + return 9400; + case 3: + return 7800; + } + case 11: + case 12: + if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT == + ADT7462_PIN28_VOLT && + !(data->pin_cfg[0] & ADT7462_VID_INPUT)) + return 7800; + } + return 0; +} + +static int temp_enabled(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + case 2: + return 1; + case 1: + if (data->pin_cfg[0] & ADT7462_DIODE1_INPUT) + return 1; + break; + case 3: + if (data->pin_cfg[0] & ADT7462_DIODE3_INPUT) + return 1; + break; + } + return 0; +} + +static const char *temp_label(struct adt7462_data *data, int which) +{ + switch (which) { + case 0: + return "local"; + case 1: + if (data->pin_cfg[0] & ADT7462_DIODE1_INPUT) + return "remote1"; + break; + case 2: + return "remote2"; + case 3: + if (data->pin_cfg[0] & ADT7462_DIODE3_INPUT) + return "remote3"; + break; + } + return "N/A"; +} + +/* Map Trange register values to mC */ +#define NUM_TRANGE_VALUES 16 +static const int trange_values[NUM_TRANGE_VALUES] = { + 2000, + 2500, + 3300, + 4000, + 5000, + 6700, + 8000, + 10000, + 13300, + 16000, + 20000, + 26700, + 32000, + 40000, + 53300, + 80000 +}; + +static int find_trange_value(int trange) +{ + int i; + + for (i = 0; i < NUM_TRANGE_VALUES; i++) + if (trange_values[i] == trange) + return i; + + return -ENODEV; +} + +static struct adt7462_data *adt7462_update_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + unsigned long local_jiffies = jiffies; + int i; + + mutex_lock(&data->lock); + if (time_before(local_jiffies, data->sensors_last_updated + + SENSOR_REFRESH_INTERVAL) + && data->sensors_valid) + goto no_sensor_update; + + for (i = 0; i < ADT7462_TEMP_COUNT; i++) { + /* + * Reading the fractional register locks the integral + * register until both have been read. + */ + data->temp_frac[i] = i2c_smbus_read_byte_data(client, + ADT7462_TEMP_REG(i)); + data->temp[i] = i2c_smbus_read_byte_data(client, + ADT7462_TEMP_REG(i) + 1); + } + + for (i = 0; i < ADT7462_FAN_COUNT; i++) + data->fan[i] = adt7462_read_word_data(client, + ADT7462_REG_FAN(i)); + + data->fan_enabled = i2c_smbus_read_byte_data(client, + ADT7462_REG_FAN_ENABLE); + + for (i = 0; i < ADT7462_PWM_COUNT; i++) + data->pwm[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_PWM(i)); + + for (i = 0; i < ADT7462_PIN_CFG_REG_COUNT; i++) + data->pin_cfg[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_PIN_CFG(i)); + + for (i = 0; i < ADT7462_VOLT_COUNT; i++) { + int reg = ADT7462_REG_VOLT(data, i); + if (!reg) + data->voltages[i] = 0; + else + data->voltages[i] = i2c_smbus_read_byte_data(client, + reg); + } + + data->alarms[0] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM1); + data->alarms[1] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM2); + data->alarms[2] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM3); + data->alarms[3] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM4); + + data->sensors_last_updated = local_jiffies; + data->sensors_valid = 1; + +no_sensor_update: + if (time_before(local_jiffies, data->limits_last_updated + + LIMIT_REFRESH_INTERVAL) + && data->limits_valid) + goto out; + + for (i = 0; i < ADT7462_TEMP_COUNT; i++) { + data->temp_min[i] = i2c_smbus_read_byte_data(client, + ADT7462_TEMP_MIN_REG(i)); + data->temp_max[i] = i2c_smbus_read_byte_data(client, + ADT7462_TEMP_MAX_REG(i)); + } + + for (i = 0; i < ADT7462_FAN_COUNT; i++) + data->fan_min[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_FAN_MIN(i)); + + for (i = 0; i < ADT7462_VOLT_COUNT; i++) { + int reg = ADT7462_REG_VOLT_MAX(data, i); + data->volt_max[i] = + (reg ? i2c_smbus_read_byte_data(client, reg) : 0); + + reg = ADT7462_REG_VOLT_MIN(data, i); + data->volt_min[i] = + (reg ? i2c_smbus_read_byte_data(client, reg) : 0); + } + + for (i = 0; i < ADT7462_PWM_COUNT; i++) { + data->pwm_min[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_PWM_MIN(i)); + data->pwm_tmin[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_PWM_TMIN(i)); + data->pwm_trange[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_PWM_TRANGE(i)); + data->pwm_cfg[i] = i2c_smbus_read_byte_data(client, + ADT7462_REG_PWM_CFG(i)); + } + + data->pwm_max = i2c_smbus_read_byte_data(client, ADT7462_REG_PWM_MAX); + + data->cfg2 = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2); + + data->limits_last_updated = local_jiffies; + data->limits_valid = 1; + +out: + mutex_unlock(&data->lock); + return data; +} + +static ssize_t show_temp_min(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + + if (!temp_enabled(data, attr->index)) + return sprintf(buf, "0\n"); + + return sprintf(buf, "%d\n", 1000 * (data->temp_min[attr->index] - 64)); +} + +static ssize_t set_temp_min(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp) || !temp_enabled(data, attr->index)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000) + 64; + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->temp_min[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_TEMP_MIN_REG(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_temp_max(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + + if (!temp_enabled(data, attr->index)) + return sprintf(buf, "0\n"); + + return sprintf(buf, "%d\n", 1000 * (data->temp_max[attr->index] - 64)); +} + +static ssize_t set_temp_max(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp) || !temp_enabled(data, attr->index)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000) + 64; + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->temp_max[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_TEMP_MAX_REG(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + u8 frac = data->temp_frac[attr->index] >> TEMP_FRAC_OFFSET; + + if (!temp_enabled(data, attr->index)) + return sprintf(buf, "0\n"); + + return sprintf(buf, "%d\n", 1000 * (data->temp[attr->index] - 64) + + 250 * frac); +} + +static ssize_t show_temp_label(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + + return sprintf(buf, "%s\n", temp_label(data, attr->index)); +} + +static ssize_t show_volt_max(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + int x = voltage_multiplier(data, attr->index); + + x *= data->volt_max[attr->index]; + x /= 1000; /* convert from uV to mV */ + + return sprintf(buf, "%d\n", x); +} + +static ssize_t set_volt_max(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + int x = voltage_multiplier(data, attr->index); + long temp; + + if (strict_strtol(buf, 10, &temp) || !x) + return -EINVAL; + + temp *= 1000; /* convert mV to uV */ + temp = ROUND_DIV(temp, x); + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->volt_max[attr->index] = temp; + i2c_smbus_write_byte_data(client, + ADT7462_REG_VOLT_MAX(data, attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_volt_min(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + int x = voltage_multiplier(data, attr->index); + + x *= data->volt_min[attr->index]; + x /= 1000; /* convert from uV to mV */ + + return sprintf(buf, "%d\n", x); +} + +static ssize_t set_volt_min(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + int x = voltage_multiplier(data, attr->index); + long temp; + + if (strict_strtol(buf, 10, &temp) || !x) + return -EINVAL; + + temp *= 1000; /* convert mV to uV */ + temp = ROUND_DIV(temp, x); + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->volt_min[attr->index] = temp; + i2c_smbus_write_byte_data(client, + ADT7462_REG_VOLT_MIN(data, attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_voltage(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + int x = voltage_multiplier(data, attr->index); + + x *= data->voltages[attr->index]; + x /= 1000; /* convert from uV to mV */ + + return sprintf(buf, "%d\n", x); +} + +static ssize_t show_voltage_label(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + + return sprintf(buf, "%s\n", voltage_label(data, attr->index)); +} + +static ssize_t show_alarm(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + int reg = attr->index >> ADT7462_ALARM_REG_SHIFT; + int mask = attr->index & ADT7462_ALARM_FLAG_MASK; + + if (data->alarms[reg] & mask) + return sprintf(buf, "1\n"); + else + return sprintf(buf, "0\n"); +} + +static int fan_enabled(struct adt7462_data *data, int fan) +{ + return data->fan_enabled & (1 << fan); +} + +static ssize_t show_fan_min(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + u16 temp; + + /* Only the MSB of the min fan period is stored... */ + temp = data->fan_min[attr->index]; + temp <<= 8; + + if (!fan_enabled(data, attr->index) || + !FAN_DATA_VALID(temp)) + return sprintf(buf, "0\n"); + + return sprintf(buf, "%d\n", FAN_PERIOD_TO_RPM(temp)); +} + +static ssize_t set_fan_min(struct device *dev, + struct device_attribute *devattr, + const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp) || !temp || + !fan_enabled(data, attr->index)) + return -EINVAL; + + temp = FAN_RPM_TO_PERIOD(temp); + temp >>= 8; + temp = SENSORS_LIMIT(temp, 1, 255); + + mutex_lock(&data->lock); + data->fan_min[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_FAN_MIN(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_fan(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + + if (!fan_enabled(data, attr->index) || + !FAN_DATA_VALID(data->fan[attr->index])) + return sprintf(buf, "0\n"); + + return sprintf(buf, "%d\n", + FAN_PERIOD_TO_RPM(data->fan[attr->index])); +} + +static ssize_t show_force_pwm_max(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct adt7462_data *data = adt7462_update_device(dev); + return sprintf(buf, "%d\n", (data->cfg2 & ADT7462_FSPD_MASK ? 1 : 0)); +} + +static ssize_t set_force_pwm_max(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + u8 reg; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + mutex_lock(&data->lock); + reg = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2); + if (temp) + reg |= ADT7462_FSPD_MASK; + else + reg &= ~ADT7462_FSPD_MASK; + data->cfg2 = reg; + i2c_smbus_write_byte_data(client, ADT7462_REG_CFG2, reg); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + return sprintf(buf, "%d\n", data->pwm[attr->index]); +} + +static ssize_t set_pwm(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->pwm[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM(attr->index), temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm_max(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct adt7462_data *data = adt7462_update_device(dev); + return sprintf(buf, "%d\n", data->pwm_max); +} + +static ssize_t set_pwm_max(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->pwm_max = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_MAX, temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm_min(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + return sprintf(buf, "%d\n", data->pwm_min[attr->index]); +} + +static ssize_t set_pwm_min(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->pwm_min[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_MIN(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm_hyst(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + return sprintf(buf, "%d\n", 1000 * + (data->pwm_trange[attr->index] & ADT7462_PWM_HYST_MASK)); +} + +static ssize_t set_pwm_hyst(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); + temp = SENSORS_LIMIT(temp, 0, 15); + + /* package things up */ + temp &= ADT7462_PWM_HYST_MASK; + temp |= data->pwm_trange[attr->index] & ADT7462_PWM_RANGE_MASK; + + mutex_lock(&data->lock); + data->pwm_trange[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_TRANGE(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm_tmax(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + + /* tmax = tmin + trange */ + int trange = trange_values[data->pwm_trange[attr->index] >> + ADT7462_PWM_RANGE_SHIFT]; + int tmin = (data->pwm_tmin[attr->index] - 64) * 1000; + + return sprintf(buf, "%d\n", tmin + trange); +} + +static ssize_t set_pwm_tmax(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + int temp; + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + int tmin, trange_value; + long trange; + + if (strict_strtol(buf, 10, &trange)) + return -EINVAL; + + /* trange = tmax - tmin */ + tmin = (data->pwm_tmin[attr->index] - 64) * 1000; + trange_value = find_trange_value(trange - tmin); + + if (trange_value < 0) + return -EINVAL; + + temp = trange_value << ADT7462_PWM_RANGE_SHIFT; + temp |= data->pwm_trange[attr->index] & ADT7462_PWM_HYST_MASK; + + mutex_lock(&data->lock); + data->pwm_trange[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_TRANGE(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm_tmin(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + return sprintf(buf, "%d\n", 1000 * (data->pwm_tmin[attr->index] - 64)); +} + +static ssize_t set_pwm_tmin(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000) + 64; + temp = SENSORS_LIMIT(temp, 0, 255); + + mutex_lock(&data->lock); + data->pwm_tmin[attr->index] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_TMIN(attr->index), + temp); + mutex_unlock(&data->lock); + + return count; +} + +static ssize_t show_pwm_auto(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + int cfg = data->pwm_cfg[attr->index] >> ADT7462_PWM_CHANNEL_SHIFT; + + switch (cfg) { + case 4: /* off */ + return sprintf(buf, "0\n"); + case 7: /* manual */ + return sprintf(buf, "1\n"); + default: /* automatic */ + return sprintf(buf, "2\n"); + } +} + +static void set_pwm_channel(struct i2c_client *client, + struct adt7462_data *data, + int which, + int value) +{ + int temp = data->pwm_cfg[which] & ~ADT7462_PWM_CHANNEL_MASK; + temp |= value << ADT7462_PWM_CHANNEL_SHIFT; + + mutex_lock(&data->lock); + data->pwm_cfg[which] = temp; + i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_CFG(which), temp); + mutex_unlock(&data->lock); +} + +static ssize_t set_pwm_auto(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + switch (temp) { + case 0: /* off */ + set_pwm_channel(client, data, attr->index, 4); + return count; + case 1: /* manual */ + set_pwm_channel(client, data, attr->index, 7); + return count; + default: + return -EINVAL; + } +} + +static ssize_t show_pwm_auto_temp(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct adt7462_data *data = adt7462_update_device(dev); + int channel = data->pwm_cfg[attr->index] >> ADT7462_PWM_CHANNEL_SHIFT; + + switch (channel) { + case 0: /* temp[1234] only */ + case 1: + case 2: + case 3: + return sprintf(buf, "%d\n", (1 << channel)); + case 5: /* temp1 & temp4 */ + return sprintf(buf, "9\n"); + case 6: + return sprintf(buf, "15\n"); + default: + return sprintf(buf, "0\n"); + } +} + +static int cvt_auto_temp(int input) +{ + if (input == 0xF) + return 6; + if (input == 0x9) + return 5; + if (input < 1 || !is_power_of_2(input)) + return -EINVAL; + return ilog2(input); +} + +static ssize_t set_pwm_auto_temp(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7462_data *data = i2c_get_clientdata(client); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = cvt_auto_temp(temp); + if (temp < 0) + return temp; + + set_pwm_channel(client, data, attr->index, temp); + + return count; +} + +static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO, show_temp_max, + set_temp_max, 0); +static SENSOR_DEVICE_ATTR(temp2_max, S_IWUSR | S_IRUGO, show_temp_max, + set_temp_max, 1); +static SENSOR_DEVICE_ATTR(temp3_max, S_IWUSR | S_IRUGO, show_temp_max, + set_temp_max, 2); +static SENSOR_DEVICE_ATTR(temp4_max, S_IWUSR | S_IRUGO, show_temp_max, + set_temp_max, 3); + +static SENSOR_DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO, show_temp_min, + set_temp_min, 0); +static SENSOR_DEVICE_ATTR(temp2_min, S_IWUSR | S_IRUGO, show_temp_min, + set_temp_min, 1); +static SENSOR_DEVICE_ATTR(temp3_min, S_IWUSR | S_IRUGO, show_temp_min, + set_temp_min, 2); +static SENSOR_DEVICE_ATTR(temp4_min, S_IWUSR | S_IRUGO, show_temp_min, + set_temp_min, 3); + +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0); +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1); +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2); +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3); + +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0); +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1); +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2); +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3); + +static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM1 | ADT7462_LT_ALARM); +static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM1 | ADT7462_R1T_ALARM); +static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM1 | ADT7462_R2T_ALARM); +static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM1 | ADT7462_R3T_ALARM); + +static SENSOR_DEVICE_ATTR(in1_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 0); +static SENSOR_DEVICE_ATTR(in2_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 1); +static SENSOR_DEVICE_ATTR(in3_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 2); +static SENSOR_DEVICE_ATTR(in4_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 3); +static SENSOR_DEVICE_ATTR(in5_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 4); +static SENSOR_DEVICE_ATTR(in6_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 5); +static SENSOR_DEVICE_ATTR(in7_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 6); +static SENSOR_DEVICE_ATTR(in8_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 7); +static SENSOR_DEVICE_ATTR(in9_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 8); +static SENSOR_DEVICE_ATTR(in10_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 9); +static SENSOR_DEVICE_ATTR(in11_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 10); +static SENSOR_DEVICE_ATTR(in12_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 11); +static SENSOR_DEVICE_ATTR(in13_max, S_IWUSR | S_IRUGO, show_volt_max, + set_volt_max, 12); + +static SENSOR_DEVICE_ATTR(in1_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 0); +static SENSOR_DEVICE_ATTR(in2_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 1); +static SENSOR_DEVICE_ATTR(in3_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 2); +static SENSOR_DEVICE_ATTR(in4_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 3); +static SENSOR_DEVICE_ATTR(in5_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 4); +static SENSOR_DEVICE_ATTR(in6_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 5); +static SENSOR_DEVICE_ATTR(in7_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 6); +static SENSOR_DEVICE_ATTR(in8_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 7); +static SENSOR_DEVICE_ATTR(in9_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 8); +static SENSOR_DEVICE_ATTR(in10_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 9); +static SENSOR_DEVICE_ATTR(in11_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 10); +static SENSOR_DEVICE_ATTR(in12_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 11); +static SENSOR_DEVICE_ATTR(in13_min, S_IWUSR | S_IRUGO, show_volt_min, + set_volt_min, 12); + +static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_voltage, NULL, 0); +static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_voltage, NULL, 1); +static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_voltage, NULL, 2); +static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, show_voltage, NULL, 3); +static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, show_voltage, NULL, 4); +static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, show_voltage, NULL, 5); +static SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, show_voltage, NULL, 6); +static SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, show_voltage, NULL, 7); +static SENSOR_DEVICE_ATTR(in9_input, S_IRUGO, show_voltage, NULL, 8); +static SENSOR_DEVICE_ATTR(in10_input, S_IRUGO, show_voltage, NULL, 9); +static SENSOR_DEVICE_ATTR(in11_input, S_IRUGO, show_voltage, NULL, 10); +static SENSOR_DEVICE_ATTR(in12_input, S_IRUGO, show_voltage, NULL, 11); +static SENSOR_DEVICE_ATTR(in13_input, S_IRUGO, show_voltage, NULL, 12); + +static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, show_voltage_label, NULL, 0); +static SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, show_voltage_label, NULL, 1); +static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_voltage_label, NULL, 2); +static SENSOR_DEVICE_ATTR(in4_label, S_IRUGO, show_voltage_label, NULL, 3); +static SENSOR_DEVICE_ATTR(in5_label, S_IRUGO, show_voltage_label, NULL, 4); +static SENSOR_DEVICE_ATTR(in6_label, S_IRUGO, show_voltage_label, NULL, 5); +static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_voltage_label, NULL, 6); +static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_voltage_label, NULL, 7); +static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_voltage_label, NULL, 8); +static SENSOR_DEVICE_ATTR(in10_label, S_IRUGO, show_voltage_label, NULL, 9); +static SENSOR_DEVICE_ATTR(in11_label, S_IRUGO, show_voltage_label, NULL, 10); +static SENSOR_DEVICE_ATTR(in12_label, S_IRUGO, show_voltage_label, NULL, 11); +static SENSOR_DEVICE_ATTR(in13_label, S_IRUGO, show_voltage_label, NULL, 12); + +static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V0_ALARM); +static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V7_ALARM); +static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V2_ALARM); +static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V6_ALARM); +static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V5_ALARM); +static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V4_ALARM); +static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V3_ALARM); +static SENSOR_DEVICE_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM2 | ADT7462_V1_ALARM); +static SENSOR_DEVICE_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM3 | ADT7462_V10_ALARM); +static SENSOR_DEVICE_ATTR(in10_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM3 | ADT7462_V9_ALARM); +static SENSOR_DEVICE_ATTR(in11_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM3 | ADT7462_V8_ALARM); +static SENSOR_DEVICE_ATTR(in12_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM3 | ADT7462_V11_ALARM); +static SENSOR_DEVICE_ATTR(in13_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM3 | ADT7462_V12_ALARM); + +static SENSOR_DEVICE_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 0); +static SENSOR_DEVICE_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 1); +static SENSOR_DEVICE_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 2); +static SENSOR_DEVICE_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 3); +static SENSOR_DEVICE_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 4); +static SENSOR_DEVICE_ATTR(fan6_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 5); +static SENSOR_DEVICE_ATTR(fan7_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 6); +static SENSOR_DEVICE_ATTR(fan8_min, S_IWUSR | S_IRUGO, show_fan_min, + set_fan_min, 7); + +static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0); +static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1); +static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2); +static SENSOR_DEVICE_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3); +static SENSOR_DEVICE_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4); +static SENSOR_DEVICE_ATTR(fan6_input, S_IRUGO, show_fan, NULL, 5); +static SENSOR_DEVICE_ATTR(fan7_input, S_IRUGO, show_fan, NULL, 6); +static SENSOR_DEVICE_ATTR(fan8_input, S_IRUGO, show_fan, NULL, 7); + +static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F0_ALARM); +static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F1_ALARM); +static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F2_ALARM); +static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F3_ALARM); +static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F4_ALARM); +static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F5_ALARM); +static SENSOR_DEVICE_ATTR(fan7_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F6_ALARM); +static SENSOR_DEVICE_ATTR(fan8_alarm, S_IRUGO, show_alarm, NULL, + ADT7462_ALARM4 | ADT7462_F7_ALARM); + +static SENSOR_DEVICE_ATTR(force_pwm_max, S_IWUSR | S_IRUGO, + show_force_pwm_max, set_force_pwm_max, 0); + +static SENSOR_DEVICE_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 0); +static SENSOR_DEVICE_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 1); +static SENSOR_DEVICE_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 2); +static SENSOR_DEVICE_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 3); + +static SENSOR_DEVICE_ATTR(pwm1_auto_point1_pwm, S_IWUSR | S_IRUGO, + show_pwm_min, set_pwm_min, 0); +static SENSOR_DEVICE_ATTR(pwm2_auto_point1_pwm, S_IWUSR | S_IRUGO, + show_pwm_min, set_pwm_min, 1); +static SENSOR_DEVICE_ATTR(pwm3_auto_point1_pwm, S_IWUSR | S_IRUGO, + show_pwm_min, set_pwm_min, 2); +static SENSOR_DEVICE_ATTR(pwm4_auto_point1_pwm, S_IWUSR | S_IRUGO, + show_pwm_min, set_pwm_min, 3); + +static SENSOR_DEVICE_ATTR(pwm1_auto_point2_pwm, S_IWUSR | S_IRUGO, + show_pwm_max, set_pwm_max, 0); +static SENSOR_DEVICE_ATTR(pwm2_auto_point2_pwm, S_IWUSR | S_IRUGO, + show_pwm_max, set_pwm_max, 1); +static SENSOR_DEVICE_ATTR(pwm3_auto_point2_pwm, S_IWUSR | S_IRUGO, + show_pwm_max, set_pwm_max, 2); +static SENSOR_DEVICE_ATTR(pwm4_auto_point2_pwm, S_IWUSR | S_IRUGO, + show_pwm_max, set_pwm_max, 3); + +static SENSOR_DEVICE_ATTR(temp1_auto_point1_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 0); +static SENSOR_DEVICE_ATTR(temp2_auto_point1_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 1); +static SENSOR_DEVICE_ATTR(temp3_auto_point1_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 2); +static SENSOR_DEVICE_ATTR(temp4_auto_point1_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 3); + +static SENSOR_DEVICE_ATTR(temp1_auto_point2_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 0); +static SENSOR_DEVICE_ATTR(temp2_auto_point2_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 1); +static SENSOR_DEVICE_ATTR(temp3_auto_point2_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 2); +static SENSOR_DEVICE_ATTR(temp4_auto_point2_hyst, S_IWUSR | S_IRUGO, + show_pwm_hyst, set_pwm_hyst, 3); + +static SENSOR_DEVICE_ATTR(temp1_auto_point1_temp, S_IWUSR | S_IRUGO, + show_pwm_tmin, set_pwm_tmin, 0); +static SENSOR_DEVICE_ATTR(temp2_auto_point1_temp, S_IWUSR | S_IRUGO, + show_pwm_tmin, set_pwm_tmin, 1); +static SENSOR_DEVICE_ATTR(temp3_auto_point1_temp, S_IWUSR | S_IRUGO, + show_pwm_tmin, set_pwm_tmin, 2); +static SENSOR_DEVICE_ATTR(temp4_auto_point1_temp, S_IWUSR | S_IRUGO, + show_pwm_tmin, set_pwm_tmin, 3); + +static SENSOR_DEVICE_ATTR(temp1_auto_point2_temp, S_IWUSR | S_IRUGO, + show_pwm_tmax, set_pwm_tmax, 0); +static SENSOR_DEVICE_ATTR(temp2_auto_point2_temp, S_IWUSR | S_IRUGO, + show_pwm_tmax, set_pwm_tmax, 1); +static SENSOR_DEVICE_ATTR(temp3_auto_point2_temp, S_IWUSR | S_IRUGO, + show_pwm_tmax, set_pwm_tmax, 2); +static SENSOR_DEVICE_ATTR(temp4_auto_point2_temp, S_IWUSR | S_IRUGO, + show_pwm_tmax, set_pwm_tmax, 3); + +static SENSOR_DEVICE_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_auto, + set_pwm_auto, 0); +static SENSOR_DEVICE_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_auto, + set_pwm_auto, 1); +static SENSOR_DEVICE_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_auto, + set_pwm_auto, 2); +static SENSOR_DEVICE_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_auto, + set_pwm_auto, 3); + +static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IWUSR | S_IRUGO, + show_pwm_auto_temp, set_pwm_auto_temp, 0); +static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IWUSR | S_IRUGO, + show_pwm_auto_temp, set_pwm_auto_temp, 1); +static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IWUSR | S_IRUGO, + show_pwm_auto_temp, set_pwm_auto_temp, 2); +static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IWUSR | S_IRUGO, + show_pwm_auto_temp, set_pwm_auto_temp, 3); + +static struct attribute *adt7462_attr[] = +{ + &sensor_dev_attr_temp1_max.dev_attr.attr, + &sensor_dev_attr_temp2_max.dev_attr.attr, + &sensor_dev_attr_temp3_max.dev_attr.attr, + &sensor_dev_attr_temp4_max.dev_attr.attr, + + &sensor_dev_attr_temp1_min.dev_attr.attr, + &sensor_dev_attr_temp2_min.dev_attr.attr, + &sensor_dev_attr_temp3_min.dev_attr.attr, + &sensor_dev_attr_temp4_min.dev_attr.attr, + + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp2_input.dev_attr.attr, + &sensor_dev_attr_temp3_input.dev_attr.attr, + &sensor_dev_attr_temp4_input.dev_attr.attr, + + &sensor_dev_attr_temp1_label.dev_attr.attr, + &sensor_dev_attr_temp2_label.dev_attr.attr, + &sensor_dev_attr_temp3_label.dev_attr.attr, + &sensor_dev_attr_temp4_label.dev_attr.attr, + + &sensor_dev_attr_temp1_alarm.dev_attr.attr, + &sensor_dev_attr_temp2_alarm.dev_attr.attr, + &sensor_dev_attr_temp3_alarm.dev_attr.attr, + &sensor_dev_attr_temp4_alarm.dev_attr.attr, + + &sensor_dev_attr_in1_max.dev_attr.attr, + &sensor_dev_attr_in2_max.dev_attr.attr, + &sensor_dev_attr_in3_max.dev_attr.attr, + &sensor_dev_attr_in4_max.dev_attr.attr, + &sensor_dev_attr_in5_max.dev_attr.attr, + &sensor_dev_attr_in6_max.dev_attr.attr, + &sensor_dev_attr_in7_max.dev_attr.attr, + &sensor_dev_attr_in8_max.dev_attr.attr, + &sensor_dev_attr_in9_max.dev_attr.attr, + &sensor_dev_attr_in10_max.dev_attr.attr, + &sensor_dev_attr_in11_max.dev_attr.attr, + &sensor_dev_attr_in12_max.dev_attr.attr, + &sensor_dev_attr_in13_max.dev_attr.attr, + + &sensor_dev_attr_in1_min.dev_attr.attr, + &sensor_dev_attr_in2_min.dev_attr.attr, + &sensor_dev_attr_in3_min.dev_attr.attr, + &sensor_dev_attr_in4_min.dev_attr.attr, + &sensor_dev_attr_in5_min.dev_attr.attr, + &sensor_dev_attr_in6_min.dev_attr.attr, + &sensor_dev_attr_in7_min.dev_attr.attr, + &sensor_dev_attr_in8_min.dev_attr.attr, + &sensor_dev_attr_in9_min.dev_attr.attr, + &sensor_dev_attr_in10_min.dev_attr.attr, + &sensor_dev_attr_in11_min.dev_attr.attr, + &sensor_dev_attr_in12_min.dev_attr.attr, + &sensor_dev_attr_in13_min.dev_attr.attr, + + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_in2_input.dev_attr.attr, + &sensor_dev_attr_in3_input.dev_attr.attr, + &sensor_dev_attr_in4_input.dev_attr.attr, + &sensor_dev_attr_in5_input.dev_attr.attr, + &sensor_dev_attr_in6_input.dev_attr.attr, + &sensor_dev_attr_in7_input.dev_attr.attr, + &sensor_dev_attr_in8_input.dev_attr.attr, + &sensor_dev_attr_in9_input.dev_attr.attr, + &sensor_dev_attr_in10_input.dev_attr.attr, + &sensor_dev_attr_in11_input.dev_attr.attr, + &sensor_dev_attr_in12_input.dev_attr.attr, + &sensor_dev_attr_in13_input.dev_attr.attr, + + &sensor_dev_attr_in1_label.dev_attr.attr, + &sensor_dev_attr_in2_label.dev_attr.attr, + &sensor_dev_attr_in3_label.dev_attr.attr, + &sensor_dev_attr_in4_label.dev_attr.attr, + &sensor_dev_attr_in5_label.dev_attr.attr, + &sensor_dev_attr_in6_label.dev_attr.attr, + &sensor_dev_attr_in7_label.dev_attr.attr, + &sensor_dev_attr_in8_label.dev_attr.attr, + &sensor_dev_attr_in9_label.dev_attr.attr, + &sensor_dev_attr_in10_label.dev_attr.attr, + &sensor_dev_attr_in11_label.dev_attr.attr, + &sensor_dev_attr_in12_label.dev_attr.attr, + &sensor_dev_attr_in13_label.dev_attr.attr, + + &sensor_dev_attr_in1_alarm.dev_attr.attr, + &sensor_dev_attr_in2_alarm.dev_attr.attr, + &sensor_dev_attr_in3_alarm.dev_attr.attr, + &sensor_dev_attr_in4_alarm.dev_attr.attr, + &sensor_dev_attr_in5_alarm.dev_attr.attr, + &sensor_dev_attr_in6_alarm.dev_attr.attr, + &sensor_dev_attr_in7_alarm.dev_attr.attr, + &sensor_dev_attr_in8_alarm.dev_attr.attr, + &sensor_dev_attr_in9_alarm.dev_attr.attr, + &sensor_dev_attr_in10_alarm.dev_attr.attr, + &sensor_dev_attr_in11_alarm.dev_attr.attr, + &sensor_dev_attr_in12_alarm.dev_attr.attr, + &sensor_dev_attr_in13_alarm.dev_attr.attr, + + &sensor_dev_attr_fan1_min.dev_attr.attr, + &sensor_dev_attr_fan2_min.dev_attr.attr, + &sensor_dev_attr_fan3_min.dev_attr.attr, + &sensor_dev_attr_fan4_min.dev_attr.attr, + &sensor_dev_attr_fan5_min.dev_attr.attr, + &sensor_dev_attr_fan6_min.dev_attr.attr, + &sensor_dev_attr_fan7_min.dev_attr.attr, + &sensor_dev_attr_fan8_min.dev_attr.attr, + + &sensor_dev_attr_fan1_input.dev_attr.attr, + &sensor_dev_attr_fan2_input.dev_attr.attr, + &sensor_dev_attr_fan3_input.dev_attr.attr, + &sensor_dev_attr_fan4_input.dev_attr.attr, + &sensor_dev_attr_fan5_input.dev_attr.attr, + &sensor_dev_attr_fan6_input.dev_attr.attr, + &sensor_dev_attr_fan7_input.dev_attr.attr, + &sensor_dev_attr_fan8_input.dev_attr.attr, + + &sensor_dev_attr_fan1_alarm.dev_attr.attr, + &sensor_dev_attr_fan2_alarm.dev_attr.attr, + &sensor_dev_attr_fan3_alarm.dev_attr.attr, + &sensor_dev_attr_fan4_alarm.dev_attr.attr, + &sensor_dev_attr_fan5_alarm.dev_attr.attr, + &sensor_dev_attr_fan6_alarm.dev_attr.attr, + &sensor_dev_attr_fan7_alarm.dev_attr.attr, + &sensor_dev_attr_fan8_alarm.dev_attr.attr, + + &sensor_dev_attr_force_pwm_max.dev_attr.attr, + &sensor_dev_attr_pwm1.dev_attr.attr, + &sensor_dev_attr_pwm2.dev_attr.attr, + &sensor_dev_attr_pwm3.dev_attr.attr, + &sensor_dev_attr_pwm4.dev_attr.attr, + + &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, + &sensor_dev_attr_pwm4_auto_point1_pwm.dev_attr.attr, + + &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, + &sensor_dev_attr_pwm4_auto_point2_pwm.dev_attr.attr, + + &sensor_dev_attr_temp1_auto_point1_hyst.dev_attr.attr, + &sensor_dev_attr_temp2_auto_point1_hyst.dev_attr.attr, + &sensor_dev_attr_temp3_auto_point1_hyst.dev_attr.attr, + &sensor_dev_attr_temp4_auto_point1_hyst.dev_attr.attr, + + &sensor_dev_attr_temp1_auto_point2_hyst.dev_attr.attr, + &sensor_dev_attr_temp2_auto_point2_hyst.dev_attr.attr, + &sensor_dev_attr_temp3_auto_point2_hyst.dev_attr.attr, + &sensor_dev_attr_temp4_auto_point2_hyst.dev_attr.attr, + + &sensor_dev_attr_temp1_auto_point1_temp.dev_attr.attr, + &sensor_dev_attr_temp2_auto_point1_temp.dev_attr.attr, + &sensor_dev_attr_temp3_auto_point1_temp.dev_attr.attr, + &sensor_dev_attr_temp4_auto_point1_temp.dev_attr.attr, + + &sensor_dev_attr_temp1_auto_point2_temp.dev_attr.attr, + &sensor_dev_attr_temp2_auto_point2_temp.dev_attr.attr, + &sensor_dev_attr_temp3_auto_point2_temp.dev_attr.attr, + &sensor_dev_attr_temp4_auto_point2_temp.dev_attr.attr, + + &sensor_dev_attr_pwm1_enable.dev_attr.attr, + &sensor_dev_attr_pwm2_enable.dev_attr.attr, + &sensor_dev_attr_pwm3_enable.dev_attr.attr, + &sensor_dev_attr_pwm4_enable.dev_attr.attr, + + &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, + &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, + NULL +}; + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int adt7462_detect(struct i2c_client *client, int kind, + struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + if (kind <= 0) { + int vendor, device, revision; + + vendor = i2c_smbus_read_byte_data(client, ADT7462_REG_VENDOR); + if (vendor != ADT7462_VENDOR) + return -ENODEV; + + device = i2c_smbus_read_byte_data(client, ADT7462_REG_DEVICE); + if (device != ADT7462_DEVICE) + return -ENODEV; + + revision = i2c_smbus_read_byte_data(client, + ADT7462_REG_REVISION); + if (revision != ADT7462_REVISION) + return -ENODEV; + } else + dev_dbg(&adapter->dev, "detection forced\n"); + + strlcpy(info->type, "adt7462", I2C_NAME_SIZE); + + return 0; +} + +static int adt7462_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct adt7462_data *data; + int err; + + data = kzalloc(sizeof(struct adt7462_data), GFP_KERNEL); + if (!data) { + err = -ENOMEM; + goto exit; + } + + i2c_set_clientdata(client, data); + mutex_init(&data->lock); + + dev_info(&client->dev, "%s chip found\n", client->name); + + /* Register sysfs hooks */ + data->attrs.attrs = adt7462_attr; + err = sysfs_create_group(&client->dev.kobj, &data->attrs); + if (err) + goto exit_free; + + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + goto exit_remove; + } + + return 0; + +exit_remove: + sysfs_remove_group(&client->dev.kobj, &data->attrs); +exit_free: + kfree(data); +exit: + return err; +} + +static int adt7462_remove(struct i2c_client *client) +{ + struct adt7462_data *data = i2c_get_clientdata(client); + + hwmon_device_unregister(data->hwmon_dev); + sysfs_remove_group(&client->dev.kobj, &data->attrs); + kfree(data); + return 0; +} + +static int __init adt7462_init(void) +{ + return i2c_add_driver(&adt7462_driver); +} + +static void __exit adt7462_exit(void) +{ + i2c_del_driver(&adt7462_driver); +} + +MODULE_AUTHOR("Darrick J. Wong "); +MODULE_DESCRIPTION("ADT7462 driver"); +MODULE_LICENSE("GPL"); + +module_init(adt7462_init); +module_exit(adt7462_exit); diff --git a/drivers/hwmon/adt7470.c b/drivers/hwmon/adt7470.c index d368d8f845e1..1311a595147e 100644 --- a/drivers/hwmon/adt7470.c +++ b/drivers/hwmon/adt7470.c @@ -137,6 +137,8 @@ I2C_CLIENT_INSMOD_1(adt7470); #define FAN_PERIOD_INVALID 65535 #define FAN_DATA_VALID(x) ((x) && (x) != FAN_PERIOD_INVALID) +#define ROUND_DIV(x, divisor) (((x) + ((divisor) / 2)) / (divisor)) + struct adt7470_data { struct device *hwmon_dev; struct attribute_group attrs; @@ -353,7 +355,13 @@ static ssize_t set_temp_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->temp_min[attr->index] = temp; @@ -381,7 +389,13 @@ static ssize_t set_temp_max(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->temp_max[attr->index] = temp; @@ -430,11 +444,13 @@ static ssize_t set_fan_max(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; - if (!temp) + if (strict_strtol(buf, 10, &temp) || !temp) return -EINVAL; + temp = FAN_RPM_TO_PERIOD(temp); + temp = SENSORS_LIMIT(temp, 1, 65534); mutex_lock(&data->lock); data->fan_max[attr->index] = temp; @@ -465,11 +481,13 @@ static ssize_t set_fan_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; - if (!temp) + if (strict_strtol(buf, 10, &temp) || !temp) return -EINVAL; + temp = FAN_RPM_TO_PERIOD(temp); + temp = SENSORS_LIMIT(temp, 1, 65534); mutex_lock(&data->lock); data->fan_min[attr->index] = temp; @@ -507,9 +525,12 @@ static ssize_t set_force_pwm_max(struct device *dev, { struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; u8 reg; + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + mutex_lock(&data->lock); data->force_pwm_max = temp; reg = i2c_smbus_read_byte_data(client, ADT7470_REG_CFG); @@ -537,7 +558,12 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *devattr, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm[attr->index] = temp; @@ -564,7 +590,12 @@ static ssize_t set_pwm_max(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm_max[attr->index] = temp; @@ -592,7 +623,12 @@ static ssize_t set_pwm_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm_min[attr->index] = temp; @@ -630,7 +666,13 @@ static ssize_t set_pwm_tmin(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm_tmin[attr->index] = temp; @@ -658,11 +700,14 @@ static ssize_t set_pwm_auto(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); int pwm_auto_reg = ADT7470_REG_PWM_CFG(attr->index); int pwm_auto_reg_mask; + long temp; u8 reg; + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + if (attr->index % 2) pwm_auto_reg_mask = ADT7470_PWM2_AUTO_MASK; else @@ -716,10 +761,14 @@ static ssize_t set_pwm_auto_temp(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7470_data *data = i2c_get_clientdata(client); - int temp = cvt_auto_temp(simple_strtol(buf, NULL, 10)); int pwm_auto_reg = ADT7470_REG_PWM_AUTO_TEMP(attr->index); + long temp; u8 reg; + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = cvt_auto_temp(temp); if (temp < 0) return temp; diff --git a/drivers/hwmon/adt7473.c b/drivers/hwmon/adt7473.c index b9a8ea30c99c..18aa30866a6c 100644 --- a/drivers/hwmon/adt7473.c +++ b/drivers/hwmon/adt7473.c @@ -129,6 +129,8 @@ I2C_CLIENT_INSMOD_1(adt7473); #define FAN_PERIOD_INVALID 65535 #define FAN_DATA_VALID(x) ((x) && (x) != FAN_PERIOD_INVALID) +#define ROUND_DIV(x, divisor) (((x) + ((divisor) / 2)) / (divisor)) + struct adt7473_data { struct device *hwmon_dev; struct attribute_group attrs; @@ -357,7 +359,12 @@ static ssize_t set_volt_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int volt = encode_volt(attr->index, simple_strtol(buf, NULL, 10)); + long volt; + + if (strict_strtol(buf, 10, &volt)) + return -EINVAL; + + volt = encode_volt(attr->index, volt); mutex_lock(&data->lock); data->volt_min[attr->index] = volt; @@ -386,7 +393,12 @@ static ssize_t set_volt_max(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int volt = encode_volt(attr->index, simple_strtol(buf, NULL, 10)); + long volt; + + if (strict_strtol(buf, 10, &volt)) + return -EINVAL; + + volt = encode_volt(attr->index, volt); mutex_lock(&data->lock); data->volt_max[attr->index] = volt; @@ -419,7 +431,8 @@ static int decode_temp(u8 twos_complement, u8 raw) static u8 encode_temp(u8 twos_complement, int cooked) { - return twos_complement ? cooked & 0xFF : cooked + 64; + u8 ret = twos_complement ? cooked & 0xFF : cooked + 64; + return SENSORS_LIMIT(ret, 0, 255); } static ssize_t show_temp_min(struct device *dev, @@ -441,7 +454,12 @@ static ssize_t set_temp_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); temp = encode_temp(data->temp_twos_complement, temp); mutex_lock(&data->lock); @@ -472,7 +490,12 @@ static ssize_t set_temp_max(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); temp = encode_temp(data->temp_twos_complement, temp); mutex_lock(&data->lock); @@ -515,11 +538,13 @@ static ssize_t set_fan_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; - if (!temp) + if (strict_strtol(buf, 10, &temp) || !temp) return -EINVAL; + temp = FAN_RPM_TO_PERIOD(temp); + temp = SENSORS_LIMIT(temp, 1, 65534); mutex_lock(&data->lock); data->fan_min[attr->index] = temp; @@ -558,7 +583,10 @@ static ssize_t set_max_duty_at_crit(struct device *dev, u8 reg; struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; mutex_lock(&data->lock); data->max_duty_at_overheat = !!temp; @@ -587,7 +615,12 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *devattr, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm[attr->index] = temp; @@ -614,7 +647,12 @@ static ssize_t set_pwm_max(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm_max[attr->index] = temp; @@ -642,7 +680,12 @@ static ssize_t set_pwm_min(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = SENSORS_LIMIT(temp, 0, 255); mutex_lock(&data->lock); data->pwm_min[attr->index] = temp; @@ -672,7 +715,12 @@ static ssize_t set_temp_tmax(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); temp = encode_temp(data->temp_twos_complement, temp); mutex_lock(&data->lock); @@ -703,7 +751,12 @@ static ssize_t set_temp_tmin(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10) / 1000; + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; + + temp = ROUND_DIV(temp, 1000); temp = encode_temp(data->temp_twos_complement, temp); mutex_lock(&data->lock); @@ -741,7 +794,10 @@ static ssize_t set_pwm_enable(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; switch (temp) { case 0: @@ -805,7 +861,10 @@ static ssize_t set_pwm_auto_temp(struct device *dev, struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct i2c_client *client = to_i2c_client(dev); struct adt7473_data *data = i2c_get_clientdata(client); - int temp = simple_strtol(buf, NULL, 10); + long temp; + + if (strict_strtol(buf, 10, &temp)) + return -EINVAL; switch (temp) { case 1: diff --git a/drivers/hwmon/applesmc.c b/drivers/hwmon/applesmc.c index bc011da79e14..086c2a5cef0b 100644 --- a/drivers/hwmon/applesmc.c +++ b/drivers/hwmon/applesmc.c @@ -116,6 +116,21 @@ static const char* temperature_sensors_sets[][36] = { /* Set 9: Macbook Pro 3,1 (Santa Rosa) */ { "TALP", "TB0T", "TC0D", "TC0P", "TG0D", "TG0H", "TTF0", "TW0P", "Th0H", "Th1H", "Th2H", "Tm0P", "Ts0P", NULL }, +/* Set 10: iMac 5,1 */ + { "TA0P", "TC0D", "TC0P", "TG0D", "TH0P", "TO0P", "Tm0P", NULL }, +/* Set 11: Macbook 5,1 */ + { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", "TC0P", "TN0D", "TN0P", + "TTF0", "Th0H", "Th1H", "ThFH", "Ts0P", "Ts0S", NULL }, +/* Set 12: Macbook Pro 5,1 */ + { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", "TC0F", "TC0P", "TG0D", + "TG0F", "TG0H", "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", "TTF0", + "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }, +/* Set 13: iMac 8,1 */ + { "TA0P", "TC0D", "TC0H", "TC0P", "TG0D", "TG0H", "TG0P", "TH0P", + "TL0P", "TO0P", "TW0P", "Tm0P", "Tp0P", NULL }, +/* Set 14: iMac 6,1 */ + { "TA0P", "TC0D", "TC0H", "TC0P", "TG0D", "TG0H", "TG0P", "TH0P", + "TO0P", "Tp0P", NULL }, }; /* List of keys used to read/write fan speeds */ @@ -1268,7 +1283,7 @@ static __initdata struct dmi_match_data applesmc_dmi_data[] = { { .accelerometer = 0, .light = 0, .temperature_set = 4 }, /* iMac: temperature set 5 */ { .accelerometer = 0, .light = 0, .temperature_set = 5 }, -/* MacBook3: accelerometer and temperature set 6 */ +/* MacBook3, MacBook4: accelerometer and temperature set 6 */ { .accelerometer = 1, .light = 0, .temperature_set = 6 }, /* MacBook Air: accelerometer, backlight and temperature set 7 */ { .accelerometer = 1, .light = 1, .temperature_set = 7 }, @@ -1276,6 +1291,16 @@ static __initdata struct dmi_match_data applesmc_dmi_data[] = { { .accelerometer = 1, .light = 1, .temperature_set = 8 }, /* MacBook Pro 3: accelerometer, backlight and temperature set 9 */ { .accelerometer = 1, .light = 1, .temperature_set = 9 }, +/* iMac 5: light sensor only, temperature set 10 */ + { .accelerometer = 0, .light = 0, .temperature_set = 10 }, +/* MacBook 5: accelerometer, backlight and temperature set 11 */ + { .accelerometer = 1, .light = 1, .temperature_set = 11 }, +/* MacBook Pro 5: accelerometer, backlight and temperature set 12 */ + { .accelerometer = 1, .light = 1, .temperature_set = 12 }, +/* iMac 8: light sensor only, temperature set 13 */ + { .accelerometer = 0, .light = 0, .temperature_set = 13 }, +/* iMac 6: light sensor only, temperature set 14 */ + { .accelerometer = 0, .light = 0, .temperature_set = 14 }, }; /* Note that DMI_MATCH(...,"MacBook") will match "MacBookPro1,1". @@ -1285,6 +1310,10 @@ static __initdata struct dmi_system_id applesmc_whitelist[] = { DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir") }, &applesmc_dmi_data[7]}, + { applesmc_dmi_match, "Apple MacBook Pro 5", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5") }, + &applesmc_dmi_data[12]}, { applesmc_dmi_match, "Apple MacBook Pro 4", { DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro4") }, @@ -1305,6 +1334,14 @@ static __initdata struct dmi_system_id applesmc_whitelist[] = { DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), DMI_MATCH(DMI_PRODUCT_NAME,"MacBook3") }, &applesmc_dmi_data[6]}, + { applesmc_dmi_match, "Apple MacBook 4", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBook4") }, + &applesmc_dmi_data[6]}, + { applesmc_dmi_match, "Apple MacBook 5", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5") }, + &applesmc_dmi_data[11]}, { applesmc_dmi_match, "Apple MacBook", { DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), DMI_MATCH(DMI_PRODUCT_NAME,"MacBook") }, @@ -1317,6 +1354,22 @@ static __initdata struct dmi_system_id applesmc_whitelist[] = { DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), DMI_MATCH(DMI_PRODUCT_NAME,"MacPro2") }, &applesmc_dmi_data[4]}, + { applesmc_dmi_match, "Apple MacPro", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "MacPro") }, + &applesmc_dmi_data[4]}, + { applesmc_dmi_match, "Apple iMac 8", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "iMac8") }, + &applesmc_dmi_data[13]}, + { applesmc_dmi_match, "Apple iMac 6", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "iMac6") }, + &applesmc_dmi_data[14]}, + { applesmc_dmi_match, "Apple iMac 5", { + DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), + DMI_MATCH(DMI_PRODUCT_NAME, "iMac5") }, + &applesmc_dmi_data[10]}, { applesmc_dmi_match, "Apple iMac", { DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), DMI_MATCH(DMI_PRODUCT_NAME,"iMac") }, @@ -1511,3 +1564,4 @@ module_exit(applesmc_exit); MODULE_AUTHOR("Nicolas Boichat"); MODULE_DESCRIPTION("Apple SMC"); MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(dmi, applesmc_whitelist); diff --git a/drivers/hwmon/ibmaem.c b/drivers/hwmon/ibmaem.c index 7b0ed5dea399..fe74609a7feb 100644 --- a/drivers/hwmon/ibmaem.c +++ b/drivers/hwmon/ibmaem.c @@ -88,9 +88,11 @@ static DEFINE_IDR(aem_idr); static DEFINE_SPINLOCK(aem_idr_lock); -static struct device_driver aem_driver = { - .name = DRVNAME, - .bus = &platform_bus_type, +static struct platform_driver aem_driver = { + .driver = { + .name = DRVNAME, + .bus = &platform_bus_type, + } }; struct aem_ipmi_data { @@ -583,7 +585,7 @@ static int aem_init_aem1_inst(struct aem_ipmi_data *probe, u8 module_handle) data->pdev = platform_device_alloc(DRVNAME, data->id); if (!data->pdev) goto dev_err; - data->pdev->dev.driver = &aem_driver; + data->pdev->dev.driver = &aem_driver.driver; res = platform_device_add(data->pdev); if (res) @@ -716,7 +718,7 @@ static int aem_init_aem2_inst(struct aem_ipmi_data *probe, data->pdev = platform_device_alloc(DRVNAME, data->id); if (!data->pdev) goto dev_err; - data->pdev->dev.driver = &aem_driver; + data->pdev->dev.driver = &aem_driver.driver; res = platform_device_add(data->pdev); if (res) @@ -1085,7 +1087,7 @@ static int __init aem_init(void) { int res; - res = driver_register(&aem_driver); + res = driver_register(&aem_driver.driver); if (res) { printk(KERN_ERR "Can't register aem driver\n"); return res; @@ -1097,7 +1099,7 @@ static int __init aem_init(void) return 0; ipmi_reg_err: - driver_unregister(&aem_driver); + driver_unregister(&aem_driver.driver); return res; } @@ -1107,7 +1109,7 @@ static void __exit aem_exit(void) struct aem_data *p1, *next1; ipmi_smi_watcher_unregister(&driver_data.bmc_events); - driver_unregister(&aem_driver); + driver_unregister(&aem_driver.driver); list_for_each_entry_safe(p1, next1, &driver_data.aem_devices, list) aem_delete(p1); } diff --git a/drivers/hwmon/lis3lv02d.c b/drivers/hwmon/lis3lv02d.c new file mode 100644 index 000000000000..c002144c76bc --- /dev/null +++ b/drivers/hwmon/lis3lv02d.c @@ -0,0 +1,581 @@ +/* + * lis3lv02d.c - ST LIS3LV02DL accelerometer driver + * + * Copyright (C) 2007-2008 Yan Burman + * Copyright (C) 2008 Eric Piel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lis3lv02d.h" + +#define DRIVER_NAME "lis3lv02d" +#define ACPI_MDPS_CLASS "accelerometer" + +/* joystick device poll interval in milliseconds */ +#define MDPS_POLL_INTERVAL 50 +/* + * The sensor can also generate interrupts (DRDY) but it's pretty pointless + * because their are generated even if the data do not change. So it's better + * to keep the interrupt for the free-fall event. The values are updated at + * 40Hz (at the lowest frequency), but as it can be pretty time consuming on + * some low processor, we poll the sensor only at 20Hz... enough for the + * joystick. + */ + +/* Maximum value our axis may get for the input device (signed 12 bits) */ +#define MDPS_MAX_VAL 2048 + +struct axis_conversion { + s8 x; + s8 y; + s8 z; +}; + +struct acpi_lis3lv02d { + struct acpi_device *device; /* The ACPI device */ + struct input_dev *idev; /* input device */ + struct task_struct *kthread; /* kthread for input */ + struct mutex lock; + struct platform_device *pdev; /* platform device */ + atomic_t count; /* interrupt count after last read */ + int xcalib; /* calibrated null value for x */ + int ycalib; /* calibrated null value for y */ + int zcalib; /* calibrated null value for z */ + unsigned char is_on; /* whether the device is on or off */ + unsigned char usage; /* usage counter */ + struct axis_conversion ac; /* hw -> logical axis */ +}; + +static struct acpi_lis3lv02d adev; + +static int lis3lv02d_remove_fs(void); +static int lis3lv02d_add_fs(struct acpi_device *device); + +/* For automatic insertion of the module */ +static struct acpi_device_id lis3lv02d_device_ids[] = { + {"HPQ0004", 0}, /* HP Mobile Data Protection System PNP */ + {"", 0}, +}; +MODULE_DEVICE_TABLE(acpi, lis3lv02d_device_ids); + +/** + * lis3lv02d_acpi_init - ACPI _INI method: initialize the device. + * @handle: the handle of the device + * + * Returns AE_OK on success. + */ +static inline acpi_status lis3lv02d_acpi_init(acpi_handle handle) +{ + return acpi_evaluate_object(handle, METHOD_NAME__INI, NULL, NULL); +} + +/** + * lis3lv02d_acpi_read - ACPI ALRD method: read a register + * @handle: the handle of the device + * @reg: the register to read + * @ret: result of the operation + * + * Returns AE_OK on success. + */ +static acpi_status lis3lv02d_acpi_read(acpi_handle handle, int reg, u8 *ret) +{ + union acpi_object arg0 = { ACPI_TYPE_INTEGER }; + struct acpi_object_list args = { 1, &arg0 }; + unsigned long long lret; + acpi_status status; + + arg0.integer.value = reg; + + status = acpi_evaluate_integer(handle, "ALRD", &args, &lret); + *ret = lret; + return status; +} + +/** + * lis3lv02d_acpi_write - ACPI ALWR method: write to a register + * @handle: the handle of the device + * @reg: the register to write to + * @val: the value to write + * + * Returns AE_OK on success. + */ +static acpi_status lis3lv02d_acpi_write(acpi_handle handle, int reg, u8 val) +{ + unsigned long long ret; /* Not used when writting */ + union acpi_object in_obj[2]; + struct acpi_object_list args = { 2, in_obj }; + + in_obj[0].type = ACPI_TYPE_INTEGER; + in_obj[0].integer.value = reg; + in_obj[1].type = ACPI_TYPE_INTEGER; + in_obj[1].integer.value = val; + + return acpi_evaluate_integer(handle, "ALWR", &args, &ret); +} + +static s16 lis3lv02d_read_16(acpi_handle handle, int reg) +{ + u8 lo, hi; + + lis3lv02d_acpi_read(handle, reg, &lo); + lis3lv02d_acpi_read(handle, reg + 1, &hi); + /* In "12 bit right justified" mode, bit 6, bit 7, bit 8 = bit 5 */ + return (s16)((hi << 8) | lo); +} + +/** + * lis3lv02d_get_axis - For the given axis, give the value converted + * @axis: 1,2,3 - can also be negative + * @hw_values: raw values returned by the hardware + * + * Returns the converted value. + */ +static inline int lis3lv02d_get_axis(s8 axis, int hw_values[3]) +{ + if (axis > 0) + return hw_values[axis - 1]; + else + return -hw_values[-axis - 1]; +} + +/** + * lis3lv02d_get_xyz - Get X, Y and Z axis values from the accelerometer + * @handle: the handle to the device + * @x: where to store the X axis value + * @y: where to store the Y axis value + * @z: where to store the Z axis value + * + * Note that 40Hz input device can eat up about 10% CPU at 800MHZ + */ +static void lis3lv02d_get_xyz(acpi_handle handle, int *x, int *y, int *z) +{ + int position[3]; + + position[0] = lis3lv02d_read_16(handle, OUTX_L); + position[1] = lis3lv02d_read_16(handle, OUTY_L); + position[2] = lis3lv02d_read_16(handle, OUTZ_L); + + *x = lis3lv02d_get_axis(adev.ac.x, position); + *y = lis3lv02d_get_axis(adev.ac.y, position); + *z = lis3lv02d_get_axis(adev.ac.z, position); +} + +static inline void lis3lv02d_poweroff(acpi_handle handle) +{ + adev.is_on = 0; + /* disable X,Y,Z axis and power down */ + lis3lv02d_acpi_write(handle, CTRL_REG1, 0x00); +} + +static void lis3lv02d_poweron(acpi_handle handle) +{ + u8 val; + + adev.is_on = 1; + lis3lv02d_acpi_init(handle); + lis3lv02d_acpi_write(handle, FF_WU_CFG, 0); + /* + * BDU: LSB and MSB values are not updated until both have been read. + * So the value read will always be correct. + * IEN: Interrupt for free-fall and DD, not for data-ready. + */ + lis3lv02d_acpi_read(handle, CTRL_REG2, &val); + val |= CTRL2_BDU | CTRL2_IEN; + lis3lv02d_acpi_write(handle, CTRL_REG2, val); +} + +#ifdef CONFIG_PM +static int lis3lv02d_suspend(struct acpi_device *device, pm_message_t state) +{ + /* make sure the device is off when we suspend */ + lis3lv02d_poweroff(device->handle); + return 0; +} + +static int lis3lv02d_resume(struct acpi_device *device) +{ + /* put back the device in the right state (ACPI might turn it on) */ + mutex_lock(&adev.lock); + if (adev.usage > 0) + lis3lv02d_poweron(device->handle); + else + lis3lv02d_poweroff(device->handle); + mutex_unlock(&adev.lock); + return 0; +} +#else +#define lis3lv02d_suspend NULL +#define lis3lv02d_resume NULL +#endif + + +/* + * To be called before starting to use the device. It makes sure that the + * device will always be on until a call to lis3lv02d_decrease_use(). Not to be + * used from interrupt context. + */ +static void lis3lv02d_increase_use(struct acpi_lis3lv02d *dev) +{ + mutex_lock(&dev->lock); + dev->usage++; + if (dev->usage == 1) { + if (!dev->is_on) + lis3lv02d_poweron(dev->device->handle); + } + mutex_unlock(&dev->lock); +} + +/* + * To be called whenever a usage of the device is stopped. + * It will make sure to turn off the device when there is not usage. + */ +static void lis3lv02d_decrease_use(struct acpi_lis3lv02d *dev) +{ + mutex_lock(&dev->lock); + dev->usage--; + if (dev->usage == 0) + lis3lv02d_poweroff(dev->device->handle); + mutex_unlock(&dev->lock); +} + +/** + * lis3lv02d_joystick_kthread - Kthread polling function + * @data: unused - here to conform to threadfn prototype + */ +static int lis3lv02d_joystick_kthread(void *data) +{ + int x, y, z; + + while (!kthread_should_stop()) { + lis3lv02d_get_xyz(adev.device->handle, &x, &y, &z); + input_report_abs(adev.idev, ABS_X, x - adev.xcalib); + input_report_abs(adev.idev, ABS_Y, y - adev.ycalib); + input_report_abs(adev.idev, ABS_Z, z - adev.zcalib); + + input_sync(adev.idev); + + try_to_freeze(); + msleep_interruptible(MDPS_POLL_INTERVAL); + } + + return 0; +} + +static int lis3lv02d_joystick_open(struct input_dev *input) +{ + lis3lv02d_increase_use(&adev); + adev.kthread = kthread_run(lis3lv02d_joystick_kthread, NULL, "klis3lv02d"); + if (IS_ERR(adev.kthread)) { + lis3lv02d_decrease_use(&adev); + return PTR_ERR(adev.kthread); + } + + return 0; +} + +static void lis3lv02d_joystick_close(struct input_dev *input) +{ + kthread_stop(adev.kthread); + lis3lv02d_decrease_use(&adev); +} + + +static inline void lis3lv02d_calibrate_joystick(void) +{ + lis3lv02d_get_xyz(adev.device->handle, &adev.xcalib, &adev.ycalib, &adev.zcalib); +} + +static int lis3lv02d_joystick_enable(void) +{ + int err; + + if (adev.idev) + return -EINVAL; + + adev.idev = input_allocate_device(); + if (!adev.idev) + return -ENOMEM; + + lis3lv02d_calibrate_joystick(); + + adev.idev->name = "ST LIS3LV02DL Accelerometer"; + adev.idev->phys = DRIVER_NAME "/input0"; + adev.idev->id.bustype = BUS_HOST; + adev.idev->id.vendor = 0; + adev.idev->dev.parent = &adev.pdev->dev; + adev.idev->open = lis3lv02d_joystick_open; + adev.idev->close = lis3lv02d_joystick_close; + + set_bit(EV_ABS, adev.idev->evbit); + input_set_abs_params(adev.idev, ABS_X, -MDPS_MAX_VAL, MDPS_MAX_VAL, 3, 3); + input_set_abs_params(adev.idev, ABS_Y, -MDPS_MAX_VAL, MDPS_MAX_VAL, 3, 3); + input_set_abs_params(adev.idev, ABS_Z, -MDPS_MAX_VAL, MDPS_MAX_VAL, 3, 3); + + err = input_register_device(adev.idev); + if (err) { + input_free_device(adev.idev); + adev.idev = NULL; + } + + return err; +} + +static void lis3lv02d_joystick_disable(void) +{ + if (!adev.idev) + return; + + input_unregister_device(adev.idev); + adev.idev = NULL; +} + + +/* + * Initialise the accelerometer and the various subsystems. + * Should be rather independant of the bus system. + */ +static int lis3lv02d_init_device(struct acpi_lis3lv02d *dev) +{ + mutex_init(&dev->lock); + lis3lv02d_add_fs(dev->device); + lis3lv02d_increase_use(dev); + + if (lis3lv02d_joystick_enable()) + printk(KERN_ERR DRIVER_NAME ": joystick initialization failed\n"); + + lis3lv02d_decrease_use(dev); + return 0; +} + +static int lis3lv02d_dmi_matched(const struct dmi_system_id *dmi) +{ + adev.ac = *((struct axis_conversion *)dmi->driver_data); + printk(KERN_INFO DRIVER_NAME ": hardware type %s found.\n", dmi->ident); + + return 1; +} + +/* Represents, for each axis seen by userspace, the corresponding hw axis (+1). + * If the value is negative, the opposite of the hw value is used. */ +static struct axis_conversion lis3lv02d_axis_normal = {1, 2, 3}; +static struct axis_conversion lis3lv02d_axis_y_inverted = {1, -2, 3}; +static struct axis_conversion lis3lv02d_axis_x_inverted = {-1, 2, 3}; +static struct axis_conversion lis3lv02d_axis_z_inverted = {1, 2, -3}; +static struct axis_conversion lis3lv02d_axis_xy_rotated_left = {-2, 1, 3}; +static struct axis_conversion lis3lv02d_axis_xy_swap_inverted = {-2, -1, 3}; + +#define AXIS_DMI_MATCH(_ident, _name, _axis) { \ + .ident = _ident, \ + .callback = lis3lv02d_dmi_matched, \ + .matches = { \ + DMI_MATCH(DMI_PRODUCT_NAME, _name) \ + }, \ + .driver_data = &lis3lv02d_axis_##_axis \ +} +static struct dmi_system_id lis3lv02d_dmi_ids[] = { + /* product names are truncated to match all kinds of a same model */ + AXIS_DMI_MATCH("NC64x0", "HP Compaq nc64", x_inverted), + AXIS_DMI_MATCH("NC84x0", "HP Compaq nc84", z_inverted), + AXIS_DMI_MATCH("NX9420", "HP Compaq nx9420", x_inverted), + AXIS_DMI_MATCH("NW9440", "HP Compaq nw9440", x_inverted), + AXIS_DMI_MATCH("NC2510", "HP Compaq 2510", y_inverted), + AXIS_DMI_MATCH("NC8510", "HP Compaq 8510", xy_swap_inverted), + AXIS_DMI_MATCH("HP2133", "HP 2133", xy_rotated_left), + { NULL, } +/* Laptop models without axis info (yet): + * "NC651xx" "HP Compaq 651" + * "NC671xx" "HP Compaq 671" + * "NC6910" "HP Compaq 6910" + * HP Compaq 8710x Notebook PC / Mobile Workstation + * "NC2400" "HP Compaq nc2400" + * "NX74x0" "HP Compaq nx74" + * "NX6325" "HP Compaq nx6325" + * "NC4400" "HP Compaq nc4400" + */ +}; + +static int lis3lv02d_add(struct acpi_device *device) +{ + u8 val; + + if (!device) + return -EINVAL; + + adev.device = device; + strcpy(acpi_device_name(device), DRIVER_NAME); + strcpy(acpi_device_class(device), ACPI_MDPS_CLASS); + device->driver_data = &adev; + + lis3lv02d_acpi_read(device->handle, WHO_AM_I, &val); + if ((val != LIS3LV02DL_ID) && (val != LIS302DL_ID)) { + printk(KERN_ERR DRIVER_NAME + ": Accelerometer chip not LIS3LV02D{L,Q}\n"); + } + + /* If possible use a "standard" axes order */ + if (dmi_check_system(lis3lv02d_dmi_ids) == 0) { + printk(KERN_INFO DRIVER_NAME ": laptop model unknown, " + "using default axes configuration\n"); + adev.ac = lis3lv02d_axis_normal; + } + + return lis3lv02d_init_device(&adev); +} + +static int lis3lv02d_remove(struct acpi_device *device, int type) +{ + if (!device) + return -EINVAL; + + lis3lv02d_joystick_disable(); + lis3lv02d_poweroff(device->handle); + + return lis3lv02d_remove_fs(); +} + + +/* Sysfs stuff */ +static ssize_t lis3lv02d_position_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int x, y, z; + + lis3lv02d_increase_use(&adev); + lis3lv02d_get_xyz(adev.device->handle, &x, &y, &z); + lis3lv02d_decrease_use(&adev); + return sprintf(buf, "(%d,%d,%d)\n", x, y, z); +} + +static ssize_t lis3lv02d_calibrate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "(%d,%d,%d)\n", adev.xcalib, adev.ycalib, adev.zcalib); +} + +static ssize_t lis3lv02d_calibrate_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + lis3lv02d_increase_use(&adev); + lis3lv02d_calibrate_joystick(); + lis3lv02d_decrease_use(&adev); + return count; +} + +/* conversion btw sampling rate and the register values */ +static int lis3lv02dl_df_val[4] = {40, 160, 640, 2560}; +static ssize_t lis3lv02d_rate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 ctrl; + int val; + + lis3lv02d_increase_use(&adev); + lis3lv02d_acpi_read(adev.device->handle, CTRL_REG1, &ctrl); + lis3lv02d_decrease_use(&adev); + val = (ctrl & (CTRL1_DF0 | CTRL1_DF1)) >> 4; + return sprintf(buf, "%d\n", lis3lv02dl_df_val[val]); +} + +static DEVICE_ATTR(position, S_IRUGO, lis3lv02d_position_show, NULL); +static DEVICE_ATTR(calibrate, S_IRUGO|S_IWUSR, lis3lv02d_calibrate_show, + lis3lv02d_calibrate_store); +static DEVICE_ATTR(rate, S_IRUGO, lis3lv02d_rate_show, NULL); + +static struct attribute *lis3lv02d_attributes[] = { + &dev_attr_position.attr, + &dev_attr_calibrate.attr, + &dev_attr_rate.attr, + NULL +}; + +static struct attribute_group lis3lv02d_attribute_group = { + .attrs = lis3lv02d_attributes +}; + +static int lis3lv02d_add_fs(struct acpi_device *device) +{ + adev.pdev = platform_device_register_simple(DRIVER_NAME, -1, NULL, 0); + if (IS_ERR(adev.pdev)) + return PTR_ERR(adev.pdev); + + return sysfs_create_group(&adev.pdev->dev.kobj, &lis3lv02d_attribute_group); +} + +static int lis3lv02d_remove_fs(void) +{ + sysfs_remove_group(&adev.pdev->dev.kobj, &lis3lv02d_attribute_group); + platform_device_unregister(adev.pdev); + return 0; +} + +/* For the HP MDPS aka 3D Driveguard */ +static struct acpi_driver lis3lv02d_driver = { + .name = DRIVER_NAME, + .class = ACPI_MDPS_CLASS, + .ids = lis3lv02d_device_ids, + .ops = { + .add = lis3lv02d_add, + .remove = lis3lv02d_remove, + .suspend = lis3lv02d_suspend, + .resume = lis3lv02d_resume, + } +}; + +static int __init lis3lv02d_init_module(void) +{ + int ret; + + if (acpi_disabled) + return -ENODEV; + + ret = acpi_bus_register_driver(&lis3lv02d_driver); + if (ret < 0) + return ret; + + printk(KERN_INFO DRIVER_NAME " driver loaded.\n"); + + return 0; +} + +static void __exit lis3lv02d_exit_module(void) +{ + acpi_bus_unregister_driver(&lis3lv02d_driver); +} + +MODULE_DESCRIPTION("ST LIS3LV02Dx three-axis digital accelerometer driver"); +MODULE_AUTHOR("Yan Burman and Eric Piel"); +MODULE_LICENSE("GPL"); + +module_init(lis3lv02d_init_module); +module_exit(lis3lv02d_exit_module); diff --git a/drivers/hwmon/lis3lv02d.h b/drivers/hwmon/lis3lv02d.h new file mode 100644 index 000000000000..330cfc60e948 --- /dev/null +++ b/drivers/hwmon/lis3lv02d.h @@ -0,0 +1,149 @@ +/* + * lis3lv02d.h - ST LIS3LV02DL accelerometer driver + * + * Copyright (C) 2007-2008 Yan Burman + * Copyright (C) 2008 Eric Piel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * The actual chip is STMicroelectronics LIS3LV02DL or LIS3LV02DQ that seems to + * be connected via SPI. There exists also several similar chips (such as LIS302DL or + * LIS3L02DQ) but not in the HP laptops and they have slightly different registers. + * They can also be connected via I²C. + */ + +#define LIS3LV02DL_ID 0x3A /* Also the LIS3LV02DQ */ +#define LIS302DL_ID 0x3B /* Also the LIS202DL! */ + +enum lis3lv02d_reg { + WHO_AM_I = 0x0F, + OFFSET_X = 0x16, + OFFSET_Y = 0x17, + OFFSET_Z = 0x18, + GAIN_X = 0x19, + GAIN_Y = 0x1A, + GAIN_Z = 0x1B, + CTRL_REG1 = 0x20, + CTRL_REG2 = 0x21, + CTRL_REG3 = 0x22, + HP_FILTER_RESET = 0x23, + STATUS_REG = 0x27, + OUTX_L = 0x28, + OUTX_H = 0x29, + OUTY_L = 0x2A, + OUTY_H = 0x2B, + OUTZ_L = 0x2C, + OUTZ_H = 0x2D, + FF_WU_CFG = 0x30, + FF_WU_SRC = 0x31, + FF_WU_ACK = 0x32, + FF_WU_THS_L = 0x34, + FF_WU_THS_H = 0x35, + FF_WU_DURATION = 0x36, + DD_CFG = 0x38, + DD_SRC = 0x39, + DD_ACK = 0x3A, + DD_THSI_L = 0x3C, + DD_THSI_H = 0x3D, + DD_THSE_L = 0x3E, + DD_THSE_H = 0x3F, +}; + +enum lis3lv02d_ctrl1 { + CTRL1_Xen = 0x01, + CTRL1_Yen = 0x02, + CTRL1_Zen = 0x04, + CTRL1_ST = 0x08, + CTRL1_DF0 = 0x10, + CTRL1_DF1 = 0x20, + CTRL1_PD0 = 0x40, + CTRL1_PD1 = 0x80, +}; +enum lis3lv02d_ctrl2 { + CTRL2_DAS = 0x01, + CTRL2_SIM = 0x02, + CTRL2_DRDY = 0x04, + CTRL2_IEN = 0x08, + CTRL2_BOOT = 0x10, + CTRL2_BLE = 0x20, + CTRL2_BDU = 0x40, /* Block Data Update */ + CTRL2_FS = 0x80, /* Full Scale selection */ +}; + + +enum lis3lv02d_ctrl3 { + CTRL3_CFS0 = 0x01, + CTRL3_CFS1 = 0x02, + CTRL3_FDS = 0x10, + CTRL3_HPFF = 0x20, + CTRL3_HPDD = 0x40, + CTRL3_ECK = 0x80, +}; + +enum lis3lv02d_status_reg { + STATUS_XDA = 0x01, + STATUS_YDA = 0x02, + STATUS_ZDA = 0x04, + STATUS_XYZDA = 0x08, + STATUS_XOR = 0x10, + STATUS_YOR = 0x20, + STATUS_ZOR = 0x40, + STATUS_XYZOR = 0x80, +}; + +enum lis3lv02d_ff_wu_cfg { + FF_WU_CFG_XLIE = 0x01, + FF_WU_CFG_XHIE = 0x02, + FF_WU_CFG_YLIE = 0x04, + FF_WU_CFG_YHIE = 0x08, + FF_WU_CFG_ZLIE = 0x10, + FF_WU_CFG_ZHIE = 0x20, + FF_WU_CFG_LIR = 0x40, + FF_WU_CFG_AOI = 0x80, +}; + +enum lis3lv02d_ff_wu_src { + FF_WU_SRC_XL = 0x01, + FF_WU_SRC_XH = 0x02, + FF_WU_SRC_YL = 0x04, + FF_WU_SRC_YH = 0x08, + FF_WU_SRC_ZL = 0x10, + FF_WU_SRC_ZH = 0x20, + FF_WU_SRC_IA = 0x40, +}; + +enum lis3lv02d_dd_cfg { + DD_CFG_XLIE = 0x01, + DD_CFG_XHIE = 0x02, + DD_CFG_YLIE = 0x04, + DD_CFG_YHIE = 0x08, + DD_CFG_ZLIE = 0x10, + DD_CFG_ZHIE = 0x20, + DD_CFG_LIR = 0x40, + DD_CFG_IEND = 0x80, +}; + +enum lis3lv02d_dd_src { + DD_SRC_XL = 0x01, + DD_SRC_XH = 0x02, + DD_SRC_YL = 0x04, + DD_SRC_YH = 0x08, + DD_SRC_ZL = 0x10, + DD_SRC_ZH = 0x20, + DD_SRC_IA = 0x40, +}; + diff --git a/drivers/hwmon/lm85.c b/drivers/hwmon/lm85.c index 3ff0285396fa..cfc1ee90f5a3 100644 --- a/drivers/hwmon/lm85.c +++ b/drivers/hwmon/lm85.c @@ -39,7 +39,8 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END }; /* Insmod parameters */ -I2C_CLIENT_INSMOD_6(lm85b, lm85c, adm1027, adt7463, emc6d100, emc6d102); +I2C_CLIENT_INSMOD_7(lm85b, lm85c, adm1027, adt7463, adt7468, emc6d100, + emc6d102); /* The LM85 registers */ @@ -59,6 +60,12 @@ I2C_CLIENT_INSMOD_6(lm85b, lm85c, adm1027, adt7463, emc6d100, emc6d102); #define LM85_REG_COMPANY 0x3e #define LM85_REG_VERSTEP 0x3f + +#define ADT7468_REG_CFG5 0x7c +#define ADT7468_OFF64 0x01 +#define IS_ADT7468_OFF64(data) \ + ((data)->type == adt7468 && !((data)->cfg5 & ADT7468_OFF64)) + /* These are the recognized values for the above regs */ #define LM85_COMPANY_NATIONAL 0x01 #define LM85_COMPANY_ANALOG_DEV 0x41 @@ -70,6 +77,8 @@ I2C_CLIENT_INSMOD_6(lm85b, lm85c, adm1027, adt7463, emc6d100, emc6d102); #define LM85_VERSTEP_ADM1027 0x60 #define LM85_VERSTEP_ADT7463 0x62 #define LM85_VERSTEP_ADT7463C 0x6A +#define LM85_VERSTEP_ADT7468_1 0x71 +#define LM85_VERSTEP_ADT7468_2 0x72 #define LM85_VERSTEP_EMC6D100_A0 0x60 #define LM85_VERSTEP_EMC6D100_A1 0x61 #define LM85_VERSTEP_EMC6D102 0x65 @@ -306,6 +315,7 @@ struct lm85_data { u8 vid; /* Register value */ u8 vrm; /* VRM version */ u32 alarms; /* Register encoding, combined */ + u8 cfg5; /* Config Register 5 on ADT7468 */ struct lm85_autofan autofan[3]; struct lm85_zone zone[3]; }; @@ -685,6 +695,9 @@ static ssize_t set_temp_min(struct device *dev, struct device_attribute *attr, struct lm85_data *data = i2c_get_clientdata(client); long val = simple_strtol(buf, NULL, 10); + if (IS_ADT7468_OFF64(data)) + val += 64; + mutex_lock(&data->update_lock); data->temp_min[nr] = TEMP_TO_REG(val); lm85_write_value(client, LM85_REG_TEMP_MIN(nr), data->temp_min[nr]); @@ -708,6 +721,9 @@ static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr, struct lm85_data *data = i2c_get_clientdata(client); long val = simple_strtol(buf, NULL, 10); + if (IS_ADT7468_OFF64(data)) + val += 64; + mutex_lock(&data->update_lock); data->temp_max[nr] = TEMP_TO_REG(val); lm85_write_value(client, LM85_REG_TEMP_MAX(nr), data->temp_max[nr]); @@ -1163,6 +1179,10 @@ static int lm85_detect(struct i2c_client *client, int kind, case LM85_VERSTEP_ADT7463C: kind = adt7463; break; + case LM85_VERSTEP_ADT7468_1: + case LM85_VERSTEP_ADT7468_2: + kind = adt7468; + break; } } else if (company == LM85_COMPANY_SMSC) { switch (verstep) { @@ -1195,6 +1215,9 @@ static int lm85_detect(struct i2c_client *client, int kind, case adt7463: type_name = "adt7463"; break; + case adt7468: + type_name = "adt7468"; + break; case emc6d100: type_name = "emc6d100"; break; @@ -1246,10 +1269,11 @@ static int lm85_probe(struct i2c_client *client, if (err) goto err_kfree; - /* The ADT7463 has an optional VRM 10 mode where pin 21 is used + /* The ADT7463/68 have an optional VRM 10 mode where pin 21 is used as a sixth digital VID input rather than an analog input. */ data->vid = lm85_read_value(client, LM85_REG_VID); - if (!(data->type == adt7463 && (data->vid & 0x80))) + if (!((data->type == adt7463 || data->type == adt7468) && + (data->vid & 0x80))) if ((err = sysfs_create_group(&client->dev.kobj, &lm85_group_in4))) goto err_remove_files; @@ -1357,7 +1381,8 @@ static struct lm85_data *lm85_update_device(struct device *dev) * There are 2 additional resolution bits per channel and we * have room for 4, so we shift them to the left. */ - if (data->type == adm1027 || data->type == adt7463) { + if (data->type == adm1027 || data->type == adt7463 || + data->type == adt7468) { int ext1 = lm85_read_value(client, ADM1027_REG_EXTEND_ADC1); int ext2 = lm85_read_value(client, @@ -1382,16 +1407,23 @@ static struct lm85_data *lm85_update_device(struct device *dev) lm85_read_value(client, LM85_REG_FAN(i)); } - if (!(data->type == adt7463 && (data->vid & 0x80))) { + if (!((data->type == adt7463 || data->type == adt7468) && + (data->vid & 0x80))) { data->in[4] = lm85_read_value(client, LM85_REG_IN(4)); } + if (data->type == adt7468) + data->cfg5 = lm85_read_value(client, ADT7468_REG_CFG5); + for (i = 0; i <= 2; ++i) { data->temp[i] = lm85_read_value(client, LM85_REG_TEMP(i)); data->pwm[i] = lm85_read_value(client, LM85_REG_PWM(i)); + + if (IS_ADT7468_OFF64(data)) + data->temp[i] -= 64; } data->alarms = lm85_read_value(client, LM85_REG_ALARM1); @@ -1446,7 +1478,8 @@ static struct lm85_data *lm85_update_device(struct device *dev) lm85_read_value(client, LM85_REG_FAN_MIN(i)); } - if (!(data->type == adt7463 && (data->vid & 0x80))) { + if (!((data->type == adt7463 || data->type == adt7468) && + (data->vid & 0x80))) { data->in_min[4] = lm85_read_value(client, LM85_REG_IN_MIN(4)); data->in_max[4] = lm85_read_value(client, @@ -1481,6 +1514,13 @@ static struct lm85_data *lm85_update_device(struct device *dev) lm85_read_value(client, LM85_REG_AFAN_LIMIT(i)); data->zone[i].critical = lm85_read_value(client, LM85_REG_AFAN_CRITICAL(i)); + + if (IS_ADT7468_OFF64(data)) { + data->temp_min[i] -= 64; + data->temp_max[i] -= 64; + data->zone[i].limit -= 64; + data->zone[i].critical -= 64; + } } i = lm85_read_value(client, LM85_REG_AFAN_SPIKE1); diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c index 228f75723063..3fcf78e906db 100644 --- a/drivers/i2c/busses/i2c-cpm.c +++ b/drivers/i2c/busses/i2c-cpm.c @@ -365,6 +365,7 @@ static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) pmsg = &msgs[tptr]; if (pmsg->flags & I2C_M_RD) ret = wait_event_interruptible_timeout(cpm->i2c_wait, + (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) || !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), 1 * HZ); else diff --git a/drivers/i2c/busses/i2c-highlander.c b/drivers/i2c/busses/i2c-highlander.c index f4d22ae9d294..e5a8dae4a289 100644 --- a/drivers/i2c/busses/i2c-highlander.c +++ b/drivers/i2c/busses/i2c-highlander.c @@ -92,7 +92,7 @@ static void highlander_i2c_setup(struct highlander_i2c_dev *dev) static void smbus_write_data(u8 *src, u16 *dst, int len) { for (; len > 1; len -= 2) { - *dst++ = be16_to_cpup((u16 *)src); + *dst++ = be16_to_cpup((__be16 *)src); src += 2; } @@ -103,7 +103,7 @@ static void smbus_write_data(u8 *src, u16 *dst, int len) static void smbus_read_data(u16 *src, u8 *dst, int len) { for (; len > 1; len -= 2) { - *(u16 *)dst = cpu_to_be16p(src++); + *(__be16 *)dst = cpu_to_be16p(src++); dst += 2; } diff --git a/drivers/i2c/busses/i2c-parport.c b/drivers/i2c/busses/i2c-parport.c index 59ba2086d2f9..a257cd5cd134 100644 --- a/drivers/i2c/busses/i2c-parport.c +++ b/drivers/i2c/busses/i2c-parport.c @@ -189,8 +189,6 @@ static void i2c_parport_attach (struct parport *port) if (adapter_parm[type].init.val) line_set(port, 1, &adapter_parm[type].init); - parport_release(adapter->pdev); - if (i2c_bit_add_bus(&adapter->adapter) < 0) { printk(KERN_ERR "i2c-parport: Unable to register with I2C\n"); goto ERROR1; @@ -202,6 +200,7 @@ static void i2c_parport_attach (struct parport *port) return; ERROR1: + parport_release(adapter->pdev); parport_unregister_device(adapter->pdev); ERROR0: kfree(adapter); @@ -221,6 +220,7 @@ static void i2c_parport_detach (struct parport *port) if (adapter_parm[type].init.val) line_set(port, 0, &adapter_parm[type].init); + parport_release(adapter->pdev); parport_unregister_device(adapter->pdev); if (prev) prev->next = adapter->next; diff --git a/drivers/i2c/busses/i2c-pmcmsp.c b/drivers/i2c/busses/i2c-pmcmsp.c index dcf2045b5222..0bdb2d7f0570 100644 --- a/drivers/i2c/busses/i2c-pmcmsp.c +++ b/drivers/i2c/busses/i2c-pmcmsp.c @@ -486,7 +486,7 @@ static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd( if (cmd->type == MSP_TWI_CMD_WRITE || cmd->type == MSP_TWI_CMD_WRITE_READ) { - __be64 tmp = cpu_to_be64p((u64 *)cmd->write_data); + u64 tmp = be64_to_cpup((__be64 *)cmd->write_data); tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8; dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp); pmcmsptwi_writel(tmp & 0x00000000ffffffffLL, diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index c772e02c2803..b7434d24904e 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -56,6 +56,7 @@ enum s3c24xx_i2c_state { struct s3c24xx_i2c { spinlock_t lock; wait_queue_head_t wait; + unsigned int suspended:1; struct i2c_msg *msg; unsigned int msg_num; @@ -507,7 +508,7 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int unsigned long timeout; int ret; - if (!readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN) + if (i2c->suspended) return -EIO; ret = s3c24xx_i2c_set_master(i2c); @@ -986,17 +987,26 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev) } #ifdef CONFIG_PM +static int s3c24xx_i2c_suspend_late(struct platform_device *dev, + pm_message_t msg) +{ + struct s3c24xx_i2c *i2c = platform_get_drvdata(dev); + i2c->suspended = 1; + return 0; +} + static int s3c24xx_i2c_resume(struct platform_device *dev) { struct s3c24xx_i2c *i2c = platform_get_drvdata(dev); - if (i2c != NULL) - s3c24xx_i2c_init(i2c); + i2c->suspended = 0; + s3c24xx_i2c_init(i2c); return 0; } #else +#define s3c24xx_i2c_suspend_late NULL #define s3c24xx_i2c_resume NULL #endif @@ -1005,6 +1015,7 @@ static int s3c24xx_i2c_resume(struct platform_device *dev) static struct platform_driver s3c2410_i2c_driver = { .probe = s3c24xx_i2c_probe, .remove = s3c24xx_i2c_remove, + .suspend_late = s3c24xx_i2c_suspend_late, .resume = s3c24xx_i2c_resume, .driver = { .owner = THIS_MODULE, @@ -1015,6 +1026,7 @@ static struct platform_driver s3c2410_i2c_driver = { static struct platform_driver s3c2440_i2c_driver = { .probe = s3c24xx_i2c_probe, .remove = s3c24xx_i2c_remove, + .suspend_late = s3c24xx_i2c_suspend_late, .resume = s3c24xx_i2c_resume, .driver = { .owner = THIS_MODULE, diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c index 640cbb237328..3384a717fec0 100644 --- a/drivers/i2c/busses/i2c-sh_mobile.c +++ b/drivers/i2c/busses/i2c-sh_mobile.c @@ -318,7 +318,8 @@ static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) } else data = i2c_op(pd, OP_RX, 0); - pd->msg->buf[real_pos] = data; + if (real_pos >= 0) + pd->msg->buf[real_pos] = data; } while (0); pd->pos++; diff --git a/drivers/i2c/busses/scx200_i2c.c b/drivers/i2c/busses/scx200_i2c.c index c3022a023449..e4c98539c517 100644 --- a/drivers/i2c/busses/scx200_i2c.c +++ b/drivers/i2c/busses/scx200_i2c.c @@ -81,6 +81,7 @@ static struct i2c_algo_bit_data scx200_i2c_data = { static struct i2c_adapter scx200_i2c_ops = { .owner = THIS_MODULE, + .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, .id = I2C_HW_B_SCX200, .algo_data = &scx200_i2c_data, .name = "NatSemi SCx200 I2C", diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/i2c/chips/isp1301_omap.c index 28902ebd5539..e0d56ef2bcb0 100644 --- a/drivers/i2c/chips/isp1301_omap.c +++ b/drivers/i2c/chips/isp1301_omap.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,10 @@ #include #include +#include + #include +#include #ifndef DEBUG @@ -88,14 +92,9 @@ struct isp1301 { /*-------------------------------------------------------------------------*/ -#ifdef CONFIG_MACH_OMAP_H2 - /* board-specific PM hooks */ -#include -#include -#include - +#if defined(CONFIG_MACH_OMAP_H2) || defined(CONFIG_MACH_OMAP_H3) #if defined(CONFIG_TPS65010) || defined(CONFIG_TPS65010_MODULE) @@ -133,6 +132,33 @@ static inline void notresponding(struct isp1301 *isp) } +#endif + +#if defined(CONFIG_MACH_OMAP_H4) + +static void enable_vbus_draw(struct isp1301 *isp, unsigned mA) +{ + /* H4 controls this by DIP switch S2.4; no soft control. + * ON means the charger is always enabled. Leave it OFF + * unless the OTG port is used only in B-peripheral mode. + */ +} + +static void enable_vbus_source(struct isp1301 *isp) +{ + /* this board won't supply more than 8mA vbus power. + * some boards can switch a 100ma "unit load" (or more). + */ +} + + +/* products will deliver OTG messages with LEDs, GUI, etc */ +static inline void notresponding(struct isp1301 *isp) +{ + printk(KERN_NOTICE "OTG device not responding.\n"); +} + + #endif /*-------------------------------------------------------------------------*/ @@ -334,8 +360,7 @@ static int gadget_suspend(struct isp1301 *isp) * NOTE: guaranteeing certain response times might mean we shouldn't * share keventd's work queue; a realtime task might be safest. */ -void -isp1301_defer_work(struct isp1301 *isp, int work) +static void isp1301_defer_work(struct isp1301 *isp, int work) { int status; @@ -512,7 +537,6 @@ static void update_otg1(struct isp1301 *isp, u8 int_src) otg_ctrl &= ~OTG_XCEIV_INPUTS; otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD); - if (int_src & INTR_SESS_VLD) otg_ctrl |= OTG_ASESSVLD; else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) { @@ -886,11 +910,11 @@ static int otg_probe(struct platform_device *dev) static int otg_remove(struct platform_device *dev) { - otg_dev = 0; + otg_dev = NULL; return 0; } -struct platform_driver omap_otg_driver = { +static struct platform_driver omap_otg_driver = { .probe = otg_probe, .remove = otg_remove, .driver = { @@ -1212,6 +1236,8 @@ static void isp1301_release(struct device *dev) isp = dev_get_drvdata(dev); + /* FIXME -- not with a "new style" driver, it doesn't!! */ + /* ugly -- i2c hijacks our memory hook to wait_for_completion() */ if (isp->i2c_release) isp->i2c_release(dev); @@ -1233,7 +1259,7 @@ static int __exit isp1301_remove(struct i2c_client *i2c) otg_unbind(isp); #endif if (machine_is_omap_h2()) - omap_free_gpio(2); + gpio_free(2); isp->timer.data = 0; set_bit(WORK_STOP, &isp->todo); @@ -1241,7 +1267,7 @@ static int __exit isp1301_remove(struct i2c_client *i2c) flush_scheduled_work(); put_device(&i2c->dev); - the_transceiver = 0; + the_transceiver = NULL; return 0; } @@ -1295,7 +1321,7 @@ isp1301_set_host(struct otg_transceiver *otg, struct usb_bus *host) if (!host) { omap_writew(0, OTG_IRQ_EN); power_down(isp); - isp->otg.host = 0; + isp->otg.host = NULL; return 0; } @@ -1344,7 +1370,9 @@ static int isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) { struct isp1301 *isp = container_of(otg, struct isp1301, otg); +#ifndef CONFIG_USB_OTG u32 l; +#endif if (!otg || isp != the_transceiver) return -ENODEV; @@ -1354,7 +1382,7 @@ isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) if (!isp->otg.default_a) enable_vbus_draw(isp, 0); usb_gadget_vbus_disconnect(isp->otg.gadget); - isp->otg.gadget = 0; + isp->otg.gadget = NULL; power_down(isp); return 0; } @@ -1379,7 +1407,7 @@ isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) power_up(isp); isp->otg.state = OTG_STATE_B_IDLE; - if (machine_is_omap_h2()) + if (machine_is_omap_h2() || machine_is_omap_h3()) isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0); isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING, @@ -1499,7 +1527,8 @@ isp1301_start_hnp(struct otg_transceiver *dev) /*-------------------------------------------------------------------------*/ -static int __init isp1301_probe(struct i2c_client *i2c) +static int __init +isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { int status; struct isp1301 *isp; @@ -1647,7 +1676,7 @@ module_init(isp_init); static void __exit isp_exit(void) { if (the_transceiver) - otg_set_transceiver(0); + otg_set_transceiver(NULL); i2c_del_driver(&isp1301_driver); } module_exit(isp_exit); diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c index 5a485c22660a..c6a63f46bc15 100644 --- a/drivers/i2c/i2c-core.c +++ b/drivers/i2c/i2c-core.c @@ -631,7 +631,7 @@ int i2c_del_adapter(struct i2c_adapter *adap) /* detach any active clients. This must be done first, because * it can fail; in which case we give up. */ - list_for_each_entry_safe(client, _n, &adap->clients, list) { + list_for_each_entry_safe_reverse(client, _n, &adap->clients, list) { struct i2c_driver *driver; driver = client->driver; diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index 6d7401772a8f..e6857e01d1ba 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -669,10 +669,12 @@ config BLK_DEV_CELLEB endif +# TODO: BLK_DEV_IDEDMA_PCI -> BLK_DEV_IDEDMA_SFF config BLK_DEV_IDE_PMAC tristate "PowerMac on-board IDE support" depends on PPC_PMAC && IDE=y select IDE_TIMINGS + select BLK_DEV_IDEDMA_PCI help This driver provides support for the on-board IDE controller on most of the recent Apple Power Macintoshes and PowerBooks. @@ -689,16 +691,6 @@ config BLK_DEV_IDE_PMAC_ATA100FIRST CD-ROM on hda. This option changes this to more natural hda for hard disk and hdc for CD-ROM. -config BLK_DEV_IDEDMA_PMAC - bool "PowerMac IDE DMA support" - depends on BLK_DEV_IDE_PMAC - select BLK_DEV_IDEDMA_PCI - help - This option allows the driver for the on-board IDE controller on - Power Macintoshes and PowerBooks to use DMA (direct memory access) - to transfer data to and from memory. Saying Y is safe and improves - performance. - config BLK_DEV_IDE_AU1XXX bool "IDE for AMD Alchemy Au1200" depends on SOC_AU1200 @@ -912,7 +904,7 @@ config BLK_DEV_UMC8672 endif config BLK_DEV_IDEDMA - def_bool BLK_DEV_IDEDMA_SFF || BLK_DEV_IDEDMA_PMAC || \ + def_bool BLK_DEV_IDEDMA_SFF || \ BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA endif # IDE diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index daf9dce39e52..45d2356bb725 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -5,7 +5,7 @@ * * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org) * May be copied or modified under the terms of the GNU General Public License - * Copyright (C) 2002 Alan Cox + * Copyright (C) 2002 Alan Cox * ALi (now ULi M5228) support by Clear Zhang * Copyright (C) 2007 MontaVista Software, Inc. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz @@ -591,7 +591,7 @@ static int __init ali15x3_ide_init(void) static void __exit ali15x3_ide_exit(void) { - return pci_unregister_driver(&alim15x3_pci_driver); + pci_unregister_driver(&alim15x3_pci_driver); } module_init(ali15x3_ide_init); diff --git a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c index 81ec73134eda..c6bcd3014a29 100644 --- a/drivers/ide/amd74xx.c +++ b/drivers/ide/amd74xx.c @@ -3,7 +3,7 @@ * IDE driver for Linux. * * Copyright (c) 2000-2002 Vojtech Pavlik - * Copyright (c) 2007 Bartlomiej Zolnierkiewicz + * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz * * Based on the work of: * Andre Hedrick @@ -263,6 +263,15 @@ static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_ d.udma_mask = ATA_UDMA5; } + /* + * It seems that on some nVidia controllers using AltStatus + * register can be unreliable so default to Status register + * if the device is in Compatibility Mode. + */ + if (dev->vendor == PCI_VENDOR_ID_NVIDIA && + ide_pci_is_in_compatibility_mode(dev)) + d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS; + printk(KERN_INFO "%s %s: UDMA%s controller\n", d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]); diff --git a/drivers/ide/hpt366.c b/drivers/ide/hpt366.c index a7909e9c720e..f5afd46ed51c 100644 --- a/drivers/ide/hpt366.c +++ b/drivers/ide/hpt366.c @@ -52,7 +52,7 @@ * different clocks on read/write. This requires overloading rw_disk and * other deeply crazy things. Thanks to for * keeping me sane. - * Alan Cox + * Alan Cox * * - fix the clock turnaround code: it was writing to the wrong ports when * called for the secondary channel, caching the current clock mode per- diff --git a/drivers/ide/icside.c b/drivers/ide/icside.c index 2d848010499d..81f70caeb40f 100644 --- a/drivers/ide/icside.c +++ b/drivers/ide/icside.c @@ -419,7 +419,7 @@ static void icside_setup_ports(hw_regs_t *hw, void __iomem *base, hw->chipset = ide_acorn; } -static int __init +static int __devinit icside_register_v5(struct icside_state *state, struct expansion_card *ec) { void __iomem *base; @@ -473,7 +473,7 @@ static const struct ide_port_info icside_v6_port_info __initdata = { .swdma_mask = ATA_SWDMA2, }; -static int __init +static int __devinit icside_register_v6(struct icside_state *state, struct expansion_card *ec) { void __iomem *ioc_base, *easi_base; diff --git a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c index 48b5eda3ab41..42ab6d8715f2 100644 --- a/drivers/ide/ide-cd.c +++ b/drivers/ide/ide-cd.c @@ -1250,7 +1250,8 @@ static void cdrom_do_block_pc(ide_drive_t *drive, struct request *rq) * separate masks. */ alignment = queue_dma_alignment(q) | q->dma_pad_mask; - if ((unsigned long)buf & alignment || rq->data_len & alignment + if ((unsigned long)buf & alignment + || rq->data_len & q->dma_pad_mask || object_is_on_stack(buf)) drive->dma = 0; } diff --git a/drivers/ide/ide-cs.c b/drivers/ide/ide-cs.c index cb199c815b53..f50210fe558f 100644 --- a/drivers/ide/ide-cs.c +++ b/drivers/ide/ide-cs.c @@ -444,6 +444,7 @@ static struct pcmcia_device_id ide_ids[] = { PCMCIA_DEVICE_PROD_ID1("STI Flash", 0xe4a13209), PCMCIA_DEVICE_PROD_ID12("STI", "Flash 5.0", 0xbf2df18d, 0x8cb57a0e), PCMCIA_MFC_DEVICE_PROD_ID12(1, "SanDisk", "ConnectPlus", 0x7a954bd9, 0x74be00c6), + PCMCIA_DEVICE_PROD_ID2("Flash Card", 0x5a362506), PCMCIA_DEVICE_NULL, }; MODULE_DEVICE_TABLE(pcmcia, ide_ids); diff --git a/drivers/ide/ide-disk.c b/drivers/ide/ide-disk.c index e5adebe8ac2c..eb9fac4d0f0c 100644 --- a/drivers/ide/ide-disk.c +++ b/drivers/ide/ide-disk.c @@ -2,7 +2,7 @@ * Copyright (C) 1994-1998 Linus Torvalds & authors (see below) * Copyright (C) 1998-2002 Linux ATA Development * Andre Hedrick - * Copyright (C) 2003 Red Hat + * Copyright (C) 2003 Red Hat * Copyright (C) 2003-2005, 2007 Bartlomiej Zolnierkiewicz */ diff --git a/drivers/ide/ide-gd.c b/drivers/ide/ide-gd.c index 7b6662854374..b8078b3231f7 100644 --- a/drivers/ide/ide-gd.c +++ b/drivers/ide/ide-gd.c @@ -281,7 +281,12 @@ static int ide_gd_media_changed(struct gendisk *disk) static int ide_gd_revalidate_disk(struct gendisk *disk) { struct ide_disk_obj *idkp = ide_drv_g(disk, ide_disk_obj); - set_capacity(disk, ide_gd_capacity(idkp->drive)); + ide_drive_t *drive = idkp->drive; + + if (ide_gd_media_changed(disk)) + drive->disk_ops->get_capacity(drive); + + set_capacity(disk, ide_gd_capacity(drive)); return 0; } diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index 7162d67562af..cc35d6dbd410 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -132,10 +132,14 @@ int ide_end_request (ide_drive_t *drive, int uptodate, int nr_sectors) } EXPORT_SYMBOL(ide_end_request); -static void ide_complete_power_step(ide_drive_t *drive, struct request *rq, u8 stat, u8 error) +static void ide_complete_power_step(ide_drive_t *drive, struct request *rq) { struct request_pm_state *pm = rq->data; +#ifdef DEBUG_PM + printk(KERN_INFO "%s: complete_power_step(step: %d)\n", + drive->name, pm->pm_step); +#endif if (drive->media != ide_disk) return; @@ -172,7 +176,7 @@ static ide_startstop_t ide_start_power_step(ide_drive_t *drive, struct request * /* Not supported? Switch to next step now. */ if (ata_id_flush_enabled(drive->id) == 0 || (drive->dev_flags & IDE_DFLAG_WCACHE) == 0) { - ide_complete_power_step(drive, rq, 0, 0); + ide_complete_power_step(drive, rq); return ide_stopped; } if (ata_id_flush_ext_enabled(drive->id)) @@ -191,7 +195,7 @@ static ide_startstop_t ide_start_power_step(ide_drive_t *drive, struct request * if (drive->media != ide_disk) pm->pm_step = IDE_PM_RESTORE_DMA; else - ide_complete_power_step(drive, rq, 0, 0); + ide_complete_power_step(drive, rq); return ide_stopped; case IDE_PM_IDLE: /* Resume step 2 (idle) */ args->tf.command = ATA_CMD_IDLEIMMEDIATE; @@ -322,11 +326,8 @@ void ide_end_drive_cmd (ide_drive_t *drive, u8 stat, u8 err) } } else if (blk_pm_request(rq)) { struct request_pm_state *pm = rq->data; -#ifdef DEBUG_PM - printk("%s: complete_power_step(step: %d, stat: %x, err: %x)\n", - drive->name, rq->pm->pm_step, stat, err); -#endif - ide_complete_power_step(drive, rq, stat, err); + + ide_complete_power_step(drive, rq); if (pm->pm_step == IDE_PM_COMPLETED) ide_complete_pm_request(drive, rq); return; @@ -804,7 +805,7 @@ static ide_startstop_t start_request (ide_drive_t *drive, struct request *rq) struct request_pm_state *pm = rq->data; #ifdef DEBUG_PM printk("%s: start_power_step(step: %d)\n", - drive->name, rq->pm->pm_step); + drive->name, pm->pm_step); #endif startstop = ide_start_power_step(drive, rq); if (startstop == ide_stopped && @@ -967,14 +968,13 @@ static void ide_do_request (ide_hwgroup_t *hwgroup, int masked_irq) ide_startstop_t startstop; int loops = 0; - /* for atari only: POSSIBLY BROKEN HERE(?) */ - ide_get_lock(ide_intr, hwgroup); - /* caller must own ide_lock */ BUG_ON(!irqs_disabled()); while (!hwgroup->busy) { hwgroup->busy = 1; + /* for atari only */ + ide_get_lock(ide_intr, hwgroup); drive = choose_drive(hwgroup); if (drive == NULL) { int sleeping = 0; diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c index bb7a1ed8094e..c41c3b9b6f02 100644 --- a/drivers/ide/ide-iops.c +++ b/drivers/ide/ide-iops.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2000-2002 Andre Hedrick - * Copyright (C) 2003 Red Hat + * Copyright (C) 2003 Red Hat * */ @@ -457,18 +457,14 @@ int drive_is_ready (ide_drive_t *drive) if (drive->waiting_for_dma) return hwif->dma_ops->dma_test_irq(drive); -#if 0 - /* need to guarantee 400ns since last command was issued */ - udelay(1); -#endif - /* * We do a passive status test under shared PCI interrupts on * cards that truly share the ATA side interrupt, but may also share * an interrupt with another pci card/device. We make no assumptions * about possible isa-pnp and pci-pnp issues yet. */ - if (hwif->io_ports.ctl_addr) + if (hwif->io_ports.ctl_addr && + (hwif->host_flags & IDE_HFLAG_BROKEN_ALTSTATUS) == 0) stat = hwif->tp_ops->read_altstatus(hwif); else /* Note: this may clear a pending IRQ!! */ @@ -610,6 +606,7 @@ static const struct drive_list_entry ivb_list[] = { { "TSSTcorp CDDVDW SH-S202N" , "SB01" }, { "TSSTcorp CDDVDW SH-S202H" , "SB00" }, { "TSSTcorp CDDVDW SH-S202H" , "SB01" }, + { "SAMSUNG SP0822N" , "WA100-10" }, { NULL , NULL } }; diff --git a/drivers/ide/ide-pci-generic.c b/drivers/ide/ide-pci-generic.c index 474f96a7c076..bddae2b329a0 100644 --- a/drivers/ide/ide-pci-generic.c +++ b/drivers/ide/ide-pci-generic.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2001-2002 Andre Hedrick - * Portions (C) Copyright 2002 Red Hat Inc + * Portions (C) Copyright 2002 Red Hat Inc * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c index 1649ea54f76c..c55bdbd22314 100644 --- a/drivers/ide/ide-probe.c +++ b/drivers/ide/ide-probe.c @@ -266,7 +266,8 @@ static int actual_try_to_identify (ide_drive_t *drive, u8 cmd) /* take a deep breath */ msleep(50); - if (io_ports->ctl_addr) { + if (io_ports->ctl_addr && + (hwif->host_flags & IDE_HFLAG_BROKEN_ALTSTATUS) == 0) { a = tp_ops->read_altstatus(hwif); s = tp_ops->read_status(hwif); if ((a ^ s) & ~ATA_IDX) diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c index c31d0dd7a532..f3cddd1b2f8f 100644 --- a/drivers/ide/ide-proc.c +++ b/drivers/ide/ide-proc.c @@ -1,6 +1,6 @@ /* * Copyright (C) 1997-1998 Mark Lord - * Copyright (C) 2003 Red Hat + * Copyright (C) 2003 Red Hat * * Some code was moved here from ide.c, see it for original copyrights. */ diff --git a/drivers/ide/it821x.c b/drivers/ide/it821x.c index 995e18bb3139..ef004089761b 100644 --- a/drivers/ide/it821x.c +++ b/drivers/ide/it821x.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Red Hat + * Copyright (C) 2004 Red Hat * Copyright (C) 2007 Bartlomiej Zolnierkiewicz * * May be copied or modified under the terms of the GNU General Public License diff --git a/drivers/ide/jmicron.c b/drivers/ide/jmicron.c index 9a68433cf46d..bf2be6431b20 100644 --- a/drivers/ide/jmicron.c +++ b/drivers/ide/jmicron.c @@ -1,6 +1,6 @@ /* - * Copyright (C) 2006 Red Hat + * Copyright (C) 2006 Red Hat * * May be copied or modified under the terms of the GNU General Public License */ diff --git a/drivers/ide/piix.c b/drivers/ide/piix.c index d63f9fdca76b..61d2d920a5cd 100644 --- a/drivers/ide/piix.c +++ b/drivers/ide/piix.c @@ -1,7 +1,7 @@ /* * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer * Copyright (C) 1998-2000 Andre Hedrick - * Copyright (C) 2003 Red Hat Inc + * Copyright (C) 2003 Red Hat * Copyright (C) 2006-2007 MontaVista Software, Inc. * * May be copied or modified under the terms of the GNU General Public License diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c index 2e19d6298536..7c481bb56fab 100644 --- a/drivers/ide/pmac.c +++ b/drivers/ide/pmac.c @@ -66,7 +66,6 @@ typedef struct pmac_ide_hwif { struct macio_dev *mdev; u32 timings[4]; volatile u32 __iomem * *kauai_fcr; -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC /* Those fields are duplicating what is in hwif. We currently * can't use the hwif ones because of some assumptions that are * beeing done by the generic code about the kind of dma controller @@ -74,8 +73,6 @@ typedef struct pmac_ide_hwif { */ volatile struct dbdma_regs __iomem * dma_regs; struct dbdma_cmd* dma_table_cpu; -#endif - } pmac_ide_hwif_t; enum { @@ -222,8 +219,6 @@ static const char* model_name[] = { #define KAUAI_FCR_UATA_RESET_N 0x00000002 #define KAUAI_FCR_UATA_ENABLE 0x00000001 -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC - /* Rounded Multiword DMA timings * * I gave up finding a generic formula for all controller @@ -413,8 +408,6 @@ static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq); static void pmac_ide_selectproc(ide_drive_t *drive); static void pmac_ide_kauai_selectproc(ide_drive_t *drive); -#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ - #define PMAC_IDE_REG(x) \ ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) @@ -584,8 +577,6 @@ pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) pmac_ide_do_update_timings(drive); } -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC - /* * Calculate KeyLargo ATA/66 UDMA timings */ @@ -786,7 +777,6 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, drive->name, speed & 0xf, *timings); #endif } -#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */ static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) { @@ -804,7 +794,6 @@ static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) tl[0] = *timings; tl[1] = *timings2; -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC if (speed >= XFER_UDMA_0) { if (pmif->kind == controller_kl_ata4) ret = set_timings_udma_ata4(&tl[0], speed); @@ -817,7 +806,7 @@ static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) ret = -1; } else set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); -#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ + if (ret) return; @@ -1008,9 +997,7 @@ static const struct ide_port_info pmac_port_info = { .chipset = ide_pmac, .tp_ops = &pmac_tp_ops, .port_ops = &pmac_ide_port_ops, -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC .dma_ops = &pmac_dma_ops, -#endif .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_MMIO | @@ -1182,7 +1169,7 @@ pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) pmif->regbase = regbase; pmif->irq = irq; pmif->kauai_fcr = NULL; -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC + if (macio_resource_count(mdev) >= 2) { if (macio_request_resource(mdev, 1, "ide-pmac (dma)")) printk(KERN_WARNING "ide-pmac: can't request DMA " @@ -1192,7 +1179,7 @@ pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000); } else pmif->dma_regs = NULL; -#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ + dev_set_drvdata(&mdev->ofdev.dev, pmif); memset(&hw, 0, sizeof(hw)); @@ -1300,9 +1287,7 @@ pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) base = ioremap(rbase, rlen); pmif->regbase = (unsigned long) base + 0x2000; -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC pmif->dma_regs = base + 0x1000; -#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ pmif->kauai_fcr = base; pmif->irq = pdev->irq; @@ -1434,8 +1419,6 @@ out: return error; } -#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC - /* * pmac_ide_build_dmatable builds the DBDMA command list * for a transfer and sets the DBDMA channel to point to it. @@ -1723,13 +1706,6 @@ static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, return 0; } -#else -static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif, - const struct ide_port_info *d) -{ - return -EOPNOTSUPP; -} -#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ module_init(pmac_ide_probe); diff --git a/drivers/ide/scc_pata.c b/drivers/ide/scc_pata.c index f26aa5d54efb..0f48f9dacfa5 100644 --- a/drivers/ide/scc_pata.c +++ b/drivers/ide/scc_pata.c @@ -5,7 +5,7 @@ * * This code is based on drivers/ide/pci/siimage.c: * Copyright (C) 2001-2002 Andre Hedrick - * Copyright (C) 2003 Red Hat + * Copyright (C) 2003 Red Hat * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/ide/sgiioc4.c b/drivers/ide/sgiioc4.c index 7defa0ae2014..a687a7dfea6f 100644 --- a/drivers/ide/sgiioc4.c +++ b/drivers/ide/sgiioc4.c @@ -550,7 +550,7 @@ static const struct ide_dma_ops sgiioc4_dma_ops = { .dma_timeout = ide_dma_timeout, }; -static const struct ide_port_info sgiioc4_port_info __devinitdata = { +static const struct ide_port_info sgiioc4_port_info __devinitconst = { .name = DRV_NAME, .chipset = ide_pci, .init_dma = ide_dma_sgiioc4, @@ -633,7 +633,7 @@ out: return ret; } -int +int __devinit ioc4_ide_attach_one(struct ioc4_driver_data *idd) { /* PCI-RT does not bring out IDE connection. @@ -645,7 +645,7 @@ ioc4_ide_attach_one(struct ioc4_driver_data *idd) return pci_init_sgiioc4(idd->idd_pdev); } -static struct ioc4_submodule ioc4_ide_submodule = { +static struct ioc4_submodule __devinitdata ioc4_ide_submodule = { .is_name = "IOC4_ide", .is_owner = THIS_MODULE, .is_probe = ioc4_ide_attach_one, diff --git a/drivers/ide/siimage.c b/drivers/ide/siimage.c index c3107df7773d..7d622d20bc4c 100644 --- a/drivers/ide/siimage.c +++ b/drivers/ide/siimage.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2001-2002 Andre Hedrick - * Copyright (C) 2003 Red Hat + * Copyright (C) 2003 Red Hat * Copyright (C) 2007-2008 MontaVista Software, Inc. * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz * diff --git a/drivers/ide/tx4938ide.c b/drivers/ide/tx4938ide.c index fa660f931a11..9120063e8f87 100644 --- a/drivers/ide/tx4938ide.c +++ b/drivers/ide/tx4938ide.c @@ -26,12 +26,13 @@ static void tx4938ide_tune_ebusc(unsigned int ebus_ch, unsigned int sp = (cr >> 4) & 3; unsigned int clock = gbus_clock / (4 - sp); unsigned int cycle = 1000000000 / clock; - unsigned int wt, shwt; + unsigned int shwt; + int wt; /* Minimum DIOx- active time */ wt = DIV_ROUND_UP(t->act8b, cycle) - 2; /* IORDY setup time: 35ns */ - wt = max(wt, DIV_ROUND_UP(35, cycle)); + wt = max_t(int, wt, DIV_ROUND_UP(35, cycle)); /* actual wait-cycle is max(wt & ~1, 1) */ if (wt > 2 && (wt & 1)) wt++; @@ -39,10 +40,17 @@ static void tx4938ide_tune_ebusc(unsigned int ebus_ch, /* Address-valid to DIOR/DIOW setup */ shwt = DIV_ROUND_UP(t->setup, cycle); + /* -DIOx recovery time (SHWT * 4) and cycle time requirement */ + while ((shwt * 4 + wt + (wt ? 2 : 3)) * cycle < t->cycle) + shwt++; + if (shwt > 7) { + pr_warning("tx4938ide: SHWT violation (%d)\n", shwt); + shwt = 7; + } pr_debug("tx4938ide: ebus %d, bus cycle %dns, WT %d, SHWT %d\n", ebus_ch, cycle, wt, shwt); - __raw_writeq((cr & ~(0x3f007ull)) | (wt << 12) | shwt, + __raw_writeq((cr & ~0x3f007ull) | (wt << 12) | shwt, &tx4938_ebuscptr->cr[ebus_ch]); } @@ -228,7 +236,7 @@ static int __init tx4938ide_probe(struct platform_device *pdev) struct resource *res; struct tx4938ide_platform_info *pdata = pdev->dev.platform_data; int irq, ret, i; - unsigned long mapbase; + unsigned long mapbase, mapctl; struct ide_port_info d = tx4938ide_port_info; irq = platform_get_irq(pdev, 0); @@ -242,38 +250,43 @@ static int __init tx4938ide_probe(struct platform_device *pdev) res->end - res->start + 1, "tx4938ide")) return -EBUSY; mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start, - res->end - res->start + 1); - if (!mapbase) + 8 << pdata->ioport_shift); + mapctl = (unsigned long)devm_ioremap(&pdev->dev, + res->start + 0x10000 + + (6 << pdata->ioport_shift), + 1 << pdata->ioport_shift); + if (!mapbase || !mapctl) return -EBUSY; memset(&hw, 0, sizeof(hw)); if (pdata->ioport_shift) { unsigned long port = mapbase; + unsigned long ctl = mapctl; hw.io_ports_array[0] = port; #ifdef __BIG_ENDIAN port++; + ctl++; #endif for (i = 1; i <= 7; i++) hw.io_ports_array[i] = port + (i << pdata->ioport_shift); - hw.io_ports.ctl_addr = - port + 0x10000 + (6 << pdata->ioport_shift); + hw.io_ports.ctl_addr = ctl; } else - ide_std_init_ports(&hw, mapbase, mapbase + 0x10006); + ide_std_init_ports(&hw, mapbase, mapctl); hw.irq = irq; hw.dev = &pdev->dev; - pr_info("TX4938 IDE interface (base %#lx, irq %d)\n", mapbase, hw.irq); + pr_info("TX4938 IDE interface (base %#lx, ctl %#lx, irq %d)\n", + mapbase, mapctl, hw.irq); if (pdata->gbus_clock) tx4938ide_tune_ebusc(pdata->ebus_ch, pdata->gbus_clock, 0); else d.port_ops = NULL; ret = ide_host_add(&d, hws, &host); - if (ret) - return ret; - platform_set_drvdata(pdev, host); - return 0; + if (!ret) + platform_set_drvdata(pdev, host); + return ret; } static int __exit tx4938ide_remove(struct platform_device *pdev) diff --git a/drivers/idle/Kconfig b/drivers/idle/Kconfig index f5b26dd579e4..f15e90a453d1 100644 --- a/drivers/idle/Kconfig +++ b/drivers/idle/Kconfig @@ -1,16 +1,18 @@ menu "Memory power savings" +depends on X86_64 config I7300_IDLE_IOAT_CHANNEL bool config I7300_IDLE - tristate "Intel chipset idle power saving driver" + tristate "Intel chipset idle memory power saving driver" select I7300_IDLE_IOAT_CHANNEL - depends on X86_64 + depends on EXPERIMENTAL help - Enable idle power savings with certain Intel server chipsets. - The chipset must have I/O AT support, such as the Intel 7300. - The power savings depends on the type and quantity of DRAM devices. + Enable memory power savings when idle with certain Intel server + chipsets. The chipset must have I/O AT support, such as the + Intel 7300. The power savings depends on the type and quantity of + DRAM devices. endmenu diff --git a/drivers/idle/i7300_idle.c b/drivers/idle/i7300_idle.c index 59d1bbc3cd3c..fb176f6ef9f8 100644 --- a/drivers/idle/i7300_idle.c +++ b/drivers/idle/i7300_idle.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -34,6 +35,8 @@ #define I7300_IDLE_DRIVER_VERSION "1.55" #define I7300_PRINT "i7300_idle:" +#define MAX_STOP_RETRIES 10 + static int debug; module_param_named(debug, debug, uint, 0644); MODULE_PARM_DESC(debug, "Enable debug printks in this driver"); @@ -46,12 +49,12 @@ MODULE_PARM_DESC(debug, "Enable debug printks in this driver"); * 0 = No throttling * 1 = Throttle when > 4 activations per eval window (Maximum throttling) * 2 = Throttle when > 8 activations - * 168 = Throttle when > 168 activations (Minimum throttling) + * 168 = Throttle when > 672 activations (Minimum throttling) */ -#define MAX_THRTLWLIMIT 168 -static uint i7300_idle_thrtlowlm = 1; -module_param_named(thrtlwlimit, i7300_idle_thrtlowlm, uint, 0644); -MODULE_PARM_DESC(thrtlwlimit, +#define MAX_THROTTLE_LOW_LIMIT 168 +static uint throttle_low_limit = 1; +module_param_named(throttle_low_limit, throttle_low_limit, uint, 0644); +MODULE_PARM_DESC(throttle_low_limit, "Value for THRTLOWLM activation field " "(0 = disable throttle, 1 = Max throttle, 168 = Min throttle)"); @@ -110,9 +113,9 @@ static int i7300_idle_ioat_start(void) static void i7300_idle_ioat_stop(void) { int i; - u8 sts; + u64 sts; - for (i = 0; i < 5; i++) { + for (i = 0; i < MAX_STOP_RETRIES; i++) { writeb(IOAT_CHANCMD_RESET, ioat_chanbase + IOAT1_CHANCMD_OFFSET); @@ -126,9 +129,10 @@ static void i7300_idle_ioat_stop(void) } - if (i == 5) - dprintk("failed to suspend+reset I/O AT after 5 retries\n"); - + if (i == MAX_STOP_RETRIES) { + dprintk("failed to stop I/O AT after %d retries\n", + MAX_STOP_RETRIES); + } } /* Test I/O AT by copying 1024 byte from 2k to 1k */ @@ -275,7 +279,7 @@ static void __exit i7300_idle_ioat_exit(void) i7300_idle_ioat_stop(); /* Wait for a while for the channel to halt before releasing */ - for (i = 0; i < 10; i++) { + for (i = 0; i < MAX_STOP_RETRIES; i++) { writeb(IOAT_CHANCMD_RESET, ioat_chanbase + IOAT1_CHANCMD_OFFSET); @@ -389,9 +393,9 @@ static void i7300_idle_start(void) new_ctl = i7300_idle_thrtctl_saved & ~DIMM_THRTCTL_THRMHUNT; pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl); - limit = i7300_idle_thrtlowlm; - if (unlikely(limit > MAX_THRTLWLIMIT)) - limit = MAX_THRTLWLIMIT; + limit = throttle_low_limit; + if (unlikely(limit > MAX_THROTTLE_LOW_LIMIT)) + limit = MAX_THROTTLE_LOW_LIMIT; pci_write_config_byte(fbd_dev, DIMM_THRTLOW, limit); @@ -440,7 +444,7 @@ static int i7300_idle_notifier(struct notifier_block *nb, unsigned long val, static ktime_t idle_begin_time; static int time_init = 1; - if (!i7300_idle_thrtlowlm) + if (!throttle_low_limit) return 0; if (unlikely(time_init)) { @@ -505,77 +509,8 @@ static struct notifier_block i7300_idle_nb = { .notifier_call = i7300_idle_notifier, }; -/* - * I/O AT controls (PCI bus 0 device 8 function 0) - * DIMM controls (PCI bus 0 device 16 function 1) - */ -#define IOAT_BUS 0 -#define IOAT_DEVFN PCI_DEVFN(8, 0) -#define MEMCTL_BUS 0 -#define MEMCTL_DEVFN PCI_DEVFN(16, 1) - -struct fbd_ioat { - unsigned int vendor; - unsigned int ioat_dev; -}; - -/* - * The i5000 chip-set has the same hooks as the i7300 - * but support is disabled by default because this driver - * has not been validated on that platform. - */ -#define SUPPORT_I5000 0 - -static const struct fbd_ioat fbd_ioat_list[] = { - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB}, -#if SUPPORT_I5000 - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT}, -#endif - {0, 0} -}; - -/* table of devices that work with this driver */ -static const struct pci_device_id pci_tbl[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FBD_CNB) }, -#if SUPPORT_I5000 - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5000_ERR) }, -#endif - { } /* Terminating entry */ -}; - MODULE_DEVICE_TABLE(pci, pci_tbl); -/* Check for known platforms with I/O-AT */ -static int __init i7300_idle_platform_probe(void) -{ - int i; - - fbd_dev = pci_get_bus_and_slot(MEMCTL_BUS, MEMCTL_DEVFN); - if (!fbd_dev) - return -ENODEV; - - for (i = 0; pci_tbl[i].vendor != 0; i++) { - if (fbd_dev->vendor == pci_tbl[i].vendor && - fbd_dev->device == pci_tbl[i].device) { - break; - } - } - if (pci_tbl[i].vendor == 0) - return -ENODEV; - - ioat_dev = pci_get_bus_and_slot(IOAT_BUS, IOAT_DEVFN); - if (!ioat_dev) - return -ENODEV; - - for (i = 0; fbd_ioat_list[i].vendor != 0; i++) { - if (ioat_dev->vendor == fbd_ioat_list[i].vendor && - ioat_dev->device == fbd_ioat_list[i].ioat_dev) { - return 0; - } - } - return -ENODEV; -} - int stats_open_generic(struct inode *inode, struct file *fp) { fp->private_data = inode->i_private; @@ -617,7 +552,7 @@ static int __init i7300_idle_init(void) cpus_clear(idle_cpumask); total_us = 0; - if (i7300_idle_platform_probe()) + if (i7300_idle_platform_probe(&fbd_dev, &ioat_dev)) return -ENODEV; if (i7300_idle_thrt_save()) diff --git a/drivers/ieee1394/dv1394.c b/drivers/ieee1394/dv1394.c index 2f83543a9dfc..c19f23267157 100644 --- a/drivers/ieee1394/dv1394.c +++ b/drivers/ieee1394/dv1394.c @@ -1270,8 +1270,14 @@ static int dv1394_mmap(struct file *file, struct vm_area_struct *vma) struct video_card *video = file_to_video_card(file); int retval = -EINVAL; - /* serialize mmap */ - mutex_lock(&video->mtx); + /* + * We cannot use the blocking variant mutex_lock here because .mmap + * is called with mmap_sem held, while .ioctl, .read, .write acquire + * video->mtx and subsequently call copy_to/from_user which will + * grab mmap_sem in case of a page fault. + */ + if (!mutex_trylock(&video->mtx)) + return -EAGAIN; if ( ! video_card_initialized(video) ) { retval = do_dv1394_init_default(video); @@ -1828,9 +1834,6 @@ static int dv1394_release(struct inode *inode, struct file *file) /* OK to free the DMA buffer, no more mappings can exist */ do_dv1394_shutdown(video, 1); - /* clean up async I/O users */ - dv1394_fasync(-1, file, 0); - /* give someone else a turn */ clear_bit(0, &video->open); diff --git a/drivers/ieee1394/highlevel.c b/drivers/ieee1394/highlevel.c index 918ffc4fc8ac..272543a42a43 100644 --- a/drivers/ieee1394/highlevel.c +++ b/drivers/ieee1394/highlevel.c @@ -46,10 +46,6 @@ static DEFINE_RWLOCK(hl_irqs_lock); static DEFINE_RWLOCK(addr_space_lock); -/* addr_space list will have zero and max already included as bounds */ -static struct hpsb_address_ops dummy_ops = { NULL, NULL, NULL, NULL }; -static struct hpsb_address_serve dummy_zero_addr, dummy_max_addr; - static struct hl_host_info *hl_get_hostinfo(struct hpsb_highlevel *hl, struct hpsb_host *host) @@ -481,20 +477,23 @@ int hpsb_unregister_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, return retval; } +static struct hpsb_address_ops dummy_ops; + +/* dummy address spaces as lower and upper bounds of the host's a.s. list */ static void init_hpsb_highlevel(struct hpsb_host *host) { - INIT_LIST_HEAD(&dummy_zero_addr.host_list); - INIT_LIST_HEAD(&dummy_zero_addr.hl_list); - INIT_LIST_HEAD(&dummy_max_addr.host_list); - INIT_LIST_HEAD(&dummy_max_addr.hl_list); + INIT_LIST_HEAD(&host->dummy_zero_addr.host_list); + INIT_LIST_HEAD(&host->dummy_zero_addr.hl_list); + INIT_LIST_HEAD(&host->dummy_max_addr.host_list); + INIT_LIST_HEAD(&host->dummy_max_addr.hl_list); - dummy_zero_addr.op = dummy_max_addr.op = &dummy_ops; + host->dummy_zero_addr.op = host->dummy_max_addr.op = &dummy_ops; - dummy_zero_addr.start = dummy_zero_addr.end = 0; - dummy_max_addr.start = dummy_max_addr.end = ((u64) 1) << 48; + host->dummy_zero_addr.start = host->dummy_zero_addr.end = 0; + host->dummy_max_addr.start = host->dummy_max_addr.end = ((u64) 1) << 48; - list_add_tail(&dummy_zero_addr.host_list, &host->addr_space); - list_add_tail(&dummy_max_addr.host_list, &host->addr_space); + list_add_tail(&host->dummy_zero_addr.host_list, &host->addr_space); + list_add_tail(&host->dummy_max_addr.host_list, &host->addr_space); } void highlevel_add_host(struct hpsb_host *host) diff --git a/drivers/ieee1394/hosts.c b/drivers/ieee1394/hosts.c index 8dd09d850419..237d0c9d69c6 100644 --- a/drivers/ieee1394/hosts.c +++ b/drivers/ieee1394/hosts.c @@ -155,11 +155,11 @@ struct hpsb_host *hpsb_alloc_host(struct hpsb_host_driver *drv, size_t extra, memcpy(&h->device, &nodemgr_dev_template_host, sizeof(h->device)); h->device.parent = dev; set_dev_node(&h->device, dev_to_node(dev)); - snprintf(h->device.bus_id, BUS_ID_SIZE, "fw-host%d", h->id); + dev_set_name(&h->device, "fw-host%d", h->id); h->host_dev.parent = &h->device; h->host_dev.class = &hpsb_host_class; - snprintf(h->host_dev.bus_id, BUS_ID_SIZE, "fw-host%d", h->id); + dev_set_name(&h->host_dev, "fw-host%d", h->id); if (device_register(&h->device)) goto fail; diff --git a/drivers/ieee1394/hosts.h b/drivers/ieee1394/hosts.h index e4e8aeb4d778..dd229950acca 100644 --- a/drivers/ieee1394/hosts.h +++ b/drivers/ieee1394/hosts.h @@ -13,6 +13,7 @@ struct module; #include "ieee1394_types.h" #include "csr.h" +#include "highlevel.h" struct hpsb_packet; struct hpsb_iso; @@ -72,6 +73,9 @@ struct hpsb_host { struct { DECLARE_BITMAP(map, 64); } tl_pool[ALL_NODES]; struct csr_control csr; + + struct hpsb_address_serve dummy_zero_addr; + struct hpsb_address_serve dummy_max_addr; }; enum devctl_cmd { diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c index 2376b729e876..79ef5fd928ae 100644 --- a/drivers/ieee1394/nodemgr.c +++ b/drivers/ieee1394/nodemgr.c @@ -115,8 +115,14 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length, return error; } +#define OUI_FREECOM_TECHNOLOGIES_GMBH 0x0001db + static int nodemgr_get_max_rom(quadlet_t *bus_info_data, void *__ci) { + /* Freecom FireWire Hard Drive firmware bug */ + if (be32_to_cpu(bus_info_data[3]) >> 8 == OUI_FREECOM_TECHNOLOGIES_GMBH) + return 0; + return (be32_to_cpu(bus_info_data[2]) >> 8) & 0x3; } @@ -826,13 +832,11 @@ static struct node_entry *nodemgr_create_node(octlet_t guid, memcpy(&ne->device, &nodemgr_dev_template_ne, sizeof(ne->device)); ne->device.parent = &host->device; - snprintf(ne->device.bus_id, BUS_ID_SIZE, "%016Lx", - (unsigned long long)(ne->guid)); + dev_set_name(&ne->device, "%016Lx", (unsigned long long)(ne->guid)); ne->node_dev.parent = &ne->device; ne->node_dev.class = &nodemgr_ne_class; - snprintf(ne->node_dev.bus_id, BUS_ID_SIZE, "%016Lx", - (unsigned long long)(ne->guid)); + dev_set_name(&ne->node_dev, "%016Lx", (unsigned long long)(ne->guid)); if (device_register(&ne->device)) goto fail_devreg; @@ -932,13 +936,11 @@ static void nodemgr_register_device(struct node_entry *ne, ud->device.parent = parent; - snprintf(ud->device.bus_id, BUS_ID_SIZE, "%s-%u", - ne->device.bus_id, ud->id); + dev_set_name(&ud->device, "%s-%u", dev_name(&ne->device), ud->id); ud->unit_dev.parent = &ud->device; ud->unit_dev.class = &nodemgr_ud_class; - snprintf(ud->unit_dev.bus_id, BUS_ID_SIZE, "%s-%u", - ne->device.bus_id, ud->id); + dev_set_name(&ud->unit_dev, "%s-%u", dev_name(&ne->device), ud->id); if (device_register(&ud->device)) goto fail_devreg; @@ -953,7 +955,7 @@ static void nodemgr_register_device(struct node_entry *ne, fail_classdevreg: device_unregister(&ud->device); fail_devreg: - HPSB_ERR("Failed to create unit %s", ud->device.bus_id); + HPSB_ERR("Failed to create unit %s", dev_name(&ud->device)); } @@ -1689,6 +1691,7 @@ static int nodemgr_host_thread(void *data) g = get_hpsb_generation(host); for (i = 0; i < 4 ; i++) { msleep_interruptible(63); + try_to_freeze(); if (kthread_should_stop()) goto exit; @@ -1729,6 +1732,7 @@ static int nodemgr_host_thread(void *data) /* Sleep 3 seconds */ for (i = 3000/200; i; i--) { msleep_interruptible(200); + try_to_freeze(); if (kthread_should_stop()) goto exit; diff --git a/drivers/ieee1394/raw1394.c b/drivers/ieee1394/raw1394.c index 9f19ac492106..bf7e761c12b1 100644 --- a/drivers/ieee1394/raw1394.c +++ b/drivers/ieee1394/raw1394.c @@ -2268,7 +2268,8 @@ static ssize_t raw1394_write(struct file *file, const char __user * buffer, return -EFAULT; } - mutex_lock(&fi->state_mutex); + if (!mutex_trylock(&fi->state_mutex)) + return -EAGAIN; switch (fi->state) { case opened: @@ -2548,7 +2549,8 @@ static int raw1394_mmap(struct file *file, struct vm_area_struct *vma) struct file_info *fi = file->private_data; int ret; - mutex_lock(&fi->state_mutex); + if (!mutex_trylock(&fi->state_mutex)) + return -EAGAIN; if (fi->iso_state == RAW1394_ISO_INACTIVE) ret = -EINVAL; @@ -2669,7 +2671,8 @@ static long raw1394_ioctl(struct file *file, unsigned int cmd, break; } - mutex_lock(&fi->state_mutex); + if (!mutex_trylock(&fi->state_mutex)) + return -EAGAIN; switch (fi->iso_state) { case RAW1394_ISO_INACTIVE: diff --git a/drivers/ieee1394/sbp2.c b/drivers/ieee1394/sbp2.c index c52f6e6e8af2..a373c18cf7b8 100644 --- a/drivers/ieee1394/sbp2.c +++ b/drivers/ieee1394/sbp2.c @@ -400,6 +400,11 @@ static const struct { .model_id = 0x000021, .workarounds = SBP2_WORKAROUND_FIX_CAPACITY, }, + /* iPod mini */ { + .firmware_revision = 0x0a2700, + .model_id = 0x000022, + .workarounds = SBP2_WORKAROUND_FIX_CAPACITY, + }, /* iPod mini */ { .firmware_revision = 0x0a2700, .model_id = 0x000023, @@ -890,12 +895,13 @@ static void sbp2_host_reset(struct hpsb_host *host) return; read_lock_irqsave(&sbp2_hi_logical_units_lock, flags); + list_for_each_entry(lu, &hi->logical_units, lu_list) - if (likely(atomic_read(&lu->state) != - SBP2LU_STATE_IN_SHUTDOWN)) { - atomic_set(&lu->state, SBP2LU_STATE_IN_RESET); + if (atomic_cmpxchg(&lu->state, + SBP2LU_STATE_RUNNING, SBP2LU_STATE_IN_RESET) + == SBP2LU_STATE_RUNNING) scsi_block_requests(lu->shost); - } + read_unlock_irqrestore(&sbp2_hi_logical_units_lock, flags); } diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index d85af1b67027..eb36a81dd09b 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -358,8 +358,6 @@ static int ib_uverbs_event_close(struct inode *inode, struct file *filp) } spin_unlock_irq(&file->lock); - ib_uverbs_event_fasync(-1, filp, 0); - if (file->is_async) { ib_unregister_event_handler(&file->uverbs_file->event_handler); kref_put(&file->uverbs_file->ref, ib_uverbs_release_file); diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.c b/drivers/infiniband/hw/cxgb3/iwch_provider.c index ecff98043589..160ef482712d 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_provider.c +++ b/drivers/infiniband/hw/cxgb3/iwch_provider.c @@ -1102,9 +1102,7 @@ static u64 fw_vers_string_to_u64(struct iwch_dev *iwch_dev) char *cp, *next; unsigned fw_maj, fw_min, fw_mic; - rtnl_lock(); lldev->ethtool_ops->get_drvinfo(lldev, &info); - rtnl_unlock(); next = info.fw_version + 1; cp = strsep(&next, "."); @@ -1192,9 +1190,7 @@ static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, ch struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev; PDBG("%s dev 0x%p\n", __func__, dev); - rtnl_lock(); lldev->ethtool_ops->get_drvinfo(lldev, &info); - rtnl_unlock(); return sprintf(buf, "%s\n", info.fw_version); } @@ -1207,9 +1203,7 @@ static ssize_t show_hca(struct device *dev, struct device_attribute *attr, struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev; PDBG("%s dev 0x%p\n", __func__, dev); - rtnl_lock(); lldev->ethtool_ops->get_drvinfo(lldev, &info); - rtnl_unlock(); return sprintf(buf, "%s\n", info.driver); } diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c index 3e4585c2318a..19661b2f0406 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_qp.c +++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c @@ -745,7 +745,6 @@ int iwch_post_zb_read(struct iwch_qp *qhp) wqe->read.rdmaop = T3_READ_REQ; wqe->read.reserved[0] = 0; wqe->read.reserved[1] = 0; - wqe->read.reserved[2] = 0; wqe->read.rem_stag = cpu_to_be32(1); wqe->read.rem_to = cpu_to_be64(1); wqe->read.local_stag = cpu_to_be32(1); diff --git a/drivers/infiniband/hw/ehca/ehca_classes.h b/drivers/infiniband/hw/ehca/ehca_classes.h index 4df887af66a5..7fc35cf0cddf 100644 --- a/drivers/infiniband/hw/ehca/ehca_classes.h +++ b/drivers/infiniband/hw/ehca/ehca_classes.h @@ -163,7 +163,8 @@ struct ehca_mod_qp_parm { /* struct for tracking if cqes have been reported to the application */ struct ehca_qmap_entry { u16 app_wr_id; - u16 reported; + u8 reported; + u8 cqe_req; }; struct ehca_queue_map { @@ -171,6 +172,7 @@ struct ehca_queue_map { unsigned int entries; unsigned int tail; unsigned int left_to_poll; + unsigned int next_wqe_idx; /* Idx to first wqe to be flushed */ }; struct ehca_qp { diff --git a/drivers/infiniband/hw/ehca/ehca_irq.c b/drivers/infiniband/hw/ehca/ehca_irq.c index cb55be04442c..757035ea246f 100644 --- a/drivers/infiniband/hw/ehca/ehca_irq.c +++ b/drivers/infiniband/hw/ehca/ehca_irq.c @@ -359,36 +359,48 @@ static void notify_port_conf_change(struct ehca_shca *shca, int port_num) *old_attr = new_attr; } +/* replay modify_qp for sqps -- return 0 if all is well, 1 if AQP1 destroyed */ +static int replay_modify_qp(struct ehca_sport *sport) +{ + int aqp1_destroyed; + unsigned long flags; + + spin_lock_irqsave(&sport->mod_sqp_lock, flags); + + aqp1_destroyed = !sport->ibqp_sqp[IB_QPT_GSI]; + + if (sport->ibqp_sqp[IB_QPT_SMI]) + ehca_recover_sqp(sport->ibqp_sqp[IB_QPT_SMI]); + if (!aqp1_destroyed) + ehca_recover_sqp(sport->ibqp_sqp[IB_QPT_GSI]); + + spin_unlock_irqrestore(&sport->mod_sqp_lock, flags); + + return aqp1_destroyed; +} + static void parse_ec(struct ehca_shca *shca, u64 eqe) { u8 ec = EHCA_BMASK_GET(NEQE_EVENT_CODE, eqe); u8 port = EHCA_BMASK_GET(NEQE_PORT_NUMBER, eqe); u8 spec_event; struct ehca_sport *sport = &shca->sport[port - 1]; - unsigned long flags; switch (ec) { case 0x30: /* port availability change */ if (EHCA_BMASK_GET(NEQE_PORT_AVAILABILITY, eqe)) { - int suppress_event; - /* replay modify_qp for sqps */ - spin_lock_irqsave(&sport->mod_sqp_lock, flags); - suppress_event = !sport->ibqp_sqp[IB_QPT_GSI]; - if (sport->ibqp_sqp[IB_QPT_SMI]) - ehca_recover_sqp(sport->ibqp_sqp[IB_QPT_SMI]); - if (!suppress_event) - ehca_recover_sqp(sport->ibqp_sqp[IB_QPT_GSI]); - spin_unlock_irqrestore(&sport->mod_sqp_lock, flags); - - /* AQP1 was destroyed, ignore this event */ - if (suppress_event) - break; + /* only replay modify_qp calls in autodetect mode; + * if AQP1 was destroyed, the port is already down + * again and we can drop the event. + */ + if (ehca_nr_ports < 0) + if (replay_modify_qp(sport)) + break; sport->port_state = IB_PORT_ACTIVE; dispatch_port_event(shca, port, IB_EVENT_PORT_ACTIVE, "is active"); - ehca_query_sma_attr(shca, port, - &sport->saved_attr); + ehca_query_sma_attr(shca, port, &sport->saved_attr); } else { sport->port_state = IB_PORT_DOWN; dispatch_port_event(shca, port, IB_EVENT_PORT_ERR, diff --git a/drivers/infiniband/hw/ehca/ehca_main.c b/drivers/infiniband/hw/ehca/ehca_main.c index bb02a86aa526..bec7e0249358 100644 --- a/drivers/infiniband/hw/ehca/ehca_main.c +++ b/drivers/infiniband/hw/ehca/ehca_main.c @@ -994,8 +994,7 @@ static int ehca_mem_notifier(struct notifier_block *nb, if (printk_timed_ratelimit(&ehca_dmem_warn_time, 30 * 1000)) ehca_gen_err("DMEM operations are not allowed" - "as long as an ehca adapter is" - "attached to the LPAR"); + "in conjunction with eHCA"); return NOTIFY_BAD; } } diff --git a/drivers/infiniband/hw/ehca/ehca_qp.c b/drivers/infiniband/hw/ehca/ehca_qp.c index 4d54b9f64567..cadbf0cdd910 100644 --- a/drivers/infiniband/hw/ehca/ehca_qp.c +++ b/drivers/infiniband/hw/ehca/ehca_qp.c @@ -435,9 +435,13 @@ static void reset_queue_map(struct ehca_queue_map *qmap) { int i; - qmap->tail = 0; - for (i = 0; i < qmap->entries; i++) + qmap->tail = qmap->entries - 1; + qmap->left_to_poll = 0; + qmap->next_wqe_idx = 0; + for (i = 0; i < qmap->entries; i++) { qmap->map[i].reported = 1; + qmap->map[i].cqe_req = 0; + } } /* @@ -860,6 +864,11 @@ static struct ehca_qp *internal_create_qp( if (qp_type == IB_QPT_GSI) { h_ret = ehca_define_sqp(shca, my_qp, init_attr); if (h_ret != H_SUCCESS) { + kfree(my_qp->mod_qp_parm); + my_qp->mod_qp_parm = NULL; + /* the QP pointer is no longer valid */ + shca->sport[init_attr->port_num - 1].ibqp_sqp[qp_type] = + NULL; ret = ehca2ib_return_code(h_ret); goto create_qp_exit6; } @@ -1116,6 +1125,7 @@ static int calc_left_cqes(u64 wqe_p, struct ipz_queue *ipz_queue, void *wqe_v; u64 q_ofs; u32 wqe_idx; + unsigned int tail_idx; /* convert real to abs address */ wqe_p = wqe_p & (~(1UL << 63)); @@ -1128,12 +1138,17 @@ static int calc_left_cqes(u64 wqe_p, struct ipz_queue *ipz_queue, return -EFAULT; } + tail_idx = (qmap->tail + 1) % qmap->entries; wqe_idx = q_ofs / ipz_queue->qe_size; - if (wqe_idx < qmap->tail) - qmap->left_to_poll = (qmap->entries - qmap->tail) + wqe_idx; - else - qmap->left_to_poll = wqe_idx - qmap->tail; + /* check all processed wqes, whether a cqe is requested or not */ + while (tail_idx != wqe_idx) { + if (qmap->map[tail_idx].cqe_req) + qmap->left_to_poll++; + tail_idx = (tail_idx + 1) % qmap->entries; + } + /* save index in queue, where we have to start flushing */ + qmap->next_wqe_idx = wqe_idx; return 0; } @@ -1180,10 +1195,14 @@ static int check_for_left_cqes(struct ehca_qp *my_qp, struct ehca_shca *shca) } else { spin_lock_irqsave(&my_qp->send_cq->spinlock, flags); my_qp->sq_map.left_to_poll = 0; + my_qp->sq_map.next_wqe_idx = (my_qp->sq_map.tail + 1) % + my_qp->sq_map.entries; spin_unlock_irqrestore(&my_qp->send_cq->spinlock, flags); spin_lock_irqsave(&my_qp->recv_cq->spinlock, flags); my_qp->rq_map.left_to_poll = 0; + my_qp->rq_map.next_wqe_idx = (my_qp->rq_map.tail + 1) % + my_qp->rq_map.entries; spin_unlock_irqrestore(&my_qp->recv_cq->spinlock, flags); } diff --git a/drivers/infiniband/hw/ehca/ehca_reqs.c b/drivers/infiniband/hw/ehca/ehca_reqs.c index 64928079eafa..00a648f4316c 100644 --- a/drivers/infiniband/hw/ehca/ehca_reqs.c +++ b/drivers/infiniband/hw/ehca/ehca_reqs.c @@ -179,6 +179,7 @@ static inline int ehca_write_swqe(struct ehca_qp *qp, qmap_entry->app_wr_id = get_app_wr_id(send_wr->wr_id); qmap_entry->reported = 0; + qmap_entry->cqe_req = 0; switch (send_wr->opcode) { case IB_WR_SEND: @@ -203,8 +204,10 @@ static inline int ehca_write_swqe(struct ehca_qp *qp, if ((send_wr->send_flags & IB_SEND_SIGNALED || qp->init_attr.sq_sig_type == IB_SIGNAL_ALL_WR) - && !hidden) + && !hidden) { wqe_p->wr_flag |= WQE_WRFLAG_REQ_SIGNAL_COM; + qmap_entry->cqe_req = 1; + } if (send_wr->opcode == IB_WR_SEND_WITH_IMM || send_wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) { @@ -569,6 +572,7 @@ static int internal_post_recv(struct ehca_qp *my_qp, qmap_entry = &my_qp->rq_map.map[rq_map_idx]; qmap_entry->app_wr_id = get_app_wr_id(cur_recv_wr->wr_id); qmap_entry->reported = 0; + qmap_entry->cqe_req = 1; wqe_cnt++; } /* eof for cur_recv_wr */ @@ -706,27 +710,34 @@ repoll: goto repoll; wc->qp = &my_qp->ib_qp; + qmap_tail_idx = get_app_wr_id(cqe->work_request_id); + if (!(cqe->w_completion_flags & WC_SEND_RECEIVE_BIT)) + /* We got a send completion. */ + qmap = &my_qp->sq_map; + else + /* We got a receive completion. */ + qmap = &my_qp->rq_map; + + /* advance the tail pointer */ + qmap->tail = qmap_tail_idx; + if (is_error) { /* * set left_to_poll to 0 because in error state, we will not * get any additional CQEs */ - ehca_add_to_err_list(my_qp, 1); + my_qp->sq_map.next_wqe_idx = (my_qp->sq_map.tail + 1) % + my_qp->sq_map.entries; my_qp->sq_map.left_to_poll = 0; + ehca_add_to_err_list(my_qp, 1); + my_qp->rq_map.next_wqe_idx = (my_qp->rq_map.tail + 1) % + my_qp->rq_map.entries; + my_qp->rq_map.left_to_poll = 0; if (HAS_RQ(my_qp)) ehca_add_to_err_list(my_qp, 0); - my_qp->rq_map.left_to_poll = 0; } - qmap_tail_idx = get_app_wr_id(cqe->work_request_id); - if (!(cqe->w_completion_flags & WC_SEND_RECEIVE_BIT)) - /* We got a send completion. */ - qmap = &my_qp->sq_map; - else - /* We got a receive completion. */ - qmap = &my_qp->rq_map; - qmap_entry = &qmap->map[qmap_tail_idx]; if (qmap_entry->reported) { ehca_warn(cq->device, "Double cqe on qp_num=%#x", @@ -738,10 +749,6 @@ repoll: wc->wr_id = replace_wr_id(cqe->work_request_id, qmap_entry->app_wr_id); qmap_entry->reported = 1; - /* this is a proper completion, we need to advance the tail pointer */ - if (++qmap->tail == qmap->entries) - qmap->tail = 0; - /* if left_to_poll is decremented to 0, add the QP to the error list */ if (qmap->left_to_poll > 0) { qmap->left_to_poll--; @@ -805,13 +812,14 @@ static int generate_flush_cqes(struct ehca_qp *my_qp, struct ib_cq *cq, else qmap = &my_qp->rq_map; - qmap_entry = &qmap->map[qmap->tail]; + qmap_entry = &qmap->map[qmap->next_wqe_idx]; while ((nr < num_entries) && (qmap_entry->reported == 0)) { /* generate flush CQE */ + memset(wc, 0, sizeof(*wc)); - offset = qmap->tail * ipz_queue->qe_size; + offset = qmap->next_wqe_idx * ipz_queue->qe_size; wqe = (struct ehca_wqe *)ipz_qeit_calc(ipz_queue, offset); if (!wqe) { ehca_err(cq->device, "Invalid wqe offset=%#lx on " @@ -850,11 +858,12 @@ static int generate_flush_cqes(struct ehca_qp *my_qp, struct ib_cq *cq, wc->qp = &my_qp->ib_qp; - /* mark as reported and advance tail pointer */ + /* mark as reported and advance next_wqe pointer */ qmap_entry->reported = 1; - if (++qmap->tail == qmap->entries) - qmap->tail = 0; - qmap_entry = &qmap->map[qmap->tail]; + qmap->next_wqe_idx++; + if (qmap->next_wqe_idx == qmap->entries) + qmap->next_wqe_idx = 0; + qmap_entry = &qmap->map[qmap->next_wqe_idx]; wc++; nr++; } diff --git a/drivers/infiniband/hw/ipath/ipath_ruc.c b/drivers/infiniband/hw/ipath/ipath_ruc.c index fc0f6d9e6030..2296832f94da 100644 --- a/drivers/infiniband/hw/ipath/ipath_ruc.c +++ b/drivers/infiniband/hw/ipath/ipath_ruc.c @@ -156,7 +156,7 @@ bail: /** * ipath_get_rwqe - copy the next RWQE into the QP's RWQE * @qp: the QP - * @wr_id_only: update wr_id only, not SGEs + * @wr_id_only: update qp->r_wr_id only, not qp->r_sge * * Return 0 if no RWQE is available, otherwise return 1. * @@ -173,8 +173,6 @@ int ipath_get_rwqe(struct ipath_qp *qp, int wr_id_only) u32 tail; int ret; - qp->r_sge.sg_list = qp->r_sg_list; - if (qp->ibqp.srq) { srq = to_isrq(qp->ibqp.srq); handler = srq->ibsrq.event_handler; @@ -206,8 +204,10 @@ int ipath_get_rwqe(struct ipath_qp *qp, int wr_id_only) wqe = get_rwqe_ptr(rq, tail); if (++tail >= rq->size) tail = 0; - } while (!wr_id_only && !ipath_init_sge(qp, wqe, &qp->r_len, - &qp->r_sge)); + if (wr_id_only) + break; + qp->r_sge.sg_list = qp->r_sg_list; + } while (!ipath_init_sge(qp, wqe, &qp->r_len, &qp->r_sge)); qp->r_wr_id = wqe->wr_id; wq->tail = tail; diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c index d0866a3636e2..18308494a195 100644 --- a/drivers/infiniband/hw/mlx4/cq.c +++ b/drivers/infiniband/hw/mlx4/cq.c @@ -343,6 +343,7 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) { struct mlx4_ib_dev *dev = to_mdev(ibcq->device); struct mlx4_ib_cq *cq = to_mcq(ibcq); + struct mlx4_mtt mtt; int outst_cqe; int err; @@ -376,10 +377,13 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) goto out; } + mtt = cq->buf.mtt; + err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); if (err) goto err_buf; + mlx4_mtt_cleanup(dev->dev, &mtt); if (ibcq->uobject) { cq->buf = cq->resize_buf->buf; cq->ibcq.cqe = cq->resize_buf->cqe; @@ -406,6 +410,7 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) goto out; err_buf: + mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); if (!ibcq->uobject) mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, cq->resize_buf->cqe); diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c index 87f5c5a87b98..8e4d26d56a95 100644 --- a/drivers/infiniband/hw/mlx4/mr.c +++ b/drivers/infiniband/hw/mlx4/mr.c @@ -205,6 +205,7 @@ struct ib_mr *mlx4_ib_alloc_fast_reg_mr(struct ib_pd *pd, goto err_mr; mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; + mr->umem = NULL; return &mr->ibmr; diff --git a/drivers/infiniband/hw/nes/nes.c b/drivers/infiniband/hw/nes/nes.c index a2b04d62b1a4..aa1dc41f04c8 100644 --- a/drivers/infiniband/hw/nes/nes.c +++ b/drivers/infiniband/hw/nes/nes.c @@ -95,6 +95,10 @@ unsigned int wqm_quanta = 0x10000; module_param(wqm_quanta, int, 0644); MODULE_PARM_DESC(wqm_quanta, "WQM quanta"); +static unsigned int limit_maxrdreqsz; +module_param(limit_maxrdreqsz, bool, 0644); +MODULE_PARM_DESC(limit_maxrdreqsz, "Limit max read request size to 256 Bytes"); + LIST_HEAD(nes_adapter_list); static LIST_HEAD(nes_dev_list); @@ -588,6 +592,18 @@ static int __devinit nes_probe(struct pci_dev *pcidev, const struct pci_device_i nesdev->nesadapter->port_count; } + if ((limit_maxrdreqsz || + ((nesdev->nesadapter->phy_type[0] == NES_PHY_TYPE_GLADIUS) && + (hw_rev == NE020_REV1))) && + (pcie_get_readrq(pcidev) > 256)) { + if (pcie_set_readrq(pcidev, 256)) + printk(KERN_ERR PFX "Unable to set max read request" + " to 256 bytes\n"); + else + nes_debug(NES_DBG_INIT, "Max read request size set" + " to 256 bytes\n"); + } + tasklet_init(&nesdev->dpc_tasklet, nes_dpc, (unsigned long)nesdev); /* bring up the Control QP */ diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h index 610b9d859597..bc0b4de04450 100644 --- a/drivers/infiniband/hw/nes/nes_hw.h +++ b/drivers/infiniband/hw/nes/nes_hw.h @@ -40,6 +40,7 @@ #define NES_PHY_TYPE_ARGUS 4 #define NES_PHY_TYPE_PUMA_1G 5 #define NES_PHY_TYPE_PUMA_10G 6 +#define NES_PHY_TYPE_GLADIUS 7 #define NES_MULTICAST_PF_MAX 8 diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c index 932e56fcf774..d36c9a0bf1bb 100644 --- a/drivers/infiniband/hw/nes/nes_verbs.c +++ b/drivers/infiniband/hw/nes/nes_verbs.c @@ -220,14 +220,14 @@ static int nes_bind_mw(struct ib_qp *ibqp, struct ib_mw *ibmw, if (nesqp->ibqp_state > IB_QPS_RTS) return -EINVAL; - spin_lock_irqsave(&nesqp->lock, flags); + spin_lock_irqsave(&nesqp->lock, flags); head = nesqp->hwqp.sq_head; qsize = nesqp->hwqp.sq_tail; /* Check for SQ overflow */ if (((head + (2 * qsize) - nesqp->hwqp.sq_tail) % qsize) == (qsize - 1)) { - spin_unlock_irqrestore(&nesqp->lock, flags); + spin_unlock_irqrestore(&nesqp->lock, flags); return -EINVAL; } @@ -269,7 +269,7 @@ static int nes_bind_mw(struct ib_qp *ibqp, struct ib_mw *ibmw, nes_write32(nesdev->regs+NES_WQE_ALLOC, (1 << 24) | 0x00800000 | nesqp->hwqp.qp_id); - spin_unlock_irqrestore(&nesqp->lock, flags); + spin_unlock_irqrestore(&nesqp->lock, flags); return 0; } @@ -349,7 +349,7 @@ static struct ib_fmr *nes_alloc_fmr(struct ib_pd *ibpd, if (nesfmr->nesmr.pbls_used > nesadapter->free_4kpbl) { spin_unlock_irqrestore(&nesadapter->pbl_lock, flags); ret = -ENOMEM; - goto failed_vpbl_alloc; + goto failed_vpbl_avail; } else { nesadapter->free_4kpbl -= nesfmr->nesmr.pbls_used; } @@ -357,7 +357,7 @@ static struct ib_fmr *nes_alloc_fmr(struct ib_pd *ibpd, if (nesfmr->nesmr.pbls_used > nesadapter->free_256pbl) { spin_unlock_irqrestore(&nesadapter->pbl_lock, flags); ret = -ENOMEM; - goto failed_vpbl_alloc; + goto failed_vpbl_avail; } else { nesadapter->free_256pbl -= nesfmr->nesmr.pbls_used; } @@ -391,14 +391,14 @@ static struct ib_fmr *nes_alloc_fmr(struct ib_pd *ibpd, goto failed_vpbl_alloc; } - nesfmr->root_vpbl.leaf_vpbl = kzalloc(sizeof(*nesfmr->root_vpbl.leaf_vpbl)*1024, GFP_KERNEL); + nesfmr->leaf_pbl_cnt = nesfmr->nesmr.pbls_used-1; + nesfmr->root_vpbl.leaf_vpbl = kzalloc(sizeof(*nesfmr->root_vpbl.leaf_vpbl)*1024, GFP_ATOMIC); if (!nesfmr->root_vpbl.leaf_vpbl) { spin_unlock_irqrestore(&nesadapter->pbl_lock, flags); ret = -ENOMEM; goto failed_leaf_vpbl_alloc; } - nesfmr->leaf_pbl_cnt = nesfmr->nesmr.pbls_used-1; nes_debug(NES_DBG_MR, "two level pbl, root_vpbl.pbl_vbase=%p" " leaf_pbl_cnt=%d root_vpbl.leaf_vpbl=%p\n", nesfmr->root_vpbl.pbl_vbase, nesfmr->leaf_pbl_cnt, nesfmr->root_vpbl.leaf_vpbl); @@ -519,6 +519,16 @@ static struct ib_fmr *nes_alloc_fmr(struct ib_pd *ibpd, nesfmr->root_vpbl.pbl_pbase); failed_vpbl_alloc: + if (nesfmr->nesmr.pbls_used != 0) { + spin_lock_irqsave(&nesadapter->pbl_lock, flags); + if (nesfmr->nesmr.pbl_4k) + nesadapter->free_4kpbl += nesfmr->nesmr.pbls_used; + else + nesadapter->free_256pbl += nesfmr->nesmr.pbls_used; + spin_unlock_irqrestore(&nesadapter->pbl_lock, flags); + } + +failed_vpbl_avail: kfree(nesfmr); failed_fmr_alloc: @@ -534,18 +544,14 @@ static struct ib_fmr *nes_alloc_fmr(struct ib_pd *ibpd, */ static int nes_dealloc_fmr(struct ib_fmr *ibfmr) { + unsigned long flags; struct nes_mr *nesmr = to_nesmr_from_ibfmr(ibfmr); struct nes_fmr *nesfmr = to_nesfmr(nesmr); struct nes_vnic *nesvnic = to_nesvnic(ibfmr->device); struct nes_device *nesdev = nesvnic->nesdev; - struct nes_mr temp_nesmr = *nesmr; + struct nes_adapter *nesadapter = nesdev->nesadapter; int i = 0; - temp_nesmr.ibmw.device = ibfmr->device; - temp_nesmr.ibmw.pd = ibfmr->pd; - temp_nesmr.ibmw.rkey = ibfmr->rkey; - temp_nesmr.ibmw.uobject = NULL; - /* free the resources */ if (nesfmr->leaf_pbl_cnt == 0) { /* single PBL case */ @@ -561,8 +567,24 @@ static int nes_dealloc_fmr(struct ib_fmr *ibfmr) pci_free_consistent(nesdev->pcidev, 8192, nesfmr->root_vpbl.pbl_vbase, nesfmr->root_vpbl.pbl_pbase); } + nesmr->ibmw.device = ibfmr->device; + nesmr->ibmw.pd = ibfmr->pd; + nesmr->ibmw.rkey = ibfmr->rkey; + nesmr->ibmw.uobject = NULL; - return nes_dealloc_mw(&temp_nesmr.ibmw); + if (nesfmr->nesmr.pbls_used != 0) { + spin_lock_irqsave(&nesadapter->pbl_lock, flags); + if (nesfmr->nesmr.pbl_4k) { + nesadapter->free_4kpbl += nesfmr->nesmr.pbls_used; + WARN_ON(nesadapter->free_4kpbl > nesadapter->max_4kpbl); + } else { + nesadapter->free_256pbl += nesfmr->nesmr.pbls_used; + WARN_ON(nesadapter->free_256pbl > nesadapter->max_256pbl); + } + spin_unlock_irqrestore(&nesadapter->pbl_lock, flags); + } + + return nes_dealloc_mw(&nesmr->ibmw); } @@ -1595,7 +1617,7 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev, int entries, nes_ucontext->mcrqf = req.mcrqf; if (nes_ucontext->mcrqf) { if (nes_ucontext->mcrqf & 0x80000000) - nescq->hw_cq.cq_number = nesvnic->nic.qp_id + 12 + (nes_ucontext->mcrqf & 0xf) - 1; + nescq->hw_cq.cq_number = nesvnic->nic.qp_id + 28 + 2 * ((nes_ucontext->mcrqf & 0xf) - 1); else if (nes_ucontext->mcrqf & 0x40000000) nescq->hw_cq.cq_number = nes_ucontext->mcrqf & 0xffff; else @@ -3212,7 +3234,7 @@ static int nes_post_send(struct ib_qp *ibqp, struct ib_send_wr *ib_wr, if (nesqp->ibqp_state > IB_QPS_RTS) return -EINVAL; - spin_lock_irqsave(&nesqp->lock, flags); + spin_lock_irqsave(&nesqp->lock, flags); head = nesqp->hwqp.sq_head; @@ -3337,7 +3359,7 @@ static int nes_post_send(struct ib_qp *ibqp, struct ib_send_wr *ib_wr, (counter << 24) | 0x00800000 | nesqp->hwqp.qp_id); } - spin_unlock_irqrestore(&nesqp->lock, flags); + spin_unlock_irqrestore(&nesqp->lock, flags); if (err) *bad_wr = ib_wr; @@ -3368,7 +3390,7 @@ static int nes_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *ib_wr, if (nesqp->ibqp_state > IB_QPS_RTS) return -EINVAL; - spin_lock_irqsave(&nesqp->lock, flags); + spin_lock_irqsave(&nesqp->lock, flags); head = nesqp->hwqp.rq_head; @@ -3421,7 +3443,7 @@ static int nes_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *ib_wr, nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter<<24) | nesqp->hwqp.qp_id); } - spin_unlock_irqrestore(&nesqp->lock, flags); + spin_unlock_irqrestore(&nesqp->lock, flags); if (err) *bad_wr = ib_wr; @@ -3453,7 +3475,7 @@ static int nes_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *entry) nes_debug(NES_DBG_CQ, "\n"); - spin_lock_irqsave(&nescq->lock, flags); + spin_lock_irqsave(&nescq->lock, flags); head = nescq->hw_cq.cq_head; cq_size = nescq->hw_cq.cq_size; @@ -3562,7 +3584,7 @@ static int nes_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *entry) nes_debug(NES_DBG_CQ, "Reporting %u completions for CQ%u.\n", cqe_count, nescq->hw_cq.cq_number); - spin_unlock_irqrestore(&nescq->lock, flags); + spin_unlock_irqrestore(&nescq->lock, flags); return cqe_count; } diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c index fddded7900d1..85257f6b9576 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_main.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c @@ -106,12 +106,13 @@ int ipoib_open(struct net_device *dev) ipoib_dbg(priv, "bringing up interface\n"); - napi_enable(&priv->napi); set_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags); if (ipoib_pkey_dev_delay_open(dev)) return 0; + napi_enable(&priv->napi); + if (ipoib_ib_dev_open(dev)) { napi_disable(&priv->napi); return -EINVAL; @@ -546,6 +547,7 @@ static int path_rec_start(struct net_device *dev, if (path->query_id < 0) { ipoib_warn(priv, "ib_sa_path_rec_get failed: %d\n", path->query_id); path->query = NULL; + complete(&path->done); return path->query_id; } @@ -662,7 +664,7 @@ static void unicast_arp_send(struct sk_buff *skb, struct net_device *dev, skb_push(skb, sizeof *phdr); __skb_queue_tail(&path->queue, skb); - if (path_rec_start(dev, path)) { + if (!path->query && path_rec_start(dev, path)) { spin_unlock_irqrestore(&priv->lock, flags); path_free(dev, path); return; diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c index 3524bef62be6..1070db330d35 100644 --- a/drivers/input/evdev.c +++ b/drivers/input/evdev.c @@ -235,7 +235,6 @@ static int evdev_release(struct inode *inode, struct file *file) evdev_ungrab(evdev, client); mutex_unlock(&evdev->mutex); - evdev_fasync(-1, file, 0); evdev_detach_client(evdev, client); kfree(client); diff --git a/drivers/input/ff-memless.c b/drivers/input/ff-memless.c index 6790e975a98c..bc4e40f3ede7 100644 --- a/drivers/input/ff-memless.c +++ b/drivers/input/ff-memless.c @@ -397,8 +397,9 @@ static int ml_ff_playback(struct input_dev *dev, int effect_id, int value) { struct ml_device *ml = dev->ff->private; struct ml_effect_state *state = &ml->states[effect_id]; + unsigned long flags; - spin_lock_bh(&ml->timer_lock); + spin_lock_irqsave(&ml->timer_lock, flags); if (value > 0) { debug("initiated play"); @@ -424,7 +425,7 @@ static int ml_ff_playback(struct input_dev *dev, int effect_id, int value) ml_play_effects(ml); } - spin_unlock_bh(&ml->timer_lock); + spin_unlock_irqrestore(&ml->timer_lock, flags); return 0; } diff --git a/drivers/input/joydev.c b/drivers/input/joydev.c index 65d7077a75a1..a85b1485e774 100644 --- a/drivers/input/joydev.c +++ b/drivers/input/joydev.c @@ -244,7 +244,6 @@ static int joydev_release(struct inode *inode, struct file *file) struct joydev_client *client = file->private_data; struct joydev *joydev = client->joydev; - joydev_fasync(-1, file, 0); joydev_detach_client(joydev, client); kfree(client); diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c index 22016ca15351..379b7ff354ec 100644 --- a/drivers/input/keyboard/atkbd.c +++ b/drivers/input/keyboard/atkbd.c @@ -824,7 +824,7 @@ static void atkbd_disconnect(struct serio *serio) atkbd_disable(atkbd); /* make sure we don't have a command in flight */ - flush_scheduled_work(); + cancel_delayed_work_sync(&atkbd->event_work); sysfs_remove_group(&serio->dev.kobj, &atkbd_attribute_group); input_unregister_device(atkbd->dev); @@ -867,6 +867,22 @@ static void atkbd_hp_keymap_fixup(struct atkbd *atkbd) atkbd->force_release_mask); } +/* + * Inventec system with broken key release on volume keys + */ +static void atkbd_inventec_keymap_fixup(struct atkbd *atkbd) +{ + const unsigned int forced_release_keys[] = { + 0xae, 0xb0, + }; + int i; + + if (atkbd->set == 2) + for (i = 0; i < ARRAY_SIZE(forced_release_keys); i++) + __set_bit(forced_release_keys[i], + atkbd->force_release_mask); +} + /* * atkbd_set_keycode_table() initializes keyboard's keycode table * according to the selected scancode set @@ -1468,6 +1484,15 @@ static struct dmi_system_id atkbd_dmi_quirk_table[] __initdata = { .callback = atkbd_setup_fixup, .driver_data = atkbd_hp_keymap_fixup, }, + { + .ident = "Inventec Symphony", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "INVENTEC"), + DMI_MATCH(DMI_PRODUCT_NAME, "SYMPHONY 6.0/7.0"), + }, + .callback = atkbd_setup_fixup, + .driver_data = atkbd_inventec_keymap_fixup, + }, { } }; diff --git a/drivers/input/misc/cm109.c b/drivers/input/misc/cm109.c index bce160f4349b..86457feccfc4 100644 --- a/drivers/input/misc/cm109.c +++ b/drivers/input/misc/cm109.c @@ -42,7 +42,7 @@ static char *phone = "kip1000"; module_param(phone, charp, S_IRUSR); -MODULE_PARM_DESC(phone, "Phone name {kip1000, gtalk, usbph01}"); +MODULE_PARM_DESC(phone, "Phone name {kip1000, gtalk, usbph01, atcom}"); enum { /* HID Registers */ @@ -258,6 +258,37 @@ static unsigned short keymap_usbph01(int scancode) } } +/* + * Keymap for ATCom AU-100 + * http://www.atcom.cn/En_products_AU100.html + * http://www.packetizer.com/products/au100/ + * http://www.voip-info.org/wiki/view/AU-100 + * + * Contributed by daniel@gimpelevich.san-francisco.ca.us + */ +static unsigned short keymap_atcom(int scancode) +{ + switch (scancode) { /* phone key: */ + case 0x82: return KEY_NUMERIC_0; /* 0 */ + case 0x11: return KEY_NUMERIC_1; /* 1 */ + case 0x12: return KEY_NUMERIC_2; /* 2 */ + case 0x14: return KEY_NUMERIC_3; /* 3 */ + case 0x21: return KEY_NUMERIC_4; /* 4 */ + case 0x22: return KEY_NUMERIC_5; /* 5 */ + case 0x24: return KEY_NUMERIC_6; /* 6 */ + case 0x41: return KEY_NUMERIC_7; /* 7 */ + case 0x42: return KEY_NUMERIC_8; /* 8 */ + case 0x44: return KEY_NUMERIC_9; /* 9 */ + case 0x84: return KEY_NUMERIC_POUND; /* # */ + case 0x81: return KEY_NUMERIC_STAR; /* * */ + case 0x18: return KEY_ENTER; /* pickup */ + case 0x28: return KEY_ESC; /* hangup */ + case 0x48: return KEY_LEFT; /* left arrow */ + case 0x88: return KEY_RIGHT; /* right arrow */ + default: return special_keymap(scancode); + } +} + static unsigned short (*keymap)(int) = keymap_kip1000; /* @@ -840,6 +871,10 @@ static int __init cm109_select_keymap(void) keymap = keymap_usbph01; printk(KERN_INFO KBUILD_MODNAME ": " "Keymap for Allied-Telesis Corega USBPH01 phone loaded\n"); + } else if (!strcasecmp(phone, "atcom")) { + keymap = keymap_atcom; + printk(KERN_INFO KBUILD_MODNAME ": " + "Keymap for ATCom AU-100 phone loaded\n"); } else { printk(KERN_ERR KBUILD_MODNAME ": " "Unsupported phone: %s\n", phone); diff --git a/drivers/input/misc/hp_sdc_rtc.c b/drivers/input/misc/hp_sdc_rtc.c index 82ec6b1b6467..216a559f55ea 100644 --- a/drivers/input/misc/hp_sdc_rtc.c +++ b/drivers/input/misc/hp_sdc_rtc.c @@ -71,7 +71,6 @@ static int hp_sdc_rtc_ioctl(struct inode *inode, struct file *file, static unsigned int hp_sdc_rtc_poll(struct file *file, poll_table *wait); static int hp_sdc_rtc_open(struct inode *inode, struct file *file); -static int hp_sdc_rtc_release(struct inode *inode, struct file *file); static int hp_sdc_rtc_fasync (int fd, struct file *filp, int on); static int hp_sdc_rtc_read_proc(char *page, char **start, off_t off, @@ -414,17 +413,6 @@ static int hp_sdc_rtc_open(struct inode *inode, struct file *file) return 0; } -static int hp_sdc_rtc_release(struct inode *inode, struct file *file) -{ - /* Turn off interrupts? */ - - if (file->f_flags & FASYNC) { - hp_sdc_rtc_fasync (-1, file, 0); - } - - return 0; -} - static int hp_sdc_rtc_fasync (int fd, struct file *filp, int on) { return fasync_helper (fd, filp, on, &hp_sdc_rtc_async_queue); @@ -680,7 +668,6 @@ static const struct file_operations hp_sdc_rtc_fops = { .poll = hp_sdc_rtc_poll, .ioctl = hp_sdc_rtc_ioctl, .open = hp_sdc_rtc_open, - .release = hp_sdc_rtc_release, .fasync = hp_sdc_rtc_fasync, }; diff --git a/drivers/input/misc/sgi_btns.c b/drivers/input/misc/sgi_btns.c index ce238f59b3c8..be3a15f5b25d 100644 --- a/drivers/input/misc/sgi_btns.c +++ b/drivers/input/misc/sgi_btns.c @@ -174,5 +174,6 @@ static void __exit sgi_buttons_exit(void) platform_driver_unregister(&sgi_buttons_driver); } +MODULE_LICENSE("GPL"); module_init(sgi_buttons_init); module_exit(sgi_buttons_exit); diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig index f488b6852baf..4e9934259775 100644 --- a/drivers/input/mouse/Kconfig +++ b/drivers/input/mouse/Kconfig @@ -25,8 +25,8 @@ config MOUSE_PS2 mice with wheels and extra buttons, Microsoft, Logitech or Genius compatible. - Synaptics TouchPad users might be interested in a specialized - XFree86 driver at: + Synaptics, ALPS or Elantech TouchPad users might be interested + in a specialized Xorg/XFree86 driver at: and a new version of GPM at: @@ -87,6 +87,27 @@ config MOUSE_PS2_TRACKPOINT If unsure, say Y. +config MOUSE_PS2_ELANTECH + bool "Elantech PS/2 protocol extension" + depends on MOUSE_PS2 + help + Say Y here if you have an Elantech PS/2 touchpad connected + to your system. + + Note that if you enable this driver you will need an updated + X.org Synaptics driver that does not require ABS_PRESSURE + reports from the touchpad (i.e. post 1.5.0 version). You can + grab a patch for the driver here: + + http://userweb.kernel.org/~dtor/synaptics-no-abspressure.patch + + If unsure, say N. + + This driver exposes some configuration registers via sysfs + entries. For further information, + see . + + config MOUSE_PS2_TOUCHKIT bool "eGalax TouchKit PS/2 protocol extension" depends on MOUSE_PS2 diff --git a/drivers/input/mouse/Makefile b/drivers/input/mouse/Makefile index 8e6e69097801..96f1dd8037f8 100644 --- a/drivers/input/mouse/Makefile +++ b/drivers/input/mouse/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_MOUSE_GPIO) += gpio_mouse.o psmouse-objs := psmouse-base.o synaptics.o psmouse-$(CONFIG_MOUSE_PS2_ALPS) += alps.o +psmouse-$(CONFIG_MOUSE_PS2_ELANTECH) += elantech.o psmouse-$(CONFIG_MOUSE_PS2_OLPC) += hgpk.o psmouse-$(CONFIG_MOUSE_PS2_LOGIPS2PP) += logips2pp.o psmouse-$(CONFIG_MOUSE_PS2_LIFEBOOK) += lifebook.o diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c new file mode 100644 index 000000000000..b9a25d57bc5e --- /dev/null +++ b/drivers/input/mouse/elantech.c @@ -0,0 +1,674 @@ +/* + * Elantech Touchpad driver (v5) + * + * Copyright (C) 2007-2008 Arjan Opmeer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Trademarks are the property of their respective owners. + */ + +#include +#include +#include +#include +#include +#include "psmouse.h" +#include "elantech.h" + +#define elantech_debug(format, arg...) \ + do { \ + if (etd->debug) \ + printk(KERN_DEBUG format, ##arg); \ + } while (0) + +/* + * Send a Synaptics style sliced query command + */ +static int synaptics_send_cmd(struct psmouse *psmouse, unsigned char c, + unsigned char *param) +{ + if (psmouse_sliced_command(psmouse, c) || + ps2_command(&psmouse->ps2dev, param, PSMOUSE_CMD_GETINFO)) { + pr_err("elantech.c: synaptics_send_cmd query 0x%02x failed.\n", c); + return -1; + } + + return 0; +} + +/* + * A retrying version of ps2_command + */ +static int elantech_ps2_command(struct psmouse *psmouse, + unsigned char *param, int command) +{ + struct ps2dev *ps2dev = &psmouse->ps2dev; + struct elantech_data *etd = psmouse->private; + int rc; + int tries = ETP_PS2_COMMAND_TRIES; + + do { + rc = ps2_command(ps2dev, param, command); + if (rc == 0) + break; + tries--; + elantech_debug("elantech.c: retrying ps2 command 0x%02x (%d).\n", + command, tries); + msleep(ETP_PS2_COMMAND_DELAY); + } while (tries > 0); + + if (rc) + pr_err("elantech.c: ps2 command 0x%02x failed.\n", command); + + return rc; +} + +/* + * Send an Elantech style special command to read a value from a register + */ +static int elantech_read_reg(struct psmouse *psmouse, unsigned char reg, + unsigned char *val) +{ + struct elantech_data *etd = psmouse->private; + unsigned char param[3]; + int rc = 0; + + if (reg < 0x10 || reg > 0x26) + return -1; + + if (reg > 0x11 && reg < 0x20) + return -1; + + switch (etd->hw_version) { + case 1: + if (psmouse_sliced_command(psmouse, ETP_REGISTER_READ) || + psmouse_sliced_command(psmouse, reg) || + ps2_command(&psmouse->ps2dev, param, PSMOUSE_CMD_GETINFO)) { + rc = -1; + } + break; + + case 2: + if (elantech_ps2_command(psmouse, NULL, ETP_PS2_CUSTOM_COMMAND) || + elantech_ps2_command(psmouse, NULL, ETP_REGISTER_READ) || + elantech_ps2_command(psmouse, NULL, ETP_PS2_CUSTOM_COMMAND) || + elantech_ps2_command(psmouse, NULL, reg) || + elantech_ps2_command(psmouse, param, PSMOUSE_CMD_GETINFO)) { + rc = -1; + } + break; + } + + if (rc) + pr_err("elantech.c: failed to read register 0x%02x.\n", reg); + else + *val = param[0]; + + return rc; +} + +/* + * Send an Elantech style special command to write a register with a value + */ +static int elantech_write_reg(struct psmouse *psmouse, unsigned char reg, + unsigned char val) +{ + struct elantech_data *etd = psmouse->private; + int rc = 0; + + if (reg < 0x10 || reg > 0x26) + return -1; + + if (reg > 0x11 && reg < 0x20) + return -1; + + switch (etd->hw_version) { + case 1: + if (psmouse_sliced_command(psmouse, ETP_REGISTER_WRITE) || + psmouse_sliced_command(psmouse, reg) || + psmouse_sliced_command(psmouse, val) || + ps2_command(&psmouse->ps2dev, NULL, PSMOUSE_CMD_SETSCALE11)) { + rc = -1; + } + break; + + case 2: + if (elantech_ps2_command(psmouse, NULL, ETP_PS2_CUSTOM_COMMAND) || + elantech_ps2_command(psmouse, NULL, ETP_REGISTER_WRITE) || + elantech_ps2_command(psmouse, NULL, ETP_PS2_CUSTOM_COMMAND) || + elantech_ps2_command(psmouse, NULL, reg) || + elantech_ps2_command(psmouse, NULL, ETP_PS2_CUSTOM_COMMAND) || + elantech_ps2_command(psmouse, NULL, val) || + elantech_ps2_command(psmouse, NULL, PSMOUSE_CMD_SETSCALE11)) { + rc = -1; + } + break; + } + + if (rc) + pr_err("elantech.c: failed to write register 0x%02x with value 0x%02x.\n", + reg, val); + + return rc; +} + +/* + * Dump a complete mouse movement packet to the syslog + */ +static void elantech_packet_dump(unsigned char *packet, int size) +{ + int i; + + printk(KERN_DEBUG "elantech.c: PS/2 packet ["); + for (i = 0; i < size; i++) + printk("%s0x%02x ", (i) ? ", " : " ", packet[i]); + printk("]\n"); +} + +/* + * Interpret complete data packets and report absolute mode input events for + * hardware version 1. (4 byte packets) + */ +static void elantech_report_absolute_v1(struct psmouse *psmouse) +{ + struct input_dev *dev = psmouse->dev; + struct elantech_data *etd = psmouse->private; + unsigned char *packet = psmouse->packet; + int fingers; + + if (etd->fw_version_maj == 0x01) { + /* byte 0: D U p1 p2 1 p3 R L + byte 1: f 0 th tw x9 x8 y9 y8 */ + fingers = ((packet[1] & 0x80) >> 7) + + ((packet[1] & 0x30) >> 4); + } else { + /* byte 0: n1 n0 p2 p1 1 p3 R L + byte 1: 0 0 0 0 x9 x8 y9 y8 */ + fingers = (packet[0] & 0xc0) >> 6; + } + + input_report_key(dev, BTN_TOUCH, fingers != 0); + + /* byte 2: x7 x6 x5 x4 x3 x2 x1 x0 + byte 3: y7 y6 y5 y4 y3 y2 y1 y0 */ + if (fingers) { + input_report_abs(dev, ABS_X, + ((packet[1] & 0x0c) << 6) | packet[2]); + input_report_abs(dev, ABS_Y, ETP_YMAX_V1 - + (((packet[1] & 0x03) << 8) | packet[3])); + } + + input_report_key(dev, BTN_TOOL_FINGER, fingers == 1); + input_report_key(dev, BTN_TOOL_DOUBLETAP, fingers == 2); + input_report_key(dev, BTN_TOOL_TRIPLETAP, fingers == 3); + input_report_key(dev, BTN_LEFT, packet[0] & 0x01); + input_report_key(dev, BTN_RIGHT, packet[0] & 0x02); + + if ((etd->fw_version_maj == 0x01) && + (etd->capabilities & ETP_CAP_HAS_ROCKER)) { + /* rocker up */ + input_report_key(dev, BTN_FORWARD, packet[0] & 0x40); + /* rocker down */ + input_report_key(dev, BTN_BACK, packet[0] & 0x80); + } + + input_sync(dev); +} + +/* + * Interpret complete data packets and report absolute mode input events for + * hardware version 2. (6 byte packets) + */ +static void elantech_report_absolute_v2(struct psmouse *psmouse) +{ + struct input_dev *dev = psmouse->dev; + unsigned char *packet = psmouse->packet; + int fingers, x1, y1, x2, y2; + + /* byte 0: n1 n0 . . . . R L */ + fingers = (packet[0] & 0xc0) >> 6; + input_report_key(dev, BTN_TOUCH, fingers != 0); + + switch (fingers) { + case 1: + /* byte 1: x15 x14 x13 x12 x11 x10 x9 x8 + byte 2: x7 x6 x5 x4 x4 x2 x1 x0 */ + input_report_abs(dev, ABS_X, (packet[1] << 8) | packet[2]); + /* byte 4: y15 y14 y13 y12 y11 y10 y8 y8 + byte 5: y7 y6 y5 y4 y3 y2 y1 y0 */ + input_report_abs(dev, ABS_Y, ETP_YMAX_V2 - + ((packet[4] << 8) | packet[5])); + break; + + case 2: + /* The coordinate of each finger is reported separately with + a lower resolution for two finger touches */ + /* byte 0: . . ay8 ax8 . . . . + byte 1: ax7 ax6 ax5 ax4 ax3 ax2 ax1 ax0 */ + x1 = ((packet[0] & 0x10) << 4) | packet[1]; + /* byte 2: ay7 ay6 ay5 ay4 ay3 ay2 ay1 ay0 */ + y1 = ETP_2FT_YMAX - (((packet[0] & 0x20) << 3) | packet[2]); + /* byte 3: . . by8 bx8 . . . . + byte 4: bx7 bx6 bx5 bx4 bx3 bx2 bx1 bx0 */ + x2 = ((packet[3] & 0x10) << 4) | packet[4]; + /* byte 5: by7 by8 by5 by4 by3 by2 by1 by0 */ + y2 = ETP_2FT_YMAX - (((packet[3] & 0x20) << 3) | packet[5]); + /* For compatibility with the X Synaptics driver scale up one + coordinate and report as ordinary mouse movent */ + input_report_abs(dev, ABS_X, x1 << 2); + input_report_abs(dev, ABS_Y, y1 << 2); + /* For compatibility with the proprietary X Elantech driver + report both coordinates as hat coordinates */ + input_report_abs(dev, ABS_HAT0X, x1); + input_report_abs(dev, ABS_HAT0Y, y1); + input_report_abs(dev, ABS_HAT1X, x2); + input_report_abs(dev, ABS_HAT1Y, y2); + break; + } + + input_report_key(dev, BTN_TOOL_FINGER, fingers == 1); + input_report_key(dev, BTN_TOOL_DOUBLETAP, fingers == 2); + input_report_key(dev, BTN_TOOL_TRIPLETAP, fingers == 3); + input_report_key(dev, BTN_LEFT, packet[0] & 0x01); + input_report_key(dev, BTN_RIGHT, packet[0] & 0x02); + + input_sync(dev); +} + +static int elantech_check_parity_v1(struct psmouse *psmouse) +{ + struct elantech_data *etd = psmouse->private; + unsigned char *packet = psmouse->packet; + unsigned char p1, p2, p3; + + /* Parity bits are placed differently */ + if (etd->fw_version_maj == 0x01) { + /* byte 0: D U p1 p2 1 p3 R L */ + p1 = (packet[0] & 0x20) >> 5; + p2 = (packet[0] & 0x10) >> 4; + } else { + /* byte 0: n1 n0 p2 p1 1 p3 R L */ + p1 = (packet[0] & 0x10) >> 4; + p2 = (packet[0] & 0x20) >> 5; + } + + p3 = (packet[0] & 0x04) >> 2; + + return etd->parity[packet[1]] == p1 && + etd->parity[packet[2]] == p2 && + etd->parity[packet[3]] == p3; +} + +/* + * Process byte stream from mouse and handle complete packets + */ +static psmouse_ret_t elantech_process_byte(struct psmouse *psmouse) +{ + struct elantech_data *etd = psmouse->private; + + if (psmouse->pktcnt < psmouse->pktsize) + return PSMOUSE_GOOD_DATA; + + if (etd->debug > 1) + elantech_packet_dump(psmouse->packet, psmouse->pktsize); + + switch (etd->hw_version) { + case 1: + if (etd->paritycheck && !elantech_check_parity_v1(psmouse)) + return PSMOUSE_BAD_DATA; + + elantech_report_absolute_v1(psmouse); + break; + + case 2: + /* We don't know how to check parity in protocol v2 */ + elantech_report_absolute_v2(psmouse); + break; + } + + return PSMOUSE_FULL_PACKET; +} + +/* + * Put the touchpad into absolute mode + */ +static int elantech_set_absolute_mode(struct psmouse *psmouse) +{ + struct elantech_data *etd = psmouse->private; + unsigned char val; + int tries = ETP_READ_BACK_TRIES; + int rc = 0; + + switch (etd->hw_version) { + case 1: + etd->reg_10 = 0x16; + etd->reg_11 = 0x8f; + if (elantech_write_reg(psmouse, 0x10, etd->reg_10) || + elantech_write_reg(psmouse, 0x11, etd->reg_11)) { + rc = -1; + } + break; + + case 2: + /* Windows driver values */ + etd->reg_10 = 0x54; + etd->reg_11 = 0x88; /* 0x8a */ + etd->reg_21 = 0x60; /* 0x00 */ + if (elantech_write_reg(psmouse, 0x10, etd->reg_10) || + elantech_write_reg(psmouse, 0x11, etd->reg_11) || + elantech_write_reg(psmouse, 0x21, etd->reg_21)) { + rc = -1; + break; + } + /* + * Read back reg 0x10. The touchpad is probably initalising + * and not ready until we read back the value we just wrote. + */ + do { + rc = elantech_read_reg(psmouse, 0x10, &val); + if (rc == 0) + break; + tries--; + elantech_debug("elantech.c: retrying read (%d).\n", + tries); + msleep(ETP_READ_BACK_DELAY); + } while (tries > 0); + if (rc) + pr_err("elantech.c: failed to read back register 0x10.\n"); + break; + } + + if (rc) + pr_err("elantech.c: failed to initialise registers.\n"); + + return rc; +} + +/* + * Set the appropriate event bits for the input subsystem + */ +static void elantech_set_input_params(struct psmouse *psmouse) +{ + struct input_dev *dev = psmouse->dev; + struct elantech_data *etd = psmouse->private; + + __set_bit(EV_KEY, dev->evbit); + __set_bit(EV_ABS, dev->evbit); + + __set_bit(BTN_LEFT, dev->keybit); + __set_bit(BTN_RIGHT, dev->keybit); + + __set_bit(BTN_TOUCH, dev->keybit); + __set_bit(BTN_TOOL_FINGER, dev->keybit); + __set_bit(BTN_TOOL_DOUBLETAP, dev->keybit); + __set_bit(BTN_TOOL_TRIPLETAP, dev->keybit); + + switch (etd->hw_version) { + case 1: + /* Rocker button */ + if ((etd->fw_version_maj == 0x01) && + (etd->capabilities & ETP_CAP_HAS_ROCKER)) { + __set_bit(BTN_FORWARD, dev->keybit); + __set_bit(BTN_BACK, dev->keybit); + } + input_set_abs_params(dev, ABS_X, ETP_XMIN_V1, ETP_XMAX_V1, 0, 0); + input_set_abs_params(dev, ABS_Y, ETP_YMIN_V1, ETP_YMAX_V1, 0, 0); + break; + + case 2: + input_set_abs_params(dev, ABS_X, ETP_XMIN_V2, ETP_XMAX_V2, 0, 0); + input_set_abs_params(dev, ABS_Y, ETP_YMIN_V2, ETP_YMAX_V2, 0, 0); + input_set_abs_params(dev, ABS_HAT0X, ETP_2FT_XMIN, ETP_2FT_XMAX, 0, 0); + input_set_abs_params(dev, ABS_HAT0Y, ETP_2FT_YMIN, ETP_2FT_YMAX, 0, 0); + input_set_abs_params(dev, ABS_HAT1X, ETP_2FT_XMIN, ETP_2FT_XMAX, 0, 0); + input_set_abs_params(dev, ABS_HAT1Y, ETP_2FT_YMIN, ETP_2FT_YMAX, 0, 0); + break; + } +} + +struct elantech_attr_data { + size_t field_offset; + unsigned char reg; +}; + +/* + * Display a register value by reading a sysfs entry + */ +static ssize_t elantech_show_int_attr(struct psmouse *psmouse, void *data, + char *buf) +{ + struct elantech_data *etd = psmouse->private; + struct elantech_attr_data *attr = data; + unsigned char *reg = (unsigned char *) etd + attr->field_offset; + int rc = 0; + + if (attr->reg) + rc = elantech_read_reg(psmouse, attr->reg, reg); + + return sprintf(buf, "0x%02x\n", (attr->reg && rc) ? -1 : *reg); +} + +/* + * Write a register value by writing a sysfs entry + */ +static ssize_t elantech_set_int_attr(struct psmouse *psmouse, + void *data, const char *buf, size_t count) +{ + struct elantech_data *etd = psmouse->private; + struct elantech_attr_data *attr = data; + unsigned char *reg = (unsigned char *) etd + attr->field_offset; + unsigned long value; + int err; + + err = strict_strtoul(buf, 16, &value); + if (err) + return err; + + if (value > 0xff) + return -EINVAL; + + /* Do we need to preserve some bits for version 2 hardware too? */ + if (etd->hw_version == 1) { + if (attr->reg == 0x10) + /* Force absolute mode always on */ + value |= ETP_R10_ABSOLUTE_MODE; + else if (attr->reg == 0x11) + /* Force 4 byte mode always on */ + value |= ETP_R11_4_BYTE_MODE; + } + + if (!attr->reg || elantech_write_reg(psmouse, attr->reg, value) == 0) + *reg = value; + + return count; +} + +#define ELANTECH_INT_ATTR(_name, _register) \ + static struct elantech_attr_data elantech_attr_##_name = { \ + .field_offset = offsetof(struct elantech_data, _name), \ + .reg = _register, \ + }; \ + PSMOUSE_DEFINE_ATTR(_name, S_IWUSR | S_IRUGO, \ + &elantech_attr_##_name, \ + elantech_show_int_attr, \ + elantech_set_int_attr) + +ELANTECH_INT_ATTR(reg_10, 0x10); +ELANTECH_INT_ATTR(reg_11, 0x11); +ELANTECH_INT_ATTR(reg_20, 0x20); +ELANTECH_INT_ATTR(reg_21, 0x21); +ELANTECH_INT_ATTR(reg_22, 0x22); +ELANTECH_INT_ATTR(reg_23, 0x23); +ELANTECH_INT_ATTR(reg_24, 0x24); +ELANTECH_INT_ATTR(reg_25, 0x25); +ELANTECH_INT_ATTR(reg_26, 0x26); +ELANTECH_INT_ATTR(debug, 0); +ELANTECH_INT_ATTR(paritycheck, 0); + +static struct attribute *elantech_attrs[] = { + &psmouse_attr_reg_10.dattr.attr, + &psmouse_attr_reg_11.dattr.attr, + &psmouse_attr_reg_20.dattr.attr, + &psmouse_attr_reg_21.dattr.attr, + &psmouse_attr_reg_22.dattr.attr, + &psmouse_attr_reg_23.dattr.attr, + &psmouse_attr_reg_24.dattr.attr, + &psmouse_attr_reg_25.dattr.attr, + &psmouse_attr_reg_26.dattr.attr, + &psmouse_attr_debug.dattr.attr, + &psmouse_attr_paritycheck.dattr.attr, + NULL +}; + +static struct attribute_group elantech_attr_group = { + .attrs = elantech_attrs, +}; + +/* + * Use magic knock to detect Elantech touchpad + */ +int elantech_detect(struct psmouse *psmouse, int set_properties) +{ + struct ps2dev *ps2dev = &psmouse->ps2dev; + unsigned char param[3]; + + ps2_command(&psmouse->ps2dev, NULL, PSMOUSE_CMD_RESET_DIS); + + if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || + ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE11) || + ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE11) || + ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE11) || + ps2_command(ps2dev, param, PSMOUSE_CMD_GETINFO)) { + pr_err("elantech.c: sending Elantech magic knock failed.\n"); + return -1; + } + + /* + * Report this in case there are Elantech models that use a different + * set of magic numbers + */ + if (param[0] != 0x3c || param[1] != 0x03 || param[2] != 0xc8) { + pr_info("elantech.c: unexpected magic knock result 0x%02x, 0x%02x, 0x%02x.\n", + param[0], param[1], param[2]); + return -1; + } + + if (set_properties) { + psmouse->vendor = "Elantech"; + psmouse->name = "Touchpad"; + } + + return 0; +} + +/* + * Clean up sysfs entries when disconnecting + */ +static void elantech_disconnect(struct psmouse *psmouse) +{ + sysfs_remove_group(&psmouse->ps2dev.serio->dev.kobj, + &elantech_attr_group); + kfree(psmouse->private); + psmouse->private = NULL; +} + +/* + * Put the touchpad back into absolute mode when reconnecting + */ +static int elantech_reconnect(struct psmouse *psmouse) +{ + if (elantech_detect(psmouse, 0)) + return -1; + + if (elantech_set_absolute_mode(psmouse)) { + pr_err("elantech.c: failed to put touchpad back into absolute mode.\n"); + return -1; + } + + return 0; +} + +/* + * Initialize the touchpad and create sysfs entries + */ +int elantech_init(struct psmouse *psmouse) +{ + struct elantech_data *etd; + int i, error; + unsigned char param[3]; + + etd = kzalloc(sizeof(struct elantech_data), GFP_KERNEL); + psmouse->private = etd; + if (!etd) + return -1; + + etd->parity[0] = 1; + for (i = 1; i < 256; i++) + etd->parity[i] = etd->parity[i & (i - 1)] ^ 1; + + /* + * Find out what version hardware this is + */ + if (synaptics_send_cmd(psmouse, ETP_FW_VERSION_QUERY, param)) { + pr_err("elantech.c: failed to query firmware version.\n"); + goto init_fail; + } + pr_info("elantech.c: Elantech version query result 0x%02x, 0x%02x, 0x%02x.\n", + param[0], param[1], param[2]); + etd->fw_version_maj = param[0]; + etd->fw_version_min = param[2]; + + /* + * Assume every version greater than this is new EeePC style + * hardware with 6 byte packets + */ + if (etd->fw_version_maj >= 0x02 && etd->fw_version_min >= 0x30) { + etd->hw_version = 2; + /* For now show extra debug information */ + etd->debug = 1; + /* Don't know how to do parity checking for version 2 */ + etd->paritycheck = 0; + } else { + etd->hw_version = 1; + etd->paritycheck = 1; + } + pr_info("elantech.c: assuming hardware version %d, firmware version %d.%d\n", + etd->hw_version, etd->fw_version_maj, etd->fw_version_min); + + if (synaptics_send_cmd(psmouse, ETP_CAPABILITIES_QUERY, param)) { + pr_err("elantech.c: failed to query capabilities.\n"); + goto init_fail; + } + pr_info("elantech.c: Synaptics capabilities query result 0x%02x, 0x%02x, 0x%02x.\n", + param[0], param[1], param[2]); + etd->capabilities = param[0]; + + if (elantech_set_absolute_mode(psmouse)) { + pr_err("elantech.c: failed to put touchpad into absolute mode.\n"); + goto init_fail; + } + + elantech_set_input_params(psmouse); + + error = sysfs_create_group(&psmouse->ps2dev.serio->dev.kobj, + &elantech_attr_group); + if (error) { + pr_err("elantech.c: failed to create sysfs attributes, error: %d.\n", + error); + goto init_fail; + } + + psmouse->protocol_handler = elantech_process_byte; + psmouse->disconnect = elantech_disconnect; + psmouse->reconnect = elantech_reconnect; + psmouse->pktsize = etd->hw_version == 2 ? 6 : 4; + + return 0; + + init_fail: + kfree(etd); + return -1; +} diff --git a/drivers/input/mouse/elantech.h b/drivers/input/mouse/elantech.h new file mode 100644 index 000000000000..bee282b540bc --- /dev/null +++ b/drivers/input/mouse/elantech.h @@ -0,0 +1,124 @@ +/* + * Elantech Touchpad driver (v5) + * + * Copyright (C) 2007-2008 Arjan Opmeer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Trademarks are the property of their respective owners. + */ + +#ifndef _ELANTECH_H +#define _ELANTECH_H + +/* + * Command values for Synaptics style queries + */ +#define ETP_FW_VERSION_QUERY 0x01 +#define ETP_CAPABILITIES_QUERY 0x02 + +/* + * Command values for register reading or writing + */ +#define ETP_REGISTER_READ 0x10 +#define ETP_REGISTER_WRITE 0x11 + +/* + * Hardware version 2 custom PS/2 command value + */ +#define ETP_PS2_CUSTOM_COMMAND 0xf8 + +/* + * Times to retry a ps2_command and millisecond delay between tries + */ +#define ETP_PS2_COMMAND_TRIES 3 +#define ETP_PS2_COMMAND_DELAY 500 + +/* + * Times to try to read back a register and millisecond delay between tries + */ +#define ETP_READ_BACK_TRIES 5 +#define ETP_READ_BACK_DELAY 2000 + +/* + * Register bitmasks for hardware version 1 + */ +#define ETP_R10_ABSOLUTE_MODE 0x04 +#define ETP_R11_4_BYTE_MODE 0x02 + +/* + * Capability bitmasks + */ +#define ETP_CAP_HAS_ROCKER 0x04 + +/* + * One hard to find application note states that X axis range is 0 to 576 + * and Y axis range is 0 to 384 for harware version 1. + * Edge fuzz might be necessary because of bezel around the touchpad + */ +#define ETP_EDGE_FUZZ_V1 32 + +#define ETP_XMIN_V1 ( 0 + ETP_EDGE_FUZZ_V1) +#define ETP_XMAX_V1 (576 - ETP_EDGE_FUZZ_V1) +#define ETP_YMIN_V1 ( 0 + ETP_EDGE_FUZZ_V1) +#define ETP_YMAX_V1 (384 - ETP_EDGE_FUZZ_V1) + +/* + * It seems the resolution for hardware version 2 doubled. + * Hence the X and Y ranges are doubled too. + * The bezel around the pad also appears to be smaller + */ +#define ETP_EDGE_FUZZ_V2 8 + +#define ETP_XMIN_V2 ( 0 + ETP_EDGE_FUZZ_V2) +#define ETP_XMAX_V2 (1152 - ETP_EDGE_FUZZ_V2) +#define ETP_YMIN_V2 ( 0 + ETP_EDGE_FUZZ_V2) +#define ETP_YMAX_V2 ( 768 - ETP_EDGE_FUZZ_V2) + +/* + * For two finger touches the coordinate of each finger gets reported + * separately but with reduced resolution. + */ +#define ETP_2FT_FUZZ 4 + +#define ETP_2FT_XMIN ( 0 + ETP_2FT_FUZZ) +#define ETP_2FT_XMAX (288 - ETP_2FT_FUZZ) +#define ETP_2FT_YMIN ( 0 + ETP_2FT_FUZZ) +#define ETP_2FT_YMAX (192 - ETP_2FT_FUZZ) + +struct elantech_data { + unsigned char reg_10; + unsigned char reg_11; + unsigned char reg_20; + unsigned char reg_21; + unsigned char reg_22; + unsigned char reg_23; + unsigned char reg_24; + unsigned char reg_25; + unsigned char reg_26; + unsigned char debug; + unsigned char capabilities; + unsigned char fw_version_maj; + unsigned char fw_version_min; + unsigned char hw_version; + unsigned char paritycheck; + unsigned char parity[256]; +}; + +#ifdef CONFIG_MOUSE_PS2_ELANTECH +int elantech_detect(struct psmouse *psmouse, int set_properties); +int elantech_init(struct psmouse *psmouse); +#else +static inline int elantech_detect(struct psmouse *psmouse, int set_properties) +{ + return -ENOSYS; +} +static inline int elantech_init(struct psmouse *psmouse) +{ + return -ENOSYS; +} +#endif /* CONFIG_MOUSE_PS2_ELANTECH */ + +#endif diff --git a/drivers/input/mouse/hgpk.c b/drivers/input/mouse/hgpk.c index e82d34201e97..88f04bf2ad6c 100644 --- a/drivers/input/mouse/hgpk.c +++ b/drivers/input/mouse/hgpk.c @@ -125,7 +125,7 @@ static void hgpk_spewing_hack(struct psmouse *psmouse, */ static int hgpk_validate_byte(unsigned char *packet) { - return (packet[0] & 0x0C) == 0x08; + return (packet[0] & 0x0C) != 0x08; } static void hgpk_process_packet(struct psmouse *psmouse) diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c index 126e977e199e..f8f86de694bb 100644 --- a/drivers/input/mouse/psmouse-base.c +++ b/drivers/input/mouse/psmouse-base.c @@ -29,6 +29,7 @@ #include "lifebook.h" #include "trackpoint.h" #include "touchkit_ps2.h" +#include "elantech.h" #define DRIVER_DESC "PS/2 mouse driver" @@ -650,6 +651,19 @@ static int psmouse_extensions(struct psmouse *psmouse, max_proto = PSMOUSE_IMEX; } +/* + * Try Elantech touchpad. + */ + if (max_proto > PSMOUSE_IMEX && + elantech_detect(psmouse, set_properties) == 0) { + if (!set_properties || elantech_init(psmouse) == 0) + return PSMOUSE_ELANTECH; +/* + * Init failed, try basic relative protocols + */ + max_proto = PSMOUSE_IMEX; + } + if (max_proto > PSMOUSE_IMEX) { if (genius_detect(psmouse, set_properties) == 0) return PSMOUSE_GENPS; @@ -789,6 +803,15 @@ static const struct psmouse_protocol psmouse_protocols[] = { .detect = hgpk_detect, }, #endif +#ifdef CONFIG_MOUSE_PS2_ELANTECH + { + .type = PSMOUSE_ELANTECH, + .name = "ETPS/2", + .alias = "elantech", + .detect = elantech_detect, + .init = elantech_init, + }, + #endif { .type = PSMOUSE_CORTRON, .name = "CortronPS/2", diff --git a/drivers/input/mouse/psmouse.h b/drivers/input/mouse/psmouse.h index 8b608a1cdd12..54ed267894bd 100644 --- a/drivers/input/mouse/psmouse.h +++ b/drivers/input/mouse/psmouse.h @@ -90,6 +90,7 @@ enum psmouse_type { PSMOUSE_TOUCHKIT_PS2, PSMOUSE_CORTRON, PSMOUSE_HGPK, + PSMOUSE_ELANTECH, PSMOUSE_AUTO /* This one should always be last */ }; diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c index 8137e50ded87..d8c056fe7e98 100644 --- a/drivers/input/mousedev.c +++ b/drivers/input/mousedev.c @@ -519,7 +519,6 @@ static int mousedev_release(struct inode *inode, struct file *file) struct mousedev_client *client = file->private_data; struct mousedev *mousedev = client->mousedev; - mousedev_fasync(-1, file, 0); mousedev_detach_client(mousedev, client); kfree(client); diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index a321aea2c7b5..29e686388a2c 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -135,6 +135,14 @@ static struct dmi_system_id __initdata i8042_dmi_noloop_table[] = { DMI_MATCH(DMI_PRODUCT_VERSION, "5a"), }, }, + { + .ident = "Blue FB5601", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "blue"), + DMI_MATCH(DMI_PRODUCT_NAME, "FB5601"), + DMI_MATCH(DMI_PRODUCT_VERSION, "M606"), + }, + }, { } }; @@ -329,6 +337,20 @@ static struct dmi_system_id __initdata i8042_dmi_nomux_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "2656"), }, }, + { + .ident = "Dell XPS M1530", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "XPS M1530"), + }, + }, + { + .ident = "Compal HEL80I", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "COMPAL"), + DMI_MATCH(DMI_PRODUCT_NAME, "HEL80I"), + }, + }, { } }; diff --git a/drivers/input/serio/serio_raw.c b/drivers/input/serio/serio_raw.c index 470770c09260..06bbd0e74c6f 100644 --- a/drivers/input/serio/serio_raw.c +++ b/drivers/input/serio/serio_raw.c @@ -135,7 +135,6 @@ static int serio_raw_release(struct inode *inode, struct file *file) mutex_lock(&serio_raw_mutex); - serio_raw_fasync(-1, file, 0); serio_raw_cleanup(serio_raw); mutex_unlock(&serio_raw_mutex); diff --git a/drivers/input/tablet/wacom.h b/drivers/input/tablet/wacom.h index ca62ec639f8f..677680e9f54f 100644 --- a/drivers/input/tablet/wacom.h +++ b/drivers/input/tablet/wacom.h @@ -66,6 +66,7 @@ * - Support Intuos3 4x6 * v1.47 (pc) - Added support for Bamboo * v1.48 (pc) - Added support for Bamboo1, BambooFun, and Cintiq 12WX + * v1.49 (pc) - Added support for USB Tablet PC (0x90, 0x93, and 0x9A) */ /* @@ -86,7 +87,7 @@ /* * Version Information */ -#define DRIVER_VERSION "v1.48" +#define DRIVER_VERSION "v1.49" #define DRIVER_AUTHOR "Vojtech Pavlik " #define DRIVER_DESC "USB Wacom Graphire and Wacom Intuos tablet driver" #define DRIVER_LICENSE "GPL" @@ -103,15 +104,15 @@ struct wacom { struct usb_device *usbdev; struct usb_interface *intf; struct urb *irq; - struct wacom_wac * wacom_wac; + struct wacom_wac *wacom_wac; struct mutex lock; unsigned int open:1; char phys[32]; }; struct wacom_combo { - struct wacom * wacom; - struct urb * urb; + struct wacom *wacom; + struct urb *urb; }; extern int wacom_wac_irq(struct wacom_wac * wacom_wac, void * wcombo); @@ -132,7 +133,7 @@ extern void input_dev_mo(struct input_dev *input_dev, struct wacom_wac *wacom_wa extern void input_dev_bee(struct input_dev *input_dev, struct wacom_wac *wacom_wac); extern __u16 wacom_le16_to_cpu(unsigned char *data); extern __u16 wacom_be16_to_cpu(unsigned char *data); -extern struct wacom_features * get_wacom_feature(const struct usb_device_id *id); -extern const struct usb_device_id * get_device_table(void); +extern struct wacom_features *get_wacom_feature(const struct usb_device_id *id); +extern const struct usb_device_id *get_device_table(void); #endif diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c index 09e227aa0d49..484496daa0f3 100644 --- a/drivers/input/tablet/wacom_sys.c +++ b/drivers/input/tablet/wacom_sys.c @@ -14,8 +14,41 @@ #include "wacom.h" #include "wacom_wac.h" +/* defines to get HID report descriptor */ +#define HID_DEVICET_HID (USB_TYPE_CLASS | 0x01) +#define HID_DEVICET_REPORT (USB_TYPE_CLASS | 0x02) +#define HID_USAGE_UNDEFINED 0x00 +#define HID_USAGE_PAGE 0x05 +#define HID_USAGE_PAGE_DIGITIZER 0x0d +#define HID_USAGE_PAGE_DESKTOP 0x01 +#define HID_USAGE 0x09 +#define HID_USAGE_X 0x30 +#define HID_USAGE_Y 0x31 +#define HID_USAGE_X_TILT 0x3d +#define HID_USAGE_Y_TILT 0x3e +#define HID_USAGE_FINGER 0x22 +#define HID_USAGE_STYLUS 0x20 +#define HID_COLLECTION 0xc0 + +enum { + WCM_UNDEFINED = 0, + WCM_DESKTOP, + WCM_DIGITIZER, +}; + +struct hid_descriptor { + struct usb_descriptor_header header; + __le16 bcdHID; + u8 bCountryCode; + u8 bNumDescriptors; + u8 bDescriptorType; + __le16 wDescriptorLength; +} __attribute__ ((packed)); + +/* defines to get/set USB message */ #define USB_REQ_GET_REPORT 0x01 #define USB_REQ_SET_REPORT 0x09 +#define WAC_HID_FEATURE_REPORT 0x03 static int usb_get_report(struct usb_interface *intf, unsigned char type, unsigned char id, void *buf, int size) @@ -80,25 +113,21 @@ static void wacom_sys_irq(struct urb *urb) void wacom_report_key(void *wcombo, unsigned int key_type, int key_data) { input_report_key(get_input_dev((struct wacom_combo *)wcombo), key_type, key_data); - return; } void wacom_report_abs(void *wcombo, unsigned int abs_type, int abs_data) { input_report_abs(get_input_dev((struct wacom_combo *)wcombo), abs_type, abs_data); - return; } void wacom_report_rel(void *wcombo, unsigned int rel_type, int rel_data) { input_report_rel(get_input_dev((struct wacom_combo *)wcombo), rel_type, rel_data); - return; } void wacom_input_event(void *wcombo, unsigned int type, unsigned int code, int value) { input_event(get_input_dev((struct wacom_combo *)wcombo), type, code, value); - return; } __u16 wacom_be16_to_cpu(unsigned char *data) @@ -118,7 +147,6 @@ __u16 wacom_le16_to_cpu(unsigned char *data) void wacom_input_sync(void *wcombo) { input_sync(get_input_dev((struct wacom_combo *)wcombo)); - return; } static int wacom_open(struct input_dev *dev) @@ -160,7 +188,7 @@ static void wacom_close(struct input_dev *dev) void input_dev_mo(struct input_dev *input_dev, struct wacom_wac *wacom_wac) { - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_1) | + input_dev->keybit[BIT_WORD(BTN_MISC)] |= BIT_MASK(BTN_1) | BIT_MASK(BTN_5); input_set_abs_params(input_dev, ABS_WHEEL, 0, 71, 0, 0); } @@ -170,7 +198,7 @@ void input_dev_g4(struct input_dev *input_dev, struct wacom_wac *wacom_wac) input_dev->evbit[0] |= BIT_MASK(EV_MSC); input_dev->mscbit[0] |= BIT_MASK(MSC_SERIAL); input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_FINGER); - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_0) | + input_dev->keybit[BIT_WORD(BTN_MISC)] |= BIT_MASK(BTN_0) | BIT_MASK(BTN_4); } @@ -178,7 +206,7 @@ void input_dev_g(struct input_dev *input_dev, struct wacom_wac *wacom_wac) { input_dev->evbit[0] |= BIT_MASK(EV_REL); input_dev->relbit[0] |= BIT_MASK(REL_WHEEL); - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_LEFT) | + input_dev->keybit[BIT_WORD(BTN_MOUSE)] |= BIT_MASK(BTN_LEFT) | BIT_MASK(BTN_RIGHT) | BIT_MASK(BTN_MIDDLE); input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_RUBBER) | BIT_MASK(BTN_TOOL_MOUSE) | BIT_MASK(BTN_STYLUS2); @@ -188,7 +216,7 @@ void input_dev_g(struct input_dev *input_dev, struct wacom_wac *wacom_wac) void input_dev_i3s(struct input_dev *input_dev, struct wacom_wac *wacom_wac) { input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_FINGER); - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_0) | + input_dev->keybit[BIT_WORD(BTN_MISC)] |= BIT_MASK(BTN_0) | BIT_MASK(BTN_1) | BIT_MASK(BTN_2) | BIT_MASK(BTN_3); input_set_abs_params(input_dev, ABS_RX, 0, 4096, 0, 0); input_set_abs_params(input_dev, ABS_Z, -900, 899, 0, 0); @@ -196,14 +224,14 @@ void input_dev_i3s(struct input_dev *input_dev, struct wacom_wac *wacom_wac) void input_dev_i3(struct input_dev *input_dev, struct wacom_wac *wacom_wac) { - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_4) | + input_dev->keybit[BIT_WORD(BTN_MISC)] |= BIT_MASK(BTN_4) | BIT_MASK(BTN_5) | BIT_MASK(BTN_6) | BIT_MASK(BTN_7); input_set_abs_params(input_dev, ABS_RY, 0, 4096, 0, 0); } void input_dev_bee(struct input_dev *input_dev, struct wacom_wac *wacom_wac) { - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_8) | BIT_MASK(BTN_9); + input_dev->keybit[BIT_WORD(BTN_MISC)] |= BIT_MASK(BTN_8) | BIT_MASK(BTN_9); } void input_dev_i(struct input_dev *input_dev, struct wacom_wac *wacom_wac) @@ -211,7 +239,7 @@ void input_dev_i(struct input_dev *input_dev, struct wacom_wac *wacom_wac) input_dev->evbit[0] |= BIT_MASK(EV_MSC) | BIT_MASK(EV_REL); input_dev->mscbit[0] |= BIT_MASK(MSC_SERIAL); input_dev->relbit[0] |= BIT_MASK(REL_WHEEL); - input_dev->keybit[BIT_WORD(BTN_LEFT)] |= BIT_MASK(BTN_LEFT) | + input_dev->keybit[BIT_WORD(BTN_MOUSE)] |= BIT_MASK(BTN_LEFT) | BIT_MASK(BTN_RIGHT) | BIT_MASK(BTN_MIDDLE) | BIT_MASK(BTN_SIDE) | BIT_MASK(BTN_EXTRA); input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_RUBBER) | @@ -228,8 +256,7 @@ void input_dev_i(struct input_dev *input_dev, struct wacom_wac *wacom_wac) void input_dev_pl(struct input_dev *input_dev, struct wacom_wac *wacom_wac) { - input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_STYLUS2) | - BIT_MASK(BTN_TOOL_RUBBER); + input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_STYLUS2); } void input_dev_pt(struct input_dev *input_dev, struct wacom_wac *wacom_wac) @@ -237,15 +264,129 @@ void input_dev_pt(struct input_dev *input_dev, struct wacom_wac *wacom_wac) input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_RUBBER); } +static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hid_desc, + struct wacom_wac *wacom_wac) +{ + struct usb_device *dev = interface_to_usbdev(intf); + struct wacom_features *features = wacom_wac->features; + char limit = 0, result = 0; + int i = 0, usage = WCM_UNDEFINED, finger = 0, pen = 0; + unsigned char *report; + + report = kzalloc(hid_desc->wDescriptorLength, GFP_KERNEL); + if (!report) + return -ENOMEM; + + /* retrive report descriptors */ + do { + result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, + USB_RECIP_INTERFACE | USB_DIR_IN, + HID_DEVICET_REPORT << 8, + intf->altsetting[0].desc.bInterfaceNumber, /* interface */ + report, + hid_desc->wDescriptorLength, + 5000); /* 5 secs */ + } while (result < 0 && limit++ < 5); + + if (result < 0) + goto out; + + for (i = 0; i < hid_desc->wDescriptorLength; i++) { + + switch (report[i]) { + case HID_USAGE_PAGE: + switch (report[i + 1]) { + case HID_USAGE_PAGE_DIGITIZER: + usage = WCM_DIGITIZER; + i++; + break; + + case HID_USAGE_PAGE_DESKTOP: + usage = WCM_DESKTOP; + i++; + break; + } + break; + + case HID_USAGE: + switch (report[i + 1]) { + case HID_USAGE_X: + if (usage == WCM_DESKTOP) { + if (finger) { + features->touch_x_max = + features->touch_y_max = + wacom_le16_to_cpu(&report[i + 3]); + features->x_max = + wacom_le16_to_cpu(&report[i + 6]); + i += 7; + } else if (pen) { + features->x_max = + wacom_le16_to_cpu(&report[i + 3]); + i += 4; + } + } else if (usage == WCM_DIGITIZER) { + /* max pressure isn't reported + features->pressure_max = (unsigned short) + (report[i+4] << 8 | report[i + 3]); + */ + features->pressure_max = 255; + i += 4; + } + break; + + case HID_USAGE_Y: + if (usage == WCM_DESKTOP) + features->y_max = + wacom_le16_to_cpu(&report[i + 3]); + i += 4; + break; + + case HID_USAGE_FINGER: + finger = 1; + i++; + break; + + case HID_USAGE_STYLUS: + pen = 1; + i++; + break; + + case HID_USAGE_UNDEFINED: + if (usage == WCM_DESKTOP && finger) /* capacity */ + features->pressure_max = + wacom_le16_to_cpu(&report[i + 3]); + i += 4; + break; + } + break; + + case HID_COLLECTION: + /* reset UsagePage ans Finger */ + finger = usage = 0; + break; + } + } + + result = 0; + + out: + kfree(report); + return result; +} + static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *id) { struct usb_device *dev = interface_to_usbdev(intf); + struct usb_host_interface *interface = intf->cur_altsetting; struct usb_endpoint_descriptor *endpoint; struct wacom *wacom; struct wacom_wac *wacom_wac; + struct wacom_features *features; struct input_dev *input_dev; int error = -ENOMEM; char rep_data[2], limit = 0; + struct hid_descriptor *hid_desc; wacom = kzalloc(sizeof(struct wacom), GFP_KERNEL); wacom_wac = kzalloc(sizeof(struct wacom_wac), GFP_KERNEL); @@ -268,8 +409,8 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i usb_make_path(dev, wacom->phys, sizeof(wacom->phys)); strlcat(wacom->phys, "/input0", sizeof(wacom->phys)); - wacom_wac->features = get_wacom_feature(id); - BUG_ON(wacom_wac->features->pktlen > 10); + wacom_wac->features = features = get_wacom_feature(id); + BUG_ON(features->pktlen > 10); input_dev->name = wacom_wac->features->name; wacom->wacom_wac = wacom_wac; @@ -282,18 +423,37 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i input_dev->open = wacom_open; input_dev->close = wacom_close; + endpoint = &intf->cur_altsetting->endpoint[0].desc; + + /* TabletPC need to retrieve the physical and logical maximum from report descriptor */ + if (wacom_wac->features->type == TABLETPC) { + if (usb_get_extra_descriptor(interface, HID_DEVICET_HID, &hid_desc)) { + if (usb_get_extra_descriptor(&interface->endpoint[0], + HID_DEVICET_REPORT, &hid_desc)) { + printk("wacom: can not retrive extra class descriptor\n"); + goto fail2; + } + } + error = wacom_parse_hid(intf, hid_desc, wacom_wac); + if (error) + goto fail2; + } + input_dev->evbit[0] |= BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_PEN) | BIT_MASK(BTN_TOUCH) | BIT_MASK(BTN_STYLUS); - input_set_abs_params(input_dev, ABS_X, 0, wacom_wac->features->x_max, 4, 0); - input_set_abs_params(input_dev, ABS_Y, 0, wacom_wac->features->y_max, 4, 0); - input_set_abs_params(input_dev, ABS_PRESSURE, 0, wacom_wac->features->pressure_max, 0, 0); + input_set_abs_params(input_dev, ABS_X, 0, features->x_max, 4, 0); + input_set_abs_params(input_dev, ABS_Y, 0, features->y_max, 4, 0); + input_set_abs_params(input_dev, ABS_PRESSURE, 0, features->pressure_max, 0, 0); + if (features->type == TABLETPC) { + input_dev->keybit[BIT_WORD(BTN_DIGI)] |= BIT_MASK(BTN_TOOL_DOUBLETAP); + input_set_abs_params(input_dev, ABS_RX, 0, features->touch_x_max, 4, 0); + input_set_abs_params(input_dev, ABS_RY, 0, features->touch_y_max, 4, 0); + } input_dev->absbit[BIT_WORD(ABS_MISC)] |= BIT_MASK(ABS_MISC); wacom_init_input_dev(input_dev, wacom_wac); - endpoint = &intf->cur_altsetting->endpoint[0].desc; - usb_fill_int_urb(wacom->irq, dev, usb_rcvintpipe(dev, endpoint->bEndpointAddress), wacom_wac->data, wacom_wac->features->pktlen, @@ -305,13 +465,22 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i if (error) goto fail3; - /* Ask the tablet to report tablet data. Repeat until it succeeds */ - do { - rep_data[0] = 2; - rep_data[1] = 2; - usb_set_report(intf, 3, 2, rep_data, 2); - usb_get_report(intf, 3, 2, rep_data, 2); - } while (rep_data[1] != 2 && limit++ < 5); + /* + * Ask the tablet to report tablet data if it is not a Tablet PC. + * Repeat until it succeeds + */ + if (wacom_wac->features->type != TABLETPC) { + do { + rep_data[0] = 2; + rep_data[1] = 2; + error = usb_set_report(intf, WAC_HID_FEATURE_REPORT, + 2, rep_data, 2); + if (error >= 0) + error = usb_get_report(intf, + WAC_HID_FEATURE_REPORT, 2, + rep_data, 2); + } while ((error < 0 || rep_data[1] != 2) && limit++ < 5); + } usb_set_intfdata(intf, wacom); return 0; @@ -333,7 +502,8 @@ static void wacom_disconnect(struct usb_interface *intf) usb_kill_urb(wacom->irq); input_unregister_device(wacom->dev); usb_free_urb(wacom->irq); - usb_buffer_free(interface_to_usbdev(intf), 10, wacom->wacom_wac->data, wacom->data_dma); + usb_buffer_free(interface_to_usbdev(intf), 10, + wacom->wacom_wac->data, wacom->data_dma); kfree(wacom->wacom_wac); kfree(wacom); } diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c index bf3d9a8b2c1b..8dc8d1e59bea 100644 --- a/drivers/input/tablet/wacom_wac.c +++ b/drivers/input/tablet/wacom_wac.c @@ -535,31 +535,147 @@ static int wacom_intuos_irq(struct wacom_wac *wacom, void *wcombo) return 1; } +int wacom_tpc_irq(struct wacom_wac *wacom, void *wcombo) +{ + char *data = wacom->data; + int prox = 0, pressure; + static int stylusInProx, touchInProx = 1, touchOut; + struct urb *urb = ((struct wacom_combo *)wcombo)->urb; + + dbg("wacom_tpc_irq: received report #%d", data[0]); + + if (urb->actual_length == 5 || data[0] == 6) { /* Touch data */ + if (urb->actual_length == 5) { /* with touch */ + prox = data[0] & 0x03; + } else { /* with capacity */ + prox = data[1] & 0x03; + } + + if (!stylusInProx) { /* stylus not in prox */ + if (prox) { + if (touchInProx) { + wacom->tool[1] = BTN_TOOL_DOUBLETAP; + wacom->id[0] = TOUCH_DEVICE_ID; + if (urb->actual_length != 5) { + wacom_report_abs(wcombo, ABS_X, wacom_le16_to_cpu(&data[2])); + wacom_report_abs(wcombo, ABS_Y, wacom_le16_to_cpu(&data[4])); + wacom_report_abs(wcombo, ABS_PRESSURE, wacom_le16_to_cpu(&data[6])); + wacom_report_key(wcombo, BTN_TOUCH, wacom_le16_to_cpu(&data[6])); + } else { + wacom_report_abs(wcombo, ABS_X, wacom_le16_to_cpu(&data[1])); + wacom_report_abs(wcombo, ABS_Y, wacom_le16_to_cpu(&data[3])); + wacom_report_key(wcombo, BTN_TOUCH, 1); + } + wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); + wacom_report_key(wcombo, wacom->tool[1], prox & 0x01); + touchOut = 1; + return 1; + } + } else { + wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); + wacom_report_key(wcombo, wacom->tool[1], prox & 0x01); + wacom_report_key(wcombo, BTN_TOUCH, 0); + touchOut = 0; + touchInProx = 1; + return 1; + } + } else if (touchOut || !prox) { /* force touch out-prox */ + wacom_report_abs(wcombo, ABS_MISC, TOUCH_DEVICE_ID); + wacom_report_key(wcombo, BTN_TOUCH, 0); + touchOut = 0; + touchInProx = 1; + return 1; + } + } else if (data[0] == 2) { /* Penabled */ + prox = data[1] & 0x20; + + touchInProx = 0; + + wacom->id[0] = ERASER_DEVICE_ID; + + /* + * if going from out of proximity into proximity select between the eraser + * and the pen based on the state of the stylus2 button, choose eraser if + * pressed else choose pen. if not a proximity change from out to in, send + * an out of proximity for previous tool then a in for new tool. + */ + if (prox) { /* in prox */ + if (!wacom->tool[0]) { + /* Going into proximity select tool */ + wacom->tool[1] = (data[1] & 0x08) ? BTN_TOOL_RUBBER : BTN_TOOL_PEN; + if (wacom->tool[1] == BTN_TOOL_PEN) + wacom->id[0] = STYLUS_DEVICE_ID; + } else if (wacom->tool[1] == BTN_TOOL_RUBBER && !(data[1] & 0x08)) { + /* + * was entered with stylus2 pressed + * report out proximity for previous tool + */ + wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); + wacom_report_key(wcombo, wacom->tool[1], 0); + wacom_input_sync(wcombo); + + /* set new tool */ + wacom->tool[1] = BTN_TOOL_PEN; + wacom->id[0] = STYLUS_DEVICE_ID; + return 0; + } + if (wacom->tool[1] != BTN_TOOL_RUBBER) { + /* Unknown tool selected default to pen tool */ + wacom->tool[1] = BTN_TOOL_PEN; + wacom->id[0] = STYLUS_DEVICE_ID; + } + wacom_report_key(wcombo, BTN_STYLUS, data[1] & 0x02); + wacom_report_key(wcombo, BTN_STYLUS2, data[1] & 0x10); + wacom_report_abs(wcombo, ABS_X, wacom_le16_to_cpu(&data[2])); + wacom_report_abs(wcombo, ABS_Y, wacom_le16_to_cpu(&data[4])); + pressure = ((data[7] & 0x01) << 8) | data[6]; + if (pressure < 0) + pressure = wacom->features->pressure_max + pressure + 1; + wacom_report_abs(wcombo, ABS_PRESSURE, pressure); + wacom_report_key(wcombo, BTN_TOUCH, pressure); + } else { + wacom_report_abs(wcombo, ABS_PRESSURE, 0); + wacom_report_key(wcombo, BTN_STYLUS, 0); + wacom_report_key(wcombo, BTN_STYLUS2, 0); + wacom_report_key(wcombo, BTN_TOUCH, 0); + } + wacom_report_key(wcombo, wacom->tool[1], prox); + wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); + stylusInProx = prox; + wacom->tool[0] = prox; + return 1; + } + return 0; +} + int wacom_wac_irq(struct wacom_wac *wacom_wac, void *wcombo) { switch (wacom_wac->features->type) { case PENPARTNER: - return (wacom_penpartner_irq(wacom_wac, wcombo)); - break; + return wacom_penpartner_irq(wacom_wac, wcombo); + case PL: - return (wacom_pl_irq(wacom_wac, wcombo)); - break; + return wacom_pl_irq(wacom_wac, wcombo); + case WACOM_G4: case GRAPHIRE: case WACOM_MO: - return (wacom_graphire_irq(wacom_wac, wcombo)); - break; + return wacom_graphire_irq(wacom_wac, wcombo); + case PTU: - return (wacom_ptu_irq(wacom_wac, wcombo)); - break; + return wacom_ptu_irq(wacom_wac, wcombo); + case INTUOS: case INTUOS3S: case INTUOS3: case INTUOS3L: case CINTIQ: case WACOM_BEE: - return (wacom_intuos_irq(wacom_wac, wcombo)); - break; + return wacom_intuos_irq(wacom_wac, wcombo); + + case TABLETPC: + return wacom_tpc_irq(wacom_wac, wcombo); + default: return 0; } @@ -586,13 +702,15 @@ void wacom_init_input_dev(struct input_dev *input_dev, struct wacom_wac *wacom_w /* fall through */ case INTUOS3S: input_dev_i3s(input_dev, wacom_wac); + /* fall through */ case INTUOS: input_dev_i(input_dev, wacom_wac); break; case PL: case PTU: + case TABLETPC: input_dev_pl(input_dev, wacom_wac); - break; + /* fall through */ case PENPARTNER: input_dev_pt(input_dev, wacom_wac); break; @@ -611,6 +729,7 @@ static struct wacom_features wacom_features[] = { { "Wacom Graphire4 6x8", 8, 16704, 12064, 511, 63, WACOM_G4 }, { "Wacom BambooFun 4x5", 9, 14760, 9225, 511, 63, WACOM_MO }, { "Wacom BambooFun 6x8", 9, 21648, 13530, 511, 63, WACOM_MO }, + { "Wacom Bamboo1 Medium",8, 16704, 12064, 511, 63, GRAPHIRE }, { "Wacom Volito", 8, 5104, 3712, 511, 63, GRAPHIRE }, { "Wacom PenStation2", 8, 3250, 2320, 255, 63, GRAPHIRE }, { "Wacom Volito2 4x5", 8, 5104, 3712, 511, 63, GRAPHIRE }, @@ -650,6 +769,10 @@ static struct wacom_features wacom_features[] = { { "Wacom Cintiq 21UX", 10, 87200, 65600, 1023, 63, CINTIQ }, { "Wacom Cintiq 20WSX", 10, 86680, 54180, 1023, 63, WACOM_BEE }, { "Wacom Cintiq 12WX", 10, 53020, 33440, 1023, 63, WACOM_BEE }, + { "Wacom DTU1931", 8, 37832, 30305, 511, 0, PL }, + { "Wacom ISDv4 90", 8, 26202, 16325, 255, 0, TABLETPC }, + { "Wacom ISDv4 93", 8, 26202, 16325, 255, 0, TABLETPC }, + { "Wacom ISDv4 9A", 8, 26202, 16325, 255, 0, TABLETPC }, { "Wacom Intuos2 6x8", 10, 20320, 16240, 1023, 31, INTUOS }, { } }; @@ -665,6 +788,7 @@ static struct usb_device_id wacom_ids[] = { { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x16) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x17) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x18) }, + { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x19) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x60) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x61) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x62) }, @@ -704,18 +828,26 @@ static struct usb_device_id wacom_ids[] = { { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x3F) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0xC5) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0xC6) }, + { USB_DEVICE(USB_VENDOR_ID_WACOM, 0xC7) }, + { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x90) }, + { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x93) }, + { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x9A) }, { USB_DEVICE(USB_VENDOR_ID_WACOM, 0x47) }, { } }; -const struct usb_device_id * get_device_table(void) { - const struct usb_device_id * id_table = wacom_ids; +const struct usb_device_id *get_device_table(void) +{ + const struct usb_device_id *id_table = wacom_ids; + return id_table; } -struct wacom_features * get_wacom_feature(const struct usb_device_id * id) { +struct wacom_features * get_wacom_feature(const struct usb_device_id *id) +{ int index = id - wacom_ids; struct wacom_features *wf = &wacom_features[index]; + return wf; } diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h index 3342bc05847d..f9c8b69673b7 100644 --- a/drivers/input/tablet/wacom_wac.h +++ b/drivers/input/tablet/wacom_wac.h @@ -10,6 +10,7 @@ #define WACOM_WAC_H #define STYLUS_DEVICE_ID 0x02 +#define TOUCH_DEVICE_ID 0x03 #define CURSOR_DEVICE_ID 0x06 #define ERASER_DEVICE_ID 0x0A #define PAD_DEVICE_ID 0x0F @@ -27,6 +28,7 @@ enum { CINTIQ, WACOM_BEE, WACOM_MO, + TABLETPC, MAX_TYPE }; @@ -38,6 +40,8 @@ struct wacom_features { int pressure_max; int distance_max; int type; + int touch_x_max; + int touch_y_max; }; struct wacom_wac { diff --git a/drivers/input/touchscreen/elo.c b/drivers/input/touchscreen/elo.c index d20689cdbd5d..8f38c5e55ce6 100644 --- a/drivers/input/touchscreen/elo.c +++ b/drivers/input/touchscreen/elo.c @@ -262,7 +262,7 @@ static int elo_setup_10(struct elo *elo) input_set_abs_params(dev, ABS_PRESSURE, 0, 255, 0, 0); printk(KERN_INFO "elo: %sTouch touchscreen, fw: %02x.%02x, " - "features: %x02x, controller: 0x%02x\n", + "features: 0x%02x, controller: 0x%02x\n", elo_types[(packet[1] -'0') & 0x03], packet[5], packet[4], packet[3], packet[7]); diff --git a/drivers/input/xen-kbdfront.c b/drivers/input/xen-kbdfront.c index 3ab6362f043c..928d2ed8865f 100644 --- a/drivers/input/xen-kbdfront.c +++ b/drivers/input/xen-kbdfront.c @@ -323,7 +323,7 @@ static struct xenbus_device_id xenkbd_ids[] = { { "" } }; -static struct xenbus_driver xenkbd = { +static struct xenbus_driver xenkbd_driver = { .name = "vkbd", .owner = THIS_MODULE, .ids = xenkbd_ids, @@ -342,12 +342,12 @@ static int __init xenkbd_init(void) if (xen_initial_domain()) return -ENODEV; - return xenbus_register_frontend(&xenkbd); + return xenbus_register_frontend(&xenkbd_driver); } static void __exit xenkbd_cleanup(void) { - xenbus_unregister_driver(&xenkbd); + xenbus_unregister_driver(&xenkbd_driver); } module_init(xenkbd_init); diff --git a/drivers/isdn/hardware/avm/b1isa.c b/drivers/isdn/hardware/avm/b1isa.c index 1e288eeb5e2a..6461a32bc838 100644 --- a/drivers/isdn/hardware/avm/b1isa.c +++ b/drivers/isdn/hardware/avm/b1isa.c @@ -233,10 +233,8 @@ static void __exit b1isa_exit(void) int i; for (i = 0; i < MAX_CARDS; i++) { - if (!io[i]) - break; - - b1isa_remove(&isa_dev[i]); + if (isa_dev[i].resource[0].start) + b1isa_remove(&isa_dev[i]); } unregister_capi_driver(&capi_driver_b1isa); } diff --git a/drivers/isdn/hisax/config.c b/drivers/isdn/hisax/config.c index 84d75a3f5d17..ded9d0baf607 100644 --- a/drivers/isdn/hisax/config.c +++ b/drivers/isdn/hisax/config.c @@ -1213,7 +1213,7 @@ static void HiSax_shiftcards(int idx) memcpy(&cards[i], &cards[i + 1], sizeof(cards[i])); } -static int HiSax_inithardware(int *busy_flag) +static int __init HiSax_inithardware(int *busy_flag) { int foundcards = 0; int i = 0; @@ -1542,7 +1542,9 @@ static void __exit HiSax_exit(void) printk(KERN_INFO "HiSax module removed\n"); } -int hisax_init_pcmcia(void *pcm_iob, int *busy_flag, struct IsdnCard *card) +#ifdef CONFIG_HOTPLUG + +int __devinit hisax_init_pcmcia(void *pcm_iob, int *busy_flag, struct IsdnCard *card) { u_char ids[16]; int ret = -1; @@ -1563,6 +1565,8 @@ error: } EXPORT_SYMBOL(hisax_init_pcmcia); +#endif + EXPORT_SYMBOL(HiSax_closecard); #include "hisax_if.h" @@ -1580,6 +1584,11 @@ static void hisax_bc_close(struct BCState *bcs); static void hisax_bh(struct work_struct *work); static void EChannel_proc_rcv(struct hisax_d_if *d_if); +static int hisax_setup_card_dynamic(struct IsdnCard *card) +{ + return 2; +} + int hisax_register(struct hisax_d_if *hisax_d_if, struct hisax_b_if *b_if[], char *name, int protocol) { @@ -1599,7 +1608,8 @@ int hisax_register(struct hisax_d_if *hisax_d_if, struct hisax_b_if *b_if[], cards[i].protocol = protocol; sprintf(id, "%s%d", name, i); nrcards++; - retval = checkcard(i, id, NULL, hisax_d_if->owner, hisax_cs_setup_card); + retval = checkcard(i, id, NULL, hisax_d_if->owner, + hisax_setup_card_dynamic); if (retval == 0) { // yuck cards[i].typ = 0; nrcards--; diff --git a/drivers/isdn/hysdn/hysdn_net.c b/drivers/isdn/hysdn/hysdn_net.c index cfa8fa5e44ab..3f2a0a20c19b 100644 --- a/drivers/isdn/hysdn/hysdn_net.c +++ b/drivers/isdn/hysdn/hysdn_net.c @@ -83,12 +83,12 @@ net_open(struct net_device *dev) /* Fill in the MAC-level header (if not already set) */ if (!card->mac_addr[0]) { - for (i = 0; i < ETH_ALEN - sizeof(unsigned long); i++) + for (i = 0; i < ETH_ALEN; i++) dev->dev_addr[i] = 0xfc; if ((in_dev = dev->ip_ptr) != NULL) { struct in_ifaddr *ifa = in_dev->ifa_list; if (ifa != NULL) - memcpy(dev->dev_addr + (ETH_ALEN - sizeof(unsigned long)), &ifa->ifa_local, sizeof(unsigned long)); + memcpy(dev->dev_addr + (ETH_ALEN - sizeof(ifa->ifa_local)), &ifa->ifa_local, sizeof(ifa->ifa_local)); } } else memcpy(dev->dev_addr, card->mac_addr, ETH_ALEN); diff --git a/drivers/isdn/i4l/isdn_net.c b/drivers/isdn/i4l/isdn_net.c index bb904a0a98bd..1bfc55d7a26c 100644 --- a/drivers/isdn/i4l/isdn_net.c +++ b/drivers/isdn/i4l/isdn_net.c @@ -1641,8 +1641,10 @@ isdn_net_ciscohdlck_slarp_send_reply(isdn_net_local *lp) /* slarp reply, send own ip/netmask; if values are nonsense remote * should think we are unable to provide it with an address via SLARP */ p += put_u32(p, CISCO_SLARP_REPLY); - p += put_u32(p, addr); // address - p += put_u32(p, mask); // netmask + *(__be32 *)p = addr; // address + p += 4; + *(__be32 *)p = mask; // netmask + p += 4; p += put_u16(p, 0); // unused isdn_net_write_super(lp, skb); diff --git a/drivers/leds/leds-da903x.c b/drivers/leds/leds-da903x.c index f1fddb18d70d..1f3cc512eff8 100644 --- a/drivers/leds/leds-da903x.c +++ b/drivers/leds/leds-da903x.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #define DA9030_LED1_CONTROL 0x20 @@ -57,7 +58,7 @@ static void da903x_led_work(struct work_struct *work) offset = DA9030_LED_OFFSET(led->id); val = led->flags & ~0x87; val |= (led->new_brightness) ? 0x80 : 0; /* EN bit */ - val |= (led->new_brightness >> 5) & 0x7; /* PWM<2:0> */ + val |= (0x7 - (led->new_brightness >> 5)) & 0x7; /* PWM<2:0> */ da903x_write(led->master, DA9030_LED1_CONTROL + offset, val); break; case DA9030_ID_VIBRA: diff --git a/drivers/leds/leds-hp-disk.c b/drivers/leds/leds-hp-disk.c index 53a25b1c2dae..44fa757d8254 100644 --- a/drivers/leds/leds-hp-disk.c +++ b/drivers/leds/leds-hp-disk.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -49,7 +48,7 @@ static struct acpi_hpled adev; static acpi_status hpled_acpi_write(acpi_handle handle, int reg) { - unsigned long ret; /* Not used when writing */ + unsigned long long ret; /* Not used when writing */ union acpi_object in_obj[1]; struct acpi_object_list args = { 1, in_obj }; diff --git a/drivers/macintosh/rack-meter.c b/drivers/macintosh/rack-meter.c index 2c21d4f25cc8..a98ab72adf95 100644 --- a/drivers/macintosh/rack-meter.c +++ b/drivers/macintosh/rack-meter.c @@ -288,7 +288,7 @@ static void __devexit rackmeter_stop_cpu_sniffer(struct rackmeter *rm) cancel_rearming_delayed_work(&rm->cpu[1].sniffer); } -static int rackmeter_setup(struct rackmeter *rm) +static int __devinit rackmeter_setup(struct rackmeter *rm) { pr_debug("rackmeter: setting up i2s..\n"); rackmeter_setup_i2s(rm); @@ -582,12 +582,12 @@ static struct of_device_id rackmeter_match[] = { { } }; -static struct macio_driver rackmeter_drv = { +static struct macio_driver rackmeter_driver = { .name = "rackmeter", .owner = THIS_MODULE, .match_table = rackmeter_match, .probe = rackmeter_probe, - .remove = rackmeter_remove, + .remove = __devexit_p(rackmeter_remove), .shutdown = rackmeter_shutdown, }; @@ -596,14 +596,14 @@ static int __init rackmeter_init(void) { pr_debug("rackmeter_init()\n"); - return macio_register_driver(&rackmeter_drv); + return macio_register_driver(&rackmeter_driver); } static void __exit rackmeter_exit(void) { pr_debug("rackmeter_exit()\n"); - macio_unregister_driver(&rackmeter_drv); + macio_unregister_driver(&rackmeter_driver); } module_init(rackmeter_init); diff --git a/drivers/md/bitmap.c b/drivers/md/bitmap.c index ac89a5deaca2..ab7c8e4a61f9 100644 --- a/drivers/md/bitmap.c +++ b/drivers/md/bitmap.c @@ -208,15 +208,18 @@ static void bitmap_checkfree(struct bitmap *bitmap, unsigned long page) */ /* IO operations when bitmap is stored near all superblocks */ -static struct page *read_sb_page(mddev_t *mddev, long offset, unsigned long index) +static struct page *read_sb_page(mddev_t *mddev, long offset, + struct page *page, + unsigned long index, int size) { /* choose a good rdev and read the page from there */ mdk_rdev_t *rdev; struct list_head *tmp; - struct page *page = alloc_page(GFP_KERNEL); sector_t target; + if (!page) + page = alloc_page(GFP_KERNEL); if (!page) return ERR_PTR(-ENOMEM); @@ -227,7 +230,9 @@ static struct page *read_sb_page(mddev_t *mddev, long offset, unsigned long inde target = rdev->sb_start + offset + index * (PAGE_SIZE/512); - if (sync_page_io(rdev->bdev, target, PAGE_SIZE, page, READ)) { + if (sync_page_io(rdev->bdev, target, + roundup(size, bdev_hardsect_size(rdev->bdev)), + page, READ)) { page->index = index; attach_page_buffers(page, NULL); /* so that free_buffer will * quietly no-op */ @@ -544,7 +549,9 @@ static int bitmap_read_sb(struct bitmap *bitmap) bitmap->sb_page = read_page(bitmap->file, 0, bitmap, bytes); } else { - bitmap->sb_page = read_sb_page(bitmap->mddev, bitmap->offset, 0); + bitmap->sb_page = read_sb_page(bitmap->mddev, bitmap->offset, + NULL, + 0, sizeof(bitmap_super_t)); } if (IS_ERR(bitmap->sb_page)) { err = PTR_ERR(bitmap->sb_page); @@ -957,11 +964,16 @@ static int bitmap_init_from_disk(struct bitmap *bitmap, sector_t start) */ page = bitmap->sb_page; offset = sizeof(bitmap_super_t); + read_sb_page(bitmap->mddev, bitmap->offset, + page, + index, count); } else if (file) { page = read_page(file, index, bitmap, count); offset = 0; } else { - page = read_sb_page(bitmap->mddev, bitmap->offset, index); + page = read_sb_page(bitmap->mddev, bitmap->offset, + NULL, + index, count); offset = 0; } if (IS_ERR(page)) { /* read error */ diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index 4840733cd903..3d7f4923cd13 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -441,13 +441,13 @@ static void process_queued_ios(struct work_struct *work) __choose_pgpath(m); pgpath = m->current_pgpath; - m->pgpath_to_activate = m->current_pgpath; if ((pgpath && !m->queue_io) || (!pgpath && !m->queue_if_no_path)) must_queue = 0; - if (m->pg_init_required && !m->pg_init_in_progress) { + if (m->pg_init_required && !m->pg_init_in_progress && pgpath) { + m->pgpath_to_activate = pgpath; m->pg_init_count++; m->pg_init_required = 0; m->pg_init_in_progress = 1; @@ -708,6 +708,10 @@ static int parse_hw_handler(struct arg_set *as, struct multipath *m) m->hw_handler_name = NULL; return -EINVAL; } + + if (hw_argc > 1) + DMWARN("Ignoring user-specified arguments for " + "hardware handler \"%s\"", m->hw_handler_name); consume(as, hw_argc - 1); return 0; diff --git a/drivers/md/dm-raid1.c b/drivers/md/dm-raid1.c index 92dcc06832a4..ec43f9fa4b2a 100644 --- a/drivers/md/dm-raid1.c +++ b/drivers/md/dm-raid1.c @@ -656,9 +656,10 @@ static void do_failures(struct mirror_set *ms, struct bio_list *failures) return; if (!ms->log_failure) { - while ((bio = bio_list_pop(failures))) + while ((bio = bio_list_pop(failures))) { ms->in_sync = 0; dm_rh_mark_nosync(ms->rh, bio, bio->bi_size, 0); + } return; } @@ -1031,6 +1032,7 @@ static void mirror_dtr(struct dm_target *ti) del_timer_sync(&ms->timer); flush_workqueue(ms->kmirrord_wq); + flush_scheduled_work(); dm_kcopyd_client_destroy(ms->kcopyd_client); destroy_workqueue(ms->kmirrord_wq); free_context(ms, ti, ms->nr_mirrors); diff --git a/drivers/md/dm-snap.c b/drivers/md/dm-snap.c index b2d9d1ac28ad..6c96db26b87c 100644 --- a/drivers/md/dm-snap.c +++ b/drivers/md/dm-snap.c @@ -229,19 +229,21 @@ static void __insert_origin(struct origin *o) */ static int register_snapshot(struct dm_snapshot *snap) { - struct origin *o; + struct origin *o, *new_o; struct block_device *bdev = snap->origin->bdev; + new_o = kmalloc(sizeof(*new_o), GFP_KERNEL); + if (!new_o) + return -ENOMEM; + down_write(&_origins_lock); o = __lookup_origin(bdev); - if (!o) { + if (o) + kfree(new_o); + else { /* New origin */ - o = kmalloc(sizeof(*o), GFP_KERNEL); - if (!o) { - up_write(&_origins_lock); - return -ENOMEM; - } + o = new_o; /* Initialise the struct */ INIT_LIST_HEAD(&o->snapshots); @@ -368,6 +370,7 @@ static struct dm_snap_pending_exception *alloc_pending_exception(struct dm_snaps struct dm_snap_pending_exception *pe = mempool_alloc(s->pending_pool, GFP_NOIO); + atomic_inc(&s->pending_exceptions_count); pe->snap = s; return pe; @@ -375,7 +378,11 @@ static struct dm_snap_pending_exception *alloc_pending_exception(struct dm_snaps static void free_pending_exception(struct dm_snap_pending_exception *pe) { - mempool_free(pe, pe->snap->pending_pool); + struct dm_snapshot *s = pe->snap; + + mempool_free(pe, s->pending_pool); + smp_mb__before_atomic_dec(); + atomic_dec(&s->pending_exceptions_count); } static void insert_completed_exception(struct dm_snapshot *s, @@ -600,6 +607,7 @@ static int snapshot_ctr(struct dm_target *ti, unsigned int argc, char **argv) s->valid = 1; s->active = 0; + atomic_set(&s->pending_exceptions_count, 0); init_rwsem(&s->lock); spin_lock_init(&s->pe_lock); s->ti = ti; @@ -726,6 +734,14 @@ static void snapshot_dtr(struct dm_target *ti) /* After this returns there can be no new kcopyd jobs. */ unregister_snapshot(s); + while (atomic_read(&s->pending_exceptions_count)) + yield(); + /* + * Ensure instructions in mempool_destroy aren't reordered + * before atomic_read. + */ + smp_mb(); + #ifdef CONFIG_DM_DEBUG for (i = 0; i < DM_TRACKED_CHUNK_HASH_SIZE; i++) BUG_ON(!hlist_empty(&s->tracked_chunk_hash[i])); diff --git a/drivers/md/dm-snap.h b/drivers/md/dm-snap.h index f07315fe2362..99c0106ede2d 100644 --- a/drivers/md/dm-snap.h +++ b/drivers/md/dm-snap.h @@ -160,6 +160,8 @@ struct dm_snapshot { mempool_t *pending_pool; + atomic_t pending_exceptions_count; + struct exception_table pending; struct exception_table complete; diff --git a/drivers/md/dm-stripe.c b/drivers/md/dm-stripe.c index a2d068dbe9e2..9e4ef88d421e 100644 --- a/drivers/md/dm-stripe.c +++ b/drivers/md/dm-stripe.c @@ -320,8 +320,10 @@ int __init dm_stripe_init(void) int r; r = dm_register_target(&stripe_target); - if (r < 0) + if (r < 0) { DMWARN("target registration failed"); + return r; + } kstriped = create_singlethread_workqueue("kstriped"); if (!kstriped) { diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c index a63161aec487..04e5fd742c2c 100644 --- a/drivers/md/dm-table.c +++ b/drivers/md/dm-table.c @@ -668,7 +668,7 @@ static void check_for_valid_limits(struct io_restrictions *rs) if (!rs->max_segment_size) rs->max_segment_size = MAX_SEGMENT_SIZE; if (!rs->seg_boundary_mask) - rs->seg_boundary_mask = -1; + rs->seg_boundary_mask = BLK_SEG_BOUNDARY_MASK; if (!rs->bounce_pfn) rs->bounce_pfn = -1; } diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 6963ad148408..c99e4728ff41 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -375,7 +375,7 @@ static void start_io_acct(struct dm_io *io) dm_disk(md)->part0.in_flight = atomic_inc_return(&md->pending); } -static int end_io_acct(struct dm_io *io) +static void end_io_acct(struct dm_io *io) { struct mapped_device *md = io->md; struct bio *bio = io->bio; @@ -391,7 +391,9 @@ static int end_io_acct(struct dm_io *io) dm_disk(md)->part0.in_flight = pending = atomic_dec_return(&md->pending); - return !pending; + /* nudge anyone waiting on suspend queue */ + if (!pending) + wake_up(&md->wait); } /* @@ -499,9 +501,7 @@ static void dec_pending(struct dm_io *io, int error) spin_unlock_irqrestore(&io->md->pushback_lock, flags); } - if (end_io_acct(io)) - /* nudge anyone waiting on suspend queue */ - wake_up(&io->md->wait); + end_io_acct(io); if (io->error != DM_ENDIO_REQUEUE) { blk_add_trace_bio(io->md->queue, io->bio, @@ -937,16 +937,24 @@ static void dm_unplug_all(struct request_queue *q) static int dm_any_congested(void *congested_data, int bdi_bits) { - int r; - struct mapped_device *md = (struct mapped_device *) congested_data; - struct dm_table *map = dm_get_table(md); + int r = bdi_bits; + struct mapped_device *md = congested_data; + struct dm_table *map; - if (!map || test_bit(DMF_BLOCK_IO, &md->flags)) - r = bdi_bits; - else - r = dm_table_any_congested(map, bdi_bits); + atomic_inc(&md->pending); + + if (!test_bit(DMF_BLOCK_IO, &md->flags)) { + map = dm_get_table(md); + if (map) { + r = dm_table_any_congested(map, bdi_bits); + dm_table_put(map); + } + } + + if (!atomic_dec_return(&md->pending)) + /* nudge anyone waiting on suspend queue */ + wake_up(&md->wait); - dm_table_put(map); return r; } diff --git a/drivers/md/linear.c b/drivers/md/linear.c index 190147c79e79..3b90c5c924ec 100644 --- a/drivers/md/linear.c +++ b/drivers/md/linear.c @@ -148,6 +148,8 @@ static linear_conf_t *linear_conf(mddev_t *mddev, int raid_disks) min_sectors = conf->array_sectors; sector_div(min_sectors, PAGE_SIZE/sizeof(struct dev_info *)); + if (min_sectors == 0) + min_sectors = 1; /* min_sectors is the minimum spacing that will fit the hash * table in one PAGE. This may be much smaller than needed. diff --git a/drivers/md/md.c b/drivers/md/md.c index c1a837ca193c..1b1d32694f6f 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -222,6 +222,9 @@ static void mddev_put(mddev_t *mddev) list_del(&mddev->all_mddevs); spin_unlock(&all_mddevs_lock); blk_cleanup_queue(mddev->queue); + if (mddev->sysfs_state) + sysfs_put(mddev->sysfs_state); + mddev->sysfs_state = NULL; kobject_put(&mddev->kobj); } else spin_unlock(&all_mddevs_lock); @@ -1459,6 +1462,8 @@ static int bind_rdev_to_array(mdk_rdev_t * rdev, mddev_t * mddev) kobject_del(&rdev->kobj); goto fail; } + rdev->sysfs_state = sysfs_get_dirent(rdev->kobj.sd, "state"); + list_add_rcu(&rdev->same_set, &mddev->disks); bd_claim_by_disk(rdev->bdev, rdev->bdev->bd_holder, mddev->gendisk); return 0; @@ -1488,7 +1493,8 @@ static void unbind_rdev_from_array(mdk_rdev_t * rdev) printk(KERN_INFO "md: unbind<%s>\n", bdevname(rdev->bdev,b)); rdev->mddev = NULL; sysfs_remove_link(&rdev->kobj, "block"); - + sysfs_put(rdev->sysfs_state); + rdev->sysfs_state = NULL; /* We need to delay this, otherwise we can deadlock when * writing to 'remove' to "dev/state". We also need * to delay it due to rcu usage. @@ -1923,8 +1929,8 @@ state_store(mdk_rdev_t *rdev, const char *buf, size_t len) err = 0; } - if (!err) - sysfs_notify(&rdev->kobj, NULL, "state"); + if (!err && rdev->sysfs_state) + sysfs_notify_dirent(rdev->sysfs_state); return err ? err : len; } static struct rdev_sysfs_entry rdev_state = @@ -2019,7 +2025,7 @@ slot_store(mdk_rdev_t *rdev, const char *buf, size_t len) rdev->raid_disk = -1; return err; } else - sysfs_notify(&rdev->kobj, NULL, "state"); + sysfs_notify_dirent(rdev->sysfs_state); sprintf(nm, "rd%d", rdev->raid_disk); if (sysfs_create_link(&rdev->mddev->kobj, &rdev->kobj, nm)) printk(KERN_WARNING @@ -2036,7 +2042,7 @@ slot_store(mdk_rdev_t *rdev, const char *buf, size_t len) clear_bit(Faulty, &rdev->flags); clear_bit(WriteMostly, &rdev->flags); set_bit(In_sync, &rdev->flags); - sysfs_notify(&rdev->kobj, NULL, "state"); + sysfs_notify_dirent(rdev->sysfs_state); } return len; } @@ -2770,7 +2776,7 @@ array_state_store(mddev_t *mddev, const char *buf, size_t len) if (err) return err; else { - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); return len; } } @@ -3457,6 +3463,11 @@ static struct kobject *md_probe(dev_t dev, int *part, void *data) disk->fops = &md_fops; disk->private_data = mddev; disk->queue = mddev->queue; + /* Allow extended partitions. This makes the + * 'mdp' device redundant, but we can really + * remove it now. + */ + disk->flags |= GENHD_FL_EXT_DEVT; add_disk(disk); mddev->gendisk = disk; error = kobject_init_and_add(&mddev->kobj, &md_ktype, @@ -3465,8 +3476,10 @@ static struct kobject *md_probe(dev_t dev, int *part, void *data) if (error) printk(KERN_WARNING "md: cannot register %s/md - name in use\n", disk->disk_name); - else + else { kobject_uevent(&mddev->kobj, KOBJ_ADD); + mddev->sysfs_state = sysfs_get_dirent(mddev->kobj.sd, "array_state"); + } return NULL; } @@ -3477,7 +3490,7 @@ static void md_safemode_timeout(unsigned long data) if (!atomic_read(&mddev->writes_pending)) { mddev->safemode = 1; if (mddev->external) - set_bit(MD_NOTIFY_ARRAY_STATE, &mddev->flags); + sysfs_notify_dirent(mddev->sysfs_state); } md_wakeup_thread(mddev->thread); } @@ -3578,7 +3591,7 @@ static int do_md_run(mddev_t * mddev) return -EINVAL; } } - sysfs_notify(&rdev->kobj, NULL, "state"); + sysfs_notify_dirent(rdev->sysfs_state); } md_probe(mddev->unit, NULL, NULL); @@ -3740,7 +3753,7 @@ static int do_md_run(mddev_t * mddev) mddev->changed = 1; md_new_event(mddev); - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); sysfs_notify(&mddev->kobj, NULL, "sync_action"); sysfs_notify(&mddev->kobj, NULL, "degraded"); kobject_uevent(&disk_to_dev(mddev->gendisk)->kobj, KOBJ_CHANGE); @@ -3767,7 +3780,7 @@ static int restart_array(mddev_t *mddev) set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); md_wakeup_thread(mddev->thread); md_wakeup_thread(mddev->sync_thread); - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); return 0; } @@ -3847,7 +3860,7 @@ static int do_md_stop(mddev_t * mddev, int mode, int is_open) module_put(mddev->pers->owner); mddev->pers = NULL; /* tell userspace to handle 'inactive' */ - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); set_capacity(disk, 0); mddev->changed = 1; @@ -3927,13 +3940,14 @@ static int do_md_stop(mddev_t * mddev, int mode, int is_open) mddev->degraded = 0; mddev->barriers_work = 0; mddev->safemode = 0; + kobject_uevent(&disk_to_dev(mddev->gendisk)->kobj, KOBJ_CHANGE); } else if (mddev->pers) printk(KERN_INFO "md: %s switched to read-only mode.\n", mdname(mddev)); err = 0; md_new_event(mddev); - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); out: return err; } @@ -4297,7 +4311,7 @@ static int add_new_disk(mddev_t * mddev, mdu_disk_info_t *info) if (err) export_rdev(rdev); else - sysfs_notify(&rdev->kobj, NULL, "state"); + sysfs_notify_dirent(rdev->sysfs_state); md_update_sb(mddev, 1); if (mddev->degraded) @@ -4938,7 +4952,7 @@ static int md_ioctl(struct block_device *bdev, fmode_t mode, if (_IOC_TYPE(cmd) == MD_MAJOR && mddev->ro && mddev->pers) { if (mddev->ro == 2) { mddev->ro = 0; - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); md_wakeup_thread(mddev->thread); } else { @@ -5612,7 +5626,7 @@ void md_write_start(mddev_t *mddev, struct bio *bi) spin_unlock_irq(&mddev->write_lock); } if (did_change) - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); wait_event(mddev->sb_wait, !test_bit(MD_CHANGE_CLEAN, &mddev->flags) && !test_bit(MD_CHANGE_PENDING, &mddev->flags)); @@ -5655,7 +5669,7 @@ int md_allow_write(mddev_t *mddev) mddev->safemode = 1; spin_unlock_irq(&mddev->write_lock); md_update_sb(mddev, 0); - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); } else spin_unlock_irq(&mddev->write_lock); @@ -6048,9 +6062,6 @@ void md_check_recovery(mddev_t *mddev) if (mddev->bitmap) bitmap_daemon_work(mddev->bitmap); - if (test_and_clear_bit(MD_NOTIFY_ARRAY_STATE, &mddev->flags)) - sysfs_notify(&mddev->kobj, NULL, "array_state"); - if (mddev->ro) return; @@ -6103,7 +6114,7 @@ void md_check_recovery(mddev_t *mddev) mddev->safemode = 0; spin_unlock_irq(&mddev->write_lock); if (did_change) - sysfs_notify(&mddev->kobj, NULL, "array_state"); + sysfs_notify_dirent(mddev->sysfs_state); } if (mddev->flags) @@ -6111,7 +6122,7 @@ void md_check_recovery(mddev_t *mddev) rdev_for_each(rdev, rtmp, mddev) if (test_and_clear_bit(StateChanged, &rdev->flags)) - sysfs_notify(&rdev->kobj, NULL, "state"); + sysfs_notify_dirent(rdev->sysfs_state); if (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery) && @@ -6221,7 +6232,7 @@ void md_check_recovery(mddev_t *mddev) void md_wait_for_blocked_rdev(mdk_rdev_t *rdev, mddev_t *mddev) { - sysfs_notify(&rdev->kobj, NULL, "state"); + sysfs_notify_dirent(rdev->sysfs_state); wait_event_timeout(rdev->blocked_wait, !test_bit(Blocked, &rdev->flags), msecs_to_jiffies(5000)); diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index da5129a24b18..970a96ef9b18 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -1137,7 +1137,7 @@ static int raid10_add_disk(mddev_t *mddev, mdk_rdev_t *rdev) if (!enough(conf)) return -EINVAL; - if (rdev->raid_disk) + if (rdev->raid_disk >= 0) first = last = rdev->raid_disk; if (rdev->saved_raid_disk >= 0 && diff --git a/drivers/media/dvb/dm1105/dm1105.c b/drivers/media/dvb/dm1105/dm1105.c index 14e627ef6465..c1d92f838ca8 100644 --- a/drivers/media/dvb/dm1105/dm1105.c +++ b/drivers/media/dvb/dm1105/dm1105.c @@ -376,7 +376,7 @@ static void dm1105dvb_dma_unmap(struct dm1105dvb *dm1105dvb) pci_free_consistent(dm1105dvb->pdev, 6*DM1105_DMA_BYTES, dm1105dvb->ts_buf, dm1105dvb->dma_addr); } -static void __devinit dm1105dvb_enable_irqs(struct dm1105dvb *dm1105dvb) +static void dm1105dvb_enable_irqs(struct dm1105dvb *dm1105dvb) { outb(INTMAK_ALLMASK, dm_io_mem(DM1105_INTMAK)); outb(1, dm_io_mem(DM1105_CR)); diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 5689d1f1d444..7a421e9dba5a 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -223,6 +223,8 @@ static void dvb_frontend_init(struct dvb_frontend *fe) if (fe->ops.init) fe->ops.init(fe); if (fe->ops.tuner_ops.init) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); fe->ops.tuner_ops.init(fe); if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); @@ -583,6 +585,8 @@ restart: if (fe->ops.set_voltage) fe->ops.set_voltage(fe, SEC_VOLTAGE_OFF); if (fe->ops.tuner_ops.sleep) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); fe->ops.tuner_ops.sleep(fe); if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); @@ -932,7 +936,8 @@ void dtv_property_dump(struct dtv_property *tvp) int is_legacy_delivery_system(fe_delivery_system_t s) { if((s == SYS_UNDEFINED) || (s == SYS_DVBC_ANNEX_AC) || - (s == SYS_DVBC_ANNEX_B) || (s == SYS_DVBT) || (s == SYS_DVBS)) + (s == SYS_DVBC_ANNEX_B) || (s == SYS_DVBT) || (s == SYS_DVBS) || + (s == SYS_ATSC)) return 1; return 0; diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig index 3c13bcfa6385..62b68c291d99 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig @@ -261,7 +261,7 @@ config DVB_USB_DW2102 Say Y here to support the DvbWorld DVB-S/S2 USB2.0 receivers and the TeVii S650. -config DVB_USB_CINERGY_T2 +config DVB_USB_CINERGY_T2 tristate "Terratec CinergyT2/qanu USB 2.0 DVB-T receiver" depends on DVB_USB help @@ -283,6 +283,7 @@ config DVB_USB_ANYSEE config DVB_USB_DTV5100 tristate "AME DTV-5100 USB2.0 DVB-T support" depends on DVB_USB + select DVB_ZL10353 if !DVB_FE_CUSTOMISE select MEDIA_TUNER_QT1010 if !DVB_FE_CUSTOMISE help Say Y here to support the AME DTV-5100 USB2.0 DVB-T receiver. diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c index cb0829c038ce..e9ab0249d133 100644 --- a/drivers/media/dvb/dvb-usb/af9015.c +++ b/drivers/media/dvb/dvb-usb/af9015.c @@ -31,13 +31,13 @@ #include "mc44s80x.h" #endif -int dvb_usb_af9015_debug; +static int dvb_usb_af9015_debug; module_param_named(debug, dvb_usb_af9015_debug, int, 0644); MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS); -int dvb_usb_af9015_remote; +static int dvb_usb_af9015_remote; module_param_named(remote, dvb_usb_af9015_remote, int, 0644); MODULE_PARM_DESC(remote, "select remote"); -int dvb_usb_af9015_dual_mode; +static int dvb_usb_af9015_dual_mode; module_param_named(dual_mode, dvb_usb_af9015_dual_mode, int, 0644); MODULE_PARM_DESC(dual_mode, "enable dual mode"); DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); @@ -46,7 +46,7 @@ static DEFINE_MUTEX(af9015_usb_mutex); static struct af9015_config af9015_config; static struct dvb_usb_device_properties af9015_properties[2]; -int af9015_properties_count = ARRAY_SIZE(af9015_properties); +static int af9015_properties_count = ARRAY_SIZE(af9015_properties); static struct af9013_config af9015_af9013_config[] = { { @@ -549,7 +549,7 @@ static int af9015_eeprom_dump(struct dvb_usb_device *d) return 0; } -int af9015_download_ir_table(struct dvb_usb_device *d) +static int af9015_download_ir_table(struct dvb_usb_device *d) { int i, packets = 0, ret; u16 addr = 0x9a56; /* ir-table start address */ @@ -681,12 +681,6 @@ static int af9015_download_firmware(struct usb_device *udev, goto error; } - /* firmware is running, reconnect device in the usb bus */ - req.cmd = RECONNECT_USB; - ret = af9015_rw_udev(udev, &req); - if (ret) - err("reconnect failed: %d", ret); - error: return ret; } @@ -999,7 +993,7 @@ static int af9015_rc_query(struct dvb_usb_device *d, u32 *event, int *state) } /* init 2nd I2C adapter */ -int af9015_i2c_init(struct dvb_usb_device *d) +static int af9015_i2c_init(struct dvb_usb_device *d) { int ret; struct af9015_state *state = d->priv; @@ -1208,6 +1202,7 @@ static struct dvb_usb_device_properties af9015_properties[] = { .usb_ctrl = DEVICE_SPECIFIC, .download_firmware = af9015_download_firmware, .firmware = "dvb-usb-af9015.fw", + .no_reconnect = 1, .size_of_priv = sizeof(struct af9015_state), \ @@ -1306,6 +1301,7 @@ static struct dvb_usb_device_properties af9015_properties[] = { .usb_ctrl = DEVICE_SPECIFIC, .download_firmware = af9015_download_firmware, .firmware = "dvb-usb-af9015.fw", + .no_reconnect = 1, .size_of_priv = sizeof(struct af9015_state), \ @@ -1419,7 +1415,7 @@ static int af9015_usb_probe(struct usb_interface *intf, return ret; } -void af9015_i2c_exit(struct dvb_usb_device *d) +static void af9015_i2c_exit(struct dvb_usb_device *d) { struct af9015_state *state = d->priv; deb_info("%s: \n", __func__); diff --git a/drivers/media/dvb/dvb-usb/af9015.h b/drivers/media/dvb/dvb-usb/af9015.h index 882e8a4b3681..6c3c97293316 100644 --- a/drivers/media/dvb/dvb-usb/af9015.h +++ b/drivers/media/dvb/dvb-usb/af9015.h @@ -27,7 +27,6 @@ #define DVB_USB_LOG_PREFIX "af9015" #include "dvb-usb.h" -extern int dvb_usb_af9015_debug; #define deb_info(args...) dprintk(dvb_usb_af9015_debug, 0x01, args) #define deb_rc(args...) dprintk(dvb_usb_af9015_debug, 0x02, args) #define deb_xfer(args...) dprintk(dvb_usb_af9015_debug, 0x04, args) diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index c786359fba03..cd2edbcaa097 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -46,7 +46,7 @@ module_param_named(delsys, dvb_usb_anysee_delsys, int, 0644); MODULE_PARM_DESC(delsys, "select delivery mode (0=DVB-C, 1=DVB-T)"); DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); -static struct mutex anysee_usb_mutex; +static DEFINE_MUTEX(anysee_usb_mutex); static int anysee_ctrl_msg(struct dvb_usb_device *d, u8 *sbuf, u8 slen, u8 *rbuf, u8 rlen) @@ -456,8 +456,6 @@ static int anysee_probe(struct usb_interface *intf, struct usb_host_interface *alt; int ret; - mutex_init(&anysee_usb_mutex); - /* There is one interface with two alternate settings. Alternate setting 0 is for bulk transfer. Alternate setting 1 is for isochronous transfer. diff --git a/drivers/media/dvb/dvb-usb/dib0700.h b/drivers/media/dvb/dvb-usb/dib0700.h index 739193943c17..8b544fe79b0d 100644 --- a/drivers/media/dvb/dvb-usb/dib0700.h +++ b/drivers/media/dvb/dvb-usb/dib0700.h @@ -22,7 +22,7 @@ extern int dvb_usb_dib0700_debug; #define REQUEST_I2C_READ 0x2 #define REQUEST_I2C_WRITE 0x3 -#define REQUEST_POLL_RC 0x4 +#define REQUEST_POLL_RC 0x4 /* deprecated in firmware v1.20 */ #define REQUEST_JUMPRAM 0x8 #define REQUEST_SET_CLOCK 0xB #define REQUEST_SET_GPIO 0xC @@ -40,11 +40,14 @@ struct dib0700_state { u16 mt2060_if1[2]; u8 rc_toggle; u8 rc_counter; + u8 rc_func_version; u8 is_dib7000pc; u8 fw_use_new_i2c_api; u8 disable_streaming_master_mode; }; +extern int dib0700_get_version(struct dvb_usb_device *d, u32 *hwversion, + u32 *romversion, u32 *ramversion, u32 *fwtype); extern int dib0700_set_gpio(struct dvb_usb_device *, enum dib07x0_gpios gpio, u8 gpio_dir, u8 gpio_val); extern int dib0700_ctrl_clock(struct dvb_usb_device *d, u32 clk_MHz, u8 clock_out_gp3); extern int dib0700_ctrl_rd(struct dvb_usb_device *d, u8 *tx, u8 txlen, u8 *rx, u8 rxlen); diff --git a/drivers/media/dvb/dvb-usb/dib0700_core.c b/drivers/media/dvb/dvb-usb/dib0700_core.c index dd53cee3896d..200b215f4d8b 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_core.c +++ b/drivers/media/dvb/dvb-usb/dib0700_core.c @@ -19,6 +19,22 @@ MODULE_PARM_DESC(dvb_usb_dib0700_ir_proto, "set ir protocol (0=NEC, 1=RC5 (defau DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +int dib0700_get_version(struct dvb_usb_device *d, u32 *hwversion, + u32 *romversion, u32 *ramversion, u32 *fwtype) +{ + u8 b[16]; + int ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), + REQUEST_GET_VERSION, + USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, + b, sizeof(b), USB_CTRL_GET_TIMEOUT); + *hwversion = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; + *romversion = (b[4] << 24) | (b[5] << 16) | (b[6] << 8) | b[7]; + *ramversion = (b[8] << 24) | (b[9] << 16) | (b[10] << 8) | b[11]; + *fwtype = (b[12] << 24) | (b[13] << 16) | (b[14] << 8) | b[15]; + return ret; +} + /* expecting rx buffer: request data[0] data[1] ... data[2] */ static int dib0700_ctrl_wr(struct dvb_usb_device *d, u8 *tx, u8 txlen) { diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c index 0cfccc24b190..f28d3ae59e04 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_devices.c +++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c @@ -38,6 +38,7 @@ static struct mt2060_config bristol_mt2060_config[2] = { } }; + static struct dibx000_agc_config bristol_dib3000p_mt2060_agc_config = { .band_caps = BAND_VHF | BAND_UHF, .setup = (1 << 8) | (5 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (2 << 0), @@ -451,8 +452,13 @@ static u8 rc_request[] = { REQUEST_POLL_RC, 0 }; /* Number of keypresses to ignore before start repeating */ #define RC_REPEAT_DELAY 2 +#define RC_REPEAT_DELAY_V1_20 5 -static int dib0700_rc_query(struct dvb_usb_device *d, u32 *event, int *state) + + +/* Used by firmware versions < 1.20 (deprecated) */ +static int dib0700_rc_query_legacy(struct dvb_usb_device *d, u32 *event, + int *state) { u8 key[4]; int i; @@ -529,6 +535,137 @@ static int dib0700_rc_query(struct dvb_usb_device *d, u32 *event, int *state) return 0; } +/* This is the structure of the RC response packet starting in firmware 1.20 */ +struct dib0700_rc_response { + u8 report_id; + u8 data_state; + u8 system_msb; + u8 system_lsb; + u8 data; + u8 not_data; +}; + +/* This supports the new IR response format for firmware v1.20 */ +static int dib0700_rc_query_v1_20(struct dvb_usb_device *d, u32 *event, + int *state) +{ + struct dvb_usb_rc_key *keymap = d->props.rc_key_map; + struct dib0700_state *st = d->priv; + struct dib0700_rc_response poll_reply; + u8 buf[6]; + int i; + int status; + int actlen; + int found = 0; + + /* Set initial results in case we exit the function early */ + *event = 0; + *state = REMOTE_NO_KEY_PRESSED; + + /* Firmware v1.20 provides RC data via bulk endpoint 1 */ + status = usb_bulk_msg(d->udev, usb_rcvbulkpipe(d->udev, 1), buf, + sizeof(buf), &actlen, 50); + if (status < 0) { + /* No data available (meaning no key press) */ + return 0; + } + + if (actlen != sizeof(buf)) { + /* We didn't get back the 6 byte message we expected */ + err("Unexpected RC response size [%d]", actlen); + return -1; + } + + poll_reply.report_id = buf[0]; + poll_reply.data_state = buf[1]; + poll_reply.system_msb = buf[2]; + poll_reply.system_lsb = buf[3]; + poll_reply.data = buf[4]; + poll_reply.not_data = buf[5]; + + /* + info("rid=%02x ds=%02x sm=%02x sl=%02x d=%02x nd=%02x\n", + poll_reply.report_id, poll_reply.data_state, + poll_reply.system_msb, poll_reply.system_lsb, + poll_reply.data, poll_reply.not_data); + */ + + if ((poll_reply.data + poll_reply.not_data) != 0xff) { + /* Key failed integrity check */ + err("key failed integrity check: %02x %02x %02x %02x", + poll_reply.system_msb, poll_reply.system_lsb, + poll_reply.data, poll_reply.not_data); + return -1; + } + + /* Find the key in the map */ + for (i = 0; i < d->props.rc_key_map_size; i++) { + if (keymap[i].custom == poll_reply.system_lsb && + keymap[i].data == poll_reply.data) { + *event = keymap[i].event; + found = 1; + break; + } + } + + if (found == 0) { + err("Unknown remote controller key: %02x %02x %02x %02x", + poll_reply.system_msb, poll_reply.system_lsb, + poll_reply.data, poll_reply.not_data); + d->last_event = 0; + return 0; + } + + if (poll_reply.data_state == 1) { + /* New key hit */ + st->rc_counter = 0; + *event = keymap[i].event; + *state = REMOTE_KEY_PRESSED; + d->last_event = keymap[i].event; + } else if (poll_reply.data_state == 2) { + /* Key repeated */ + st->rc_counter++; + + /* prevents unwanted double hits */ + if (st->rc_counter > RC_REPEAT_DELAY_V1_20) { + *event = d->last_event; + *state = REMOTE_KEY_PRESSED; + st->rc_counter = RC_REPEAT_DELAY_V1_20; + } + } else { + err("Unknown data state [%d]", poll_reply.data_state); + } + + return 0; +} + +static int dib0700_rc_query(struct dvb_usb_device *d, u32 *event, int *state) +{ + struct dib0700_state *st = d->priv; + + /* Because some people may have improperly named firmware files, + let's figure out whether to use the new firmware call or the legacy + call based on the firmware version embedded in the file */ + if (st->rc_func_version == 0) { + u32 hwver, romver, ramver, fwtype; + int ret = dib0700_get_version(d, &hwver, &romver, &ramver, + &fwtype); + if (ret < 0) { + err("Could not determine version info"); + return -1; + } + if (ramver < 0x10200) + st->rc_func_version = 1; + else + st->rc_func_version = 2; + } + + if (st->rc_func_version == 2) + return dib0700_rc_query_v1_20(d, event, state); + else + return dib0700_rc_query_legacy(d, event, state); +} + static struct dvb_usb_rc_key dib0700_rc_keys[] = { /* Key codes for the tiny Pinnacle remote*/ { 0x07, 0x00, KEY_MUTE }, diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-urb.c b/drivers/media/dvb/dvb-usb/dvb-usb-urb.c index 5cef12a07f72..6fe71c6745eb 100644 --- a/drivers/media/dvb/dvb-usb/dvb-usb-urb.c +++ b/drivers/media/dvb/dvb-usb/dvb-usb-urb.c @@ -13,14 +13,14 @@ int dvb_usb_generic_rw(struct dvb_usb_device *d, u8 *wbuf, u16 wlen, u8 *rbuf, { int actlen,ret = -ENOMEM; + if (!d || wbuf == NULL || wlen == 0) + return -EINVAL; + if (d->props.generic_bulk_ctrl_endpoint == 0) { err("endpoint for generic control not specified."); return -EINVAL; } - if (wbuf == NULL || wlen == 0) - return -EINVAL; - if ((ret = mutex_lock_interruptible(&d->usb_mutex))) return ret; diff --git a/drivers/media/dvb/dvb-usb/usb-urb.c b/drivers/media/dvb/dvb-usb/usb-urb.c index 397f51a7b2ad..da93b9e982c0 100644 --- a/drivers/media/dvb/dvb-usb/usb-urb.c +++ b/drivers/media/dvb/dvb-usb/usb-urb.c @@ -135,7 +135,7 @@ stream->buf_list[stream->buf_num], (long long)stream->dma_addr[stream->buf_num]) static int usb_bulk_urb_init(struct usb_data_stream *stream) { - int i; + int i, j; if ((i = usb_allocate_stream_buffers(stream,stream->props.count, stream->props.u.bulk.buffersize)) < 0) @@ -143,9 +143,13 @@ static int usb_bulk_urb_init(struct usb_data_stream *stream) /* allocate the URBs */ for (i = 0; i < stream->props.count; i++) { - if ((stream->urb_list[i] = usb_alloc_urb(0,GFP_ATOMIC)) == NULL) + stream->urb_list[i] = usb_alloc_urb(0, GFP_ATOMIC); + if (!stream->urb_list[i]) { + deb_mem("not enough memory for urb_alloc_urb!.\n"); + for (j = 0; j < i; j++) + usb_free_urb(stream->urb_list[i]); return -ENOMEM; - + } usb_fill_bulk_urb( stream->urb_list[i], stream->udev, usb_rcvbulkpipe(stream->udev,stream->props.endpoint), stream->buf_list[i], @@ -170,9 +174,14 @@ static int usb_isoc_urb_init(struct usb_data_stream *stream) for (i = 0; i < stream->props.count; i++) { struct urb *urb; int frame_offset = 0; - if ((stream->urb_list[i] = - usb_alloc_urb(stream->props.u.isoc.framesperurb,GFP_ATOMIC)) == NULL) + + stream->urb_list[i] = usb_alloc_urb(stream->props.u.isoc.framesperurb, GFP_ATOMIC); + if (!stream->urb_list[i]) { + deb_mem("not enough memory for urb_alloc_urb!\n"); + for (j = 0; j < i; j++) + usb_free_urb(stream->urb_list[i]); return -ENOMEM; + } urb = stream->urb_list[i]; diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c index 21c1060cf10e..692b68a9e73b 100644 --- a/drivers/media/dvb/frontends/af9013.c +++ b/drivers/media/dvb/frontends/af9013.c @@ -1187,7 +1187,7 @@ static int af9013_read_status(struct dvb_frontend *fe, fe_status_t *status) if (tmp) *status |= FE_HAS_SYNC | FE_HAS_LOCK; - if (!*status & FE_HAS_SIGNAL) { + if (!(*status & FE_HAS_SIGNAL)) { /* AGC lock */ ret = af9013_read_reg_bits(state, 0xd1a0, 6, 1, &tmp); if (ret) @@ -1196,7 +1196,7 @@ static int af9013_read_status(struct dvb_frontend *fe, fe_status_t *status) *status |= FE_HAS_SIGNAL; } - if (!*status & FE_HAS_CARRIER) { + if (!(*status & FE_HAS_CARRIER)) { /* CFO lock */ ret = af9013_read_reg_bits(state, 0xd333, 7, 1, &tmp); if (ret) @@ -1205,7 +1205,7 @@ static int af9013_read_status(struct dvb_frontend *fe, fe_status_t *status) *status |= FE_HAS_CARRIER; } - if (!*status & FE_HAS_CARRIER) { + if (!(*status & FE_HAS_CARRIER)) { /* SFOE lock */ ret = af9013_read_reg_bits(state, 0xd334, 6, 1, &tmp); if (ret) diff --git a/drivers/media/dvb/siano/sms-cards.c b/drivers/media/dvb/siano/sms-cards.c index 6f9b77360440..e98d6caf2c23 100644 --- a/drivers/media/dvb/siano/sms-cards.c +++ b/drivers/media/dvb/siano/sms-cards.c @@ -95,7 +95,7 @@ static struct sms_board sms_boards[] = { [SMS1XXX_BOARD_HAUPPAUGE_WINDHAM] = { .name = "Hauppauge WinTV MiniStick", .type = SMS_NOVA_B0, - .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-01.fw", + .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw", }, }; diff --git a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c index 66ab0c6e9783..4a3f2b8ea37d 100644 --- a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c +++ b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c @@ -808,6 +808,12 @@ static int ttusb_alloc_iso_urbs(struct ttusb *ttusb) ISO_BUF_COUNT, &ttusb->iso_dma_handle); + if (!ttusb->iso_buffer) { + dprintk("%s: pci_alloc_consistent - not enough memory\n", + __func__); + return -ENOMEM; + } + memset(ttusb->iso_buffer, 0, ISO_FRAME_SIZE * FRAMES_PER_ISO_BUF * ISO_BUF_COUNT); @@ -1659,7 +1665,14 @@ static int ttusb_probe(struct usb_interface *intf, const struct usb_device_id *i ttusb_setup_interfaces(ttusb); - ttusb_alloc_iso_urbs(ttusb); + result = ttusb_alloc_iso_urbs(ttusb); + if (result < 0) { + dprintk("%s: ttusb_alloc_iso_urbs - failed\n", __func__); + mutex_unlock(&ttusb->semi2c); + kfree(ttusb); + return result; + } + if (ttusb_init_controller(ttusb)) printk("ttusb_init_controller: error\n"); diff --git a/drivers/media/dvb/ttusb-dec/ttusb_dec.c b/drivers/media/dvb/ttusb-dec/ttusb_dec.c index ab33fec8a19f..0aa96df80fc2 100644 --- a/drivers/media/dvb/ttusb-dec/ttusb_dec.c +++ b/drivers/media/dvb/ttusb-dec/ttusb_dec.c @@ -1157,6 +1157,12 @@ static int ttusb_dec_alloc_iso_urbs(struct ttusb_dec *dec) ISO_BUF_COUNT), &dec->iso_dma_handle); + if (!dec->iso_buffer) { + dprintk("%s: pci_alloc_consistent - not enough memory\n", + __func__); + return -ENOMEM; + } + memset(dec->iso_buffer, 0, ISO_FRAME_SIZE * (FRAMES_PER_ISO_BUF * ISO_BUF_COUNT)); @@ -1254,6 +1260,7 @@ static int ttusb_dec_init_usb(struct ttusb_dec *dec) dec->irq_buffer = usb_buffer_alloc(dec->udev,IRQ_PACKET_SIZE, GFP_ATOMIC, &dec->irq_dma_handle); if(!dec->irq_buffer) { + usb_free_urb(dec->irq_urb); return -ENOMEM; } usb_fill_int_urb(dec->irq_urb, dec->udev,dec->irq_pipe, diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig index 04cd7c04bdde..5189c4eb439f 100644 --- a/drivers/media/radio/Kconfig +++ b/drivers/media/radio/Kconfig @@ -355,6 +355,20 @@ config USB_SI470X tristate "Silicon Labs Si470x FM Radio Receiver support" depends on USB && VIDEO_V4L2 ---help--- + This is a driver for USB devices with the Silicon Labs SI470x + chip. Currently these devices are known to work: + - 10c4:818a: Silicon Labs USB FM Radio Reference Design + - 06e1:a155: ADS/Tech FM Radio Receiver (formerly Instant FM Music) + - 1b80:d700: KWorld USB FM Radio SnapMusic Mobile 700 (FM700) + + Sound is provided by the ALSA USB Audio/MIDI driver. Therefore + if you don't want to use the device solely for RDS receiving, + it is recommended to also select SND_USB_AUDIO. + + Please have a look at the documentation, especially on how + to redirect the audio stream from the radio to your sound device: + Documentation/video4linux/si470x.txt + Say Y here if you want to connect this type of radio to your computer's USB port. diff --git a/drivers/media/radio/radio-si470x.c b/drivers/media/radio/radio-si470x.c index 5920cd306975..3e1830293de5 100644 --- a/drivers/media/radio/radio-si470x.c +++ b/drivers/media/radio/radio-si470x.c @@ -4,6 +4,7 @@ * Driver for USB radios for the Silicon Labs Si470x FM Radio Receivers: * - Silicon Labs USB FM Radio Reference Design * - ADS/Tech FM Radio Receiver (formerly Instant FM Music) (RDX-155-EF) + * - KWorld USB FM Radio SnapMusic Mobile 700 (FM700) * * Copyright (c) 2008 Tobias Lorenz * @@ -23,19 +24,6 @@ */ -/* - * User Notes: - * - USB Audio is provided by the alsa snd_usb_audio module. - * For listing you have to redirect the sound, for example using: - * arecord -D hw:1,0 -r96000 -c2 -f S16_LE | artsdsp aplay -B - - * - regarding module parameters in /sys/module/radio_si470x/parameters: - * the contents of read-only files (0444) are not updated, even if - * space, band and de are changed using private video controls - * - increase tune_timeout, if you often get -EIO errors - * - hw_freq_seek returns -EAGAIN, when timed out or band limit is reached - */ - - /* * History: * 2008-01-12 Tobias Lorenz @@ -105,6 +93,9 @@ * - afc indication * - more safety checks, let si470x_get_freq return errno * - vidioc behavior corrected according to v4l2 spec + * 2008-10-20 Alexey Klimov + * - add support for KWorld USB FM Radio FM700 + * - blacklisted KWorld radio in hid-core.c and hid-ids.h * * ToDo: * - add firmware download/update support @@ -145,6 +136,8 @@ static struct usb_device_id si470x_usb_driver_id_table[] = { { USB_DEVICE_AND_INTERFACE_INFO(0x10c4, 0x818a, USB_CLASS_HID, 0, 0) }, /* ADS/Tech FM Radio Receiver (formerly Instant FM Music) */ { USB_DEVICE_AND_INTERFACE_INFO(0x06e1, 0xa155, USB_CLASS_HID, 0, 0) }, + /* KWorld USB FM Radio SnapMusic Mobile 700 (FM700) */ + { USB_DEVICE_AND_INTERFACE_INFO(0x1b80, 0xd700, USB_CLASS_HID, 0, 0) }, /* Terminating entry */ { } }; diff --git a/drivers/media/video/cafe_ccic.c b/drivers/media/video/cafe_ccic.c index a8c068e1de1c..1740b9ebdcef 100644 --- a/drivers/media/video/cafe_ccic.c +++ b/drivers/media/video/cafe_ccic.c @@ -1476,12 +1476,9 @@ static int cafe_v4l_open(struct inode *inode, struct file *filp) { struct cafe_camera *cam; - lock_kernel(); cam = cafe_find_dev(iminor(inode)); - if (cam == NULL) { - unlock_kernel(); + if (cam == NULL) return -ENODEV; - } filp->private_data = cam; mutex_lock(&cam->s_mutex); @@ -1493,7 +1490,6 @@ static int cafe_v4l_open(struct inode *inode, struct file *filp) } (cam->users)++; mutex_unlock(&cam->s_mutex); - unlock_kernel(); return 0; } diff --git a/drivers/media/video/compat_ioctl32.c b/drivers/media/video/compat_ioctl32.c index bd5d9de5a008..e6ca4012b5f0 100644 --- a/drivers/media/video/compat_ioctl32.c +++ b/drivers/media/video/compat_ioctl32.c @@ -867,6 +867,7 @@ long v4l_compat_ioctl32(struct file *file, unsigned int cmd, unsigned long arg) case VIDIOC_STREAMON32: case VIDIOC_STREAMOFF32: case VIDIOC_G_PARM: + case VIDIOC_S_PARM: case VIDIOC_G_STD: case VIDIOC_S_STD: case VIDIOC_G_TUNER: @@ -885,6 +886,8 @@ long v4l_compat_ioctl32(struct file *file, unsigned int cmd, unsigned long arg) case VIDIOC_S_INPUT32: case VIDIOC_TRY_FMT32: case VIDIOC_S_HW_FREQ_SEEK: + case VIDIOC_ENUM_FRAMESIZES: + case VIDIOC_ENUM_FRAMEINTERVALS: ret = do_video_ioctl(file, cmd, arg); break; diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 7a1a7830a6b3..7874d9790a51 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -448,7 +448,14 @@ static int __devinit cx18_init_struct1(struct cx18 *cx) mutex_init(&cx->gpio_lock); spin_lock_init(&cx->lock); - spin_lock_init(&cx->dma_reg_lock); + + cx->work_queue = create_singlethread_workqueue(cx->name); + if (cx->work_queue == NULL) { + CX18_ERR("Could not create work queue\n"); + return -1; + } + + INIT_WORK(&cx->work, cx18_work_handler); /* start counting open_id at 1 */ cx->open_id = 1; @@ -581,10 +588,10 @@ static void cx18_load_and_init_modules(struct cx18 *cx) #ifdef MODULE /* load modules */ -#ifndef CONFIG_MEDIA_TUNER +#ifdef CONFIG_MEDIA_TUNER_MODULE hw = cx18_request_module(cx, hw, "tuner", CX18_HW_TUNER); #endif -#ifndef CONFIG_VIDEO_CS5345 +#ifdef CONFIG_VIDEO_CS5345_MODULE hw = cx18_request_module(cx, hw, "cs5345", CX18_HW_CS5345); #endif #endif @@ -832,6 +839,7 @@ free_map: free_mem: release_mem_region(cx->base_addr, CX18_MEM_SIZE); free_workqueue: + destroy_workqueue(cx->work_queue); err: if (retval == 0) retval = -ENODEV; @@ -932,6 +940,9 @@ static void cx18_remove(struct pci_dev *pci_dev) cx18_halt_firmware(cx); + flush_workqueue(cx->work_queue); + destroy_workqueue(cx->work_queue); + cx18_streams_cleanup(cx, 1); exit_cx18_i2c(cx); diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h index a4b1708fafe7..bbdd5f25041d 100644 --- a/drivers/media/video/cx18/cx18-driver.h +++ b/drivers/media/video/cx18/cx18-driver.h @@ -199,12 +199,15 @@ struct cx18_options { #define CX18_F_S_APPL_IO 8 /* this stream is used read/written by an application */ /* per-cx18, i_flags */ -#define CX18_F_I_LOADED_FW 0 /* Loaded the firmware the first time */ -#define CX18_F_I_EOS 4 /* End of encoder stream reached */ -#define CX18_F_I_RADIO_USER 5 /* The radio tuner is selected */ -#define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */ -#define CX18_F_I_INITED 21 /* set after first open */ -#define CX18_F_I_FAILED 22 /* set if first open failed */ +#define CX18_F_I_LOADED_FW 0 /* Loaded firmware 1st time */ +#define CX18_F_I_EOS 4 /* End of encoder stream */ +#define CX18_F_I_RADIO_USER 5 /* radio tuner is selected */ +#define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */ +#define CX18_F_I_HAVE_WORK 15 /* there is work to be done */ +#define CX18_F_I_WORK_HANDLER_DVB 18 /* work to be done for DVB */ +#define CX18_F_I_INITED 21 /* set after first open */ +#define CX18_F_I_FAILED 22 /* set if first open failed */ +#define CX18_F_I_WORK_INITED 23 /* worker thread initialized */ /* These are the VBI types as they appear in the embedded VBI private packets. */ #define CX18_SLICED_TYPE_TELETEXT_B (1) @@ -402,8 +405,6 @@ struct cx18 { spinlock_t lock; /* lock access to this struct */ int search_pack_header; - spinlock_t dma_reg_lock; /* lock access to DMA engine registers */ - int open_id; /* incremented each time an open occurs, used as unique ID. Starts at 1, so 0 can be used as uninitialized value in the stream->id. */ @@ -433,6 +434,9 @@ struct cx18 { /* when the current DMA is finished this queue is woken up */ wait_queue_head_t dma_waitq; + struct workqueue_struct *work_queue; + struct work_struct work; + /* i2c */ struct i2c_adapter i2c_adap[2]; struct i2c_algo_bit_data i2c_algo[2]; diff --git a/drivers/media/video/cx18/cx18-dvb.c b/drivers/media/video/cx18/cx18-dvb.c index afc694e7bdb2..4542e2e5e3d7 100644 --- a/drivers/media/video/cx18/cx18-dvb.c +++ b/drivers/media/video/cx18/cx18-dvb.c @@ -23,6 +23,8 @@ #include "cx18-dvb.h" #include "cx18-io.h" #include "cx18-streams.h" +#include "cx18-queue.h" +#include "cx18-scb.h" #include "cx18-cards.h" #include "s5h1409.h" #include "mxl5005s.h" @@ -300,3 +302,24 @@ static int dvb_register(struct cx18_stream *stream) return ret; } + +void cx18_dvb_work_handler(struct cx18 *cx) +{ + struct cx18_buffer *buf; + struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_TS]; + + while ((buf = cx18_dequeue(s, &s->q_full)) != NULL) { + if (s->dvb.enabled) + dvb_dmx_swfilter(&s->dvb.demux, buf->buf, + buf->bytesused); + + cx18_enqueue(s, buf, &s->q_free); + cx18_buf_sync_for_device(s, buf); + if (s->handle == CX18_INVALID_TASK_HANDLE) /* FIXME: improve */ + continue; + + cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle, + (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem, + 1, buf->id, s->buf_size); + } +} diff --git a/drivers/media/video/cx18/cx18-dvb.h b/drivers/media/video/cx18/cx18-dvb.h index bf8d8f6f5455..bbdcefc87f28 100644 --- a/drivers/media/video/cx18/cx18-dvb.h +++ b/drivers/media/video/cx18/cx18-dvb.h @@ -23,3 +23,4 @@ int cx18_dvb_register(struct cx18_stream *stream); void cx18_dvb_unregister(struct cx18_stream *stream); +void cx18_dvb_work_handler(struct cx18 *cx); diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c index 700ab9439c16..220fae8d4ad7 100644 --- a/drivers/media/video/cx18/cx18-io.c +++ b/drivers/media/video/cx18/cx18-io.c @@ -88,6 +88,19 @@ void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) cx18_log_write_retries(cx, i, addr); } +void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, + u32 eval, u32 mask) +{ + int i; + eval &= mask; + for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + cx18_writel_noretry(cx, val, addr); + if (eval == (cx18_readl_noretry(cx, addr) & mask)) + break; + } + cx18_log_write_retries(cx, i, addr); +} + void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) { int i; @@ -218,7 +231,7 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) { u32 r; - cx18_write_reg(cx, val, SW1_INT_STATUS); + cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); } @@ -233,7 +246,7 @@ void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) { u32 r; - cx18_write_reg(cx, val, SW2_INT_STATUS); + cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); } diff --git a/drivers/media/video/cx18/cx18-io.h b/drivers/media/video/cx18/cx18-io.h index 287a5e8bf67b..425244453ea7 100644 --- a/drivers/media/video/cx18/cx18-io.h +++ b/drivers/media/video/cx18/cx18-io.h @@ -133,6 +133,8 @@ static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) cx18_writel_noretry(cx, val, addr); } +void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, + u32 eval, u32 mask); static inline void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) @@ -271,6 +273,21 @@ static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) cx18_write_reg_noretry(cx, val, reg); } +static inline void _cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, + u32 eval, u32 mask) +{ + _cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); +} + +static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, + u32 eval, u32 mask) +{ + if (cx18_retry_mmio) + _cx18_write_reg_expect(cx, val, reg, eval, mask); + else + cx18_write_reg_noretry(cx, val, reg); +} + static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg) { diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c index 360330f5463f..5fbfbd0f1493 100644 --- a/drivers/media/video/cx18/cx18-irq.c +++ b/drivers/media/video/cx18/cx18-irq.c @@ -29,8 +29,20 @@ #include "cx18-mailbox.h" #include "cx18-vbi.h" #include "cx18-scb.h" +#include "cx18-dvb.h" -#define DMA_MAGIC_COOKIE 0x000001fe +void cx18_work_handler(struct work_struct *work) +{ + struct cx18 *cx = container_of(work, struct cx18, work); + if (test_and_clear_bit(CX18_F_I_WORK_INITED, &cx->i_flags)) { + struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 }; + /* This thread must use the FIFO scheduler as it + * is realtime sensitive. */ + sched_setscheduler(current, SCHED_FIFO, ¶m); + } + if (test_and_clear_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags)) + cx18_dvb_work_handler(cx); +} static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) { @@ -67,17 +79,11 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) if (buf) { cx18_buf_sync_for_cpu(s, buf); if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) { - /* process the buffer here */ - CX18_DEBUG_HI_DMA("TS recv and sent bytesused=%d\n", - buf->bytesused); - - dvb_dmx_swfilter(&s->dvb.demux, buf->buf, + CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n", buf->bytesused); - cx18_buf_sync_for_device(s, buf); - cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle, - (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem, - 1, buf->id, s->buf_size); + set_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags); + set_bit(CX18_F_I_HAVE_WORK, &cx->i_flags); } else set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); } else { @@ -109,7 +115,7 @@ static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb) CX18_INFO("FW version: %s\n", p - 1); } -static void hpu_cmd(struct cx18 *cx, u32 sw1) +static void epu_cmd(struct cx18 *cx, u32 sw1) { struct cx18_mailbox mb; @@ -125,12 +131,31 @@ static void hpu_cmd(struct cx18 *cx, u32 sw1) epu_debug(cx, &mb); break; default: - CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd); + CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n", + mb.cmd); break; } } - if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU)) - CX18_WARN("Unexpected interrupt %08x\n", sw1); + + if (sw1 & IRQ_APU_TO_EPU) { + cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb)); + CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd); + } + + if (sw1 & IRQ_HPU_TO_EPU) { + cx18_memcpy_fromio(cx, &mb, &cx->scb->hpu2epu_mb, sizeof(mb)); + CX18_WARN("Unknown HPU_TO_EPU mailbox command %#08x\n", mb.cmd); + } +} + +static void xpu_ack(struct cx18 *cx, u32 sw2) +{ + if (sw2 & IRQ_CPU_TO_EPU_ACK) + wake_up(&cx->mb_cpu_waitq); + if (sw2 & IRQ_APU_TO_EPU_ACK) + wake_up(&cx->mb_apu_waitq); + if (sw2 & IRQ_HPU_TO_EPU_ACK) + wake_up(&cx->mb_hpu_waitq); } irqreturn_t cx18_irq_handler(int irq, void *dev_id) @@ -140,43 +165,36 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id) u32 sw2, sw2_mask; u32 hw2, hw2_mask; - spin_lock(&cx->dma_reg_lock); - + sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); + sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; + sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); + sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; - sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK; - sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; - sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU; - sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; - cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS); - cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS); - cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS); + if (sw1) + cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1); + if (sw2) + cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2); + if (hw2) + cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2); if (sw1 || sw2 || hw2) CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); /* To do: interrupt-based I2C handling - if (hw2 & 0x00c00000) { + if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) { } */ - if (sw2) { - if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) | - cx18_readl(cx, &cx->scb->cpu2epu_irq_ack))) - wake_up(&cx->mb_cpu_waitq); - if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) | - cx18_readl(cx, &cx->scb->apu2epu_irq_ack))) - wake_up(&cx->mb_apu_waitq); - if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack)) - wake_up(&cx->mb_epu_waitq); - if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack)) - wake_up(&cx->mb_hpu_waitq); - } + if (sw2) + xpu_ack(cx, sw2); if (sw1) - hpu_cmd(cx, sw1); - spin_unlock(&cx->dma_reg_lock); + epu_cmd(cx, sw1); + + if (test_and_clear_bit(CX18_F_I_HAVE_WORK, &cx->i_flags)) + queue_work(cx->work_queue, &cx->work); - return (hw2 | sw1 | sw2) ? IRQ_HANDLED : IRQ_NONE; + return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; } diff --git a/drivers/media/video/cx18/cx18-irq.h b/drivers/media/video/cx18/cx18-irq.h index 379f704f5cba..6173ca3bc9e4 100644 --- a/drivers/media/video/cx18/cx18-irq.h +++ b/drivers/media/video/cx18/cx18-irq.h @@ -32,6 +32,4 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id); -void cx18_irq_work_handler(struct work_struct *work); -void cx18_dma_stream_dec_prepare(struct cx18_stream *s, u32 offset, int lock); -void cx18_unfinished_dma(unsigned long arg); +void cx18_work_handler(struct work_struct *work); diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c index 9d18dd22de76..acff7dfb60df 100644 --- a/drivers/media/video/cx18/cx18-mailbox.c +++ b/drivers/media/video/cx18/cx18-mailbox.c @@ -83,7 +83,7 @@ static const struct cx18_api_info api_info[] = { API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST), - API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, 0), + API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW), API_ENTRY(0, 0, 0), }; @@ -176,7 +176,7 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb) cx18_setup_page(cx, SCB_OFFSET); cx18_write_sync(cx, mb->request, &ack_mb->ack); - cx18_write_reg(cx, ack_irq, SW2_INT_SET); + cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); return 0; } @@ -225,7 +225,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) } if (info->flags & API_FAST) timeout /= 2; - cx18_write_reg(cx, irq, SW1_INT_SET); + cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq); while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request) && cnt < 660) { diff --git a/drivers/media/video/cx18/cx18-queue.c b/drivers/media/video/cx18/cx18-queue.c index a33ba04a2686..174682c2582f 100644 --- a/drivers/media/video/cx18/cx18-queue.c +++ b/drivers/media/video/cx18/cx18-queue.c @@ -88,15 +88,13 @@ struct cx18_buffer *cx18_queue_get_buf_irq(struct cx18_stream *s, u32 id, if (buf->id != id) continue; + buf->bytesused = bytesused; - /* the transport buffers are handled differently, - they are not moved to the full queue */ - if (s->type != CX18_ENC_STREAM_TYPE_TS) { - atomic_dec(&s->q_free.buffers); - atomic_inc(&s->q_full.buffers); - s->q_full.bytesused += buf->bytesused; - list_move_tail(&buf->list, &s->q_full.list); - } + atomic_dec(&s->q_free.buffers); + atomic_inc(&s->q_full.buffers); + s->q_full.bytesused += buf->bytesused; + list_move_tail(&buf->list, &s->q_full.list); + spin_unlock(&s->qlock); return buf; } diff --git a/drivers/media/video/cx18/cx18-scb.h b/drivers/media/video/cx18/cx18-scb.h index 86b4cb15d163..594713bbed68 100644 --- a/drivers/media/video/cx18/cx18-scb.h +++ b/drivers/media/video/cx18/cx18-scb.h @@ -128,22 +128,22 @@ struct cx18_scb { u32 apu2cpu_irq; /* Value to write to register SW2 register set (0xC7003140) after the command is cleared */ - u32 apu2cpu_irq_ack; + u32 cpu2apu_irq_ack; u32 reserved2[13]; u32 hpu2cpu_mb_offset; u32 hpu2cpu_irq; - u32 hpu2cpu_irq_ack; + u32 cpu2hpu_irq_ack; u32 reserved3[13]; u32 ppu2cpu_mb_offset; u32 ppu2cpu_irq; - u32 ppu2cpu_irq_ack; + u32 cpu2ppu_irq_ack; u32 reserved4[13]; u32 epu2cpu_mb_offset; u32 epu2cpu_irq; - u32 epu2cpu_irq_ack; + u32 cpu2epu_irq_ack; u32 reserved5[13]; u32 reserved6[8]; @@ -153,22 +153,22 @@ struct cx18_scb { u32 reserved11[7]; u32 cpu2apu_mb_offset; u32 cpu2apu_irq; - u32 cpu2apu_irq_ack; + u32 apu2cpu_irq_ack; u32 reserved12[13]; u32 hpu2apu_mb_offset; u32 hpu2apu_irq; - u32 hpu2apu_irq_ack; + u32 apu2hpu_irq_ack; u32 reserved13[13]; u32 ppu2apu_mb_offset; u32 ppu2apu_irq; - u32 ppu2apu_irq_ack; + u32 apu2ppu_irq_ack; u32 reserved14[13]; u32 epu2apu_mb_offset; u32 epu2apu_irq; - u32 epu2apu_irq_ack; + u32 apu2epu_irq_ack; u32 reserved15[13]; u32 reserved16[8]; @@ -178,22 +178,22 @@ struct cx18_scb { u32 reserved21[7]; u32 cpu2hpu_mb_offset; u32 cpu2hpu_irq; - u32 cpu2hpu_irq_ack; + u32 hpu2cpu_irq_ack; u32 reserved22[13]; u32 apu2hpu_mb_offset; u32 apu2hpu_irq; - u32 apu2hpu_irq_ack; + u32 hpu2apu_irq_ack; u32 reserved23[13]; u32 ppu2hpu_mb_offset; u32 ppu2hpu_irq; - u32 ppu2hpu_irq_ack; + u32 hpu2ppu_irq_ack; u32 reserved24[13]; u32 epu2hpu_mb_offset; u32 epu2hpu_irq; - u32 epu2hpu_irq_ack; + u32 hpu2epu_irq_ack; u32 reserved25[13]; u32 reserved26[8]; @@ -203,22 +203,22 @@ struct cx18_scb { u32 reserved31[7]; u32 cpu2ppu_mb_offset; u32 cpu2ppu_irq; - u32 cpu2ppu_irq_ack; + u32 ppu2cpu_irq_ack; u32 reserved32[13]; u32 apu2ppu_mb_offset; u32 apu2ppu_irq; - u32 apu2ppu_irq_ack; + u32 ppu2apu_irq_ack; u32 reserved33[13]; u32 hpu2ppu_mb_offset; u32 hpu2ppu_irq; - u32 hpu2ppu_irq_ack; + u32 ppu2hpu_irq_ack; u32 reserved34[13]; u32 epu2ppu_mb_offset; u32 epu2ppu_irq; - u32 epu2ppu_irq_ack; + u32 ppu2epu_irq_ack; u32 reserved35[13]; u32 reserved36[8]; @@ -228,22 +228,22 @@ struct cx18_scb { u32 reserved41[7]; u32 cpu2epu_mb_offset; u32 cpu2epu_irq; - u32 cpu2epu_irq_ack; + u32 epu2cpu_irq_ack; u32 reserved42[13]; u32 apu2epu_mb_offset; u32 apu2epu_irq; - u32 apu2epu_irq_ack; + u32 epu2apu_irq_ack; u32 reserved43[13]; u32 hpu2epu_mb_offset; u32 hpu2epu_irq; - u32 hpu2epu_irq_ack; + u32 epu2hpu_irq_ack; u32 reserved44[13]; u32 ppu2epu_mb_offset; u32 ppu2epu_irq; - u32 ppu2epu_irq_ack; + u32 epu2ppu_irq_ack; u32 reserved45[13]; u32 reserved46[8]; diff --git a/drivers/media/video/cx88/cx88-blackbird.c b/drivers/media/video/cx88/cx88-blackbird.c index 078be6319556..d3ae5b4dfca7 100644 --- a/drivers/media/video/cx88/cx88-blackbird.c +++ b/drivers/media/video/cx88/cx88-blackbird.c @@ -1078,7 +1078,7 @@ static int mpeg_open(struct inode *inode, struct file *file) } } - if (blackbird_initialize_codec(dev) < 0) { + if (!atomic_read(&dev->core->mpeg_users) && blackbird_initialize_codec(dev) < 0) { if (drv) drv->request_release(drv); unlock_kernel(); @@ -1109,6 +1109,8 @@ static int mpeg_open(struct inode *inode, struct file *file) fh->mpegq.field); unlock_kernel(); + atomic_inc(&dev->core->mpeg_users); + return 0; } @@ -1118,7 +1120,7 @@ static int mpeg_release(struct inode *inode, struct file *file) struct cx8802_dev *dev = fh->dev; struct cx8802_driver *drv = NULL; - if (dev->mpeg_active) + if (dev->mpeg_active && atomic_read(&dev->core->mpeg_users) == 1) blackbird_stop_codec(dev); cx8802_cancel_buffers(fh->dev); @@ -1138,6 +1140,8 @@ static int mpeg_release(struct inode *inode, struct file *file) if (drv) drv->request_release(drv); + atomic_dec(&dev->core->mpeg_users); + return 0; } @@ -1158,6 +1162,10 @@ static unsigned int mpeg_poll(struct file *file, struct poll_table_struct *wait) { struct cx8802_fh *fh = file->private_data; + struct cx8802_dev *dev = fh->dev; + + if (!dev->mpeg_active) + blackbird_start_codec(file, fh); return videobuf_poll_stream(file, &fh->mpegq, wait); } diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c index cf6c30d4e545..309ca5e68063 100644 --- a/drivers/media/video/cx88/cx88-dvb.c +++ b/drivers/media/video/cx88/cx88-dvb.c @@ -598,6 +598,11 @@ static int dvb_register(struct cx8802_dev *dev) struct videobuf_dvb_frontend *fe0, *fe1 = NULL; int mfe_shared = 0; /* bus not shared by default */ + if (0 != core->i2c_rc) { + printk(KERN_ERR "%s/2: no i2c-bus available, cannot attach dvb drivers\n", core->name); + goto frontend_detach; + } + /* Get the first frontend */ fe0 = videobuf_dvb_get_frontend(&dev->frontends, 1); if (!fe0) diff --git a/drivers/media/video/cx88/cx88-mpeg.c b/drivers/media/video/cx88/cx88-mpeg.c index a1c435b4b1cd..3ebdcd1d83f8 100644 --- a/drivers/media/video/cx88/cx88-mpeg.c +++ b/drivers/media/video/cx88/cx88-mpeg.c @@ -769,10 +769,6 @@ static int __devinit cx8802_probe(struct pci_dev *pci_dev, struct cx8802_dev *dev; struct cx88_core *core; int err; -#if defined(CONFIG_VIDEO_CX88_DVB) || defined(CONFIG_VIDEO_CX88_DVB_MODULE) - struct videobuf_dvb_frontend *demod; - int i; -#endif /* general setup */ core = cx88_core_get(pci_dev); @@ -803,15 +799,21 @@ static int __devinit cx8802_probe(struct pci_dev *pci_dev, mutex_init(&dev->frontends.lock); INIT_LIST_HEAD(&dev->frontends.felist); - if (core->board.num_frontends) - printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, core->board.num_frontends); - - for (i = 1; i <= core->board.num_frontends; i++) { - demod = videobuf_dvb_alloc_frontend(&dev->frontends, i); - if(demod == NULL) { - printk(KERN_ERR "%s() failed to alloc\n", __func__); - err = -ENOMEM; - goto fail_free; + if (core->board.num_frontends) { + struct videobuf_dvb_frontend *fe; + int i; + + printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, + core->board.num_frontends); + for (i = 1; i <= core->board.num_frontends; i++) { + fe = videobuf_dvb_alloc_frontend(&dev->frontends, i); + if(fe == NULL) { + printk(KERN_ERR "%s() failed to alloc\n", + __func__); + videobuf_dvb_dealloc_frontends(&dev->frontends); + err = -ENOMEM; + goto fail_free; + } } } #endif diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c index 61265fd04d56..b96ce991d968 100644 --- a/drivers/media/video/cx88/cx88-video.c +++ b/drivers/media/video/cx88/cx88-video.c @@ -1216,8 +1216,12 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) struct cx8800_fh *fh = priv; struct cx8800_dev *dev = fh->dev; - if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) + /* We should remember that this driver also supports teletext, */ + /* so we have to test if the v4l2_buf_type is VBI capture data. */ + if (unlikely((fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) && + (fh->type != V4L2_BUF_TYPE_VBI_CAPTURE))) return -EINVAL; + if (unlikely(i != fh->type)) return -EINVAL; @@ -1232,8 +1236,10 @@ static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) struct cx8800_dev *dev = fh->dev; int err, res; - if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if ((fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) && + (fh->type != V4L2_BUF_TYPE_VBI_CAPTURE)) return -EINVAL; + if (i != fh->type) return -EINVAL; diff --git a/drivers/media/video/cx88/cx88.h b/drivers/media/video/cx88/cx88.h index 76207c2856b7..f4240965be32 100644 --- a/drivers/media/video/cx88/cx88.h +++ b/drivers/media/video/cx88/cx88.h @@ -352,6 +352,7 @@ struct cx88_core { /* various v4l controls */ u32 freq; atomic_t users; + atomic_t mpeg_users; /* cx88-video needs to access cx8802 for hybrid tuner pll access. */ struct cx8802_dev *dvbdev; diff --git a/drivers/media/video/em28xx/em28xx-audio.c b/drivers/media/video/em28xx/em28xx-audio.c index ac3292d7646c..7a8d49ef646e 100644 --- a/drivers/media/video/em28xx/em28xx-audio.c +++ b/drivers/media/video/em28xx/em28xx-audio.c @@ -62,7 +62,7 @@ static int em28xx_isoc_audio_deinit(struct em28xx *dev) dprintk("Stopping isoc\n"); for (i = 0; i < EM28XX_AUDIO_BUFS; i++) { - usb_kill_urb(dev->adev->urb[i]); + usb_unlink_urb(dev->adev->urb[i]); usb_free_urb(dev->adev->urb[i]); dev->adev->urb[i] = NULL; } @@ -75,7 +75,6 @@ static void em28xx_audio_isocirq(struct urb *urb) struct em28xx *dev = urb->context; int i; unsigned int oldptr; - unsigned long flags; int period_elapsed = 0; int status; unsigned char *cp; @@ -96,9 +95,21 @@ static void em28xx_audio_isocirq(struct urb *urb) if (!length) continue; - spin_lock_irqsave(&dev->adev->slock, flags); - oldptr = dev->adev->hwptr_done_capture; + if (oldptr + length >= runtime->buffer_size) { + unsigned int cnt = + runtime->buffer_size - oldptr; + memcpy(runtime->dma_area + oldptr * stride, cp, + cnt * stride); + memcpy(runtime->dma_area, cp + cnt * stride, + length * stride - cnt * stride); + } else { + memcpy(runtime->dma_area + oldptr * stride, cp, + length * stride); + } + + snd_pcm_stream_lock(substream); + dev->adev->hwptr_done_capture += length; if (dev->adev->hwptr_done_capture >= runtime->buffer_size) @@ -113,19 +124,7 @@ static void em28xx_audio_isocirq(struct urb *urb) period_elapsed = 1; } - spin_unlock_irqrestore(&dev->adev->slock, flags); - - if (oldptr + length >= runtime->buffer_size) { - unsigned int cnt = - runtime->buffer_size - oldptr; - memcpy(runtime->dma_area + oldptr * stride, cp, - cnt * stride); - memcpy(runtime->dma_area, cp + cnt * stride, - length * stride - cnt * stride); - } else { - memcpy(runtime->dma_area + oldptr * stride, cp, - length * stride); - } + snd_pcm_stream_unlock(substream); } if (period_elapsed) snd_pcm_period_elapsed(substream); diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c index 5d837c16ee22..15e2b525310d 100644 --- a/drivers/media/video/em28xx/em28xx-core.c +++ b/drivers/media/video/em28xx/em28xx-core.c @@ -69,19 +69,33 @@ int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, int ret, byte; if (dev->state & DEV_DISCONNECTED) - return(-ENODEV); + return -ENODEV; + + if (len > URB_MAX_CTRL_SIZE) + return -EINVAL; em28xx_regdbg("req=%02x, reg=%02x ", req, reg); + mutex_lock(&dev->ctrl_urb_lock); ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - 0x0000, reg, buf, len, HZ); + 0x0000, reg, dev->urb_buf, len, HZ); + if (ret < 0) { + if (reg_debug) + printk(" failed!\n"); + mutex_unlock(&dev->ctrl_urb_lock); + return ret; + } + + if (len) + memcpy(buf, dev->urb_buf, len); + + mutex_unlock(&dev->ctrl_urb_lock); if (reg_debug) { - printk(ret < 0 ? " failed!\n" : "%02x values: ", ret); + printk("%02x values: ", ret); for (byte = 0; byte < len; byte++) printk(" %02x", (unsigned char)buf[byte]); - printk("\n"); } @@ -102,16 +116,20 @@ int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg) em28xx_regdbg("req=%02x, reg=%02x:", req, reg); + mutex_lock(&dev->ctrl_urb_lock); ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - 0x0000, reg, &val, 1, HZ); - - if (reg_debug) - printk(ret < 0 ? " failed!\n" : - "%02x\n", (unsigned char) val); + 0x0000, reg, dev->urb_buf, 1, HZ); + val = dev->urb_buf[0]; + mutex_unlock(&dev->ctrl_urb_lock); - if (ret < 0) + if (ret < 0) { + printk(" failed!\n"); return ret; + } + + if (reg_debug) + printk("%02x\n", (unsigned char) val); return val; } @@ -130,19 +148,13 @@ int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, { int ret; - /*usb_control_msg seems to expect a kmalloced buffer */ - unsigned char *bufs; - if (dev->state & DEV_DISCONNECTED) return -ENODEV; - if (len < 1) + if ((len < 1) || (len > URB_MAX_CTRL_SIZE)) return -EINVAL; - bufs = kmalloc(len, GFP_KERNEL); - em28xx_regdbg("req=%02x reg=%02x:", req, reg); - if (reg_debug) { int i; for (i = 0; i < len; ++i) @@ -150,16 +162,16 @@ int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, printk("\n"); } - if (!bufs) - return -ENOMEM; - memcpy(bufs, buf, len); + mutex_lock(&dev->ctrl_urb_lock); + memcpy(dev->urb_buf, buf, len); ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - 0x0000, reg, bufs, len, HZ); + 0x0000, reg, dev->urb_buf, len, HZ); + mutex_unlock(&dev->ctrl_urb_lock); + if (dev->wait_after_write) msleep(dev->wait_after_write); - kfree(bufs); return ret; } @@ -270,6 +282,8 @@ static int em28xx_set_audio_source(struct em28xx *dev) break; case EM28XX_AMUX_LINE_IN: input = EM28XX_AUDIO_SRC_LINE; + video = disable; + line = enable; break; case EM28XX_AMUX_AC97_VIDEO: input = EM28XX_AUDIO_SRC_LINE; diff --git a/drivers/media/video/em28xx/em28xx-i2c.c b/drivers/media/video/em28xx/em28xx-i2c.c index 3bab56b997fc..2360c61ddca9 100644 --- a/drivers/media/video/em28xx/em28xx-i2c.c +++ b/drivers/media/video/em28xx/em28xx-i2c.c @@ -337,9 +337,9 @@ static int em28xx_i2c_eeprom(struct em28xx *dev, unsigned char *eedata, int len) /* Check if board has eeprom */ err = i2c_master_recv(&dev->i2c_client, &buf, 0); if (err < 0) { - em28xx_errdev("%s: i2c_master_recv failed! err [%d]\n", - __func__, err); - return err; + em28xx_errdev("board has no eeprom\n"); + memset(eedata, 0, len); + return -ENODEV; } buf = 0; @@ -609,14 +609,16 @@ int em28xx_i2c_register(struct em28xx *dev) dev->i2c_client.adapter = &dev->i2c_adap; retval = em28xx_i2c_eeprom(dev, dev->eedata, sizeof(dev->eedata)); - if (retval < 0) { + if ((retval < 0) && (retval != -ENODEV)) { em28xx_errdev("%s: em28xx_i2_eeprom failed! retval [%d]\n", __func__, retval); + return retval; } if (i2c_scan) em28xx_do_i2c_scan(dev); + return 0; } diff --git a/drivers/media/video/em28xx/em28xx-video.c b/drivers/media/video/em28xx/em28xx-video.c index a1ab2ef45578..610f535a257c 100644 --- a/drivers/media/video/em28xx/em28xx-video.c +++ b/drivers/media/video/em28xx/em28xx-video.c @@ -73,6 +73,7 @@ MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL"); static LIST_HEAD(em28xx_devlist); +static DEFINE_MUTEX(em28xx_devlist_mutex); static unsigned int card[] = {[0 ... (EM28XX_MAXBOARDS - 1)] = UNSET }; static unsigned int video_nr[] = {[0 ... (EM28XX_MAXBOARDS - 1)] = UNSET }; @@ -1519,7 +1520,7 @@ static int em28xx_v4l2_open(struct inode *inode, struct file *filp) struct em28xx_fh *fh; enum v4l2_buf_type fh_type = 0; - lock_kernel(); + mutex_lock(&em28xx_devlist_mutex); list_for_each_entry(h, &em28xx_devlist, devlist) { if (h->vdev->minor == minor) { dev = h; @@ -1535,10 +1536,11 @@ static int em28xx_v4l2_open(struct inode *inode, struct file *filp) dev = h; } } - if (NULL == dev) { - unlock_kernel(); + mutex_unlock(&em28xx_devlist_mutex); + if (NULL == dev) return -ENODEV; - } + + mutex_lock(&dev->lock); em28xx_videodbg("open minor=%d type=%s users=%d\n", minor, v4l2_type_names[fh_type], dev->users); @@ -1547,10 +1549,9 @@ static int em28xx_v4l2_open(struct inode *inode, struct file *filp) fh = kzalloc(sizeof(struct em28xx_fh), GFP_KERNEL); if (!fh) { em28xx_errdev("em28xx-video.c: Out of memory?!\n"); - unlock_kernel(); + mutex_unlock(&dev->lock); return -ENOMEM; } - mutex_lock(&dev->lock); fh->dev = dev; fh->radio = radio; fh->type = fh_type; @@ -1584,7 +1585,6 @@ static int em28xx_v4l2_open(struct inode *inode, struct file *filp) sizeof(struct em28xx_buffer), fh); mutex_unlock(&dev->lock); - unlock_kernel(); return errCode; } @@ -1871,6 +1871,7 @@ int em28xx_register_extension(struct em28xx_ops *ops) { struct em28xx *dev = NULL; + mutex_lock(&em28xx_devlist_mutex); mutex_lock(&em28xx_extension_devlist_lock); list_add_tail(&ops->next, &em28xx_extension_devlist); list_for_each_entry(dev, &em28xx_devlist, devlist) { @@ -1879,6 +1880,7 @@ int em28xx_register_extension(struct em28xx_ops *ops) } printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name); mutex_unlock(&em28xx_extension_devlist_lock); + mutex_unlock(&em28xx_devlist_mutex); return 0; } EXPORT_SYMBOL(em28xx_register_extension); @@ -1887,6 +1889,7 @@ void em28xx_unregister_extension(struct em28xx_ops *ops) { struct em28xx *dev = NULL; + mutex_lock(&em28xx_devlist_mutex); list_for_each_entry(dev, &em28xx_devlist, devlist) { if (dev) ops->fini(dev); @@ -1896,6 +1899,7 @@ void em28xx_unregister_extension(struct em28xx_ops *ops) printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name); list_del(&ops->next); mutex_unlock(&em28xx_extension_devlist_lock); + mutex_unlock(&em28xx_devlist_mutex); } EXPORT_SYMBOL(em28xx_unregister_extension); @@ -1921,6 +1925,60 @@ static struct video_device *em28xx_vdev_init(struct em28xx *dev, } +static int register_analog_devices(struct em28xx *dev) +{ + int ret; + + /* allocate and fill video video_device struct */ + dev->vdev = em28xx_vdev_init(dev, &em28xx_video_template, "video"); + if (!dev->vdev) { + em28xx_errdev("cannot allocate video_device.\n"); + return -ENODEV; + } + + /* register v4l2 video video_device */ + ret = video_register_device(dev->vdev, VFL_TYPE_GRABBER, + video_nr[dev->devno]); + if (ret) { + em28xx_errdev("unable to register video device (error=%i).\n", + ret); + return ret; + } + + /* Allocate and fill vbi video_device struct */ + dev->vbi_dev = em28xx_vdev_init(dev, &em28xx_video_template, "vbi"); + + /* register v4l2 vbi video_device */ + ret = video_register_device(dev->vbi_dev, VFL_TYPE_VBI, + vbi_nr[dev->devno]); + if (ret < 0) { + em28xx_errdev("unable to register vbi device\n"); + return ret; + } + + if (em28xx_boards[dev->model].radio.type == EM28XX_RADIO) { + dev->radio_dev = em28xx_vdev_init(dev, &em28xx_radio_template, "radio"); + if (!dev->radio_dev) { + em28xx_errdev("cannot allocate video_device.\n"); + return -ENODEV; + } + ret = video_register_device(dev->radio_dev, VFL_TYPE_RADIO, + radio_nr[dev->devno]); + if (ret < 0) { + em28xx_errdev("can't register radio device\n"); + return ret; + } + em28xx_info("Registered radio device as /dev/radio%d\n", + dev->radio_dev->num); + } + + em28xx_info("V4L2 device registered as /dev/video%d and /dev/vbi%d\n", + dev->vdev->num, dev->vbi_dev->num); + + return 0; +} + + /* * em28xx_init_dev() * allocates and inits the device structs, registers i2c bus and v4l device @@ -1936,6 +1994,7 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, dev->udev = udev; mutex_init(&dev->lock); + mutex_init(&dev->ctrl_urb_lock); spin_lock_init(&dev->slock); init_waitqueue_head(&dev->open); init_waitqueue_head(&dev->wait_frame); @@ -1953,8 +2012,6 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, errCode = em28xx_config(dev); if (errCode) { em28xx_errdev("error configuring device\n"); - em28xx_devused &= ~(1<devno); - kfree(dev); return -ENOMEM; } @@ -2001,50 +2058,6 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, return errCode; } - list_add_tail(&dev->devlist, &em28xx_devlist); - - /* allocate and fill video video_device struct */ - dev->vdev = em28xx_vdev_init(dev, &em28xx_video_template, "video"); - if (NULL == dev->vdev) { - em28xx_errdev("cannot allocate video_device.\n"); - goto fail_unreg; - } - - /* register v4l2 video video_device */ - retval = video_register_device(dev->vdev, VFL_TYPE_GRABBER, - video_nr[dev->devno]); - if (retval) { - em28xx_errdev("unable to register video device (error=%i).\n", - retval); - goto fail_unreg; - } - - /* Allocate and fill vbi video_device struct */ - dev->vbi_dev = em28xx_vdev_init(dev, &em28xx_video_template, "vbi"); - /* register v4l2 vbi video_device */ - if (video_register_device(dev->vbi_dev, VFL_TYPE_VBI, - vbi_nr[dev->devno]) < 0) { - em28xx_errdev("unable to register vbi device\n"); - retval = -ENODEV; - goto fail_unreg; - } - - if (em28xx_boards[dev->model].radio.type == EM28XX_RADIO) { - dev->radio_dev = em28xx_vdev_init(dev, &em28xx_radio_template, "radio"); - if (NULL == dev->radio_dev) { - em28xx_errdev("cannot allocate video_device.\n"); - goto fail_unreg; - } - retval = video_register_device(dev->radio_dev, VFL_TYPE_RADIO, - radio_nr[dev->devno]); - if (retval < 0) { - em28xx_errdev("can't register radio device\n"); - goto fail_unreg; - } - em28xx_info("Registered radio device as /dev/radio%d\n", - dev->radio_dev->num); - } - /* init video dma queues */ INIT_LIST_HEAD(&dev->vidq.active); INIT_LIST_HEAD(&dev->vidq.queued); @@ -2071,8 +2084,14 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, video_mux(dev, 0); - em28xx_info("V4L2 device registered as /dev/video%d and /dev/vbi%d\n", - dev->vdev->num, dev->vbi_dev->num); + mutex_lock(&em28xx_devlist_mutex); + list_add_tail(&dev->devlist, &em28xx_devlist); + retval = register_analog_devices(dev); + if (retval < 0) { + em28xx_release_resources(dev); + mutex_unlock(&em28xx_devlist_mutex); + goto fail_reg_devices; + } mutex_lock(&em28xx_extension_devlist_lock); if (!list_empty(&em28xx_extension_devlist)) { @@ -2082,13 +2101,12 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev, } } mutex_unlock(&em28xx_extension_devlist_lock); + mutex_unlock(&em28xx_devlist_mutex); return 0; -fail_unreg: - em28xx_release_resources(dev); +fail_reg_devices: mutex_unlock(&dev->lock); - kfree(dev); return retval; } @@ -2231,8 +2249,12 @@ static int em28xx_usb_probe(struct usb_interface *interface, /* allocate device struct */ retval = em28xx_init_dev(&dev, udev, nr); - if (retval) + if (retval) { + em28xx_devused &= ~(1<devno); + kfree(dev); + return retval; + } em28xx_info("Found %s\n", em28xx_boards[dev->model].name); diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h index 82781178e0a3..5956e9b3062f 100644 --- a/drivers/media/video/em28xx/em28xx.h +++ b/drivers/media/video/em28xx/em28xx.h @@ -102,6 +102,9 @@ #define EM28XX_MIN_BUF 4 #define EM28XX_DEF_BUF 8 +/*Limits the max URB message size */ +#define URB_MAX_CTRL_SIZE 80 + /* Params for validated field */ #define EM28XX_BOARD_NOT_VALIDATED 1 #define EM28XX_BOARD_VALIDATED 0 @@ -430,6 +433,7 @@ struct em28xx { /* locks */ struct mutex lock; + struct mutex ctrl_urb_lock; /* protects urb_buf */ /* spinlock_t queue_lock; */ struct list_head inqueue, outqueue; wait_queue_head_t open, wait_frame, wait_stream; @@ -451,6 +455,8 @@ struct em28xx { unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */ struct urb *urb[EM28XX_NUM_BUFS]; /* urb for isoc transfers */ char *transfer_buffer[EM28XX_NUM_BUFS]; /* transfer buffers for isoc transfer */ + char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */ + /* helper funcs that call usb_control_msg */ int (*em28xx_write_regs) (struct em28xx *dev, u16 reg, char *buf, int len); diff --git a/drivers/media/video/gspca/Kconfig b/drivers/media/video/gspca/Kconfig index 4d0817471c9f..6b557c057fac 100644 --- a/drivers/media/video/gspca/Kconfig +++ b/drivers/media/video/gspca/Kconfig @@ -3,16 +3,16 @@ menuconfig USB_GSPCA depends on VIDEO_V4L2 default m ---help--- - Say Y here if you want to enable selecting webcams based - on the GSPCA framework. + Say Y here if you want to enable selecting webcams based + on the GSPCA framework. - See for more info. + See for more info. - This driver uses the Video For Linux API. You must say Y or M to - "Video For Linux" to use this driver. + This driver uses the Video For Linux API. You must say Y or M to + "Video For Linux" to use this driver. - To compile this driver as modules, choose M here: the - modules will be called gspca_main. + To compile this driver as modules, choose M here: the + modules will be called gspca_main. if USB_GSPCA && VIDEO_V4L2 @@ -23,190 +23,190 @@ config USB_GSPCA_CONEX tristate "Conexant Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the Conexant chip. + Say Y here if you want support for cameras based on the Conexant chip. - To compile this driver as a module, choose M here: the - module will be called gspca_conex. + To compile this driver as a module, choose M here: the + module will be called gspca_conex. config USB_GSPCA_ETOMS tristate "Etoms USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the Etoms chip. + Say Y here if you want support for cameras based on the Etoms chip. - To compile this driver as a module, choose M here: the - module will be called gspca_etoms. + To compile this driver as a module, choose M here: the + module will be called gspca_etoms. config USB_GSPCA_FINEPIX tristate "Fujifilm FinePix USB V4L2 driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the FinePix chip. + Say Y here if you want support for cameras based on the FinePix chip. - To compile this driver as a module, choose M here: the - module will be called gspca_finepix. + To compile this driver as a module, choose M here: the + module will be called gspca_finepix. config USB_GSPCA_MARS tristate "Mars USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the Mars chip. + Say Y here if you want support for cameras based on the Mars chip. - To compile this driver as a module, choose M here: the - module will be called gspca_mars. + To compile this driver as a module, choose M here: the + module will be called gspca_mars. config USB_GSPCA_OV519 tristate "OV519 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the OV519 chip. + Say Y here if you want support for cameras based on the OV519 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_ov519. + To compile this driver as a module, choose M here: the + module will be called gspca_ov519. config USB_GSPCA_PAC207 tristate "Pixart PAC207 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the PAC207 chip. + Say Y here if you want support for cameras based on the PAC207 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_pac207. + To compile this driver as a module, choose M here: the + module will be called gspca_pac207. config USB_GSPCA_PAC7311 tristate "Pixart PAC7311 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the PAC7311 chip. + Say Y here if you want support for cameras based on the PAC7311 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_pac7311. + To compile this driver as a module, choose M here: the + module will be called gspca_pac7311. config USB_GSPCA_SONIXB tristate "SN9C102 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SONIXB chip. + Say Y here if you want support for cameras based on the SONIXB chip. - To compile this driver as a module, choose M here: the - module will be called gspca_sonixb. + To compile this driver as a module, choose M here: the + module will be called gspca_sonixb. config USB_GSPCA_SONIXJ tristate "SONIX JPEG USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SONIXJ chip. + Say Y here if you want support for cameras based on the SONIXJ chip. - To compile this driver as a module, choose M here: the - module will be called gspca_sonixj + To compile this driver as a module, choose M here: the + module will be called gspca_sonixj config USB_GSPCA_SPCA500 tristate "SPCA500 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SPCA500 chip. + Say Y here if you want support for cameras based on the SPCA500 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_spca500. + To compile this driver as a module, choose M here: the + module will be called gspca_spca500. config USB_GSPCA_SPCA501 tristate "SPCA501 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SPCA501 chip. + Say Y here if you want support for cameras based on the SPCA501 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_spca501. + To compile this driver as a module, choose M here: the + module will be called gspca_spca501. config USB_GSPCA_SPCA505 tristate "SPCA505 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SPCA505 chip. + Say Y here if you want support for cameras based on the SPCA505 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_spca505. + To compile this driver as a module, choose M here: the + module will be called gspca_spca505. config USB_GSPCA_SPCA506 tristate "SPCA506 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SPCA506 chip. + Say Y here if you want support for cameras based on the SPCA506 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_spca506. + To compile this driver as a module, choose M here: the + module will be called gspca_spca506. config USB_GSPCA_SPCA508 tristate "SPCA508 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SPCA508 chip. + Say Y here if you want support for cameras based on the SPCA508 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_spca508. + To compile this driver as a module, choose M here: the + module will be called gspca_spca508. config USB_GSPCA_SPCA561 tristate "SPCA561 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the SPCA561 chip. + Say Y here if you want support for cameras based on the SPCA561 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_spca561. + To compile this driver as a module, choose M here: the + module will be called gspca_spca561. config USB_GSPCA_STK014 tristate "Syntek DV4000 (STK014) USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the STK014 chip. + Say Y here if you want support for cameras based on the STK014 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_stk014. + To compile this driver as a module, choose M here: the + module will be called gspca_stk014. config USB_GSPCA_SUNPLUS tristate "SUNPLUS USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the Sunplus - SPCA504(abc) SPCA533 SPCA536 chips. + Say Y here if you want support for cameras based on the Sunplus + SPCA504(abc) SPCA533 SPCA536 chips. - To compile this driver as a module, choose M here: the - module will be called gspca_spca5xx. + To compile this driver as a module, choose M here: the + module will be called gspca_spca5xx. config USB_GSPCA_T613 tristate "T613 (JPEG Compliance) USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the T613 chip. + Say Y here if you want support for cameras based on the T613 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_t613. + To compile this driver as a module, choose M here: the + module will be called gspca_t613. config USB_GSPCA_TV8532 tristate "TV8532 USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the TV8531 chip. + Say Y here if you want support for cameras based on the TV8531 chip. - To compile this driver as a module, choose M here: the - module will be called gspca_tv8532. + To compile this driver as a module, choose M here: the + module will be called gspca_tv8532. config USB_GSPCA_VC032X tristate "VC032X USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the VC032X chip. + Say Y here if you want support for cameras based on the VC032X chip. - To compile this driver as a module, choose M here: the - module will be called gspca_vc032x. + To compile this driver as a module, choose M here: the + module will be called gspca_vc032x. config USB_GSPCA_ZC3XX - tristate "VC3xx USB Camera Driver" + tristate "ZC3XX USB Camera Driver" depends on VIDEO_V4L2 && USB_GSPCA help - Say Y here if you want support for cameras based on the ZC3XX chip. + Say Y here if you want support for cameras based on the ZC3XX chip. - To compile this driver as a module, choose M here: the - module will be called gspca_zc3xx. + To compile this driver as a module, choose M here: the + module will be called gspca_zc3xx. endif diff --git a/drivers/media/video/gspca/conex.c b/drivers/media/video/gspca/conex.c index a9d51ba7c57c..de28354ea5ba 100644 --- a/drivers/media/video/gspca/conex.c +++ b/drivers/media/video/gspca/conex.c @@ -846,10 +846,13 @@ static int sd_start(struct gspca_dev *gspca_dev) return 0; } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { int retry = 50; + if (!gspca_dev->present) + return; reg_w_val(gspca_dev, 0x0000, 0x00); reg_r(gspca_dev, 0x0002, 1); reg_w_val(gspca_dev, 0x0053, 0x00); diff --git a/drivers/media/video/gspca/finepix.c b/drivers/media/video/gspca/finepix.c index 65d3cbfe6b27..607942fd7970 100644 --- a/drivers/media/video/gspca/finepix.c +++ b/drivers/media/video/gspca/finepix.c @@ -276,6 +276,12 @@ static void sd_stopN(struct gspca_dev *gspca_dev) /* Stop the state machine */ if (dev->state != FPIX_NOP) wait_for_completion(&dev->can_close); +} + +/* called on streamoff with alt 0 and disconnect */ +static void sd_stop0(struct gspca_dev *gspca_dev) +{ + struct usb_fpix *dev = (struct usb_fpix *) gspca_dev; usb_free_urb(dev->control_urb); dev->control_urb = NULL; @@ -385,6 +391,7 @@ static int sd_start(struct gspca_dev *gspca_dev) error: /* Free the ressources */ sd_stopN(gspca_dev); + sd_stop0(gspca_dev); return ret; } @@ -425,6 +432,7 @@ static const struct sd_desc sd_desc = { .init = sd_init, .start = sd_start, .stopN = sd_stopN, + .stop0 = sd_stop0, }; /* -- device connect -- */ diff --git a/drivers/media/video/gspca/gspca.c b/drivers/media/video/gspca/gspca.c index e48fbfc8ad05..748a87e82e44 100644 --- a/drivers/media/video/gspca/gspca.c +++ b/drivers/media/video/gspca/gspca.c @@ -646,15 +646,14 @@ static void gspca_stream_off(struct gspca_dev *gspca_dev) { gspca_dev->streaming = 0; atomic_set(&gspca_dev->nevent, 0); - if (gspca_dev->present) { - if (gspca_dev->sd_desc->stopN) - gspca_dev->sd_desc->stopN(gspca_dev); - destroy_urbs(gspca_dev); - gspca_set_alt0(gspca_dev); - if (gspca_dev->sd_desc->stop0) - gspca_dev->sd_desc->stop0(gspca_dev); - PDEBUG(D_STREAM, "stream off OK"); - } + if (gspca_dev->present + && gspca_dev->sd_desc->stopN) + gspca_dev->sd_desc->stopN(gspca_dev); + destroy_urbs(gspca_dev); + gspca_set_alt0(gspca_dev); + if (gspca_dev->sd_desc->stop0) + gspca_dev->sd_desc->stop0(gspca_dev); + PDEBUG(D_STREAM, "stream off OK"); } static void gspca_set_default_mode(struct gspca_dev *gspca_dev) @@ -863,7 +862,7 @@ static int dev_open(struct inode *inode, struct file *file) int ret; PDEBUG(D_STREAM, "%s open", current->comm); - gspca_dev = (struct gspca_dev *) video_devdata(file); + gspca_dev = video_drvdata(file); if (mutex_lock_interruptible(&gspca_dev->queue_lock)) return -ERESTARTSYS; if (!gspca_dev->present) { @@ -875,6 +874,13 @@ static int dev_open(struct inode *inode, struct file *file) ret = -EBUSY; goto out; } + + /* protect the subdriver against rmmod */ + if (!try_module_get(gspca_dev->module)) { + ret = -ENODEV; + goto out; + } + gspca_dev->users++; /* one more user */ @@ -884,10 +890,10 @@ static int dev_open(struct inode *inode, struct file *file) #ifdef GSPCA_DEBUG /* activate the v4l2 debug */ if (gspca_debug & D_V4L2) - gspca_dev->vdev.debug |= V4L2_DEBUG_IOCTL + gspca_dev->vdev->debug |= V4L2_DEBUG_IOCTL | V4L2_DEBUG_IOCTL_ARG; else - gspca_dev->vdev.debug &= ~(V4L2_DEBUG_IOCTL + gspca_dev->vdev->debug &= ~(V4L2_DEBUG_IOCTL | V4L2_DEBUG_IOCTL_ARG); #endif ret = 0; @@ -921,6 +927,7 @@ static int dev_close(struct inode *inode, struct file *file) gspca_dev->memory = GSPCA_MEMORY_NO; } file->private_data = NULL; + module_put(gspca_dev->module); mutex_unlock(&gspca_dev->queue_lock); PDEBUG(D_STREAM, "close done"); @@ -1748,11 +1755,6 @@ out: return ret; } -static void dev_release(struct video_device *vfd) -{ - /* nothing */ -} - static struct file_operations dev_fops = { .owner = THIS_MODULE, .open = dev_open, @@ -1800,7 +1802,7 @@ static struct video_device gspca_template = { .name = "gspca main driver", .fops = &dev_fops, .ioctl_ops = &dev_ioctl_ops, - .release = dev_release, /* mandatory */ + .release = video_device_release, .minor = -1, }; @@ -1869,17 +1871,18 @@ int gspca_dev_probe(struct usb_interface *intf, init_waitqueue_head(&gspca_dev->wq); /* init video stuff */ - memcpy(&gspca_dev->vdev, &gspca_template, sizeof gspca_template); - gspca_dev->vdev.parent = &dev->dev; - memcpy(&gspca_dev->fops, &dev_fops, sizeof gspca_dev->fops); - gspca_dev->vdev.fops = &gspca_dev->fops; - gspca_dev->fops.owner = module; /* module protection */ + gspca_dev->vdev = video_device_alloc(); + memcpy(gspca_dev->vdev, &gspca_template, sizeof gspca_template); + gspca_dev->vdev->parent = &dev->dev; + gspca_dev->module = module; gspca_dev->present = 1; - ret = video_register_device(&gspca_dev->vdev, + video_set_drvdata(gspca_dev->vdev, gspca_dev); + ret = video_register_device(gspca_dev->vdev, VFL_TYPE_GRABBER, video_nr); if (ret < 0) { err("video_register_device err %d", ret); + video_device_release(gspca_dev->vdev); goto out; } @@ -1887,7 +1890,8 @@ int gspca_dev_probe(struct usb_interface *intf, PDEBUG(D_PROBE, "probe ok"); return 0; out: - kref_put(&gspca_dev->kref, gspca_delete); + kfree(gspca_dev->usb_buf); + kfree(gspca_dev); return ret; } EXPORT_SYMBOL(gspca_dev_probe); @@ -1905,7 +1909,7 @@ void gspca_disconnect(struct usb_interface *intf) usb_set_intfdata(intf, NULL); /* We don't want people trying to open up the device */ - video_unregister_device(&gspca_dev->vdev); + video_unregister_device(gspca_dev->vdev); gspca_dev->present = 0; gspca_dev->streaming = 0; diff --git a/drivers/media/video/gspca/gspca.h b/drivers/media/video/gspca/gspca.h index 1d9dc90b4791..d25e8d69373b 100644 --- a/drivers/media/video/gspca/gspca.h +++ b/drivers/media/video/gspca/gspca.h @@ -97,7 +97,7 @@ struct sd_desc { cam_pkt_op pkt_scan; /* optional operations */ cam_v_op stopN; /* called on stream off - main alt */ - cam_v_op stop0; /* called on stream off - alt 0 */ + cam_v_op stop0; /* called on stream off & disconnect - alt 0 */ cam_v_op dq_callback; /* called when a frame has been dequeued */ cam_jpg_op get_jcomp; cam_jpg_op set_jcomp; @@ -120,8 +120,8 @@ struct gspca_frame { }; struct gspca_dev { - struct video_device vdev; /* !! must be the first item */ - struct file_operations fops; + struct video_device *vdev; + struct module *module; /* subdriver handling the device */ struct usb_device *dev; struct kref kref; struct file *capt_file; /* file doing video capture */ diff --git a/drivers/media/video/gspca/pac7311.c b/drivers/media/video/gspca/pac7311.c index e5ff9a6199ef..fbd45e235d97 100644 --- a/drivers/media/video/gspca/pac7311.c +++ b/drivers/media/video/gspca/pac7311.c @@ -749,10 +749,13 @@ static void sd_stopN(struct gspca_dev *gspca_dev) reg_w(gspca_dev, 0x78, 0x44); /* Bit_0=start stream, Bit_6=LED */ } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; + if (!gspca_dev->present) + return; if (sd->sensor == SENSOR_PAC7302) { reg_w(gspca_dev, 0xff, 0x01); reg_w(gspca_dev, 0x78, 0x40); diff --git a/drivers/media/video/gspca/spca501.c b/drivers/media/video/gspca/spca501.c index b742f260c7ca..e29954c1c38c 100644 --- a/drivers/media/video/gspca/spca501.c +++ b/drivers/media/video/gspca/spca501.c @@ -2022,8 +2022,11 @@ static void sd_stopN(struct gspca_dev *gspca_dev) reg_write(gspca_dev->dev, SPCA501_REG_CTLRL, 0x01, 0x00); } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { + if (!gspca_dev->present) + return; reg_write(gspca_dev->dev, SPCA501_REG_CTLRL, 0x05, 0x00); } diff --git a/drivers/media/video/gspca/spca505.c b/drivers/media/video/gspca/spca505.c index b345749213cf..895b9fe4018c 100644 --- a/drivers/media/video/gspca/spca505.c +++ b/drivers/media/video/gspca/spca505.c @@ -742,8 +742,12 @@ static void sd_stopN(struct gspca_dev *gspca_dev) reg_write(gspca_dev->dev, 0x02, 0x00, 0x00); } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { + if (!gspca_dev->present) + return; + /* This maybe reset or power control */ reg_write(gspca_dev->dev, 0x03, 0x03, 0x20); reg_write(gspca_dev->dev, 0x03, 0x01, 0x0); diff --git a/drivers/media/video/gspca/spca561.c b/drivers/media/video/gspca/spca561.c index 020a03c466c1..c3de4e44123d 100644 --- a/drivers/media/video/gspca/spca561.c +++ b/drivers/media/video/gspca/spca561.c @@ -766,10 +766,13 @@ static void sd_stopN(struct gspca_dev *gspca_dev) } } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; + if (!gspca_dev->present) + return; if (sd->chip_revision == Rev012A) { reg_w_val(gspca_dev->dev, 0x8118, 0x29); reg_w_val(gspca_dev->dev, 0x8114, 0x08); diff --git a/drivers/media/video/gspca/vc032x.c b/drivers/media/video/gspca/vc032x.c index be46d9232540..17af353ddd1c 100644 --- a/drivers/media/video/gspca/vc032x.c +++ b/drivers/media/video/gspca/vc032x.c @@ -1633,10 +1633,13 @@ static void sd_stopN(struct gspca_dev *gspca_dev) reg_w(dev, 0xa0, 0x09, 0xb003); } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { struct usb_device *dev = gspca_dev->dev; + if (!gspca_dev->present) + return; reg_w(dev, 0x89, 0xffff, 0xffff); } diff --git a/drivers/media/video/gspca/zc3xx.c b/drivers/media/video/gspca/zc3xx.c index d0a4451dc46f..0befacf49855 100644 --- a/drivers/media/video/gspca/zc3xx.c +++ b/drivers/media/video/gspca/zc3xx.c @@ -2266,7 +2266,7 @@ static const struct usb_action hdcs2020b_NoFliker[] = { {} }; -static const struct usb_action hv7131bxx_Initial[] = { +static const struct usb_action hv7131bxx_Initial[] = { /* 320x240 */ {0xa0, 0x01, ZC3XX_R000_SYSTEMCONTROL}, {0xa0, 0x10, ZC3XX_R002_CLOCKSELECT}, {0xa0, 0x00, ZC3XX_R010_CMOSSENSORSELECT}, @@ -2290,7 +2290,7 @@ static const struct usb_action hv7131bxx_Initial[] = { {0xaa, 0x14, 0x0001}, {0xaa, 0x15, 0x00e8}, {0xaa, 0x16, 0x0002}, - {0xaa, 0x17, 0x0086}, + {0xaa, 0x17, 0x0086}, /* 00,17,88,aa */ {0xaa, 0x31, 0x0038}, {0xaa, 0x32, 0x0038}, {0xaa, 0x33, 0x0038}, @@ -2309,7 +2309,7 @@ static const struct usb_action hv7131bxx_Initial[] = { {0xa0, 0x13, ZC3XX_R1CB_SHARPNESS05}, {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE}, {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS}, - {0xaa, 0x02, 0x0080}, /* {0xaa, 0x02, 0x0090}; */ + {0xaa, 0x02, 0x0090}, /* 00,02,80,aa */ {0xa1, 0x01, 0x0002}, {0xa0, 0x00, ZC3XX_R092_I2CADDRESSSELECT}, {0xa0, 0x02, ZC3XX_R090_I2CCOMMAND}, @@ -2374,7 +2374,7 @@ static const struct usb_action hv7131bxx_Initial[] = { {} }; -static const struct usb_action hv7131bxx_InitialScale[] = { +static const struct usb_action hv7131bxx_InitialScale[] = { /* 640x480*/ {0xa0, 0x01, ZC3XX_R000_SYSTEMCONTROL}, {0xa0, 0x00, ZC3XX_R002_CLOCKSELECT}, {0xa0, 0x00, ZC3XX_R010_CMOSSENSORSELECT}, @@ -6388,6 +6388,8 @@ static void setbrightness(struct gspca_dev *gspca_dev) /*fixme: is it really write to 011d and 018d for all other sensors? */ brightness = sd->brightness; reg_w(gspca_dev->dev, brightness, 0x011d); + if (sd->sensor == SENSOR_HV7131B) + return; if (brightness < 0x70) brightness += 0x10; else @@ -6529,6 +6531,7 @@ static void setquality(struct gspca_dev *gspca_dev) switch (sd->sensor) { case SENSOR_GC0305: + case SENSOR_HV7131B: case SENSOR_OV7620: case SENSOR_PO2030: return; @@ -7209,7 +7212,6 @@ static int sd_start(struct gspca_dev *gspca_dev) mode = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv; zc3_init = init_tb[(int) sd->sensor][mode]; switch (sd->sensor) { - case SENSOR_HV7131B: case SENSOR_HV7131C: zcxx_probeSensor(gspca_dev); break; @@ -7334,10 +7336,13 @@ static int sd_start(struct gspca_dev *gspca_dev) return 0; } +/* called on streamoff with alt 0 and on disconnect */ static void sd_stop0(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; + if (!gspca_dev->present) + return; send_unknown(gspca_dev->dev, sd->sensor); } diff --git a/drivers/media/video/ivtv/Kconfig b/drivers/media/video/ivtv/Kconfig index 0069898bddab..c46bfb1569e3 100644 --- a/drivers/media/video/ivtv/Kconfig +++ b/drivers/media/video/ivtv/Kconfig @@ -1,6 +1,6 @@ config VIDEO_IVTV tristate "Conexant cx23416/cx23415 MPEG encoder/decoder support" - depends on VIDEO_V4L1 && VIDEO_V4L2 && PCI && I2C && EXPERIMENTAL + depends on VIDEO_V4L2 && PCI && I2C depends on INPUT # due to VIDEO_IR select I2C_ALGOBIT select VIDEO_IR @@ -12,7 +12,6 @@ config VIDEO_IVTV select VIDEO_SAA711X select VIDEO_SAA717X select VIDEO_SAA7127 - select VIDEO_TVAUDIO select VIDEO_CS53L32A select VIDEO_M52790 select VIDEO_WM8775 @@ -32,7 +31,7 @@ config VIDEO_IVTV config VIDEO_FB_IVTV tristate "Conexant cx23415 framebuffer support" - depends on VIDEO_IVTV && FB && EXPERIMENTAL + depends on VIDEO_IVTV && FB select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c index d36485023b68..b69cc1d55e5b 100644 --- a/drivers/media/video/ivtv/ivtv-driver.c +++ b/drivers/media/video/ivtv/ivtv-driver.c @@ -875,43 +875,43 @@ static void ivtv_load_and_init_modules(struct ivtv *itv) #ifdef MODULE /* load modules */ -#ifndef CONFIG_MEDIA_TUNER +#ifdef CONFIG_MEDIA_TUNER_MODULE hw = ivtv_request_module(itv, hw, "tuner", IVTV_HW_TUNER); #endif -#ifndef CONFIG_VIDEO_CX25840 +#ifdef CONFIG_VIDEO_CX25840_MODULE hw = ivtv_request_module(itv, hw, "cx25840", IVTV_HW_CX25840); #endif -#ifndef CONFIG_VIDEO_SAA711X +#ifdef CONFIG_VIDEO_SAA711X_MODULE hw = ivtv_request_module(itv, hw, "saa7115", IVTV_HW_SAA711X); #endif -#ifndef CONFIG_VIDEO_SAA7127 +#ifdef CONFIG_VIDEO_SAA7127_MODULE hw = ivtv_request_module(itv, hw, "saa7127", IVTV_HW_SAA7127); #endif -#ifndef CONFIG_VIDEO_SAA717X +#ifdef CONFIG_VIDEO_SAA717X_MODULE hw = ivtv_request_module(itv, hw, "saa717x", IVTV_HW_SAA717X); #endif -#ifndef CONFIG_VIDEO_UPD64031A +#ifdef CONFIG_VIDEO_UPD64031A_MODULE hw = ivtv_request_module(itv, hw, "upd64031a", IVTV_HW_UPD64031A); #endif -#ifndef CONFIG_VIDEO_UPD64083 +#ifdef CONFIG_VIDEO_UPD64083_MODULE hw = ivtv_request_module(itv, hw, "upd64083", IVTV_HW_UPD6408X); #endif -#ifndef CONFIG_VIDEO_MSP3400 +#ifdef CONFIG_VIDEO_MSP3400_MODULE hw = ivtv_request_module(itv, hw, "msp3400", IVTV_HW_MSP34XX); #endif -#ifndef CONFIG_VIDEO_VP27SMPX +#ifdef CONFIG_VIDEO_VP27SMPX_MODULE hw = ivtv_request_module(itv, hw, "vp27smpx", IVTV_HW_VP27SMPX); #endif -#ifndef CONFIG_VIDEO_WM8775 +#ifdef CONFIG_VIDEO_WM8775_MODULE hw = ivtv_request_module(itv, hw, "wm8775", IVTV_HW_WM8775); #endif -#ifndef CONFIG_VIDEO_WM8739 +#ifdef CONFIG_VIDEO_WM8739_MODULE hw = ivtv_request_module(itv, hw, "wm8739", IVTV_HW_WM8739); #endif -#ifndef CONFIG_VIDEO_CS53L32A +#ifdef CONFIG_VIDEO_CS53L32A_MODULE hw = ivtv_request_module(itv, hw, "cs53l32a", IVTV_HW_CS53L32A); #endif -#ifndef CONFIG_VIDEO_M52790 +#ifdef CONFIG_VIDEO_M52790_MODULE hw = ivtv_request_module(itv, hw, "m52790", IVTV_HW_M52790); #endif #endif diff --git a/drivers/media/video/s2255drv.c b/drivers/media/video/s2255drv.c index 5272926db73e..3c3f8cf73108 100644 --- a/drivers/media/video/s2255drv.c +++ b/drivers/media/video/s2255drv.c @@ -192,7 +192,7 @@ struct s2255_dmaqueue { #define S2255_FW_FAILED 3 #define S2255_FW_DISCONNECTING 4 -#define S2255_FW_MARKER 0x22552f2f +#define S2255_FW_MARKER cpu_to_le32(0x22552f2f) /* 2255 read states */ #define S2255_READ_IDLE 0 #define S2255_READ_FRAME 1 diff --git a/drivers/media/video/saa7110.c b/drivers/media/video/saa7110.c index adf2ba79496a..37860698f782 100644 --- a/drivers/media/video/saa7110.c +++ b/drivers/media/video/saa7110.c @@ -47,7 +47,7 @@ module_param(debug, int, 0); MODULE_PARM_DESC(debug, "Debug level (0-1)"); #define SAA7110_MAX_INPUT 9 /* 6 CVBS, 3 SVHS */ -#define SAA7110_MAX_OUTPUT 0 /* its a decoder only */ +#define SAA7110_MAX_OUTPUT 1 /* 1 YUV */ #define SAA7110_NR_REG 0x35 @@ -327,7 +327,7 @@ saa7110_command (struct i2c_client *client, case DECODER_SET_INPUT: v = *(int *) arg; - if (v < 0 || v > SAA7110_MAX_INPUT) { + if (v < 0 || v >= SAA7110_MAX_INPUT) { v4l_dbg(1, debug, client, "input=%d not available\n", v); return -EINVAL; } diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c index 249184452949..dfbe08a9ad9b 100644 --- a/drivers/media/video/saa7134/saa7134-core.c +++ b/drivers/media/video/saa7134/saa7134-core.c @@ -941,7 +941,8 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, dev->name,(unsigned long long)pci_resource_start(pci_dev,0)); goto fail1; } - dev->lmmio = ioremap(pci_resource_start(pci_dev,0), 0x1000); + dev->lmmio = ioremap(pci_resource_start(pci_dev, 0), + pci_resource_len(pci_dev, 0)); dev->bmmio = (__u8 __iomem *)dev->lmmio; if (NULL == dev->lmmio) { err = -EIO; diff --git a/drivers/media/video/tvaudio.c b/drivers/media/video/tvaudio.c index b59e47272abf..3720f0e03a16 100644 --- a/drivers/media/video/tvaudio.c +++ b/drivers/media/video/tvaudio.c @@ -1,5 +1,5 @@ /* - * experimental driver for simple i2c audio chips. + * Driver for simple i2c audio chips. * * Copyright (c) 2000 Gerd Knorr * based on code by: @@ -7,6 +7,10 @@ * Steve VanDeBogart (vandebo@uclink.berkeley.edu) * Greg Alexander (galexand@acm.org) * + * Copyright(c) 2005-2008 Mauro Carvalho Chehab + * - Some cleanups, code fixes, etc + * - Convert it to V4L2 API + * * This code is placed under the terms of the GNU General Public License * * OPTIONS: @@ -30,6 +34,7 @@ #include #include +#include #include #include @@ -58,7 +63,6 @@ typedef int (*checkit)(struct CHIPSTATE*); typedef int (*initialize)(struct CHIPSTATE*); typedef int (*getmode)(struct CHIPSTATE*); typedef void (*setmode)(struct CHIPSTATE*, int mode); -typedef void (*checkmode)(struct CHIPSTATE*); /* i2c command */ typedef struct AUDIOCMD { @@ -79,6 +83,7 @@ struct CHIPDESC { #define CHIP_HAS_VOLUME 1 #define CHIP_HAS_BASSTREBLE 2 #define CHIP_HAS_INPUTSEL 4 +#define CHIP_NEED_CHECKMODE 8 /* various i2c command sequences */ audiocmd init; @@ -96,23 +101,20 @@ struct CHIPDESC { getmode getmode; setmode setmode; - /* check / autoswitch audio after channel switches */ - checkmode checkmode; - /* input switch register + values for v4l inputs */ int inputreg; int inputmap[4]; int inputmute; int inputmask; }; -static struct CHIPDESC chiplist[]; /* current state of the chip */ struct CHIPSTATE { struct i2c_client *c; - /* index into CHIPDESC array */ - int type; + /* chip-specific description - should point to + an entry at CHIPDESC table */ + struct CHIPDESC *desc; /* shadow register set */ audiocmd shadow; @@ -152,7 +154,7 @@ static int chip_write(struct CHIPSTATE *chip, int subaddr, int val) { unsigned char buffer[2]; - if (-1 == subaddr) { + if (subaddr < 0) { v4l_dbg(1, debug, chip->c, "%s: chip_write: 0x%x\n", chip->c->name, val); chip->shadow.bytes[1] = val; @@ -163,6 +165,13 @@ static int chip_write(struct CHIPSTATE *chip, int subaddr, int val) return -1; } } else { + if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) { + v4l_info(chip->c, + "Tried to access a non-existent register: %d\n", + subaddr); + return -EINVAL; + } + v4l_dbg(1, debug, chip->c, "%s: chip_write: reg%d=0x%x\n", chip->c->name, subaddr, val); chip->shadow.bytes[subaddr+1] = val; @@ -177,12 +186,20 @@ static int chip_write(struct CHIPSTATE *chip, int subaddr, int val) return 0; } -static int chip_write_masked(struct CHIPSTATE *chip, int subaddr, int val, int mask) +static int chip_write_masked(struct CHIPSTATE *chip, + int subaddr, int val, int mask) { if (mask != 0) { - if (-1 == subaddr) { + if (subaddr < 0) { val = (chip->shadow.bytes[1] & ~mask) | (val & mask); } else { + if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) { + v4l_info(chip->c, + "Tried to access a non-existent register: %d\n", + subaddr); + return -EINVAL; + } + val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask); } } @@ -228,6 +245,15 @@ static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd) if (0 == cmd->count) return 0; + if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) { + v4l_info(chip->c, + "Tried to access a non-existent register range: %d to %d\n", + cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1); + return -EINVAL; + } + + /* FIXME: it seems that the shadow bytes are wrong bellow !*/ + /* update our shadow register set; print bytes if (debug > 0) */ v4l_dbg(1, debug, chip->c, "%s: chip_cmd(%s): reg=%d, data:", chip->c->name, name,cmd->bytes[0]); @@ -263,7 +289,8 @@ static void chip_thread_wake(unsigned long data) static int chip_thread(void *data) { struct CHIPSTATE *chip = data; - struct CHIPDESC *desc = chiplist + chip->type; + struct CHIPDESC *desc = chip->desc; + int mode; v4l_dbg(1, debug, chip->c, "%s: thread started\n", chip->c->name); set_freezable(); @@ -282,7 +309,26 @@ static int chip_thread(void *data) continue; /* have a look what's going on */ - desc->checkmode(chip); + mode = desc->getmode(chip); + if (mode == chip->prevmode) + continue; + + /* chip detected a new audio mode - set it */ + v4l_dbg(1, debug, chip->c, "%s: thread checkmode\n", + chip->c->name); + + chip->prevmode = mode; + + if (mode & V4L2_TUNER_MODE_STEREO) + desc->setmode(chip, V4L2_TUNER_MODE_STEREO); + if (mode & V4L2_TUNER_MODE_LANG1_LANG2) + desc->setmode(chip, V4L2_TUNER_MODE_STEREO); + else if (mode & V4L2_TUNER_MODE_LANG1) + desc->setmode(chip, V4L2_TUNER_MODE_LANG1); + else if (mode & V4L2_TUNER_MODE_LANG2) + desc->setmode(chip, V4L2_TUNER_MODE_LANG2); + else + desc->setmode(chip, V4L2_TUNER_MODE_MONO); /* schedule next check */ mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000)); @@ -292,29 +338,6 @@ static int chip_thread(void *data) return 0; } -static void generic_checkmode(struct CHIPSTATE *chip) -{ - struct CHIPDESC *desc = chiplist + chip->type; - int mode = desc->getmode(chip); - - if (mode == chip->prevmode) - return; - - v4l_dbg(1, debug, chip->c, "%s: thread checkmode\n", chip->c->name); - chip->prevmode = mode; - - if (mode & V4L2_TUNER_MODE_STEREO) - desc->setmode(chip,V4L2_TUNER_MODE_STEREO); - if (mode & V4L2_TUNER_MODE_LANG1_LANG2) - desc->setmode(chip,V4L2_TUNER_MODE_STEREO); - else if (mode & V4L2_TUNER_MODE_LANG1) - desc->setmode(chip,V4L2_TUNER_MODE_LANG1); - else if (mode & V4L2_TUNER_MODE_LANG2) - desc->setmode(chip,V4L2_TUNER_MODE_LANG2); - else - desc->setmode(chip,V4L2_TUNER_MODE_MONO); -} - /* ---------------------------------------------------------------------- */ /* audio chip descriptions - defines+functions for tda9840 */ @@ -777,7 +800,7 @@ static struct tda9874a_MODES { char *name; audiocmd cmd; } tda9874a_modelist[9] = { - { "A2, B/G", + { "A2, B/G", /* default */ { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} }, { "A2, M (Korea)", { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} }, @@ -791,7 +814,7 @@ static struct tda9874a_MODES { { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} }, { "NICAM, B/G", { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} }, - { "NICAM, D/K", /* default */ + { "NICAM, D/K", { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} }, { "NICAM, L", { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} } @@ -981,7 +1004,7 @@ static int tda9874a_initialize(struct CHIPSTATE *chip) { if (tda9874a_SIF > 2) tda9874a_SIF = 1; - if (tda9874a_STD > 8) + if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist)) tda9874a_STD = 0; if(tda9874a_AMSEL > 1) tda9874a_AMSEL = 0; @@ -1089,7 +1112,7 @@ static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; } static int tda8425_initialize(struct CHIPSTATE *chip) { - struct CHIPDESC *desc = chiplist + chip->type; + struct CHIPDESC *desc = chip->desc; int inputmap[4] = { /* tuner */ TDA8425_S1_CH2, /* radio */ TDA8425_S1_CH1, /* extern */ TDA8425_S1_CH1, /* intern */ TDA8425_S1_OFF}; @@ -1259,27 +1282,28 @@ static struct CHIPDESC chiplist[] = { .addr_lo = I2C_ADDR_TDA9840 >> 1, .addr_hi = I2C_ADDR_TDA9840 >> 1, .registers = 5, + .flags = CHIP_NEED_CHECKMODE, + /* callbacks */ .checkit = tda9840_checkit, .getmode = tda9840_getmode, .setmode = tda9840_setmode, - .checkmode = generic_checkmode, .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN /* ,TDA9840_SW, TDA9840_MONO */} } }, { .name = "tda9873h", - .checkit = tda9873_checkit, .insmodopt = &tda9873, .addr_lo = I2C_ADDR_TDA985x_L >> 1, .addr_hi = I2C_ADDR_TDA985x_H >> 1, .registers = 3, - .flags = CHIP_HAS_INPUTSEL, + .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE, + /* callbacks */ + .checkit = tda9873_checkit, .getmode = tda9873_getmode, .setmode = tda9873_setmode, - .checkmode = generic_checkmode, .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } }, .inputreg = TDA9873_SW, @@ -1290,15 +1314,16 @@ static struct CHIPDESC chiplist[] = { }, { .name = "tda9874h/a", - .checkit = tda9874a_checkit, - .initialize = tda9874a_initialize, .insmodopt = &tda9874a, .addr_lo = I2C_ADDR_TDA9874 >> 1, .addr_hi = I2C_ADDR_TDA9874 >> 1, + .flags = CHIP_NEED_CHECKMODE, + /* callbacks */ + .initialize = tda9874a_initialize, + .checkit = tda9874a_checkit, .getmode = tda9874a_getmode, .setmode = tda9874a_setmode, - .checkmode = generic_checkmode, }, { .name = "tda9850", @@ -1324,10 +1349,11 @@ static struct CHIPDESC chiplist[] = { .rightreg = TDA9855_VR, .bassreg = TDA9855_BA, .treblereg = TDA9855_TR, + + /* callbacks */ .volfunc = tda9855_volume, .bassfunc = tda9855_bass, .treblefunc = tda9855_treble, - .getmode = tda985x_getmode, .setmode = tda985x_setmode, @@ -1348,6 +1374,8 @@ static struct CHIPDESC chiplist[] = { .rightreg = TEA6300_VL, .bassreg = TEA6300_BA, .treblereg = TEA6300_TR, + + /* callbacks */ .volfunc = tea6300_shift10, .bassfunc = tea6300_shift12, .treblefunc = tea6300_shift12, @@ -1358,7 +1386,6 @@ static struct CHIPDESC chiplist[] = { }, { .name = "tea6320", - .initialize = tea6320_initialize, .insmodopt = &tea6320, .addr_lo = I2C_ADDR_TEA6300 >> 1, .addr_hi = I2C_ADDR_TEA6300 >> 1, @@ -1369,6 +1396,9 @@ static struct CHIPDESC chiplist[] = { .rightreg = TEA6320_V, .bassreg = TEA6320_BA, .treblereg = TEA6320_TR, + + /* callbacks */ + .initialize = tea6320_initialize, .volfunc = tea6320_volume, .bassfunc = tea6320_shift11, .treblefunc = tea6320_shift11, @@ -1401,16 +1431,18 @@ static struct CHIPDESC chiplist[] = { .rightreg = TDA8425_VR, .bassreg = TDA8425_BA, .treblereg = TDA8425_TR, + + /* callbacks */ + .initialize = tda8425_initialize, .volfunc = tda8425_shift10, .bassfunc = tda8425_shift12, .treblefunc = tda8425_shift12, + .setmode = tda8425_setmode, .inputreg = TDA8425_S1, .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 }, .inputmute = TDA8425_S1_OFF, - .setmode = tda8425_setmode, - .initialize = tda8425_initialize, }, { .name = "pic16c54 (PV951)", @@ -1434,10 +1466,11 @@ static struct CHIPDESC chiplist[] = { .addr_lo = I2C_ADDR_TDA9840 >> 1, .addr_hi = I2C_ADDR_TDA9840 >> 1, .registers = 2, + .flags = CHIP_NEED_CHECKMODE, + /* callbacks */ .getmode = ta8874z_getmode, .setmode = ta8874z_setmode, - .checkmode = generic_checkmode, .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}}, }, @@ -1481,6 +1514,7 @@ static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) } if (desc->name == NULL) { v4l_dbg(1, debug, client, "no matching chip description found\n"); + kfree(chip); return -EIO; } v4l_info(client, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name); @@ -1494,7 +1528,7 @@ static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) /* fill required data structures */ if (!id) strlcpy(client->name, desc->name, I2C_NAME_SIZE); - chip->type = desc-chiplist; + chip->desc = desc; chip->shadow.count = desc->registers+1; chip->prevmode = -1; chip->audmode = V4L2_TUNER_MODE_LANG1; @@ -1506,20 +1540,49 @@ static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) chip_cmd(chip,"init",&desc->init); if (desc->flags & CHIP_HAS_VOLUME) { - chip->left = desc->leftinit ? desc->leftinit : 65535; - chip->right = desc->rightinit ? desc->rightinit : 65535; - chip_write(chip,desc->leftreg,desc->volfunc(chip->left)); - chip_write(chip,desc->rightreg,desc->volfunc(chip->right)); + if (!desc->volfunc) { + /* This shouldn't be happen. Warn user, but keep working + without volume controls + */ + v4l_info(chip->c, "volume callback undefined!\n"); + desc->flags &= ~CHIP_HAS_VOLUME; + } else { + chip->left = desc->leftinit ? desc->leftinit : 65535; + chip->right = desc->rightinit ? desc->rightinit : 65535; + chip_write(chip, desc->leftreg, + desc->volfunc(chip->left)); + chip_write(chip, desc->rightreg, + desc->volfunc(chip->right)); + } } if (desc->flags & CHIP_HAS_BASSTREBLE) { - chip->treble = desc->trebleinit ? desc->trebleinit : 32768; - chip->bass = desc->bassinit ? desc->bassinit : 32768; - chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass)); - chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble)); + if (!desc->bassfunc || !desc->treblefunc) { + /* This shouldn't be happen. Warn user, but keep working + without bass/treble controls + */ + v4l_info(chip->c, "bass/treble callbacks undefined!\n"); + desc->flags &= ~CHIP_HAS_BASSTREBLE; + } else { + chip->treble = desc->trebleinit ? + desc->trebleinit : 32768; + chip->bass = desc->bassinit ? + desc->bassinit : 32768; + chip_write(chip, desc->bassreg, + desc->bassfunc(chip->bass)); + chip_write(chip, desc->treblereg, + desc->treblefunc(chip->treble)); + } } chip->thread = NULL; - if (desc->checkmode) { + if (desc->flags & CHIP_NEED_CHECKMODE) { + if (!desc->getmode || !desc->setmode) { + /* This shouldn't be happen. Warn user, but keep working + without kthread + */ + v4l_info(chip->c, "set/get mode callbacks undefined!\n"); + return 0; + } /* start async thread */ init_timer(&chip->wt); chip->wt.function = chip_thread_wake; @@ -1552,7 +1615,7 @@ static int chip_remove(struct i2c_client *client) static int tvaudio_get_ctrl(struct CHIPSTATE *chip, struct v4l2_control *ctrl) { - struct CHIPDESC *desc = chiplist + chip->type; + struct CHIPDESC *desc = chip->desc; switch (ctrl->id) { case V4L2_CID_AUDIO_MUTE: @@ -1576,13 +1639,13 @@ static int tvaudio_get_ctrl(struct CHIPSTATE *chip, return 0; } case V4L2_CID_AUDIO_BASS: - if (desc->flags & CHIP_HAS_BASSTREBLE) + if (!(desc->flags & CHIP_HAS_BASSTREBLE)) break; ctrl->value = chip->bass; return 0; case V4L2_CID_AUDIO_TREBLE: - if (desc->flags & CHIP_HAS_BASSTREBLE) - return -EINVAL; + if (!(desc->flags & CHIP_HAS_BASSTREBLE)) + break; ctrl->value = chip->treble; return 0; } @@ -1592,7 +1655,7 @@ static int tvaudio_get_ctrl(struct CHIPSTATE *chip, static int tvaudio_set_ctrl(struct CHIPSTATE *chip, struct v4l2_control *ctrl) { - struct CHIPDESC *desc = chiplist + chip->type; + struct CHIPDESC *desc = chip->desc; switch (ctrl->id) { case V4L2_CID_AUDIO_MUTE: @@ -1642,16 +1705,15 @@ static int tvaudio_set_ctrl(struct CHIPSTATE *chip, return 0; } case V4L2_CID_AUDIO_BASS: - if (desc->flags & CHIP_HAS_BASSTREBLE) + if (!(desc->flags & CHIP_HAS_BASSTREBLE)) break; chip->bass = ctrl->value; chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass)); return 0; case V4L2_CID_AUDIO_TREBLE: - if (desc->flags & CHIP_HAS_BASSTREBLE) - return -EINVAL; - + if (!(desc->flags & CHIP_HAS_BASSTREBLE)) + break; chip->treble = ctrl->value; chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble)); @@ -1668,9 +1730,12 @@ static int chip_command(struct i2c_client *client, unsigned int cmd, void *arg) { struct CHIPSTATE *chip = i2c_get_clientdata(client); - struct CHIPDESC *desc = chiplist + chip->type; + struct CHIPDESC *desc = chip->desc; - v4l_dbg(1, debug, chip->c, "%s: chip_command 0x%x\n", chip->c->name, cmd); + if (debug > 0) { + v4l_i2c_print_ioctl(chip->c, cmd); + printk("\n"); + } switch (cmd) { case AUDC_SET_RADIO: @@ -1695,7 +1760,7 @@ static int chip_command(struct i2c_client *client, break; case V4L2_CID_AUDIO_BASS: case V4L2_CID_AUDIO_TREBLE: - if (desc->flags & CHIP_HAS_BASSTREBLE) + if (!(desc->flags & CHIP_HAS_BASSTREBLE)) return -EINVAL; break; default: @@ -1792,12 +1857,20 @@ static int chip_command(struct i2c_client *client, break; case VIDIOC_S_FREQUENCY: chip->mode = 0; /* automatic */ - if (desc->checkmode && desc->setmode) { + + /* For chips that provide getmode and setmode, and doesn't + automatically follows the stereo carrier, a kthread is + created to set the audio standard. In this case, when then + the video channel is changed, tvaudio starts on MONO mode. + After waiting for 2 seconds, the kernel thread is called, + to follow whatever audio standard is pointed by the + audio carrier. + */ + if (chip->thread) { desc->setmode(chip,V4L2_TUNER_MODE_MONO); if (chip->prevmode != V4L2_TUNER_MODE_MONO) chip->prevmode = -1; /* reset previous mode */ mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000)); - /* the thread will call checkmode() later */ } break; @@ -1836,9 +1909,3 @@ static struct v4l2_i2c_driver_data v4l2_i2c_data = { .legacy_probe = chip_legacy_probe, .id_table = chip_id, }; - -/* - * Local variables: - * c-basic-offset: 8 - * End: - */ diff --git a/drivers/media/video/usbvideo/ibmcam.c b/drivers/media/video/usbvideo/ibmcam.c index 28421d386f1e..c710bcd1df48 100644 --- a/drivers/media/video/usbvideo/ibmcam.c +++ b/drivers/media/video/usbvideo/ibmcam.c @@ -3695,7 +3695,7 @@ static int ibmcam_probe(struct usb_interface *intf, const struct usb_device_id * unsigned char video_ep = 0; if (debug >= 1) - dev_info(&uvd->dev->dev, "ibmcam_probe(%p,%u.)\n", intf, ifnum); + dev_info(&dev->dev, "ibmcam_probe(%p,%u.)\n", intf, ifnum); /* We don't handle multi-config cameras */ if (dev->descriptor.bNumConfigurations != 1) @@ -3746,7 +3746,7 @@ static int ibmcam_probe(struct usb_interface *intf, const struct usb_device_id * brand = "IBM PC Camera"; /* a.k.a. Xirlink C-It */ break; } - dev_info(&uvd->dev->dev, + dev_info(&dev->dev, "%s USB camera found (model %d, rev. 0x%04x)\n", brand, model, le16_to_cpu(dev->descriptor.bcdDevice)); } while (0); @@ -3754,7 +3754,7 @@ static int ibmcam_probe(struct usb_interface *intf, const struct usb_device_id * /* Validate found interface: must have one ISO endpoint */ nas = intf->num_altsetting; if (debug > 0) - dev_info(&uvd->dev->dev, "Number of alternate settings=%d.\n", + dev_info(&dev->dev, "Number of alternate settings=%d.\n", nas); if (nas < 2) { err("Too few alternate settings for this camera!"); @@ -3799,7 +3799,7 @@ static int ibmcam_probe(struct usb_interface *intf, const struct usb_device_id * actInterface = i; maxPS = le16_to_cpu(endpoint->wMaxPacketSize); if (debug > 0) - dev_info(&uvd->dev->dev, + dev_info(&dev->dev, "Active setting=%d. " "maxPS=%d.\n", i, maxPS); } else @@ -3840,7 +3840,7 @@ static int ibmcam_probe(struct usb_interface *intf, const struct usb_device_id * RESTRICT_TO_RANGE(framerate, 0, 5); break; default: - dev_info(&uvd->dev->dev, "IBM camera: using 320x240\n"); + dev_info(&dev->dev, "IBM camera: using 320x240\n"); size = SIZE_320x240; /* No break here */ case SIZE_320x240: @@ -3869,7 +3869,7 @@ static int ibmcam_probe(struct usb_interface *intf, const struct usb_device_id * canvasY = 120; break; default: - dev_info(&uvd->dev->dev, "IBM NetCamera: using 176x144\n"); + dev_info(&dev->dev, "IBM NetCamera: using 176x144\n"); size = SIZE_176x144; /* No break here */ case SIZE_176x144: diff --git a/drivers/message/fusion/mptctl.c b/drivers/message/fusion/mptctl.c index f5233f3d9eff..b89f476cd0a9 100644 --- a/drivers/message/fusion/mptctl.c +++ b/drivers/message/fusion/mptctl.c @@ -559,12 +559,6 @@ mptctl_fasync(int fd, struct file *filep, int mode) return ret; } -static int -mptctl_release(struct inode *inode, struct file *filep) -{ - return fasync_helper(-1, filep, 0, &async_queue); -} - /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* * MPT ioctl handler @@ -2706,7 +2700,6 @@ mptctl_hp_targetinfo(unsigned long arg) static const struct file_operations mptctl_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .release = mptctl_release, .fasync = mptctl_fasync, .unlocked_ioctl = mptctl_ioctl, #ifdef CONFIG_COMPAT diff --git a/drivers/message/fusion/mptlan.c b/drivers/message/fusion/mptlan.c index a1abf95cf751..603ffd008c73 100644 --- a/drivers/message/fusion/mptlan.c +++ b/drivers/message/fusion/mptlan.c @@ -77,12 +77,6 @@ MODULE_VERSION(my_VERSION); * Fusion MPT LAN private structures */ -struct NAA_Hosed { - u16 NAA; - u8 ieee[FC_ALEN]; - struct NAA_Hosed *next; -}; - struct BufferControl { struct sk_buff *skb; dma_addr_t dma; @@ -159,11 +153,6 @@ static u8 LanCtx = MPT_MAX_PROTOCOL_DRIVERS; static u32 max_buckets_out = 127; static u32 tx_max_out_p = 127 - 16; -#ifdef QLOGIC_NAA_WORKAROUND -static struct NAA_Hosed *mpt_bad_naa = NULL; -DEFINE_RWLOCK(bad_naa_lock); -#endif - /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /** * lan_reply - Handle all data sent from the hardware. @@ -780,30 +769,6 @@ mpt_lan_sdu_send (struct sk_buff *skb, struct net_device *dev) // ctx, skb, skb->data)); mac = skb_mac_header(skb); -#ifdef QLOGIC_NAA_WORKAROUND -{ - struct NAA_Hosed *nh; - - /* Munge the NAA for Tx packets to QLogic boards, which don't follow - RFC 2625. The longer I look at this, the more my opinion of Qlogic - drops. */ - read_lock_irq(&bad_naa_lock); - for (nh = mpt_bad_naa; nh != NULL; nh=nh->next) { - if ((nh->ieee[0] == mac[0]) && - (nh->ieee[1] == mac[1]) && - (nh->ieee[2] == mac[2]) && - (nh->ieee[3] == mac[3]) && - (nh->ieee[4] == mac[4]) && - (nh->ieee[5] == mac[5])) { - cur_naa = nh->NAA; - dlprintk ((KERN_INFO "mptlan/sdu_send: using NAA value " - "= %04x.\n", cur_naa)); - break; - } - } - read_unlock_irq(&bad_naa_lock); -} -#endif pTrans->TransactionDetails[0] = cpu_to_le32((cur_naa << 16) | (mac[0] << 8) | @@ -1572,79 +1537,6 @@ mpt_lan_type_trans(struct sk_buff *skb, struct net_device *dev) fcllc = (struct fcllc *)skb->data; -#ifdef QLOGIC_NAA_WORKAROUND -{ - u16 source_naa = fch->stype, found = 0; - - /* Workaround for QLogic not following RFC 2625 in regards to the NAA - value. */ - - if ((source_naa & 0xF000) == 0) - source_naa = swab16(source_naa); - - if (fcllc->ethertype == htons(ETH_P_ARP)) - dlprintk ((KERN_INFO "mptlan/type_trans: got arp req/rep w/ naa of " - "%04x.\n", source_naa)); - - if ((fcllc->ethertype == htons(ETH_P_ARP)) && - ((source_naa >> 12) != MPT_LAN_NAA_RFC2625)){ - struct NAA_Hosed *nh, *prevnh; - int i; - - dlprintk ((KERN_INFO "mptlan/type_trans: ARP Req/Rep from " - "system with non-RFC 2625 NAA value (%04x).\n", - source_naa)); - - write_lock_irq(&bad_naa_lock); - for (prevnh = nh = mpt_bad_naa; nh != NULL; - prevnh=nh, nh=nh->next) { - if ((nh->ieee[0] == fch->saddr[0]) && - (nh->ieee[1] == fch->saddr[1]) && - (nh->ieee[2] == fch->saddr[2]) && - (nh->ieee[3] == fch->saddr[3]) && - (nh->ieee[4] == fch->saddr[4]) && - (nh->ieee[5] == fch->saddr[5])) { - found = 1; - dlprintk ((KERN_INFO "mptlan/type_trans: ARP Re" - "q/Rep w/ bad NAA from system already" - " in DB.\n")); - break; - } - } - - if ((!found) && (nh == NULL)) { - - nh = kmalloc(sizeof(struct NAA_Hosed), GFP_KERNEL); - dlprintk ((KERN_INFO "mptlan/type_trans: ARP Req/Rep w/" - " bad NAA from system not yet in DB.\n")); - - if (nh != NULL) { - nh->next = NULL; - if (!mpt_bad_naa) - mpt_bad_naa = nh; - if (prevnh) - prevnh->next = nh; - - nh->NAA = source_naa; /* Set the S_NAA value. */ - for (i = 0; i < FC_ALEN; i++) - nh->ieee[i] = fch->saddr[i]; - dlprintk ((KERN_INFO "Got ARP from %02x:%02x:%02x:%02x:" - "%02x:%02x with non-compliant S_NAA value.\n", - fch->saddr[0], fch->saddr[1], fch->saddr[2], - fch->saddr[3], fch->saddr[4],fch->saddr[5])); - } else { - printk (KERN_ERR "mptlan/type_trans: Unable to" - " kmalloc a NAA_Hosed struct.\n"); - } - } else if (!found) { - printk (KERN_ERR "mptlan/type_trans: found not" - " set, but nh isn't null. Evil " - "funkiness abounds.\n"); - } - write_unlock_irq(&bad_naa_lock); - } -} -#endif /* Strip the SNAP header from ARP packets since we don't * pass them through to the 802.2/SNAP layers. diff --git a/drivers/message/fusion/mptscsih.c b/drivers/message/fusion/mptscsih.c index d62fd4f6b52e..ee090413e598 100644 --- a/drivers/message/fusion/mptscsih.c +++ b/drivers/message/fusion/mptscsih.c @@ -2008,6 +2008,9 @@ mptscsih_host_reset(struct scsi_cmnd *SCpnt) return FAILED; } + /* make sure we have no outstanding commands at this stage */ + mptscsih_flush_running_cmds(hd); + ioc = hd->ioc; printk(MYIOC_s_INFO_FMT "attempting host reset! (sc=%p)\n", ioc->name, SCpnt); diff --git a/drivers/message/i2o/i2o_block.c b/drivers/message/i2o/i2o_block.c index 11a617ab4243..a443e136dc41 100644 --- a/drivers/message/i2o/i2o_block.c +++ b/drivers/message/i2o/i2o_block.c @@ -354,7 +354,7 @@ static inline void i2o_block_sglist_free(struct i2o_block_request *ireq) * @req: the request to prepare * * Allocate the necessary i2o_block_request struct and connect it to - * the request. This is needed that we not loose the SG list later on. + * the request. This is needed that we not lose the SG list later on. * * Returns BLKPREP_OK on success or BLKPREP_DEFER on failure. */ @@ -567,8 +567,8 @@ static void i2o_block_biosparam(unsigned long capacity, unsigned short *cyls, /** * i2o_block_open - Open the block device - * @inode: inode for block device being opened - * @file: file to open + * @bdev: block device being opened + * @mode: file open mode * * Power up the device, mount and lock the media. This function is called, * if the block device is opened for access. @@ -596,8 +596,8 @@ static int i2o_block_open(struct block_device *bdev, fmode_t mode) /** * i2o_block_release - Release the I2O block device - * @inode: inode for block device being released - * @file: file to close + * @disk: gendisk device being released + * @mode: file open mode * * Unlock and unmount the media, and power down the device. Gets called if * the block device is closed. @@ -643,8 +643,8 @@ static int i2o_block_getgeo(struct block_device *bdev, struct hd_geometry *geo) /** * i2o_block_ioctl - Issue device specific ioctl calls. - * @inode: inode for block device ioctl - * @file: file for ioctl + * @bdev: block device being opened + * @mode: file open mode * @cmd: ioctl command * @arg: arg * diff --git a/drivers/message/i2o/i2o_config.c b/drivers/message/i2o/i2o_config.c index a3fabdbe6ca6..f3384c32b9a1 100644 --- a/drivers/message/i2o/i2o_config.c +++ b/drivers/message/i2o/i2o_config.c @@ -1097,28 +1097,17 @@ static int cfg_fasync(int fd, struct file *fp, int on) static int cfg_release(struct inode *inode, struct file *file) { ulong id = (ulong) file->private_data; - struct i2o_cfg_info *p1, *p2; + struct i2o_cfg_info *p, **q; unsigned long flags; lock_kernel(); - p1 = p2 = NULL; - spin_lock_irqsave(&i2o_config_lock, flags); - for (p1 = open_files; p1;) { - if (p1->q_id == id) { - - if (p1->fasync) - cfg_fasync(-1, file, 0); - if (p2) - p2->next = p1->next; - else - open_files = p1->next; - - kfree(p1); + for (q = &open_files; (p = *q) != NULL; q = &p->next) { + if (p->q_id == id) { + *q = p->next; + kfree(p); break; } - p2 = p1; - p1 = p1->next; } spin_unlock_irqrestore(&i2o_config_lock, flags); unlock_kernel(); diff --git a/drivers/message/i2o/iop.c b/drivers/message/i2o/iop.c index be2b5926d26c..6e53a30bfd38 100644 --- a/drivers/message/i2o/iop.c +++ b/drivers/message/i2o/iop.c @@ -49,7 +49,6 @@ static int i2o_hrt_get(struct i2o_controller *c); /** * i2o_msg_get_wait - obtain an I2O message from the IOP * @c: I2O controller - * @msg: pointer to a I2O message pointer * @wait: how long to wait until timeout * * This function waits up to wait seconds for a message slot to be diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 5a79d2d4cdae..257277394f8c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -81,7 +81,7 @@ config MFD_TMIO config MFD_T7L66XB bool "Support Toshiba T7L66XB" - depends on ARM + depends on ARM && HAVE_CLK select MFD_CORE select MFD_TMIO help @@ -89,7 +89,7 @@ config MFD_T7L66XB config MFD_TC6387XB bool "Support Toshiba TC6387XB" - depends on ARM + depends on ARM && HAVE_CLK select MFD_CORE select MFD_TMIO help @@ -103,8 +103,20 @@ config MFD_TC6393XB help Support for Toshiba Mobile IO Controller TC6393XB +config PMIC_DA903X + bool "Dialog Semiconductor DA9030/DA9034 PMIC Support" + depends on I2C=y + help + Say yes here to support for Dialog Semiconductor DA9030 (a.k.a + ARAVA) and DA9034 (a.k.a MICCO), these are Power Management IC + usually found on PXA processors-based platforms. This includes + the I2C driver and the core APIs _only_, you have to select + individual components like LCD backlight, voltage regulators, + LEDs and battery-charger under the corresponding menus. + config MFD_WM8400 tristate "Support Wolfson Microelectronics WM8400" + depends on I2C help Support for the Wolfson Microelecronics WM8400 PMIC and audio CODEC. This driver adds provides common support for accessing diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 0acefe8aff87..9a5ad8af9116 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -30,3 +30,5 @@ ifeq ($(CONFIG_SA1100_ASSABET),y) obj-$(CONFIG_MCP_UCB1200) += ucb1x00-assabet.o endif obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o + +obj-$(CONFIG_PMIC_DA903X) += da903x.o \ No newline at end of file diff --git a/drivers/mfd/da903x.c b/drivers/mfd/da903x.c index b57326ae464d..0b5bd85dfcec 100644 --- a/drivers/mfd/da903x.c +++ b/drivers/mfd/da903x.c @@ -267,7 +267,7 @@ static int da9030_mask_events(struct da903x_chip *chip, unsigned int events) { uint8_t v[3]; - chip->events_mask &= ~events; + chip->events_mask |= events; v[0] = (chip->events_mask & 0xff); v[1] = (chip->events_mask >> 8) & 0xff; diff --git a/drivers/mfd/wm8350-i2c.c b/drivers/mfd/wm8350-i2c.c index 8dfe21bb3bd1..3e0ce0e50ea2 100644 --- a/drivers/mfd/wm8350-i2c.c +++ b/drivers/mfd/wm8350-i2c.c @@ -30,7 +30,12 @@ static int wm8350_i2c_read_device(struct wm8350 *wm8350, char reg, ret = i2c_master_send(wm8350->i2c_client, ®, 1); if (ret < 0) return ret; - return i2c_master_recv(wm8350->i2c_client, dest, bytes); + ret = i2c_master_recv(wm8350->i2c_client, dest, bytes); + if (ret < 0) + return ret; + if (ret != bytes) + return -EIO; + return 0; } static int wm8350_i2c_write_device(struct wm8350 *wm8350, char reg, @@ -38,13 +43,19 @@ static int wm8350_i2c_write_device(struct wm8350 *wm8350, char reg, { /* we add 1 byte for device register */ u8 msg[(WM8350_MAX_REGISTER << 1) + 1]; + int ret; if (bytes > ((WM8350_MAX_REGISTER << 1) + 1)) return -EINVAL; msg[0] = reg; memcpy(&msg[1], src, bytes); - return i2c_master_send(wm8350->i2c_client, msg, bytes + 1); + ret = i2c_master_send(wm8350->i2c_client, msg, bytes + 1); + if (ret < 0) + return ret; + if (ret != bytes + 1) + return -EIO; + return 0; } static int wm8350_i2c_probe(struct i2c_client *i2c, diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 9494400e8fd0..fee7304102af 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -227,10 +227,20 @@ config HP_WMI To compile this driver as a module, choose M here: the module will be called hp-wmi. +config ICS932S401 + tristate "Integrated Circuits ICS932S401" + depends on I2C && EXPERIMENTAL + help + If you say yes here you get support for the Integrated Circuits + ICS932S401 clock control chips. + + This driver can also be built as a module. If so, the module + will be called ics932s401. + config MSI_LAPTOP tristate "MSI Laptop Extras" depends on X86 - depends on ACPI_EC + depends on ACPI depends on BACKLIGHT_CLASS_DEVICE ---help--- This is a driver for laptops built by MSI (MICRO-STAR @@ -260,7 +270,7 @@ config PANASONIC_LAPTOP config COMPAL_LAPTOP tristate "Compal Laptop Extras" depends on X86 - depends on ACPI_EC + depends on ACPI depends on BACKLIGHT_CLASS_DEVICE ---help--- This is a driver for laptops built by Compal: @@ -488,4 +498,6 @@ config SGI_GRU_DEBUG This option enables addition debugging code for the SGI GRU driver. If you are unsure, say N. +source "drivers/misc/c2port/Kconfig" + endif # MISC_DEVICES diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 909e2468cdc9..817f7f5ab3bd 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o obj-$(CONFIG_HP_WMI) += hp-wmi.o +obj-$(CONFIG_ICS932S401) += ics932s401.o obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o obj-$(CONFIG_LKDTM) += lkdtm.o obj-$(CONFIG_TIFM_CORE) += tifm_core.o @@ -31,3 +32,4 @@ obj-$(CONFIG_KGDB_TESTS) += kgdbts.o obj-$(CONFIG_SGI_XP) += sgi-xp/ obj-$(CONFIG_SGI_GRU) += sgi-gru/ obj-$(CONFIG_HP_ILO) += hpilo.o +obj-$(CONFIG_C2PORT) += c2port/ diff --git a/drivers/misc/acer-wmi.c b/drivers/misc/acer-wmi.c index 0532a2de2ce4..94c9f911824e 100644 --- a/drivers/misc/acer-wmi.c +++ b/drivers/misc/acer-wmi.c @@ -1297,6 +1297,12 @@ static int __init acer_wmi_init(void) set_quirks(); + if (!acpi_video_backlight_support() && has_cap(ACER_CAP_BRIGHTNESS)) { + interface->capability &= ~ACER_CAP_BRIGHTNESS; + printk(ACER_INFO "Brightness must be controlled by " + "generic video driver\n"); + } + if (platform_driver_register(&acer_platform_driver)) { printk(ACER_ERR "Unable to register platform driver.\n"); goto error_platform_register; diff --git a/drivers/misc/asus-laptop.c b/drivers/misc/asus-laptop.c index a9d5228724a6..8fb8b3591048 100644 --- a/drivers/misc/asus-laptop.c +++ b/drivers/misc/asus-laptop.c @@ -1208,9 +1208,13 @@ static int __init asus_laptop_init(void) dev = acpi_get_physical_device(hotk->device->handle); - result = asus_backlight_init(dev); - if (result) - goto fail_backlight; + if (!acpi_video_backlight_support()) { + result = asus_backlight_init(dev); + if (result) + goto fail_backlight; + } else + printk(ASUS_INFO "Brightness ignored, must be controlled by " + "ACPI video driver\n"); result = asus_led_init(dev); if (result) diff --git a/drivers/misc/c2port/Kconfig b/drivers/misc/c2port/Kconfig new file mode 100644 index 000000000000..e46af9a5810d --- /dev/null +++ b/drivers/misc/c2port/Kconfig @@ -0,0 +1,35 @@ +# +# C2 port devices +# + +menuconfig C2PORT + tristate "Silicon Labs C2 port support (EXPERIMENTAL)" + depends on EXPERIMENTAL + default no + help + This option enables support for Silicon Labs C2 port used to + program Silicon micro controller chips (and other 8051 compatible). + + If your board have no such micro controllers you don't need this + interface at all. + + To compile this driver as a module, choose M here: the module will + be called c2port_core. Note that you also need a client module + usually called c2port-*. + + If you are not sure, say N here. + +if C2PORT + +config C2PORT_DURAMAR_2150 + tristate "C2 port support for Eurotech's Duramar 2150 (EXPERIMENTAL)" + depends on X86 && C2PORT + default no + help + This option enables C2 support for the Eurotech's Duramar 2150 + on board micro controller. + + To compile this driver as a module, choose M here: the module will + be called c2port-duramar2150. + +endif # C2PORT diff --git a/drivers/misc/c2port/Makefile b/drivers/misc/c2port/Makefile new file mode 100644 index 000000000000..3b2cf43d60f5 --- /dev/null +++ b/drivers/misc/c2port/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_C2PORT) += core.o + +obj-$(CONFIG_C2PORT_DURAMAR_2150) += c2port-duramar2150.o diff --git a/drivers/misc/c2port/c2port-duramar2150.c b/drivers/misc/c2port/c2port-duramar2150.c new file mode 100644 index 000000000000..338dcc121507 --- /dev/null +++ b/drivers/misc/c2port/c2port-duramar2150.c @@ -0,0 +1,158 @@ +/* + * Silicon Labs C2 port Linux support for Eurotech Duramar 2150 + * + * Copyright (c) 2008 Rodolfo Giometti + * Copyright (c) 2008 Eurotech S.p.A. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DATA_PORT 0x325 +#define DIR_PORT 0x326 +#define C2D (1 << 0) +#define C2CK (1 << 1) + +static DEFINE_MUTEX(update_lock); + +/* + * C2 port operations + */ + +static void duramar2150_c2port_access(struct c2port_device *dev, int status) +{ + u8 v; + + mutex_lock(&update_lock); + + v = inb(DIR_PORT); + + /* 0 = input, 1 = output */ + if (status) + outb(v | (C2D | C2CK), DIR_PORT); + else + /* When access is "off" is important that both lines are set + * as inputs or hi-impedence */ + outb(v & ~(C2D | C2CK), DIR_PORT); + + mutex_unlock(&update_lock); +} + +static void duramar2150_c2port_c2d_dir(struct c2port_device *dev, int dir) +{ + u8 v; + + mutex_lock(&update_lock); + + v = inb(DIR_PORT); + + if (dir) + outb(v & ~C2D, DIR_PORT); + else + outb(v | C2D, DIR_PORT); + + mutex_unlock(&update_lock); +} + +static int duramar2150_c2port_c2d_get(struct c2port_device *dev) +{ + return inb(DATA_PORT) & C2D; +} + +static void duramar2150_c2port_c2d_set(struct c2port_device *dev, int status) +{ + u8 v; + + mutex_lock(&update_lock); + + v = inb(DATA_PORT); + + if (status) + outb(v | C2D, DATA_PORT); + else + outb(v & ~C2D, DATA_PORT); + + mutex_unlock(&update_lock); +} + +static void duramar2150_c2port_c2ck_set(struct c2port_device *dev, int status) +{ + u8 v; + + mutex_lock(&update_lock); + + v = inb(DATA_PORT); + + if (status) + outb(v | C2CK, DATA_PORT); + else + outb(v & ~C2CK, DATA_PORT); + + mutex_unlock(&update_lock); +} + +static struct c2port_ops duramar2150_c2port_ops = { + .block_size = 512, /* bytes */ + .blocks_num = 30, /* total flash size: 15360 bytes */ + + .access = duramar2150_c2port_access, + .c2d_dir = duramar2150_c2port_c2d_dir, + .c2d_get = duramar2150_c2port_c2d_get, + .c2d_set = duramar2150_c2port_c2d_set, + .c2ck_set = duramar2150_c2port_c2ck_set, +}; + +static struct c2port_device *duramar2150_c2port_dev; + +/* + * Module stuff + */ + +static int __init duramar2150_c2port_init(void) +{ + struct resource *res; + int ret = 0; + + res = request_region(0x325, 2, "c2port"); + if (!res) + return -EBUSY; + + duramar2150_c2port_dev = c2port_device_register("uc", + &duramar2150_c2port_ops, NULL); + if (!duramar2150_c2port_dev) { + ret = -ENODEV; + goto free_region; + } + + return 0; + +free_region: + release_region(0x325, 2); + return ret; +} + +static void __exit duramar2150_c2port_exit(void) +{ + /* Setup the GPIOs as input by default (access = 0) */ + duramar2150_c2port_access(duramar2150_c2port_dev, 0); + + c2port_device_unregister(duramar2150_c2port_dev); + + release_region(0x325, 2); +} + +module_init(duramar2150_c2port_init); +module_exit(duramar2150_c2port_exit); + +MODULE_AUTHOR("Rodolfo Giometti "); +MODULE_DESCRIPTION("Silicon Labs C2 port Linux support for Duramar 2150"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/c2port/core.c b/drivers/misc/c2port/core.c new file mode 100644 index 000000000000..0207dd59090d --- /dev/null +++ b/drivers/misc/c2port/core.c @@ -0,0 +1,1003 @@ +/* + * Silicon Labs C2 port core Linux support + * + * Copyright (c) 2007 Rodolfo Giometti + * Copyright (c) 2007 Eurotech S.p.A. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "c2port" +#define DRIVER_VERSION "0.51.0" + +static DEFINE_SPINLOCK(c2port_idr_lock); +static DEFINE_IDR(c2port_idr); + +/* + * Local variables + */ + +static struct class *c2port_class; + +/* + * C2 registers & commands defines + */ + +/* C2 registers */ +#define C2PORT_DEVICEID 0x00 +#define C2PORT_REVID 0x01 +#define C2PORT_FPCTL 0x02 +#define C2PORT_FPDAT 0xB4 + +/* C2 interface commands */ +#define C2PORT_GET_VERSION 0x01 +#define C2PORT_DEVICE_ERASE 0x03 +#define C2PORT_BLOCK_READ 0x06 +#define C2PORT_BLOCK_WRITE 0x07 +#define C2PORT_PAGE_ERASE 0x08 + +/* C2 status return codes */ +#define C2PORT_INVALID_COMMAND 0x00 +#define C2PORT_COMMAND_FAILED 0x02 +#define C2PORT_COMMAND_OK 0x0d + +/* + * C2 port low level signal managements + */ + +static void c2port_reset(struct c2port_device *dev) +{ + struct c2port_ops *ops = dev->ops; + + /* To reset the device we have to keep clock line low for at least + * 20us. + */ + local_irq_disable(); + ops->c2ck_set(dev, 0); + udelay(25); + ops->c2ck_set(dev, 1); + local_irq_enable(); + + udelay(1); +} + +static void c2port_strobe_ck(struct c2port_device *dev) +{ + struct c2port_ops *ops = dev->ops; + + /* During hi-low-hi transition we disable local IRQs to avoid + * interructions since C2 port specification says that it must be + * shorter than 5us, otherwise the microcontroller may consider + * it as a reset signal! + */ + local_irq_disable(); + ops->c2ck_set(dev, 0); + udelay(1); + ops->c2ck_set(dev, 1); + local_irq_enable(); + + udelay(1); +} + +/* + * C2 port basic functions + */ + +static void c2port_write_ar(struct c2port_device *dev, u8 addr) +{ + struct c2port_ops *ops = dev->ops; + int i; + + /* START field */ + c2port_strobe_ck(dev); + + /* INS field (11b, LSB first) */ + ops->c2d_dir(dev, 0); + ops->c2d_set(dev, 1); + c2port_strobe_ck(dev); + ops->c2d_set(dev, 1); + c2port_strobe_ck(dev); + + /* ADDRESS field */ + for (i = 0; i < 8; i++) { + ops->c2d_set(dev, addr & 0x01); + c2port_strobe_ck(dev); + + addr >>= 1; + } + + /* STOP field */ + ops->c2d_dir(dev, 1); + c2port_strobe_ck(dev); +} + +static int c2port_read_ar(struct c2port_device *dev, u8 *addr) +{ + struct c2port_ops *ops = dev->ops; + int i; + + /* START field */ + c2port_strobe_ck(dev); + + /* INS field (10b, LSB first) */ + ops->c2d_dir(dev, 0); + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + ops->c2d_set(dev, 1); + c2port_strobe_ck(dev); + + /* ADDRESS field */ + ops->c2d_dir(dev, 1); + *addr = 0; + for (i = 0; i < 8; i++) { + *addr >>= 1; /* shift in 8-bit ADDRESS field LSB first */ + + c2port_strobe_ck(dev); + if (ops->c2d_get(dev)) + *addr |= 0x80; + } + + /* STOP field */ + c2port_strobe_ck(dev); + + return 0; +} + +static int c2port_write_dr(struct c2port_device *dev, u8 data) +{ + struct c2port_ops *ops = dev->ops; + int timeout, i; + + /* START field */ + c2port_strobe_ck(dev); + + /* INS field (01b, LSB first) */ + ops->c2d_dir(dev, 0); + ops->c2d_set(dev, 1); + c2port_strobe_ck(dev); + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + + /* LENGTH field (00b, LSB first -> 1 byte) */ + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + + /* DATA field */ + for (i = 0; i < 8; i++) { + ops->c2d_set(dev, data & 0x01); + c2port_strobe_ck(dev); + + data >>= 1; + } + + /* WAIT field */ + ops->c2d_dir(dev, 1); + timeout = 20; + do { + c2port_strobe_ck(dev); + if (ops->c2d_get(dev)) + break; + + udelay(1); + } while (--timeout > 0); + if (timeout == 0) + return -EIO; + + /* STOP field */ + c2port_strobe_ck(dev); + + return 0; +} + +static int c2port_read_dr(struct c2port_device *dev, u8 *data) +{ + struct c2port_ops *ops = dev->ops; + int timeout, i; + + /* START field */ + c2port_strobe_ck(dev); + + /* INS field (00b, LSB first) */ + ops->c2d_dir(dev, 0); + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + + /* LENGTH field (00b, LSB first -> 1 byte) */ + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + ops->c2d_set(dev, 0); + c2port_strobe_ck(dev); + + /* WAIT field */ + ops->c2d_dir(dev, 1); + timeout = 20; + do { + c2port_strobe_ck(dev); + if (ops->c2d_get(dev)) + break; + + udelay(1); + } while (--timeout > 0); + if (timeout == 0) + return -EIO; + + /* DATA field */ + *data = 0; + for (i = 0; i < 8; i++) { + *data >>= 1; /* shift in 8-bit DATA field LSB first */ + + c2port_strobe_ck(dev); + if (ops->c2d_get(dev)) + *data |= 0x80; + } + + /* STOP field */ + c2port_strobe_ck(dev); + + return 0; +} + +static int c2port_poll_in_busy(struct c2port_device *dev) +{ + u8 addr; + int ret, timeout = 20; + + do { + ret = (c2port_read_ar(dev, &addr)); + if (ret < 0) + return -EIO; + + if (!(addr & 0x02)) + break; + + udelay(1); + } while (--timeout > 0); + if (timeout == 0) + return -EIO; + + return 0; +} + +static int c2port_poll_out_ready(struct c2port_device *dev) +{ + u8 addr; + int ret, timeout = 10000; /* erase flash needs long time... */ + + do { + ret = (c2port_read_ar(dev, &addr)); + if (ret < 0) + return -EIO; + + if (addr & 0x01) + break; + + udelay(1); + } while (--timeout > 0); + if (timeout == 0) + return -EIO; + + return 0; +} + +/* + * sysfs methods + */ + +static ssize_t c2port_show_name(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", c2dev->name); +} + +static ssize_t c2port_show_flash_blocks_num(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + struct c2port_ops *ops = c2dev->ops; + + return sprintf(buf, "%d\n", ops->blocks_num); +} + +static ssize_t c2port_show_flash_block_size(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + struct c2port_ops *ops = c2dev->ops; + + return sprintf(buf, "%d\n", ops->block_size); +} + +static ssize_t c2port_show_flash_size(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + struct c2port_ops *ops = c2dev->ops; + + return sprintf(buf, "%d\n", ops->blocks_num * ops->block_size); +} + +static ssize_t c2port_show_access(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", c2dev->access); +} + +static ssize_t c2port_store_access(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + struct c2port_ops *ops = c2dev->ops; + int status, ret; + + ret = sscanf(buf, "%d", &status); + if (ret != 1) + return -EINVAL; + + mutex_lock(&c2dev->mutex); + + c2dev->access = !!status; + + /* If access is "on" clock should be HIGH _before_ setting the line + * as output and data line should be set as INPUT anyway */ + if (c2dev->access) + ops->c2ck_set(c2dev, 1); + ops->access(c2dev, c2dev->access); + if (c2dev->access) + ops->c2d_dir(c2dev, 1); + + mutex_unlock(&c2dev->mutex); + + return count; +} + +static ssize_t c2port_store_reset(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + + /* Check the device access status */ + if (!c2dev->access) + return -EBUSY; + + mutex_lock(&c2dev->mutex); + + c2port_reset(c2dev); + c2dev->flash_access = 0; + + mutex_unlock(&c2dev->mutex); + + return count; +} + +static ssize_t __c2port_show_dev_id(struct c2port_device *dev, char *buf) +{ + u8 data; + int ret; + + /* Select DEVICEID register for C2 data register accesses */ + c2port_write_ar(dev, C2PORT_DEVICEID); + + /* Read and return the device ID register */ + ret = c2port_read_dr(dev, &data); + if (ret < 0) + return ret; + + return sprintf(buf, "%d\n", data); +} + +static ssize_t c2port_show_dev_id(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + ssize_t ret; + + /* Check the device access status */ + if (!c2dev->access) + return -EBUSY; + + mutex_lock(&c2dev->mutex); + ret = __c2port_show_dev_id(c2dev, buf); + mutex_unlock(&c2dev->mutex); + + if (ret < 0) + dev_err(dev, "cannot read from %s\n", c2dev->name); + + return ret; +} + +static ssize_t __c2port_show_rev_id(struct c2port_device *dev, char *buf) +{ + u8 data; + int ret; + + /* Select REVID register for C2 data register accesses */ + c2port_write_ar(dev, C2PORT_REVID); + + /* Read and return the revision ID register */ + ret = c2port_read_dr(dev, &data); + if (ret < 0) + return ret; + + return sprintf(buf, "%d\n", data); +} + +static ssize_t c2port_show_rev_id(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + ssize_t ret; + + /* Check the device access status */ + if (!c2dev->access) + return -EBUSY; + + mutex_lock(&c2dev->mutex); + ret = __c2port_show_rev_id(c2dev, buf); + mutex_unlock(&c2dev->mutex); + + if (ret < 0) + dev_err(c2dev->dev, "cannot read from %s\n", c2dev->name); + + return ret; +} + +static ssize_t c2port_show_flash_access(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", c2dev->flash_access); +} + +static ssize_t __c2port_store_flash_access(struct c2port_device *dev, + int status) +{ + int ret; + + /* Check the device access status */ + if (!dev->access) + return -EBUSY; + + dev->flash_access = !!status; + + /* If flash_access is off we have nothing to do... */ + if (dev->flash_access == 0) + return 0; + + /* Target the C2 flash programming control register for C2 data + * register access */ + c2port_write_ar(dev, C2PORT_FPCTL); + + /* Write the first keycode to enable C2 Flash programming */ + ret = c2port_write_dr(dev, 0x02); + if (ret < 0) + return ret; + + /* Write the second keycode to enable C2 Flash programming */ + ret = c2port_write_dr(dev, 0x01); + if (ret < 0) + return ret; + + /* Delay for at least 20ms to ensure the target is ready for + * C2 flash programming */ + mdelay(25); + + return 0; +} + +static ssize_t c2port_store_flash_access(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + int status; + ssize_t ret; + + ret = sscanf(buf, "%d", &status); + if (ret != 1) + return -EINVAL; + + mutex_lock(&c2dev->mutex); + ret = __c2port_store_flash_access(c2dev, status); + mutex_unlock(&c2dev->mutex); + + if (ret < 0) { + dev_err(c2dev->dev, "cannot enable %s flash programming\n", + c2dev->name); + return ret; + } + + return count; +} + +static ssize_t __c2port_write_flash_erase(struct c2port_device *dev) +{ + u8 status; + int ret; + + /* Target the C2 flash programming data register for C2 data register + * access. + */ + c2port_write_ar(dev, C2PORT_FPDAT); + + /* Send device erase command */ + c2port_write_dr(dev, C2PORT_DEVICE_ERASE); + + /* Wait for input acknowledge */ + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Should check status before starting FLASH access sequence */ + + /* Wait for status information */ + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + /* Read flash programming interface status */ + ret = c2port_read_dr(dev, &status); + if (ret < 0) + return ret; + if (status != C2PORT_COMMAND_OK) + return -EBUSY; + + /* Send a three-byte arming sequence to enable the device erase. + * If the sequence is not received correctly, the command will be + * ignored. + * Sequence is: 0xde, 0xad, 0xa5. + */ + c2port_write_dr(dev, 0xde); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + c2port_write_dr(dev, 0xad); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + c2port_write_dr(dev, 0xa5); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + return 0; +} + +static ssize_t c2port_store_flash_erase(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct c2port_device *c2dev = dev_get_drvdata(dev); + int ret; + + /* Check the device and flash access status */ + if (!c2dev->access || !c2dev->flash_access) + return -EBUSY; + + mutex_lock(&c2dev->mutex); + ret = __c2port_write_flash_erase(c2dev); + mutex_unlock(&c2dev->mutex); + + if (ret < 0) { + dev_err(c2dev->dev, "cannot erase %s flash\n", c2dev->name); + return ret; + } + + return count; +} + +static ssize_t __c2port_read_flash_data(struct c2port_device *dev, + char *buffer, loff_t offset, size_t count) +{ + struct c2port_ops *ops = dev->ops; + u8 status, nread = 128; + int i, ret; + + /* Check for flash end */ + if (offset >= ops->block_size * ops->blocks_num) + return 0; + + if (ops->block_size * ops->blocks_num - offset < nread) + nread = ops->block_size * ops->blocks_num - offset; + if (count < nread) + nread = count; + if (nread == 0) + return nread; + + /* Target the C2 flash programming data register for C2 data register + * access */ + c2port_write_ar(dev, C2PORT_FPDAT); + + /* Send flash block read command */ + c2port_write_dr(dev, C2PORT_BLOCK_READ); + + /* Wait for input acknowledge */ + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Should check status before starting FLASH access sequence */ + + /* Wait for status information */ + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + /* Read flash programming interface status */ + ret = c2port_read_dr(dev, &status); + if (ret < 0) + return ret; + if (status != C2PORT_COMMAND_OK) + return -EBUSY; + + /* Send address high byte */ + c2port_write_dr(dev, offset >> 8); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Send address low byte */ + c2port_write_dr(dev, offset & 0x00ff); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Send address block size */ + c2port_write_dr(dev, nread); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Should check status before reading FLASH block */ + + /* Wait for status information */ + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + /* Read flash programming interface status */ + ret = c2port_read_dr(dev, &status); + if (ret < 0) + return ret; + if (status != C2PORT_COMMAND_OK) + return -EBUSY; + + /* Read flash block */ + for (i = 0; i < nread; i++) { + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + ret = c2port_read_dr(dev, buffer+i); + if (ret < 0) + return ret; + } + + return nread; +} + +static ssize_t c2port_read_flash_data(struct kobject *kobj, + struct bin_attribute *attr, + char *buffer, loff_t offset, size_t count) +{ + struct c2port_device *c2dev = + dev_get_drvdata(container_of(kobj, + struct device, kobj)); + ssize_t ret; + + /* Check the device and flash access status */ + if (!c2dev->access || !c2dev->flash_access) + return -EBUSY; + + mutex_lock(&c2dev->mutex); + ret = __c2port_read_flash_data(c2dev, buffer, offset, count); + mutex_unlock(&c2dev->mutex); + + if (ret < 0) + dev_err(c2dev->dev, "cannot read %s flash\n", c2dev->name); + + return ret; +} + +static ssize_t __c2port_write_flash_data(struct c2port_device *dev, + char *buffer, loff_t offset, size_t count) +{ + struct c2port_ops *ops = dev->ops; + u8 status, nwrite = 128; + int i, ret; + + if (nwrite > count) + nwrite = count; + if (ops->block_size * ops->blocks_num - offset < nwrite) + nwrite = ops->block_size * ops->blocks_num - offset; + + /* Check for flash end */ + if (offset >= ops->block_size * ops->blocks_num) + return -EINVAL; + + /* Target the C2 flash programming data register for C2 data register + * access */ + c2port_write_ar(dev, C2PORT_FPDAT); + + /* Send flash block write command */ + c2port_write_dr(dev, C2PORT_BLOCK_WRITE); + + /* Wait for input acknowledge */ + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Should check status before starting FLASH access sequence */ + + /* Wait for status information */ + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + /* Read flash programming interface status */ + ret = c2port_read_dr(dev, &status); + if (ret < 0) + return ret; + if (status != C2PORT_COMMAND_OK) + return -EBUSY; + + /* Send address high byte */ + c2port_write_dr(dev, offset >> 8); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Send address low byte */ + c2port_write_dr(dev, offset & 0x00ff); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Send address block size */ + c2port_write_dr(dev, nwrite); + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + /* Should check status before writing FLASH block */ + + /* Wait for status information */ + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + /* Read flash programming interface status */ + ret = c2port_read_dr(dev, &status); + if (ret < 0) + return ret; + if (status != C2PORT_COMMAND_OK) + return -EBUSY; + + /* Write flash block */ + for (i = 0; i < nwrite; i++) { + ret = c2port_write_dr(dev, *(buffer+i)); + if (ret < 0) + return ret; + + ret = c2port_poll_in_busy(dev); + if (ret < 0) + return ret; + + } + + /* Wait for last flash write to complete */ + ret = c2port_poll_out_ready(dev); + if (ret < 0) + return ret; + + return nwrite; +} + +static ssize_t c2port_write_flash_data(struct kobject *kobj, + struct bin_attribute *attr, + char *buffer, loff_t offset, size_t count) +{ + struct c2port_device *c2dev = + dev_get_drvdata(container_of(kobj, + struct device, kobj)); + int ret; + + /* Check the device access status */ + if (!c2dev->access || !c2dev->flash_access) + return -EBUSY; + + mutex_lock(&c2dev->mutex); + ret = __c2port_write_flash_data(c2dev, buffer, offset, count); + mutex_unlock(&c2dev->mutex); + + if (ret < 0) + dev_err(c2dev->dev, "cannot write %s flash\n", c2dev->name); + + return ret; +} + +/* + * Class attributes + */ + +static struct device_attribute c2port_attrs[] = { + __ATTR(name, 0444, c2port_show_name, NULL), + __ATTR(flash_blocks_num, 0444, c2port_show_flash_blocks_num, NULL), + __ATTR(flash_block_size, 0444, c2port_show_flash_block_size, NULL), + __ATTR(flash_size, 0444, c2port_show_flash_size, NULL), + __ATTR(access, 0644, c2port_show_access, c2port_store_access), + __ATTR(reset, 0200, NULL, c2port_store_reset), + __ATTR(dev_id, 0444, c2port_show_dev_id, NULL), + __ATTR(rev_id, 0444, c2port_show_rev_id, NULL), + + __ATTR(flash_access, 0644, c2port_show_flash_access, + c2port_store_flash_access), + __ATTR(flash_erase, 0200, NULL, c2port_store_flash_erase), + __ATTR_NULL, +}; + +static struct bin_attribute c2port_bin_attrs = { + .attr = { + .name = "flash_data", + .mode = 0644 + }, + .read = c2port_read_flash_data, + .write = c2port_write_flash_data, + /* .size is computed at run-time */ +}; + +/* + * Exported functions + */ + +struct c2port_device *c2port_device_register(char *name, + struct c2port_ops *ops, void *devdata) +{ + struct c2port_device *c2dev; + int id, ret; + + if (unlikely(!ops) || unlikely(!ops->access) || \ + unlikely(!ops->c2d_dir) || unlikely(!ops->c2ck_set) || \ + unlikely(!ops->c2d_get) || unlikely(!ops->c2d_set)) + return ERR_PTR(-EINVAL); + + c2dev = kmalloc(sizeof(struct c2port_device), GFP_KERNEL); + if (unlikely(!c2dev)) + return ERR_PTR(-ENOMEM); + + ret = idr_pre_get(&c2port_idr, GFP_KERNEL); + if (!ret) { + ret = -ENOMEM; + goto error_idr_get_new; + } + + spin_lock_irq(&c2port_idr_lock); + ret = idr_get_new(&c2port_idr, c2dev, &id); + spin_unlock_irq(&c2port_idr_lock); + + if (ret < 0) + goto error_idr_get_new; + c2dev->id = id; + + c2dev->dev = device_create(c2port_class, NULL, 0, c2dev, + "c2port%d", id); + if (unlikely(!c2dev->dev)) { + ret = -ENOMEM; + goto error_device_create; + } + dev_set_drvdata(c2dev->dev, c2dev); + + strncpy(c2dev->name, name, C2PORT_NAME_LEN); + c2dev->ops = ops; + mutex_init(&c2dev->mutex); + + /* Create binary file */ + c2port_bin_attrs.size = ops->blocks_num * ops->block_size; + ret = device_create_bin_file(c2dev->dev, &c2port_bin_attrs); + if (unlikely(ret)) + goto error_device_create_bin_file; + + /* By default C2 port access is off */ + c2dev->access = c2dev->flash_access = 0; + ops->access(c2dev, 0); + + dev_info(c2dev->dev, "C2 port %s added\n", name); + dev_info(c2dev->dev, "%s flash has %d blocks x %d bytes " + "(%d bytes total)\n", + name, ops->blocks_num, ops->block_size, + ops->blocks_num * ops->block_size); + + return c2dev; + +error_device_create_bin_file: + device_destroy(c2port_class, 0); + +error_device_create: + spin_lock_irq(&c2port_idr_lock); + idr_remove(&c2port_idr, id); + spin_unlock_irq(&c2port_idr_lock); + +error_idr_get_new: + kfree(c2dev); + + return ERR_PTR(ret); +} +EXPORT_SYMBOL(c2port_device_register); + +void c2port_device_unregister(struct c2port_device *c2dev) +{ + if (!c2dev) + return; + + dev_info(c2dev->dev, "C2 port %s removed\n", c2dev->name); + + device_remove_bin_file(c2dev->dev, &c2port_bin_attrs); + spin_lock_irq(&c2port_idr_lock); + idr_remove(&c2port_idr, c2dev->id); + spin_unlock_irq(&c2port_idr_lock); + + device_destroy(c2port_class, c2dev->id); + + kfree(c2dev); +} +EXPORT_SYMBOL(c2port_device_unregister); + +/* + * Module stuff + */ + +static int __init c2port_init(void) +{ + printk(KERN_INFO "Silicon Labs C2 port support v. " DRIVER_VERSION + " - (C) 2007 Rodolfo Giometti\n"); + + c2port_class = class_create(THIS_MODULE, "c2port"); + if (!c2port_class) { + printk(KERN_ERR "c2port: failed to allocate class\n"); + return -ENOMEM; + } + c2port_class->dev_attrs = c2port_attrs; + + return 0; +} + +static void __exit c2port_exit(void) +{ + class_destroy(c2port_class); +} + +module_init(c2port_init); +module_exit(c2port_exit); + +MODULE_AUTHOR("Rodolfo Giometti "); +MODULE_DESCRIPTION("Silicon Labs C2 port support v. " DRIVER_VERSION); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/compal-laptop.c b/drivers/misc/compal-laptop.c index 344b790a6253..11003bba10d3 100644 --- a/drivers/misc/compal-laptop.c +++ b/drivers/misc/compal-laptop.c @@ -326,12 +326,14 @@ static int __init compal_init(void) /* Register backlight stuff */ - compalbl_device = backlight_device_register("compal-laptop", NULL, NULL, - &compalbl_ops); - if (IS_ERR(compalbl_device)) - return PTR_ERR(compalbl_device); + if (!acpi_video_backlight_support()) { + compalbl_device = backlight_device_register("compal-laptop", NULL, NULL, + &compalbl_ops); + if (IS_ERR(compalbl_device)) + return PTR_ERR(compalbl_device); - compalbl_device->props.max_brightness = COMPAL_LCD_LEVEL_MAX-1; + compalbl_device->props.max_brightness = COMPAL_LCD_LEVEL_MAX-1; + } ret = platform_driver_register(&compal_driver); if (ret) diff --git a/drivers/misc/eeepc-laptop.c b/drivers/misc/eeepc-laptop.c index 9ef98b2d5039..02fe2b8b8939 100644 --- a/drivers/misc/eeepc-laptop.c +++ b/drivers/misc/eeepc-laptop.c @@ -825,9 +825,15 @@ static int __init eeepc_laptop_init(void) return -ENODEV; } dev = acpi_get_physical_device(ehotk->device->handle); - result = eeepc_backlight_init(dev); - if (result) - goto fail_backlight; + + if (!acpi_video_backlight_support()) { + result = eeepc_backlight_init(dev); + if (result) + goto fail_backlight; + } else + printk(EEEPC_INFO "Backlight controlled by ACPI video " + "driver\n"); + result = eeepc_hwmon_init(dev); if (result) goto fail_hwmon; diff --git a/drivers/misc/fujitsu-laptop.c b/drivers/misc/fujitsu-laptop.c index d2cf0bfe3163..a7dd3e9fb79d 100644 --- a/drivers/misc/fujitsu-laptop.c +++ b/drivers/misc/fujitsu-laptop.c @@ -464,6 +464,14 @@ static int dmi_check_cb_s6410(const struct dmi_system_id *id) return 0; } +static int dmi_check_cb_s6420(const struct dmi_system_id *id) +{ + dmi_check_cb_common(id); + fujitsu->keycode1 = KEY_SCREENLOCK; /* "Lock" */ + fujitsu->keycode2 = KEY_HELP; /* "Mobility Center" */ + return 0; +} + static int dmi_check_cb_p8010(const struct dmi_system_id *id) { dmi_check_cb_common(id); @@ -473,7 +481,7 @@ static int dmi_check_cb_p8010(const struct dmi_system_id *id) return 0; } -static struct dmi_system_id __initdata fujitsu_dmi_table[] = { +static struct dmi_system_id fujitsu_dmi_table[] = { { .ident = "Fujitsu Siemens S6410", .matches = { @@ -481,6 +489,13 @@ static struct dmi_system_id __initdata fujitsu_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK S6410"), }, .callback = dmi_check_cb_s6410}, + { + .ident = "Fujitsu Siemens S6420", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), + DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK S6420"), + }, + .callback = dmi_check_cb_s6420}, { .ident = "Fujitsu LifeBook P8010", .matches = { @@ -990,16 +1005,16 @@ static int __init fujitsu_init(void) /* Register backlight stuff */ - fujitsu->bl_device = - backlight_device_register("fujitsu-laptop", NULL, NULL, - &fujitsubl_ops); - if (IS_ERR(fujitsu->bl_device)) - return PTR_ERR(fujitsu->bl_device); - - max_brightness = fujitsu->max_brightness; - - fujitsu->bl_device->props.max_brightness = max_brightness - 1; - fujitsu->bl_device->props.brightness = fujitsu->brightness_level; + if (!acpi_video_backlight_support()) { + fujitsu->bl_device = + backlight_device_register("fujitsu-laptop", NULL, NULL, + &fujitsubl_ops); + if (IS_ERR(fujitsu->bl_device)) + return PTR_ERR(fujitsu->bl_device); + max_brightness = fujitsu->max_brightness; + fujitsu->bl_device->props.max_brightness = max_brightness - 1; + fujitsu->bl_device->props.brightness = fujitsu->brightness_level; + } ret = platform_driver_register(&fujitsupf_driver); if (ret) @@ -1035,7 +1050,8 @@ fail_hotkey: fail_backlight: - backlight_device_unregister(fujitsu->bl_device); + if (fujitsu->bl_device) + backlight_device_unregister(fujitsu->bl_device); fail_platform_device2: @@ -1062,7 +1078,8 @@ static void __exit fujitsu_cleanup(void) &fujitsupf_attribute_group); platform_device_unregister(fujitsu->pf_device); platform_driver_unregister(&fujitsupf_driver); - backlight_device_unregister(fujitsu->bl_device); + if (fujitsu->bl_device) + backlight_device_unregister(fujitsu->bl_device); acpi_bus_unregister_driver(&acpi_fujitsu_driver); diff --git a/drivers/misc/hdpuftrs/hdpu_nexus.c b/drivers/misc/hdpuftrs/hdpu_nexus.c index 08e26beefe64..ce39fa54949b 100644 --- a/drivers/misc/hdpuftrs/hdpu_nexus.c +++ b/drivers/misc/hdpuftrs/hdpu_nexus.c @@ -113,7 +113,6 @@ static int hdpu_nexus_probe(struct platform_device *pdev) if (!hdpu_chassis_id) printk(KERN_WARNING "sky_nexus: " "Unable to create proc dir entry: sky_chassis_id\n"); - } return 0; } diff --git a/drivers/misc/ics932s401.c b/drivers/misc/ics932s401.c new file mode 100644 index 000000000000..6e43ab4231ae --- /dev/null +++ b/drivers/misc/ics932s401.c @@ -0,0 +1,515 @@ +/* + * A driver for the Integrated Circuits ICS932S401 + * Copyright (C) 2008 IBM + * + * Author: Darrick J. Wong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END }; + +/* Insmod parameters */ +I2C_CLIENT_INSMOD_1(ics932s401); + +/* ICS932S401 registers */ +#define ICS932S401_REG_CFG2 0x01 +#define ICS932S401_CFG1_SPREAD 0x01 +#define ICS932S401_REG_CFG7 0x06 +#define ICS932S401_FS_MASK 0x07 +#define ICS932S401_REG_VENDOR_REV 0x07 +#define ICS932S401_VENDOR 1 +#define ICS932S401_VENDOR_MASK 0x0F +#define ICS932S401_REV 4 +#define ICS932S401_REV_SHIFT 4 +#define ICS932S401_REG_DEVICE 0x09 +#define ICS932S401_DEVICE 11 +#define ICS932S401_REG_CTRL 0x0A +#define ICS932S401_MN_ENABLED 0x80 +#define ICS932S401_CPU_ALT 0x04 +#define ICS932S401_SRC_ALT 0x08 +#define ICS932S401_REG_CPU_M_CTRL 0x0B +#define ICS932S401_M_MASK 0x3F +#define ICS932S401_REG_CPU_N_CTRL 0x0C +#define ICS932S401_REG_CPU_SPREAD1 0x0D +#define ICS932S401_REG_CPU_SPREAD2 0x0E +#define ICS932S401_SPREAD_MASK 0x7FFF +#define ICS932S401_REG_SRC_M_CTRL 0x0F +#define ICS932S401_REG_SRC_N_CTRL 0x10 +#define ICS932S401_REG_SRC_SPREAD1 0x11 +#define ICS932S401_REG_SRC_SPREAD2 0x12 +#define ICS932S401_REG_CPU_DIVISOR 0x13 +#define ICS932S401_CPU_DIVISOR_SHIFT 4 +#define ICS932S401_REG_PCISRC_DIVISOR 0x14 +#define ICS932S401_SRC_DIVISOR_MASK 0x0F +#define ICS932S401_PCI_DIVISOR_SHIFT 4 + +/* Base clock is 14.318MHz */ +#define BASE_CLOCK 14318 + +#define NUM_REGS 21 +#define NUM_MIRRORED_REGS 15 + +static int regs_to_copy[NUM_MIRRORED_REGS] = { + ICS932S401_REG_CFG2, + ICS932S401_REG_CFG7, + ICS932S401_REG_VENDOR_REV, + ICS932S401_REG_DEVICE, + ICS932S401_REG_CTRL, + ICS932S401_REG_CPU_M_CTRL, + ICS932S401_REG_CPU_N_CTRL, + ICS932S401_REG_CPU_SPREAD1, + ICS932S401_REG_CPU_SPREAD2, + ICS932S401_REG_SRC_M_CTRL, + ICS932S401_REG_SRC_N_CTRL, + ICS932S401_REG_SRC_SPREAD1, + ICS932S401_REG_SRC_SPREAD2, + ICS932S401_REG_CPU_DIVISOR, + ICS932S401_REG_PCISRC_DIVISOR, +}; + +/* How often do we reread sensors values? (In jiffies) */ +#define SENSOR_REFRESH_INTERVAL (2 * HZ) + +/* How often do we reread sensor limit values? (In jiffies) */ +#define LIMIT_REFRESH_INTERVAL (60 * HZ) + +struct ics932s401_data { + struct attribute_group attrs; + struct mutex lock; + char sensors_valid; + unsigned long sensors_last_updated; /* In jiffies */ + + u8 regs[NUM_REGS]; +}; + +static int ics932s401_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int ics932s401_detect(struct i2c_client *client, int kind, + struct i2c_board_info *info); +static int ics932s401_remove(struct i2c_client *client); + +static const struct i2c_device_id ics932s401_id[] = { + { "ics932s401", ics932s401 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ics932s401_id); + +static struct i2c_driver ics932s401_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "ics932s401", + }, + .probe = ics932s401_probe, + .remove = ics932s401_remove, + .id_table = ics932s401_id, + .detect = ics932s401_detect, + .address_data = &addr_data, +}; + +static struct ics932s401_data *ics932s401_update_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ics932s401_data *data = i2c_get_clientdata(client); + unsigned long local_jiffies = jiffies; + int i, temp; + + mutex_lock(&data->lock); + if (time_before(local_jiffies, data->sensors_last_updated + + SENSOR_REFRESH_INTERVAL) + && data->sensors_valid) + goto out; + + /* + * Each register must be read as a word and then right shifted 8 bits. + * Not really sure why this is; setting the "byte count programming" + * register to 1 does not fix this problem. + */ + for (i = 0; i < NUM_MIRRORED_REGS; i++) { + temp = i2c_smbus_read_word_data(client, regs_to_copy[i]); + data->regs[regs_to_copy[i]] = temp >> 8; + } + + data->sensors_last_updated = local_jiffies; + data->sensors_valid = 1; + +out: + mutex_unlock(&data->lock); + return data; +} + +static ssize_t show_spread_enabled(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + + if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD) + return sprintf(buf, "1\n"); + + return sprintf(buf, "0\n"); +} + +/* bit to cpu khz map */ +static const int fs_speeds[] = { + 266666, + 133333, + 200000, + 166666, + 333333, + 100000, + 400000, + 0, +}; + +/* clock divisor map */ +static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16, + 24, 40, 120}; + +/* Calculate CPU frequency from the M/N registers. */ +static int calculate_cpu_freq(struct ics932s401_data *data) +{ + int m, n, freq; + + m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK; + n = data->regs[ICS932S401_REG_CPU_N_CTRL]; + + /* Pull in bits 8 & 9 from the M register */ + n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1; + n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3; + + freq = BASE_CLOCK * (n + 8) / (m + 2); + freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >> + ICS932S401_CPU_DIVISOR_SHIFT]; + + return freq; +} + +static ssize_t show_cpu_clock(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + + return sprintf(buf, "%d\n", calculate_cpu_freq(data)); +} + +static ssize_t show_cpu_clock_sel(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + int freq; + + if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED) + freq = calculate_cpu_freq(data); + else { + /* Freq is neatly wrapped up for us */ + int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK; + freq = fs_speeds[fid]; + if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) { + switch (freq) { + case 166666: + freq = 160000; + break; + case 333333: + freq = 320000; + break; + } + } + } + + return sprintf(buf, "%d\n", freq); +} + +/* Calculate SRC frequency from the M/N registers. */ +static int calculate_src_freq(struct ics932s401_data *data) +{ + int m, n, freq; + + m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK; + n = data->regs[ICS932S401_REG_SRC_N_CTRL]; + + /* Pull in bits 8 & 9 from the M register */ + n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1; + n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3; + + freq = BASE_CLOCK * (n + 8) / (m + 2); + freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] & + ICS932S401_SRC_DIVISOR_MASK]; + + return freq; +} + +static ssize_t show_src_clock(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + + return sprintf(buf, "%d\n", calculate_src_freq(data)); +} + +static ssize_t show_src_clock_sel(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + int freq; + + if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED) + freq = calculate_src_freq(data); + else + /* Freq is neatly wrapped up for us */ + if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT && + data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT) + freq = 96000; + else + freq = 100000; + + return sprintf(buf, "%d\n", freq); +} + +/* Calculate PCI frequency from the SRC M/N registers. */ +static int calculate_pci_freq(struct ics932s401_data *data) +{ + int m, n, freq; + + m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK; + n = data->regs[ICS932S401_REG_SRC_N_CTRL]; + + /* Pull in bits 8 & 9 from the M register */ + n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1; + n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3; + + freq = BASE_CLOCK * (n + 8) / (m + 2); + freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >> + ICS932S401_PCI_DIVISOR_SHIFT]; + + return freq; +} + +static ssize_t show_pci_clock(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + + return sprintf(buf, "%d\n", calculate_pci_freq(data)); +} + +static ssize_t show_pci_clock_sel(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + int freq; + + if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED) + freq = calculate_pci_freq(data); + else + freq = 33333; + + return sprintf(buf, "%d\n", freq); +} + +static ssize_t show_value(struct device *dev, + struct device_attribute *devattr, + char *buf); + +static ssize_t show_spread(struct device *dev, + struct device_attribute *devattr, + char *buf); + +static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL); +static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL); +static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL); +static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL); +static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL); +static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL); +static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL); +static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL); +static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL); +static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL); +static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL); + +static struct attribute *ics932s401_attr[] = +{ + &dev_attr_spread_enabled.attr, + &dev_attr_cpu_clock_selection.attr, + &dev_attr_cpu_clock.attr, + &dev_attr_src_clock_selection.attr, + &dev_attr_src_clock.attr, + &dev_attr_pci_clock_selection.attr, + &dev_attr_pci_clock.attr, + &dev_attr_usb_clock.attr, + &dev_attr_ref_clock.attr, + &dev_attr_cpu_spread.attr, + &dev_attr_src_spread.attr, + NULL +}; + +static ssize_t show_value(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + int x; + + if (devattr == &dev_attr_usb_clock) + x = 48000; + else if (devattr == &dev_attr_ref_clock) + x = BASE_CLOCK; + else + BUG(); + + return sprintf(buf, "%d\n", x); +} + +static ssize_t show_spread(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct ics932s401_data *data = ics932s401_update_device(dev); + int reg; + unsigned long val; + + if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)) + return sprintf(buf, "0%%\n"); + + if (devattr == &dev_attr_src_spread) + reg = ICS932S401_REG_SRC_SPREAD1; + else if (devattr == &dev_attr_cpu_spread) + reg = ICS932S401_REG_CPU_SPREAD1; + else + BUG(); + + val = data->regs[reg] | (data->regs[reg + 1] << 8); + val &= ICS932S401_SPREAD_MASK; + + /* Scale 0..2^14 to -0.5. */ + val = 500000 * val / 16384; + return sprintf(buf, "-0.%lu%%\n", val); +} + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int ics932s401_detect(struct i2c_client *client, int kind, + struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + if (kind <= 0) { + int vendor, device, revision; + + vendor = i2c_smbus_read_word_data(client, + ICS932S401_REG_VENDOR_REV); + vendor >>= 8; + revision = vendor >> ICS932S401_REV_SHIFT; + vendor &= ICS932S401_VENDOR_MASK; + if (vendor != ICS932S401_VENDOR) + return -ENODEV; + + device = i2c_smbus_read_word_data(client, + ICS932S401_REG_DEVICE); + device >>= 8; + if (device != ICS932S401_DEVICE) + return -ENODEV; + + if (revision != ICS932S401_REV) + dev_info(&adapter->dev, "Unknown revision %d\n", + revision); + } else + dev_dbg(&adapter->dev, "detection forced\n"); + + strlcpy(info->type, "ics932s401", I2C_NAME_SIZE); + + return 0; +} + +static int ics932s401_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ics932s401_data *data; + int err; + + data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL); + if (!data) { + err = -ENOMEM; + goto exit; + } + + i2c_set_clientdata(client, data); + mutex_init(&data->lock); + + dev_info(&client->dev, "%s chip found\n", client->name); + + /* Register sysfs hooks */ + data->attrs.attrs = ics932s401_attr; + err = sysfs_create_group(&client->dev.kobj, &data->attrs); + if (err) + goto exit_free; + + return 0; + +exit_free: + kfree(data); +exit: + return err; +} + +static int ics932s401_remove(struct i2c_client *client) +{ + struct ics932s401_data *data = i2c_get_clientdata(client); + + sysfs_remove_group(&client->dev.kobj, &data->attrs); + kfree(data); + return 0; +} + +static int __init ics932s401_init(void) +{ + return i2c_add_driver(&ics932s401_driver); +} + +static void __exit ics932s401_exit(void) +{ + i2c_del_driver(&ics932s401_driver); +} + +MODULE_AUTHOR("Darrick J. Wong "); +MODULE_DESCRIPTION("ICS932S401 driver"); +MODULE_LICENSE("GPL"); + +module_init(ics932s401_init); +module_exit(ics932s401_exit); + +/* IBM IntelliStation Z30 */ +MODULE_ALIAS("dmi:bvnIBM:*:rn9228:*"); +MODULE_ALIAS("dmi:bvnIBM:*:rn9232:*"); + +/* IBM x3650/x3550 */ +MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650*"); +MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550*"); diff --git a/drivers/misc/intel_menlow.c b/drivers/misc/intel_menlow.c index e00a2756e97e..27b7662955bb 100644 --- a/drivers/misc/intel_menlow.c +++ b/drivers/misc/intel_menlow.c @@ -52,6 +52,11 @@ MODULE_LICENSE("GPL"); #define MEMORY_ARG_CUR_BANDWIDTH 1 #define MEMORY_ARG_MAX_BANDWIDTH 0 +/* + * GTHS returning 'n' would mean that [0,n-1] states are supported + * In that case max_cstate would be n-1 + * GTHS returning '0' would mean that no bandwidth control states are supported + */ static int memory_get_int_max_bandwidth(struct thermal_cooling_device *cdev, unsigned long *max_state) { @@ -71,6 +76,9 @@ static int memory_get_int_max_bandwidth(struct thermal_cooling_device *cdev, if (ACPI_FAILURE(status)) return -EFAULT; + if (!value) + return -EINVAL; + *max_state = value - 1; return 0; } @@ -121,7 +129,7 @@ static int memory_set_cur_bandwidth(struct thermal_cooling_device *cdev, if (memory_get_int_max_bandwidth(cdev, &max_state)) return -EFAULT; - if (max_state < 0 || state > max_state) + if (state > max_state) return -EINVAL; arg_list.count = 1; diff --git a/drivers/misc/msi-laptop.c b/drivers/misc/msi-laptop.c index de898c6938f3..759763d18e4c 100644 --- a/drivers/misc/msi-laptop.c +++ b/drivers/misc/msi-laptop.c @@ -347,12 +347,16 @@ static int __init msi_init(void) /* Register backlight stuff */ - msibl_device = backlight_device_register("msi-laptop-bl", NULL, NULL, - &msibl_ops); - if (IS_ERR(msibl_device)) - return PTR_ERR(msibl_device); - - msibl_device->props.max_brightness = MSI_LCD_LEVEL_MAX-1; + if (acpi_video_backlight_support()) { + printk(KERN_INFO "MSI: Brightness ignored, must be controlled " + "by ACPI video driver\n"); + } else { + msibl_device = backlight_device_register("msi-laptop-bl", NULL, + NULL, &msibl_ops); + if (IS_ERR(msibl_device)) + return PTR_ERR(msibl_device); + msibl_device->props.max_brightness = MSI_LCD_LEVEL_MAX-1; + } ret = platform_driver_register(&msipf_driver); if (ret) diff --git a/drivers/misc/panasonic-laptop.c b/drivers/misc/panasonic-laptop.c index a2cb598d8ab5..4a1bc64485d5 100644 --- a/drivers/misc/panasonic-laptop.c +++ b/drivers/misc/panasonic-laptop.c @@ -116,7 +116,6 @@ * */ -#include #include #include #include diff --git a/drivers/misc/sgi-gru/Makefile b/drivers/misc/sgi-gru/Makefile index d03597a521b0..9e9170b3599a 100644 --- a/drivers/misc/sgi-gru/Makefile +++ b/drivers/misc/sgi-gru/Makefile @@ -1,3 +1,7 @@ +ifdef CONFIG_SGI_GRU_DEBUG + EXTRA_CFLAGS += -DDEBUG +endif + obj-$(CONFIG_SGI_GRU) := gru.o gru-y := grufile.o grumain.o grufault.o grutlbpurge.o gruprocfs.o grukservices.o diff --git a/drivers/misc/sgi-gru/grufault.c b/drivers/misc/sgi-gru/grufault.c index 8c389d606c30..3ee698ad8599 100644 --- a/drivers/misc/sgi-gru/grufault.c +++ b/drivers/misc/sgi-gru/grufault.c @@ -254,7 +254,11 @@ static int atomic_pte_lookup(struct vm_area_struct *vma, unsigned long vaddr, return 1; *paddr = pte_pfn(pte) << PAGE_SHIFT; +#ifdef CONFIG_HUGETLB_PAGE *pageshift = is_vm_hugetlb_page(vma) ? HPAGE_SHIFT : PAGE_SHIFT; +#else + *pageshift = PAGE_SHIFT; +#endif return 0; err: diff --git a/drivers/misc/sgi-gru/grufile.c b/drivers/misc/sgi-gru/grufile.c index 5c027b6b4e5a..650983806392 100644 --- a/drivers/misc/sgi-gru/grufile.c +++ b/drivers/misc/sgi-gru/grufile.c @@ -481,7 +481,7 @@ struct vm_operations_struct gru_vm_ops = { .fault = gru_fault, }; -module_init(gru_init); +fs_initcall(gru_init); module_exit(gru_exit); module_param(gru_options, ulong, 0644); diff --git a/drivers/misc/sgi-gru/gruprocfs.c b/drivers/misc/sgi-gru/gruprocfs.c index 533923f83f1a..73b0ca061bb5 100644 --- a/drivers/misc/sgi-gru/gruprocfs.c +++ b/drivers/misc/sgi-gru/gruprocfs.c @@ -317,7 +317,6 @@ int gru_proc_init(void) { struct proc_entry *p; - proc_mkdir("sgi_uv", NULL); proc_gru = proc_mkdir("sgi_uv/gru", NULL); for (p = proc_files; p->name; p++) diff --git a/drivers/misc/sgi-xp/Makefile b/drivers/misc/sgi-xp/Makefile index 35ce28578075..4fc40d8e1bcc 100644 --- a/drivers/misc/sgi-xp/Makefile +++ b/drivers/misc/sgi-xp/Makefile @@ -5,14 +5,14 @@ obj-$(CONFIG_SGI_XP) += xp.o xp-y := xp_main.o xp-$(CONFIG_IA64_SGI_SN2) += xp_sn2.o xp_nofault.o -xp-$(CONFIG_IA64_GENERIC) += xp_sn2.o xp_nofault.o xp_uv.o +xp-$(CONFIG_IA64_GENERIC) += xp_sn2.o xp_nofault.o xp-$(CONFIG_IA64_SGI_UV) += xp_uv.o xp-$(CONFIG_X86_64) += xp_uv.o obj-$(CONFIG_SGI_XP) += xpc.o xpc-y := xpc_main.o xpc_channel.o xpc_partition.o xpc-$(CONFIG_IA64_SGI_SN2) += xpc_sn2.o -xpc-$(CONFIG_IA64_GENERIC) += xpc_sn2.o xpc_uv.o +xpc-$(CONFIG_IA64_GENERIC) += xpc_sn2.o xpc-$(CONFIG_IA64_SGI_UV) += xpc_uv.o xpc-$(CONFIG_X86_64) += xpc_uv.o diff --git a/drivers/misc/sgi-xp/xp.h b/drivers/misc/sgi-xp/xp.h index 859a5281c61b..7b4cbd5e03e9 100644 --- a/drivers/misc/sgi-xp/xp.h +++ b/drivers/misc/sgi-xp/xp.h @@ -19,7 +19,11 @@ #include #include /* defines is_shub1() and is_shub2() */ #define is_shub() ia64_platform_is("sn2") +#ifdef CONFIG_IA64_SGI_UV #define is_uv() ia64_platform_is("uv") +#else +#define is_uv() 0 +#endif #endif #ifdef CONFIG_X86_64 #include @@ -190,9 +194,10 @@ enum xp_retval { xpGruSendMqError, /* 59: gru send message queue related error */ xpBadChannelNumber, /* 60: invalid channel number */ - xpBadMsgType, /* 60: invalid message type */ + xpBadMsgType, /* 61: invalid message type */ + xpBiosError, /* 62: BIOS error */ - xpUnknownReason /* 61: unknown reason - must be last in enum */ + xpUnknownReason /* 63: unknown reason - must be last in enum */ }; /* @@ -341,6 +346,8 @@ extern unsigned long (*xp_pa) (void *); extern enum xp_retval (*xp_remote_memcpy) (unsigned long, const unsigned long, size_t); extern int (*xp_cpu_to_nasid) (int); +extern enum xp_retval (*xp_expand_memprotect) (unsigned long, unsigned long); +extern enum xp_retval (*xp_restrict_memprotect) (unsigned long, unsigned long); extern u64 xp_nofault_PIOR_target; extern int xp_nofault_PIOR(void *); diff --git a/drivers/misc/sgi-xp/xp_main.c b/drivers/misc/sgi-xp/xp_main.c index 66a1d19e08ad..9a2e77172d94 100644 --- a/drivers/misc/sgi-xp/xp_main.c +++ b/drivers/misc/sgi-xp/xp_main.c @@ -51,6 +51,13 @@ EXPORT_SYMBOL_GPL(xp_remote_memcpy); int (*xp_cpu_to_nasid) (int cpuid); EXPORT_SYMBOL_GPL(xp_cpu_to_nasid); +enum xp_retval (*xp_expand_memprotect) (unsigned long phys_addr, + unsigned long size); +EXPORT_SYMBOL_GPL(xp_expand_memprotect); +enum xp_retval (*xp_restrict_memprotect) (unsigned long phys_addr, + unsigned long size); +EXPORT_SYMBOL_GPL(xp_restrict_memprotect); + /* * xpc_registrations[] keeps track of xpc_connect()'s done by the kernel-level * users of XPC. diff --git a/drivers/misc/sgi-xp/xp_sn2.c b/drivers/misc/sgi-xp/xp_sn2.c index 1440134caf31..fb3ec9d735a9 100644 --- a/drivers/misc/sgi-xp/xp_sn2.c +++ b/drivers/misc/sgi-xp/xp_sn2.c @@ -120,6 +120,38 @@ xp_cpu_to_nasid_sn2(int cpuid) return cpuid_to_nasid(cpuid); } +static enum xp_retval +xp_expand_memprotect_sn2(unsigned long phys_addr, unsigned long size) +{ + u64 nasid_array = 0; + int ret; + + ret = sn_change_memprotect(phys_addr, size, SN_MEMPROT_ACCESS_CLASS_1, + &nasid_array); + if (ret != 0) { + dev_err(xp, "sn_change_memprotect(,, " + "SN_MEMPROT_ACCESS_CLASS_1,) failed ret=%d\n", ret); + return xpSalError; + } + return xpSuccess; +} + +static enum xp_retval +xp_restrict_memprotect_sn2(unsigned long phys_addr, unsigned long size) +{ + u64 nasid_array = 0; + int ret; + + ret = sn_change_memprotect(phys_addr, size, SN_MEMPROT_ACCESS_CLASS_0, + &nasid_array); + if (ret != 0) { + dev_err(xp, "sn_change_memprotect(,, " + "SN_MEMPROT_ACCESS_CLASS_0,) failed ret=%d\n", ret); + return xpSalError; + } + return xpSuccess; +} + enum xp_retval xp_init_sn2(void) { @@ -132,6 +164,8 @@ xp_init_sn2(void) xp_pa = xp_pa_sn2; xp_remote_memcpy = xp_remote_memcpy_sn2; xp_cpu_to_nasid = xp_cpu_to_nasid_sn2; + xp_expand_memprotect = xp_expand_memprotect_sn2; + xp_restrict_memprotect = xp_restrict_memprotect_sn2; return xp_register_nofault_code_sn2(); } diff --git a/drivers/misc/sgi-xp/xp_uv.c b/drivers/misc/sgi-xp/xp_uv.c index d9f7ce2510bc..d238576b26fa 100644 --- a/drivers/misc/sgi-xp/xp_uv.c +++ b/drivers/misc/sgi-xp/xp_uv.c @@ -15,6 +15,11 @@ #include #include +#if defined CONFIG_X86_64 +#include +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV +#include +#endif #include "../sgi-gru/grukservices.h" #include "xp.h" @@ -49,18 +54,79 @@ xp_cpu_to_nasid_uv(int cpuid) return UV_PNODE_TO_NASID(uv_cpu_to_pnode(cpuid)); } +static enum xp_retval +xp_expand_memprotect_uv(unsigned long phys_addr, unsigned long size) +{ + int ret; + +#if defined CONFIG_X86_64 + ret = uv_bios_change_memprotect(phys_addr, size, UV_MEMPROT_ALLOW_RW); + if (ret != BIOS_STATUS_SUCCESS) { + dev_err(xp, "uv_bios_change_memprotect(,, " + "UV_MEMPROT_ALLOW_RW) failed, ret=%d\n", ret); + return xpBiosError; + } + +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + u64 nasid_array; + + ret = sn_change_memprotect(phys_addr, size, SN_MEMPROT_ACCESS_CLASS_1, + &nasid_array); + if (ret != 0) { + dev_err(xp, "sn_change_memprotect(,, " + "SN_MEMPROT_ACCESS_CLASS_1,) failed ret=%d\n", ret); + return xpSalError; + } +#else + #error not a supported configuration +#endif + return xpSuccess; +} + +static enum xp_retval +xp_restrict_memprotect_uv(unsigned long phys_addr, unsigned long size) +{ + int ret; + +#if defined CONFIG_X86_64 + ret = uv_bios_change_memprotect(phys_addr, size, + UV_MEMPROT_RESTRICT_ACCESS); + if (ret != BIOS_STATUS_SUCCESS) { + dev_err(xp, "uv_bios_change_memprotect(,, " + "UV_MEMPROT_RESTRICT_ACCESS) failed, ret=%d\n", ret); + return xpBiosError; + } + +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + u64 nasid_array; + + ret = sn_change_memprotect(phys_addr, size, SN_MEMPROT_ACCESS_CLASS_0, + &nasid_array); + if (ret != 0) { + dev_err(xp, "sn_change_memprotect(,, " + "SN_MEMPROT_ACCESS_CLASS_0,) failed ret=%d\n", ret); + return xpSalError; + } +#else + #error not a supported configuration +#endif + return xpSuccess; +} + enum xp_retval xp_init_uv(void) { BUG_ON(!is_uv()); xp_max_npartitions = XP_MAX_NPARTITIONS_UV; - xp_partition_id = 0; /* !!! not correct value */ - xp_region_size = 0; /* !!! not correct value */ + xp_partition_id = sn_partition_id; + xp_region_size = sn_region_size; xp_pa = xp_pa_uv; xp_remote_memcpy = xp_remote_memcpy_uv; xp_cpu_to_nasid = xp_cpu_to_nasid_uv; + xp_expand_memprotect = xp_expand_memprotect_uv; + xp_restrict_memprotect = xp_restrict_memprotect_uv; return xpSuccess; } diff --git a/drivers/misc/sgi-xp/xpc.h b/drivers/misc/sgi-xp/xpc.h index 619208d61862..a5bd658c2e83 100644 --- a/drivers/misc/sgi-xp/xpc.h +++ b/drivers/misc/sgi-xp/xpc.h @@ -180,6 +180,18 @@ struct xpc_vars_part_sn2 { (XPC_RP_MACH_NASIDS(_rp) + \ xpc_nasid_mask_nlongs)) +/* + * Info pertinent to a GRU message queue using a watch list for irq generation. + */ +struct xpc_gru_mq_uv { + void *address; /* address of GRU message queue */ + unsigned int order; /* size of GRU message queue as a power of 2 */ + int irq; /* irq raised when message is received in mq */ + int mmr_blade; /* blade where watchlist was allocated from */ + unsigned long mmr_offset; /* offset of irq mmr located on mmr_blade */ + int watchlist_num; /* number of watchlist allocatd by BIOS */ +}; + /* * The activate_mq is used to send/receive GRU messages that affect XPC's * heartbeat, partition active state, and channel state. This is UV only. diff --git a/drivers/misc/sgi-xp/xpc_main.c b/drivers/misc/sgi-xp/xpc_main.c index 46325fc84811..e8d5cfbd32c2 100644 --- a/drivers/misc/sgi-xp/xpc_main.c +++ b/drivers/misc/sgi-xp/xpc_main.c @@ -1104,7 +1104,7 @@ xpc_do_exit(enum xp_retval reason) if (is_shub()) xpc_exit_sn2(); - else + else if (is_uv()) xpc_exit_uv(); } @@ -1363,7 +1363,7 @@ out_2: out_1: if (is_shub()) xpc_exit_sn2(); - else + else if (is_uv()) xpc_exit_uv(); return ret; } diff --git a/drivers/misc/sgi-xp/xpc_sn2.c b/drivers/misc/sgi-xp/xpc_sn2.c index b4882ccf6344..73b7fb8de47a 100644 --- a/drivers/misc/sgi-xp/xpc_sn2.c +++ b/drivers/misc/sgi-xp/xpc_sn2.c @@ -553,22 +553,17 @@ static u64 xpc_prot_vec_sn2[MAX_NUMNODES]; static enum xp_retval xpc_allow_amo_ops_sn2(struct amo *amos_page) { - u64 nasid_array = 0; - int ret; + enum xp_retval ret = xpSuccess; /* * On SHUB 1.1, we cannot call sn_change_memprotect() since the BIST * collides with memory operations. On those systems we call * xpc_allow_amo_ops_shub_wars_1_1_sn2() instead. */ - if (!enable_shub_wars_1_1()) { - ret = sn_change_memprotect(ia64_tpa((u64)amos_page), PAGE_SIZE, - SN_MEMPROT_ACCESS_CLASS_1, - &nasid_array); - if (ret != 0) - return xpSalError; - } - return xpSuccess; + if (!enable_shub_wars_1_1()) + ret = xp_expand_memprotect(ia64_tpa((u64)amos_page), PAGE_SIZE); + + return ret; } /* diff --git a/drivers/misc/sgi-xp/xpc_uv.c b/drivers/misc/sgi-xp/xpc_uv.c index 1ac694c01623..91a55b1b1037 100644 --- a/drivers/misc/sgi-xp/xpc_uv.c +++ b/drivers/misc/sgi-xp/xpc_uv.c @@ -18,7 +18,15 @@ #include #include #include +#include #include +#if defined CONFIG_X86_64 +#include +#include +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV +#include +#include +#endif #include "../sgi-gru/gru.h" #include "../sgi-gru/grukservices.h" #include "xpc.h" @@ -27,15 +35,17 @@ static atomic64_t xpc_heartbeat_uv; static DECLARE_BITMAP(xpc_heartbeating_to_mask_uv, XP_MAX_NPARTITIONS_UV); #define XPC_ACTIVATE_MSG_SIZE_UV (1 * GRU_CACHE_LINE_BYTES) -#define XPC_NOTIFY_MSG_SIZE_UV (2 * GRU_CACHE_LINE_BYTES) +#define XPC_ACTIVATE_MQ_SIZE_UV (4 * XP_MAX_NPARTITIONS_UV * \ + XPC_ACTIVATE_MSG_SIZE_UV) +#define XPC_ACTIVATE_IRQ_NAME "xpc_activate" -#define XPC_ACTIVATE_MQ_SIZE_UV (4 * XP_MAX_NPARTITIONS_UV * \ - XPC_ACTIVATE_MSG_SIZE_UV) -#define XPC_NOTIFY_MQ_SIZE_UV (4 * XP_MAX_NPARTITIONS_UV * \ - XPC_NOTIFY_MSG_SIZE_UV) +#define XPC_NOTIFY_MSG_SIZE_UV (2 * GRU_CACHE_LINE_BYTES) +#define XPC_NOTIFY_MQ_SIZE_UV (4 * XP_MAX_NPARTITIONS_UV * \ + XPC_NOTIFY_MSG_SIZE_UV) +#define XPC_NOTIFY_IRQ_NAME "xpc_notify" -static void *xpc_activate_mq_uv; -static void *xpc_notify_mq_uv; +static struct xpc_gru_mq_uv *xpc_activate_mq_uv; +static struct xpc_gru_mq_uv *xpc_notify_mq_uv; static int xpc_setup_partitions_sn_uv(void) @@ -52,62 +62,209 @@ xpc_setup_partitions_sn_uv(void) return 0; } -static void * -xpc_create_gru_mq_uv(unsigned int mq_size, int cpuid, unsigned int irq, +static int +xpc_get_gru_mq_irq_uv(struct xpc_gru_mq_uv *mq, int cpu, char *irq_name) +{ +#if defined CONFIG_X86_64 + mq->irq = uv_setup_irq(irq_name, cpu, mq->mmr_blade, mq->mmr_offset); + if (mq->irq < 0) { + dev_err(xpc_part, "uv_setup_irq() returned error=%d\n", + mq->irq); + } + +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + int mmr_pnode; + unsigned long mmr_value; + + if (strcmp(irq_name, XPC_ACTIVATE_IRQ_NAME) == 0) + mq->irq = SGI_XPC_ACTIVATE; + else if (strcmp(irq_name, XPC_NOTIFY_IRQ_NAME) == 0) + mq->irq = SGI_XPC_NOTIFY; + else + return -EINVAL; + + mmr_pnode = uv_blade_to_pnode(mq->mmr_blade); + mmr_value = (unsigned long)cpu_physical_id(cpu) << 32 | mq->irq; + + uv_write_global_mmr64(mmr_pnode, mq->mmr_offset, mmr_value); +#else + #error not a supported configuration +#endif + + return 0; +} + +static void +xpc_release_gru_mq_irq_uv(struct xpc_gru_mq_uv *mq) +{ +#if defined CONFIG_X86_64 + uv_teardown_irq(mq->irq, mq->mmr_blade, mq->mmr_offset); + +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + int mmr_pnode; + unsigned long mmr_value; + + mmr_pnode = uv_blade_to_pnode(mq->mmr_blade); + mmr_value = 1UL << 16; + + uv_write_global_mmr64(mmr_pnode, mq->mmr_offset, mmr_value); +#else + #error not a supported configuration +#endif +} + +static int +xpc_gru_mq_watchlist_alloc_uv(struct xpc_gru_mq_uv *mq) +{ + int ret; + +#if defined CONFIG_X86_64 + ret = uv_bios_mq_watchlist_alloc(mq->mmr_blade, uv_gpa(mq->address), + mq->order, &mq->mmr_offset); + if (ret < 0) { + dev_err(xpc_part, "uv_bios_mq_watchlist_alloc() failed, " + "ret=%d\n", ret); + return ret; + } +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + ret = sn_mq_watchlist_alloc(mq->mmr_blade, uv_gpa(mq->address), + mq->order, &mq->mmr_offset); + if (ret < 0) { + dev_err(xpc_part, "sn_mq_watchlist_alloc() failed, ret=%d\n", + ret); + return -EBUSY; + } +#else + #error not a supported configuration +#endif + + mq->watchlist_num = ret; + return 0; +} + +static void +xpc_gru_mq_watchlist_free_uv(struct xpc_gru_mq_uv *mq) +{ + int ret; + +#if defined CONFIG_X86_64 + ret = uv_bios_mq_watchlist_free(mq->mmr_blade, mq->watchlist_num); + BUG_ON(ret != BIOS_STATUS_SUCCESS); +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + ret = sn_mq_watchlist_free(mq->mmr_blade, mq->watchlist_num); + BUG_ON(ret != SALRET_OK); +#else + #error not a supported configuration +#endif +} + +static struct xpc_gru_mq_uv * +xpc_create_gru_mq_uv(unsigned int mq_size, int cpu, char *irq_name, irq_handler_t irq_handler) { + enum xp_retval xp_ret; int ret; int nid; - int mq_order; + int pg_order; struct page *page; - void *mq; + struct xpc_gru_mq_uv *mq; + + mq = kmalloc(sizeof(struct xpc_gru_mq_uv), GFP_KERNEL); + if (mq == NULL) { + dev_err(xpc_part, "xpc_create_gru_mq_uv() failed to kmalloc() " + "a xpc_gru_mq_uv structure\n"); + ret = -ENOMEM; + goto out_1; + } + + pg_order = get_order(mq_size); + mq->order = pg_order + PAGE_SHIFT; + mq_size = 1UL << mq->order; + + mq->mmr_blade = uv_cpu_to_blade_id(cpu); - nid = cpu_to_node(cpuid); - mq_order = get_order(mq_size); + nid = cpu_to_node(cpu); page = alloc_pages_node(nid, GFP_KERNEL | __GFP_ZERO | GFP_THISNODE, - mq_order); + pg_order); if (page == NULL) { dev_err(xpc_part, "xpc_create_gru_mq_uv() failed to alloc %d " "bytes of memory on nid=%d for GRU mq\n", mq_size, nid); - return NULL; + ret = -ENOMEM; + goto out_2; } + mq->address = page_address(page); - mq = page_address(page); - ret = gru_create_message_queue(mq, mq_size); + ret = gru_create_message_queue(mq->address, mq_size); if (ret != 0) { dev_err(xpc_part, "gru_create_message_queue() returned " "error=%d\n", ret); - free_pages((unsigned long)mq, mq_order); - return NULL; + ret = -EINVAL; + goto out_3; } - /* !!! Need to do some other things to set up IRQ */ + /* enable generation of irq when GRU mq operation occurs to this mq */ + ret = xpc_gru_mq_watchlist_alloc_uv(mq); + if (ret != 0) + goto out_3; - ret = request_irq(irq, irq_handler, 0, "xpc", NULL); + ret = xpc_get_gru_mq_irq_uv(mq, cpu, irq_name); + if (ret != 0) + goto out_4; + + ret = request_irq(mq->irq, irq_handler, 0, irq_name, NULL); if (ret != 0) { dev_err(xpc_part, "request_irq(irq=%d) returned error=%d\n", - irq, ret); - free_pages((unsigned long)mq, mq_order); - return NULL; + mq->irq, ret); + goto out_5; } - /* !!! enable generation of irq when GRU mq op occurs to this mq */ - - /* ??? allow other partitions to access GRU mq? */ + /* allow other partitions to access this GRU mq */ + xp_ret = xp_expand_memprotect(xp_pa(mq->address), mq_size); + if (xp_ret != xpSuccess) { + ret = -EACCES; + goto out_6; + } return mq; + + /* something went wrong */ +out_6: + free_irq(mq->irq, NULL); +out_5: + xpc_release_gru_mq_irq_uv(mq); +out_4: + xpc_gru_mq_watchlist_free_uv(mq); +out_3: + free_pages((unsigned long)mq->address, pg_order); +out_2: + kfree(mq); +out_1: + return ERR_PTR(ret); } static void -xpc_destroy_gru_mq_uv(void *mq, unsigned int mq_size, unsigned int irq) +xpc_destroy_gru_mq_uv(struct xpc_gru_mq_uv *mq) { - /* ??? disallow other partitions to access GRU mq? */ + unsigned int mq_size; + int pg_order; + int ret; + + /* disallow other partitions to access GRU mq */ + mq_size = 1UL << mq->order; + ret = xp_restrict_memprotect(xp_pa(mq->address), mq_size); + BUG_ON(ret != xpSuccess); - /* !!! disable generation of irq when GRU mq op occurs to this mq */ + /* unregister irq handler and release mq irq/vector mapping */ + free_irq(mq->irq, NULL); + xpc_release_gru_mq_irq_uv(mq); - free_irq(irq, NULL); + /* disable generation of irq when GRU mq op occurs to this mq */ + xpc_gru_mq_watchlist_free_uv(mq); - free_pages((unsigned long)mq, get_order(mq_size)); + pg_order = mq->order - PAGE_SHIFT; + free_pages((unsigned long)mq->address, pg_order); + + kfree(mq); } static enum xp_retval @@ -402,7 +559,10 @@ xpc_handle_activate_IRQ_uv(int irq, void *dev_id) struct xpc_partition *part; int wakeup_hb_checker = 0; - while ((msg_hdr = gru_get_next_message(xpc_activate_mq_uv)) != NULL) { + while (1) { + msg_hdr = gru_get_next_message(xpc_activate_mq_uv->address); + if (msg_hdr == NULL) + break; partid = msg_hdr->partid; if (partid < 0 || partid >= XP_MAX_NPARTITIONS_UV) { @@ -418,7 +578,7 @@ xpc_handle_activate_IRQ_uv(int irq, void *dev_id) } } - gru_free_message(xpc_activate_mq_uv, msg_hdr); + gru_free_message(xpc_activate_mq_uv->address, msg_hdr); } if (wakeup_hb_checker) @@ -482,7 +642,7 @@ xpc_send_local_activate_IRQ_uv(struct xpc_partition *part, int act_state_req) struct xpc_partition_uv *part_uv = &part->sn.uv; /* - * !!! Make our side think that the remote parition sent an activate + * !!! Make our side think that the remote partition sent an activate * !!! message our way by doing what the activate IRQ handler would * !!! do had one really been sent. */ @@ -500,14 +660,39 @@ static enum xp_retval xpc_get_partition_rsvd_page_pa_uv(void *buf, u64 *cookie, unsigned long *rp_pa, size_t *len) { - /* !!! call the UV version of sn_partition_reserved_page_pa() */ - return xpUnsupported; + s64 status; + enum xp_retval ret; + +#if defined CONFIG_X86_64 + status = uv_bios_reserved_page_pa((u64)buf, cookie, (u64 *)rp_pa, + (u64 *)len); + if (status == BIOS_STATUS_SUCCESS) + ret = xpSuccess; + else if (status == BIOS_STATUS_MORE_PASSES) + ret = xpNeedMoreInfo; + else + ret = xpBiosError; + +#elif defined CONFIG_IA64_GENERIC || defined CONFIG_IA64_SGI_UV + status = sn_partition_reserved_page_pa((u64)buf, cookie, rp_pa, len); + if (status == SALRET_OK) + ret = xpSuccess; + else if (status == SALRET_MORE_PASSES) + ret = xpNeedMoreInfo; + else + ret = xpSalError; + +#else + #error not a supported configuration +#endif + + return ret; } static int xpc_setup_rsvd_page_sn_uv(struct xpc_rsvd_page *rp) { - rp->sn.activate_mq_gpa = uv_gpa(xpc_activate_mq_uv); + rp->sn.activate_mq_gpa = uv_gpa(xpc_activate_mq_uv->address); return 0; } @@ -1411,22 +1596,18 @@ xpc_init_uv(void) return -E2BIG; } - /* ??? The cpuid argument's value is 0, is that what we want? */ - /* !!! The irq argument's value isn't correct. */ - xpc_activate_mq_uv = xpc_create_gru_mq_uv(XPC_ACTIVATE_MQ_SIZE_UV, 0, 0, + xpc_activate_mq_uv = xpc_create_gru_mq_uv(XPC_ACTIVATE_MQ_SIZE_UV, 0, + XPC_ACTIVATE_IRQ_NAME, xpc_handle_activate_IRQ_uv); - if (xpc_activate_mq_uv == NULL) - return -ENOMEM; + if (IS_ERR(xpc_activate_mq_uv)) + return PTR_ERR(xpc_activate_mq_uv); - /* ??? The cpuid argument's value is 0, is that what we want? */ - /* !!! The irq argument's value isn't correct. */ - xpc_notify_mq_uv = xpc_create_gru_mq_uv(XPC_NOTIFY_MQ_SIZE_UV, 0, 0, + xpc_notify_mq_uv = xpc_create_gru_mq_uv(XPC_NOTIFY_MQ_SIZE_UV, 0, + XPC_NOTIFY_IRQ_NAME, xpc_handle_notify_IRQ_uv); - if (xpc_notify_mq_uv == NULL) { - /* !!! The irq argument's value isn't correct. */ - xpc_destroy_gru_mq_uv(xpc_activate_mq_uv, - XPC_ACTIVATE_MQ_SIZE_UV, 0); - return -ENOMEM; + if (IS_ERR(xpc_notify_mq_uv)) { + xpc_destroy_gru_mq_uv(xpc_activate_mq_uv); + return PTR_ERR(xpc_notify_mq_uv); } return 0; @@ -1435,9 +1616,6 @@ xpc_init_uv(void) void xpc_exit_uv(void) { - /* !!! The irq argument's value isn't correct. */ - xpc_destroy_gru_mq_uv(xpc_notify_mq_uv, XPC_NOTIFY_MQ_SIZE_UV, 0); - - /* !!! The irq argument's value isn't correct. */ - xpc_destroy_gru_mq_uv(xpc_activate_mq_uv, XPC_ACTIVATE_MQ_SIZE_UV, 0); + xpc_destroy_gru_mq_uv(xpc_notify_mq_uv); + xpc_destroy_gru_mq_uv(xpc_activate_mq_uv); } diff --git a/drivers/misc/sony-laptop.c b/drivers/misc/sony-laptop.c index 5a97d3a9d745..571b211608d1 100644 --- a/drivers/misc/sony-laptop.c +++ b/drivers/misc/sony-laptop.c @@ -1038,7 +1038,11 @@ static int sony_nc_add(struct acpi_device *device) goto outinput; } - if (ACPI_SUCCESS(acpi_get_handle(sony_nc_acpi_handle, "GBRT", &handle))) { + if (acpi_video_backlight_support()) { + printk(KERN_INFO DRV_PFX "brightness ignored, must be " + "controlled by ACPI video driver\n"); + } else if (ACPI_SUCCESS(acpi_get_handle(sony_nc_acpi_handle, "GBRT", + &handle))) { sony_backlight_device = backlight_device_register("sony", NULL, NULL, &sony_backlight_ops); @@ -1920,7 +1924,6 @@ static int sonypi_misc_fasync(int fd, struct file *filp, int on) static int sonypi_misc_release(struct inode *inode, struct file *file) { - sonypi_misc_fasync(-1, file, 0); atomic_dec(&sonypi_compat.open_count); return 0; } @@ -2315,8 +2318,10 @@ end: */ static int sony_pic_disable(struct acpi_device *device) { - if (ACPI_FAILURE(acpi_evaluate_object(device->handle, - "_DIS", NULL, NULL))) + acpi_status ret = acpi_evaluate_object(device->handle, "_DIS", NULL, + NULL); + + if (ACPI_FAILURE(ret) && ret != AE_NOT_FOUND) return -ENXIO; dprintk("Device disabled\n"); diff --git a/drivers/misc/thinkpad_acpi.c b/drivers/misc/thinkpad_acpi.c index 4db1cf9078d9..899766e16fa8 100644 --- a/drivers/misc/thinkpad_acpi.c +++ b/drivers/misc/thinkpad_acpi.c @@ -4932,16 +4932,25 @@ static int __init brightness_init(struct ibm_init_struct *iibm) */ b = tpacpi_check_std_acpi_brightness_support(); if (b > 0) { - if (thinkpad_id.vendor == PCI_VENDOR_ID_LENOVO) { - printk(TPACPI_NOTICE - "Lenovo BIOS switched to ACPI backlight " - "control mode\n"); - } - if (brightness_enable > 1) { - printk(TPACPI_NOTICE - "standard ACPI backlight interface " - "available, not loading native one...\n"); - return 1; + + if (acpi_video_backlight_support()) { + if (brightness_enable > 1) { + printk(TPACPI_NOTICE + "Standard ACPI backlight interface " + "available, not loading native one.\n"); + return 1; + } else if (brightness_enable == 1) { + printk(TPACPI_NOTICE + "Backlight control force enabled, even if standard " + "ACPI backlight interface is available\n"); + } + } else { + if (brightness_enable > 1) { + printk(TPACPI_NOTICE + "Standard ACPI backlight interface not " + "available, thinkpad_acpi native " + "brightness control enabled\n"); + } } } @@ -5309,6 +5318,7 @@ static enum fan_control_commands fan_control_commands; static u8 fan_control_initial_status; static u8 fan_control_desired_level; +static u8 fan_control_resume_level; static int fan_watchdog_maxinterval; static struct mutex fan_mutex; @@ -5431,8 +5441,8 @@ static int fan_set_level(int level) case TPACPI_FAN_WR_ACPI_FANS: case TPACPI_FAN_WR_TPEC: - if ((level != TP_EC_FAN_AUTO) && - (level != TP_EC_FAN_FULLSPEED) && + if (!(level & TP_EC_FAN_AUTO) && + !(level & TP_EC_FAN_FULLSPEED) && ((level < 0) || (level > 7))) return -EINVAL; @@ -5996,38 +6006,67 @@ static void fan_exit(void) static void fan_suspend(pm_message_t state) { + int rc; + if (!fan_control_allowed) return; /* Store fan status in cache */ - fan_get_status_safe(NULL); + fan_control_resume_level = 0; + rc = fan_get_status_safe(&fan_control_resume_level); + if (rc < 0) + printk(TPACPI_NOTICE + "failed to read fan level for later " + "restore during resume: %d\n", rc); + + /* if it is undefined, don't attempt to restore it. + * KEEP THIS LAST */ if (tp_features.fan_ctrl_status_undef) - fan_control_desired_level = TP_EC_FAN_AUTO; + fan_control_resume_level = 0; } static void fan_resume(void) { - u8 saved_fan_level; u8 current_level = 7; bool do_set = false; + int rc; /* DSDT *always* updates status on resume */ tp_features.fan_ctrl_status_undef = 0; - saved_fan_level = fan_control_desired_level; if (!fan_control_allowed || + !fan_control_resume_level || (fan_get_status_safe(¤t_level) < 0)) return; switch (fan_control_access_mode) { case TPACPI_FAN_WR_ACPI_SFAN: - do_set = (saved_fan_level > current_level); + /* never decrease fan level */ + do_set = (fan_control_resume_level > current_level); break; case TPACPI_FAN_WR_ACPI_FANS: case TPACPI_FAN_WR_TPEC: - do_set = ((saved_fan_level & TP_EC_FAN_FULLSPEED) || - (saved_fan_level == 7 && - !(current_level & TP_EC_FAN_FULLSPEED))); + /* never decrease fan level, scale is: + * TP_EC_FAN_FULLSPEED > 7 >= TP_EC_FAN_AUTO + * + * We expect the firmware to set either 7 or AUTO, but we + * handle FULLSPEED out of paranoia. + * + * So, we can safely only restore FULLSPEED or 7, anything + * else could slow the fan. Restoring AUTO is useless, at + * best that's exactly what the DSDT already set (it is the + * slower it uses). + * + * Always keep in mind that the DSDT *will* have set the + * fans to what the vendor supposes is the best level. We + * muck with it only to speed the fan up. + */ + if (fan_control_resume_level != 7 && + !(fan_control_resume_level & TP_EC_FAN_FULLSPEED)) + return; + else + do_set = !(current_level & TP_EC_FAN_FULLSPEED) && + (current_level != fan_control_resume_level); break; default: return; @@ -6035,8 +6074,11 @@ static void fan_resume(void) if (do_set) { printk(TPACPI_NOTICE "restoring fan level to 0x%02x\n", - saved_fan_level); - fan_set_level_safe(saved_fan_level); + fan_control_resume_level); + rc = fan_set_level_safe(fan_control_resume_level); + if (rc < 0) + printk(TPACPI_NOTICE + "failed to restore fan level: %d\n", rc); } } diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index 0d9b2d6f9ebf..f210a8ee6861 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -216,8 +216,7 @@ int mmc_add_card(struct mmc_card *card) int ret; const char *type; - snprintf(card->dev.bus_id, sizeof(card->dev.bus_id), - "%s:%04x", mmc_hostname(card->host), card->rca); + dev_set_name(&card->dev, "%s:%04x", mmc_hostname(card->host), card->rca); switch (card->type) { case MMC_TYPE_MMC: diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 044d84eeed7c..f7284b905eb3 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -280,7 +280,11 @@ void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card) (card->host->ios.clock / 1000); if (data->flags & MMC_DATA_WRITE) - limit_us = 250000; + /* + * The limit is really 250 ms, but that is + * insufficient for some crappy cards. + */ + limit_us = 300000; else limit_us = 100000; diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 6da80fd4d974..5e945e64ead7 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -73,8 +73,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev) if (err) goto free; - snprintf(host->class_dev.bus_id, BUS_ID_SIZE, - "mmc%d", host->index); + dev_set_name(&host->class_dev, "mmc%d", host->index); host->parent = dev; host->class_dev.parent = dev; @@ -121,7 +120,7 @@ int mmc_add_host(struct mmc_host *host) WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) && !host->ops->enable_sdio_irq); - led_trigger_register_simple(host->class_dev.bus_id, &host->led); + led_trigger_register_simple(dev_name(&host->class_dev), &host->led); err = device_add(&host->class_dev); if (err) diff --git a/drivers/mmc/core/sdio_bus.c b/drivers/mmc/core/sdio_bus.c index 233d0f9b3c4b..46284b527397 100644 --- a/drivers/mmc/core/sdio_bus.c +++ b/drivers/mmc/core/sdio_bus.c @@ -239,8 +239,7 @@ int sdio_add_func(struct sdio_func *func) { int ret; - snprintf(func->dev.bus_id, sizeof(func->dev.bus_id), - "%s:%d", mmc_card_id(func->card), func->num); + dev_set_name(&func->dev, "%s:%d", mmc_card_id(func->card), func->num); ret = device_add(&func->dev); if (ret == 0) diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c index 07faf5412a1f..ad00e1632317 100644 --- a/drivers/mmc/host/mmc_spi.c +++ b/drivers/mmc/host/mmc_spi.c @@ -1348,7 +1348,7 @@ static int mmc_spi_probe(struct spi_device *spi) goto fail_add_host; dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n", - mmc->class_dev.bus_id, + dev_name(&mmc->class_dev), host->dma_dev ? "" : ", no DMA", (host->pdata && host->pdata->get_ro) ? "" : ", no WP", diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 696cf3647ceb..2fadf323c696 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -391,6 +391,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct mmci_host *host = mmc_priv(mmc); + unsigned long flags; WARN_ON(host->mrq != NULL); @@ -402,7 +403,7 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) return; } - spin_lock_irq(&host->lock); + spin_lock_irqsave(&host->lock, flags); host->mrq = mrq; @@ -411,7 +412,7 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) mmci_start_command(host, mrq->cmd, 0); - spin_unlock_irq(&host->lock); + spin_unlock_irqrestore(&host->lock, flags); } static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 30f64b1f2354..4d010a984bed 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1733,7 +1733,7 @@ int sdhci_add_host(struct sdhci_host *host) mmc_add_host(mmc); printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n", - mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id, + mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), (host->flags & SDHCI_USE_ADMA)?"A":"", (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); diff --git a/drivers/mmc/host/tifm_sd.c b/drivers/mmc/host/tifm_sd.c index 13844843e8de..82554ddec6b3 100644 --- a/drivers/mmc/host/tifm_sd.c +++ b/drivers/mmc/host/tifm_sd.c @@ -632,7 +632,7 @@ static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq) if (host->req) { printk(KERN_ERR "%s : unfinished request detected\n", - sock->dev.bus_id); + dev_name(&sock->dev)); mrq->cmd->error = -ETIMEDOUT; goto err_out; } @@ -672,7 +672,7 @@ static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE)) { printk(KERN_ERR "%s : scatterlist map failed\n", - sock->dev.bus_id); + dev_name(&sock->dev)); mrq->cmd->error = -ENOMEM; goto err_out; } @@ -684,7 +684,7 @@ static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq) : PCI_DMA_FROMDEVICE); if (host->sg_len < 1) { printk(KERN_ERR "%s : scatterlist map failed\n", - sock->dev.bus_id); + dev_name(&sock->dev)); tifm_unmap_sg(sock, &host->bounce_buf, 1, r_data->flags & MMC_DATA_WRITE ? PCI_DMA_TODEVICE @@ -748,7 +748,7 @@ static void tifm_sd_end_cmd(unsigned long data) if (!mrq) { printk(KERN_ERR " %s : no request to complete?\n", - sock->dev.bus_id); + dev_name(&sock->dev)); spin_unlock_irqrestore(&sock->lock, flags); return; } @@ -789,7 +789,7 @@ static void tifm_sd_abort(unsigned long data) printk(KERN_ERR "%s : card failed to respond for a long period of time " "(%x, %x)\n", - host->dev->dev.bus_id, host->req->cmd->opcode, host->cmd_flags); + dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags); tifm_eject(host->dev); } @@ -906,7 +906,7 @@ static int tifm_sd_initialize_host(struct tifm_sd *host) if (rc) { printk(KERN_ERR "%s : controller failed to reset\n", - sock->dev.bus_id); + dev_name(&sock->dev)); return -ENODEV; } @@ -933,7 +933,7 @@ static int tifm_sd_initialize_host(struct tifm_sd *host) if (rc) { printk(KERN_ERR "%s : card not ready - probe failed on initialization\n", - sock->dev.bus_id); + dev_name(&sock->dev)); return -ENODEV; } @@ -954,7 +954,7 @@ static int tifm_sd_probe(struct tifm_dev *sock) if (!(TIFM_SOCK_STATE_OCCUPIED & readl(sock->addr + SOCK_PRESENT_STATE))) { printk(KERN_WARNING "%s : card gone, unexpectedly\n", - sock->dev.bus_id); + dev_name(&sock->dev)); return rc; } diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c index 3e6f5d8609e8..d74ec46aa032 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c @@ -406,19 +406,6 @@ struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) /* Set the default CFI lock/unlock addresses */ cfi->addr_unlock1 = 0x555; cfi->addr_unlock2 = 0x2aa; - /* Modify the unlock address if we are in compatibility mode */ - if ( /* x16 in x8 mode */ - ((cfi->device_type == CFI_DEVICETYPE_X8) && - (cfi->cfiq->InterfaceDesc == - CFI_INTERFACE_X8_BY_X16_ASYNC)) || - /* x32 in x16 mode */ - ((cfi->device_type == CFI_DEVICETYPE_X16) && - (cfi->cfiq->InterfaceDesc == - CFI_INTERFACE_X16_BY_X32_ASYNC))) - { - cfi->addr_unlock1 = 0xaaa; - cfi->addr_unlock2 = 0x555; - } } /* CFI mode */ else if (cfi->cfi_mode == CFI_MODE_JEDEC) { diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c index f84ab6182148..2f3f2f719ba4 100644 --- a/drivers/mtd/chips/jedec_probe.c +++ b/drivers/mtd/chips/jedec_probe.c @@ -1808,9 +1808,7 @@ static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, * several first banks can contain 0x7f instead of actual ID */ do { - uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), - cfi_interleave(cfi), - cfi->device_type); + uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); mask = (1 << (cfi->device_type * 8)) - 1; result = map_read(map, base + ofs); bank++; @@ -1824,7 +1822,7 @@ static inline u32 jedec_read_id(struct map_info *map, uint32_t base, { map_word result; unsigned long mask; - u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type); + u32 ofs = cfi_build_cmd_addr(1, map, cfi); mask = (1 << (cfi->device_type * 8)) -1; result = map_read(map, base + ofs); return result.x[0] & mask; @@ -2067,8 +2065,8 @@ static int jedec_probe_chip(struct map_info *map, __u32 base, } /* Ensure the unlock addresses we try stay inside the map */ - probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type); - probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type); + probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi); + probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi); if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) goto retry; diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 76a76751da36..6659b2275c0c 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -37,9 +37,9 @@ #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define OPCODE_BE 0xc7 /* Erase whole flash block */ +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ #define OPCODE_RDID 0x9f /* Read JEDEC ID */ @@ -167,7 +167,7 @@ static int wait_till_ready(struct m25p *flash) * * Returns 0 if successful, non-zero otherwise. */ -static int erase_block(struct m25p *flash) +static int erase_chip(struct m25p *flash) { DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB\n", flash->spi->dev.bus_id, __func__, @@ -181,7 +181,7 @@ static int erase_block(struct m25p *flash) write_enable(flash); /* Set up command buffer. */ - flash->command[0] = OPCODE_BE; + flash->command[0] = OPCODE_CHIP_ERASE; spi_write(flash->spi, flash->command, 1); @@ -250,15 +250,18 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) mutex_lock(&flash->lock); - /* REVISIT in some cases we could speed up erasing large regions - * by using OPCODE_SE instead of OPCODE_BE_4K - */ - - /* now erase those sectors */ - if (len == flash->mtd.size && erase_block(flash)) { + /* whole-chip erase? */ + if (len == flash->mtd.size && erase_chip(flash)) { instr->state = MTD_ERASE_FAILED; mutex_unlock(&flash->lock); return -EIO; + + /* REVISIT in some cases we could speed up erasing large regions + * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up + * to use "small sector erase", but that's not always optimal. + */ + + /* "sector"-at-a-time erase */ } else { while (len) { if (erase_sector(flash, addr)) { @@ -574,10 +577,11 @@ static struct flash_info *__devinit jedec_probe(struct spi_device *spi) for (tmp = 0, info = m25p_data; tmp < ARRAY_SIZE(m25p_data); tmp++, info++) { - if (info->jedec_id == jedec) - if (ext_jedec != 0 && info->ext_id != ext_jedec) + if (info->jedec_id == jedec) { + if (info->ext_id != 0 && info->ext_id != ext_jedec) continue; return info; + } } dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); return NULL; diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c index e5059aa3c724..8d92d8db9a98 100644 --- a/drivers/mtd/maps/cdb89712.c +++ b/drivers/mtd/maps/cdb89712.c @@ -14,7 +14,18 @@ #include #include - +/* dynamic ioremap() areas */ +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x800000 +#define FLASH_WIDTH 4 + +#define SRAM_START 0x60000000 +#define SRAM_SIZE 0xc000 +#define SRAM_WIDTH 4 + +#define BOOTROM_START 0x70000000 +#define BOOTROM_SIZE 0x80 +#define BOOTROM_WIDTH 4 static struct mtd_info *flash_mtd; diff --git a/drivers/mtd/maps/h720x-flash.c b/drivers/mtd/maps/h720x-flash.c index 35fef655ccc4..3b959fad1c4e 100644 --- a/drivers/mtd/maps/h720x-flash.c +++ b/drivers/mtd/maps/h720x-flash.c @@ -24,8 +24,8 @@ static struct mtd_info *mymtd; static struct map_info h720x_map = { .name = "H720X", .bankwidth = 4, - .size = FLASH_SIZE, - .phys = FLASH_PHYS, + .size = H720X_FLASH_SIZE, + .phys = H720X_FLASH_PHYS, }; static struct mtd_partition h720x_partitions[] = { @@ -70,7 +70,7 @@ int __init h720x_mtd_init(void) char *part_type = NULL; - h720x_map.virt = ioremap(FLASH_PHYS, FLASH_SIZE); + h720x_map.virt = ioremap(h720x_map.phys, h720x_map.size); if (!h720x_map.virt) { printk(KERN_ERR "H720x-MTD: ioremap failed\n"); diff --git a/drivers/mtd/maps/physmap.c b/drivers/mtd/maps/physmap.c index 42d844f8f6bf..dfbf3f270cea 100644 --- a/drivers/mtd/maps/physmap.c +++ b/drivers/mtd/maps/physmap.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #define MAX_RESOURCES 4 @@ -27,7 +27,6 @@ struct physmap_flash_info { struct mtd_info *mtd[MAX_RESOURCES]; struct mtd_info *cmtd; struct map_info map[MAX_RESOURCES]; - struct resource *res; #ifdef CONFIG_MTD_PARTITIONS int nr_parts; struct mtd_partition *parts; @@ -70,16 +69,7 @@ static int physmap_flash_remove(struct platform_device *dev) #endif map_destroy(info->mtd[i]); } - - if (info->map[i].virt != NULL) - iounmap(info->map[i].virt); - } - - if (info->res != NULL) { - release_resource(info->res); - kfree(info->res); } - return 0; } @@ -101,7 +91,8 @@ static int physmap_flash_probe(struct platform_device *dev) if (physmap_data == NULL) return -ENODEV; - info = kzalloc(sizeof(struct physmap_flash_info), GFP_KERNEL); + info = devm_kzalloc(&dev->dev, sizeof(struct physmap_flash_info), + GFP_KERNEL); if (info == NULL) { err = -ENOMEM; goto err_out; @@ -114,10 +105,10 @@ static int physmap_flash_probe(struct platform_device *dev) (unsigned long long)(dev->resource[i].end - dev->resource[i].start + 1), (unsigned long long)dev->resource[i].start); - info->res = request_mem_region(dev->resource[i].start, - dev->resource[i].end - dev->resource[i].start + 1, - dev->dev.bus_id); - if (info->res == NULL) { + if (!devm_request_mem_region(&dev->dev, + dev->resource[i].start, + dev->resource[i].end - dev->resource[i].start + 1, + dev->dev.bus_id)) { dev_err(&dev->dev, "Could not reserve memory region\n"); err = -ENOMEM; goto err_out; @@ -129,7 +120,8 @@ static int physmap_flash_probe(struct platform_device *dev) info->map[i].bankwidth = physmap_data->width; info->map[i].set_vpp = physmap_data->set_vpp; - info->map[i].virt = ioremap(info->map[i].phys, info->map[i].size); + info->map[i].virt = devm_ioremap(&dev->dev, info->map[i].phys, + info->map[i].size); if (info->map[i].virt == NULL) { dev_err(&dev->dev, "Failed to ioremap flash region\n"); err = EIO; diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 024e3fffd4bb..a83192f80eba 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -163,9 +163,11 @@ static int __devinit fun_chip_init(struct fsl_upm_nand *fun, ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0); #ifdef CONFIG_MTD_OF_PARTS - if (ret == 0) - ret = of_mtd_parse_partitions(fun->dev, &fun->mtd, - flash_np, &fun->parts); + if (ret == 0) { + ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts); + if (ret < 0) + goto err; + } #endif if (ret > 0) ret = add_mtd_partitions(&fun->mtd, fun->parts, ret); diff --git a/drivers/mtd/nand/pasemi_nand.c b/drivers/mtd/nand/pasemi_nand.c index 75c899039023..9bd6c9ac8443 100644 --- a/drivers/mtd/nand/pasemi_nand.c +++ b/drivers/mtd/nand/pasemi_nand.c @@ -141,6 +141,7 @@ static int __devinit pasemi_nand_probe(struct of_device *ofdev, } lpcctl = pci_resource_start(pdev, 0); + pci_dev_put(pdev); if (!request_region(lpcctl, 4, driver_name)) { err = -EBUSY; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index c0fa9c9edf08..15f0a26730ae 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -269,6 +269,7 @@ static struct pxa3xx_nand_timing stm2GbX16_timing = { static struct pxa3xx_nand_flash stm2GbX16 = { .timing = &stm2GbX16_timing, + .cmdset = &largepage_cmdset, .page_per_block = 64, .page_size = 2048, .flash_width = 16, diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c index 8387e05daae2..a7e4d985f5ef 100644 --- a/drivers/mtd/onenand/omap2.c +++ b/drivers/mtd/onenand/omap2.c @@ -32,20 +32,18 @@ #include #include #include +#include +#include -#include #include -#include -#include -#include -#include -#include +#include +#include +#include +#include -#include -#include -#include +#include -#include +#include #define DRIVER_NAME "omap2-onenand" diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index e04bcf1dff87..d8966bae0e0b 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -1022,7 +1022,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, } /* - * OK, now the LEB is locked and we can safely start moving iy. Since + * OK, now the LEB is locked and we can safely start moving it. Since * this function utilizes thie @ubi->peb1_buf buffer which is shared * with some other functions, so lock the buffer by taking the * @ubi->buf_mutex. diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c index 4f2daa5bbecf..41d47e1cf15c 100644 --- a/drivers/mtd/ubi/scan.c +++ b/drivers/mtd/ubi/scan.c @@ -320,7 +320,7 @@ static int compare_lebs(struct ubi_device *ubi, const struct ubi_scan_leb *seb, } err = ubi_io_read_data(ubi, buf, pnum, 0, len); - if (err && err != UBI_IO_BITFLIPS) + if (err && err != UBI_IO_BITFLIPS && err != -EBADMSG) goto out_free_buf; data_crc = be32_to_cpu(vid_hdr->data_crc); diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 05d70937b543..dcb6dac1dc54 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -1396,7 +1396,8 @@ int ubi_thread(void *u) ubi_msg("%s: %d consecutive failures", ubi->bgt_name, WL_MAX_FAILURES); ubi_ro_mode(ubi); - break; + ubi->thread_enabled = 0; + continue; } } else failures = 0; diff --git a/drivers/net/3c509.c b/drivers/net/3c509.c index 3a7bc524af33..c7a4f3bcc2bc 100644 --- a/drivers/net/3c509.c +++ b/drivers/net/3c509.c @@ -94,7 +94,7 @@ #include #include -static char version[] __initdata = DRV_NAME ".c:" DRV_VERSION " " DRV_RELDATE " becker@scyld.com\n"; +static char version[] __devinitdata = DRV_NAME ".c:" DRV_VERSION " " DRV_RELDATE " becker@scyld.com\n"; #ifdef EL3_DEBUG static int el3_debug = EL3_DEBUG; @@ -186,7 +186,7 @@ static int max_interrupt_work = 10; static int nopnp; #endif -static int __init el3_common_init(struct net_device *dev); +static int __devinit el3_common_init(struct net_device *dev); static void el3_common_remove(struct net_device *dev); static ushort id_read_eeprom(int index); static ushort read_eeprom(int ioaddr, int index); @@ -537,7 +537,7 @@ static struct mca_driver el3_mca_driver = { static int mca_registered; #endif /* CONFIG_MCA */ -static int __init el3_common_init(struct net_device *dev) +static int __devinit el3_common_init(struct net_device *dev) { struct el3_private *lp = netdev_priv(dev); int err; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f749b40f954e..231eeaf1d552 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1825,9 +1825,10 @@ config FEC2 config FEC_MPC52xx tristate "MPC52xx FEC driver" - depends on PPC_MPC52xx && PPC_BESTCOMM_FEC + depends on PPC_MPC52xx && PPC_BESTCOMM select CRC32 select PHYLIB + select PPC_BESTCOMM_FEC ---help--- This option enables support for the MPC5200's on-chip Fast Ethernet Controller @@ -2010,9 +2011,13 @@ config IGB_LRO If in doubt, say N. config IGB_DCA - bool "Enable DCA" + bool "Direct Cache Access (DCA) Support" default y depends on IGB && DCA && !(IGB=y && DCA=m) + ---help--- + Say Y here if you want to use Direct Cache Access (DCA) in the + driver. DCA is a method for warming the CPU cache before data + is used, with the intent of lessening the impact of cache misses. source "drivers/net/ixp2000/Kconfig" @@ -2437,9 +2442,13 @@ config IXGBE will be called ixgbe. config IXGBE_DCA - bool + bool "Direct Cache Access (DCA) Support" default y depends on IXGBE && DCA && !(IXGBE=y && DCA=m) + ---help--- + Say Y here if you want to use Direct Cache Access (DCA) in the + driver. DCA is a method for warming the CPU cache before data + is used, with the intent of lessening the impact of cache misses. config IXGB tristate "Intel(R) PRO/10GbE support" @@ -2489,9 +2498,13 @@ config MYRI10GE will be called myri10ge. config MYRI10GE_DCA - bool + bool "Direct Cache Access (DCA) Support" default y depends on MYRI10GE && DCA && !(MYRI10GE=y && DCA=m) + ---help--- + Say Y here if you want to use Direct Cache Access (DCA) in the + driver. DCA is a method for warming the CPU cache before data + is used, with the intent of lessening the impact of cache misses. config NETXEN_NIC tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f19acf8b9220..017383ad5ec6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -114,7 +114,7 @@ obj-$(CONFIG_EL2) += 3c503.o 8390p.o obj-$(CONFIG_NE2000) += ne.o 8390p.o obj-$(CONFIG_NE2_MCA) += ne2.o 8390p.o obj-$(CONFIG_HPLAN) += hp.o 8390p.o -obj-$(CONFIG_HPLAN_PLUS) += hp-plus.o 8390.o +obj-$(CONFIG_HPLAN_PLUS) += hp-plus.o 8390p.o obj-$(CONFIG_ULTRA) += smc-ultra.o 8390.o obj-$(CONFIG_ULTRAMCA) += smc-mca.o 8390.o obj-$(CONFIG_ULTRA32) += smc-ultra32.o 8390.o diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c index c54967f7942a..07a6697e3635 100644 --- a/drivers/net/amd8111e.c +++ b/drivers/net/amd8111e.c @@ -644,10 +644,6 @@ This function frees the transmiter and receiver descriptor rings. */ static void amd8111e_free_ring(struct amd8111e_priv* lp) { - - /* Free transmit and receive skbs */ - amd8111e_free_skbs(lp->amd8111e_net_dev); - /* Free transmit and receive descriptor rings */ if(lp->rx_ring){ pci_free_consistent(lp->pci_dev, @@ -833,12 +829,14 @@ static int amd8111e_rx_poll(struct napi_struct *napi, int budget) } while(intr0 & RINT0); - /* Receive descriptor is empty now */ - spin_lock_irqsave(&lp->lock, flags); - __netif_rx_complete(dev, napi); - writel(VAL0|RINTEN0, mmio + INTEN0); - writel(VAL2 | RDMD0, mmio + CMD0); - spin_unlock_irqrestore(&lp->lock, flags); + if (rx_pkt_limit > 0) { + /* Receive descriptor is empty now */ + spin_lock_irqsave(&lp->lock, flags); + __netif_rx_complete(dev, napi); + writel(VAL0|RINTEN0, mmio + INTEN0); + writel(VAL2 | RDMD0, mmio + CMD0); + spin_unlock_irqrestore(&lp->lock, flags); + } rx_not_empty: return num_rx_pkt; @@ -1231,7 +1229,9 @@ static int amd8111e_close(struct net_device * dev) amd8111e_disable_interrupt(lp); amd8111e_stop_chip(lp); - amd8111e_free_ring(lp); + + /* Free transmit and receive skbs */ + amd8111e_free_skbs(lp->amd8111e_net_dev); netif_carrier_off(lp->amd8111e_net_dev); @@ -1241,6 +1241,7 @@ static int amd8111e_close(struct net_device * dev) spin_unlock_irq(&lp->lock); free_irq(dev->irq, dev); + amd8111e_free_ring(lp); /* Update the statistics before closing */ amd8111e_get_stats(dev); diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c index 0fa53464efb2..6f431a887e7e 100644 --- a/drivers/net/arm/at91_ether.c +++ b/drivers/net/arm/at91_ether.c @@ -1080,7 +1080,8 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add init_timer(&lp->check_timer); lp->check_timer.data = (unsigned long)dev; lp->check_timer.function = at91ether_check_link; - } + } else if (lp->board_data.phy_irq_pin >= 32) + gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); /* Display ethernet banner */ printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%s)\n", @@ -1167,6 +1168,9 @@ static int __devexit at91ether_remove(struct platform_device *pdev) struct net_device *dev = platform_get_drvdata(pdev); struct at91_private *lp = netdev_priv(dev); + if (lp->board_data.phy_irq_pin >= 32) + gpio_free(lp->board_data.phy_irq_pin); + unregister_netdev(dev); free_irq(dev->irq, dev); dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); diff --git a/drivers/net/atl1e/atl1e.h b/drivers/net/atl1e/atl1e.h index b645fa0f3f64..c49550d507a0 100644 --- a/drivers/net/atl1e/atl1e.h +++ b/drivers/net/atl1e/atl1e.h @@ -46,7 +46,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/atl1e/atl1e_hw.c b/drivers/net/atl1e/atl1e_hw.c index 8cbc1b59bd62..4a7700620119 100644 --- a/drivers/net/atl1e/atl1e_hw.c +++ b/drivers/net/atl1e/atl1e_hw.c @@ -163,9 +163,6 @@ int atl1e_read_mac_addr(struct atl1e_hw *hw) * atl1e_hash_mc_addr * purpose * set hash value for a multicast address - * hash calcu processing : - * 1. calcu 32bit CRC for multicast address - * 2. reverse crc with MSB to LSB */ u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr) { @@ -174,7 +171,6 @@ u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr) int i; crc32 = ether_crc_le(6, mc_addr); - crc32 = ~crc32; for (i = 0; i < 32; i++) value |= (((crc32 >> i) & 1) << (31 - i)); diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c index 3cf59a7f5a1c..aef403d299ee 100644 --- a/drivers/net/atlx/atl1.c +++ b/drivers/net/atlx/atl1.c @@ -2310,7 +2310,8 @@ static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, if (tpd != ptpd) memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); tpd->buffer_addr = cpu_to_le64(buffer_info->dma); - tpd->word2 = (cpu_to_le16(buffer_info->length) & + tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); + tpd->word2 |= (cpu_to_le16(buffer_info->length) & TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; /* @@ -2409,8 +2410,8 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev) vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | ((vlan_tag >> 9) & 0x8); ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; - ptpd->word3 |= (vlan_tag & TPD_VL_TAGGED_MASK) << - TPD_VL_TAGGED_SHIFT; + ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << + TPD_VLANTAG_SHIFT; } tso = atl1_tso(adapter, skb, ptpd); @@ -3403,14 +3404,8 @@ static void atl1_get_wol(struct net_device *netdev, { struct atl1_adapter *adapter = netdev_priv(netdev); - wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC; + wol->supported = WAKE_MAGIC; wol->wolopts = 0; - if (adapter->wol & ATLX_WUFC_EX) - wol->wolopts |= WAKE_UCAST; - if (adapter->wol & ATLX_WUFC_MC) - wol->wolopts |= WAKE_MCAST; - if (adapter->wol & ATLX_WUFC_BC) - wol->wolopts |= WAKE_BCAST; if (adapter->wol & ATLX_WUFC_MAG) wol->wolopts |= WAKE_MAGIC; return; @@ -3421,15 +3416,10 @@ static int atl1_set_wol(struct net_device *netdev, { struct atl1_adapter *adapter = netdev_priv(netdev); - if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) + if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | + WAKE_ARP | WAKE_MAGICSECURE)) return -EOPNOTSUPP; adapter->wol = 0; - if (wol->wolopts & WAKE_UCAST) - adapter->wol |= ATLX_WUFC_EX; - if (wol->wolopts & WAKE_MCAST) - adapter->wol |= ATLX_WUFC_MC; - if (wol->wolopts & WAKE_BCAST) - adapter->wol |= ATLX_WUFC_BC; if (wol->wolopts & WAKE_MAGIC) adapter->wol |= ATLX_WUFC_MAG; return 0; diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h index a5015b14a429..ffa73fc8d95e 100644 --- a/drivers/net/atlx/atl1.h +++ b/drivers/net/atlx/atl1.h @@ -504,7 +504,7 @@ struct rx_free_desc { #define TPD_PKTNT_MASK 0x0001 #define TPD_PKTINT_SHIFT 15 #define TPD_VLANTAG_MASK 0xFFFF -#define TPD_VLAN_SHIFT 16 +#define TPD_VLANTAG_SHIFT 16 /* tpd word 3 bits 0:13 */ #define TPD_EOP_MASK 0x0001 diff --git a/drivers/net/atlx/atl2.c b/drivers/net/atlx/atl2.c index f5bdc92c1a65..8571e8c0bc67 100644 --- a/drivers/net/atlx/atl2.c +++ b/drivers/net/atlx/atl2.c @@ -1690,9 +1690,11 @@ static int atl2_resume(struct pci_dev *pdev) ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); - err = atl2_request_irq(adapter); - if (netif_running(netdev) && err) - return err; + if (netif_running(netdev)) { + err = atl2_request_irq(adapter); + if (err) + return err; + } atl2_reset_hw(&adapter->hw); diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 430d430bce29..9e8222f9e90e 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -543,9 +543,9 @@ bnx2_free_rx_mem(struct bnx2 *bp) for (j = 0; j < bp->rx_max_pg_ring; j++) { if (rxr->rx_pg_desc_ring[j]) pci_free_consistent(bp->pdev, RXBD_RING_SIZE, - rxr->rx_pg_desc_ring[i], - rxr->rx_pg_desc_mapping[i]); - rxr->rx_pg_desc_ring[i] = NULL; + rxr->rx_pg_desc_ring[j], + rxr->rx_pg_desc_mapping[j]); + rxr->rx_pg_desc_ring[j] = NULL; } if (rxr->rx_pg_ring) vfree(rxr->rx_pg_ring); @@ -3144,6 +3144,28 @@ bnx2_has_work(struct bnx2_napi *bnapi) return 0; } +static void +bnx2_chk_missed_msi(struct bnx2 *bp) +{ + struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; + u32 msi_ctrl; + + if (bnx2_has_work(bnapi)) { + msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL); + if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) + return; + + if (bnapi->last_status_idx == bp->idle_chk_status_idx) { + REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & + ~BNX2_PCICFG_MSI_CONTROL_ENABLE); + REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); + bnx2_msi(bp->irq_tbl[0].vector, bnapi); + } + } + + bp->idle_chk_status_idx = bnapi->last_status_idx; +} + static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) { struct status_block *sblk = bnapi->status_blk.msi; @@ -3218,14 +3240,15 @@ static int bnx2_poll(struct napi_struct *napi, int budget) work_done = bnx2_poll_work(bp, bnapi, work_done, budget); - if (unlikely(work_done >= budget)) - break; - /* bnapi->last_status_idx is used below to tell the hw how * much work has been processed, so we must read it before * checking for more work. */ bnapi->last_status_idx = sblk->status_idx; + + if (unlikely(work_done >= budget)) + break; + rmb(); if (likely(!bnx2_has_work(bnapi))) { netif_rx_complete(bp->dev, napi); @@ -4570,6 +4593,8 @@ bnx2_init_chip(struct bnx2 *bp) for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) bp->bnx2_napi[i].last_status_idx = 0; + bp->idle_chk_status_idx = 0xffff; + bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; /* Set up how to generate a link change interrupt. */ @@ -5718,6 +5743,10 @@ bnx2_timer(unsigned long data) if (atomic_read(&bp->intr_sem) != 0) goto bnx2_restart_timer; + if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == + BNX2_FLAG_USING_MSI) + bnx2_chk_missed_msi(bp); + bnx2_send_heart_beat(bp); bp->stats_blk->stat_FwRxDrop = @@ -7204,10 +7233,13 @@ static void poll_bnx2(struct net_device *dev) { struct bnx2 *bp = netdev_priv(dev); + int i; - disable_irq(bp->pdev->irq); - bnx2_interrupt(bp->pdev->irq, dev); - enable_irq(bp->pdev->irq); + for (i = 0; i < bp->irq_nvecs; i++) { + disable_irq(bp->irq_tbl[i].vector); + bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]); + enable_irq(bp->irq_tbl[i].vector); + } } #endif diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 617d95340160..0b032c3c7b61 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -378,6 +378,9 @@ struct l2_fhdr { * pci_config_l definition * offset: 0000 */ +#define BNX2_PCICFG_MSI_CONTROL 0x00000058 +#define BNX2_PCICFG_MSI_CONTROL_ENABLE (1L<<16) + #define BNX2_PCICFG_MISC_CONFIG 0x00000068 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) @@ -6863,6 +6866,9 @@ struct bnx2 { u8 num_tx_rings; u8 num_rx_rings; + + u32 idle_chk_status_idx; + }; #define REG_RD(bp, offset) \ diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 130927cfc75b..a6c0b3abba29 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h @@ -564,14 +564,15 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { static void bnx2x_init_pxp(struct bnx2x *bp) { + u16 devctl; int r_order, w_order; u32 val, i; pci_read_config_word(bp->pdev, - bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val); - DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val); - w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5); - r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12); + bp->pcie_cap + PCI_EXP_DEVCTL, &devctl); + DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); + w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); + r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); if (r_order > MAX_RD_ORD) { DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index fce745148ff9..600210d7eff9 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c @@ -59,8 +59,8 @@ #include "bnx2x.h" #include "bnx2x_init.h" -#define DRV_MODULE_VERSION "1.45.22" -#define DRV_MODULE_RELDATE "2008/09/09" +#define DRV_MODULE_VERSION "1.45.23" +#define DRV_MODULE_RELDATE "2008/11/03" #define BNX2X_BC_VER 0x040200 /* Time in jiffies before concluding the transmitter is hung */ @@ -6481,6 +6481,7 @@ load_int_disable: bnx2x_free_irq(bp); load_error: bnx2x_free_mem(bp); + bp->port.pmf = 0; /* TBD we really need to reset the chip if we want to recover from this */ @@ -6791,6 +6792,7 @@ unload_error: /* Report UNLOAD_DONE to MCP */ if (!BP_NOMCP(bp)) bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); + bp->port.pmf = 0; /* Free SKBs, SGEs, TPA pool and driver internals */ bnx2x_free_skbs(bp); @@ -10204,8 +10206,6 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, return -ENOMEM; } - netif_carrier_off(dev); - bp = netdev_priv(dev); bp->msglevel = debug; @@ -10229,6 +10229,8 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, goto init_one_exit; } + netif_carrier_off(dev); + bp->common.name = board_info[ent->driver_data].name; printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx," " IRQ %d, ", dev->name, bp->common.name, diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c index ade5f3f6693b..87437c788476 100644 --- a/drivers/net/bonding/bond_alb.c +++ b/drivers/net/bonding/bond_alb.c @@ -169,11 +169,14 @@ static void tlb_clear_slave(struct bonding *bond, struct slave *slave, int save_ /* clear slave from tx_hashtbl */ tx_hash_table = BOND_ALB_INFO(bond).tx_hashtbl; - index = SLAVE_TLB_INFO(slave).head; - while (index != TLB_NULL_INDEX) { - u32 next_index = tx_hash_table[index].next; - tlb_init_table_entry(&tx_hash_table[index], save_load); - index = next_index; + /* skip this if we've already freed the tx hash table */ + if (tx_hash_table) { + index = SLAVE_TLB_INFO(slave).head; + while (index != TLB_NULL_INDEX) { + u32 next_index = tx_hash_table[index].next; + tlb_init_table_entry(&tx_hash_table[index], save_load); + index = next_index; + } } tlb_init_slave(slave); diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 832739f38db4..a3efba59eee9 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -1979,6 +1979,20 @@ void bond_destroy(struct bonding *bond) unregister_netdevice(bond->dev); } +static void bond_destructor(struct net_device *bond_dev) +{ + struct bonding *bond = bond_dev->priv; + + if (bond->wq) + destroy_workqueue(bond->wq); + + netif_addr_lock_bh(bond_dev); + bond_mc_list_destroy(bond); + netif_addr_unlock_bh(bond_dev); + + free_netdev(bond_dev); +} + /* * First release a slave and than destroy the bond if no more slaves iare left. * Must be under rtnl_lock when this function is called. @@ -2376,6 +2390,9 @@ static void bond_miimon_commit(struct bonding *bond) continue; case BOND_LINK_DOWN: + if (slave->link_failure_count < UINT_MAX) + slave->link_failure_count++; + slave->link = BOND_LINK_DOWN; if (bond->params.mode == BOND_MODE_ACTIVEBACKUP || @@ -4550,7 +4567,7 @@ static int bond_init(struct net_device *bond_dev, struct bond_params *params) bond_set_mode_ops(bond, bond->params.mode); - bond_dev->destructor = free_netdev; + bond_dev->destructor = bond_destructor; /* Initialize the device options */ bond_dev->tx_queue_len = 0; @@ -4589,20 +4606,6 @@ static int bond_init(struct net_device *bond_dev, struct bond_params *params) return 0; } -/* De-initialize device specific data. - * Caller must hold rtnl_lock. - */ -static void bond_deinit(struct net_device *bond_dev) -{ - struct bonding *bond = bond_dev->priv; - - list_del(&bond->bond_list); - -#ifdef CONFIG_PROC_FS - bond_remove_proc_entry(bond); -#endif -} - static void bond_work_cancel_all(struct bonding *bond) { write_lock_bh(&bond->lock); @@ -4624,6 +4627,22 @@ static void bond_work_cancel_all(struct bonding *bond) cancel_delayed_work(&bond->ad_work); } +/* De-initialize device specific data. + * Caller must hold rtnl_lock. + */ +static void bond_deinit(struct net_device *bond_dev) +{ + struct bonding *bond = bond_dev->priv; + + list_del(&bond->bond_list); + + bond_work_cancel_all(bond); + +#ifdef CONFIG_PROC_FS + bond_remove_proc_entry(bond); +#endif +} + /* Unregister and free all bond devices. * Caller must hold rtnl_lock. */ @@ -4635,9 +4654,6 @@ static void bond_free_all(void) struct net_device *bond_dev = bond->dev; bond_work_cancel_all(bond); - netif_addr_lock_bh(bond_dev); - bond_mc_list_destroy(bond); - netif_addr_unlock_bh(bond_dev); /* Release the bonded slaves */ bond_release_all(bond_dev); bond_destroy(bond); diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c index d6c7d2aa761b..7092df50ff78 100644 --- a/drivers/net/chelsio/sge.c +++ b/drivers/net/chelsio/sge.c @@ -1035,10 +1035,6 @@ MODULE_PARM_DESC(copybreak, "Receive copy threshold"); * @pdev: the PCI device that received the packet * @fl: the SGE free list holding the packet * @len: the actual packet length, excluding any SGE padding - * @dma_pad: padding at beginning of buffer left by SGE DMA - * @skb_pad: padding to be used if the packet is copied - * @copy_thres: length threshold under which a packet should be copied - * @drop_thres: # of remaining buffers before we start dropping packets * * Get the next packet from a free list and complete setup of the * sk_buff. If the packet is small we make a copy and recycle the diff --git a/drivers/net/cris/eth_v10.c b/drivers/net/cris/eth_v10.c index 65d0a9103297..7e8a63106bdf 100644 --- a/drivers/net/cris/eth_v10.c +++ b/drivers/net/cris/eth_v10.c @@ -32,14 +32,14 @@ #include #include -#include /* DMA and register descriptions */ +#include /* DMA and register descriptions */ #include /* CRIS_LED_* I/O functions */ #include #include #include #include #include -#include +#include //#define ETHDEBUG #define D(x) diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c index 1ace41a13ac3..2c341f83d327 100644 --- a/drivers/net/cxgb3/cxgb3_main.c +++ b/drivers/net/cxgb3/cxgb3_main.c @@ -1307,8 +1307,10 @@ static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) u32 fw_vers = 0; u32 tp_vers = 0; + spin_lock(&adapter->stats_lock); t3_get_fw_version(adapter, &fw_vers); t3_get_tp_version(adapter, &tp_vers); + spin_unlock(&adapter->stats_lock); strcpy(info->driver, DRV_NAME); strcpy(info->version, DRV_VERSION); @@ -2699,7 +2701,7 @@ static void set_nqsets(struct adapter *adap) int hwports = adap->params.nports; int nqsets = SGE_QSETS; - if (adap->params.rev > 0) { + if (adap->params.rev > 0 && adap->flags & USING_MSIX) { if (hwports == 2 && (hwports * nqsets > SGE_QSETS || num_cpus >= nqsets / hwports)) diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c index 968f64be3743..9a0898b0dbce 100644 --- a/drivers/net/cxgb3/t3_hw.c +++ b/drivers/net/cxgb3/t3_hw.c @@ -572,7 +572,7 @@ struct t3_vpd { u32 pad; /* for multiple-of-4 sizing and alignment */ }; -#define EEPROM_MAX_POLL 4 +#define EEPROM_MAX_POLL 40 #define EEPROM_STAT_ADDR 0x4000 #define VPD_BASE 0xc00 @@ -3690,6 +3690,12 @@ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, ; pti = &port_types[adapter->params.vpd.port_type[j]]; + if (!pti->phy_prep) { + CH_ALERT(adapter, "Invalid port type index %d\n", + adapter->params.vpd.port_type[j]); + return -EINVAL; + } + ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j, ai->mdio_ops); if (ret) diff --git a/drivers/net/e100.c b/drivers/net/e100.c index 3d69fae781cf..e8bfcce6b319 100644 --- a/drivers/net/e100.c +++ b/drivers/net/e100.c @@ -166,7 +166,7 @@ #define DRV_NAME "e100" #define DRV_EXT "-NAPI" -#define DRV_VERSION "3.5.23-k4"DRV_EXT +#define DRV_VERSION "3.5.23-k6"DRV_EXT #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation" #define PFX DRV_NAME ": " @@ -1804,7 +1804,7 @@ static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx) struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data; put_unaligned_le32(rx->dma_addr, &prev_rfd->link); pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr, - sizeof(struct rfd), PCI_DMA_TODEVICE); + sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL); } return 0; @@ -1823,7 +1823,7 @@ static int e100_rx_indicate(struct nic *nic, struct rx *rx, /* Need to sync before taking a peek at cb_complete bit */ pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr, - sizeof(struct rfd), PCI_DMA_FROMDEVICE); + sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL); rfd_status = le16_to_cpu(rfd->status); DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status); @@ -1850,7 +1850,7 @@ static int e100_rx_indicate(struct nic *nic, struct rx *rx, /* Get data */ pci_unmap_single(nic->pdev, rx->dma_addr, - RFD_BUF_LEN, PCI_DMA_FROMDEVICE); + RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL); /* If this buffer has the el bit, but we think the receiver * is still running, check to see if it really stopped while @@ -1943,7 +1943,7 @@ static void e100_rx_clean(struct nic *nic, unsigned int *work_done, new_before_last_rfd->command |= cpu_to_le16(cb_el); pci_dma_sync_single_for_device(nic->pdev, new_before_last_rx->dma_addr, sizeof(struct rfd), - PCI_DMA_TODEVICE); + PCI_DMA_BIDIRECTIONAL); /* Now that we have a new stopping point, we can clear the old * stopping point. We must sync twice to get the proper @@ -1951,11 +1951,11 @@ static void e100_rx_clean(struct nic *nic, unsigned int *work_done, old_before_last_rfd->command &= ~cpu_to_le16(cb_el); pci_dma_sync_single_for_device(nic->pdev, old_before_last_rx->dma_addr, sizeof(struct rfd), - PCI_DMA_TODEVICE); + PCI_DMA_BIDIRECTIONAL); old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN); pci_dma_sync_single_for_device(nic->pdev, old_before_last_rx->dma_addr, sizeof(struct rfd), - PCI_DMA_TODEVICE); + PCI_DMA_BIDIRECTIONAL); } if(restart_required) { @@ -1978,7 +1978,7 @@ static void e100_rx_clean_list(struct nic *nic) for(rx = nic->rxs, i = 0; i < count; rx++, i++) { if(rx->skb) { pci_unmap_single(nic->pdev, rx->dma_addr, - RFD_BUF_LEN, PCI_DMA_FROMDEVICE); + RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL); dev_kfree_skb(rx->skb); } } @@ -2021,7 +2021,7 @@ static int e100_rx_alloc_list(struct nic *nic) before_last->command |= cpu_to_le16(cb_el); before_last->size = 0; pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr, - sizeof(struct rfd), PCI_DMA_TODEVICE); + sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL); nic->rx_to_use = nic->rx_to_clean = nic->rxs; nic->ru_running = RU_SUSPENDED; @@ -2222,7 +2222,7 @@ static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode) msleep(10); pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr, - RFD_BUF_LEN, PCI_DMA_FROMDEVICE); + RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL); if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd), skb->data, ETH_DATA_LEN)) diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c index 6a3893acfe04..c854c96f5ab3 100644 --- a/drivers/net/e1000/e1000_ethtool.c +++ b/drivers/net/e1000/e1000_ethtool.c @@ -1774,7 +1774,8 @@ static void e1000_get_wol(struct net_device *netdev, /* this function will set ->supported = 0 and return 1 if wol is not * supported by this hardware */ - if (e1000_wol_exclusion(adapter, wol)) + if (e1000_wol_exclusion(adapter, wol) || + !device_can_wakeup(&adapter->pdev->dev)) return; /* apply any specific unsupported masks here */ @@ -1811,7 +1812,8 @@ static int e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) return -EOPNOTSUPP; - if (e1000_wol_exclusion(adapter, wol)) + if (e1000_wol_exclusion(adapter, wol) || + !device_can_wakeup(&adapter->pdev->dev)) return wol->wolopts ? -EOPNOTSUPP : 0; switch (hw->device_id) { @@ -1838,6 +1840,8 @@ static int e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) if (wol->wolopts & WAKE_MAGIC) adapter->wol |= E1000_WUFC_MAG; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); + return 0; } diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c index fac82152e4c8..872799b746f5 100644 --- a/drivers/net/e1000/e1000_main.c +++ b/drivers/net/e1000/e1000_main.c @@ -1179,6 +1179,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, /* initialize the wol settings based on the eeprom settings */ adapter->wol = adapter->eeprom_wol; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); /* print bus type/speed/width info */ DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ", diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index c55de1c027af..c55fd6fdb91c 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h @@ -299,6 +299,7 @@ struct e1000_adapter { unsigned long led_status; unsigned int flags; + unsigned int flags2; struct work_struct downshift_task; struct work_struct update_phy_task; }; @@ -306,6 +307,7 @@ struct e1000_adapter { struct e1000_info { enum e1000_mac_type mac; unsigned int flags; + unsigned int flags2; u32 pba; s32 (*get_variants)(struct e1000_adapter *); struct e1000_mac_operations *mac_ops; @@ -347,6 +349,9 @@ struct e1000_info { #define FLAG_RX_RESTART_NOW (1 << 30) #define FLAG_MSI_TEST_FAILED (1 << 31) +/* CRC Stripping defines */ +#define FLAG2_CRC_STRIPPING (1 << 0) + #define E1000_RX_DESC_PS(R, i) \ (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index 70c11c811a08..62421ce96311 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c @@ -1713,7 +1713,8 @@ static void e1000_get_wol(struct net_device *netdev, wol->supported = 0; wol->wolopts = 0; - if (!(adapter->flags & FLAG_HAS_WOL)) + if (!(adapter->flags & FLAG_HAS_WOL) || + !device_can_wakeup(&adapter->pdev->dev)) return; wol->supported = WAKE_UCAST | WAKE_MCAST | @@ -1751,7 +1752,8 @@ static int e1000_set_wol(struct net_device *netdev, if (wol->wolopts & WAKE_MAGICSECURE) return -EOPNOTSUPP; - if (!(adapter->flags & FLAG_HAS_WOL)) + if (!(adapter->flags & FLAG_HAS_WOL) || + !device_can_wakeup(&adapter->pdev->dev)) return wol->wolopts ? -EOPNOTSUPP : 0; /* these settings will always override what we currently have */ @@ -1770,6 +1772,8 @@ static int e1000_set_wol(struct net_device *netdev, if (wol->wolopts & WAKE_ARP) adapter->wol |= E1000_WUFC_ARP; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); + return 0; } diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 523b9716a543..d115a6d30f29 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -1893,12 +1893,17 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ctrl |= E1000_CTRL_PHY_RST; } ret_val = e1000_acquire_swflag_ich8lan(hw); + /* Whether or not the swflag was acquired, we need to reset the part */ hw_dbg(hw, "Issuing a global reset to ich8lan"); ew32(CTRL, (ctrl | E1000_CTRL_RST)); msleep(20); - /* release the swflag because it is not reset by hardware reset */ - e1000_release_swflag_ich8lan(hw); + if (!ret_val) { + /* release the swflag because it is not reset by + * hardware reset + */ + e1000_release_swflag_ich8lan(hw); + } ret_val = e1000e_get_auto_rd_done(hw); if (ret_val) { diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index abd492b7336d..122539a0e1fe 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c @@ -345,7 +345,6 @@ no_buffers: /** * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers * @adapter: address of board private structure - * @rx_ring: pointer to receive ring structure * @cleaned_count: number of buffers to allocate this pass **/ @@ -499,6 +498,10 @@ static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, goto next_desc; } + /* adjust length to remove Ethernet CRC */ + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) + length -= 4; + total_rx_bytes += length; total_rx_packets++; @@ -804,6 +807,10 @@ static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, pci_dma_sync_single_for_device(pdev, ps_page->dma, PAGE_SIZE, PCI_DMA_FROMDEVICE); + /* remove the CRC */ + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) + l1 -= 4; + skb_put(skb, l1); goto copydone; } /* if */ @@ -825,6 +832,12 @@ static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, skb->truesize += length; } + /* strip the ethernet crc, problem is we're using pages now so + * this whole operation can get a little cpu intensive + */ + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) + pskb_trim(skb, skb->len - 4); + copydone: total_rx_bytes += skb->len; total_rx_packets++; @@ -2301,8 +2314,12 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter) else rctl |= E1000_RCTL_LPE; - /* Enable hardware CRC frame stripping */ - rctl |= E1000_RCTL_SECRC; + /* Some systems expect that the CRC is included in SMBUS traffic. The + * hardware strips the CRC before sending to both SMBUS (BMC) and to + * host memory when this is enabled + */ + if (adapter->flags2 & FLAG2_CRC_STRIPPING) + rctl |= E1000_RCTL_SECRC; /* Setup buffer sizes */ rctl &= ~E1000_RCTL_SZ_4096; @@ -4766,6 +4783,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, adapter->ei = ei; adapter->pba = ei->pba; adapter->flags = ei->flags; + adapter->flags2 = ei->flags2; adapter->hw.adapter = adapter; adapter->hw.mac.type = ei->mac; adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1; @@ -4970,6 +4988,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, /* initialize the wol settings based on the eeprom settings */ adapter->wol = adapter->eeprom_wol; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); /* reset the hardware with the new settings */ e1000e_reset(adapter); @@ -5008,6 +5027,7 @@ err_hw_init: err_sw_init: if (adapter->hw.flash_address) iounmap(adapter->hw.flash_address); + e1000e_reset_interrupt_capability(adapter); err_flashmap: iounmap(adapter->hw.hw_addr); err_ioremap: diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c index 77a3d7207a5f..e909f96698e8 100644 --- a/drivers/net/e1000e/param.c +++ b/drivers/net/e1000e/param.c @@ -151,6 +151,16 @@ E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); */ E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]"); +/* + * Enable CRC Stripping + * + * Valid Range: 0, 1 + * + * Default Value: 1 (enabled) + */ +E1000_PARAM(CrcStripping, "Enable CRC Stripping, disable if your BMC needs " \ + "the CRC"); + struct e1000_option { enum { enable_option, range_option, list_option } type; const char *name; @@ -404,6 +414,21 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter) adapter->flags |= FLAG_SMART_POWER_DOWN; } } + { /* CRC Stripping */ + const struct e1000_option opt = { + .type = enable_option, + .name = "CRC Stripping", + .err = "defaulting to enabled", + .def = OPTION_ENABLED + }; + + if (num_CrcStripping > bd) { + unsigned int crc_stripping = CrcStripping[bd]; + e1000_validate_option(&crc_stripping, &opt, adapter); + if (crc_stripping == OPTION_ENABLED) + adapter->flags2 |= FLAG2_CRC_STRIPPING; + } + } { /* Kumeran Lock Loss Workaround */ const struct e1000_option opt = { .type = enable_option, diff --git a/drivers/net/ehea/ehea.h b/drivers/net/ehea/ehea.h index 82dd1a891ce7..002d918fb4c7 100644 --- a/drivers/net/ehea/ehea.h +++ b/drivers/net/ehea/ehea.h @@ -40,7 +40,7 @@ #include #define DRV_NAME "ehea" -#define DRV_VERSION "EHEA_0094" +#define DRV_VERSION "EHEA_0095" /* eHEA capability flags */ #define DLPAR_PORT_ADD_REM 1 diff --git a/drivers/net/ehea/ehea_qmr.c b/drivers/net/ehea/ehea_qmr.c index 9b61dc9865d1..9d006878f045 100644 --- a/drivers/net/ehea/ehea_qmr.c +++ b/drivers/net/ehea/ehea_qmr.c @@ -632,10 +632,13 @@ static void ehea_rebuild_busmap(void) } } -static int ehea_update_busmap(unsigned long pfn, unsigned long pgnum, int add) +static int ehea_update_busmap(unsigned long pfn, unsigned long nr_pages, int add) { unsigned long i, start_section, end_section; + if (!nr_pages) + return 0; + if (!ehea_bmap) { ehea_bmap = kzalloc(sizeof(struct ehea_bmap), GFP_KERNEL); if (!ehea_bmap) @@ -643,7 +646,7 @@ static int ehea_update_busmap(unsigned long pfn, unsigned long pgnum, int add) } start_section = (pfn * PAGE_SIZE) / EHEA_SECTSIZE; - end_section = start_section + ((pgnum * PAGE_SIZE) / EHEA_SECTSIZE); + end_section = start_section + ((nr_pages * PAGE_SIZE) / EHEA_SECTSIZE); /* Mark entries as valid or invalid only; address is assigned later */ for (i = start_section; i < end_section; i++) { u64 flag; @@ -692,10 +695,54 @@ int ehea_rem_sect_bmap(unsigned long pfn, unsigned long nr_pages) return ret; } -static int ehea_create_busmap_callback(unsigned long pfn, - unsigned long nr_pages, void *arg) +static int ehea_is_hugepage(unsigned long pfn) +{ + int page_order; + + if (pfn & EHEA_HUGEPAGE_PFN_MASK) + return 0; + + page_order = compound_order(pfn_to_page(pfn)); + if (page_order + PAGE_SHIFT != EHEA_HUGEPAGESHIFT) + return 0; + + return 1; +} + +static int ehea_create_busmap_callback(unsigned long initial_pfn, + unsigned long total_nr_pages, void *arg) { - return ehea_update_busmap(pfn, nr_pages, EHEA_BUSMAP_ADD_SECT); + int ret; + unsigned long pfn, start_pfn, end_pfn, nr_pages; + + if ((total_nr_pages * PAGE_SIZE) < EHEA_HUGEPAGE_SIZE) + return ehea_update_busmap(initial_pfn, total_nr_pages, + EHEA_BUSMAP_ADD_SECT); + + /* Given chunk is >= 16GB -> check for hugepages */ + start_pfn = initial_pfn; + end_pfn = initial_pfn + total_nr_pages; + pfn = start_pfn; + + while (pfn < end_pfn) { + if (ehea_is_hugepage(pfn)) { + /* Add mem found in front of the hugepage */ + nr_pages = pfn - start_pfn; + ret = ehea_update_busmap(start_pfn, nr_pages, + EHEA_BUSMAP_ADD_SECT); + if (ret) + return ret; + + /* Skip the hugepage */ + pfn += (EHEA_HUGEPAGE_SIZE / PAGE_SIZE); + start_pfn = pfn; + } else + pfn += (EHEA_SECTSIZE / PAGE_SIZE); + } + + /* Add mem found behind the hugepage(s) */ + nr_pages = pfn - start_pfn; + return ehea_update_busmap(start_pfn, nr_pages, EHEA_BUSMAP_ADD_SECT); } int ehea_create_busmap(void) diff --git a/drivers/net/ehea/ehea_qmr.h b/drivers/net/ehea/ehea_qmr.h index 1e58dc06b7d2..0817c1e74a19 100644 --- a/drivers/net/ehea/ehea_qmr.h +++ b/drivers/net/ehea/ehea_qmr.h @@ -40,6 +40,9 @@ #define EHEA_PAGESIZE (1UL << EHEA_PAGESHIFT) #define EHEA_SECTSIZE (1UL << 24) #define EHEA_PAGES_PER_SECTION (EHEA_SECTSIZE >> EHEA_PAGESHIFT) +#define EHEA_HUGEPAGESHIFT 34 +#define EHEA_HUGEPAGE_SIZE (1UL << EHEA_HUGEPAGESHIFT) +#define EHEA_HUGEPAGE_PFN_MASK ((EHEA_HUGEPAGE_SIZE - 1) >> PAGE_SHIFT) #if ((1UL << SECTION_SIZE_BITS) < EHEA_SECTSIZE) #error eHEA module cannot work if kernel sectionsize < ehea sectionsize diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index e1b441effbbe..36cb6e95b465 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -568,6 +568,17 @@ static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end) return erxrdpt; } +/* + * Calculate wrap around when reading beyond the end of the RX buffer + */ +static u16 rx_packet_start(u16 ptr) +{ + if (ptr + RSV_SIZE > RXEND_INIT) + return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1); + else + return ptr + RSV_SIZE; +} + static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end) { u16 erxrdpt; @@ -938,8 +949,9 @@ static void enc28j60_hw_rx(struct net_device *ndev) skb->dev = ndev; skb_reserve(skb, NET_IP_ALIGN); /* copy the packet from the receive buffer */ - enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv), - len, skb_put(skb, len)); + enc28j60_mem_read(priv, + rx_packet_start(priv->next_pk_ptr), + len, skb_put(skb, len)); if (netif_msg_pktdata(priv)) dump_packet(__func__, skb->len, skb->data); skb->protocol = eth_type_trans(skb, ndev); @@ -947,7 +959,7 @@ static void enc28j60_hw_rx(struct net_device *ndev) ndev->stats.rx_packets++; ndev->stats.rx_bytes += len; ndev->last_rx = jiffies; - netif_rx(skb); + netif_rx_ni(skb); } } /* diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c index cb51c1fb0338..a6f49d025787 100644 --- a/drivers/net/fs_enet/fs_enet-main.c +++ b/drivers/net/fs_enet/fs_enet-main.c @@ -1099,7 +1099,9 @@ static int __devinit fs_enet_probe(struct of_device *ofdev, ndev->stop = fs_enet_close; ndev->get_stats = fs_enet_get_stats; ndev->set_multicast_list = fs_set_multicast_list; - +#ifdef CONFIG_NET_POLL_CONTROLLER + ndev->poll_controller = fs_enet_netpoll; +#endif if (fpi->use_napi) netif_napi_add(ndev, &fep->napi, fs_enet_rx_napi, fpi->napi_weight); @@ -1209,7 +1211,7 @@ static void __exit fs_cleanup(void) static void fs_enet_netpoll(struct net_device *dev) { disable_irq(dev->irq); - fs_enet_interrupt(dev->irq, dev, NULL); + fs_enet_interrupt(dev->irq, dev); enable_irq(dev->irq); } #endif diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 64b201134fdb..c4af949bf860 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -586,6 +586,18 @@ static void gfar_configure_serdes(struct net_device *dev) struct gfar_mii __iomem *regs = (void __iomem *)&priv->regs->gfar_mii_regs; int tbipa = gfar_read(&priv->regs->tbipa); + struct mii_bus *bus = gfar_get_miibus(priv); + + if (bus) + mutex_lock(&bus->mdio_lock); + + /* If the link is already up, we must already be ok, and don't need to + * configure and reset the TBI<->SerDes link. Maybe U-Boot configured + * everything for us? Resetting it takes the link down and requires + * several seconds for it to come back. + */ + if (gfar_local_mdio_read(regs, tbipa, MII_BMSR) & BMSR_LSTATUS) + goto done; /* Single clk mode, mii mode off(for serdes communication) */ gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT); @@ -596,6 +608,10 @@ static void gfar_configure_serdes(struct net_device *dev) gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); + + done: + if (bus) + mutex_unlock(&bus->mdio_lock); } static void init_registers(struct net_device *dev) @@ -1391,6 +1407,10 @@ static int gfar_clean_tx_ring(struct net_device *dev) if (bdp->status & TXBD_DEF) dev->stats.collisions++; + /* Unmap the DMA memory */ + dma_unmap_single(&priv->dev->dev, bdp->bufPtr, + bdp->length, DMA_TO_DEVICE); + /* Free the sk buffer associated with this TxBD */ dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]); @@ -1650,6 +1670,9 @@ int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) skb = priv->rx_skbuff[priv->skb_currx]; + dma_unmap_single(&priv->dev->dev, bdp->bufPtr, + priv->rx_buffer_size, DMA_FROM_DEVICE); + /* We drop the frame if we failed to allocate a new buffer */ if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || bdp->status & RXBD_ERR)) { @@ -1658,14 +1681,8 @@ int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) if (unlikely(!newskb)) newskb = skb; - if (skb) { - dma_unmap_single(&priv->dev->dev, - bdp->bufPtr, - priv->rx_buffer_size, - DMA_FROM_DEVICE); - + if (skb) dev_kfree_skb_any(skb); - } } else { /* Increment the number of packets */ dev->stats.rx_packets++; diff --git a/drivers/net/gianfar_mii.c b/drivers/net/gianfar_mii.c index bf73eea98010..0e2595d24933 100644 --- a/drivers/net/gianfar_mii.c +++ b/drivers/net/gianfar_mii.c @@ -269,6 +269,27 @@ static struct device_driver gianfar_mdio_driver = { .remove = gfar_mdio_remove, }; +static int match_mdio_bus(struct device *dev, void *data) +{ + const struct gfar_private *priv = data; + const struct platform_device *pdev = to_platform_device(dev); + + return !strcmp(pdev->name, gianfar_mdio_driver.name) && + pdev->id == priv->einfo->mdio_bus; +} + +/* Given a gfar_priv structure, find the mii_bus controlled by this device (not + * necessarily the same as the bus the gfar's PHY is on), if one exists. + * Normally only the first gianfar controls a mii_bus. */ +struct mii_bus *gfar_get_miibus(const struct gfar_private *priv) +{ + /*const*/ struct device *d; + + d = bus_find_device(gianfar_mdio_driver.bus, NULL, (void *)priv, + match_mdio_bus); + return d ? dev_get_drvdata(d) : NULL; +} + int __init gfar_mdio_init(void) { return driver_register(&gianfar_mdio_driver); diff --git a/drivers/net/gianfar_mii.h b/drivers/net/gianfar_mii.h index 2af28b16a0e2..02dc970ca1ff 100644 --- a/drivers/net/gianfar_mii.h +++ b/drivers/net/gianfar_mii.h @@ -18,6 +18,8 @@ #ifndef __GIANFAR_MII_H #define __GIANFAR_MII_H +struct gfar_private; /* forward ref */ + #define MIIMIND_BUSY 0x00000001 #define MIIMIND_NOTVALID 0x00000004 @@ -44,6 +46,7 @@ int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value); int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id, int regnum, u16 value); int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum); +struct mii_bus *gfar_get_miibus(const struct gfar_private *priv); int __init gfar_mdio_init(void); void gfar_mdio_exit(void); #endif /* GIANFAR_PHY_H */ diff --git a/drivers/net/hp-plus.c b/drivers/net/hp-plus.c index fbbd3e660c27..c01e290d09d2 100644 --- a/drivers/net/hp-plus.c +++ b/drivers/net/hp-plus.c @@ -230,7 +230,7 @@ static int __init hpp_probe1(struct net_device *dev, int ioaddr) dev->open = &hpp_open; dev->stop = &hpp_close; #ifdef CONFIG_NET_POLL_CONTROLLER - dev->poll_controller = ei_poll; + dev->poll_controller = eip_poll; #endif ei_status.name = name; diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c index 2ee2622258f5..901212aa37cb 100644 --- a/drivers/net/ibm_newemac/core.c +++ b/drivers/net/ibm_newemac/core.c @@ -2605,7 +2605,7 @@ static int __devinit emac_init_config(struct emac_instance *dev) of_device_is_compatible(np, "ibm,emac-440gr")) dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; if (of_device_is_compatible(np, "ibm,emac-405ez")) { -#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CONTROL +#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x; #else printk(KERN_ERR "%s: Flow control not disabled!\n", diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c index 58906c984be9..89964fa739a0 100644 --- a/drivers/net/igb/igb_ethtool.c +++ b/drivers/net/igb/igb_ethtool.c @@ -1776,7 +1776,8 @@ static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) /* this function will set ->supported = 0 and return 1 if wol is not * supported by this hardware */ - if (igb_wol_exclusion(adapter, wol)) + if (igb_wol_exclusion(adapter, wol) || + !device_can_wakeup(&adapter->pdev->dev)) return; /* apply any specific unsupported masks here */ @@ -1805,7 +1806,8 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) return -EOPNOTSUPP; - if (igb_wol_exclusion(adapter, wol)) + if (igb_wol_exclusion(adapter, wol) || + !device_can_wakeup(&adapter->pdev->dev)) return wol->wolopts ? -EOPNOTSUPP : 0; switch (hw->device_id) { @@ -1825,6 +1827,8 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) if (wol->wolopts & WAKE_MAGIC) adapter->wol |= E1000_WUFC_MAG; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); + return 0; } diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 1f397cd99414..20d27e622ec1 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c @@ -1019,10 +1019,9 @@ static int __devinit igb_probe(struct pci_dev *pdev, state &= ~PCIE_LINK_STATE_L0S; pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL, state); - printk(KERN_INFO "Disabling ASPM L0s upstream switch " - "port %x:%x.%x\n", us_dev->bus->number, - PCI_SLOT(us_dev->devfn), - PCI_FUNC(us_dev->devfn)); + dev_info(&pdev->dev, + "Disabling ASPM L0s upstream switch port %s\n", + pci_name(us_dev)); } default: break; @@ -1244,6 +1243,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, /* initialize the wol settings based on the eeprom settings */ adapter->wol = adapter->eeprom_wol; + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); /* reset the hardware with the new settings */ igb_reset(adapter); @@ -1980,7 +1980,6 @@ static void igb_configure_rx(struct igb_adapter *adapter) /** * igb_free_tx_resources - Free Tx Resources per Queue - * @adapter: board private structure * @tx_ring: Tx descriptor ring for a specific queue * * Free all transmit software resources @@ -2033,7 +2032,6 @@ static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, /** * igb_clean_tx_ring - Free Tx Buffers - * @adapter: board private structure * @tx_ring: ring to be cleaned **/ static void igb_clean_tx_ring(struct igb_ring *tx_ring) @@ -2080,7 +2078,6 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter) /** * igb_free_rx_resources - Free Rx Resources - * @adapter: board private structure * @rx_ring: ring to clean the resources from * * Free all receive software resources @@ -2120,7 +2117,6 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter) /** * igb_clean_rx_ring - Free Rx Buffers per Queue - * @adapter: board private structure * @rx_ring: ring to free buffers from **/ static void igb_clean_rx_ring(struct igb_ring *rx_ring) diff --git a/drivers/net/ipg.c b/drivers/net/ipg.c index 7373dafbb3f7..059369885be1 100644 --- a/drivers/net/ipg.c +++ b/drivers/net/ipg.c @@ -1112,7 +1112,7 @@ static void ipg_nic_rx_free_skb(struct net_device *dev) struct ipg_rx *rxfd = sp->rxd + entry; pci_unmap_single(sp->pdev, - le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), + le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN, sp->rx_buf_sz, PCI_DMA_FROMDEVICE); dev_kfree_skb_irq(sp->rx_buff[entry]); sp->rx_buff[entry] = NULL; @@ -1179,7 +1179,7 @@ static int ipg_nic_rx_check_error(struct net_device *dev) */ if (sp->rx_buff[entry]) { pci_unmap_single(sp->pdev, - le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), + le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN, sp->rx_buf_sz, PCI_DMA_FROMDEVICE); dev_kfree_skb_irq(sp->rx_buff[entry]); @@ -1246,7 +1246,7 @@ static void ipg_nic_rx_with_start(struct net_device *dev, if (jumbo->found_start) dev_kfree_skb_irq(jumbo->skb); - pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN), + pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN, sp->rx_buf_sz, PCI_DMA_FROMDEVICE); skb_put(skb, sp->rxfrag_size); @@ -1349,7 +1349,7 @@ static int ipg_nic_rx_jumbo(struct net_device *dev) unsigned int entry = curr % IPG_RFDLIST_LENGTH; struct ipg_rx *rxfd = sp->rxd + entry; - if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE))) + if (!(rxfd->rfs & cpu_to_le64(IPG_RFS_RFDDONE))) break; switch (ipg_nic_rx_check_frame_type(dev)) { diff --git a/drivers/net/irda/ks959-sir.c b/drivers/net/irda/ks959-sir.c index 2482d61662a2..2e67ae015d91 100644 --- a/drivers/net/irda/ks959-sir.c +++ b/drivers/net/irda/ks959-sir.c @@ -118,7 +118,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/irda/ksdazzle-sir.c b/drivers/net/irda/ksdazzle-sir.c index 1e0de93fd618..3843b5faba8b 100644 --- a/drivers/net/irda/ksdazzle-sir.c +++ b/drivers/net/irda/ksdazzle-sir.c @@ -82,7 +82,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 7548fb7360d9..5236f633ee36 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -1287,13 +1287,39 @@ static void ixgbe_set_itr(struct ixgbe_adapter *adapter) return; } -static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter); +/** + * ixgbe_irq_disable - Mask off interrupt generation on the NIC + * @adapter: board private structure + **/ +static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) +{ + IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); + IXGBE_WRITE_FLUSH(&adapter->hw); + if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { + int i; + for (i = 0; i < adapter->num_msix_vectors; i++) + synchronize_irq(adapter->msix_entries[i].vector); + } else { + synchronize_irq(adapter->pdev->irq); + } +} + +/** + * ixgbe_irq_enable - Enable default interrupt generation settings + * @adapter: board private structure + **/ +static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) +{ + u32 mask; + mask = IXGBE_EIMS_ENABLE_MASK; + IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); + IXGBE_WRITE_FLUSH(&adapter->hw); +} /** * ixgbe_intr - legacy mode Interrupt Handler * @irq: interrupt number * @data: pointer to a network interface device structure - * @pt_regs: CPU registers structure **/ static irqreturn_t ixgbe_intr(int irq, void *data) { @@ -1393,35 +1419,6 @@ static void ixgbe_free_irq(struct ixgbe_adapter *adapter) } } -/** - * ixgbe_irq_disable - Mask off interrupt generation on the NIC - * @adapter: board private structure - **/ -static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) -{ - IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); - IXGBE_WRITE_FLUSH(&adapter->hw); - if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { - int i; - for (i = 0; i < adapter->num_msix_vectors; i++) - synchronize_irq(adapter->msix_entries[i].vector); - } else { - synchronize_irq(adapter->pdev->irq); - } -} - -/** - * ixgbe_irq_enable - Enable default interrupt generation settings - * @adapter: board private structure - **/ -static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) -{ - u32 mask; - mask = IXGBE_EIMS_ENABLE_MASK; - IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); - IXGBE_WRITE_FLUSH(&adapter->hw); -} - /** * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts * @@ -2332,7 +2329,7 @@ static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, * Once we know the feature-set enabled for the device, we'll cache * the register offset the descriptor ring is assigned to. **/ -static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) +static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) { int feature_mask = 0, rss_i; int i, txr_idx, rxr_idx; @@ -2369,7 +2366,7 @@ static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) * number of queues at compile-time. The polling_netdev array is * intended for Multiqueue, but should work fine with a single queue. **/ -static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter) +static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) { int i; @@ -2410,8 +2407,7 @@ err_tx_ring_allocation: * Attempt to configure the interrupts using the best available * capabilities of the hardware and the kernel. **/ -static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter - *adapter) +static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) { int err = 0; int vector, v_budget; @@ -2503,7 +2499,7 @@ static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) * - Hardware queue count (num_*_queues) * - defined by miscellaneous hardware support/features (RSS, etc.) **/ -static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) +static int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) { int err; diff --git a/drivers/net/jme.c b/drivers/net/jme.c index 81c6cdc3851f..665e70d620fc 100644 --- a/drivers/net/jme.c +++ b/drivers/net/jme.c @@ -912,23 +912,23 @@ jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx) skb_put(skb, framesize); skb->protocol = eth_type_trans(skb, jme->dev); - if (jme_rxsum_ok(jme, rxdesc->descwb.flags)) + if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags))) skb->ip_summed = CHECKSUM_UNNECESSARY; else skb->ip_summed = CHECKSUM_NONE; - if (rxdesc->descwb.flags & RXWBFLAG_TAGON) { + if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) { if (jme->vlgrp) { jme->jme_vlan_rx(skb, jme->vlgrp, - le32_to_cpu(rxdesc->descwb.vlan)); + le16_to_cpu(rxdesc->descwb.vlan)); NET_STAT(jme).rx_bytes += 4; } } else { jme->jme_rx(skb); } - if ((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) == - RXWBFLAG_DEST_MUL) + if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) == + cpu_to_le16(RXWBFLAG_DEST_MUL)) ++(NET_STAT(jme).multicast); jme->dev->last_rx = jiffies; @@ -961,7 +961,7 @@ jme_process_receive(struct jme_adapter *jme, int limit) rxdesc = rxring->desc; rxdesc += i; - if ((rxdesc->descwb.flags & RXWBFLAG_OWN) || + if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) || !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL)) goto out; @@ -1763,10 +1763,9 @@ jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb) } static int -jme_tx_tso(struct sk_buff *skb, - u16 *mss, u8 *flags) +jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags) { - *mss = skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT; + *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT); if (*mss) { *flags |= TXFLAG_LSEN; @@ -1826,11 +1825,11 @@ jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags) } static inline void -jme_tx_vlan(struct sk_buff *skb, u16 *vlan, u8 *flags) +jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags) { if (vlan_tx_tag_present(skb)) { *flags |= TXFLAG_TAGON; - *vlan = vlan_tx_tag_get(skb); + *vlan = cpu_to_le16(vlan_tx_tag_get(skb)); } } diff --git a/drivers/net/jme.h b/drivers/net/jme.h index f863aee6648b..3f5d91543246 100644 --- a/drivers/net/jme.h +++ b/drivers/net/jme.h @@ -22,7 +22,7 @@ */ #ifndef __JME_H_INCLUDED__ -#define __JME_H_INCLUDEE__ +#define __JME_H_INCLUDED__ #define DRV_NAME "jme" #define DRV_VERSION "1.0.3" diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 3b43bfd85a0f..b1ac63ab8c16 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -76,15 +76,6 @@ static int loopback_xmit(struct sk_buff *skb, struct net_device *dev) skb->protocol = eth_type_trans(skb,dev); -#ifdef LOOPBACK_TSO - if (skb_is_gso(skb)) { - BUG_ON(skb->protocol != htons(ETH_P_IP)); - BUG_ON(ip_hdr(skb)->protocol != IPPROTO_TCP); - - emulate_large_send_offload(skb); - return 0; - } -#endif dev->last_rx = jiffies; /* it's OK to use per_cpu_ptr() because BHs are off */ diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index 42394505bb50..590039cbb146 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -70,6 +70,9 @@ static void macvlan_broadcast(struct sk_buff *skb, struct sk_buff *nskb; unsigned int i; + if (skb->protocol == htons(ETH_P_PAUSE)) + return; + for (i = 0; i < MACVLAN_HASH_SIZE; i++) { hlist_for_each_entry_rcu(vlan, n, &port->vlan_hash[i], hlist) { dev = vlan->dev; diff --git a/drivers/net/mlx4/en_main.c b/drivers/net/mlx4/en_main.c index 1b0eebf84f76..4b9794e97a79 100644 --- a/drivers/net/mlx4/en_main.c +++ b/drivers/net/mlx4/en_main.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include diff --git a/drivers/net/mlx4/en_netdev.c b/drivers/net/mlx4/en_netdev.c index a339afbeed38..96e709d6440a 100644 --- a/drivers/net/mlx4/en_netdev.c +++ b/drivers/net/mlx4/en_netdev.c @@ -656,10 +656,10 @@ static int mlx4_en_start_port(struct net_device *dev) /* Configure port */ err = mlx4_SET_PORT_general(mdev->dev, priv->port, priv->rx_skb_size + ETH_FCS_LEN, - mdev->profile.tx_pause, - mdev->profile.tx_ppp, - mdev->profile.rx_pause, - mdev->profile.rx_ppp); + priv->prof->tx_pause, + priv->prof->tx_ppp, + priv->prof->rx_pause, + priv->prof->rx_ppp); if (err) { mlx4_err(mdev, "Failed setting port general configurations" " for port %d, with error %d\n", priv->port, err); @@ -706,7 +706,7 @@ tx_err: mlx4_en_release_rss_steer(priv); rx_err: for (i = 0; i < priv->rx_ring_num; i++) - mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[rx_index]); + mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); cq_err: while (rx_index--) mlx4_en_deactivate_cq(priv, &priv->rx_cq[rx_index]); diff --git a/drivers/net/mlx4/en_params.c b/drivers/net/mlx4/en_params.c index c2e69b1bcd0a..95706ee1c019 100644 --- a/drivers/net/mlx4/en_params.c +++ b/drivers/net/mlx4/en_params.c @@ -90,6 +90,7 @@ MLX4_EN_PARM_INT(rx_ring_size2, MLX4_EN_AUTO_CONF, "Rx ring size for port 2"); int mlx4_en_get_profile(struct mlx4_en_dev *mdev) { struct mlx4_en_profile *params = &mdev->profile; + int i; params->rx_moder_cnt = min_t(int, rx_moder_cnt, MLX4_EN_AUTO_CONF); params->rx_moder_time = min_t(int, rx_moder_time, MLX4_EN_AUTO_CONF); @@ -97,11 +98,13 @@ int mlx4_en_get_profile(struct mlx4_en_dev *mdev) params->rss_xor = (rss_xor != 0); params->rss_mask = rss_mask & 0x1f; params->num_lro = min_t(int, num_lro , MLX4_EN_MAX_LRO_DESCRIPTORS); - params->rx_pause = pprx; - params->rx_ppp = pfcrx; - params->tx_pause = pptx; - params->tx_ppp = pfctx; - if (params->rx_ppp || params->tx_ppp) { + for (i = 1; i <= MLX4_MAX_PORTS; i++) { + params->prof[i].rx_pause = pprx; + params->prof[i].rx_ppp = pfcrx; + params->prof[i].tx_pause = pptx; + params->prof[i].tx_ppp = pfctx; + } + if (pfcrx || pfctx) { params->prof[1].tx_ring_num = MLX4_EN_TX_RING_NUM; params->prof[2].tx_ring_num = MLX4_EN_TX_RING_NUM; } else { @@ -407,14 +410,14 @@ static int mlx4_en_set_pauseparam(struct net_device *dev, struct mlx4_en_dev *mdev = priv->mdev; int err; - mdev->profile.tx_pause = pause->tx_pause != 0; - mdev->profile.rx_pause = pause->rx_pause != 0; + priv->prof->tx_pause = pause->tx_pause != 0; + priv->prof->rx_pause = pause->rx_pause != 0; err = mlx4_SET_PORT_general(mdev->dev, priv->port, priv->rx_skb_size + ETH_FCS_LEN, - mdev->profile.tx_pause, - mdev->profile.tx_ppp, - mdev->profile.rx_pause, - mdev->profile.rx_ppp); + priv->prof->tx_pause, + priv->prof->tx_ppp, + priv->prof->rx_pause, + priv->prof->rx_ppp); if (err) mlx4_err(mdev, "Failed setting pause params to\n"); @@ -425,10 +428,9 @@ static void mlx4_en_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) { struct mlx4_en_priv *priv = netdev_priv(dev); - struct mlx4_en_dev *mdev = priv->mdev; - pause->tx_pause = mdev->profile.tx_pause; - pause->rx_pause = mdev->profile.rx_pause; + pause->tx_pause = priv->prof->tx_pause; + pause->rx_pause = priv->prof->rx_pause; } static void mlx4_en_get_ringparam(struct net_device *dev, diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c index be09fdb79cb8..cee199ceba2f 100644 --- a/drivers/net/mlx4/fw.c +++ b/drivers/net/mlx4/fw.c @@ -360,9 +360,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) #define QUERY_PORT_ETH_MTU_OFFSET 0x02 #define QUERY_PORT_WIDTH_OFFSET 0x06 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 -#define QUERY_PORT_MAC_OFFSET 0x08 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a #define QUERY_PORT_MAX_VL_OFFSET 0x0b +#define QUERY_PORT_MAC_OFFSET 0x10 for (i = 1; i <= dev_cap->num_ports; ++i) { err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, diff --git a/drivers/net/mlx4/main.c b/drivers/net/mlx4/main.c index 468921b8f4b6..90a0281d15ea 100644 --- a/drivers/net/mlx4/main.c +++ b/drivers/net/mlx4/main.c @@ -753,6 +753,7 @@ static int mlx4_setup_hca(struct mlx4_dev *dev) struct mlx4_priv *priv = mlx4_priv(dev); int err; int port; + __be32 ib_port_default_caps; err = mlx4_init_uar_table(dev); if (err) { @@ -852,6 +853,13 @@ static int mlx4_setup_hca(struct mlx4_dev *dev) } for (port = 1; port <= dev->caps.num_ports; port++) { + ib_port_default_caps = 0; + err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps); + if (err) + mlx4_warn(dev, "failed to get port %d default " + "ib capabilities (%d). Continuing with " + "caps = 0\n", port, err); + dev->caps.ib_port_def_cap[port] = ib_port_default_caps; err = mlx4_SET_PORT(dev, port); if (err) { mlx4_err(dev, "Failed to set port %d, aborting\n", diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h index fa431fad0eec..34c909deaff3 100644 --- a/drivers/net/mlx4/mlx4.h +++ b/drivers/net/mlx4/mlx4.h @@ -87,6 +87,9 @@ enum { #ifdef CONFIG_MLX4_DEBUG extern int mlx4_debug_level; +#else /* CONFIG_MLX4_DEBUG */ +#define mlx4_debug_level (0) +#endif /* CONFIG_MLX4_DEBUG */ #define mlx4_dbg(mdev, format, arg...) \ do { \ @@ -94,12 +97,6 @@ extern int mlx4_debug_level; dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \ } while (0) -#else /* CONFIG_MLX4_DEBUG */ - -#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0) - -#endif /* CONFIG_MLX4_DEBUG */ - #define mlx4_err(mdev, format, arg...) \ dev_err(&mdev->pdev->dev, format, ## arg) #define mlx4_info(mdev, format, arg...) \ @@ -388,5 +385,6 @@ void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); +int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); #endif /* MLX4_H */ diff --git a/drivers/net/mlx4/mlx4_en.h b/drivers/net/mlx4/mlx4_en.h index 11fb17c6e97b..98ddc0811f93 100644 --- a/drivers/net/mlx4/mlx4_en.h +++ b/drivers/net/mlx4/mlx4_en.h @@ -322,6 +322,10 @@ struct mlx4_en_port_profile { u32 rx_ring_num; u32 tx_ring_size; u32 rx_ring_size; + u8 rx_pause; + u8 rx_ppp; + u8 tx_pause; + u8 tx_ppp; }; struct mlx4_en_profile { @@ -333,10 +337,6 @@ struct mlx4_en_profile { int rx_moder_cnt; int rx_moder_time; int auto_moder; - u8 rx_pause; - u8 rx_ppp; - u8 tx_pause; - u8 tx_ppp; u8 no_reset; struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; }; diff --git a/drivers/net/mlx4/port.c b/drivers/net/mlx4/port.c index e2fdab42c4ce..0a057e5dc63b 100644 --- a/drivers/net/mlx4/port.c +++ b/drivers/net/mlx4/port.c @@ -258,6 +258,42 @@ out: } EXPORT_SYMBOL_GPL(mlx4_unregister_vlan); +int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps) +{ + struct mlx4_cmd_mailbox *inmailbox, *outmailbox; + u8 *inbuf, *outbuf; + int err; + + inmailbox = mlx4_alloc_cmd_mailbox(dev); + if (IS_ERR(inmailbox)) + return PTR_ERR(inmailbox); + + outmailbox = mlx4_alloc_cmd_mailbox(dev); + if (IS_ERR(outmailbox)) { + mlx4_free_cmd_mailbox(dev, inmailbox); + return PTR_ERR(outmailbox); + } + + inbuf = inmailbox->buf; + outbuf = outmailbox->buf; + memset(inbuf, 0, 256); + memset(outbuf, 0, 256); + inbuf[0] = 1; + inbuf[1] = 1; + inbuf[2] = 1; + inbuf[3] = 1; + *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015); + *(__be32 *) (&inbuf[20]) = cpu_to_be32(port); + + err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3, + MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C); + if (!err) + *caps = *(__be32 *) (outbuf + 84); + mlx4_free_cmd_mailbox(dev, inmailbox); + mlx4_free_cmd_mailbox(dev, outmailbox); + return err; +} + int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port) { struct mlx4_cmd_mailbox *mailbox; @@ -273,7 +309,8 @@ int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port) ((u8 *) mailbox->buf)[3] = 6; ((__be16 *) mailbox->buf)[4] = cpu_to_be16(1 << 15); ((__be16 *) mailbox->buf)[6] = cpu_to_be16(1 << 15); - } + } else + ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port]; err = mlx4_cmd(dev, mailbox->dma, port, is_eth, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B); diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index a9c8c08044b1..e513f76f2a9f 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c @@ -899,7 +899,8 @@ static int txq_reclaim(struct tx_queue *txq, int budget, int force) if (skb != NULL) { if (skb_queue_len(&mp->rx_recycle) < mp->default_rx_ring_size && - skb_recycle_check(skb, mp->skb_size)) + skb_recycle_check(skb, mp->skb_size + + dma_get_cache_alignment() - 1)) __skb_queue_head(&mp->rx_recycle, skb); else dev_kfree_skb(skb); @@ -1066,9 +1067,12 @@ static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) return 0; } - if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), - msecs_to_jiffies(100))) - return -ETIMEDOUT; + if (!smi_is_done(msp)) { + wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), + msecs_to_jiffies(100)); + if (!smi_is_done(msp)) + return -ETIMEDOUT; + } return 0; } @@ -2432,8 +2436,8 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev) struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; if (pd == NULL || pd->shared_smi == NULL) { - mdiobus_free(msp->smi_bus); mdiobus_unregister(msp->smi_bus); + mdiobus_free(msp->smi_bus); } if (msp->err_interrupt != NO_IRQ) free_irq(msp->err_interrupt, msp); diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c index b1556b2e404c..b37867097308 100644 --- a/drivers/net/myri10ge/myri10ge.c +++ b/drivers/net/myri10ge/myri10ge.c @@ -75,7 +75,7 @@ #include "myri10ge_mcp.h" #include "myri10ge_mcp_gen_header.h" -#define MYRI10GE_VERSION_STR "1.4.3-1.371" +#define MYRI10GE_VERSION_STR "1.4.3-1.378" MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); MODULE_AUTHOR("Maintainer: help@myri.com"); @@ -1393,6 +1393,8 @@ myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index) if (tx->req == tx->done) { tx->queue_active = 0; put_be32(htonl(1), tx->send_stop); + mb(); + mmiowb(); } __netif_tx_unlock(dev_queue); } @@ -2864,6 +2866,8 @@ again: if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) { tx->queue_active = 1; put_be32(htonl(1), tx->send_go); + mb(); + mmiowb(); } tx->pkt_start++; if ((avail - count) < MXGEFW_MAX_SEND_DESC) { diff --git a/drivers/net/netx-eth.c b/drivers/net/netx-eth.c index b9bed82e1d21..b289a0a2b945 100644 --- a/drivers/net/netx-eth.c +++ b/drivers/net/netx-eth.c @@ -401,6 +401,8 @@ static int netx_eth_drv_probe(struct platform_device *pdev) priv->xmac_base = priv->xc->xmac_base; priv->sram_base = priv->xc->sram_base; + spin_lock_init(&priv->lock); + ret = pfifo_request(PFIFO_MASK(priv->id)); if (ret) { printk("unable to request PFIFO\n"); diff --git a/drivers/net/niu.c b/drivers/net/niu.c index ebc812702903..1b6f548c4411 100644 --- a/drivers/net/niu.c +++ b/drivers/net/niu.c @@ -33,8 +33,8 @@ #define DRV_MODULE_NAME "niu" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "0.9" -#define DRV_MODULE_RELDATE "May 4, 2008" +#define DRV_MODULE_VERSION "1.0" +#define DRV_MODULE_RELDATE "Nov 14, 2008" static char version[] __devinitdata = DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; @@ -51,8 +51,7 @@ MODULE_VERSION(DRV_MODULE_VERSION); #ifndef readq static u64 readq(void __iomem *reg) { - return (((u64)readl(reg + 0x4UL) << 32) | - (u64)readl(reg)); + return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); } static void writeq(u64 val, void __iomem *reg) @@ -407,7 +406,7 @@ static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) } /* Mode is always 10G fiber. */ -static int serdes_init_niu(struct niu *np) +static int serdes_init_niu_10g_fiber(struct niu *np) { struct niu_link_config *lp = &np->link_config; u32 tx_cfg, rx_cfg; @@ -444,6 +443,223 @@ static int serdes_init_niu(struct niu *np) return 0; } +static int serdes_init_niu_1g_serdes(struct niu *np) +{ + struct niu_link_config *lp = &np->link_config; + u16 pll_cfg, pll_sts; + int max_retry = 100; + u64 sig, mask, val; + u32 tx_cfg, rx_cfg; + unsigned long i; + int err; + + tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | + PLL_TX_CFG_RATE_HALF); + rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | + PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | + PLL_RX_CFG_RATE_HALF); + + if (np->port == 0) + rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; + + if (lp->loopback_mode == LOOPBACK_PHY) { + u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; + + mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, + ESR2_TI_PLL_TEST_CFG_L, test_cfg); + + tx_cfg |= PLL_TX_CFG_ENTEST; + rx_cfg |= PLL_RX_CFG_ENTEST; + } + + /* Initialize PLL for 1G */ + pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); + + err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, + ESR2_TI_PLL_CFG_L, pll_cfg); + if (err) { + dev_err(np->device, PFX "NIU Port %d " + "serdes_init_niu_1g_serdes: " + "mdio write to ESR2_TI_PLL_CFG_L failed", np->port); + return err; + } + + pll_sts = PLL_CFG_ENPLL; + + err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, + ESR2_TI_PLL_STS_L, pll_sts); + if (err) { + dev_err(np->device, PFX "NIU Port %d " + "serdes_init_niu_1g_serdes: " + "mdio write to ESR2_TI_PLL_STS_L failed", np->port); + return err; + } + + udelay(200); + + /* Initialize all 4 lanes of the SERDES. */ + for (i = 0; i < 4; i++) { + err = esr2_set_tx_cfg(np, i, tx_cfg); + if (err) + return err; + } + + for (i = 0; i < 4; i++) { + err = esr2_set_rx_cfg(np, i, rx_cfg); + if (err) + return err; + } + + switch (np->port) { + case 0: + val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); + mask = val; + break; + + case 1: + val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); + mask = val; + break; + + default: + return -EINVAL; + } + + while (max_retry--) { + sig = nr64(ESR_INT_SIGNALS); + if ((sig & mask) == val) + break; + + mdelay(500); + } + + if ((sig & mask) != val) { + dev_err(np->device, PFX "Port %u signal bits [%08x] are not " + "[%08x]\n", np->port, (int) (sig & mask), (int) val); + return -ENODEV; + } + + return 0; +} + +static int serdes_init_niu_10g_serdes(struct niu *np) +{ + struct niu_link_config *lp = &np->link_config; + u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; + int max_retry = 100; + u64 sig, mask, val; + unsigned long i; + int err; + + tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); + rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | + PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | + PLL_RX_CFG_EQ_LP_ADAPTIVE); + + if (lp->loopback_mode == LOOPBACK_PHY) { + u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; + + mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, + ESR2_TI_PLL_TEST_CFG_L, test_cfg); + + tx_cfg |= PLL_TX_CFG_ENTEST; + rx_cfg |= PLL_RX_CFG_ENTEST; + } + + /* Initialize PLL for 10G */ + pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); + + err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, + ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); + if (err) { + dev_err(np->device, PFX "NIU Port %d " + "serdes_init_niu_10g_serdes: " + "mdio write to ESR2_TI_PLL_CFG_L failed", np->port); + return err; + } + + pll_sts = PLL_CFG_ENPLL; + + err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, + ESR2_TI_PLL_STS_L, pll_sts & 0xffff); + if (err) { + dev_err(np->device, PFX "NIU Port %d " + "serdes_init_niu_10g_serdes: " + "mdio write to ESR2_TI_PLL_STS_L failed", np->port); + return err; + } + + udelay(200); + + /* Initialize all 4 lanes of the SERDES. */ + for (i = 0; i < 4; i++) { + err = esr2_set_tx_cfg(np, i, tx_cfg); + if (err) + return err; + } + + for (i = 0; i < 4; i++) { + err = esr2_set_rx_cfg(np, i, rx_cfg); + if (err) + return err; + } + + /* check if serdes is ready */ + + switch (np->port) { + case 0: + mask = ESR_INT_SIGNALS_P0_BITS; + val = (ESR_INT_SRDY0_P0 | + ESR_INT_DET0_P0 | + ESR_INT_XSRDY_P0 | + ESR_INT_XDP_P0_CH3 | + ESR_INT_XDP_P0_CH2 | + ESR_INT_XDP_P0_CH1 | + ESR_INT_XDP_P0_CH0); + break; + + case 1: + mask = ESR_INT_SIGNALS_P1_BITS; + val = (ESR_INT_SRDY0_P1 | + ESR_INT_DET0_P1 | + ESR_INT_XSRDY_P1 | + ESR_INT_XDP_P1_CH3 | + ESR_INT_XDP_P1_CH2 | + ESR_INT_XDP_P1_CH1 | + ESR_INT_XDP_P1_CH0); + break; + + default: + return -EINVAL; + } + + while (max_retry--) { + sig = nr64(ESR_INT_SIGNALS); + if ((sig & mask) == val) + break; + + mdelay(500); + } + + if ((sig & mask) != val) { + pr_info(PFX "NIU Port %u signal bits [%08x] are not " + "[%08x] for 10G...trying 1G\n", + np->port, (int) (sig & mask), (int) val); + + /* 10G failed, try initializing at 1G */ + err = serdes_init_niu_1g_serdes(np); + if (!err) { + np->flags &= ~NIU_FLAGS_10G; + np->mac_xcvr = MAC_XCVR_PCS; + } else { + dev_err(np->device, PFX "Port %u 10G/1G SERDES " + "Link Failed \n", np->port); + return -ENODEV; + } + } + return 0; +} + static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) { int err; @@ -1955,13 +2171,23 @@ static const struct niu_phy_ops phy_ops_10g_serdes = { .link_status = link_status_10g_serdes, }; +static const struct niu_phy_ops phy_ops_10g_serdes_niu = { + .serdes_init = serdes_init_niu_10g_serdes, + .link_status = link_status_10g_serdes, +}; + +static const struct niu_phy_ops phy_ops_1g_serdes_niu = { + .serdes_init = serdes_init_niu_1g_serdes, + .link_status = link_status_1g_serdes, +}; + static const struct niu_phy_ops phy_ops_1g_rgmii = { .xcvr_init = xcvr_init_1g_rgmii, .link_status = link_status_1g_rgmii, }; static const struct niu_phy_ops phy_ops_10g_fiber_niu = { - .serdes_init = serdes_init_niu, + .serdes_init = serdes_init_niu_10g_fiber, .xcvr_init = xcvr_init_10g, .link_status = link_status_10g, }; @@ -1999,11 +2225,21 @@ struct niu_phy_template { u32 phy_addr_base; }; -static const struct niu_phy_template phy_template_niu = { +static const struct niu_phy_template phy_template_niu_10g_fiber = { .ops = &phy_ops_10g_fiber_niu, .phy_addr_base = 16, }; +static const struct niu_phy_template phy_template_niu_10g_serdes = { + .ops = &phy_ops_10g_serdes_niu, + .phy_addr_base = 0, +}; + +static const struct niu_phy_template phy_template_niu_1g_serdes = { + .ops = &phy_ops_1g_serdes_niu, + .phy_addr_base = 0, +}; + static const struct niu_phy_template phy_template_10g_fiber = { .ops = &phy_ops_10g_fiber, .phy_addr_base = 8, @@ -2183,8 +2419,25 @@ static int niu_determine_phy_disposition(struct niu *np) u32 phy_addr_off = 0; if (plat_type == PLAT_TYPE_NIU) { - tp = &phy_template_niu; - phy_addr_off += np->port; + switch (np->flags & + (NIU_FLAGS_10G | + NIU_FLAGS_FIBER | + NIU_FLAGS_XCVR_SERDES)) { + case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: + /* 10G Serdes */ + tp = &phy_template_niu_10g_serdes; + break; + case NIU_FLAGS_XCVR_SERDES: + /* 1G Serdes */ + tp = &phy_template_niu_1g_serdes; + break; + case NIU_FLAGS_10G | NIU_FLAGS_FIBER: + /* 10G Fiber */ + default: + tp = &phy_template_niu_10g_fiber; + phy_addr_off += np->port; + break; + } } else { switch (np->flags & (NIU_FLAGS_10G | @@ -7214,6 +7467,12 @@ static int __devinit niu_phy_type_prop_decode(struct niu *np, np->flags |= NIU_FLAGS_10G; np->flags &= ~NIU_FLAGS_FIBER; np->mac_xcvr = MAC_XCVR_XPCS; + } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) { + /* 10G Serdes or 1G Serdes, default to 10G */ + np->flags |= NIU_FLAGS_10G; + np->flags &= ~NIU_FLAGS_FIBER; + np->flags |= NIU_FLAGS_XCVR_SERDES; + np->mac_xcvr = MAC_XCVR_XPCS; } else { return -EINVAL; } @@ -7742,6 +8001,8 @@ static int __devinit walk_phys(struct niu *np, struct niu_parent *parent) u32 val; int err; + num_10g = num_1g = 0; + if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { num_10g = 0; @@ -7758,6 +8019,16 @@ static int __devinit walk_phys(struct niu *np, struct niu_parent *parent) parent->num_ports = 2; val = (phy_encode(PORT_TYPE_10G, 0) | phy_encode(PORT_TYPE_10G, 1)); + } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) && + (parent->plat_type == PLAT_TYPE_NIU)) { + /* this is the Monza case */ + if (np->flags & NIU_FLAGS_10G) { + val = (phy_encode(PORT_TYPE_10G, 0) | + phy_encode(PORT_TYPE_10G, 1)); + } else { + val = (phy_encode(PORT_TYPE_1G, 0) | + phy_encode(PORT_TYPE_1G, 1)); + } } else { err = fill_phy_probe_info(np, parent, info); if (err) @@ -8657,7 +8928,9 @@ static void __devinit niu_device_announce(struct niu *np) dev->name, (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), - (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"), + (np->flags & NIU_FLAGS_FIBER ? "FIBER" : + (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" : + "COPPER")), (np->mac_xcvr == MAC_XCVR_MII ? "MII" : (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), np->vpd.phy_type); @@ -8667,7 +8940,6 @@ static void __devinit niu_device_announce(struct niu *np) static int __devinit niu_pci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { - unsigned long niureg_base, niureg_len; union niu_parent_id parent_id; struct net_device *dev; struct niu *np; @@ -8758,10 +9030,7 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev, dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); - niureg_base = pci_resource_start(pdev, 0); - niureg_len = pci_resource_len(pdev, 0); - - np->regs = ioremap_nocache(niureg_base, niureg_len); + np->regs = pci_ioremap_bar(pdev, 0); if (!np->regs) { dev_err(&pdev->dev, PFX "Cannot map device registers, " "aborting.\n"); diff --git a/drivers/net/niu.h b/drivers/net/niu.h index c6fa883daa22..180ca8ae93de 100644 --- a/drivers/net/niu.h +++ b/drivers/net/niu.h @@ -1048,6 +1048,13 @@ #define PLL_CFG_LD_SHIFT 8 #define PLL_CFG_MPY 0x0000001e #define PLL_CFG_MPY_SHIFT 1 +#define PLL_CFG_MPY_4X 0x0 +#define PLL_CFG_MPY_5X 0x00000002 +#define PLL_CFG_MPY_6X 0x00000004 +#define PLL_CFG_MPY_8X 0x00000008 +#define PLL_CFG_MPY_10X 0x0000000a +#define PLL_CFG_MPY_12X 0x0000000c +#define PLL_CFG_MPY_12P5X 0x0000000e #define PLL_CFG_ENPLL 0x00000001 #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002) @@ -1093,6 +1100,9 @@ #define PLL_TX_CFG_INVPAIR 0x00000080 #define PLL_TX_CFG_RATE 0x00000060 #define PLL_TX_CFG_RATE_SHIFT 5 +#define PLL_TX_CFG_RATE_FULL 0x0 +#define PLL_TX_CFG_RATE_HALF 0x20 +#define PLL_TX_CFG_RATE_QUAD 0x40 #define PLL_TX_CFG_BUSWIDTH 0x0000001c #define PLL_TX_CFG_BUSWIDTH_SHIFT 2 #define PLL_TX_CFG_ENTEST 0x00000002 @@ -1132,6 +1142,9 @@ #define PLL_RX_CFG_INVPAIR 0x00000080 #define PLL_RX_CFG_RATE 0x00000060 #define PLL_RX_CFG_RATE_SHIFT 5 +#define PLL_RX_CFG_RATE_FULL 0x0 +#define PLL_RX_CFG_RATE_HALF 0x20 +#define PLL_RX_CFG_RATE_QUAD 0x40 #define PLL_RX_CFG_BUSWIDTH 0x0000001c #define PLL_RX_CFG_BUSWIDTH_SHIFT 2 #define PLL_RX_CFG_ENTEST 0x00000002 diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c index b37a498939ae..0418045166c3 100644 --- a/drivers/net/pcmcia/axnet_cs.c +++ b/drivers/net/pcmcia/axnet_cs.c @@ -779,6 +779,7 @@ static struct pcmcia_device_id axnet_ids[] = { PCMCIA_DEVICE_PROD_ID12("IO DATA", "ETXPCM", 0x547e66dc, 0x233adac2), PCMCIA_DEVICE_PROD_ID12("Linksys", "EtherFast 10/100 PC Card (PCMPC100 V3)", 0x0733cc81, 0x232019a8), PCMCIA_DEVICE_PROD_ID12("MELCO", "LPC3-TX", 0x481e0094, 0xf91af609), + PCMCIA_DEVICE_PROD_ID12("NETGEAR", "FA411", 0x9aa79dc3, 0x40fad875), PCMCIA_DEVICE_PROD_ID12("PCMCIA", "100BASE", 0x281f1c5d, 0x7c2add04), PCMCIA_DEVICE_PROD_ID12("PCMCIA", "FastEtherCard", 0x281f1c5d, 0x7ef26116), PCMCIA_DEVICE_PROD_ID12("PCMCIA", "FEP501", 0x281f1c5d, 0x2e272058), @@ -1174,7 +1175,6 @@ static int ei_start_xmit(struct sk_buff *skb, struct net_device *dev) * ax_interrupt - handle the interrupts from an 8390 * @irq: interrupt number * @dev_id: a pointer to the net_device - * @regs: unused * * Handle the ether interface interrupts. We pull packets from * the 8390 via the card specific functions and fire them at the networking diff --git a/drivers/net/pcmcia/ibmtr_cs.c b/drivers/net/pcmcia/ibmtr_cs.c index cf3cca4642f2..f51944b28cfa 100644 --- a/drivers/net/pcmcia/ibmtr_cs.c +++ b/drivers/net/pcmcia/ibmtr_cs.c @@ -349,7 +349,7 @@ static int ibmtr_suspend(struct pcmcia_device *link) return 0; } -static int ibmtr_resume(struct pcmcia_device *link) +static int __devinit ibmtr_resume(struct pcmcia_device *link) { ibmtr_dev_t *info = link->priv; struct net_device *dev = info->dev; diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c index e40d6301aa7a..ce486f094492 100644 --- a/drivers/net/pcmcia/pcnet_cs.c +++ b/drivers/net/pcmcia/pcnet_cs.c @@ -1693,7 +1693,6 @@ static struct pcmcia_device_id pcnet_ids[] = { PCMCIA_DEVICE_PROD_ID12("National Semiconductor", "InfoMover NE4100", 0x36e1191f, 0xa6617ec8), PCMCIA_DEVICE_PROD_ID12("NEC", "PC-9801N-J12", 0x18df0ba0, 0xbc912d76), PCMCIA_DEVICE_PROD_ID12("NETGEAR", "FA410TX", 0x9aa79dc3, 0x60e5bc0e), - PCMCIA_DEVICE_PROD_ID12("NETGEAR", "FA411", 0x9aa79dc3, 0x40fad875), PCMCIA_DEVICE_PROD_ID12("Network Everywhere", "Fast Ethernet 10/100 PC Card", 0x820a67b6, 0x31ed1a5f), PCMCIA_DEVICE_PROD_ID12("NextCom K.K.", "Next Hawk", 0xaedaec74, 0xad050ef1), PCMCIA_DEVICE_PROD_ID12("PCMCIA", "10/100Mbps Ethernet Card", 0x281f1c5d, 0x6e41773b), diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 4aa547947040..eb6411c4694f 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -227,6 +227,59 @@ static int m88e1111_config_init(struct phy_device *phydev) return 0; } +static int m88e1118_config_aneg(struct phy_device *phydev) +{ + int err; + + err = phy_write(phydev, MII_BMCR, BMCR_RESET); + if (err < 0) + return err; + + err = phy_write(phydev, MII_M1011_PHY_SCR, + MII_M1011_PHY_SCR_AUTO_CROSS); + if (err < 0) + return err; + + err = genphy_config_aneg(phydev); + return 0; +} + +static int m88e1118_config_init(struct phy_device *phydev) +{ + int err; + + /* Change address */ + err = phy_write(phydev, 0x16, 0x0002); + if (err < 0) + return err; + + /* Enable 1000 Mbit */ + err = phy_write(phydev, 0x15, 0x1070); + if (err < 0) + return err; + + /* Change address */ + err = phy_write(phydev, 0x16, 0x0003); + if (err < 0) + return err; + + /* Adjust LED Control */ + err = phy_write(phydev, 0x10, 0x021e); + if (err < 0) + return err; + + /* Reset address */ + err = phy_write(phydev, 0x16, 0x0); + if (err < 0) + return err; + + err = phy_write(phydev, MII_BMCR, BMCR_RESET); + if (err < 0) + return err; + + return 0; +} + static int m88e1145_config_init(struct phy_device *phydev) { int err; @@ -415,6 +468,19 @@ static struct phy_driver marvell_drivers[] = { .config_intr = &marvell_config_intr, .driver = { .owner = THIS_MODULE }, }, + { + .phy_id = 0x01410e10, + .phy_id_mask = 0xfffffff0, + .name = "Marvell 88E1118", + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_init = &m88e1118_config_init, + .config_aneg = &m88e1118_config_aneg, + .read_status = &genphy_read_status, + .ack_interrupt = &marvell_ack_interrupt, + .config_intr = &marvell_config_intr, + .driver = {.owner = THIS_MODULE,}, + }, { .phy_id = 0x01410cd0, .phy_id_mask = 0xfffffff0, diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index d0ed1ef284a8..289fc267edf3 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -105,8 +105,6 @@ int mdiobus_register(struct mii_bus *bus) return -EINVAL; } - bus->state = MDIOBUS_REGISTERED; - mutex_init(&bus->mdio_lock); if (bus->reset) @@ -123,6 +121,9 @@ int mdiobus_register(struct mii_bus *bus) } } + if (!err) + bus->state = MDIOBUS_REGISTERED; + pr_info("%s: probed\n", bus->name); return err; @@ -136,7 +137,7 @@ void mdiobus_unregister(struct mii_bus *bus) BUG_ON(bus->state != MDIOBUS_REGISTERED); bus->state = MDIOBUS_UNREGISTERED; - device_unregister(&bus->dev); + device_del(&bus->dev); for (i = 0; i < PHY_MAX_ADDR; i++) { if (bus->phy_map[i]) device_unregister(&bus->phy_map[i]->dev); diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index e11b03b2b25a..25acbbde4a60 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -227,8 +227,17 @@ struct phy_device * get_phy_device(struct mii_bus *bus, int addr) if (r) return ERR_PTR(r); - /* If the phy_id is all Fs, there is no device there */ - if (0xffffffff == phy_id) + /* If the phy_id is mostly Fs, there is no device there */ + if ((phy_id & 0x1fffffff) == 0x1fffffff) + return NULL; + + /* + * Broken hardware is sometimes missing the pull down resistor on the + * MDIO line, which results in reads to non-existent devices returning + * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent + * device as well. + */ + if (phy_id == 0) return NULL; dev = phy_device_create(bus, addr, phy_id); @@ -564,20 +573,32 @@ EXPORT_SYMBOL(genphy_restart_aneg); */ int genphy_config_aneg(struct phy_device *phydev) { - int result = 0; + int result; - if (AUTONEG_ENABLE == phydev->autoneg) { - int result = genphy_config_advert(phydev); + if (AUTONEG_ENABLE != phydev->autoneg) + return genphy_setup_forced(phydev); - if (result < 0) /* error */ - return result; + result = genphy_config_advert(phydev); + + if (result < 0) /* error */ + return result; + + if (result == 0) { + /* Advertisment hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? */ + int ctl = phy_read(phydev, MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) + result = 1; /* do restart aneg */ + } - /* Only restart aneg if we are advertising something different - * than we were before. */ - if (result > 0) - result = genphy_restart_aneg(phydev); - } else - result = genphy_setup_forced(phydev); + /* Only restart aneg if we are advertising something different + * than we were before. */ + if (result > 0) + result = genphy_restart_aneg(phydev); return result; } diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 8874497b6bbf..dd3b2447e85a 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -34,6 +34,8 @@ #define MII_VSC8244_IMASK_DUPLEX 0x1000 #define MII_VSC8244_IMASK_MASK 0xf000 +#define MII_VSC8221_IMASK_MASK 0xa000 + /* Vitesse Interrupt Status Register */ #define MII_VSC8244_ISTAT 0x1a #define MII_VSC8244_ISTAT_STATUS 0x8000 @@ -49,6 +51,12 @@ #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010 #define MII_VSC8244_AUXCONSTAT_100 0x0008 +#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */ +#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004 + +#define PHY_ID_VSC8244 0x000fc6c0 +#define PHY_ID_VSC8221 0x000fc550 + MODULE_DESCRIPTION("Vitesse PHY driver"); MODULE_AUTHOR("Kriston Carson"); MODULE_LICENSE("GPL"); @@ -95,13 +103,15 @@ static int vsc824x_ack_interrupt(struct phy_device *phydev) return (err < 0) ? err : 0; } -static int vsc824x_config_intr(struct phy_device *phydev) +static int vsc82xx_config_intr(struct phy_device *phydev) { int err; if (phydev->interrupts == PHY_INTERRUPT_ENABLED) err = phy_write(phydev, MII_VSC8244_IMASK, - MII_VSC8244_IMASK_MASK); + phydev->drv->phy_id == PHY_ID_VSC8244 ? + MII_VSC8244_IMASK_MASK : + MII_VSC8221_IMASK_MASK); else { /* * The Vitesse PHY cannot clear the interrupt @@ -120,7 +130,7 @@ static int vsc824x_config_intr(struct phy_device *phydev) /* Vitesse 824x */ static struct phy_driver vsc8244_driver = { - .phy_id = 0x000fc6c0, + .phy_id = PHY_ID_VSC8244, .name = "Vitesse VSC8244", .phy_id_mask = 0x000fffc0, .features = PHY_GBIT_FEATURES, @@ -129,19 +139,55 @@ static struct phy_driver vsc8244_driver = { .config_aneg = &genphy_config_aneg, .read_status = &genphy_read_status, .ack_interrupt = &vsc824x_ack_interrupt, - .config_intr = &vsc824x_config_intr, + .config_intr = &vsc82xx_config_intr, .driver = { .owner = THIS_MODULE,}, }; -static int __init vsc8244_init(void) +static int vsc8221_config_init(struct phy_device *phydev) { - return phy_driver_register(&vsc8244_driver); + int err; + + err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, + MII_VSC8221_AUXCONSTAT_INIT); + return err; + + /* Perhaps we should set EXT_CON1 based on the interface? + Options are 802.3Z SerDes or SGMII */ +} + +/* Vitesse 8221 */ +static struct phy_driver vsc8221_driver = { + .phy_id = PHY_ID_VSC8221, + .phy_id_mask = 0x000ffff0, + .name = "Vitesse VSC8221", + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_init = &vsc8221_config_init, + .config_aneg = &genphy_config_aneg, + .read_status = &genphy_read_status, + .ack_interrupt = &vsc824x_ack_interrupt, + .config_intr = &vsc82xx_config_intr, + .driver = { .owner = THIS_MODULE,}, +}; + +static int __init vsc82xx_init(void) +{ + int err; + + err = phy_driver_register(&vsc8244_driver); + if (err < 0) + return err; + err = phy_driver_register(&vsc8221_driver); + if (err < 0) + phy_driver_unregister(&vsc8244_driver); + return err; } -static void __exit vsc8244_exit(void) +static void __exit vsc82xx_exit(void) { phy_driver_unregister(&vsc8244_driver); + phy_driver_unregister(&vsc8221_driver); } -module_init(vsc8244_init); -module_exit(vsc8244_exit); +module_init(vsc82xx_init); +module_exit(vsc82xx_exit); diff --git a/drivers/net/pppoe.c b/drivers/net/pppoe.c index fc6f4b8c64b3..b646e92134dc 100644 --- a/drivers/net/pppoe.c +++ b/drivers/net/pppoe.c @@ -399,11 +399,11 @@ static int pppoe_rcv(struct sk_buff *skb, if (skb->len < len) goto drop; - po = get_item(ph->sid, eth_hdr(skb)->h_source, dev->ifindex); - if (!po) + if (pskb_trim_rcsum(skb, len)) goto drop; - if (pskb_trim_rcsum(skb, len)) + po = get_item(ph->sid, eth_hdr(skb)->h_source, dev->ifindex); + if (!po) goto drop; return sk_receive_skb(sk_pppox(po), skb, 0); diff --git a/drivers/net/pppol2tp.c b/drivers/net/pppol2tp.c index 185b1dff10a8..e98d9773158d 100644 --- a/drivers/net/pppol2tp.c +++ b/drivers/net/pppol2tp.c @@ -1353,6 +1353,7 @@ static int pppol2tp_release(struct socket *sock) kfree_skb(skb); sock_put(sk); } + sock_put(sk); } release_sock(sk); diff --git a/drivers/net/qla3xxx.c b/drivers/net/qla3xxx.c index 3cdd07c45b6d..508452c02151 100644 --- a/drivers/net/qla3xxx.c +++ b/drivers/net/qla3xxx.c @@ -1515,9 +1515,6 @@ static u32 ql_get_link_state(struct ql3_adapter *qdev) linkState = LS_UP; } else { linkState = LS_DOWN; - if (netif_msg_link(qdev)) - printk(KERN_WARNING PFX - "%s: Link is down.\n", qdev->ndev->name); } return linkState; } @@ -1581,10 +1578,6 @@ static int ql_finish_auto_neg(struct ql3_adapter *qdev) ql_mac_enable(qdev, 1); } - if (netif_msg_link(qdev)) - printk(KERN_DEBUG PFX - "%s: Change port_link_state LS_DOWN to LS_UP.\n", - qdev->ndev->name); qdev->port_link_state = LS_UP; netif_start_queue(qdev->ndev); netif_carrier_on(qdev->ndev); @@ -1655,14 +1648,9 @@ static void ql_link_state_machine_work(struct work_struct *work) /* Fall Through */ case LS_DOWN: - if (netif_msg_link(qdev)) - printk(KERN_DEBUG PFX - "%s: port_link_state = LS_DOWN.\n", - qdev->ndev->name); if (curr_link_state == LS_UP) { if (netif_msg_link(qdev)) - printk(KERN_DEBUG PFX - "%s: curr_link_state = LS_UP.\n", + printk(KERN_INFO PFX "%s: Link is up.\n", qdev->ndev->name); if (ql_is_auto_neg_complete(qdev)) ql_finish_auto_neg(qdev); @@ -1670,6 +1658,7 @@ static void ql_link_state_machine_work(struct work_struct *work) if (qdev->port_link_state == LS_UP) ql_link_down_detect_clear(qdev); + qdev->port_link_state = LS_UP; } break; @@ -1678,12 +1667,14 @@ static void ql_link_state_machine_work(struct work_struct *work) * See if the link is currently down or went down and came * back up */ - if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) { + if (curr_link_state == LS_DOWN) { if (netif_msg_link(qdev)) printk(KERN_INFO PFX "%s: Link is down.\n", qdev->ndev->name); qdev->port_link_state = LS_DOWN; } + if (ql_link_down_detect(qdev)) + qdev->port_link_state = LS_DOWN; break; } spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); diff --git a/drivers/net/sfc/ethtool.c b/drivers/net/sfc/ethtool.c index fa98af58223e..cd0d0873d978 100644 --- a/drivers/net/sfc/ethtool.c +++ b/drivers/net/sfc/ethtool.c @@ -174,8 +174,8 @@ static struct efx_ethtool_stat efx_ethtool_stats[] = { /* EEPROM range with gPXE configuration */ #define EFX_ETHTOOL_EEPROM_MAGIC 0xEFAB -#define EFX_ETHTOOL_EEPROM_MIN 0x100U -#define EFX_ETHTOOL_EEPROM_MAX 0x400U +#define EFX_ETHTOOL_EEPROM_MIN 0x800U +#define EFX_ETHTOOL_EEPROM_MAX 0x1800U /************************************************************************** * diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index a24bb68887ab..59f242a67714 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -927,7 +927,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_txdesc *txdesc; u32 entry; - int flags; + unsigned long flags; spin_lock_irqsave(&mdp->lock, flags); if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) { @@ -1141,7 +1141,7 @@ static int sh_mdio_init(struct net_device *ndev, int id) /* Hook up MII support for ethtool */ mdp->mii_bus->name = "sh_mii"; mdp->mii_bus->parent = &ndev->dev; - mdp->mii_bus->id[0] = id; + snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id); /* PHY IRQ */ mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); diff --git a/drivers/net/sis900.c b/drivers/net/sis900.c index fa3a460f8e2f..8e8337e8b072 100644 --- a/drivers/net/sis900.c +++ b/drivers/net/sis900.c @@ -1630,7 +1630,6 @@ sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev) * sis900_interrupt - sis900 interrupt handler * @irq: the irq number * @dev_instance: the client data object - * @regs: snapshot of processor context * * The interrupt handler does all of the Rx thread work, * and cleans up after the Tx thread diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index f59c7772f344..9a16a79b67d0 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -499,7 +499,7 @@ static void smc911x_hardware_send_pkt(struct net_device *dev) #else SMC_PUSH_DATA(lp, buf, len); dev->trans_start = jiffies; - dev_kfree_skb(skb); + dev_kfree_skb_irq(skb); #endif if (!lp->tx_throttle) { netif_wake_queue(dev); @@ -1735,7 +1735,7 @@ static const struct ethtool_ops smc911x_ethtool_ops = { * This routine has a simple purpose -- make the SMC chip generate an * interrupt, so an auto-detect routine can detect it, and find the IRQ, */ -static int __init smc911x_findirq(struct net_device *dev) +static int __devinit smc911x_findirq(struct net_device *dev) { struct smc911x_local *lp = netdev_priv(dev); int timeout = 20; @@ -1799,7 +1799,7 @@ static int __init smc911x_findirq(struct net_device *dev) * o actually GRAB the irq. * o GRAB the region */ -static int __init smc911x_probe(struct net_device *dev) +static int __devinit smc911x_probe(struct net_device *dev) { struct smc911x_local *lp = netdev_priv(dev); int i, retval; @@ -1813,7 +1813,7 @@ static int __init smc911x_probe(struct net_device *dev) val = SMC_GET_BYTE_TEST(lp); DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val); if (val != 0x87654321) { - printk(KERN_ERR "Invalid chip endian 0x08%x\n",val); + printk(KERN_ERR "Invalid chip endian 0x%08x\n",val); retval = -ENODEV; goto err_out; } @@ -2048,9 +2048,11 @@ err_out: * 0 --> there is a device * anything else, error */ -static int smc911x_drv_probe(struct platform_device *pdev) +static int __devinit smc911x_drv_probe(struct platform_device *pdev) { +#ifdef SMC_DYNAMIC_BUS_CONFIG struct smc911x_platdata *pd = pdev->dev.platform_data; +#endif struct net_device *ndev; struct resource *res; struct smc911x_local *lp; @@ -2122,7 +2124,7 @@ out: return ret; } -static int smc911x_drv_remove(struct platform_device *pdev) +static int __devexit smc911x_drv_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct smc911x_local *lp = netdev_priv(ndev); @@ -2182,9 +2184,9 @@ static int smc911x_drv_resume(struct platform_device *dev) if (netif_running(ndev)) { smc911x_reset(ndev); - smc911x_enable(ndev); if (lp->phy_type != 0) smc911x_phy_configure(&lp->phy_configure); + smc911x_enable(ndev); netif_device_attach(ndev); } } @@ -2193,7 +2195,7 @@ static int smc911x_drv_resume(struct platform_device *dev) static struct platform_driver smc911x_driver = { .probe = smc911x_drv_probe, - .remove = smc911x_drv_remove, + .remove = __devexit_p(smc911x_drv_remove), .suspend = smc911x_drv_suspend, .resume = smc911x_drv_resume, .driver = { diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c index c70870e0fd61..35c56abf4113 100644 --- a/drivers/net/smc91x.c +++ b/drivers/net/smc91x.c @@ -1696,7 +1696,7 @@ static const struct ethtool_ops smc_ethtool_ops = { * I just deleted auto_irq.c, since it was never built... * --jgarzik */ -static int __init smc_findirq(struct smc_local *lp) +static int __devinit smc_findirq(struct smc_local *lp) { void __iomem *ioaddr = lp->base; int timeout = 20; @@ -1770,7 +1770,7 @@ static int __init smc_findirq(struct smc_local *lp) * o actually GRAB the irq. * o GRAB the region */ -static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr, +static int __devinit smc_probe(struct net_device *dev, void __iomem *ioaddr, unsigned long irq_flags) { struct smc_local *lp = netdev_priv(dev); @@ -2060,7 +2060,7 @@ static int smc_request_attrib(struct platform_device *pdev, struct net_device *ndev) { struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); - struct smc_local *lp = netdev_priv(ndev); + struct smc_local *lp __maybe_unused = netdev_priv(ndev); if (!res) return 0; @@ -2075,7 +2075,7 @@ static void smc_release_attrib(struct platform_device *pdev, struct net_device *ndev) { struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); - struct smc_local *lp = netdev_priv(ndev); + struct smc_local *lp __maybe_unused = netdev_priv(ndev); if (res) release_mem_region(res->start, ATTRIB_SIZE); @@ -2126,7 +2126,7 @@ static void smc_release_datacs(struct platform_device *pdev, struct net_device * * 0 --> there is a device * anything else, error */ -static int smc_drv_probe(struct platform_device *pdev) +static int __devinit smc_drv_probe(struct platform_device *pdev) { struct smc91x_platdata *pd = pdev->dev.platform_data; struct smc_local *lp; @@ -2240,7 +2240,7 @@ static int smc_drv_probe(struct platform_device *pdev) return ret; } -static int smc_drv_remove(struct platform_device *pdev) +static int __devexit smc_drv_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct smc_local *lp = netdev_priv(ndev); @@ -2305,7 +2305,7 @@ static int smc_drv_resume(struct platform_device *dev) static struct platform_driver smc_driver = { .probe = smc_drv_probe, - .remove = smc_drv_remove, + .remove = __devexit_p(smc_drv_remove), .suspend = smc_drv_suspend, .resume = smc_drv_resume, .driver = { diff --git a/drivers/net/spider_net.c b/drivers/net/spider_net.c index b6435d0d71f9..07599b492359 100644 --- a/drivers/net/spider_net.c +++ b/drivers/net/spider_net.c @@ -672,7 +672,6 @@ write_hash: /** * spider_net_prepare_tx_descr - fill tx descriptor with skb data * @card: card structure - * @descr: descriptor structure to fill out * @skb: packet to use * * returns 0 on success, <0 on failure. @@ -867,7 +866,6 @@ spider_net_release_tx_chain(struct spider_net_card *card, int brutal) /** * spider_net_kick_tx_dma - enables TX DMA processing * @card: card structure - * @descr: descriptor address to enable TX processing at * * This routine will start the transmit DMA running if * it is not already running. This routine ned only be @@ -1637,7 +1635,6 @@ spider_net_handle_error_irq(struct spider_net_card *card, u32 status_reg, * spider_net_interrupt - interrupt handler for spider_net * @irq: interrupt number * @ptr: pointer to net_device - * @regs: PU registers * * returns IRQ_HANDLED, if interrupt was for driver, or IRQ_NONE, if no * interrupt found raised by card. @@ -2419,7 +2416,6 @@ spider_net_undo_pci_setup(struct spider_net_card *card) /** * spider_net_setup_pci_dev - sets up the device in terms of PCI operations - * @card: card structure * @pdev: PCI device * * Returns the card structure or NULL if any errors occur diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c index 1d2ef8f47780..5a40f2d78beb 100644 --- a/drivers/net/starfire.c +++ b/drivers/net/starfire.c @@ -1509,6 +1509,11 @@ static int __netdev_rx(struct net_device *dev, int *quota) desc->status = 0; np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE; } + + if (*quota == 0) { /* out of rx quota */ + retcode = 1; + goto out; + } writew(np->rx_done, np->base + CompletionQConsumerIdx); out: diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c index 4291458955ef..fed7eba65ead 100644 --- a/drivers/net/sungem.c +++ b/drivers/net/sungem.c @@ -1142,6 +1142,70 @@ static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev) return NETDEV_TX_OK; } +static void gem_pcs_reset(struct gem *gp) +{ + int limit; + u32 val; + + /* Reset PCS unit. */ + val = readl(gp->regs + PCS_MIICTRL); + val |= PCS_MIICTRL_RST; + writel(val, gp->regs + PCS_MIICTRL); + + limit = 32; + while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { + udelay(100); + if (limit-- <= 0) + break; + } + if (limit <= 0) + printk(KERN_WARNING "%s: PCS reset bit would not clear.\n", + gp->dev->name); +} + +static void gem_pcs_reinit_adv(struct gem *gp) +{ + u32 val; + + /* Make sure PCS is disabled while changing advertisement + * configuration. + */ + val = readl(gp->regs + PCS_CFG); + val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO); + writel(val, gp->regs + PCS_CFG); + + /* Advertise all capabilities except assymetric + * pause. + */ + val = readl(gp->regs + PCS_MIIADV); + val |= (PCS_MIIADV_FD | PCS_MIIADV_HD | + PCS_MIIADV_SP | PCS_MIIADV_AP); + writel(val, gp->regs + PCS_MIIADV); + + /* Enable and restart auto-negotiation, disable wrapback/loopback, + * and re-enable PCS. + */ + val = readl(gp->regs + PCS_MIICTRL); + val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE); + val &= ~PCS_MIICTRL_WB; + writel(val, gp->regs + PCS_MIICTRL); + + val = readl(gp->regs + PCS_CFG); + val |= PCS_CFG_ENABLE; + writel(val, gp->regs + PCS_CFG); + + /* Make sure serialink loopback is off. The meaning + * of this bit is logically inverted based upon whether + * you are in Serialink or SERDES mode. + */ + val = readl(gp->regs + PCS_SCTRL); + if (gp->phy_type == phy_serialink) + val &= ~PCS_SCTRL_LOOP; + else + val |= PCS_SCTRL_LOOP; + writel(val, gp->regs + PCS_SCTRL); +} + #define STOP_TRIES 32 /* Must be invoked under gp->lock and gp->tx_lock. */ @@ -1168,6 +1232,9 @@ static void gem_reset(struct gem *gp) if (limit <= 0) printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name); + + if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) + gem_pcs_reinit_adv(gp); } /* Must be invoked under gp->lock and gp->tx_lock. */ @@ -1324,7 +1391,7 @@ static int gem_set_link_modes(struct gem *gp) gp->phy_type == phy_serdes) { u32 pcs_lpa = readl(gp->regs + PCS_MIILP); - if (pcs_lpa & PCS_MIIADV_FD) + if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) full_duplex = 1; speed = SPEED_1000; } @@ -1488,6 +1555,9 @@ static void gem_link_timer(unsigned long data) val = readl(gp->regs + PCS_MIISTAT); if ((val & PCS_MIISTAT_LS) != 0) { + if (gp->lstate == link_up) + goto restart; + gp->lstate = link_up; netif_carrier_on(gp->dev); (void)gem_set_link_modes(gp); @@ -1708,61 +1778,8 @@ static void gem_init_phy(struct gem *gp) if (gp->phy_mii.def && gp->phy_mii.def->ops->init) gp->phy_mii.def->ops->init(&gp->phy_mii); } else { - u32 val; - int limit; - - /* Reset PCS unit. */ - val = readl(gp->regs + PCS_MIICTRL); - val |= PCS_MIICTRL_RST; - writeb(val, gp->regs + PCS_MIICTRL); - - limit = 32; - while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { - udelay(100); - if (limit-- <= 0) - break; - } - if (limit <= 0) - printk(KERN_WARNING "%s: PCS reset bit would not clear.\n", - gp->dev->name); - - /* Make sure PCS is disabled while changing advertisement - * configuration. - */ - val = readl(gp->regs + PCS_CFG); - val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO); - writel(val, gp->regs + PCS_CFG); - - /* Advertise all capabilities except assymetric - * pause. - */ - val = readl(gp->regs + PCS_MIIADV); - val |= (PCS_MIIADV_FD | PCS_MIIADV_HD | - PCS_MIIADV_SP | PCS_MIIADV_AP); - writel(val, gp->regs + PCS_MIIADV); - - /* Enable and restart auto-negotiation, disable wrapback/loopback, - * and re-enable PCS. - */ - val = readl(gp->regs + PCS_MIICTRL); - val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE); - val &= ~PCS_MIICTRL_WB; - writel(val, gp->regs + PCS_MIICTRL); - - val = readl(gp->regs + PCS_CFG); - val |= PCS_CFG_ENABLE; - writel(val, gp->regs + PCS_CFG); - - /* Make sure serialink loopback is off. The meaning - * of this bit is logically inverted based upon whether - * you are in Serialink or SERDES mode. - */ - val = readl(gp->regs + PCS_SCTRL); - if (gp->phy_type == phy_serialink) - val &= ~PCS_SCTRL_LOOP; - else - val |= PCS_SCTRL_LOOP; - writel(val, gp->regs + PCS_SCTRL); + gem_pcs_reset(gp); + gem_pcs_reinit_adv(gp); } /* Default aneg parameters */ @@ -2680,6 +2697,21 @@ static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) cmd->speed = 0; cmd->duplex = cmd->port = cmd->phy_address = cmd->transceiver = cmd->autoneg = 0; + + /* serdes means usually a Fibre connector, with most fixed */ + if (gp->phy_type == phy_serdes) { + cmd->port = PORT_FIBRE; + cmd->supported = (SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full | + SUPPORTED_FIBRE | SUPPORTED_Autoneg | + SUPPORTED_Pause | SUPPORTED_Asym_Pause); + cmd->advertising = cmd->supported; + cmd->transceiver = XCVR_INTERNAL; + if (gp->lstate == link_up) + cmd->speed = SPEED_1000; + cmd->duplex = DUPLEX_FULL; + cmd->autoneg = 1; + } } cmd->maxtxpkt = cmd->maxrxpkt = 0; diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c index c41d68761364..e60498232b94 100644 --- a/drivers/net/tlan.c +++ b/drivers/net/tlan.c @@ -1098,6 +1098,7 @@ static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev ) dma_addr_t tail_list_phys; u8 *tail_buffer; unsigned long flags; + unsigned int txlen; if ( ! priv->phyOnline ) { TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n", @@ -1108,6 +1109,7 @@ static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev ) if (skb_padto(skb, TLAN_MIN_FRAME_SIZE)) return 0; + txlen = max(skb->len, (unsigned int)TLAN_MIN_FRAME_SIZE); tail_list = priv->txList + priv->txTail; tail_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txTail; @@ -1125,16 +1127,16 @@ static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev ) if ( bbuf ) { tail_buffer = priv->txBuffer + ( priv->txTail * TLAN_MAX_FRAME_SIZE ); - skb_copy_from_linear_data(skb, tail_buffer, skb->len); + skb_copy_from_linear_data(skb, tail_buffer, txlen); } else { tail_list->buffer[0].address = pci_map_single(priv->pciDev, - skb->data, skb->len, + skb->data, txlen, PCI_DMA_TODEVICE); TLan_StoreSKB(tail_list, skb); } - tail_list->frameSize = (u16) skb->len; - tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) skb->len; + tail_list->frameSize = (u16) txlen; + tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) txlen; tail_list->buffer[1].count = 0; tail_list->buffer[1].address = 0; @@ -1431,7 +1433,9 @@ static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int ) if ( ! bbuf ) { struct sk_buff *skb = TLan_GetSKB(head_list); pci_unmap_single(priv->pciDev, head_list->buffer[0].address, - skb->len, PCI_DMA_TODEVICE); + max(skb->len, + (unsigned int)TLAN_MIN_FRAME_SIZE), + PCI_DMA_TODEVICE); dev_kfree_skb_any(skb); head_list->buffer[8].address = 0; head_list->buffer[9].address = 0; @@ -2055,9 +2059,12 @@ static void TLan_FreeLists( struct net_device *dev ) list = priv->txList + i; skb = TLan_GetSKB(list); if ( skb ) { - pci_unmap_single(priv->pciDev, - list->buffer[0].address, skb->len, - PCI_DMA_TODEVICE); + pci_unmap_single( + priv->pciDev, + list->buffer[0].address, + max(skb->len, + (unsigned int)TLAN_MIN_FRAME_SIZE), + PCI_DMA_TODEVICE); dev_kfree_skb_any( skb ); list->buffer[8].address = 0; list->buffer[9].address = 0; diff --git a/drivers/net/tulip/dmfe.c b/drivers/net/tulip/dmfe.c index 8e46a513a252..c91852f49a48 100644 --- a/drivers/net/tulip/dmfe.c +++ b/drivers/net/tulip/dmfe.c @@ -420,9 +420,13 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev, /* Allocate Tx/Rx descriptor memory */ db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); + if (!db->desc_pool_ptr) + goto err_out_res; db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); + if (!db->buf_pool_ptr) + goto err_out_free_desc; db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; db->first_tx_desc_dma = db->desc_pool_dma_ptr; @@ -469,7 +473,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev, err = register_netdev (dev); if (err) - goto err_out_res; + goto err_out_free_buf; printk(KERN_INFO "%s: Davicom DM%04lx at pci%s, " "%s, irq %d.\n", @@ -483,6 +487,12 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev, return 0; +err_out_free_buf: + pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, + db->buf_pool_ptr, db->buf_pool_dma_ptr); +err_out_free_desc: + pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, + db->desc_pool_ptr, db->desc_pool_dma_ptr); err_out_res: pci_release_regions(pdev); err_out_disable: diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 6daea0c91862..33b6d1b122fb 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1070,8 +1070,6 @@ static int tun_chr_close(struct inode *inode, struct file *file) DBG(KERN_INFO "%s: tun_chr_close\n", tun->dev->name); - tun_chr_fasync(-1, file, 0); - rtnl_lock(); /* Detach from net device */ diff --git a/drivers/net/ucc_geth_ethtool.c b/drivers/net/ucc_geth_ethtool.c index cfbbfee55836..68a7f5414133 100644 --- a/drivers/net/ucc_geth_ethtool.c +++ b/drivers/net/ucc_geth_ethtool.c @@ -37,7 +37,6 @@ #include #include #include -#include #include "ucc_geth.h" #include "ucc_geth_mii.h" @@ -324,17 +323,17 @@ static void uec_get_ethtool_stats(struct net_device *netdev, if (stats_mode & UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE) { base = (u32 __iomem *)&ugeth->ug_regs->tx64; for (i = 0; i < UEC_HW_STATS_LEN; i++) - data[j++] = (u64)in_be32(&base[i]); + data[j++] = in_be32(&base[i]); } if (stats_mode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { base = (u32 __iomem *)ugeth->p_tx_fw_statistics_pram; for (i = 0; i < UEC_TX_FW_STATS_LEN; i++) - data[j++] = (u64)in_be32(&base[i]); + data[j++] = base ? in_be32(&base[i]) : 0; } if (stats_mode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { base = (u32 __iomem *)ugeth->p_rx_fw_statistics_pram; for (i = 0; i < UEC_RX_FW_STATS_LEN; i++) - data[j++] = (u64)in_be32(&base[i]); + data[j++] = base ? in_be32(&base[i]) : 0; } } diff --git a/drivers/net/usb/asix.c b/drivers/net/usb/asix.c index 37ecf845edfe..de57490103fc 100644 --- a/drivers/net/usb/asix.c +++ b/drivers/net/usb/asix.c @@ -1102,12 +1102,14 @@ static int ax88178_link_reset(struct usbnet *dev) mode = AX88178_MEDIUM_DEFAULT; if (ecmd.speed == SPEED_1000) - mode |= AX_MEDIUM_GM | AX_MEDIUM_ENCK; + mode |= AX_MEDIUM_GM; else if (ecmd.speed == SPEED_100) mode |= AX_MEDIUM_PS; else mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); + mode |= AX_MEDIUM_ENCK; + if (ecmd.duplex == DUPLEX_FULL) mode |= AX_MEDIUM_FD; else @@ -1444,6 +1446,10 @@ static const struct usb_device_id products [] = { // Apple USB Ethernet Adapter USB_DEVICE(0x05ac, 0x1402), .driver_info = (unsigned long) &ax88772_info, +}, { + // Cables-to-Go USB Ethernet Adapter + USB_DEVICE(0x0b95, 0x772a), + .driver_info = (unsigned long) &ax88772_info, }, { }, // END }; diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c index 78df2be8a728..db3377dae9d5 100644 --- a/drivers/net/usb/dm9601.c +++ b/drivers/net/usb/dm9601.c @@ -396,6 +396,20 @@ static void dm9601_set_multicast(struct net_device *net) dm_write_reg_async(dev, DM_RX_CTRL, rx_ctl); } +static int dm9601_set_mac_address(struct net_device *net, void *p) +{ + struct sockaddr *addr = p; + struct usbnet *dev = netdev_priv(net); + + if (!is_valid_ether_addr(addr->sa_data)) + return -EINVAL; + + memcpy(net->dev_addr, addr->sa_data, net->addr_len); + dm_write_async(dev, DM_PHY_ADDR, net->addr_len, net->dev_addr); + + return 0; +} + static int dm9601_bind(struct usbnet *dev, struct usb_interface *intf) { int ret; @@ -406,6 +420,7 @@ static int dm9601_bind(struct usbnet *dev, struct usb_interface *intf) dev->net->do_ioctl = dm9601_ioctl; dev->net->set_multicast_list = dm9601_set_multicast; + dev->net->set_mac_address = dm9601_set_mac_address; dev->net->ethtool_ops = &dm9601_ethtool_ops; dev->net->hard_header_len += DM_TX_OVERHEAD; dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c index 1164c52e2c0a..8e90891f0e42 100644 --- a/drivers/net/usb/hso.c +++ b/drivers/net/usb/hso.c @@ -2184,19 +2184,20 @@ static void hso_create_rfkill(struct hso_device *hso_dev, struct usb_interface *interface) { struct hso_net *hso_net = dev2net(hso_dev); - struct device *dev = hso_dev->dev; + struct device *dev = &hso_net->net->dev; char *rfkn; hso_net->rfkill = rfkill_allocate(&interface_to_usbdev(interface)->dev, - RFKILL_TYPE_WLAN); + RFKILL_TYPE_WWAN); if (!hso_net->rfkill) { - dev_err(dev, "%s - Out of memory", __func__); + dev_err(dev, "%s - Out of memory\n", __func__); return; } rfkn = kzalloc(20, GFP_KERNEL); if (!rfkn) { rfkill_free(hso_net->rfkill); - dev_err(dev, "%s - Out of memory", __func__); + hso_net->rfkill = NULL; + dev_err(dev, "%s - Out of memory\n", __func__); return; } snprintf(rfkn, 20, "hso-%d", @@ -2209,7 +2210,8 @@ static void hso_create_rfkill(struct hso_device *hso_dev, kfree(rfkn); hso_net->rfkill->name = NULL; rfkill_free(hso_net->rfkill); - dev_err(dev, "%s - Failed to register rfkill", __func__); + hso_net->rfkill = NULL; + dev_err(dev, "%s - Failed to register rfkill\n", __func__); return; } } diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index 2dced383bcfb..11cb3e504e1c 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c @@ -521,7 +521,7 @@ static void __devexit velocity_remove1(struct pci_dev *pdev) * we don't duplicate code for each option. */ -static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, char *devname) +static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, const char *devname) { if (val == -1) *opt = def; @@ -550,7 +550,7 @@ static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, * we don't duplicate code for each option. */ -static void __devinit velocity_set_bool_opt(u32 * opt, int val, int def, u32 flag, char *name, char *devname) +static void __devinit velocity_set_bool_opt(u32 * opt, int val, int def, u32 flag, char *name, const char *devname) { (*opt) &= (~flag); if (val == -1) @@ -576,7 +576,7 @@ static void __devinit velocity_set_bool_opt(u32 * opt, int val, int def, u32 fla * for the current device */ -static void __devinit velocity_get_options(struct velocity_opt *opts, int index, char *devname) +static void __devinit velocity_get_options(struct velocity_opt *opts, int index, const char *devname) { velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname); @@ -863,6 +863,7 @@ static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_devi static int first = 1; struct net_device *dev; int i; + const char *drv_string; const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data]; struct velocity_info *vptr; struct mac_regs __iomem * regs; @@ -935,7 +936,9 @@ static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_devi dev->dev_addr[i] = readb(®s->PAR[i]); - velocity_get_options(&vptr->options, velocity_nics, dev->name); + drv_string = dev_driver_string(&pdev->dev); + + velocity_get_options(&vptr->options, velocity_nics, drv_string); /* * Mask out the options cannot be set to the chip @@ -2293,7 +2296,7 @@ static void velocity_set_multi(struct net_device *dev) } mac_set_cam_mask(regs, vptr->mCAMmask); - rx_mode = (RCR_AM | RCR_AB); + rx_mode = RCR_AM | RCR_AB | RCR_AP; } if (dev->mtu > 1500) rx_mode |= RCR_AL; diff --git a/drivers/net/wan/syncppp.c b/drivers/net/wan/syncppp.c index 327d58589e12..6e92f7b44b1a 100644 --- a/drivers/net/wan/syncppp.c +++ b/drivers/net/wan/syncppp.c @@ -756,10 +756,11 @@ static void sppp_cisco_input (struct sppp *sp, struct sk_buff *skb) case CISCO_ADDR_REQ: /* Stolen from net/ipv4/devinet.c -- SIOCGIFADDR ioctl */ { - struct in_device *in_dev; - struct in_ifaddr *ifa; __be32 addr = 0, mask = htonl(~0U); /* FIXME: is the mask correct? */ #ifdef CONFIG_INET + struct in_device *in_dev; + struct in_ifaddr *ifa; + rcu_read_lock(); if ((in_dev = __in_dev_get_rcu(dev)) != NULL) { diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index ccd9cd35ecbe..5bf7e01ef0e9 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -695,7 +695,6 @@ EXPORT_SYMBOL(z8530_nop); * z8530_interrupt - Handle an interrupt from a Z8530 * @irq: Interrupt number * @dev_id: The Z8530 device that is interrupting. - * @regs: unused * * A Z85[2]30 device has stuck its hand in the air for attention. * We scan both the channels on the chip for events and then call diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index 0f1d6bdd51a2..2d14255eb103 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c @@ -240,6 +240,10 @@ static u64 ath5k_get_tsf(struct ieee80211_hw *hw); static void ath5k_reset_tsf(struct ieee80211_hw *hw); static int ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb); +static void ath5k_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *bss_conf, + u32 changes); static struct ieee80211_ops ath5k_hw_ops = { .tx = ath5k_tx, @@ -256,6 +260,7 @@ static struct ieee80211_ops ath5k_hw_ops = { .get_tx_stats = ath5k_get_tx_stats, .get_tsf = ath5k_get_tsf, .reset_tsf = ath5k_reset_tsf, + .bss_info_changed = ath5k_bss_info_changed, }; /* @@ -661,8 +666,7 @@ ath5k_pci_resume(struct pci_dev *pdev) { struct ieee80211_hw *hw = pci_get_drvdata(pdev); struct ath5k_softc *sc = hw->priv; - struct ath5k_hw *ah = sc->ah; - int i, err; + int err; pci_restore_state(pdev); @@ -688,16 +692,6 @@ ath5k_pci_resume(struct pci_dev *pdev) goto err_irq; ath5k_led_enable(sc); - /* - * Reset the key cache since some parts do not - * reset the contents on initial power up or resume. - * - * FIXME: This may need to be revisited when mac80211 becomes - * aware of suspend/resume. - */ - for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) - ath5k_hw_reset_key(ah, i); - return 0; err_irq: free_irq(pdev->irq, sc); @@ -718,7 +712,6 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) struct ath5k_softc *sc = hw->priv; struct ath5k_hw *ah = sc->ah; u8 mac[ETH_ALEN]; - unsigned int i; int ret; ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); @@ -736,13 +729,6 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) if (ret > 0) __set_bit(ATH_STAT_MRRETRY, sc->status); - /* - * Reset the key cache since some parts do not - * reset the contents on initial power up. - */ - for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) - ath5k_hw_reset_key(ah, i); - /* * Collect the channel list. The 802.11 layer * is resposible for filtering this list based @@ -2202,7 +2188,8 @@ ath5k_beacon_config(struct ath5k_softc *sc) static int ath5k_init(struct ath5k_softc *sc, bool is_resume) { - int ret; + struct ath5k_hw *ah = sc->ah; + int ret, i; mutex_lock(&sc->lock); @@ -2235,10 +2222,17 @@ ath5k_init(struct ath5k_softc *sc, bool is_resume) if (ret) goto done; + /* + * Reset the key cache since some parts do not reset the + * contents on initial power up or resume from suspend. + */ + for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) + ath5k_hw_reset_key(ah, i); + __set_bit(ATH_STAT_STARTED, sc->status); /* Set ack to be sent at low bit-rates */ - ath5k_hw_set_ack_bitrate_high(sc->ah, false); + ath5k_hw_set_ack_bitrate_high(ah, false); mod_timer(&sc->calib_tim, round_jiffies(jiffies + msecs_to_jiffies(ath5k_calinterval * 1000))); @@ -2953,7 +2947,7 @@ static void ath5k_configure_filter(struct ieee80211_hw *hw, sc->opmode != NL80211_IFTYPE_MESH_POINT && test_bit(ATH_STAT_PROMISC, sc->status)) rfilt |= AR5K_RX_FILTER_PROM; - if (sc->opmode == NL80211_IFTYPE_STATION || + if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) || sc->opmode == NL80211_IFTYPE_ADHOC) { rfilt |= AR5K_RX_FILTER_BEACON; } @@ -3094,4 +3088,32 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) end: return ret; } +static void +set_beacon_filter(struct ieee80211_hw *hw, bool enable) +{ + struct ath5k_softc *sc = hw->priv; + struct ath5k_hw *ah = sc->ah; + u32 rfilt; + rfilt = ath5k_hw_get_rx_filter(ah); + if (enable) + rfilt |= AR5K_RX_FILTER_BEACON; + else + rfilt &= ~AR5K_RX_FILTER_BEACON; + ath5k_hw_set_rx_filter(ah, rfilt); + sc->filter_flags = rfilt; +} +static void ath5k_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *bss_conf, + u32 changes) +{ + struct ath5k_softc *sc = hw->priv; + if (changes & BSS_CHANGED_ASSOC) { + mutex_lock(&sc->lock); + sc->assoc = bss_conf->assoc; + if (sc->opmode == NL80211_IFTYPE_STATION) + set_beacon_filter(hw, sc->assoc); + mutex_unlock(&sc->lock); + } +} diff --git a/drivers/net/wireless/ath5k/base.h b/drivers/net/wireless/ath5k/base.h index 06d1054ca94b..facc60ddada2 100644 --- a/drivers/net/wireless/ath5k/base.h +++ b/drivers/net/wireless/ath5k/base.h @@ -179,6 +179,7 @@ struct ath5k_softc { struct timer_list calib_tim; /* calibration timer */ int power_level; /* Requested tx power in dbm */ + bool assoc; /* assocate state */ }; #define ath5k_hw_hasbssidmask(_ah) \ diff --git a/drivers/net/wireless/ath5k/debug.c b/drivers/net/wireless/ath5k/debug.c index 8f92d670f614..ccaeb5c219d2 100644 --- a/drivers/net/wireless/ath5k/debug.c +++ b/drivers/net/wireless/ath5k/debug.c @@ -339,7 +339,7 @@ static struct { { ATH5K_DEBUG_BEACON, "beacon", "beacon handling" }, { ATH5K_DEBUG_CALIBRATE, "calib", "periodic calibration" }, { ATH5K_DEBUG_TXPOWER, "txpower", "transmit power setting" }, - { ATH5K_DEBUG_LED, "led", "LED mamagement" }, + { ATH5K_DEBUG_LED, "led", "LED management" }, { ATH5K_DEBUG_DUMP_RX, "dumprx", "print received skb content" }, { ATH5K_DEBUG_DUMP_TX, "dumptx", "print transmit skb content" }, { ATH5K_DEBUG_DUMPBANDS, "dumpbands", "dump bands" }, @@ -417,19 +417,19 @@ ath5k_debug_init_device(struct ath5k_softc *sc) sc->debug.debugfs_phydir = debugfs_create_dir(wiphy_name(sc->hw->wiphy), ath5k_global_debugfs); - sc->debug.debugfs_debug = debugfs_create_file("debug", 0666, + sc->debug.debugfs_debug = debugfs_create_file("debug", S_IWUSR | S_IRUGO, sc->debug.debugfs_phydir, sc, &fops_debug); - sc->debug.debugfs_registers = debugfs_create_file("registers", 0444, + sc->debug.debugfs_registers = debugfs_create_file("registers", S_IRUGO, sc->debug.debugfs_phydir, sc, &fops_registers); - sc->debug.debugfs_tsf = debugfs_create_file("tsf", 0666, + sc->debug.debugfs_tsf = debugfs_create_file("tsf", S_IWUSR | S_IRUGO, sc->debug.debugfs_phydir, sc, &fops_tsf); - sc->debug.debugfs_beacon = debugfs_create_file("beacon", 0666, + sc->debug.debugfs_beacon = debugfs_create_file("beacon", S_IWUSR | S_IRUGO, sc->debug.debugfs_phydir, sc, &fops_beacon); - sc->debug.debugfs_reset = debugfs_create_file("reset", 0222, + sc->debug.debugfs_reset = debugfs_create_file("reset", S_IWUSR, sc->debug.debugfs_phydir, sc, &fops_reset); } diff --git a/drivers/net/wireless/ath5k/desc.c b/drivers/net/wireless/ath5k/desc.c index dd1374052ba9..5e362a7a3620 100644 --- a/drivers/net/wireless/ath5k/desc.c +++ b/drivers/net/wireless/ath5k/desc.c @@ -531,10 +531,10 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL); rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE); - rs->rs_antenna = rx_status->rx_status_0 & - AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA; - rs->rs_more = rx_status->rx_status_0 & - AR5K_5210_RX_DESC_STATUS0_MORE; + rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA); + rs->rs_more = !!(rx_status->rx_status_0 & + AR5K_5210_RX_DESC_STATUS0_MORE); /* TODO: this timestamp is 13 bit, later on we assume 15 bit */ rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); @@ -607,10 +607,10 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); - rs->rs_antenna = rx_status->rx_status_0 & - AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA; - rs->rs_more = rx_status->rx_status_0 & - AR5K_5212_RX_DESC_STATUS0_MORE; + rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA); + rs->rs_more = !!(rx_status->rx_status_0 & + AR5K_5212_RX_DESC_STATUS0_MORE); rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); rs->rs_status = 0; diff --git a/drivers/net/wireless/ath5k/initvals.c b/drivers/net/wireless/ath5k/initvals.c index ea2e1a20b499..ceaa6c475c06 100644 --- a/drivers/net/wireless/ath5k/initvals.c +++ b/drivers/net/wireless/ath5k/initvals.c @@ -806,6 +806,8 @@ static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = { { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY(642), { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, + { 0xa228, + { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } }, { 0xa23c, { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } }, }; diff --git a/drivers/net/wireless/ath5k/reset.c b/drivers/net/wireless/ath5k/reset.c index 8f1886834e61..1b6d45b6772d 100644 --- a/drivers/net/wireless/ath5k/reset.c +++ b/drivers/net/wireless/ath5k/reset.c @@ -537,9 +537,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, mdelay(1); /* - * Write some more initial register settings + * Write some more initial register settings for revised chips */ - if (ah->ah_version == AR5K_AR5212) { + if (ah->ah_version == AR5K_AR5212 && + ah->ah_phy_revision > 0x41) { ath5k_hw_reg_write(ah, 0x0002a002, 0x982c); if (channel->hw_value == CHANNEL_G) @@ -558,19 +559,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, else ath5k_hw_reg_write(ah, 0x00000000, 0x994c); - /* Some bits are disabled here, we know nothing about - * register 0xa228 yet, most of the times this ends up - * with a value 0x9b5 -haven't seen any dump with - * a different value- */ - /* Got this from decompiling binary HAL */ - data = ath5k_hw_reg_read(ah, 0xa228); - data &= 0xfffffdff; - ath5k_hw_reg_write(ah, data, 0xa228); - - data = ath5k_hw_reg_read(ah, 0xa228); - data &= 0xfffe03ff; - ath5k_hw_reg_write(ah, data, 0xa228); - data = 0; + /* Got this from legacy-hal */ + AR5K_REG_DISABLE_BITS(ah, 0xa228, 0x200); + + AR5K_REG_MASKED_BITS(ah, 0xa228, 0x800, 0xfffe03ff); /* Just write 0x9b5 ? */ /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */ diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 9e15c30bbc06..4dd1c1bda0fb 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -170,7 +170,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) skb = (struct sk_buff *)bf->bf_mpdu; if (skb) { pci_unmap_single(sc->pdev, bf->bf_dmacontext, - skb_end_pointer(skb) - skb->head, + skb->len, PCI_DMA_TODEVICE); } @@ -193,7 +193,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) bf->bf_buf_addr = bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data, - skb_end_pointer(skb) - skb->head, + skb->len, PCI_DMA_TODEVICE); skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data); @@ -352,7 +352,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) if (bf->bf_mpdu != NULL) { skb = (struct sk_buff *)bf->bf_mpdu; pci_unmap_single(sc->pdev, bf->bf_dmacontext, - skb_end_pointer(skb) - skb->head, + skb->len, PCI_DMA_TODEVICE); dev_kfree_skb_any(skb); bf->bf_mpdu = NULL; @@ -412,7 +412,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) bf->bf_buf_addr = bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data, - skb_end_pointer(skb) - skb->head, + skb->len, PCI_DMA_TODEVICE); bf->bf_mpdu = skb; @@ -439,7 +439,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) if (bf->bf_mpdu != NULL) { struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; pci_unmap_single(sc->pdev, bf->bf_dmacontext, - skb_end_pointer(skb) - skb->head, + skb->len, PCI_DMA_TODEVICE); dev_kfree_skb_any(skb); bf->bf_mpdu = NULL; diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index 4983402af559..504a0444d89f 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -49,10 +49,12 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) ASSERT(skb != NULL); ds->ds_vdata = skb->data; - /* setup rx descriptors */ + /* setup rx descriptors. The sc_rxbufsize here tells the harware + * how much data it can DMA to us and that we are prepared + * to process */ ath9k_hw_setuprxdesc(ah, ds, - skb_tailroom(skb), /* buffer size */ + sc->sc_rxbufsize, 0); if (sc->sc_rxlink == NULL) @@ -398,6 +400,13 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, * in rx'd frames. */ + /* Note: the kernel can allocate a value greater than + * what we ask it to give us. We really only need 4 KB as that + * is this hardware supports and in fact we need at least 3849 + * as that is the MAX AMSDU size this hardware supports. + * Unfortunately this means we may get 8 KB here from the + * kernel... and that is actually what is observed on some + * systems :( */ skb = dev_alloc_skb(len + sc->sc_cachelsz - 1); if (skb != NULL) { off = ((unsigned long) skb->data) % sc->sc_cachelsz; @@ -456,7 +465,7 @@ static int ath_rx_indicate(struct ath_softc *sc, if (nskb != NULL) { bf->bf_mpdu = nskb; bf->bf_buf_addr = pci_map_single(sc->pdev, nskb->data, - skb_end_pointer(nskb) - nskb->head, + sc->sc_rxbufsize, PCI_DMA_FROMDEVICE); bf->bf_dmacontext = bf->bf_buf_addr; ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf; @@ -542,7 +551,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) bf->bf_mpdu = skb; bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data, - skb_end_pointer(skb) - skb->head, + sc->sc_rxbufsize, PCI_DMA_FROMDEVICE); bf->bf_dmacontext = bf->bf_buf_addr; ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf; @@ -1007,7 +1016,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) pci_dma_sync_single_for_cpu(sc->pdev, bf->bf_buf_addr, - skb_tailroom(skb), + sc->sc_rxbufsize, PCI_DMA_FROMDEVICE); pci_unmap_single(sc->pdev, bf->bf_buf_addr, diff --git a/drivers/net/wireless/hostap/hostap_wlan.h b/drivers/net/wireless/hostap/hostap_wlan.h index ffdf4876121b..a68f97c39359 100644 --- a/drivers/net/wireless/hostap/hostap_wlan.h +++ b/drivers/net/wireless/hostap/hostap_wlan.h @@ -918,9 +918,12 @@ struct hostap_interface { /* * TX meta data - stored in skb->cb buffer, so this must not be increased over - * the 40-byte limit + * the 48-byte limit. + * THE PADDING THIS STARTS WITH IS A HORRIBLE HACK THAT SHOULD NOT LIVE + * TO SEE THE DAY. */ struct hostap_skb_tx_data { + unsigned int __padding_for_default_qdiscs; u32 magic; /* HOSTAP_SKB_TX_DATA_MAGIC */ u8 rate; /* transmit rate */ #define HOSTAP_TX_FLAGS_WDS BIT(0) diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c index dcce3542d5a7..7a9f901d4ff6 100644 --- a/drivers/net/wireless/ipw2200.c +++ b/drivers/net/wireless/ipw2200.c @@ -3897,6 +3897,7 @@ static int ipw_disassociate(void *data) if (!(priv->status & (STATUS_ASSOCIATED | STATUS_ASSOCIATING))) return 0; ipw_send_disassociate(data, 0); + netif_carrier_off(priv->net_dev); return 1; } @@ -10190,6 +10191,9 @@ static int ipw_tx_skb(struct ipw_priv *priv, struct ieee80211_txb *txb, u16 remaining_bytes; int fc; + if (!(priv->status & STATUS_ASSOCIATED)) + goto drop; + hdr_len = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl)); switch (priv->ieee->iw_mode) { case IW_MODE_ADHOC: diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 24a1aeb6448f..c4c0371c763b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c @@ -1384,9 +1384,11 @@ void iwl_rx_handle(struct iwl_priv *priv) rxq->queue[i] = NULL; - pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, - priv->hw_params.rx_buf_size, - PCI_DMA_FROMDEVICE); + dma_sync_single_range_for_cpu( + &priv->pci_dev->dev, rxb->real_dma_addr, + rxb->aligned_dma_addr - rxb->real_dma_addr, + priv->hw_params.rx_buf_size, + PCI_DMA_FROMDEVICE); pkt = (struct iwl_rx_packet *)rxb->skb->data; /* Reclaim a command buffer only if this packet is a response @@ -1436,8 +1438,8 @@ void iwl_rx_handle(struct iwl_priv *priv) rxb->skb = NULL; } - pci_unmap_single(priv->pci_dev, rxb->dma_addr, - priv->hw_params.rx_buf_size, + pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, + priv->hw_params.rx_buf_size + 256, PCI_DMA_FROMDEVICE); spin_lock_irqsave(&rxq->lock, flags); list_add_tail(&rxb->list, &priv->rxq.rx_used); @@ -2090,7 +2092,6 @@ static void iwl_alive_start(struct iwl_priv *priv) iwl4965_error_recovery(priv); iwl_power_update_mode(priv, 1); - ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) iwl4965_set_mode(priv, priv->iw_mode); @@ -3252,7 +3253,11 @@ static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw, return; } - iwl_scan_cancel_timeout(priv, 100); + if (iwl_scan_cancel(priv)) { + /* cancel scan failed, just live w/ bad key and rely + briefly on SW decryption */ + return; + } key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c index 4c312c55f90c..01a845851338 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.c +++ b/drivers/net/wireless/iwlwifi/iwl-core.c @@ -290,6 +290,9 @@ void iwl_clear_stations_table(struct iwl_priv *priv) priv->num_stations = 0; memset(priv->stations, 0, sizeof(priv->stations)); + /* clean ucode key table bit map */ + priv->ucode_key_table = 0; + spin_unlock_irqrestore(&priv->sta_lock, flags); } EXPORT_SYMBOL(iwl_clear_stations_table); diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h index c018121085e9..9966d4e384ce 100644 --- a/drivers/net/wireless/iwlwifi/iwl-dev.h +++ b/drivers/net/wireless/iwlwifi/iwl-dev.h @@ -89,7 +89,8 @@ extern struct iwl_cfg iwl5100_abg_cfg; #define DEFAULT_LONG_RETRY_LIMIT 4U struct iwl_rx_mem_buffer { - dma_addr_t dma_addr; + dma_addr_t real_dma_addr; + dma_addr_t aligned_dma_addr; struct sk_buff *skb; struct list_head list; }; diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c index 7cde9d76ff5d..0509c16dbe75 100644 --- a/drivers/net/wireless/iwlwifi/iwl-rx.c +++ b/drivers/net/wireless/iwlwifi/iwl-rx.c @@ -204,7 +204,7 @@ int iwl_rx_queue_restock(struct iwl_priv *priv) list_del(element); /* Point to Rx buffer via next RBD in circular buffer */ - rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->dma_addr); + rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr); rxq->queue[rxq->write] = rxb; rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; rxq->free_count--; @@ -251,7 +251,7 @@ void iwl_rx_allocate(struct iwl_priv *priv) rxb = list_entry(element, struct iwl_rx_mem_buffer, list); /* Alloc a new receive buffer */ - rxb->skb = alloc_skb(priv->hw_params.rx_buf_size, + rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256, __GFP_NOWARN | GFP_ATOMIC); if (!rxb->skb) { if (net_ratelimit()) @@ -266,9 +266,17 @@ void iwl_rx_allocate(struct iwl_priv *priv) list_del(element); /* Get physical address of RB/SKB */ - rxb->dma_addr = - pci_map_single(priv->pci_dev, rxb->skb->data, - priv->hw_params.rx_buf_size, PCI_DMA_FROMDEVICE); + rxb->real_dma_addr = pci_map_single( + priv->pci_dev, + rxb->skb->data, + priv->hw_params.rx_buf_size + 256, + PCI_DMA_FROMDEVICE); + /* dma address must be no more than 36 bits */ + BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36)); + /* and also 256 byte aligned! */ + rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256); + skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr); + list_add_tail(&rxb->list, &rxq->rx_free); rxq->free_count++; } @@ -300,8 +308,8 @@ void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { if (rxq->pool[i].skb != NULL) { pci_unmap_single(priv->pci_dev, - rxq->pool[i].dma_addr, - priv->hw_params.rx_buf_size, + rxq->pool[i].real_dma_addr, + priv->hw_params.rx_buf_size + 256, PCI_DMA_FROMDEVICE); dev_kfree_skb(rxq->pool[i].skb); } @@ -354,8 +362,8 @@ void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) * to an SKB, so we need to unmap and free potential storage */ if (rxq->pool[i].skb != NULL) { pci_unmap_single(priv->pci_dev, - rxq->pool[i].dma_addr, - priv->hw_params.rx_buf_size, + rxq->pool[i].real_dma_addr, + priv->hw_params.rx_buf_size + 256, PCI_DMA_FROMDEVICE); priv->alloc_rxb_skb--; dev_kfree_skb(rxq->pool[i].skb); diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c index 3b0bee331a33..c89365e2ca58 100644 --- a/drivers/net/wireless/iwlwifi/iwl-scan.c +++ b/drivers/net/wireless/iwlwifi/iwl-scan.c @@ -896,6 +896,13 @@ static void iwl_bg_request_scan(struct work_struct *data) return; done: + /* Cannot perform scan. Make sure we clear scanning + * bits from status so next scan request can be performed. + * If we don't clear scanning status bit here all next scan + * will fail + */ + clear_bit(STATUS_SCAN_HW, &priv->status); + clear_bit(STATUS_SCANNING, &priv->status); /* inform mac80211 scan aborted */ queue_work(priv->workqueue, &priv->scan_completed); mutex_unlock(&priv->mutex); diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c index 61797f3f8d5c..26f7084d3011 100644 --- a/drivers/net/wireless/iwlwifi/iwl-sta.c +++ b/drivers/net/wireless/iwlwifi/iwl-sta.c @@ -475,7 +475,7 @@ static int iwl_get_free_ucode_key_index(struct iwl_priv *priv) if (!test_and_set_bit(i, &priv->ucode_key_table)) return i; - return -1; + return WEP_INVALID_OFFSET; } int iwl_send_static_wepkey_cmd(struct iwl_priv *priv, u8 send_if_empty) @@ -620,6 +620,9 @@ static int iwl_set_wep_dynamic_key_info(struct iwl_priv *priv, /* else, we are overriding an existing key => no need to allocated room * in uCode. */ + WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, + "no space for new kew"); + priv->stations[sta_id].sta.key.key_flags = key_flags; priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; @@ -637,6 +640,7 @@ static int iwl_set_ccmp_dynamic_key_info(struct iwl_priv *priv, { unsigned long flags; __le16 key_flags = 0; + int ret; key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); @@ -664,14 +668,18 @@ static int iwl_set_ccmp_dynamic_key_info(struct iwl_priv *priv, /* else, we are overriding an existing key => no need to allocated room * in uCode. */ + WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, + "no space for new kew"); + priv->stations[sta_id].sta.key.key_flags = key_flags; priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; + ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); + spin_unlock_irqrestore(&priv->sta_lock, flags); - IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); - return iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); + return ret; } static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv, @@ -696,6 +704,9 @@ static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv, /* else, we are overriding an existing key => no need to allocated room * in uCode. */ + WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, + "no space for new kew"); + /* This copy is acutally not needed: we get the key with each TX */ memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16); @@ -734,6 +745,13 @@ int iwl_remove_dynamic_key(struct iwl_priv *priv, return 0; } + if (priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) { + IWL_WARNING("Removing wrong key %d 0x%x\n", + keyconf->keyidx, key_flags); + spin_unlock_irqrestore(&priv->sta_lock, flags); + return 0; + } + if (!test_and_clear_bit(priv->stations[sta_id].sta.key.key_offset, &priv->ucode_key_table)) IWL_ERROR("index %d not used in uCode key table.\n", diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c index d15a2c997954..45a6b0c35695 100644 --- a/drivers/net/wireless/iwlwifi/iwl3945-base.c +++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c @@ -5768,7 +5768,6 @@ static void iwl3945_alive_start(struct iwl3945_priv *priv) if (priv->error_recovering) iwl3945_error_recovery(priv); - ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); return; restart: @@ -6256,6 +6255,11 @@ static void iwl3945_bg_request_scan(struct work_struct *data) n_probes, (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); + if (scan->channel_count == 0) { + IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count); + goto done; + } + cmd.len += le16_to_cpu(scan->tx_cmd.len) + scan->channel_count * sizeof(struct iwl3945_scan_channel); cmd.data = scan; @@ -6273,6 +6277,14 @@ static void iwl3945_bg_request_scan(struct work_struct *data) return; done: + /* can not perform scan make sure we clear scanning + * bits from status so next scan request can be performed. + * if we dont clear scanning status bit here all next scan + * will fail + */ + clear_bit(STATUS_SCAN_HW, &priv->status); + clear_bit(STATUS_SCANNING, &priv->status); + /* inform mac80211 scan aborted */ queue_work(priv->workqueue, &priv->scan_completed); mutex_unlock(&priv->mutex); diff --git a/drivers/net/wireless/libertas/cmd.c b/drivers/net/wireless/libertas/cmd.c index 297696de2da0..8265c7d25edc 100644 --- a/drivers/net/wireless/libertas/cmd.c +++ b/drivers/net/wireless/libertas/cmd.c @@ -605,9 +605,9 @@ int lbs_get_tx_power(struct lbs_private *priv, s16 *curlevel, s16 *minlevel, if (ret == 0) { *curlevel = le16_to_cpu(cmd.curlevel); if (minlevel) - *minlevel = le16_to_cpu(cmd.minlevel); + *minlevel = cmd.minlevel; if (maxlevel) - *maxlevel = le16_to_cpu(cmd.maxlevel); + *maxlevel = cmd.maxlevel; } lbs_deb_leave(LBS_DEB_CMD); diff --git a/drivers/net/wireless/libertas/rx.c b/drivers/net/wireless/libertas/rx.c index 5749f22b296f..079e6aa874dc 100644 --- a/drivers/net/wireless/libertas/rx.c +++ b/drivers/net/wireless/libertas/rx.c @@ -328,7 +328,7 @@ static int process_rxed_802_11_packet(struct lbs_private *priv, lbs_deb_rx("rx err: frame received with bad length\n"); priv->stats.rx_length_errors++; ret = -EINVAL; - kfree(skb); + kfree_skb(skb); goto done; } diff --git a/drivers/net/wireless/libertas/scan.c b/drivers/net/wireless/libertas/scan.c index 8f66903641b9..22c4c6110521 100644 --- a/drivers/net/wireless/libertas/scan.c +++ b/drivers/net/wireless/libertas/scan.c @@ -598,8 +598,8 @@ static int lbs_process_bss(struct bss_descriptor *bss, switch (elem->id) { case MFIE_TYPE_SSID: - bss->ssid_len = elem->len; - memcpy(bss->ssid, elem->data, elem->len); + bss->ssid_len = min_t(int, 32, elem->len); + memcpy(bss->ssid, elem->data, bss->ssid_len); lbs_deb_scan("got SSID IE: '%s', len %u\n", escape_essid(bss->ssid, bss->ssid_len), bss->ssid_len); diff --git a/drivers/net/wireless/libertas_tf/if_usb.c b/drivers/net/wireless/libertas_tf/if_usb.c index 1cc03a8dd67a..59634c33b1f9 100644 --- a/drivers/net/wireless/libertas_tf/if_usb.c +++ b/drivers/net/wireless/libertas_tf/if_usb.c @@ -331,7 +331,7 @@ static int __if_usb_submit_rx_urb(struct if_usb_card *cardp, /* Fill the receive configuration URB and initialise the Rx call back */ usb_fill_bulk_urb(cardp->rx_urb, cardp->udev, usb_rcvbulkpipe(cardp->udev, cardp->ep_in), - (void *) (skb->tail), + skb_tail_pointer(skb), MRVDRV_ETH_RX_PACKET_BUFFER_SIZE, callbackfn, cardp); cardp->rx_urb->transfer_flags |= URB_ZERO_PACKET; diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c index 2d022f83774c..827ca0384a4c 100644 --- a/drivers/net/wireless/p54/p54common.c +++ b/drivers/net/wireless/p54/p54common.c @@ -319,7 +319,7 @@ static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len) void *tmp; int err; u8 *end = (u8 *)eeprom + len; - u16 synth; + u16 synth = 0; DECLARE_MAC_BUF(mac); wrap = (struct eeprom_pda_wrap *) eeprom; @@ -422,7 +422,8 @@ static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len) entry = (void *)entry + (entry_len + 1)*2; } - if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) { + if (!synth || !priv->iq_autocal || !priv->output_limit || + !priv->curve_data) { printk(KERN_ERR "p54: not all required entries found in eeprom!\n"); err = -EINVAL; goto err; diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c index 1c2a02a741af..88b3cad8b65e 100644 --- a/drivers/net/wireless/p54/p54pci.c +++ b/drivers/net/wireless/p54/p54pci.c @@ -346,68 +346,6 @@ static void p54p_tx(struct ieee80211_hw *dev, struct p54_control_hdr *data, printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy)); } -static int p54p_open(struct ieee80211_hw *dev) -{ - struct p54p_priv *priv = dev->priv; - int err; - - init_completion(&priv->boot_comp); - err = request_irq(priv->pdev->irq, &p54p_interrupt, - IRQF_SHARED, "p54pci", dev); - if (err) { - printk(KERN_ERR "%s: failed to register IRQ handler\n", - wiphy_name(dev->wiphy)); - return err; - } - - memset(priv->ring_control, 0, sizeof(*priv->ring_control)); - err = p54p_upload_firmware(dev); - if (err) { - free_irq(priv->pdev->irq, dev); - return err; - } - priv->rx_idx_data = priv->tx_idx_data = 0; - priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0; - - p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data, - ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data); - - p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt, - ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt); - - P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma)); - P54P_READ(ring_control_base); - wmb(); - udelay(10); - - P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT)); - P54P_READ(int_enable); - wmb(); - udelay(10); - - P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); - P54P_READ(dev_int); - - if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) { - printk(KERN_ERR "%s: Cannot boot firmware!\n", - wiphy_name(dev->wiphy)); - free_irq(priv->pdev->irq, dev); - return -ETIMEDOUT; - } - - P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)); - P54P_READ(int_enable); - wmb(); - udelay(10); - - P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); - P54P_READ(dev_int); - wmb(); - udelay(10); - - return 0; -} - static void p54p_stop(struct ieee80211_hw *dev) { struct p54p_priv *priv = dev->priv; @@ -474,6 +412,68 @@ static void p54p_stop(struct ieee80211_hw *dev) memset(ring_control, 0, sizeof(*ring_control)); } +static int p54p_open(struct ieee80211_hw *dev) +{ + struct p54p_priv *priv = dev->priv; + int err; + + init_completion(&priv->boot_comp); + err = request_irq(priv->pdev->irq, &p54p_interrupt, + IRQF_SHARED, "p54pci", dev); + if (err) { + printk(KERN_ERR "%s: failed to register IRQ handler\n", + wiphy_name(dev->wiphy)); + return err; + } + + memset(priv->ring_control, 0, sizeof(*priv->ring_control)); + err = p54p_upload_firmware(dev); + if (err) { + free_irq(priv->pdev->irq, dev); + return err; + } + priv->rx_idx_data = priv->tx_idx_data = 0; + priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0; + + p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data, + ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data); + + p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt, + ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt); + + P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma)); + P54P_READ(ring_control_base); + wmb(); + udelay(10); + + P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT)); + P54P_READ(int_enable); + wmb(); + udelay(10); + + P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); + P54P_READ(dev_int); + + if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) { + printk(KERN_ERR "%s: Cannot boot firmware!\n", + wiphy_name(dev->wiphy)); + p54p_stop(dev); + return -ETIMEDOUT; + } + + P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)); + P54P_READ(int_enable); + wmb(); + udelay(10); + + P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); + P54P_READ(dev_int); + wmb(); + udelay(10); + + return 0; +} + static int __devinit p54p_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -556,11 +556,13 @@ static int __devinit p54p_probe(struct pci_dev *pdev, spin_lock_init(&priv->lock); tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev); - p54p_open(dev); + err = p54p_open(dev); + if (err) + goto err_free_common; err = p54_read_eeprom(dev); p54p_stop(dev); if (err) - goto err_free_desc; + goto err_free_common; err = ieee80211_register_hw(dev); if (err) { @@ -573,8 +575,6 @@ static int __devinit p54p_probe(struct pci_dev *pdev, err_free_common: p54_free_common(dev); - - err_free_desc: pci_free_consistent(pdev, sizeof(*priv->ring_control), priv->ring_control, priv->ring_control_dma); diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig index f839ce044afd..95511ac22470 100644 --- a/drivers/net/wireless/rt2x00/Kconfig +++ b/drivers/net/wireless/rt2x00/Kconfig @@ -1,5 +1,5 @@ menuconfig RT2X00 - bool "Ralink driver support" + tristate "Ralink driver support" depends on MAC80211 && WLAN_80211 && EXPERIMENTAL ---help--- This will enable the experimental support for the Ralink drivers, diff --git a/drivers/net/wireless/rtl8187_dev.c b/drivers/net/wireless/rtl8187_dev.c index 431e3c78bf27..69eb0132593b 100644 --- a/drivers/net/wireless/rtl8187_dev.c +++ b/drivers/net/wireless/rtl8187_dev.c @@ -48,6 +48,9 @@ static struct usb_device_id rtl8187_table[] __devinitdata = { {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187}, /* Sitecom */ {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187}, + {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B}, + /* Abocom */ + {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187}, {} }; diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c index fe1867b25ff7..cac732f4047f 100644 --- a/drivers/net/wireless/zd1211rw/zd_mac.c +++ b/drivers/net/wireless/zd1211rw/zd_mac.c @@ -615,7 +615,7 @@ static int filter_ack(struct ieee80211_hw *hw, struct ieee80211_hdr *rx_hdr, struct ieee80211_hdr *tx_hdr; tx_hdr = (struct ieee80211_hdr *)skb->data; - if (likely(!compare_ether_addr(tx_hdr->addr2, rx_hdr->addr1))) + if (likely(!memcmp(tx_hdr->addr2, rx_hdr->addr1, ETH_ALEN))) { __skb_unlink(skb, q); tx_status(hw, skb, IEEE80211_TX_STAT_ACK, stats->signal, 1); diff --git a/drivers/net/wireless/zd1211rw/zd_usb.c b/drivers/net/wireless/zd1211rw/zd_usb.c index a60ae86bd5c9..a3ccd8c1c716 100644 --- a/drivers/net/wireless/zd1211rw/zd_usb.c +++ b/drivers/net/wireless/zd1211rw/zd_usb.c @@ -61,6 +61,7 @@ static struct usb_device_id usb_ids[] = { { USB_DEVICE(0x0105, 0x145f), .driver_info = DEVICE_ZD1211 }, /* ZD1211B */ { USB_DEVICE(0x0ace, 0x1215), .driver_info = DEVICE_ZD1211B }, + { USB_DEVICE(0x0ace, 0xb215), .driver_info = DEVICE_ZD1211B }, { USB_DEVICE(0x157e, 0x300d), .driver_info = DEVICE_ZD1211B }, { USB_DEVICE(0x079b, 0x0062), .driver_info = DEVICE_ZD1211B }, { USB_DEVICE(0x1582, 0x6003), .driver_info = DEVICE_ZD1211B }, @@ -82,6 +83,7 @@ static struct usb_device_id usb_ids[] = { { USB_DEVICE(0x0cde, 0x001a), .driver_info = DEVICE_ZD1211B }, { USB_DEVICE(0x0586, 0x340a), .driver_info = DEVICE_ZD1211B }, { USB_DEVICE(0x0471, 0x1237), .driver_info = DEVICE_ZD1211B }, + { USB_DEVICE(0x07fa, 0x1196), .driver_info = DEVICE_ZD1211B }, /* "Driverless" devices that need ejecting */ { USB_DEVICE(0x0ace, 0x2011), .driver_info = DEVICE_INSTALLER }, { USB_DEVICE(0x0ace, 0x20ff), .driver_info = DEVICE_INSTALLER }, diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c index c6948d8f53f6..6d017adc914a 100644 --- a/drivers/net/xen-netfront.c +++ b/drivers/net/xen-netfront.c @@ -1785,7 +1785,7 @@ static int __devexit xennet_remove(struct xenbus_device *dev) return 0; } -static struct xenbus_driver netfront = { +static struct xenbus_driver netfront_driver = { .name = "vif", .owner = THIS_MODULE, .ids = netfront_ids, @@ -1805,7 +1805,7 @@ static int __init netif_init(void) printk(KERN_INFO "Initialising Xen virtual ethernet driver.\n"); - return xenbus_register_frontend(&netfront); + return xenbus_register_frontend(&netfront_driver); } module_init(netif_init); @@ -1815,7 +1815,7 @@ static void __exit netif_exit(void) if (xen_initial_domain()) return; - xenbus_unregister_driver(&netfront); + xenbus_unregister_driver(&netfront_driver); } module_exit(netif_exit); diff --git a/drivers/of/device.c b/drivers/of/device.c index 51e5214071da..224ae6bc67b6 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -105,7 +105,16 @@ EXPORT_SYMBOL(of_release_dev); int of_device_register(struct of_device *ofdev) { BUG_ON(ofdev->node == NULL); - return device_register(&ofdev->dev); + + device_initialize(&ofdev->dev); + + /* device_add will assume that this device is on the same node as + * the parent. If there is no parent defined, set the node + * explicitly */ + if (!ofdev->dev.parent) + set_dev_node(&ofdev->dev, of_node_to_nid(ofdev->node)); + + return device_add(&ofdev->dev); } EXPORT_SYMBOL(of_device_register); diff --git a/drivers/oprofile/event_buffer.c b/drivers/oprofile/event_buffer.c index d962ba0dd87a..191a3202cecc 100644 --- a/drivers/oprofile/event_buffer.c +++ b/drivers/oprofile/event_buffer.c @@ -105,7 +105,7 @@ static int event_buffer_open(struct inode *inode, struct file *file) if (!capable(CAP_SYS_ADMIN)) return -EPERM; - if (test_and_set_bit(0, &buffer_opened)) + if (test_and_set_bit_lock(0, &buffer_opened)) return -EBUSY; /* Register as a user of dcookies @@ -129,7 +129,7 @@ static int event_buffer_open(struct inode *inode, struct file *file) fail: dcookie_unregister(file->private_data); out: - clear_bit(0, &buffer_opened); + __clear_bit_unlock(0, &buffer_opened); return err; } @@ -141,7 +141,7 @@ static int event_buffer_release(struct inode *inode, struct file *file) dcookie_unregister(file->private_data); buffer_pos = 0; atomic_set(&buffer_ready, 0); - clear_bit(0, &buffer_opened); + __clear_bit_unlock(0, &buffer_opened); return 0; } diff --git a/drivers/parport/Kconfig b/drivers/parport/Kconfig index 209b4a464bcf..855f389eea40 100644 --- a/drivers/parport/Kconfig +++ b/drivers/parport/Kconfig @@ -36,7 +36,7 @@ if PARPORT config PARPORT_PC tristate "PC-style hardware" depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \ - (!M68K || ISA) && !MN10300 && !AVR32 + (!M68K || ISA) && !MN10300 && !AVR32 && !BLACKFIN ---help--- You should say Y here if you have a PC-style parallel port. All IBM PC compatible computers and some Alphas have PC-style diff --git a/drivers/parport/parport_cs.c b/drivers/parport/parport_cs.c index b1899e9c1f65..0cd5fbc7f2c2 100644 --- a/drivers/parport/parport_cs.c +++ b/drivers/parport/parport_cs.c @@ -112,7 +112,7 @@ static int parport_probe(struct pcmcia_device *link) link->io.Attributes1 = IO_DATA_PATH_WIDTH_8; link->io.Attributes2 = IO_DATA_PATH_WIDTH_8; - link->irq.Attributes = IRQ_TYPE_EXCLUSIVE; + link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING; link->irq.IRQInfo1 = IRQ_LEVEL_ID; link->conf.Attributes = CONF_ENABLE_IRQ; link->conf.IntType = INT_MEMORY_AND_IO; diff --git a/drivers/parport/parport_serial.c b/drivers/parport/parport_serial.c index e2e95b36a603..101ed49a2d15 100644 --- a/drivers/parport/parport_serial.c +++ b/drivers/parport/parport_serial.c @@ -70,6 +70,8 @@ static int __devinit netmos_parallel_init(struct pci_dev *dev, struct parport_pc * parallel ports and is the number of serial ports. */ card->numports = (dev->subsystem_device & 0xf0) >> 4; + if (card->numports > ARRAY_SIZE(card->addr)) + card->numports = ARRAY_SIZE(card->addr); return 0; } diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h index f9e244da30ae..9bcb6cbd5aa9 100644 --- a/drivers/pci/hotplug/acpiphp.h +++ b/drivers/pci/hotplug/acpiphp.h @@ -113,7 +113,7 @@ struct acpiphp_slot { u8 device; /* pci device# */ - u32 sun; /* ACPI _SUN (slot unique number) */ + unsigned long long sun; /* ACPI _SUN (slot unique number) */ u32 flags; /* see below */ }; diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c index 95b536a23d25..43c10bd261b4 100644 --- a/drivers/pci/hotplug/acpiphp_core.c +++ b/drivers/pci/hotplug/acpiphp_core.c @@ -337,7 +337,7 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot) slot->hotplug_slot->info->cur_bus_speed = PCI_SPEED_UNKNOWN; acpiphp_slot->slot = slot; - snprintf(name, SLOT_NAME_SIZE, "%u", slot->acpi_slot->sun); + snprintf(name, SLOT_NAME_SIZE, "%llu", slot->acpi_slot->sun); retval = pci_hp_register(slot->hotplug_slot, acpiphp_slot->bridge->pci_bus, diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 955aae4071f7..3affc6472e65 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -255,13 +255,13 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv) bridge->nr_slots++; - dbg("found ACPI PCI Hotplug slot %d at PCI %04x:%02x:%02x\n", + dbg("found ACPI PCI Hotplug slot %llu at PCI %04x:%02x:%02x\n", slot->sun, pci_domain_nr(bridge->pci_bus), bridge->pci_bus->number, slot->device); retval = acpiphp_register_hotplug_slot(slot); if (retval) { if (retval == -EBUSY) - warn("Slot %d already registered by another " + warn("Slot %llu already registered by another " "hotplug driver\n", slot->sun); else warn("acpiphp_register_hotplug_slot failed " diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c index c892daae74d6..633e743442ac 100644 --- a/drivers/pci/hotplug/ibmphp_core.c +++ b/drivers/pci/hotplug/ibmphp_core.c @@ -1402,10 +1402,6 @@ static int __init ibmphp_init(void) goto error; } - /* lock ourselves into memory with a module - * count of -1 so that no one can unload us. */ - module_put(THIS_MODULE); - exit: return rc; @@ -1423,4 +1419,3 @@ static void __exit ibmphp_exit(void) } module_init(ibmphp_init); -module_exit(ibmphp_exit); diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c index 4b23bc39b11e..39cf248d24e3 100644 --- a/drivers/pci/hotplug/pciehp_core.c +++ b/drivers/pci/hotplug/pciehp_core.c @@ -432,18 +432,19 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_ goto err_out_release_ctlr; } + /* Check if slot is occupied */ t_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); - - t_slot->hpc_ops->get_adapter_status(t_slot, &value); /* Check if slot is occupied */ - if (value && pciehp_force) { - rc = pciehp_enable_slot(t_slot); - if (rc) /* -ENODEV: shouldn't happen, but deal with it */ - value = 0; - } - if ((POWER_CTRL(ctrl)) && !value) { - rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/ - if (rc) - goto err_out_free_ctrl_slot; + t_slot->hpc_ops->get_adapter_status(t_slot, &value); + if (value) { + if (pciehp_force) + pciehp_enable_slot(t_slot); + } else { + /* Power off slot if not occupied */ + if (POWER_CTRL(ctrl)) { + rc = t_slot->hpc_ops->power_off_slot(t_slot); + if (rc) + goto err_out_free_ctrl_slot; + } } return 0; diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index a2692724b68f..5c8baa43ac9c 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -1655,12 +1655,14 @@ int __init init_dmars(void) iommu->flush.flush_context = __iommu_flush_context; iommu->flush.flush_iotlb = __iommu_flush_iotlb; printk(KERN_INFO "IOMMU 0x%Lx: using Register based " - "invalidation\n", drhd->reg_base_addr); + "invalidation\n", + (unsigned long long)drhd->reg_base_addr); } else { iommu->flush.flush_context = qi_flush_context; iommu->flush.flush_iotlb = qi_flush_iotlb; printk(KERN_INFO "IOMMU 0x%Lx: using Queued " - "invalidation\n", drhd->reg_base_addr); + "invalidation\n", + (unsigned long long)drhd->reg_base_addr); } } diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index dfe7c8e1b185..ae5ec76dca77 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -63,7 +63,7 @@ static acpi_status acpi_run_osc(acpi_handle handle, union acpi_object in_params[4]; struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; union acpi_object *out_obj; - u32 osc_dw0, flags = osc_args->capbuf[OSC_QUERY_TYPE]; + u32 errors, flags = osc_args->capbuf[OSC_QUERY_TYPE]; /* Setting up input parameters */ input.count = 4; @@ -83,21 +83,25 @@ static acpi_status acpi_run_osc(acpi_handle handle, if (ACPI_FAILURE(status)) return status; + if (!output.length) + return AE_NULL_OBJECT; + out_obj = output.pointer; if (out_obj->type != ACPI_TYPE_BUFFER) { printk(KERN_DEBUG "Evaluate _OSC returns wrong type\n"); status = AE_TYPE; goto out_kfree; } - osc_dw0 = *((u32 *)out_obj->buffer.pointer); - if (osc_dw0) { - if (osc_dw0 & OSC_REQUEST_ERROR) + /* Need to ignore the bit0 in result code */ + errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0); + if (errors) { + if (errors & OSC_REQUEST_ERROR) printk(KERN_DEBUG "_OSC request fails\n"); - if (osc_dw0 & OSC_INVALID_UUID_ERROR) + if (errors & OSC_INVALID_UUID_ERROR) printk(KERN_DEBUG "_OSC invalid UUID\n"); - if (osc_dw0 & OSC_INVALID_REVISION_ERROR) + if (errors & OSC_INVALID_REVISION_ERROR) printk(KERN_DEBUG "_OSC invalid revision\n"); - if (osc_dw0 & OSC_CAPABILITIES_MASK_ERROR) { + if (errors & OSC_CAPABILITIES_MASK_ERROR) { if (flags & OSC_QUERY_ENABLE) goto out_success; printk(KERN_DEBUG "_OSC FW not grant req. control\n"); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 110022d78689..5d72866897a8 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -575,7 +575,7 @@ static int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct nr = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; start = vma->vm_pgoff; - size = pci_resource_len(pdev, resno) >> PAGE_SHIFT; + size = ((pci_resource_len(pdev, resno) - 1) >> PAGE_SHIFT) + 1; if (start < size && size - start >= nr) return 1; WARN(1, "process \"%s\" tried to map 0x%08lx-0x%08lx on %s BAR %d (size 0x%08lx)\n", diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 21f2ac639cab..061d1ee0046a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1832,7 +1832,7 @@ int pci_reset_function(struct pci_dev *dev) if (!(cap & PCI_EXP_DEVCAP_FLR)) return -ENOTTY; - if (!dev->msi_enabled && !dev->msix_enabled) + if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) disable_irq(dev->irq); pci_save_state(dev); @@ -1841,7 +1841,7 @@ int pci_reset_function(struct pci_dev *dev) r = pci_execute_reset_function(dev); pci_restore_state(dev); - if (!dev->msi_enabled && !dev->msix_enabled) + if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) enable_irq(dev->irq); return r; @@ -2042,7 +2042,7 @@ static int __devinit pci_init(void) return 0; } -static int __devinit pci_setup(char *str) +static int __init pci_setup(char *str) { while (str) { char *k = strchr(str, ','); diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index dfc63d01f20a..aac7006949f1 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -252,7 +252,7 @@ static void report_resume(struct pci_dev *dev, void *data) if (!dev->driver || !dev->driver->err_handler || - !dev->driver->err_handler->slot_reset) + !dev->driver->err_handler->resume) return; err_handler = dev->driver->err_handler; diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 8f63f4c6b85f..9aad608bcf3f 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -161,11 +162,12 @@ static void pcie_check_clock_pm(struct pci_dev *pdev) */ static void pcie_aspm_configure_common_clock(struct pci_dev *pdev) { - int pos, child_pos; + int pos, child_pos, i = 0; u16 reg16 = 0; struct pci_dev *child_dev; int same_clock = 1; - + unsigned long start_jiffies; + u16 child_regs[8], parent_reg; /* * all functions of a slot should have the same Slot Clock * Configuration, so just check one function @@ -191,16 +193,19 @@ static void pcie_aspm_configure_common_clock(struct pci_dev *pdev) child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL, ®16); + child_regs[i] = reg16; if (same_clock) reg16 |= PCI_EXP_LNKCTL_CCC; else reg16 &= ~PCI_EXP_LNKCTL_CCC; pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL, reg16); + i++; } /* Configure upstream component */ pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); + parent_reg = reg16; if (same_clock) reg16 |= PCI_EXP_LNKCTL_CCC; else @@ -212,12 +217,30 @@ static void pcie_aspm_configure_common_clock(struct pci_dev *pdev) pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); /* Wait for link training end */ - while (1) { + /* break out after waiting for 1 second */ + start_jiffies = jiffies; + while ((jiffies - start_jiffies) < HZ) { pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16); if (!(reg16 & PCI_EXP_LNKSTA_LT)) break; cpu_relax(); } + /* training failed -> recover */ + if ((jiffies - start_jiffies) >= HZ) { + dev_printk (KERN_ERR, &pdev->dev, "ASPM: Could not configure" + " common clock\n"); + i = 0; + list_for_each_entry(child_dev, &pdev->subordinate->devices, + bus_list) { + child_pos = pci_find_capability(child_dev, + PCI_CAP_ID_EXP); + pci_write_config_word(child_dev, + child_pos + PCI_EXP_LNKCTL, + child_regs[i]); + i++; + } + pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, parent_reg); + } } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0b60ed884d98..ce0985615133 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "pci.h" int isa_dma_bridge_buggy; @@ -43,20 +44,6 @@ static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); -/* Many VIA bridges seem to corrupt data for DAC. Disable it here */ -int forbid_dac __read_mostly; -EXPORT_SYMBOL(forbid_dac); - -static __devinit void via_no_dac(struct pci_dev *dev) -{ - if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) { - dev_info(&dev->dev, - "VIA PCI bridge detected. Disabling DAC.\n"); - forbid_dac = 1; - } -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac); - /* Deal with broken BIOS'es that neglect to enable passive release, which can cause problems in combination with the 82441FX/PPro MTRRs */ static void quirk_passive_release(struct pci_dev *dev) @@ -1834,24 +1821,24 @@ static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) } } -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, - PCI_DEVICE_ID_NX2_5706, - quirk_brcm_570x_limit_vpd); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, - PCI_DEVICE_ID_NX2_5706S, - quirk_brcm_570x_limit_vpd); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, - PCI_DEVICE_ID_NX2_5708, - quirk_brcm_570x_limit_vpd); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, - PCI_DEVICE_ID_NX2_5708S, - quirk_brcm_570x_limit_vpd); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, - PCI_DEVICE_ID_NX2_5709, - quirk_brcm_570x_limit_vpd); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, - PCI_DEVICE_ID_NX2_5709S, - quirk_brcm_570x_limit_vpd); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, + PCI_DEVICE_ID_NX2_5706, + quirk_brcm_570x_limit_vpd); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, + PCI_DEVICE_ID_NX2_5706S, + quirk_brcm_570x_limit_vpd); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, + PCI_DEVICE_ID_NX2_5708, + quirk_brcm_570x_limit_vpd); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, + PCI_DEVICE_ID_NX2_5708S, + quirk_brcm_570x_limit_vpd); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, + PCI_DEVICE_ID_NX2_5709, + quirk_brcm_570x_limit_vpd); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, + PCI_DEVICE_ID_NX2_5709S, + quirk_brcm_570x_limit_vpd); #ifdef CONFIG_PCI_MSI /* Some chipsets do not support MSI. We cannot easily rely on setting @@ -1970,6 +1957,22 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, ht_enable_msi_mapping); +/* The P5N32-SLI Premium motherboard from Asus has a problem with msi + * for the MCP55 NIC. It is not yet determined whether the msi problem + * also affects other devices. As for now, turn off msi for this device. + */ +static void __devinit nvenet_msi_disable(struct pci_dev *dev) +{ + if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) { + dev_info(&dev->dev, + "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n"); + dev->no_msi = 1; + } +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_NVENET_15, + nvenet_msi_disable); + static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev) { struct pci_dev *host_bridge; diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c index 1f5f6143f35c..132a78159b60 100644 --- a/drivers/pci/rom.c +++ b/drivers/pci/rom.c @@ -100,7 +100,8 @@ size_t pci_get_rom_size(void __iomem *rom, size_t size) * pci_map_rom - map a PCI ROM to kernel space * @pdev: pointer to pci device struct * @size: pointer to receive size of pci window over ROM - * @return: kernel virtual pointer to image of ROM + * + * Return: kernel virtual pointer to image of ROM * * Map a PCI ROM into kernel space. If ROM is boot video ROM, * the shadow BIOS copy will be returned instead of the @@ -167,7 +168,8 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) * pci_map_rom_copy - map a PCI ROM to kernel space, create a copy * @pdev: pointer to pci device struct * @size: pointer to receive size of pci window over ROM - * @return: kernel virtual pointer to image of ROM + * + * Return: kernel virtual pointer to image of ROM * * Map a PCI ROM into kernel space. If ROM is boot video ROM, * the shadow BIOS copy will be returned instead of the diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index 4dd1c3e157ae..5a8ccb4f604d 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -253,6 +253,7 @@ placeholder: __func__, pci_domain_nr(parent), parent->number, slot_nr); out: + kfree(slot_name); up_write(&pci_bus_sem); return slot; err: diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index f57eeae3830a..222904411a13 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -188,10 +188,6 @@ config PCMCIA_M8XX This driver is also available as a module called m8xx_pcmcia. -config HD64465_PCMCIA - tristate "HD64465 host bridge support" - depends on HD64465 && PCMCIA - config PCMCIA_AU1X00 tristate "Au1x00 pcmcia support" depends on SOC_AU1X00 && PCMCIA diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 23e492bf75cf..238629ad7f7c 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_I82365) += i82365.o obj-$(CONFIG_I82092) += i82092.o obj-$(CONFIG_TCIC) += tcic.o obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o -obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o obj-$(CONFIG_M32R_PCC) += m32r_pcc.o diff --git a/drivers/pcmcia/bfin_cf_pcmcia.c b/drivers/pcmcia/bfin_cf_pcmcia.c index bb7338863fb9..b59d4115d20f 100644 --- a/drivers/pcmcia/bfin_cf_pcmcia.c +++ b/drivers/pcmcia/bfin_cf_pcmcia.c @@ -334,6 +334,6 @@ static void __exit bfin_cf_exit(void) module_init(bfin_cf_init); module_exit(bfin_cf_exit); -MODULE_AUTHOR("Michael Hennerich ") +MODULE_AUTHOR("Michael Hennerich "); MODULE_DESCRIPTION("BFIN CF/PCMCIA Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pcmcia/cistpl.c b/drivers/pcmcia/cistpl.c index dcce9f5d8465..4a110b7b2673 100644 --- a/drivers/pcmcia/cistpl.c +++ b/drivers/pcmcia/cistpl.c @@ -351,10 +351,11 @@ int verify_cis_cache(struct pcmcia_socket *s) char *buf; buf = kmalloc(256, GFP_KERNEL); - if (buf == NULL) + if (buf == NULL) { dev_printk(KERN_WARNING, &s->dev, "no memory for verifying CIS\n"); return -ENOMEM; + } list_for_each_entry(cis, &s->cis_cache, node) { int len = cis->len; diff --git a/drivers/pcmcia/cs.c b/drivers/pcmcia/cs.c index c68c5d338285..0660ad182589 100644 --- a/drivers/pcmcia/cs.c +++ b/drivers/pcmcia/cs.c @@ -186,12 +186,6 @@ int pcmcia_register_socket(struct pcmcia_socket *socket) spin_lock_init(&socket->lock); - if (socket->resource_ops->init) { - ret = socket->resource_ops->init(socket); - if (ret) - return (ret); - } - /* try to obtain a socket number [yes, it gets ugly if we * register more than 2^sizeof(unsigned int) pcmcia * sockets... but the socket number is deprecated @@ -226,7 +220,7 @@ int pcmcia_register_socket(struct pcmcia_socket *socket) /* set proper values in socket->dev */ dev_set_drvdata(&socket->dev, socket); socket->dev.class = &pcmcia_socket_class; - snprintf(socket->dev.bus_id, BUS_ID_SIZE, "pcmcia_socket%u", socket->sock); + dev_set_name(&socket->dev, "pcmcia_socket%u", socket->sock); /* base address = 0, map = 0 */ socket->cis_mem.flags = 0; @@ -239,6 +233,12 @@ int pcmcia_register_socket(struct pcmcia_socket *socket) mutex_init(&socket->skt_mutex); spin_lock_init(&socket->thread_lock); + if (socket->resource_ops->init) { + ret = socket->resource_ops->init(socket); + if (ret) + goto err; + } + tsk = kthread_run(pccardd, socket, "pccardd"); if (IS_ERR(tsk)) { ret = PTR_ERR(tsk); diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c index 795660255490..47cab31ff6e4 100644 --- a/drivers/pcmcia/ds.c +++ b/drivers/pcmcia/ds.c @@ -622,7 +622,6 @@ struct pcmcia_device * pcmcia_device_add(struct pcmcia_socket *s, unsigned int f { struct pcmcia_device *p_dev, *tmp_dev; unsigned long flags; - int bus_id_len; s = pcmcia_get_socket(s); if (!s) @@ -650,12 +649,12 @@ struct pcmcia_device * pcmcia_device_add(struct pcmcia_socket *s, unsigned int f /* by default don't allow DMA */ p_dev->dma_mask = DMA_MASK_NONE; p_dev->dev.dma_mask = &p_dev->dma_mask; - bus_id_len = sprintf (p_dev->dev.bus_id, "%d.%d", p_dev->socket->sock, p_dev->device_no); - - p_dev->devname = kmalloc(6 + bus_id_len + 1, GFP_KERNEL); + dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); + if (!dev_name(&p_dev->dev)) + goto err_free; + p_dev->devname = kasprintf(GFP_KERNEL, "pcmcia%s", dev_name(&p_dev->dev)); if (!p_dev->devname) goto err_free; - sprintf (p_dev->devname, "pcmcia%s", p_dev->dev.bus_id); ds_dev_dbg(3, &p_dev->dev, "devname is %s\n", p_dev->devname); spin_lock_irqsave(&pcmcia_dev_list_lock, flags); @@ -668,6 +667,8 @@ struct pcmcia_device * pcmcia_device_add(struct pcmcia_socket *s, unsigned int f list_for_each_entry(tmp_dev, &s->devices_list, socket_device_list) if (p_dev->func == tmp_dev->func) { p_dev->function_config = tmp_dev->function_config; + p_dev->io = tmp_dev->io; + p_dev->irq = tmp_dev->irq; kref_get(&p_dev->function_config->ref); } diff --git a/drivers/pcmcia/hd64465_ss.c b/drivers/pcmcia/hd64465_ss.c deleted file mode 100644 index 9ef69cdb3183..000000000000 --- a/drivers/pcmcia/hd64465_ss.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - * Device driver for the PCMCIA controller module of the - * Hitachi HD64465 handheld companion chip. - * - * Note that the HD64465 provides a very thin PCMCIA host bridge - * layer, requiring a lot of the work of supporting cards to be - * performed by the processor. For example: mapping of card - * interrupts to processor IRQs is done by IRQ demuxing software; - * IO and memory mappings are fixed; setting voltages according - * to card Voltage Select pins etc is done in software. - * - * Note also that this driver uses only the simple, fixed, - * 16MB, 16-bit wide mappings to PCMCIA spaces defined by the - * HD64465. Larger mappings, smaller mappings, or mappings of - * different width to the same socket, are all possible only by - * involving the SH7750's MMU, which is considered unnecessary here. - * The downside is that it may be possible for some drivers to - * break because they need or expect 8-bit mappings. - * - * This driver currently supports only the following configuration: - * SH7750 CPU, HD64465, TPS2206 voltage control chip. - * - * by Greg Banks - * (c) 2000 PocketPenguins Inc - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#define MODNAME "hd64465_ss" - -/* #define HD64465_DEBUG 1 */ - -#if HD64465_DEBUG -#define DPRINTK(args...) printk(MODNAME ": " args) -#else -#define DPRINTK(args...) -#endif - -extern int hd64465_io_debug; -extern void * p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags); -extern void p3_iounmap(void *addr); - -/*============================================================*/ - -#define HS_IO_MAP_SIZE (64*1024) - -typedef struct hs_socket_t -{ - unsigned int number; - u_int irq; - u_long mem_base; - void *io_base; - u_long mem_length; - u_int ctrl_base; - socket_state_t state; - pccard_io_map io_maps[MAX_IO_WIN]; - pccard_mem_map mem_maps[MAX_WIN]; - struct pcmcia_socket socket; -} hs_socket_t; - - - -#define HS_MAX_SOCKETS 2 -static hs_socket_t hs_sockets[HS_MAX_SOCKETS]; - -#define hs_in(sp, r) inb((sp)->ctrl_base + (r)) -#define hs_out(sp, v, r) outb(v, (sp)->ctrl_base + (r)) - - -/* translate a boolean value to a bit in a register */ -#define bool_to_regbit(sp, r, bi, bo) \ - do { \ - unsigned short v = hs_in(sp, r); \ - if (bo) \ - v |= (bi); \ - else \ - v &= ~(bi); \ - hs_out(sp, v, r); \ - } while(0) - -/* register offsets from HD64465_REG_PCC[01]ISR */ -#define ISR 0x0 -#define GCR 0x2 -#define CSCR 0x4 -#define CSCIER 0x6 -#define SCR 0x8 - - -/* Mask and values for CSCIER register */ -#define IER_MASK 0x80 -#define IER_ON 0x3f /* interrupts on */ -#define IER_OFF 0x00 /* interrupts off */ - -/*============================================================*/ - -#if HD64465_DEBUG > 10 - -static void cis_hex_dump(const unsigned char *x, int len) -{ - int i; - - for (i=0 ; inumber); - - cscier = hs_in(sp, CSCIER); - cscier &= ~HD64465_PCCCSCIER_PIREQE_MASK; - cscier |= HD64465_PCCCSCIER_PIREQE_LEVEL; - hs_out(sp, cscier, CSCIER); -} - -static void hs_socket_disable_ireq(hs_socket_t *sp) -{ - unsigned short cscier; - - DPRINTK("hs_socket_disable_ireq(sock=%d)\n", sp->number); - - cscier = hs_in(sp, CSCIER); - cscier &= ~HD64465_PCCCSCIER_PIREQE_MASK; - hs_out(sp, cscier, CSCIER); -} - -static unsigned int hs_startup_irq(unsigned int irq) -{ - hs_socket_enable_ireq(hs_mapped_irq[irq].sock); - hs_mapped_irq[irq].old_handler->startup(irq); - return 0; -} - -static void hs_shutdown_irq(unsigned int irq) -{ - hs_socket_disable_ireq(hs_mapped_irq[irq].sock); - hs_mapped_irq[irq].old_handler->shutdown(irq); -} - -static void hs_enable_irq(unsigned int irq) -{ - hs_socket_enable_ireq(hs_mapped_irq[irq].sock); - hs_mapped_irq[irq].old_handler->enable(irq); -} - -static void hs_disable_irq(unsigned int irq) -{ - hs_socket_disable_ireq(hs_mapped_irq[irq].sock); - hs_mapped_irq[irq].old_handler->disable(irq); -} - -extern struct hw_interrupt_type no_irq_type; - -static void hs_mask_and_ack_irq(unsigned int irq) -{ - hs_socket_disable_ireq(hs_mapped_irq[irq].sock); - /* ack_none() spuriously complains about an unexpected IRQ */ - if (hs_mapped_irq[irq].old_handler != &no_irq_type) - hs_mapped_irq[irq].old_handler->ack(irq); -} - -static void hs_end_irq(unsigned int irq) -{ - hs_socket_enable_ireq(hs_mapped_irq[irq].sock); - hs_mapped_irq[irq].old_handler->end(irq); -} - - -static struct hw_interrupt_type hd64465_ss_irq_type = { - .typename = "PCMCIA-IRQ", - .startup = hs_startup_irq, - .shutdown = hs_shutdown_irq, - .enable = hs_enable_irq, - .disable = hs_disable_irq, - .ack = hs_mask_and_ack_irq, - .end = hs_end_irq -}; - -/* - * This function should only ever be called with interrupts disabled. - */ -static void hs_map_irq(hs_socket_t *sp, unsigned int irq) -{ - struct irq_desc *desc; - - DPRINTK("hs_map_irq(sock=%d irq=%d)\n", sp->number, irq); - - if (irq >= HS_NUM_MAPPED_IRQS) - return; - - desc = irq_to_desc(irq); - hs_mapped_irq[irq].sock = sp; - /* insert ourselves as the irq controller */ - hs_mapped_irq[irq].old_handler = desc->chip; - desc->chip = &hd64465_ss_irq_type; -} - - -/* - * This function should only ever be called with interrupts disabled. - */ -static void hs_unmap_irq(hs_socket_t *sp, unsigned int irq) -{ - struct irq_desc *desc; - - DPRINTK("hs_unmap_irq(sock=%d irq=%d)\n", sp->number, irq); - - if (irq >= HS_NUM_MAPPED_IRQS) - return; - - desc = irq_to_desc(irq); - /* restore the original irq controller */ - desc->chip = hs_mapped_irq[irq].old_handler; -} - -/*============================================================*/ - - -/* - * Set Vpp and Vcc (in tenths of a Volt). Does not - * support the hi-Z state. - * - * Note, this assumes the board uses a TPS2206 chip to control - * the Vcc and Vpp voltages to the hs_sockets. If your board - * uses the MIC2563 (also supported by the HD64465) then you - * will have to modify this function. - */ - /* 0V 3.3V 5.5V */ -static const u_char hs_tps2206_avcc[3] = { 0x00, 0x04, 0x08 }; -static const u_char hs_tps2206_bvcc[3] = { 0x00, 0x80, 0x40 }; - -static int hs_set_voltages(hs_socket_t *sp, int Vcc, int Vpp) -{ - u_int psr; - u_int vcci = 0; - u_int sock = sp->number; - - DPRINTK("hs_set_voltage(%d, %d, %d)\n", sock, Vcc, Vpp); - - switch (Vcc) - { - case 0: vcci = 0; break; - case 33: vcci = 1; break; - case 50: vcci = 2; break; - default: return 0; - } - - /* Note: Vpp = 120 not supported -- Greg Banks */ - if (Vpp != 0 && Vpp != Vcc) - return 0; - - /* The PSR register holds 8 of the 9 bits which control - * the TPS2206 via its serial interface. - */ - psr = inw(HD64465_REG_PCCPSR); - switch (sock) - { - case 0: - psr &= 0x0f; - psr |= hs_tps2206_avcc[vcci]; - psr |= (Vpp == 0 ? 0x00 : 0x02); - break; - case 1: - psr &= 0xf0; - psr |= hs_tps2206_bvcc[vcci]; - psr |= (Vpp == 0 ? 0x00 : 0x20); - break; - }; - outw(psr, HD64465_REG_PCCPSR); - - return 1; -} - - -/*============================================================*/ - -/* - * Drive the RESET line to the card. - */ -static void hs_reset_socket(hs_socket_t *sp, int on) -{ - unsigned short v; - - v = hs_in(sp, GCR); - if (on) - v |= HD64465_PCCGCR_PCCR; - else - v &= ~HD64465_PCCGCR_PCCR; - hs_out(sp, v, GCR); -} - -/*============================================================*/ - -static int hs_init(struct pcmcia_socket *s) -{ - hs_socket_t *sp = container_of(s, struct hs_socket_t, socket); - - DPRINTK("hs_init(%d)\n", sp->number); - - return 0; -} - -/*============================================================*/ - - -static int hs_get_status(struct pcmcia_socket *s, u_int *value) -{ - hs_socket_t *sp = container_of(s, struct hs_socket_t, socket); - unsigned int isr; - u_int status = 0; - - - isr = hs_in(sp, ISR); - - /* Card is seated and powered when *both* CD pins are low */ - if ((isr & HD64465_PCCISR_PCD_MASK) == 0) - { - status |= SS_DETECT; /* card present */ - - switch (isr & HD64465_PCCISR_PBVD_MASK) - { - case HD64465_PCCISR_PBVD_BATGOOD: - break; - case HD64465_PCCISR_PBVD_BATWARN: - status |= SS_BATWARN; - break; - default: - status |= SS_BATDEAD; - break; - } - - if (isr & HD64465_PCCISR_PREADY) - status |= SS_READY; - - if (isr & HD64465_PCCISR_PMWP) - status |= SS_WRPROT; - - /* Voltage Select pins interpreted as per Table 4-5 of the std. - * Assuming we have the TPS2206, the socket is a "Low Voltage - * key, 3.3V and 5V available, no X.XV available". - */ - switch (isr & (HD64465_PCCISR_PVS2|HD64465_PCCISR_PVS1)) - { - case HD64465_PCCISR_PVS1: - printk(KERN_NOTICE MODNAME ": cannot handle X.XV card, ignored\n"); - status = 0; - break; - case 0: - case HD64465_PCCISR_PVS2: - /* 3.3V */ - status |= SS_3VCARD; - break; - case HD64465_PCCISR_PVS2|HD64465_PCCISR_PVS1: - /* 5V */ - break; - } - - /* TODO: SS_POWERON */ - /* TODO: SS_STSCHG */ - } - - DPRINTK("hs_get_status(%d) = %x\n", sock, status); - - *value = status; - return 0; -} - -/*============================================================*/ - -static int hs_set_socket(struct pcmcia_socket *s, socket_state_t *state) -{ - hs_socket_t *sp = container_of(s, struct hs_socket_t, socket); - u_long flags; - u_int changed; - unsigned short cscier; - - DPRINTK("hs_set_socket(sock=%d, flags=%x, csc_mask=%x, Vcc=%d, Vpp=%d, io_irq=%d)\n", - sock, state->flags, state->csc_mask, state->Vcc, state->Vpp, state->io_irq); - - local_irq_save(flags); /* Don't want interrupts happening here */ - - if (state->Vpp != sp->state.Vpp || - state->Vcc != sp->state.Vcc) { - if (!hs_set_voltages(sp, state->Vcc, state->Vpp)) { - local_irq_restore(flags); - return -EINVAL; - } - } - -/* hd64465_io_debug = 1; */ - /* - * Handle changes in the Card Status Change mask, - * by propagating to the CSCR register - */ - changed = sp->state.csc_mask ^ state->csc_mask; - cscier = hs_in(sp, CSCIER); - - if (changed & SS_DETECT) { - if (state->csc_mask & SS_DETECT) - cscier |= HD64465_PCCCSCIER_PCDE; - else - cscier &= ~HD64465_PCCCSCIER_PCDE; - } - - if (changed & SS_READY) { - if (state->csc_mask & SS_READY) - cscier |= HD64465_PCCCSCIER_PRE; - else - cscier &= ~HD64465_PCCCSCIER_PRE; - } - - if (changed & SS_BATDEAD) { - if (state->csc_mask & SS_BATDEAD) - cscier |= HD64465_PCCCSCIER_PBDE; - else - cscier &= ~HD64465_PCCCSCIER_PBDE; - } - - if (changed & SS_BATWARN) { - if (state->csc_mask & SS_BATWARN) - cscier |= HD64465_PCCCSCIER_PBWE; - else - cscier &= ~HD64465_PCCCSCIER_PBWE; - } - - if (changed & SS_STSCHG) { - if (state->csc_mask & SS_STSCHG) - cscier |= HD64465_PCCCSCIER_PSCE; - else - cscier &= ~HD64465_PCCCSCIER_PSCE; - } - - hs_out(sp, cscier, CSCIER); - - if (sp->state.io_irq && !state->io_irq) - hs_unmap_irq(sp, sp->state.io_irq); - else if (!sp->state.io_irq && state->io_irq) - hs_map_irq(sp, state->io_irq); - - - /* - * Handle changes in the flags field, - * by propagating to config registers. - */ - changed = sp->state.flags ^ state->flags; - - if (changed & SS_IOCARD) { - DPRINTK("card type: %s\n", - (state->flags & SS_IOCARD ? "i/o" : "memory" )); - bool_to_regbit(sp, GCR, HD64465_PCCGCR_PCCT, - state->flags & SS_IOCARD); - } - - if (changed & SS_RESET) { - DPRINTK("%s reset card\n", - (state->flags & SS_RESET ? "start" : "stop")); - bool_to_regbit(sp, GCR, HD64465_PCCGCR_PCCR, - state->flags & SS_RESET); - } - - if (changed & SS_OUTPUT_ENA) { - DPRINTK("%sabling card output\n", - (state->flags & SS_OUTPUT_ENA ? "en" : "dis")); - bool_to_regbit(sp, GCR, HD64465_PCCGCR_PDRV, - state->flags & SS_OUTPUT_ENA); - } - - /* TODO: SS_SPKR_ENA */ - -/* hd64465_io_debug = 0; */ - sp->state = *state; - - local_irq_restore(flags); - -#if HD64465_DEBUG > 10 - if (state->flags & SS_OUTPUT_ENA) - cis_hex_dump((const unsigned char*)sp->mem_base, 0x100); -#endif - return 0; -} - -/*============================================================*/ - -static int hs_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) -{ - hs_socket_t *sp = container_of(s, struct hs_socket_t, socket); - int map = io->map; - int sock = sp->number; - struct pccard_io_map *sio; - pgprot_t prot; - - DPRINTK("hs_set_io_map(sock=%d, map=%d, flags=0x%x, speed=%dns, start=%#lx, stop=%#lx)\n", - sock, map, io->flags, io->speed, io->start, io->stop); - if (map >= MAX_IO_WIN) - return -EINVAL; - sio = &sp->io_maps[map]; - - /* check for null changes */ - if (io->flags == sio->flags && - io->start == sio->start && - io->stop == sio->stop) - return 0; - - if (io->flags & MAP_AUTOSZ) - prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IODYN); - else if (io->flags & MAP_16BIT) - prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IO16); - else - prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IO8); - - /* TODO: handle MAP_USE_WAIT */ - if (io->flags & MAP_USE_WAIT) - printk(KERN_INFO MODNAME ": MAP_USE_WAIT unimplemented\n"); - /* TODO: handle MAP_PREFETCH */ - if (io->flags & MAP_PREFETCH) - printk(KERN_INFO MODNAME ": MAP_PREFETCH unimplemented\n"); - /* TODO: handle MAP_WRPROT */ - if (io->flags & MAP_WRPROT) - printk(KERN_INFO MODNAME ": MAP_WRPROT unimplemented\n"); - /* TODO: handle MAP_0WS */ - if (io->flags & MAP_0WS) - printk(KERN_INFO MODNAME ": MAP_0WS unimplemented\n"); - - if (io->flags & MAP_ACTIVE) { - unsigned long pstart, psize, paddrbase; - - paddrbase = virt_to_phys((void*)(sp->mem_base + 2 * HD64465_PCC_WINDOW)); - pstart = io->start & PAGE_MASK; - psize = ((io->stop + PAGE_SIZE) & PAGE_MASK) - pstart; - - /* - * Change PTEs in only that portion of the mapping requested - * by the caller. This means that most of the time, most of - * the PTEs in the io_vma will be unmapped and only the bottom - * page will be mapped. But the code allows for weird cards - * that might want IO ports > 4K. - */ - sp->io_base = p3_ioremap(paddrbase + pstart, psize, pgprot_val(prot)); - - /* - * Change the mapping used by inb() outb() etc - */ - hd64465_port_map(io->start, - io->stop - io->start + 1, - (unsigned long)sp->io_base + io->start, 0); - } else { - hd64465_port_unmap(sio->start, sio->stop - sio->start + 1); - p3_iounmap(sp->io_base); - } - - *sio = *io; - return 0; -} - -/*============================================================*/ - -static int hs_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem) -{ - hs_socket_t *sp = container_of(s, struct hs_socket_t, socket); - struct pccard_mem_map *smem; - int map = mem->map; - unsigned long paddr; - -#if 0 - DPRINTK("hs_set_mem_map(sock=%d, map=%d, flags=0x%x, card_start=0x%08x)\n", - sock, map, mem->flags, mem->card_start); -#endif - - if (map >= MAX_WIN) - return -EINVAL; - smem = &sp->mem_maps[map]; - - paddr = sp->mem_base; /* base of Attribute mapping */ - if (!(mem->flags & MAP_ATTRIB)) - paddr += HD64465_PCC_WINDOW; /* base of Common mapping */ - paddr += mem->card_start; - - /* Because we specified SS_CAP_STATIC_MAP, we are obliged - * at this time to report the system address corresponding - * to the card address requested. This is how Socket Services - * queries our fixed mapping. I wish this fact had been - * documented - Greg Banks. - */ - mem->static_start = paddr; - - *smem = *mem; - - return 0; -} - -/* TODO: do we need to use the MMU to access Common memory ??? */ - -/*============================================================*/ - -/* - * This function is registered with the HD64465 glue code to do a - * secondary demux step on the PCMCIA interrupts. It handles - * mapping the IREQ request from the card to a standard Linux - * IRQ, as requested by SocketServices. - */ -static int hs_irq_demux(int irq, void *dev) -{ - hs_socket_t *sp = dev; - u_int cscr; - - DPRINTK("hs_irq_demux(irq=%d)\n", irq); - - if (sp->state.io_irq && - (cscr = hs_in(sp, CSCR)) & HD64465_PCCCSCR_PIREQ) { - cscr &= ~HD64465_PCCCSCR_PIREQ; - hs_out(sp, cscr, CSCR); - return sp->state.io_irq; - } - - return irq; -} - -/*============================================================*/ - -/* - * Interrupt handling routine. - */ - -static irqreturn_t hs_interrupt(int irq, void *dev) -{ - hs_socket_t *sp = dev; - u_int events = 0; - u_int cscr; - - cscr = hs_in(sp, CSCR); - - DPRINTK("hs_interrupt, cscr=%04x\n", cscr); - - /* check for bus-related changes to be reported to Socket Services */ - if (cscr & HD64465_PCCCSCR_PCDC) { - /* double-check for a 16-bit card, as we don't support CardBus */ - if ((hs_in(sp, ISR) & HD64465_PCCISR_PCD_MASK) != 0) { - printk(KERN_NOTICE MODNAME - ": socket %d, card not a supported card type or not inserted correctly\n", - sp->number); - /* Don't do the rest unless a card is present */ - cscr &= ~(HD64465_PCCCSCR_PCDC| - HD64465_PCCCSCR_PRC| - HD64465_PCCCSCR_PBW| - HD64465_PCCCSCR_PBD| - HD64465_PCCCSCR_PSC); - } else { - cscr &= ~HD64465_PCCCSCR_PCDC; - events |= SS_DETECT; /* card insertion or removal */ - } - } - if (cscr & HD64465_PCCCSCR_PRC) { - cscr &= ~HD64465_PCCCSCR_PRC; - events |= SS_READY; /* ready signal changed */ - } - if (cscr & HD64465_PCCCSCR_PBW) { - cscr &= ~HD64465_PCCCSCR_PSC; - events |= SS_BATWARN; /* battery warning */ - } - if (cscr & HD64465_PCCCSCR_PBD) { - cscr &= ~HD64465_PCCCSCR_PSC; - events |= SS_BATDEAD; /* battery dead */ - } - if (cscr & HD64465_PCCCSCR_PSC) { - cscr &= ~HD64465_PCCCSCR_PSC; - events |= SS_STSCHG; /* STSCHG (status changed) signal */ - } - - if (cscr & HD64465_PCCCSCR_PIREQ) { - cscr &= ~HD64465_PCCCSCR_PIREQ; - - /* This should have been dealt with during irq demux */ - printk(KERN_NOTICE MODNAME ": unexpected IREQ from card\n"); - } - - hs_out(sp, cscr, CSCR); - - if (events) - pcmcia_parse_events(&sp->socket, events); - - return IRQ_HANDLED; -} - -/*============================================================*/ - -static struct pccard_operations hs_operations = { - .init = hs_init, - .get_status = hs_get_status, - .set_socket = hs_set_socket, - .set_io_map = hs_set_io_map, - .set_mem_map = hs_set_mem_map, -}; - -static int hs_init_socket(hs_socket_t *sp, int irq, unsigned long mem_base, - unsigned int ctrl_base) -{ - unsigned short v; - int i, err; - - memset(sp, 0, sizeof(*sp)); - sp->irq = irq; - sp->mem_base = mem_base; - sp->mem_length = 4*HD64465_PCC_WINDOW; /* 16MB */ - sp->ctrl_base = ctrl_base; - - for (i=0 ; iio_maps[i].map = i; - for (i=0 ; imem_maps[i].map = i; - - hd64465_register_irq_demux(sp->irq, hs_irq_demux, sp); - - if ((err = request_irq(sp->irq, hs_interrupt, IRQF_DISABLED, MODNAME, sp)) < 0) - return err; - if (request_mem_region(sp->mem_base, sp->mem_length, MODNAME) == 0) { - sp->mem_base = 0; - return -ENOMEM; - } - - - /* According to section 3.2 of the PCMCIA standard, low-voltage - * capable cards must implement cold insertion, i.e. Vpp and - * Vcc set to 0 before card is inserted. - */ - /*hs_set_voltages(sp, 0, 0);*/ - - /* hi-Z the outputs to the card and set 16MB map mode */ - v = hs_in(sp, GCR); - v &= ~HD64465_PCCGCR_PCCT; /* memory-only card */ - hs_out(sp, v, GCR); - - v = hs_in(sp, GCR); - v |= HD64465_PCCGCR_PDRV; /* enable outputs to card */ - hs_out(sp, v, GCR); - - v = hs_in(sp, GCR); - v |= HD64465_PCCGCR_PMMOD; /* 16MB mapping mode */ - hs_out(sp, v, GCR); - - v = hs_in(sp, GCR); - /* lowest 16MB of Common */ - v &= ~(HD64465_PCCGCR_PPA25|HD64465_PCCGCR_PPA24); - hs_out(sp, v, GCR); - - hs_reset_socket(sp, 1); - - printk(KERN_INFO "HD64465 PCMCIA bridge socket %d at 0x%08lx irq %d\n", - i, sp->mem_base, sp->irq); - - return 0; -} - -static void hs_exit_socket(hs_socket_t *sp) -{ - unsigned short cscier, gcr; - unsigned long flags; - - local_irq_save(flags); - - /* turn off interrupts in hardware */ - cscier = hs_in(sp, CSCIER); - cscier = (cscier & IER_MASK) | IER_OFF; - hs_out(sp, cscier, CSCIER); - - /* hi-Z the outputs to the card */ - gcr = hs_in(sp, GCR); - gcr &= HD64465_PCCGCR_PDRV; - hs_out(sp, gcr, GCR); - - /* power the card down */ - hs_set_voltages(sp, 0, 0); - - if (sp->mem_base != 0) - release_mem_region(sp->mem_base, sp->mem_length); - if (sp->irq != 0) { - free_irq(sp->irq, hs_interrupt); - hd64465_unregister_irq_demux(sp->irq); - } - - local_irq_restore(flags); -} - -static struct device_driver hd64465_driver = { - .name = "hd64465-pcmcia", - .bus = &platform_bus_type, - .suspend = pcmcia_socket_dev_suspend, - .resume = pcmcia_socket_dev_resume, -}; - -static struct platform_device hd64465_device = { - .name = "hd64465-pcmcia", - .id = 0, -}; - -static int __init init_hs(void) -{ - int i; - unsigned short v; - -/* hd64465_io_debug = 1; */ - if (driver_register(&hd64465_driver)) - return -EINVAL; - - /* Wake both sockets out of STANDBY mode */ - /* TODO: wait 15ms */ - v = inw(HD64465_REG_SMSCR); - v &= ~(HD64465_SMSCR_PC0ST|HD64465_SMSCR_PC1ST); - outw(v, HD64465_REG_SMSCR); - - /* keep power controller out of shutdown mode */ - v = inb(HD64465_REG_PCC0SCR); - v |= HD64465_PCCSCR_SHDN; - outb(v, HD64465_REG_PCC0SCR); - - /* use serial (TPS2206) power controller */ - v = inb(HD64465_REG_PCC0CSCR); - v |= HD64465_PCCCSCR_PSWSEL; - outb(v, HD64465_REG_PCC0CSCR); - - /* - * Setup hs_sockets[] structures and request system resources. - * TODO: on memory allocation failure, power down the socket - * before quitting. - */ - for (i=0; iAttributes & CONF_VPP1_CHANGE_VALID) && (mod->Attributes & CONF_VPP2_CHANGE_VALID)) { - if (mod->Vpp1 != mod->Vpp2) + if (mod->Vpp1 != mod->Vpp2) { ds_dbg(s, 0, "Vpp1 and Vpp2 must be the same\n"); return -EINVAL; + } s->socket.Vpp = mod->Vpp1; if (s->ops->set_socket(s, &s->socket)) { dev_printk(KERN_WARNING, &s->dev, @@ -693,8 +694,9 @@ int pcmcia_request_irq(struct pcmcia_device *p_dev, irq_req_t *req) type = 0; if (s->functions > 1) /* All of this ought to be handled higher up */ type = IRQF_SHARED; - if (req->Attributes & IRQ_TYPE_DYNAMIC_SHARING) + else if (req->Attributes & IRQ_TYPE_DYNAMIC_SHARING) type = IRQF_SHARED; + else printk(KERN_WARNING "pcmcia: Driver needs updating to support IRQ sharing.\n"); #ifdef CONFIG_PCMCIA_PROBE diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstatic.c index 17f4ecf1c0c5..9ca22c7aafb2 100644 --- a/drivers/pcmcia/rsrc_nonstatic.c +++ b/drivers/pcmcia/rsrc_nonstatic.c @@ -71,7 +71,7 @@ static DEFINE_MUTEX(rsrc_mutex); ======================================================================*/ static struct resource * -make_resource(resource_size_t b, resource_size_t n, int flags, char *name) +make_resource(resource_size_t b, resource_size_t n, int flags, const char *name) { struct resource *res = kzalloc(sizeof(*res), GFP_KERNEL); @@ -624,7 +624,7 @@ static int nonstatic_adjust_io_region(struct resource *res, unsigned long r_star static struct resource *nonstatic_find_io_region(unsigned long base, int num, unsigned long align, struct pcmcia_socket *s) { - struct resource *res = make_resource(0, num, IORESOURCE_IO, s->dev.bus_id); + struct resource *res = make_resource(0, num, IORESOURCE_IO, dev_name(&s->dev)); struct socket_data *s_data = s->resource_data; struct pcmcia_align_data data; unsigned long min = base; @@ -658,7 +658,7 @@ static struct resource *nonstatic_find_io_region(unsigned long base, int num, static struct resource * nonstatic_find_mem_region(u_long base, u_long num, u_long align, int low, struct pcmcia_socket *s) { - struct resource *res = make_resource(0, num, IORESOURCE_MEM, s->dev.bus_id); + struct resource *res = make_resource(0, num, IORESOURCE_MEM, dev_name(&s->dev)); struct socket_data *s_data = s->resource_data; struct pcmcia_align_data data; unsigned long min, max; diff --git a/drivers/pnp/interface.c b/drivers/pnp/interface.c index 478a4a739c00..c3f1c8e9d254 100644 --- a/drivers/pnp/interface.c +++ b/drivers/pnp/interface.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ps3/ps3-lpm.c b/drivers/ps3/ps3-lpm.c index 85edf945ab86..204158cf7a55 100644 --- a/drivers/ps3/ps3-lpm.c +++ b/drivers/ps3/ps3-lpm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/rapidio/rio-scan.c b/drivers/rapidio/rio-scan.c index a926c896475e..643a6b98462b 100644 --- a/drivers/rapidio/rio-scan.c +++ b/drivers/rapidio/rio-scan.c @@ -879,7 +879,7 @@ static void rio_update_route_tables(struct rio_mport *port) * link, then start recursive peer enumeration. Returns %0 if * enumeration succeeds or %-EBUSY if enumeration fails. */ -int rio_enum_mport(struct rio_mport *mport) +int __devinit rio_enum_mport(struct rio_mport *mport) { struct rio_net *net = NULL; int rc = 0; @@ -972,7 +972,7 @@ static void rio_enum_timeout(unsigned long data) * peer discovery. Returns %0 if discovery succeeds or %-EBUSY * on failure. */ -int rio_disc_mport(struct rio_mport *mport) +int __devinit rio_disc_mport(struct rio_mport *mport) { struct rio_net *net = NULL; int enum_timeout_flag = 0; diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c index 680661abbc4b..6395c780008b 100644 --- a/drivers/rapidio/rio.c +++ b/drivers/rapidio/rio.c @@ -467,7 +467,7 @@ static int __devinit rio_init(void) device_initcall(rio_init); -int rio_init_mports(void) +int __devinit rio_init_mports(void) { int rc = 0; struct rio_mport *port; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 4dada6ee1119..39360e2a4540 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1,6 +1,4 @@ -menu "Voltage and Current regulators" - -config REGULATOR +menuconfig REGULATOR bool "Voltage and Current Regulator Support" default n help @@ -23,21 +21,20 @@ config REGULATOR If unsure, say no. +if REGULATOR + config REGULATOR_DEBUG bool "Regulator debug support" - depends on REGULATOR help Say yes here to enable debugging support. config REGULATOR_FIXED_VOLTAGE tristate default n - select REGULATOR config REGULATOR_VIRTUAL_CONSUMER tristate "Virtual regulator consumer support" default n - select REGULATOR help This driver provides a virtual consumer for the voltage and current regulator API which provides sysfs controls for @@ -49,7 +46,6 @@ config REGULATOR_VIRTUAL_CONSUMER config REGULATOR_BQ24022 tristate "TI bq24022 Dual Input 1-Cell Li-Ion Charger IC" default n - select REGULATOR help This driver controls a TI bq24022 Charger attached via GPIOs. The provided current regulator can enable/disable @@ -59,7 +55,6 @@ config REGULATOR_BQ24022 config REGULATOR_WM8350 tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC" depends on MFD_WM8350 - select REGULATOR help This driver provides support for the voltage and current regulators of the WM8350 AudioPlus PMIC. @@ -67,7 +62,6 @@ config REGULATOR_WM8350 config REGULATOR_WM8400 tristate "Wolfson Microelectroncis WM8400 AudioPlus PMIC" depends on MFD_WM8400 - select REGULATOR help This driver provides support for the voltage regulators of the WM8400 AudioPlus PMIC. @@ -75,9 +69,8 @@ config REGULATOR_WM8400 config REGULATOR_DA903X tristate "Support regulators on Dialog Semiconductor DA9030/DA9034 PMIC" depends on PMIC_DA903X - select REGULATOR help Say y here to support the BUCKs and LDOs regulators found on Dialog Semiconductor DA9030/DA9034 PMIC. -endmenu +endif diff --git a/drivers/regulator/da903x.c b/drivers/regulator/da903x.c index 3688e339db87..773b29cec8be 100644 --- a/drivers/regulator/da903x.c +++ b/drivers/regulator/da903x.c @@ -79,6 +79,11 @@ struct da903x_regulator_info { int enable_bit; }; +static inline struct device *to_da903x_dev(struct regulator_dev *rdev) +{ + return rdev_get_dev(rdev)->parent->parent; +} + static inline int check_range(struct da903x_regulator_info *info, int min_uV, int max_uV) { @@ -93,7 +98,7 @@ static int da903x_set_ldo_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); uint8_t val, mask; if (check_range(info, min_uV, max_uV)) { @@ -111,7 +116,7 @@ static int da903x_set_ldo_voltage(struct regulator_dev *rdev, static int da903x_get_voltage(struct regulator_dev *rdev) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); uint8_t val, mask; int ret; @@ -128,7 +133,7 @@ static int da903x_get_voltage(struct regulator_dev *rdev) static int da903x_enable(struct regulator_dev *rdev) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); return da903x_set_bits(da9034_dev, info->enable_reg, 1 << info->enable_bit); @@ -137,7 +142,7 @@ static int da903x_enable(struct regulator_dev *rdev) static int da903x_disable(struct regulator_dev *rdev) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); return da903x_clr_bits(da9034_dev, info->enable_reg, 1 << info->enable_bit); @@ -146,7 +151,7 @@ static int da903x_disable(struct regulator_dev *rdev) static int da903x_is_enabled(struct regulator_dev *rdev) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); uint8_t reg_val; int ret; @@ -162,7 +167,7 @@ static int da9030_set_ldo1_15_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da903x_dev = rdev_get_dev(rdev)->parent; + struct device *da903x_dev = to_da903x_dev(rdev); uint8_t val, mask; int ret; @@ -189,7 +194,7 @@ static int da9030_set_ldo14_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da903x_dev = rdev_get_dev(rdev)->parent; + struct device *da903x_dev = to_da903x_dev(rdev); uint8_t val, mask; int thresh; @@ -215,7 +220,7 @@ static int da9030_set_ldo14_voltage(struct regulator_dev *rdev, static int da9030_get_ldo14_voltage(struct regulator_dev *rdev) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da903x_dev = rdev_get_dev(rdev)->parent; + struct device *da903x_dev = to_da903x_dev(rdev); uint8_t val, mask; int ret; @@ -238,7 +243,7 @@ static int da9034_set_dvc_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); uint8_t val, mask; int ret; @@ -264,7 +269,7 @@ static int da9034_set_ldo12_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); uint8_t val, mask; if (check_range(info, min_uV, max_uV)) { @@ -283,7 +288,7 @@ static int da9034_set_ldo12_voltage(struct regulator_dev *rdev, static int da9034_get_ldo12_voltage(struct regulator_dev *rdev) { struct da903x_regulator_info *info = rdev_get_drvdata(rdev); - struct device *da9034_dev = rdev_get_dev(rdev)->parent; + struct device *da9034_dev = to_da903x_dev(rdev); uint8_t val, mask; int ret; @@ -466,7 +471,7 @@ static int __devinit da903x_regulator_probe(struct platform_device *pdev) if (ri->desc.id == DA9030_ID_LDO1 || ri->desc.id == DA9030_ID_LDO15) ri->desc.ops = &da9030_regulator_ldo1_15_ops; - rdev = regulator_register(&ri->desc, pdev->dev.parent, ri); + rdev = regulator_register(&ri->desc, &pdev->dev, ri); if (IS_ERR(rdev)) { dev_err(&pdev->dev, "failed to register regulator %s\n", ri->desc.name); diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8abbb2020af9..123092d8a984 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -277,6 +277,14 @@ config RTC_DRV_FM3130 This driver can also be built as a module. If so the module will be called rtc-fm3130. +config RTC_DRV_RX8581 + tristate "Epson RX-8581" + help + If you say yes here you will get support for the Epson RX-8581. + + This driver can also be built as a module. If so the module + will be called rtc-rx8581. + endif # I2C comment "SPI RTC drivers" @@ -302,6 +310,17 @@ config RTC_DRV_DS1305 This driver can also be built as a module. If so, the module will be called rtc-ds1305. +config RTC_DRV_DS1390 + tristate "Dallas/Maxim DS1390/93/94" + help + If you say yes here you get support for the DS1390/93/94 chips. + + This driver only supports the RTC feature, and not other chip + features such as alarms and trickle charging. + + This driver can also be built as a module. If so, the module + will be called rtc-ds1390. + config RTC_DRV_MAX6902 tristate "Maxim MAX6902" help @@ -468,6 +487,16 @@ config RTC_DRV_V3020 This driver can also be built as a module. If so, the module will be called rtc-v3020. +config RTC_DRV_WM8350 + tristate "Wolfson Microelectronics WM8350 RTC" + depends on MFD_WM8350 + help + If you say yes here you will get support for the RTC subsystem + of the Wolfson Microelectronics WM8350. + + This driver can also be built as a module. If so, the module + will be called "rtc-wm8350". + comment "on-CPU RTC drivers" config RTC_DRV_OMAP diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index e9e8474cc8fe..6e79c912bf9e 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_RTC_DRV_DS1302) += rtc-ds1302.o obj-$(CONFIG_RTC_DRV_DS1305) += rtc-ds1305.o obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o obj-$(CONFIG_RTC_DRV_DS1374) += rtc-ds1374.o +obj-$(CONFIG_RTC_DRV_DS1390) += rtc-ds1390.o obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o @@ -57,6 +58,7 @@ obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o +obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_SA1100) += rtc-sa1100.o @@ -66,4 +68,5 @@ obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl4030.o obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o +obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c index 7af60b98d8a4..a04c1b6b1575 100644 --- a/drivers/rtc/interface.c +++ b/drivers/rtc/interface.c @@ -271,7 +271,7 @@ int rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) dev_dbg(&rtc->dev, "alarm rollover: %s\n", "year"); do { alarm->time.tm_year++; - } while (!rtc_valid_tm(&alarm->time)); + } while (rtc_valid_tm(&alarm->time) != 0); break; default: diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index 5549231179a2..6cf8e282338f 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -794,7 +794,7 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) goto cleanup2; } - pr_info("%s: alarms up to one %s%s, %zd bytes nvram, %s irqs\n", + pr_info("%s: alarms up to one %s%s, %zd bytes nvram%s\n", cmos_rtc.rtc->dev.bus_id, is_valid_irq(rtc_irq) ? (cmos_rtc.mon_alrm diff --git a/drivers/rtc/rtc-dev.c b/drivers/rtc/rtc-dev.c index 079e9ed907e0..ecdea44ae4e5 100644 --- a/drivers/rtc/rtc-dev.c +++ b/drivers/rtc/rtc-dev.c @@ -446,9 +446,6 @@ static int rtc_dev_release(struct inode *inode, struct file *file) if (rtc->ops->release) rtc->ops->release(rtc->dev.parent); - if (file->f_flags & FASYNC) - rtc_dev_fasync(-1, file, 0); - clear_bit_unlock(RTC_DEV_BUSY, &rtc->flags); return 0; } diff --git a/drivers/rtc/rtc-ds1390.c b/drivers/rtc/rtc-ds1390.c new file mode 100644 index 000000000000..599e976bf014 --- /dev/null +++ b/drivers/rtc/rtc-ds1390.c @@ -0,0 +1,220 @@ +/* + * rtc-ds1390.c -- driver for DS1390/93/94 + * + * Copyright (C) 2008 Mercury IMC Ltd + * Written by Mark Jackson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * NOTE : Currently this driver only supports the bare minimum for read + * and write the RTC. The extra features provided by the chip family + * (alarms, trickle charger, different control registers) are unavailable. + */ + +#include +#include +#include +#include + +#define DS1390_REG_100THS 0x00 +#define DS1390_REG_SECONDS 0x01 +#define DS1390_REG_MINUTES 0x02 +#define DS1390_REG_HOURS 0x03 +#define DS1390_REG_DAY 0x04 +#define DS1390_REG_DATE 0x05 +#define DS1390_REG_MONTH_CENT 0x06 +#define DS1390_REG_YEAR 0x07 + +#define DS1390_REG_ALARM_100THS 0x08 +#define DS1390_REG_ALARM_SECONDS 0x09 +#define DS1390_REG_ALARM_MINUTES 0x0A +#define DS1390_REG_ALARM_HOURS 0x0B +#define DS1390_REG_ALARM_DAY_DATE 0x0C + +#define DS1390_REG_CONTROL 0x0D +#define DS1390_REG_STATUS 0x0E +#define DS1390_REG_TRICKLE 0x0F + +struct ds1390 { + struct rtc_device *rtc; + u8 txrx_buf[9]; /* cmd + 8 registers */ +}; + +static void ds1390_set_reg(struct device *dev, unsigned char address, + unsigned char data) +{ + struct spi_device *spi = to_spi_device(dev); + struct ds1390 *chip = dev_get_drvdata(dev); + + /* Set MSB to indicate write */ + chip->txrx_buf[0] = address | 0x80; + chip->txrx_buf[1] = data; + + /* do the i/o */ + spi_write_then_read(spi, chip->txrx_buf, 2, NULL, 0); +} + +static int ds1390_get_reg(struct device *dev, unsigned char address, + unsigned char *data) +{ + struct spi_device *spi = to_spi_device(dev); + struct ds1390 *chip = dev_get_drvdata(dev); + int status; + + if (!data) + return -EINVAL; + + /* Clear MSB to indicate read */ + chip->txrx_buf[0] = address & 0x7f; + /* do the i/o */ + status = spi_write_then_read(spi, chip->txrx_buf, 1, chip->txrx_buf, 1); + if (status != 0) + return status; + + *data = chip->txrx_buf[1]; + + return 0; +} + +static int ds1390_get_datetime(struct device *dev, struct rtc_time *dt) +{ + struct spi_device *spi = to_spi_device(dev); + struct ds1390 *chip = dev_get_drvdata(dev); + int status; + + /* build the message */ + chip->txrx_buf[0] = DS1390_REG_SECONDS; + + /* do the i/o */ + status = spi_write_then_read(spi, chip->txrx_buf, 1, chip->txrx_buf, 8); + if (status != 0) + return status; + + /* The chip sends data in this order: + * Seconds, Minutes, Hours, Day, Date, Month / Century, Year */ + dt->tm_sec = bcd2bin(chip->txrx_buf[0]); + dt->tm_min = bcd2bin(chip->txrx_buf[1]); + dt->tm_hour = bcd2bin(chip->txrx_buf[2]); + dt->tm_wday = bcd2bin(chip->txrx_buf[3]); + dt->tm_mday = bcd2bin(chip->txrx_buf[4]); + /* mask off century bit */ + dt->tm_mon = bcd2bin(chip->txrx_buf[5] & 0x7f) - 1; + /* adjust for century bit */ + dt->tm_year = bcd2bin(chip->txrx_buf[6]) + ((chip->txrx_buf[5] & 0x80) ? 100 : 0); + + return rtc_valid_tm(dt); +} + +static int ds1390_set_datetime(struct device *dev, struct rtc_time *dt) +{ + struct spi_device *spi = to_spi_device(dev); + struct ds1390 *chip = dev_get_drvdata(dev); + + /* build the message */ + chip->txrx_buf[0] = DS1390_REG_SECONDS | 0x80; + chip->txrx_buf[1] = bin2bcd(dt->tm_sec); + chip->txrx_buf[2] = bin2bcd(dt->tm_min); + chip->txrx_buf[3] = bin2bcd(dt->tm_hour); + chip->txrx_buf[4] = bin2bcd(dt->tm_wday); + chip->txrx_buf[5] = bin2bcd(dt->tm_mday); + chip->txrx_buf[6] = bin2bcd(dt->tm_mon + 1) | + ((dt->tm_year > 99) ? 0x80 : 0x00); + chip->txrx_buf[7] = bin2bcd(dt->tm_year % 100); + + /* do the i/o */ + return spi_write_then_read(spi, chip->txrx_buf, 8, NULL, 0); +} + +static int ds1390_read_time(struct device *dev, struct rtc_time *tm) +{ + return ds1390_get_datetime(dev, tm); +} + +static int ds1390_set_time(struct device *dev, struct rtc_time *tm) +{ + return ds1390_set_datetime(dev, tm); +} + +static const struct rtc_class_ops ds1390_rtc_ops = { + .read_time = ds1390_read_time, + .set_time = ds1390_set_time, +}; + +static int __devinit ds1390_probe(struct spi_device *spi) +{ + struct rtc_device *rtc; + unsigned char tmp; + struct ds1390 *chip; + int res; + + printk(KERN_DEBUG "DS1390 SPI RTC driver\n"); + + rtc = rtc_device_register("ds1390", + &spi->dev, &ds1390_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + printk(KERN_ALERT "RTC : unable to register device\n"); + return PTR_ERR(rtc); + } + + spi->mode = SPI_MODE_3; + spi->bits_per_word = 8; + spi_setup(spi); + + chip = kzalloc(sizeof *chip, GFP_KERNEL); + if (!chip) { + printk(KERN_ALERT "RTC : unable to allocate device memory\n"); + rtc_device_unregister(rtc); + return -ENOMEM; + } + chip->rtc = rtc; + dev_set_drvdata(&spi->dev, chip); + + res = ds1390_get_reg(&spi->dev, DS1390_REG_SECONDS, &tmp); + if (res) { + printk(KERN_ALERT "RTC : unable to read device\n"); + rtc_device_unregister(rtc); + return res; + } + + return 0; +} + +static int __devexit ds1390_remove(struct spi_device *spi) +{ + struct ds1390 *chip = platform_get_drvdata(spi); + struct rtc_device *rtc = chip->rtc; + + if (rtc) + rtc_device_unregister(rtc); + + kfree(chip); + + return 0; +} + +static struct spi_driver ds1390_driver = { + .driver = { + .name = "rtc-ds1390", + .owner = THIS_MODULE, + }, + .probe = ds1390_probe, + .remove = __devexit_p(ds1390_remove), +}; + +static __init int ds1390_init(void) +{ + return spi_register_driver(&ds1390_driver); +} +module_init(ds1390_init); + +static __exit void ds1390_exit(void) +{ + spi_unregister_driver(&ds1390_driver); +} +module_exit(ds1390_exit); + +MODULE_DESCRIPTION("DS1390/93/94 SPI RTC driver"); +MODULE_AUTHOR("Mark Jackson "); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-ds1672.c b/drivers/rtc/rtc-ds1672.c index 341d7a5b45a2..4e91419e8911 100644 --- a/drivers/rtc/rtc-ds1672.c +++ b/drivers/rtc/rtc-ds1672.c @@ -209,12 +209,18 @@ static int ds1672_probe(struct i2c_client *client, return err; } +static struct i2c_device_id ds1672_id[] = { + { "ds1672", 0 }, + { } +}; + static struct i2c_driver ds1672_driver = { .driver = { .name = "rtc-ds1672", }, .probe = &ds1672_probe, .remove = &ds1672_remove, + .id_table = ds1672_id, }; static int __init ds1672_init(void) diff --git a/drivers/rtc/rtc-ds3234.c b/drivers/rtc/rtc-ds3234.c index 37d131d03f33..45e5b106af73 100644 --- a/drivers/rtc/rtc-ds3234.c +++ b/drivers/rtc/rtc-ds3234.c @@ -189,7 +189,7 @@ static const struct rtc_class_ops ds3234_rtc_ops = { .set_time = ds3234_set_time, }; -static int ds3234_probe(struct spi_device *spi) +static int __devinit ds3234_probe(struct spi_device *spi) { struct rtc_device *rtc; unsigned char tmp; @@ -249,7 +249,7 @@ static int ds3234_probe(struct spi_device *spi) return 0; } -static int __exit ds3234_remove(struct spi_device *spi) +static int __devexit ds3234_remove(struct spi_device *spi) { struct ds3234 *chip = platform_get_drvdata(spi); struct rtc_device *rtc = chip->rtc; diff --git a/drivers/rtc/rtc-m48t59.c b/drivers/rtc/rtc-m48t59.c index 04b63dab6932..43afb7ab5289 100644 --- a/drivers/rtc/rtc-m48t59.c +++ b/drivers/rtc/rtc-m48t59.c @@ -87,6 +87,10 @@ static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm) dev_dbg(dev, "Century bit is enabled\n"); tm->tm_year += 100; /* one century */ } +#ifdef CONFIG_SPARC + /* Sun SPARC machines count years since 1968 */ + tm->tm_year += 68; +#endif tm->tm_wday = bcd2bin(val & 0x07); tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F); @@ -110,11 +114,20 @@ static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm) struct m48t59_private *m48t59 = platform_get_drvdata(pdev); unsigned long flags; u8 val = 0; + int year = tm->tm_year; + +#ifdef CONFIG_SPARC + /* Sun SPARC machines count years since 1968 */ + year -= 68; +#endif dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n", - tm->tm_year + 1900, tm->tm_mon, tm->tm_mday, + year + 1900, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); + if (year < 0) + return -EINVAL; + spin_lock_irqsave(&m48t59->lock, flags); /* Issue the WRITE command */ M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL); @@ -125,9 +138,9 @@ static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm) M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY); /* tm_mon is 0-11 */ M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH); - M48T59_WRITE(bin2bcd(tm->tm_year % 100), M48T59_YEAR); + M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR); - if (pdata->type == M48T59RTC_TYPE_M48T59 && (tm->tm_year / 100)) + if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100)) val = (M48T59_WDAY_CEB | M48T59_WDAY_CB); val |= (bin2bcd(tm->tm_wday) & 0x07); M48T59_WRITE(val, M48T59_WDAY); @@ -159,6 +172,10 @@ static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL); tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR)); +#ifdef CONFIG_SPARC + /* Sun SPARC machines count years since 1968 */ + tm->tm_year += 68; +#endif /* tm_mon is 0-11 */ tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1; @@ -192,11 +209,20 @@ static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) struct rtc_time *tm = &alrm->time; u8 mday, hour, min, sec; unsigned long flags; + int year = tm->tm_year; + +#ifdef CONFIG_SPARC + /* Sun SPARC machines count years since 1968 */ + year -= 68; +#endif /* If no irq, we don't support ALARM */ if (m48t59->irq == NO_IRQ) return -EIO; + if (year < 0) + return -EINVAL; + /* * 0xff means "always match" */ @@ -228,7 +254,7 @@ static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) spin_unlock_irqrestore(&m48t59->lock, flags); dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n", - tm->tm_year + 1900, tm->tm_mon, tm->tm_mday, + year + 1900, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); return 0; } diff --git a/drivers/rtc/rtc-max6900.c b/drivers/rtc/rtc-max6900.c index 80782798763f..a4f6665ab3c5 100644 --- a/drivers/rtc/rtc-max6900.c +++ b/drivers/rtc/rtc-max6900.c @@ -247,12 +247,18 @@ max6900_probe(struct i2c_client *client, const struct i2c_device_id *id) return 0; } +static struct i2c_device_id max6900_id[] = { + { "max6900", 0 }, + { } +}; + static struct i2c_driver max6900_driver = { .driver = { .name = "rtc-max6900", }, .probe = max6900_probe, .remove = max6900_remove, + .id_table = max6900_id, }; static int __init max6900_init(void) diff --git a/drivers/rtc/rtc-rx8581.c b/drivers/rtc/rtc-rx8581.c new file mode 100644 index 000000000000..c9522f3bc21c --- /dev/null +++ b/drivers/rtc/rtc-rx8581.c @@ -0,0 +1,281 @@ +/* + * An I2C driver for the Epson RX8581 RTC + * + * Author: Martyn Welch + * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Based on: rtc-pcf8563.c (An I2C driver for the Philips PCF8563 RTC) + * Copyright 2005-06 Tower Technologies + */ + +#include +#include +#include +#include +#include + +#define DRV_VERSION "0.1" + +#define RX8581_REG_SC 0x00 /* Second in BCD */ +#define RX8581_REG_MN 0x01 /* Minute in BCD */ +#define RX8581_REG_HR 0x02 /* Hour in BCD */ +#define RX8581_REG_DW 0x03 /* Day of Week */ +#define RX8581_REG_DM 0x04 /* Day of Month in BCD */ +#define RX8581_REG_MO 0x05 /* Month in BCD */ +#define RX8581_REG_YR 0x06 /* Year in BCD */ +#define RX8581_REG_RAM 0x07 /* RAM */ +#define RX8581_REG_AMN 0x08 /* Alarm Min in BCD*/ +#define RX8581_REG_AHR 0x09 /* Alarm Hour in BCD */ +#define RX8581_REG_ADM 0x0A +#define RX8581_REG_ADW 0x0A +#define RX8581_REG_TMR0 0x0B +#define RX8581_REG_TMR1 0x0C +#define RX8581_REG_EXT 0x0D /* Extension Register */ +#define RX8581_REG_FLAG 0x0E /* Flag Register */ +#define RX8581_REG_CTRL 0x0F /* Control Register */ + + +/* Flag Register bit definitions */ +#define RX8581_FLAG_UF 0x20 /* Update */ +#define RX8581_FLAG_TF 0x10 /* Timer */ +#define RX8581_FLAG_AF 0x08 /* Alarm */ +#define RX8581_FLAG_VLF 0x02 /* Voltage Low */ + +/* Control Register bit definitions */ +#define RX8581_CTRL_UIE 0x20 /* Update Interrupt Enable */ +#define RX8581_CTRL_TIE 0x10 /* Timer Interrupt Enable */ +#define RX8581_CTRL_AIE 0x08 /* Alarm Interrupt Enable */ +#define RX8581_CTRL_STOP 0x02 /* STOP bit */ +#define RX8581_CTRL_RESET 0x01 /* RESET bit */ + +static struct i2c_driver rx8581_driver; + +/* + * In the routines that deal directly with the rx8581 hardware, we use + * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. + */ +static int rx8581_get_datetime(struct i2c_client *client, struct rtc_time *tm) +{ + unsigned char date[7]; + int data, err; + + /* First we ensure that the "update flag" is not set, we read the + * time and date then re-read the "update flag". If the update flag + * has been set, we know that the time has changed during the read so + * we repeat the whole process again. + */ + data = i2c_smbus_read_byte_data(client, RX8581_REG_FLAG); + if (data < 0) { + dev_err(&client->dev, "Unable to read device flags\n"); + return -EIO; + } + + do { + /* If update flag set, clear it */ + if (data & RX8581_FLAG_UF) { + err = i2c_smbus_write_byte_data(client, + RX8581_REG_FLAG, (data & ~RX8581_FLAG_UF)); + if (err != 0) { + dev_err(&client->dev, "Unable to write device " + "flags\n"); + return -EIO; + } + } + + /* Now read time and date */ + err = i2c_smbus_read_i2c_block_data(client, RX8581_REG_SC, + 7, date); + if (err < 0) { + dev_err(&client->dev, "Unable to read date\n"); + return -EIO; + } + + /* Check flag register */ + data = i2c_smbus_read_byte_data(client, RX8581_REG_FLAG); + if (data < 0) { + dev_err(&client->dev, "Unable to read device flags\n"); + return -EIO; + } + } while (data & RX8581_FLAG_UF); + + if (data & RX8581_FLAG_VLF) + dev_info(&client->dev, + "low voltage detected, date/time is not reliable.\n"); + + dev_dbg(&client->dev, + "%s: raw data is sec=%02x, min=%02x, hr=%02x, " + "wday=%02x, mday=%02x, mon=%02x, year=%02x\n", + __func__, + date[0], date[1], date[2], date[3], date[4], date[5], date[6]); + + tm->tm_sec = bcd2bin(date[RX8581_REG_SC] & 0x7F); + tm->tm_min = bcd2bin(date[RX8581_REG_MN] & 0x7F); + tm->tm_hour = bcd2bin(date[RX8581_REG_HR] & 0x3F); /* rtc hr 0-23 */ + tm->tm_wday = ilog2(date[RX8581_REG_DW] & 0x7F); + tm->tm_mday = bcd2bin(date[RX8581_REG_DM] & 0x3F); + tm->tm_mon = bcd2bin(date[RX8581_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */ + tm->tm_year = bcd2bin(date[RX8581_REG_YR]); + if (tm->tm_year < 70) + tm->tm_year += 100; /* assume we are in 1970...2069 */ + + + dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __func__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); + + err = rtc_valid_tm(tm); + if (err < 0) + dev_err(&client->dev, "retrieved date/time is not valid.\n"); + + return err; +} + +static int rx8581_set_datetime(struct i2c_client *client, struct rtc_time *tm) +{ + int data, err; + unsigned char buf[7]; + + dev_dbg(&client->dev, "%s: secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __func__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); + + /* hours, minutes and seconds */ + buf[RX8581_REG_SC] = bin2bcd(tm->tm_sec); + buf[RX8581_REG_MN] = bin2bcd(tm->tm_min); + buf[RX8581_REG_HR] = bin2bcd(tm->tm_hour); + + buf[RX8581_REG_DM] = bin2bcd(tm->tm_mday); + + /* month, 1 - 12 */ + buf[RX8581_REG_MO] = bin2bcd(tm->tm_mon + 1); + + /* year and century */ + buf[RX8581_REG_YR] = bin2bcd(tm->tm_year % 100); + buf[RX8581_REG_DW] = (0x1 << tm->tm_wday); + + /* Stop the clock */ + data = i2c_smbus_read_byte_data(client, RX8581_REG_CTRL); + if (data < 0) { + dev_err(&client->dev, "Unable to read control register\n"); + return -EIO; + } + + err = i2c_smbus_write_byte_data(client, RX8581_REG_FLAG, + (data | RX8581_CTRL_STOP)); + if (err < 0) { + dev_err(&client->dev, "Unable to write control register\n"); + return -EIO; + } + + /* write register's data */ + err = i2c_smbus_write_i2c_block_data(client, RX8581_REG_SC, 7, buf); + if (err < 0) { + dev_err(&client->dev, "Unable to write to date registers\n"); + return -EIO; + } + + /* Restart the clock */ + data = i2c_smbus_read_byte_data(client, RX8581_REG_CTRL); + if (data < 0) { + dev_err(&client->dev, "Unable to read control register\n"); + return -EIO; + } + + err = i2c_smbus_write_byte_data(client, RX8581_REG_FLAG, + (data | ~(RX8581_CTRL_STOP))); + if (err != 0) { + dev_err(&client->dev, "Unable to write control register\n"); + return -EIO; + } + + return 0; +} + +static int rx8581_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + return rx8581_get_datetime(to_i2c_client(dev), tm); +} + +static int rx8581_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + return rx8581_set_datetime(to_i2c_client(dev), tm); +} + +static const struct rtc_class_ops rx8581_rtc_ops = { + .read_time = rx8581_rtc_read_time, + .set_time = rx8581_rtc_set_time, +}; + +static int __devinit rx8581_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct rtc_device *rtc; + + dev_dbg(&client->dev, "%s\n", __func__); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return -ENODEV; + + dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n"); + + rtc = rtc_device_register(rx8581_driver.driver.name, + &client->dev, &rx8581_rtc_ops, THIS_MODULE); + + if (IS_ERR(rtc)) + return PTR_ERR(rtc); + + i2c_set_clientdata(client, rtc); + + return 0; +} + +static int __devexit rx8581_remove(struct i2c_client *client) +{ + struct rtc_device *rtc = i2c_get_clientdata(client); + + rtc_device_unregister(rtc); + + return 0; +} + +static const struct i2c_device_id rx8581_id[] = { + { "rx8581", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rx8581_id); + +static struct i2c_driver rx8581_driver = { + .driver = { + .name = "rtc-rx8581", + .owner = THIS_MODULE, + }, + .probe = rx8581_probe, + .remove = __devexit_p(rx8581_remove), + .id_table = rx8581_id, +}; + +static int __init rx8581_init(void) +{ + return i2c_add_driver(&rx8581_driver); +} + +static void __exit rx8581_exit(void) +{ + i2c_del_driver(&rx8581_driver); +} + +MODULE_AUTHOR("Martyn Welch "); +MODULE_DESCRIPTION("Epson RX-8581 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); + +module_init(rx8581_init); +module_exit(rx8581_exit); diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c index 910bc704939c..f59277bbedaa 100644 --- a/drivers/rtc/rtc-s3c.c +++ b/drivers/rtc/rtc-s3c.c @@ -455,6 +455,8 @@ static int __devinit s3c_rtc_probe(struct platform_device *pdev) s3c_rtc_setfreq(&pdev->dev, 1); + device_init_wakeup(&pdev->dev, 1); + /* register RTC and exit */ rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops, @@ -507,7 +509,7 @@ static int s3c_rtc_resume(struct platform_device *pdev) #define s3c_rtc_resume NULL #endif -static struct platform_driver s3c2410_rtcdrv = { +static struct platform_driver s3c2410_rtc_driver = { .probe = s3c_rtc_probe, .remove = __devexit_p(s3c_rtc_remove), .suspend = s3c_rtc_suspend, @@ -523,12 +525,12 @@ static char __initdata banner[] = "S3C24XX RTC, (c) 2004,2006 Simtec Electronics static int __init s3c_rtc_init(void) { printk(banner); - return platform_driver_register(&s3c2410_rtcdrv); + return platform_driver_register(&s3c2410_rtc_driver); } static void __exit s3c_rtc_exit(void) { - platform_driver_unregister(&s3c2410_rtcdrv); + platform_driver_unregister(&s3c2410_rtc_driver); } module_init(s3c_rtc_init); diff --git a/drivers/rtc/rtc-starfire.c b/drivers/rtc/rtc-starfire.c index 7ccb0dd700af..5be98bfd7ed3 100644 --- a/drivers/rtc/rtc-starfire.c +++ b/drivers/rtc/rtc-starfire.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include @@ -16,11 +15,6 @@ MODULE_AUTHOR("David S. Miller "); MODULE_DESCRIPTION("Starfire RTC driver"); MODULE_LICENSE("GPL"); -struct starfire_rtc { - struct rtc_device *rtc; - spinlock_t lock; -}; - static u32 starfire_get_time(void) { static char obp_gettod[32]; @@ -35,64 +29,31 @@ static u32 starfire_get_time(void) static int starfire_read_time(struct device *dev, struct rtc_time *tm) { - struct starfire_rtc *p = dev_get_drvdata(dev); - unsigned long flags, secs; - - spin_lock_irqsave(&p->lock, flags); - secs = starfire_get_time(); - spin_unlock_irqrestore(&p->lock, flags); - - rtc_time_to_tm(secs, tm); - - return 0; -} - -static int starfire_set_time(struct device *dev, struct rtc_time *tm) -{ - unsigned long secs; - int err; - - err = rtc_tm_to_time(tm, &secs); - if (err) - return err; - - /* Do nothing, time is set using the service processor - * console on this platform. - */ - return 0; + rtc_time_to_tm(starfire_get_time(), tm); + return rtc_valid_tm(tm); } static const struct rtc_class_ops starfire_rtc_ops = { .read_time = starfire_read_time, - .set_time = starfire_set_time, }; -static int __devinit starfire_rtc_probe(struct platform_device *pdev) +static int __init starfire_rtc_probe(struct platform_device *pdev) { - struct starfire_rtc *p = kzalloc(sizeof(*p), GFP_KERNEL); - - if (!p) - return -ENOMEM; + struct rtc_device *rtc = rtc_device_register("starfire", &pdev->dev, + &starfire_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc)) + return PTR_ERR(rtc); - spin_lock_init(&p->lock); + platform_set_drvdata(pdev, rtc); - p->rtc = rtc_device_register("starfire", &pdev->dev, - &starfire_rtc_ops, THIS_MODULE); - if (IS_ERR(p->rtc)) { - int err = PTR_ERR(p->rtc); - kfree(p); - return err; - } - platform_set_drvdata(pdev, p); return 0; } -static int __devexit starfire_rtc_remove(struct platform_device *pdev) +static int __exit starfire_rtc_remove(struct platform_device *pdev) { - struct starfire_rtc *p = platform_get_drvdata(pdev); + struct rtc_device *rtc = platform_get_drvdata(pdev); - rtc_device_unregister(p->rtc); - kfree(p); + rtc_device_unregister(rtc); return 0; } @@ -102,13 +63,12 @@ static struct platform_driver starfire_rtc_driver = { .name = "rtc-starfire", .owner = THIS_MODULE, }, - .probe = starfire_rtc_probe, - .remove = __devexit_p(starfire_rtc_remove), + .remove = __exit_p(starfire_rtc_remove), }; static int __init starfire_rtc_init(void) { - return platform_driver_register(&starfire_rtc_driver); + return platform_driver_probe(&starfire_rtc_driver, starfire_rtc_probe); } static void __exit starfire_rtc_exit(void) diff --git a/drivers/rtc/rtc-sun4v.c b/drivers/rtc/rtc-sun4v.c index 2012ccbb4a53..5b2261052a65 100644 --- a/drivers/rtc/rtc-sun4v.c +++ b/drivers/rtc/rtc-sun4v.c @@ -1,4 +1,4 @@ -/* rtc-sun4c.c: Hypervisor based RTC for SUN4V systems. +/* rtc-sun4v.c: Hypervisor based RTC for SUN4V systems. * * Copyright (C) 2008 David S. Miller */ @@ -7,21 +7,11 @@ #include #include #include -#include #include #include #include -MODULE_AUTHOR("David S. Miller "); -MODULE_DESCRIPTION("SUN4V RTC driver"); -MODULE_LICENSE("GPL"); - -struct sun4v_rtc { - struct rtc_device *rtc; - spinlock_t lock; -}; - static unsigned long hypervisor_get_time(void) { unsigned long ret, time; @@ -45,15 +35,7 @@ retry: static int sun4v_read_time(struct device *dev, struct rtc_time *tm) { - struct sun4v_rtc *p = dev_get_drvdata(dev); - unsigned long flags, secs; - - spin_lock_irqsave(&p->lock, flags); - secs = hypervisor_get_time(); - spin_unlock_irqrestore(&p->lock, flags); - - rtc_time_to_tm(secs, tm); - + rtc_time_to_tm(hypervisor_get_time(), tm); return 0; } @@ -80,19 +62,14 @@ retry: static int sun4v_set_time(struct device *dev, struct rtc_time *tm) { - struct sun4v_rtc *p = dev_get_drvdata(dev); - unsigned long flags, secs; + unsigned long secs; int err; err = rtc_tm_to_time(tm, &secs); if (err) return err; - spin_lock_irqsave(&p->lock, flags); - err = hypervisor_set_time(secs); - spin_unlock_irqrestore(&p->lock, flags); - - return err; + return hypervisor_set_time(secs); } static const struct rtc_class_ops sun4v_rtc_ops = { @@ -100,33 +77,22 @@ static const struct rtc_class_ops sun4v_rtc_ops = { .set_time = sun4v_set_time, }; -static int __devinit sun4v_rtc_probe(struct platform_device *pdev) +static int __init sun4v_rtc_probe(struct platform_device *pdev) { - struct sun4v_rtc *p = kzalloc(sizeof(*p), GFP_KERNEL); - - if (!p) - return -ENOMEM; - - spin_lock_init(&p->lock); - - p->rtc = rtc_device_register("sun4v", &pdev->dev, + struct rtc_device *rtc = rtc_device_register("sun4v", &pdev->dev, &sun4v_rtc_ops, THIS_MODULE); - if (IS_ERR(p->rtc)) { - int err = PTR_ERR(p->rtc); - kfree(p); - return err; - } - platform_set_drvdata(pdev, p); + if (IS_ERR(rtc)) + return PTR_ERR(rtc); + + platform_set_drvdata(pdev, rtc); return 0; } -static int __devexit sun4v_rtc_remove(struct platform_device *pdev) +static int __exit sun4v_rtc_remove(struct platform_device *pdev) { - struct sun4v_rtc *p = platform_get_drvdata(pdev); - - rtc_device_unregister(p->rtc); - kfree(p); + struct rtc_device *rtc = platform_get_drvdata(pdev); + rtc_device_unregister(rtc); return 0; } @@ -135,13 +101,12 @@ static struct platform_driver sun4v_rtc_driver = { .name = "rtc-sun4v", .owner = THIS_MODULE, }, - .probe = sun4v_rtc_probe, - .remove = __devexit_p(sun4v_rtc_remove), + .remove = __exit_p(sun4v_rtc_remove), }; static int __init sun4v_rtc_init(void) { - return platform_driver_register(&sun4v_rtc_driver); + return platform_driver_probe(&sun4v_rtc_driver, sun4v_rtc_probe); } static void __exit sun4v_rtc_exit(void) @@ -151,3 +116,7 @@ static void __exit sun4v_rtc_exit(void) module_init(sun4v_rtc_init); module_exit(sun4v_rtc_exit); + +MODULE_AUTHOR("David S. Miller "); +MODULE_DESCRIPTION("SUN4V RTC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-twl4030.c b/drivers/rtc/rtc-twl4030.c index abe87a4d2665..01d8da9afdc8 100644 --- a/drivers/rtc/rtc-twl4030.c +++ b/drivers/rtc/rtc-twl4030.c @@ -337,7 +337,7 @@ static int twl4030_rtc_ioctl(struct device *dev, unsigned int cmd, } #else -#define omap_rtc_ioctl NULL +#define twl4030_rtc_ioctl NULL #endif static irqreturn_t twl4030_rtc_interrupt(int irq, void *rtc) diff --git a/drivers/rtc/rtc-wm8350.c b/drivers/rtc/rtc-wm8350.c new file mode 100644 index 000000000000..5c5e3aa91385 --- /dev/null +++ b/drivers/rtc/rtc-wm8350.c @@ -0,0 +1,514 @@ +/* + * Real Time Clock driver for Wolfson Microelectronics WM8350 + * + * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. + * + * Author: Liam Girdwood + * linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WM8350_SET_ALM_RETRIES 5 +#define WM8350_SET_TIME_RETRIES 5 +#define WM8350_GET_TIME_RETRIES 5 + +#define to_wm8350_from_rtc_dev(d) container_of(d, struct wm8350, rtc.pdev.dev) + +/* + * Read current time and date in RTC + */ +static int wm8350_rtc_readtime(struct device *dev, struct rtc_time *tm) +{ + struct wm8350 *wm8350 = dev_get_drvdata(dev); + u16 time1[4], time2[4]; + int retries = WM8350_GET_TIME_RETRIES, ret; + + /* + * Read the time twice and compare. + * If time1 == time2, then time is valid else retry. + */ + do { + ret = wm8350_block_read(wm8350, WM8350_RTC_SECONDS_MINUTES, + 4, time1); + if (ret < 0) + return ret; + ret = wm8350_block_read(wm8350, WM8350_RTC_SECONDS_MINUTES, + 4, time2); + if (ret < 0) + return ret; + + if (memcmp(time1, time2, sizeof(time1)) == 0) { + tm->tm_sec = time1[0] & WM8350_RTC_SECS_MASK; + + tm->tm_min = (time1[0] & WM8350_RTC_MINS_MASK) + >> WM8350_RTC_MINS_SHIFT; + + tm->tm_hour = time1[1] & WM8350_RTC_HRS_MASK; + + tm->tm_wday = ((time1[1] >> WM8350_RTC_DAY_SHIFT) + & 0x7) - 1; + + tm->tm_mon = ((time1[2] & WM8350_RTC_MTH_MASK) + >> WM8350_RTC_MTH_SHIFT) - 1; + + tm->tm_mday = (time1[2] & WM8350_RTC_DATE_MASK); + + tm->tm_year = ((time1[3] & WM8350_RTC_YHUNDREDS_MASK) + >> WM8350_RTC_YHUNDREDS_SHIFT) * 100; + tm->tm_year += time1[3] & WM8350_RTC_YUNITS_MASK; + + tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, + tm->tm_year); + tm->tm_year -= 1900; + + dev_dbg(dev, "Read (%d left): %04x %04x %04x %04x\n", + retries, + time1[0], time1[1], time1[2], time1[3]); + + return 0; + } + } while (retries--); + + dev_err(dev, "timed out reading RTC time\n"); + return -EIO; +} + +/* + * Set current time and date in RTC + */ +static int wm8350_rtc_settime(struct device *dev, struct rtc_time *tm) +{ + struct wm8350 *wm8350 = dev_get_drvdata(dev); + u16 time[4]; + u16 rtc_ctrl; + int ret, retries = WM8350_SET_TIME_RETRIES; + + time[0] = tm->tm_sec; + time[0] |= tm->tm_min << WM8350_RTC_MINS_SHIFT; + time[1] = tm->tm_hour; + time[1] |= (tm->tm_wday + 1) << WM8350_RTC_DAY_SHIFT; + time[2] = tm->tm_mday; + time[2] |= (tm->tm_mon + 1) << WM8350_RTC_MTH_SHIFT; + time[3] = ((tm->tm_year + 1900) / 100) << WM8350_RTC_YHUNDREDS_SHIFT; + time[3] |= (tm->tm_year + 1900) % 100; + + dev_dbg(dev, "Setting: %04x %04x %04x %04x\n", + time[0], time[1], time[2], time[3]); + + /* Set RTC_SET to stop the clock */ + ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL, WM8350_RTC_SET); + if (ret < 0) + return ret; + + /* Wait until confirmation of stopping */ + do { + rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL); + schedule_timeout_uninterruptible(msecs_to_jiffies(1)); + } while (retries-- && !(rtc_ctrl & WM8350_RTC_STS)); + + if (!retries) { + dev_err(dev, "timed out on set confirmation\n"); + return -EIO; + } + + /* Write time to RTC */ + ret = wm8350_block_write(wm8350, WM8350_RTC_SECONDS_MINUTES, 4, time); + if (ret < 0) + return ret; + + /* Clear RTC_SET to start the clock */ + ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL, + WM8350_RTC_SET); + return ret; +} + +/* + * Read alarm time and date in RTC + */ +static int wm8350_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct wm8350 *wm8350 = dev_get_drvdata(dev); + struct rtc_time *tm = &alrm->time; + u16 time[4]; + int ret; + + ret = wm8350_block_read(wm8350, WM8350_ALARM_SECONDS_MINUTES, 4, time); + if (ret < 0) + return ret; + + tm->tm_sec = time[0] & WM8350_RTC_ALMSECS_MASK; + if (tm->tm_sec == WM8350_RTC_ALMSECS_MASK) + tm->tm_sec = -1; + + tm->tm_min = time[0] & WM8350_RTC_ALMMINS_MASK; + if (tm->tm_min == WM8350_RTC_ALMMINS_MASK) + tm->tm_min = -1; + else + tm->tm_min >>= WM8350_RTC_ALMMINS_SHIFT; + + tm->tm_hour = time[1] & WM8350_RTC_ALMHRS_MASK; + if (tm->tm_hour == WM8350_RTC_ALMHRS_MASK) + tm->tm_hour = -1; + + tm->tm_wday = ((time[1] >> WM8350_RTC_ALMDAY_SHIFT) & 0x7) - 1; + if (tm->tm_wday > 7) + tm->tm_wday = -1; + + tm->tm_mon = time[2] & WM8350_RTC_ALMMTH_MASK; + if (tm->tm_mon == WM8350_RTC_ALMMTH_MASK) + tm->tm_mon = -1; + else + tm->tm_mon = (tm->tm_mon >> WM8350_RTC_ALMMTH_SHIFT) - 1; + + tm->tm_mday = (time[2] & WM8350_RTC_ALMDATE_MASK); + if (tm->tm_mday == WM8350_RTC_ALMDATE_MASK) + tm->tm_mday = -1; + + tm->tm_year = -1; + + alrm->enabled = !(time[3] & WM8350_RTC_ALMSTS); + + return 0; +} + +static int wm8350_rtc_stop_alarm(struct wm8350 *wm8350) +{ + int retries = WM8350_SET_ALM_RETRIES; + u16 rtc_ctrl; + int ret; + + /* Set RTC_SET to stop the clock */ + ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL, + WM8350_RTC_ALMSET); + if (ret < 0) + return ret; + + /* Wait until confirmation of stopping */ + do { + rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL); + schedule_timeout_uninterruptible(msecs_to_jiffies(1)); + } while (retries-- && !(rtc_ctrl & WM8350_RTC_ALMSTS)); + + if (!(rtc_ctrl & WM8350_RTC_ALMSTS)) + return -ETIMEDOUT; + + return 0; +} + +static int wm8350_rtc_start_alarm(struct wm8350 *wm8350) +{ + int ret; + int retries = WM8350_SET_ALM_RETRIES; + u16 rtc_ctrl; + + ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL, + WM8350_RTC_ALMSET); + if (ret < 0) + return ret; + + /* Wait until confirmation */ + do { + rtc_ctrl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL); + schedule_timeout_uninterruptible(msecs_to_jiffies(1)); + } while (retries-- && rtc_ctrl & WM8350_RTC_ALMSTS); + + if (rtc_ctrl & WM8350_RTC_ALMSTS) + return -ETIMEDOUT; + + return 0; +} + +static int wm8350_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct wm8350 *wm8350 = dev_get_drvdata(dev); + struct rtc_time *tm = &alrm->time; + u16 time[3]; + int ret; + + memset(time, 0, sizeof(time)); + + if (tm->tm_sec != -1) + time[0] |= tm->tm_sec; + else + time[0] |= WM8350_RTC_ALMSECS_MASK; + + if (tm->tm_min != -1) + time[0] |= tm->tm_min << WM8350_RTC_ALMMINS_SHIFT; + else + time[0] |= WM8350_RTC_ALMMINS_MASK; + + if (tm->tm_hour != -1) + time[1] |= tm->tm_hour; + else + time[1] |= WM8350_RTC_ALMHRS_MASK; + + if (tm->tm_wday != -1) + time[1] |= (tm->tm_wday + 1) << WM8350_RTC_ALMDAY_SHIFT; + else + time[1] |= WM8350_RTC_ALMDAY_MASK; + + if (tm->tm_mday != -1) + time[2] |= tm->tm_mday; + else + time[2] |= WM8350_RTC_ALMDATE_MASK; + + if (tm->tm_mon != -1) + time[2] |= (tm->tm_mon + 1) << WM8350_RTC_ALMMTH_SHIFT; + else + time[2] |= WM8350_RTC_ALMMTH_MASK; + + ret = wm8350_rtc_stop_alarm(wm8350); + if (ret < 0) + return ret; + + /* Write time to RTC */ + ret = wm8350_block_write(wm8350, WM8350_ALARM_SECONDS_MINUTES, + 3, time); + if (ret < 0) + return ret; + + if (alrm->enabled) + ret = wm8350_rtc_start_alarm(wm8350); + + return ret; +} + +/* + * Handle commands from user-space + */ +static int wm8350_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + struct wm8350 *wm8350 = dev_get_drvdata(dev); + + switch (cmd) { + case RTC_AIE_OFF: + return wm8350_rtc_stop_alarm(wm8350); + case RTC_AIE_ON: + return wm8350_rtc_start_alarm(wm8350); + + case RTC_UIE_OFF: + wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_SEC); + break; + case RTC_UIE_ON: + wm8350_unmask_irq(wm8350, WM8350_IRQ_RTC_SEC); + break; + + default: + return -ENOIOCTLCMD; + } + + return 0; +} + +static void wm8350_rtc_alarm_handler(struct wm8350 *wm8350, int irq, + void *data) +{ + struct rtc_device *rtc = wm8350->rtc.rtc; + int ret; + + rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF); + + /* Make it one shot */ + ret = wm8350_set_bits(wm8350, WM8350_RTC_TIME_CONTROL, + WM8350_RTC_ALMSET); + if (ret != 0) { + dev_err(&(wm8350->rtc.pdev->dev), + "Failed to disable alarm: %d\n", ret); + } +} + +static void wm8350_rtc_update_handler(struct wm8350 *wm8350, int irq, + void *data) +{ + struct rtc_device *rtc = wm8350->rtc.rtc; + + rtc_update_irq(rtc, 1, RTC_IRQF | RTC_UF); +} + +static const struct rtc_class_ops wm8350_rtc_ops = { + .ioctl = wm8350_rtc_ioctl, + .read_time = wm8350_rtc_readtime, + .set_time = wm8350_rtc_settime, + .read_alarm = wm8350_rtc_readalarm, + .set_alarm = wm8350_rtc_setalarm, +}; + +#ifdef CONFIG_PM +static int wm8350_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev); + int ret = 0; + u16 reg; + + reg = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL); + + if (device_may_wakeup(&wm8350->rtc.pdev->dev) && + reg & WM8350_RTC_ALMSTS) { + ret = wm8350_rtc_stop_alarm(wm8350); + if (ret != 0) + dev_err(&pdev->dev, "Failed to stop RTC alarm: %d\n", + ret); + } + + return ret; +} + +static int wm8350_rtc_resume(struct platform_device *pdev) +{ + struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev); + int ret; + + if (wm8350->rtc.alarm_enabled) { + ret = wm8350_rtc_start_alarm(wm8350); + if (ret != 0) + dev_err(&pdev->dev, + "Failed to restart RTC alarm: %d\n", ret); + } + + return 0; +} + +#else +#define wm8350_rtc_suspend NULL +#define wm8350_rtc_resume NULL +#endif + +static int wm8350_rtc_probe(struct platform_device *pdev) +{ + struct wm8350 *wm8350 = platform_get_drvdata(pdev); + struct wm8350_rtc *wm_rtc = &wm8350->rtc; + int ret = 0; + u16 timectl, power5; + + timectl = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL); + if (timectl & WM8350_RTC_BCD) { + dev_err(&pdev->dev, "RTC BCD mode not supported\n"); + return -EINVAL; + } + if (timectl & WM8350_RTC_12HR) { + dev_err(&pdev->dev, "RTC 12 hour mode not supported\n"); + return -EINVAL; + } + + /* enable the RTC if it's not already enabled */ + power5 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5); + if (!(power5 & WM8350_RTC_TICK_ENA)) { + dev_info(wm8350->dev, "Starting RTC\n"); + + wm8350_reg_unlock(wm8350); + + ret = wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, + WM8350_RTC_TICK_ENA); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable RTC: %d\n", ret); + return ret; + } + + wm8350_reg_lock(wm8350); + } + + if (timectl & WM8350_RTC_STS) { + int retries; + + ret = wm8350_clear_bits(wm8350, WM8350_RTC_TIME_CONTROL, + WM8350_RTC_SET); + if (ret < 0) { + dev_err(&pdev->dev, "failed to start: %d\n", ret); + return ret; + } + + retries = WM8350_SET_TIME_RETRIES; + do { + timectl = wm8350_reg_read(wm8350, + WM8350_RTC_TIME_CONTROL); + } while (timectl & WM8350_RTC_STS && retries--); + + if (retries == 0) { + dev_err(&pdev->dev, "failed to start: timeout\n"); + return -ENODEV; + } + } + + device_init_wakeup(&pdev->dev, 1); + + wm_rtc->rtc = rtc_device_register("wm8350", &pdev->dev, + &wm8350_rtc_ops, THIS_MODULE); + if (IS_ERR(wm_rtc->rtc)) { + ret = PTR_ERR(wm_rtc->rtc); + dev_err(&pdev->dev, "failed to register RTC: %d\n", ret); + return ret; + } + + wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_SEC); + wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_PER); + + wm8350_register_irq(wm8350, WM8350_IRQ_RTC_SEC, + wm8350_rtc_update_handler, NULL); + + wm8350_register_irq(wm8350, WM8350_IRQ_RTC_ALM, + wm8350_rtc_alarm_handler, NULL); + wm8350_unmask_irq(wm8350, WM8350_IRQ_RTC_ALM); + + return 0; +} + +static int __devexit wm8350_rtc_remove(struct platform_device *pdev) +{ + struct wm8350 *wm8350 = platform_get_drvdata(pdev); + struct wm8350_rtc *wm_rtc = &wm8350->rtc; + + wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_SEC); + + wm8350_free_irq(wm8350, WM8350_IRQ_RTC_SEC); + wm8350_free_irq(wm8350, WM8350_IRQ_RTC_ALM); + + rtc_device_unregister(wm_rtc->rtc); + + return 0; +} + +static struct platform_driver wm8350_rtc_driver = { + .probe = wm8350_rtc_probe, + .remove = __devexit_p(wm8350_rtc_remove), + .suspend = wm8350_rtc_suspend, + .resume = wm8350_rtc_resume, + .driver = { + .name = "wm8350-rtc", + }, +}; + +static int __init wm8350_rtc_init(void) +{ + return platform_driver_register(&wm8350_rtc_driver); +} +module_init(wm8350_rtc_init); + +static void __exit wm8350_rtc_exit(void) +{ + platform_driver_unregister(&wm8350_rtc_driver); +} +module_exit(wm8350_rtc_exit); + +MODULE_AUTHOR("Mark Brown "); +MODULE_DESCRIPTION("RTC driver for the WM8350"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:wm8350-rtc"); diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c index 4b76fca64a6f..363bd1303d21 100644 --- a/drivers/s390/block/dasd.c +++ b/drivers/s390/block/dasd.c @@ -1746,6 +1746,11 @@ restart: goto restart; } + /* log sense for fatal error */ + if (cqr->status == DASD_CQR_FAILED) { + dasd_log_sense(cqr, &cqr->irb); + } + /* First of all call extended error reporting. */ if (dasd_eer_enabled(base) && cqr->status == DASD_CQR_FAILED) { diff --git a/drivers/s390/char/sclp_cmd.c b/drivers/s390/char/sclp_cmd.c index eb5f1b8bc57f..ec9c0bcf66ee 100644 --- a/drivers/s390/char/sclp_cmd.c +++ b/drivers/s390/char/sclp_cmd.c @@ -324,6 +324,9 @@ static int do_assign_storage(sclp_cmdw_t cmd, u16 rn) case 0x0120: break; default: + pr_warning("assign storage failed (cmd=0x%08x, " + "response=0x%04x, rn=0x%04x)\n", cmd, + sccb->header.response_code, rn); rc = -EIO; break; } diff --git a/drivers/s390/char/tape_block.c b/drivers/s390/char/tape_block.c index 023803dbb0c7..ae18baf59f06 100644 --- a/drivers/s390/char/tape_block.c +++ b/drivers/s390/char/tape_block.c @@ -76,7 +76,7 @@ tapeblock_trigger_requeue(struct tape_device *device) static void tapeblock_end_request(struct request *req, int error) { - if (__blk_end_request(req, error, blk_rq_bytes(req))) + if (blk_end_request(req, error, blk_rq_bytes(req))) BUG(); } @@ -166,7 +166,7 @@ tapeblock_requeue(struct work_struct *work) { nr_queued++; spin_unlock(get_ccwdev_lock(device->cdev)); - spin_lock(&device->blk_data.request_queue_lock); + spin_lock_irq(&device->blk_data.request_queue_lock); while ( !blk_queue_plugged(queue) && elv_next_request(queue) && @@ -176,7 +176,9 @@ tapeblock_requeue(struct work_struct *work) { if (rq_data_dir(req) == WRITE) { DBF_EVENT(1, "TBLOCK: Rejecting write request\n"); blkdev_dequeue_request(req); + spin_unlock_irq(&device->blk_data.request_queue_lock); tapeblock_end_request(req, -EIO); + spin_lock_irq(&device->blk_data.request_queue_lock); continue; } blkdev_dequeue_request(req); diff --git a/drivers/s390/char/tape_core.c b/drivers/s390/char/tape_core.c index d7073dbf825c..f9bb51fa7f5b 100644 --- a/drivers/s390/char/tape_core.c +++ b/drivers/s390/char/tape_core.c @@ -1200,7 +1200,7 @@ tape_open(struct tape_device *device) { int rc; - spin_lock(get_ccwdev_lock(device->cdev)); + spin_lock_irq(get_ccwdev_lock(device->cdev)); if (device->tape_state == TS_NOT_OPER) { DBF_EVENT(6, "TAPE:nodev\n"); rc = -ENODEV; @@ -1218,7 +1218,7 @@ tape_open(struct tape_device *device) tape_state_set(device, TS_IN_USE); rc = 0; } - spin_unlock(get_ccwdev_lock(device->cdev)); + spin_unlock_irq(get_ccwdev_lock(device->cdev)); return rc; } @@ -1228,11 +1228,11 @@ tape_open(struct tape_device *device) int tape_release(struct tape_device *device) { - spin_lock(get_ccwdev_lock(device->cdev)); + spin_lock_irq(get_ccwdev_lock(device->cdev)); if (device->tape_state == TS_IN_USE) tape_state_set(device, TS_UNUSED); module_put(device->discipline->owner); - spin_unlock(get_ccwdev_lock(device->cdev)); + spin_unlock_irq(get_ccwdev_lock(device->cdev)); return 0; } diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c index 4e78c82194b4..4e4008325e28 100644 --- a/drivers/s390/cio/device.c +++ b/drivers/s390/cio/device.c @@ -874,11 +874,15 @@ void ccw_device_move_to_orphanage(struct work_struct *work) replacing_cdev = get_disc_ccwdev_by_dev_id(&dev_id, cdev); if (replacing_cdev) { sch_attach_disconnected_device(sch, replacing_cdev); + /* Release reference from get_disc_ccwdev_by_dev_id() */ + put_device(&cdev->dev); return; } replacing_cdev = get_orphaned_ccwdev_by_dev_id(css, &dev_id); if (replacing_cdev) { sch_attach_orphaned_device(sch, replacing_cdev); + /* Release reference from get_orphaned_ccwdev_by_dev_id() */ + put_device(&cdev->dev); return; } sch_create_and_recog_new_device(sch); diff --git a/drivers/s390/cio/qdio_debug.c b/drivers/s390/cio/qdio_debug.c index b5390821434f..f05590355be8 100644 --- a/drivers/s390/cio/qdio_debug.c +++ b/drivers/s390/cio/qdio_debug.c @@ -20,6 +20,7 @@ static struct dentry *debugfs_root; #define MAX_DEBUGFS_QUEUES 32 static struct dentry *debugfs_queues[MAX_DEBUGFS_QUEUES] = { NULL }; static DEFINE_MUTEX(debugfs_mutex); +#define QDIO_DEBUGFS_NAME_LEN 40 void qdio_allocate_do_dbf(struct qdio_initialize *init_data) { @@ -152,17 +153,6 @@ static int qstat_seq_open(struct inode *inode, struct file *filp) filp->f_path.dentry->d_inode->i_private); } -static void get_queue_name(struct qdio_q *q, struct ccw_device *cdev, char *name) -{ - memset(name, 0, sizeof(name)); - sprintf(name, "%s", dev_name(&cdev->dev)); - if (q->is_input_q) - sprintf(name + strlen(name), "_input"); - else - sprintf(name + strlen(name), "_output"); - sprintf(name + strlen(name), "_%d", q->nr); -} - static void remove_debugfs_entry(struct qdio_q *q) { int i; @@ -189,14 +179,17 @@ static struct file_operations debugfs_fops = { static void setup_debugfs_entry(struct qdio_q *q, struct ccw_device *cdev) { int i = 0; - char name[40]; + char name[QDIO_DEBUGFS_NAME_LEN]; while (debugfs_queues[i] != NULL) { i++; if (i >= MAX_DEBUGFS_QUEUES) return; } - get_queue_name(q, cdev, name); + snprintf(name, QDIO_DEBUGFS_NAME_LEN, "%s_%s_%d", + dev_name(&cdev->dev), + q->is_input_q ? "input" : "output", + q->nr); debugfs_queues[i] = debugfs_create_file(name, S_IFREG | S_IRUGO | S_IWUSR, debugfs_root, q, &debugfs_fops); } diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index a50682d2a0fa..7c8659151993 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -1083,7 +1083,6 @@ void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, case -EIO: sprintf(dbf_text, "ierr%4x", irq_ptr->schid.sch_no); QDIO_DBF_TEXT2(1, setup, dbf_text); - qdio_int_error(cdev); return; case -ETIMEDOUT: sprintf(dbf_text, "qtoh%4x", irq_ptr->schid.sch_no); diff --git a/drivers/s390/kvm/kvm_virtio.c b/drivers/s390/kvm/kvm_virtio.c index ff4a6931bb8e..3d442444c618 100644 --- a/drivers/s390/kvm/kvm_virtio.c +++ b/drivers/s390/kvm/kvm_virtio.c @@ -322,13 +322,13 @@ static int __init kvm_devices_init(void) return rc; } - rc = vmem_add_mapping(PFN_PHYS(max_pfn), PAGE_SIZE); + rc = vmem_add_mapping(real_memory_size, PAGE_SIZE); if (rc) { s390_root_dev_unregister(kvm_root); return rc; } - kvm_devices = (void *) PFN_PHYS(max_pfn); + kvm_devices = (void *) real_memory_size; ctl_set_bit(0, 9); register_external_interrupt(0x2603, kvm_extint_handler); diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 7de410d5be4a..52d26592c72c 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -3025,7 +3025,7 @@ static inline void __qeth_fill_buffer(struct sk_buff *skb, struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill, int offset) { - int length = skb->len - offset; + int length = skb->len; int length_here; int element; char *data; @@ -3037,6 +3037,7 @@ static inline void __qeth_fill_buffer(struct sk_buff *skb, if (offset >= 0) { data = skb->data + offset; + length -= offset; first_lap = 0; } diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index 955ba7a31b90..1b1e80336d2c 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c @@ -373,8 +373,6 @@ static int qeth_l2_stop_card(struct qeth_card *card, int recovery_mode) QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); qeth_set_allowed_threads(card, 0, 1); - if (qeth_wait_for_threads(card, ~QETH_RECOVER_THREAD)) - return -ERESTARTSYS; if (card->read.state == CH_STATE_UP && card->write.state == CH_STATE_UP && (card->state == CARD_STATE_UP)) { @@ -451,12 +449,15 @@ static void qeth_l2_process_inbound_buffer(struct qeth_card *card, netif_rx(skb); break; case QETH_HEADER_TYPE_OSN: - skb_push(skb, sizeof(struct qeth_hdr)); - skb_copy_to_linear_data(skb, hdr, + if (card->info.type == QETH_CARD_TYPE_OSN) { + skb_push(skb, sizeof(struct qeth_hdr)); + skb_copy_to_linear_data(skb, hdr, sizeof(struct qeth_hdr)); - len = skb->len; - card->osn_info.data_cb(skb); - break; + len = skb->len; + card->osn_info.data_cb(skb); + break; + } + /* else unknown */ default: dev_kfree_skb_any(skb); QETH_DBF_TEXT(TRACE, 3, "inbunkno"); @@ -975,12 +976,6 @@ static int __qeth_l2_set_online(struct ccwgroup_device *gdev, int recovery_mode) QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); qeth_set_allowed_threads(card, QETH_RECOVER_THREAD, 1); - if (qeth_wait_for_threads(card, ~QETH_RECOVER_THREAD)) { - PRINT_WARN("set_online of card %s interrupted by user!\n", - CARD_BUS_ID(card)); - return -ERESTARTSYS; - } - recover_flag = card->state; rc = ccw_device_set_online(CARD_RDEV(card)); if (rc) { @@ -1091,11 +1086,7 @@ static int __qeth_l2_set_offline(struct ccwgroup_device *cgdev, if (card->dev && netif_carrier_ok(card->dev)) netif_carrier_off(card->dev); recover_flag = card->state; - if (qeth_l2_stop_card(card, recovery_mode) == -ERESTARTSYS) { - PRINT_WARN("Stopping card %s interrupted by user!\n", - CARD_BUS_ID(card)); - return -ERESTARTSYS; - } + qeth_l2_stop_card(card, recovery_mode); rc = ccw_device_set_offline(CARD_DDEV(card)); rc2 = ccw_device_set_offline(CARD_WDEV(card)); rc3 = ccw_device_set_offline(CARD_RDEV(card)); diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 99547dea44de..ed59fedd5922 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -2064,8 +2064,6 @@ static int qeth_l3_stop_card(struct qeth_card *card, int recovery_mode) QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); qeth_set_allowed_threads(card, 0, 1); - if (qeth_wait_for_threads(card, ~QETH_RECOVER_THREAD)) - return -ERESTARTSYS; if (card->read.state == CH_STATE_UP && card->write.state == CH_STATE_UP && (card->state == CARD_STATE_UP)) { @@ -3049,11 +3047,6 @@ static int __qeth_l3_set_online(struct ccwgroup_device *gdev, int recovery_mode) QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); qeth_set_allowed_threads(card, QETH_RECOVER_THREAD, 1); - if (qeth_wait_for_threads(card, ~QETH_RECOVER_THREAD)) { - PRINT_WARN("set_online of card %s interrupted by user!\n", - CARD_BUS_ID(card)); - return -ERESTARTSYS; - } recover_flag = card->state; rc = ccw_device_set_online(CARD_RDEV(card)); @@ -3170,11 +3163,7 @@ static int __qeth_l3_set_offline(struct ccwgroup_device *cgdev, if (card->dev && netif_carrier_ok(card->dev)) netif_carrier_off(card->dev); recover_flag = card->state; - if (qeth_l3_stop_card(card, recovery_mode) == -ERESTARTSYS) { - PRINT_WARN("Stopping card %s interrupted by user!\n", - CARD_BUS_ID(card)); - return -ERESTARTSYS; - } + qeth_l3_stop_card(card, recovery_mode); rc = ccw_device_set_offline(CARD_DDEV(card)); rc2 = ccw_device_set_offline(CARD_WDEV(card)); rc3 = ccw_device_set_offline(CARD_RDEV(card)); diff --git a/drivers/s390/net/qeth_l3_sys.c b/drivers/s390/net/qeth_l3_sys.c index 210ddb639748..c144b9924d52 100644 --- a/drivers/s390/net/qeth_l3_sys.c +++ b/drivers/s390/net/qeth_l3_sys.c @@ -121,9 +121,6 @@ static ssize_t qeth_l3_dev_route6_show(struct device *dev, if (!card) return -EINVAL; - if (!qeth_is_supported(card, IPA_IPV6)) - return sprintf(buf, "%s\n", "n/a"); - return qeth_l3_dev_route_show(card, &card->options.route6, buf); } @@ -135,10 +132,6 @@ static ssize_t qeth_l3_dev_route6_store(struct device *dev, if (!card) return -EINVAL; - if (!qeth_is_supported(card, IPA_IPV6)) { - return -EOPNOTSUPP; - } - return qeth_l3_dev_route_store(card, &card->options.route6, QETH_PROT_IPV6, buf, count); } diff --git a/drivers/s390/scsi/zfcp_aux.c b/drivers/s390/scsi/zfcp_aux.c index 3b56220fb900..3d4e3e3f3fc0 100644 --- a/drivers/s390/scsi/zfcp_aux.c +++ b/drivers/s390/scsi/zfcp_aux.c @@ -610,7 +610,8 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, atomic_set_mask(status | ZFCP_STATUS_COMMON_REMOVE, &port->status); atomic_set(&port->refcount, 0); - dev_set_name(&port->sysfs_device, "0x%016llx", wwpn); + dev_set_name(&port->sysfs_device, "0x%016llx", + (unsigned long long)wwpn); port->sysfs_device.parent = &adapter->ccw_device->dev; port->sysfs_device.release = zfcp_sysfs_port_release; diff --git a/drivers/s390/scsi/zfcp_ccw.c b/drivers/s390/scsi/zfcp_ccw.c index b04038c74786..951a8d409d1d 100644 --- a/drivers/s390/scsi/zfcp_ccw.c +++ b/drivers/s390/scsi/zfcp_ccw.c @@ -116,7 +116,9 @@ static int zfcp_ccw_set_online(struct ccw_device *ccw_device) zfcp_erp_adapter_reopen(adapter, ZFCP_STATUS_COMMON_ERP_FAILED, 85, NULL); zfcp_erp_wait(adapter); - goto out; + up(&zfcp_data.config_sema); + flush_work(&adapter->scan_work); + return 0; out_scsi_register: zfcp_erp_thread_kill(adapter); diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c index 060f5f2352ec..31012d58cfb7 100644 --- a/drivers/s390/scsi/zfcp_dbf.c +++ b/drivers/s390/scsi/zfcp_dbf.c @@ -30,7 +30,7 @@ static void zfcp_dbf_hexdump(debug_info_t *dbf, void *to, int to_len, dump->offset = offset; dump->size = min(from_len - offset, room); memcpy(dump->data, from + offset, dump->size); - debug_event(dbf, level, dump, dump->size); + debug_event(dbf, level, dump, dump->size + sizeof(*dump)); } } @@ -108,7 +108,7 @@ static int zfcp_dbf_view_header(debug_info_t *id, struct debug_view *view, t.tv_sec, t.tv_nsec); zfcp_dbf_out(&p, "cpu", "%02i", entry->id.fields.cpuid); } else { - zfcp_dbf_outd(&p, NULL, dump->data, dump->size, dump->offset, + zfcp_dbf_outd(&p, "", dump->data, dump->size, dump->offset, dump->total_size); if ((dump->offset + dump->size) == dump->total_size) p += sprintf(p, "\n"); @@ -366,6 +366,7 @@ static void zfcp_hba_dbf_view_response(char **p, break; zfcp_dbf_out(p, "scsi_cmnd", "0x%0Lx", r->u.fcp.cmnd); zfcp_dbf_out(p, "scsi_serial", "0x%016Lx", r->u.fcp.serial); + p += sprintf(*p, "\n"); break; case FSF_QTCB_OPEN_PORT_WITH_DID: @@ -465,7 +466,8 @@ static int zfcp_hba_dbf_view_format(debug_info_t *id, struct debug_view *view, else if (strncmp(r->tag, "berr", ZFCP_DBF_TAG_SIZE) == 0) zfcp_hba_dbf_view_berr(&p, &r->u.berr); - p += sprintf(p, "\n"); + if (strncmp(r->tag, "resp", ZFCP_DBF_TAG_SIZE) != 0) + p += sprintf(p, "\n"); return p - out_buf; } @@ -880,6 +882,7 @@ void zfcp_san_dbf_event_ct_request(struct zfcp_fsf_req *fsf_req) struct ct_hdr *hdr = sg_virt(ct->req); struct zfcp_san_dbf_record *r = &adapter->san_dbf_buf; struct zfcp_san_dbf_record_ct_request *oct = &r->u.ct_req; + int level = 3; unsigned long flags; spin_lock_irqsave(&adapter->san_dbf_lock, flags); @@ -896,9 +899,10 @@ void zfcp_san_dbf_event_ct_request(struct zfcp_fsf_req *fsf_req) oct->options = hdr->options; oct->max_res_size = hdr->max_res_size; oct->len = min((int)ct->req->length - (int)sizeof(struct ct_hdr), - ZFCP_DBF_CT_PAYLOAD); - memcpy(oct->payload, (void *)hdr + sizeof(struct ct_hdr), oct->len); - debug_event(adapter->san_dbf, 3, r, sizeof(*r)); + ZFCP_DBF_SAN_MAX_PAYLOAD); + debug_event(adapter->san_dbf, level, r, sizeof(*r)); + zfcp_dbf_hexdump(adapter->san_dbf, r, sizeof(*r), level, + (void *)hdr + sizeof(struct ct_hdr), oct->len); spin_unlock_irqrestore(&adapter->san_dbf_lock, flags); } @@ -914,6 +918,7 @@ void zfcp_san_dbf_event_ct_response(struct zfcp_fsf_req *fsf_req) struct ct_hdr *hdr = sg_virt(ct->resp); struct zfcp_san_dbf_record *r = &adapter->san_dbf_buf; struct zfcp_san_dbf_record_ct_response *rct = &r->u.ct_resp; + int level = 3; unsigned long flags; spin_lock_irqsave(&adapter->san_dbf_lock, flags); @@ -929,9 +934,10 @@ void zfcp_san_dbf_event_ct_response(struct zfcp_fsf_req *fsf_req) rct->expl = hdr->reason_code_expl; rct->vendor_unique = hdr->vendor_unique; rct->len = min((int)ct->resp->length - (int)sizeof(struct ct_hdr), - ZFCP_DBF_CT_PAYLOAD); - memcpy(rct->payload, (void *)hdr + sizeof(struct ct_hdr), rct->len); - debug_event(adapter->san_dbf, 3, r, sizeof(*r)); + ZFCP_DBF_SAN_MAX_PAYLOAD); + debug_event(adapter->san_dbf, level, r, sizeof(*r)); + zfcp_dbf_hexdump(adapter->san_dbf, r, sizeof(*r), level, + (void *)hdr + sizeof(struct ct_hdr), rct->len); spin_unlock_irqrestore(&adapter->san_dbf_lock, flags); } @@ -954,7 +960,7 @@ static void zfcp_san_dbf_event_els(const char *tag, int level, rec->u.els.ls_code = ls_code; debug_event(adapter->san_dbf, level, rec, sizeof(*rec)); zfcp_dbf_hexdump(adapter->san_dbf, rec, sizeof(*rec), level, - buffer, min(buflen, ZFCP_DBF_ELS_MAX_PAYLOAD)); + buffer, min(buflen, ZFCP_DBF_SAN_MAX_PAYLOAD)); spin_unlock_irqrestore(&adapter->san_dbf_lock, flags); } @@ -1008,8 +1014,6 @@ static int zfcp_san_dbf_view_format(debug_info_t *id, struct debug_view *view, char *out_buf, const char *in_buf) { struct zfcp_san_dbf_record *r = (struct zfcp_san_dbf_record *)in_buf; - char *buffer = NULL; - int buflen = 0, total = 0; char *p = out_buf; if (strncmp(r->tag, "dump", ZFCP_DBF_TAG_SIZE) == 0) @@ -1029,9 +1033,6 @@ static int zfcp_san_dbf_view_format(debug_info_t *id, struct debug_view *view, zfcp_dbf_out(&p, "gs_subtype", "0x%02x", ct->gs_subtype); zfcp_dbf_out(&p, "options", "0x%02x", ct->options); zfcp_dbf_out(&p, "max_res_size", "0x%04x", ct->max_res_size); - total = ct->len; - buffer = ct->payload; - buflen = min(total, ZFCP_DBF_CT_PAYLOAD); } else if (strncmp(r->tag, "rctc", ZFCP_DBF_TAG_SIZE) == 0) { struct zfcp_san_dbf_record_ct_response *ct = &r->u.ct_resp; zfcp_dbf_out(&p, "cmd_rsp_code", "0x%04x", ct->cmd_rsp_code); @@ -1039,23 +1040,12 @@ static int zfcp_san_dbf_view_format(debug_info_t *id, struct debug_view *view, zfcp_dbf_out(&p, "reason_code", "0x%02x", ct->reason_code); zfcp_dbf_out(&p, "reason_code_expl", "0x%02x", ct->expl); zfcp_dbf_out(&p, "vendor_unique", "0x%02x", ct->vendor_unique); - total = ct->len; - buffer = ct->payload; - buflen = min(total, ZFCP_DBF_CT_PAYLOAD); } else if (strncmp(r->tag, "oels", ZFCP_DBF_TAG_SIZE) == 0 || strncmp(r->tag, "rels", ZFCP_DBF_TAG_SIZE) == 0 || strncmp(r->tag, "iels", ZFCP_DBF_TAG_SIZE) == 0) { struct zfcp_san_dbf_record_els *els = &r->u.els; zfcp_dbf_out(&p, "ls_code", "0x%02x", els->ls_code); - total = els->len; - buffer = els->payload; - buflen = min(total, ZFCP_DBF_ELS_PAYLOAD); } - - zfcp_dbf_outd(&p, "payload", buffer, buflen, 0, total); - if (buflen == total) - p += sprintf(p, "\n"); - return p - out_buf; } diff --git a/drivers/s390/scsi/zfcp_dbf.h b/drivers/s390/scsi/zfcp_dbf.h index e8f450801fea..5d6b2dff855b 100644 --- a/drivers/s390/scsi/zfcp_dbf.h +++ b/drivers/s390/scsi/zfcp_dbf.h @@ -163,8 +163,6 @@ struct zfcp_san_dbf_record_ct_request { u8 options; u16 max_res_size; u32 len; -#define ZFCP_DBF_CT_PAYLOAD 24 - u8 payload[ZFCP_DBF_CT_PAYLOAD]; } __attribute__ ((packed)); struct zfcp_san_dbf_record_ct_response { @@ -174,15 +172,11 @@ struct zfcp_san_dbf_record_ct_response { u8 expl; u8 vendor_unique; u32 len; - u8 payload[ZFCP_DBF_CT_PAYLOAD]; } __attribute__ ((packed)); struct zfcp_san_dbf_record_els { u8 ls_code; u32 len; -#define ZFCP_DBF_ELS_PAYLOAD 32 -#define ZFCP_DBF_ELS_MAX_PAYLOAD 1024 - u8 payload[ZFCP_DBF_ELS_PAYLOAD]; } __attribute__ ((packed)); struct zfcp_san_dbf_record { @@ -196,6 +190,8 @@ struct zfcp_san_dbf_record { struct zfcp_san_dbf_record_ct_response ct_resp; struct zfcp_san_dbf_record_els els; } u; +#define ZFCP_DBF_SAN_MAX_PAYLOAD 1024 + u8 payload[32]; } __attribute__ ((packed)); struct zfcp_scsi_dbf_record { diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c index 9040f738ff33..c557ba34e1aa 100644 --- a/drivers/s390/scsi/zfcp_erp.c +++ b/drivers/s390/scsi/zfcp_erp.c @@ -472,6 +472,7 @@ static void zfcp_erp_strategy_check_fsfreq(struct zfcp_erp_action *act) ZFCP_STATUS_ERP_TIMEDOUT)) { act->fsf_req->status |= ZFCP_STATUS_FSFREQ_DISMISSED; zfcp_rec_dbf_event_action(142, act); + act->fsf_req->erp_action = NULL; } if (act->status & ZFCP_STATUS_ERP_TIMEDOUT) zfcp_rec_dbf_event_action(143, act); @@ -719,7 +720,6 @@ static int zfcp_erp_adapter_strategy_generic(struct zfcp_erp_action *act, goto failed_openfcp; atomic_set_mask(ZFCP_STATUS_COMMON_OPEN, &act->adapter->status); - schedule_work(&act->adapter->scan_work); return ZFCP_ERP_SUCCEEDED; @@ -1185,7 +1185,9 @@ static void zfcp_erp_scsi_scan(struct work_struct *work) container_of(work, struct zfcp_erp_add_work, work); struct zfcp_unit *unit = p->unit; struct fc_rport *rport = unit->port->rport; - scsi_scan_target(&rport->dev, 0, rport->scsi_target_id, + + if (rport && rport->port_state == FC_PORTSTATE_ONLINE) + scsi_scan_target(&rport->dev, 0, rport->scsi_target_id, scsilun_to_int((struct scsi_lun *)&unit->fcp_lun), 0); atomic_clear_mask(ZFCP_STATUS_UNIT_SCSI_WORK_PENDING, &unit->status); zfcp_unit_put(unit); @@ -1281,6 +1283,8 @@ static void zfcp_erp_action_cleanup(struct zfcp_erp_action *act, int result) case ZFCP_ERP_ACTION_REOPEN_ADAPTER: if (result != ZFCP_ERP_SUCCEEDED) zfcp_erp_rports_del(adapter); + else + schedule_work(&adapter->scan_work); zfcp_adapter_put(adapter); break; } diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c index 1a7c80a77ff5..8aab3091a7b1 100644 --- a/drivers/s390/scsi/zfcp_fc.c +++ b/drivers/s390/scsi/zfcp_fc.c @@ -50,7 +50,8 @@ static int zfcp_wka_port_get(struct zfcp_wka_port *wka_port) if (mutex_lock_interruptible(&wka_port->mutex)) return -ERESTARTSYS; - if (wka_port->status != ZFCP_WKA_PORT_ONLINE) { + if (wka_port->status == ZFCP_WKA_PORT_OFFLINE || + wka_port->status == ZFCP_WKA_PORT_CLOSING) { wka_port->status = ZFCP_WKA_PORT_OPENING; if (zfcp_fsf_open_wka_port(wka_port)) wka_port->status = ZFCP_WKA_PORT_OFFLINE; @@ -125,8 +126,7 @@ static void _zfcp_fc_incoming_rscn(struct zfcp_fsf_req *fsf_req, u32 range, read_lock_irqsave(&zfcp_data.config_lock, flags); list_for_each_entry(port, &fsf_req->adapter->port_list_head, list) { - /* FIXME: ZFCP_STATUS_PORT_DID_DID check is racy */ - if (!(atomic_read(&port->status) & ZFCP_STATUS_PORT_DID_DID)) + if (!(atomic_read(&port->status) & ZFCP_STATUS_PORT_PHYS_OPEN)) /* Try to connect to unused ports anyway. */ zfcp_erp_port_reopen(port, ZFCP_STATUS_COMMON_ERP_FAILED, @@ -610,7 +610,6 @@ int zfcp_scan_ports(struct zfcp_adapter *adapter) int ret, i; struct zfcp_gpn_ft *gpn_ft; - zfcp_erp_wait(adapter); /* wait until adapter is finished with ERP */ if (fc_host_port_type(adapter->scsi_host) != FC_PORTTYPE_NPORT) return 0; diff --git a/drivers/s390/scsi/zfcp_fsf.c b/drivers/s390/scsi/zfcp_fsf.c index 5ae1d497e5ed..dc0367690405 100644 --- a/drivers/s390/scsi/zfcp_fsf.c +++ b/drivers/s390/scsi/zfcp_fsf.c @@ -683,6 +683,7 @@ static struct zfcp_fsf_req *zfcp_fsf_alloc_noqtcb(mempool_t *pool) if (!req) return NULL; memset(req, 0, sizeof(*req)); + req->pool = pool; return req; } @@ -769,28 +770,24 @@ static struct zfcp_fsf_req *zfcp_fsf_req_create(struct zfcp_adapter *adapter, static int zfcp_fsf_req_send(struct zfcp_fsf_req *req) { struct zfcp_adapter *adapter = req->adapter; - struct zfcp_qdio_queue *req_q = &adapter->req_q; + unsigned long flags; int idx; /* put allocated FSF request into hash table */ - spin_lock(&adapter->req_list_lock); + spin_lock_irqsave(&adapter->req_list_lock, flags); idx = zfcp_reqlist_hash(req->req_id); list_add_tail(&req->list, &adapter->req_list[idx]); - spin_unlock(&adapter->req_list_lock); + spin_unlock_irqrestore(&adapter->req_list_lock, flags); - req->qdio_outb_usage = atomic_read(&req_q->count); + req->qdio_outb_usage = atomic_read(&adapter->req_q.count); req->issued = get_clock(); if (zfcp_qdio_send(req)) { - /* Queues are down..... */ del_timer(&req->timer); - spin_lock(&adapter->req_list_lock); - zfcp_reqlist_remove(adapter, req); - spin_unlock(&adapter->req_list_lock); - /* undo changes in request queue made for this request */ - atomic_add(req->sbal_number, &req_q->count); - req_q->first -= req->sbal_number; - req_q->first += QDIO_MAX_BUFFERS_PER_Q; - req_q->first %= QDIO_MAX_BUFFERS_PER_Q; /* wrap */ + spin_lock_irqsave(&adapter->req_list_lock, flags); + /* lookup request again, list might have changed */ + if (zfcp_reqlist_find_safe(adapter, req)) + zfcp_reqlist_remove(adapter, req); + spin_unlock_irqrestore(&adapter->req_list_lock, flags); zfcp_erp_adapter_reopen(adapter, 0, 116, req); return -EIO; } @@ -933,8 +930,10 @@ struct zfcp_fsf_req *zfcp_fsf_abort_fcp_command(unsigned long old_req_id, goto out; req = zfcp_fsf_req_create(adapter, FSF_QTCB_ABORT_FCP_CMND, req_flags, adapter->pool.fsf_req_abort); - if (IS_ERR(req)) + if (IS_ERR(req)) { + req = NULL; goto out; + } if (unlikely(!(atomic_read(&unit->status) & ZFCP_STATUS_COMMON_UNBLOCKED))) @@ -1587,6 +1586,7 @@ static void zfcp_fsf_open_wka_port_handler(struct zfcp_fsf_req *req) wka_port->status = ZFCP_WKA_PORT_OFFLINE; break; case FSF_PORT_ALREADY_OPEN: + break; case FSF_GOOD: wka_port->handle = header->port_handle; wka_port->status = ZFCP_WKA_PORT_ONLINE; @@ -2116,18 +2116,21 @@ static inline void zfcp_fsf_trace_latency(struct zfcp_fsf_req *fsf_req) static void zfcp_fsf_send_fcp_command_task_handler(struct zfcp_fsf_req *req) { - struct scsi_cmnd *scpnt = req->data; + struct scsi_cmnd *scpnt; struct fcp_rsp_iu *fcp_rsp_iu = (struct fcp_rsp_iu *) &(req->qtcb->bottom.io.fcp_rsp); u32 sns_len; char *fcp_rsp_info = (unsigned char *) &fcp_rsp_iu[1]; unsigned long flags; - if (unlikely(!scpnt)) - return; - read_lock_irqsave(&req->adapter->abort_lock, flags); + scpnt = req->data; + if (unlikely(!scpnt)) { + read_unlock_irqrestore(&req->adapter->abort_lock, flags); + return; + } + if (unlikely(req->status & ZFCP_STATUS_FSFREQ_ABORTED)) { set_host_byte(scpnt, DID_SOFT_ERROR); set_driver_byte(scpnt, SUGGEST_RETRY); @@ -2445,8 +2448,10 @@ struct zfcp_fsf_req *zfcp_fsf_send_fcp_ctm(struct zfcp_adapter *adapter, goto out; req = zfcp_fsf_req_create(adapter, FSF_QTCB_FCP_CMND, req_flags, adapter->pool.fsf_req_scsi); - if (IS_ERR(req)) + if (IS_ERR(req)) { + req = NULL; goto out; + } req->status |= ZFCP_STATUS_FSFREQ_TASK_MANAGEMENT; req->data = unit; diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c index ca8f85f3dad4..468c880f8b6d 100644 --- a/drivers/s390/scsi/zfcp_scsi.c +++ b/drivers/s390/scsi/zfcp_scsi.c @@ -24,14 +24,10 @@ char *zfcp_get_fcp_sns_info_ptr(struct fcp_rsp_iu *fcp_rsp_iu) static void zfcp_scsi_slave_destroy(struct scsi_device *sdpnt) { struct zfcp_unit *unit = (struct zfcp_unit *) sdpnt->hostdata; - WARN_ON(!unit); - if (unit) { - atomic_clear_mask(ZFCP_STATUS_UNIT_REGISTERED, &unit->status); - sdpnt->hostdata = NULL; - unit->device = NULL; - zfcp_erp_unit_failed(unit, 12, NULL); - zfcp_unit_put(unit); - } + atomic_clear_mask(ZFCP_STATUS_UNIT_REGISTERED, &unit->status); + unit->device = NULL; + zfcp_erp_unit_failed(unit, 12, NULL); + zfcp_unit_put(unit); } static int zfcp_scsi_slave_configure(struct scsi_device *sdp) @@ -92,7 +88,7 @@ static int zfcp_scsi_queuecommand(struct scsi_cmnd *scpnt, ret = zfcp_fsf_send_fcp_command_task(adapter, unit, scpnt, 0, ZFCP_REQ_AUTO_CLEANUP); if (unlikely(ret == -EBUSY)) - zfcp_scsi_command_fail(scpnt, DID_NO_CONNECT); + return SCSI_MLQUEUE_DEVICE_BUSY; else if (unlikely(ret < 0)) return SCSI_MLQUEUE_HOST_BUSY; diff --git a/drivers/sbus/char/jsflash.c b/drivers/sbus/char/jsflash.c index 2bec9ccc0293..a9a9893a5f95 100644 --- a/drivers/sbus/char/jsflash.c +++ b/drivers/sbus/char/jsflash.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c index 9aa301c1ed07..94acbeed4e7c 100644 --- a/drivers/scsi/aacraid/linit.c +++ b/drivers/scsi/aacraid/linit.c @@ -175,8 +175,8 @@ static struct aac_driver_ident aac_drivers[] = { { aac_rx_init, "percraid", "DELL ", "PERCRAID ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* PERC 3/Di (Boxster/PERC3DiB) */ { aac_rx_init, "aacraid", "ADAPTEC ", "catapult ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* catapult */ { aac_rx_init, "aacraid", "ADAPTEC ", "tomcat ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* tomcat */ - { aac_rx_init, "aacraid", "ADAPTEC ", "Adaptec 2120S ", 1, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* Adaptec 2120S (Crusader) */ - { aac_rx_init, "aacraid", "ADAPTEC ", "Adaptec 2200S ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* Adaptec 2200S (Vulcan) */ + { aac_rx_init, "aacraid", "ADAPTEC ", "Adaptec 2120S ", 1, AAC_QUIRK_31BIT | AAC_QUIRK_34SG }, /* Adaptec 2120S (Crusader) */ + { aac_rx_init, "aacraid", "ADAPTEC ", "Adaptec 2200S ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG }, /* Adaptec 2200S (Vulcan) */ { aac_rx_init, "aacraid", "ADAPTEC ", "Adaptec 2200S ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* Adaptec 2200S (Vulcan-2m) */ { aac_rx_init, "aacraid", "Legend ", "Legend S220 ", 1, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* Legend S220 (Legend Crusader) */ { aac_rx_init, "aacraid", "Legend ", "Legend S230 ", 2, AAC_QUIRK_31BIT | AAC_QUIRK_34SG | AAC_QUIRK_SCSI_32 }, /* Legend S230 (Legend Vulcan) */ @@ -427,8 +427,8 @@ static int aac_slave_configure(struct scsi_device *sdev) * Firmware has an individual device recovery time typically * of 35 seconds, give us a margin. */ - if (sdev->timeout < (45 * HZ)) - sdev->timeout = 45 * HZ; + if (sdev->request_queue->rq_timeout < (45 * HZ)) + blk_queue_rq_timeout(sdev->request_queue, 45*HZ); for (cid = 0; cid < aac->maximum_num_containers; ++cid) if (aac->fsa_dev[cid].valid) ++num_lsu; diff --git a/drivers/scsi/advansys.c b/drivers/scsi/advansys.c index 218777bfc143..399fe559e4de 100644 --- a/drivers/scsi/advansys.c +++ b/drivers/scsi/advansys.c @@ -13872,8 +13872,10 @@ static int __devinit advansys_board_found(struct Scsi_Host *shost, advansys_wide_free_mem(boardp); free_irq(boardp->irq, shost); err_free_dma: +#ifdef CONFIG_ISA if (shost->dma_channel != NO_ISA_DMA) free_dma(shost->dma_channel); +#endif err_free_proc: kfree(boardp->prtbuf); err_unmap: @@ -13894,10 +13896,12 @@ static int advansys_release(struct Scsi_Host *shost) ASC_DBG(1, "begin\n"); scsi_remove_host(shost); free_irq(board->irq, shost); +#ifdef CONFIG_ISA if (shost->dma_channel != NO_ISA_DMA) { ASC_DBG(1, "free_dma()\n"); free_dma(shost->dma_channel); } +#endif if (ASC_NARROW_BOARD(board)) { dma_unmap_single(board->dev, board->dvc_var.asc_dvc_var.overrun_dma, diff --git a/drivers/scsi/device_handler/scsi_dh_hp_sw.c b/drivers/scsi/device_handler/scsi_dh_hp_sw.c index 9aec4ca64e56..f7da7530875e 100644 --- a/drivers/scsi/device_handler/scsi_dh_hp_sw.c +++ b/drivers/scsi/device_handler/scsi_dh_hp_sw.c @@ -107,6 +107,7 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h) struct request *req; int ret; +retry: req = blk_get_request(sdev->request_queue, WRITE, GFP_NOIO); if (!req) return SCSI_DH_RES_TEMP_UNAVAIL; @@ -121,7 +122,6 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h) memset(req->sense, 0, SCSI_SENSE_BUFFERSIZE); req->sense_len = 0; -retry: ret = blk_execute_rq(req->q, NULL, req, 1); if (ret == -EIO) { if (req->sense_len > 0) { @@ -136,8 +136,10 @@ retry: h->path_state = HP_SW_PATH_ACTIVE; ret = SCSI_DH_OK; } - if (ret == SCSI_DH_IMM_RETRY) + if (ret == SCSI_DH_IMM_RETRY) { + blk_put_request(req); goto retry; + } if (ret == SCSI_DH_DEV_OFFLINED) { h->path_state = HP_SW_PATH_PASSIVE; ret = SCSI_DH_OK; @@ -200,6 +202,7 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h) struct request *req; int ret, retry; +retry: req = blk_get_request(sdev->request_queue, WRITE, GFP_NOIO); if (!req) return SCSI_DH_RES_TEMP_UNAVAIL; @@ -216,7 +219,6 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h) req->sense_len = 0; retry = h->retries; -retry: ret = blk_execute_rq(req->q, NULL, req, 1); if (ret == -EIO) { if (req->sense_len > 0) { @@ -231,8 +233,10 @@ retry: ret = SCSI_DH_OK; if (ret == SCSI_DH_RETRY) { - if (--retry) + if (--retry) { + blk_put_request(req); goto retry; + } ret = SCSI_DH_IO; } diff --git a/drivers/scsi/dpt_i2o.c b/drivers/scsi/dpt_i2o.c index 8aba4fdfb522..6194ed5d02c4 100644 --- a/drivers/scsi/dpt_i2o.c +++ b/drivers/scsi/dpt_i2o.c @@ -2445,7 +2445,7 @@ static s32 adpt_i2o_to_scsi(void __iomem *reply, struct scsi_cmnd* cmd) hba_status = detailed_status >> 8; // calculate resid for sg - scsi_set_resid(cmd, scsi_bufflen(cmd) - readl(reply+5)); + scsi_set_resid(cmd, scsi_bufflen(cmd) - readl(reply+20)); pHba = (adpt_hba*) cmd->device->host->hostdata[0]; @@ -2456,7 +2456,7 @@ static s32 adpt_i2o_to_scsi(void __iomem *reply, struct scsi_cmnd* cmd) case I2O_SCSI_DSC_SUCCESS: cmd->result = (DID_OK << 16); // handle underflow - if(readl(reply+5) < cmd->underflow ) { + if (readl(reply+20) < cmd->underflow) { cmd->result = (DID_ERROR <<16); printk(KERN_WARNING"%s: SCSI CMD underflow\n",pHba->name); } diff --git a/drivers/scsi/fdomain.c b/drivers/scsi/fdomain.c index c33bcb284df7..56f4e6bffc21 100644 --- a/drivers/scsi/fdomain.c +++ b/drivers/scsi/fdomain.c @@ -290,9 +290,11 @@ #include #include "fdomain.h" +#ifndef PCMCIA MODULE_AUTHOR("Rickard E. Faith"); MODULE_DESCRIPTION("Future domain SCSI driver"); MODULE_LICENSE("GPL"); +#endif #define VERSION "$Revision: 5.51 $" diff --git a/drivers/scsi/gdth.c b/drivers/scsi/gdth.c index c387c15a2128..fb247fdfa2bd 100644 --- a/drivers/scsi/gdth.c +++ b/drivers/scsi/gdth.c @@ -588,7 +588,7 @@ static struct pci_driver gdth_pci_driver = { .remove = gdth_pci_remove_one, }; -static void gdth_pci_remove_one(struct pci_dev *pdev) +static void __devexit gdth_pci_remove_one(struct pci_dev *pdev) { gdth_ha_str *ha = pci_get_drvdata(pdev); @@ -600,7 +600,7 @@ static void gdth_pci_remove_one(struct pci_dev *pdev) pci_disable_device(pdev); } -static int gdth_pci_init_one(struct pci_dev *pdev, +static int __devinit gdth_pci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { ushort vendor = pdev->vendor; @@ -853,7 +853,7 @@ static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha) #endif /* CONFIG_ISA */ #ifdef CONFIG_PCI -static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr, +static int __devinit gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr, gdth_ha_str *ha) { register gdt6_dpram_str __iomem *dp6_ptr; @@ -1237,7 +1237,7 @@ static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr, /* controller protocol functions */ -static void __init gdth_enable_int(gdth_ha_str *ha) +static void __devinit gdth_enable_int(gdth_ha_str *ha) { ulong flags; gdt2_dpram_str __iomem *dp2_ptr; @@ -1553,7 +1553,7 @@ static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode, /* search for devices */ -static int __init gdth_search_drives(gdth_ha_str *ha) +static int __devinit gdth_search_drives(gdth_ha_str *ha) { ushort cdev_cnt, i; int ok; @@ -4935,7 +4935,7 @@ static int __init gdth_eisa_probe_one(ushort eisa_slot) #endif /* CONFIG_EISA */ #ifdef CONFIG_PCI -static int gdth_pci_probe_one(gdth_pci_str *pcistr, +static int __devinit gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out) { struct Scsi_Host *shp; diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c b/drivers/scsi/ibmvscsi/ibmvscsi.c index 87e09f35d3d4..6cad1758243a 100644 --- a/drivers/scsi/ibmvscsi/ibmvscsi.c +++ b/drivers/scsi/ibmvscsi/ibmvscsi.c @@ -1442,7 +1442,7 @@ static int ibmvscsi_slave_configure(struct scsi_device *sdev) spin_lock_irqsave(shost->host_lock, lock_flags); if (sdev->type == TYPE_DISK) { sdev->allow_restart = 1; - sdev->timeout = 60 * HZ; + blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); } scsi_adjust_queue_depth(sdev, 0, shost->cmd_per_lun); spin_unlock_irqrestore(shost->host_lock, lock_flags); diff --git a/drivers/scsi/ibmvscsi/ibmvstgt.c b/drivers/scsi/ibmvscsi/ibmvstgt.c index 2a5b29d12172..e2dd6a45924a 100644 --- a/drivers/scsi/ibmvscsi/ibmvstgt.c +++ b/drivers/scsi/ibmvscsi/ibmvstgt.c @@ -864,21 +864,23 @@ static int ibmvstgt_probe(struct vio_dev *dev, const struct vio_device_id *id) INIT_WORK(&vport->crq_work, handle_crq); - err = crq_queue_create(&vport->crq_queue, target); + err = scsi_add_host(shost, target->dev); if (err) goto free_srp_target; - err = scsi_add_host(shost, target->dev); + err = scsi_tgt_alloc_queue(shost); if (err) - goto destroy_queue; + goto remove_host; - err = scsi_tgt_alloc_queue(shost); + err = crq_queue_create(&vport->crq_queue, target); if (err) - goto destroy_queue; + goto free_queue; return 0; -destroy_queue: - crq_queue_destroy(target); +free_queue: + scsi_tgt_free_queue(shost); +remove_host: + scsi_remove_host(shost); free_srp_target: srp_target_free(target); put_host: diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 801c7cf54d2e..3fdee7370ccc 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -489,12 +489,6 @@ __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, if (!__kfifo_get(session->cmdpool.queue, (void*)&task, sizeof(void*))) return NULL; - - if ((hdr->opcode == (ISCSI_OP_NOOP_OUT | ISCSI_OP_IMMEDIATE)) && - hdr->ttt == RESERVED_ITT) { - conn->ping_task = task; - conn->last_ping = jiffies; - } } /* * released in complete pdu for task we expect a response for, and @@ -703,6 +697,11 @@ static void iscsi_send_nopout(struct iscsi_conn *conn, struct iscsi_nopin *rhdr) task = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)&hdr, NULL, 0); if (!task) iscsi_conn_printk(KERN_ERR, conn, "Could not send nopout\n"); + else if (!rhdr) { + /* only track our nops */ + conn->ping_task = task; + conn->last_ping = jiffies; + } } static int iscsi_handle_reject(struct iscsi_conn *conn, struct iscsi_hdr *hdr, diff --git a/drivers/scsi/megaraid.c b/drivers/scsi/megaraid.c index 28c9da7d4a5c..7dc62deb4087 100644 --- a/drivers/scsi/megaraid.c +++ b/drivers/scsi/megaraid.c @@ -4402,6 +4402,10 @@ mega_internal_command(adapter_t *adapter, megacmd_t *mc, mega_passthru *pthru) scb_t *scb; int rval; + scmd = scsi_allocate_command(GFP_KERNEL); + if (!scmd) + return -ENOMEM; + /* * The internal commands share one command id and hence are * serialized. This is so because we want to reserve maximum number of @@ -4412,12 +4416,11 @@ mega_internal_command(adapter_t *adapter, megacmd_t *mc, mega_passthru *pthru) scb = &adapter->int_scb; memset(scb, 0, sizeof(scb_t)); - scmd = &adapter->int_scmd; - memset(scmd, 0, sizeof(Scsi_Cmnd)); - sdev = kzalloc(sizeof(struct scsi_device), GFP_KERNEL); scmd->device = sdev; + memset(adapter->int_cdb, 0, sizeof(adapter->int_cdb)); + scmd->cmnd = adapter->int_cdb; scmd->device->host = adapter->host; scmd->host_scribble = (void *)scb; scmd->cmnd[0] = MEGA_INTERNAL_CMD; @@ -4456,6 +4459,8 @@ mega_internal_command(adapter_t *adapter, megacmd_t *mc, mega_passthru *pthru) mutex_unlock(&adapter->int_mtx); + scsi_free_command(GFP_KERNEL, scmd); + return rval; } diff --git a/drivers/scsi/megaraid.h b/drivers/scsi/megaraid.h index ee70bd4ae4ba..795201fa0b48 100644 --- a/drivers/scsi/megaraid.h +++ b/drivers/scsi/megaraid.h @@ -888,8 +888,8 @@ typedef struct { u8 sglen; /* f/w supported scatter-gather list length */ + unsigned char int_cdb[MAX_COMMAND_SIZE]; scb_t int_scb; - Scsi_Cmnd int_scmd; struct mutex int_mtx; /* To synchronize the internal commands */ struct completion int_waitq; /* wait queue for internal diff --git a/drivers/scsi/megaraid/megaraid_sas.c b/drivers/scsi/megaraid/megaraid_sas.c index afe1de998763..17ce7abe17ee 100644 --- a/drivers/scsi/megaraid/megaraid_sas.c +++ b/drivers/scsi/megaraid/megaraid_sas.c @@ -1016,7 +1016,8 @@ static int megasas_slave_configure(struct scsi_device *sdev) * The RAID firmware may require extended timeouts. */ if (sdev->channel >= MEGASAS_MAX_PD_CHANNELS) - sdev->timeout = MEGASAS_DEFAULT_CMD_TIMEOUT * HZ; + blk_queue_rq_timeout(sdev->request_queue, + MEGASAS_DEFAULT_CMD_TIMEOUT * HZ); return 0; } @@ -2987,17 +2988,6 @@ static int megasas_mgmt_open(struct inode *inode, struct file *filep) return 0; } -/** - * megasas_mgmt_release - char node "release" entry point - */ -static int megasas_mgmt_release(struct inode *inode, struct file *filep) -{ - filep->private_data = NULL; - fasync_helper(-1, filep, 0, &megasas_async_queue); - - return 0; -} - /** * megasas_mgmt_fasync - Async notifier registration from applications * @@ -3345,7 +3335,6 @@ megasas_mgmt_compat_ioctl(struct file *file, unsigned int cmd, static const struct file_operations megasas_mgmt_fops = { .owner = THIS_MODULE, .open = megasas_mgmt_open, - .release = megasas_mgmt_release, .fasync = megasas_mgmt_fasync, .unlocked_ioctl = megasas_mgmt_ioctl, #ifdef CONFIG_COMPAT diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h index f25f41a499e5..b97194096d8e 100644 --- a/drivers/scsi/qla2xxx/qla_def.h +++ b/drivers/scsi/qla2xxx/qla_def.h @@ -2547,7 +2547,6 @@ typedef struct scsi_qla_host { uint8_t fcode_revision[16]; uint32_t fw_revision[4]; - uint16_t fdt_odd_index; uint32_t fdt_wrt_disable; uint32_t fdt_erase_cmd; uint32_t fdt_block_size; diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index a470f2d3270d..4218f20f5ed5 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c @@ -140,7 +140,6 @@ int qla2100_pci_config(scsi_qla_host_t *ha) { uint16_t w; - uint32_t d; unsigned long flags; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; @@ -151,10 +150,7 @@ qla2100_pci_config(scsi_qla_host_t *ha) w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); pci_write_config_word(ha->pdev, PCI_COMMAND, w); - /* Reset expansion ROM address decode enable */ - pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); - d &= ~PCI_ROM_ADDRESS_ENABLE; - pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); + pci_disable_rom(ha->pdev); /* Get PCI bus information. */ spin_lock_irqsave(&ha->hardware_lock, flags); @@ -174,7 +170,6 @@ int qla2300_pci_config(scsi_qla_host_t *ha) { uint16_t w; - uint32_t d; unsigned long flags = 0; uint32_t cnt; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; @@ -236,10 +231,7 @@ qla2300_pci_config(scsi_qla_host_t *ha) pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); - /* Reset expansion ROM address decode enable */ - pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); - d &= ~PCI_ROM_ADDRESS_ENABLE; - pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); + pci_disable_rom(ha->pdev); /* Get PCI bus information. */ spin_lock_irqsave(&ha->hardware_lock, flags); @@ -259,7 +251,6 @@ int qla24xx_pci_config(scsi_qla_host_t *ha) { uint16_t w; - uint32_t d; unsigned long flags = 0; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; @@ -281,10 +272,7 @@ qla24xx_pci_config(scsi_qla_host_t *ha) if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) pcie_set_readrq(ha->pdev, 2048); - /* Reset expansion ROM address decode enable */ - pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); - d &= ~PCI_ROM_ADDRESS_ENABLE; - pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); + pci_disable_rom(ha->pdev); ha->chip_revision = ha->pdev->revision; @@ -306,7 +294,6 @@ int qla25xx_pci_config(scsi_qla_host_t *ha) { uint16_t w; - uint32_t d; pci_set_master(ha->pdev); pci_try_set_mwi(ha->pdev); @@ -320,10 +307,7 @@ qla25xx_pci_config(scsi_qla_host_t *ha) if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) pcie_set_readrq(ha->pdev, 2048); - /* Reset expansion ROM address decode enable */ - pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); - d &= ~PCI_ROM_ADDRESS_ENABLE; - pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); + pci_disable_rom(ha->pdev); ha->chip_revision = ha->pdev->revision; @@ -980,7 +964,6 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) &ha->fw_minor_version, &ha->fw_subminor_version, &ha->fw_attributes, &ha->fw_memory_size); - qla2x00_resize_request_q(ha); ha->flags.npiv_supported = 0; if ((IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA84XX(ha)) && @@ -992,6 +975,7 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; } + qla2x00_resize_request_q(ha); if (ql2xallocfwdump) qla2x00_alloc_fw_dump(ha); diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c index 36bc6851e23d..3402746ec128 100644 --- a/drivers/scsi/qla2xxx/qla_mbx.c +++ b/drivers/scsi/qla2xxx/qla_mbx.c @@ -1964,7 +1964,7 @@ qla2x00_get_resource_cnts(scsi_qla_host_t *ha, uint16_t *cur_xchg_cnt, *cur_iocb_cnt = mcp->mb[7]; if (orig_iocb_cnt) *orig_iocb_cnt = mcp->mb[10]; - if (max_npiv_vports) + if (ha->flags.npiv_supported && max_npiv_vports) *max_npiv_vports = mcp->mb[11]; } diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 21dd182ad512..35567203ef61 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -728,6 +728,7 @@ qla2xxx_eh_abort(struct scsi_cmnd *cmd) if (ha->isp_ops->abort_command(ha, sp)) { DEBUG2(printk("%s(%ld): abort_command " "mbx failed.\n", __func__, ha->host_no)); + ret = FAILED; } else { DEBUG3(printk("%s(%ld): abort_command " "mbx success.\n", __func__, ha->host_no)); diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c index 90a13211717f..e4af678eb2d6 100644 --- a/drivers/scsi/qla2xxx/qla_sup.c +++ b/drivers/scsi/qla2xxx/qla_sup.c @@ -722,6 +722,7 @@ done: static void qla2xxx_get_fdt_info(scsi_qla_host_t *ha) { +#define FLASH_BLK_SIZE_4K 0x1000 #define FLASH_BLK_SIZE_32K 0x8000 #define FLASH_BLK_SIZE_64K 0x10000 const char *loc, *locations[] = { "MID", "FDT" }; @@ -755,7 +756,6 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *ha) loc = locations[1]; mid = le16_to_cpu(fdt->man_id); fid = le16_to_cpu(fdt->id); - ha->fdt_odd_index = mid == 0x1f; ha->fdt_wrt_disable = fdt->wrt_disable_bits; ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd); ha->fdt_block_size = le32_to_cpu(fdt->block_size); @@ -788,8 +788,7 @@ no_flash_data: ha->fdt_block_size = FLASH_BLK_SIZE_64K; break; case 0x1f: /* Atmel 26DF081A. */ - ha->fdt_odd_index = 1; - ha->fdt_block_size = FLASH_BLK_SIZE_64K; + ha->fdt_block_size = FLASH_BLK_SIZE_4K; ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320); ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339); ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336); @@ -801,9 +800,9 @@ no_flash_data: } done: DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " - "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n", loc, mid, fid, + "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, - ha->fdt_unprotect_sec_cmd, ha->fdt_odd_index, ha->fdt_wrt_disable, + ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable, ha->fdt_block_size)); } @@ -987,13 +986,9 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, qla24xx_unprotect_flash(ha); for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { - if (ha->fdt_odd_index) { - findex = faddr << 2; - fdata = findex & sec_mask; - } else { - findex = faddr; - fdata = (findex & sec_mask) << 2; - } + + findex = faddr; + fdata = (findex & sec_mask) << 2; /* Are we at the beginning of a sector? */ if ((findex & rest_addr) == 0) { diff --git a/drivers/scsi/qla2xxx/qla_version.h b/drivers/scsi/qla2xxx/qla_version.h index be5e299df528..eea6720adf16 100644 --- a/drivers/scsi/qla2xxx/qla_version.h +++ b/drivers/scsi/qla2xxx/qla_version.h @@ -7,7 +7,7 @@ /* * Driver version */ -#define QLA2XXX_VERSION "8.02.01-k8" +#define QLA2XXX_VERSION "8.02.01-k9" #define QLA_DRIVER_MAJOR_VER 8 #define QLA_DRIVER_MINOR_VER 2 diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c index 94ed262bdf0c..edfaf241c5ba 100644 --- a/drivers/scsi/scsi_error.c +++ b/drivers/scsi/scsi_error.c @@ -932,8 +932,7 @@ static int scsi_eh_try_stu(struct scsi_cmnd *scmd) int i, rtn = NEEDS_RETRY; for (i = 0; rtn == NEEDS_RETRY && i < 2; i++) - rtn = scsi_send_eh_cmnd(scmd, stu_command, 6, - scmd->device->timeout, 0); + rtn = scsi_send_eh_cmnd(scmd, stu_command, 6, scmd->device->request_queue->rq_timeout, 0); if (rtn == SUCCESS) return 0; @@ -1340,9 +1339,10 @@ int scsi_decide_disposition(struct scsi_cmnd *scmd) * LLD/transport was disrupted during processing of the IO. * The transport class is now blocked/blocking, * and the transport will decide what to do with the IO - * based on its timers and recovery capablilities. + * based on its timers and recovery capablilities if + * there are enough retries. */ - return ADD_TO_MLQUEUE; + goto maybe_retry; case DID_TRANSPORT_FAILFAST: /* * The transport decided to failfast the IO (most likely diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index f5d3b96890dc..148d3af92aef 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -567,15 +567,18 @@ static inline int scsi_host_is_busy(struct Scsi_Host *shost) */ static void scsi_run_queue(struct request_queue *q) { - struct scsi_device *starved_head = NULL, *sdev = q->queuedata; + struct scsi_device *sdev = q->queuedata; struct Scsi_Host *shost = sdev->host; + LIST_HEAD(starved_list); unsigned long flags; if (scsi_target(sdev)->single_lun) scsi_single_lun_run(sdev); spin_lock_irqsave(shost->host_lock, flags); - while (!list_empty(&shost->starved_list) && !scsi_host_is_busy(shost)) { + list_splice_init(&shost->starved_list, &starved_list); + + while (!list_empty(&starved_list)) { int flagset; /* @@ -588,24 +591,18 @@ static void scsi_run_queue(struct request_queue *q) * scsi_request_fn must get the host_lock before checking * or modifying starved_list or starved_entry. */ - sdev = list_entry(shost->starved_list.next, - struct scsi_device, starved_entry); - /* - * The *queue_ready functions can add a device back onto the - * starved list's tail, so we must check for a infinite loop. - */ - if (sdev == starved_head) + if (scsi_host_is_busy(shost)) break; - if (!starved_head) - starved_head = sdev; + sdev = list_entry(starved_list.next, + struct scsi_device, starved_entry); + list_del_init(&sdev->starved_entry); if (scsi_target_is_busy(scsi_target(sdev))) { list_move_tail(&sdev->starved_entry, &shost->starved_list); continue; } - list_del_init(&sdev->starved_entry); spin_unlock(shost->host_lock); spin_lock(sdev->request_queue->queue_lock); @@ -621,6 +618,8 @@ static void scsi_run_queue(struct request_queue *q) spin_lock(shost->host_lock); } + /* put any unprocessed entries back */ + list_splice(&starved_list, &shost->starved_list); spin_unlock_irqrestore(shost->host_lock, flags); blk_run_queue(q); @@ -649,8 +648,8 @@ static void scsi_requeue_command(struct request_queue *q, struct scsi_cmnd *cmd) struct request *req = cmd->request; unsigned long flags; - scsi_unprep_request(req); spin_lock_irqsave(q->queue_lock, flags); + scsi_unprep_request(req); blk_requeue_request(q, req); spin_unlock_irqrestore(q->queue_lock, flags); diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index c9e1242eaf25..5081b3981d3c 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c @@ -757,7 +757,7 @@ static int sd_ioctl(struct block_device *bdev, fmode_t mode, * access to the device is prohibited. */ error = scsi_nonblockable_ioctl(sdp, cmd, p, - (mode & FMODE_NDELAY_NOW) != 0); + (mode & FMODE_NDELAY) != 0); if (!scsi_block_when_processing_errors(sdp) || !error) return error; diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c index 9adf35bd8b56..5103855242ae 100644 --- a/drivers/scsi/sg.c +++ b/drivers/scsi/sg.c @@ -327,7 +327,6 @@ sg_release(struct inode *inode, struct file *filp) if ((!(sfp = (Sg_fd *) filp->private_data)) || (!(sdp = sfp->parentdp))) return -ENXIO; SCSI_LOG_TIMEOUT(3, printk("sg_release: %s\n", sdp->disk->disk_name)); - sg_fasync(-1, filp, 0); /* remove filp from async notification list */ if (0 == sg_remove_sfp(sdp, sfp)) { /* Returns 1 when sdp gone */ if (!sdp->detached) { scsi_device_put(sdp->device); diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c index 62b6633e3a97..45b66b98a516 100644 --- a/drivers/scsi/sr.c +++ b/drivers/scsi/sr.c @@ -521,7 +521,7 @@ static int sr_block_ioctl(struct block_device *bdev, fmode_t mode, unsigned cmd, * if it doesn't recognise the ioctl */ ret = scsi_nonblockable_ioctl(sdev, cmd, argp, - (mode & FMODE_NDELAY_NOW) != 0); + (mode & FMODE_NDELAY) != 0); if (ret != -ENODEV) return ret; return scsi_ioctl(sdev, cmd, argp); diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c index 3790906a77d1..2fa830c0be27 100644 --- a/drivers/scsi/stex.c +++ b/drivers/scsi/stex.c @@ -477,7 +477,7 @@ stex_slave_config(struct scsi_device *sdev) { sdev->use_10_for_rw = 1; sdev->use_10_for_ms = 1; - sdev->timeout = 60 * HZ; + blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); sdev->tagged_supported = 1; return 0; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c94d3c4b7521..579d63a81aa2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1276,7 +1276,7 @@ config SERIAL_SGI_IOC3 say Y or M. Otherwise, say N. config SERIAL_NETX - bool "NetX serial port support" + tristate "NetX serial port support" depends on ARM && ARCH_NETX select SERIAL_CORE help @@ -1288,7 +1288,7 @@ config SERIAL_NETX config SERIAL_NETX_CONSOLE bool "Console on NetX serial port" - depends on SERIAL_NETX + depends on SERIAL_NETX=y select SERIAL_CORE_CONSOLE help If you have enabled the serial port on the Hilscher NetX SoC diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c index 61fb8b6d19af..d5efd6c77904 100644 --- a/drivers/serial/atmel_serial.c +++ b/drivers/serial/atmel_serial.c @@ -1258,6 +1258,8 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, atmel_port->clk = clk_get(&pdev->dev, "usart"); clk_enable(atmel_port->clk); port->uartclk = clk_get_rate(atmel_port->clk); + clk_disable(atmel_port->clk); + /* only enable clock when USART is in use */ } atmel_port->use_dma_rx = data->use_dma_rx; @@ -1379,6 +1381,8 @@ static int __init atmel_console_setup(struct console *co, char *options) return -ENODEV; } + clk_enable(atmel_ports[co->index].clk); + UART_PUT_IDR(port, -1); UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); @@ -1403,7 +1407,7 @@ static struct console atmel_console = { .data = &atmel_uart, }; -#define ATMEL_CONSOLE_DEVICE &atmel_console +#define ATMEL_CONSOLE_DEVICE (&atmel_console) /* * Early console initialization (before VM subsystem initialized). @@ -1534,6 +1538,15 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev) if (ret) goto err_add_port; + if (atmel_is_console_port(&port->uart) + && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { + /* + * The serial core enabled the clock for us, so undo + * the clk_enable() in atmel_console_setup() + */ + clk_disable(port->clk); + } + device_init_wakeup(&pdev->dev, 1); platform_set_drvdata(pdev, port); @@ -1544,7 +1557,6 @@ err_add_port: port->rx_ring.buf = NULL; err_alloc_ring: if (!atmel_is_console_port(&port->uart)) { - clk_disable(port->clk); clk_put(port->clk); port->clk = NULL; } @@ -1568,7 +1580,6 @@ static int __devexit atmel_serial_remove(struct platform_device *pdev) /* "port" is allocated statically, so we shouldn't free it */ - clk_disable(atmel_port->clk); clk_put(atmel_port->clk); return ret; diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c index 211c21797ce0..8b2c619a09f2 100644 --- a/drivers/serial/crisv10.c +++ b/drivers/serial/crisv10.c @@ -34,14 +34,14 @@ static char *serial_version = "$Revision: 1.25 $"; #include #include -#include +#include /* non-arch dependent serial structures are in linux/serial.h */ #include /* while we keep our own stuff (struct e100_serial) in a local .h file */ #include "crisv10.h" #include -#include +#include #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER #ifndef CONFIG_ETRAX_FAST_TIMER diff --git a/drivers/serial/crisv10.h b/drivers/serial/crisv10.h index e3c5c8c3c09b..f36a729280bc 100644 --- a/drivers/serial/crisv10.h +++ b/drivers/serial/crisv10.h @@ -10,7 +10,7 @@ #include #include #include -#include +#include /* Software state per channel */ diff --git a/drivers/serial/ioc3_serial.c b/drivers/serial/ioc3_serial.c index 6dd98f9fb89c..ae3699d77dd0 100644 --- a/drivers/serial/ioc3_serial.c +++ b/drivers/serial/ioc3_serial.c @@ -2149,7 +2149,7 @@ out4: return ret; } -static struct ioc3_submodule ioc3uart_submodule = { +static struct ioc3_submodule ioc3uart_ops = { .name = "IOC3uart", .probe = ioc3uart_probe, .remove = ioc3uart_remove, @@ -2173,7 +2173,7 @@ static int __devinit ioc3uart_init(void) __func__); return ret; } - ret = ioc3_register_submodule(&ioc3uart_submodule); + ret = ioc3_register_submodule(&ioc3uart_ops); if (ret) uart_unregister_driver(&ioc3_uart); return ret; @@ -2181,7 +2181,7 @@ static int __devinit ioc3uart_init(void) static void __devexit ioc3uart_exit(void) { - ioc3_unregister_submodule(&ioc3uart_submodule); + ioc3_unregister_submodule(&ioc3uart_ops); uart_unregister_driver(&ioc3_uart); } diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c index 6117d3db0b66..28c00c3d58f5 100644 --- a/drivers/serial/mpc52xx_uart.c +++ b/drivers/serial/mpc52xx_uart.c @@ -591,8 +591,8 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, /* Update the per-port timeout */ uart_update_timeout(port, new->c_cflag, baud); - /* Do our best to flush TX & RX, so we don't loose anything */ - /* But we don't wait indefinitly ! */ + /* Do our best to flush TX & RX, so we don't lose anything */ + /* But we don't wait indefinitely ! */ j = 5000000; /* Maximum wait */ /* FIXME Can't receive chars since set_termios might be called at early * boot for the console, all stuff is not yet ready to receive at that diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c index 3f489329e8d3..3e5dda8518b7 100644 --- a/drivers/serial/netx-serial.c +++ b/drivers/serial/netx-serial.c @@ -42,8 +42,6 @@ #define SERIAL_NX_MAJOR 204 #define MINOR_START 170 -#ifdef CONFIG_SERIAL_NETX_CONSOLE - enum uart_regs { UART_DR = 0x00, UART_SR = 0x04, @@ -528,6 +526,8 @@ static struct netx_port netx_ports[] = { } }; +#ifdef CONFIG_SERIAL_NETX_CONSOLE + static void netx_console_putchar(struct uart_port *port, int ch) { while (readl(port->membase + UART_FR) & FR_BUSY); diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c index 317d239ab740..29cbb0afef8e 100644 --- a/drivers/serial/s3c2440.c +++ b/drivers/serial/s3c2440.c @@ -177,5 +177,5 @@ module_exit(s3c2440_serial_exit); MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver"); MODULE_AUTHOR("Ben Dooks "); -MODULE_LICENSE("GPLi v2"); +MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:s3c2440-uart"); diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index f0658d2c45b2..165fc010978c 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c @@ -144,9 +144,9 @@ static void put_char(struct uart_port *port, char c) status = sci_in(port, SCxSR); } while (!(status & SCxSR_TDxE(port))); - sci_out(port, SCxTDR, c); sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); + sci_out(port, SCxTDR, c); spin_unlock_irqrestore(&port->lock, flags); } @@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port) } #endif -#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ - defined(__H8300H__) || defined(__H8300S__) +#if defined(__H8300H__) || defined(__H8300S__) static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) { int ch = (port->mapbase - SMR0) >> 3; @@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) #define sci_init_pins_irda NULL #endif -#ifdef SCI_ONLY -#define sci_init_pins_scif NULL -#endif - -#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) { @@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port) return sci_in(port, SCFDR) & SCIF_RFDC_MASK; } #endif -#endif /* SCIF_ONLY || SCI_AND_SCIF */ static inline int sci_txroom(struct uart_port *port) { @@ -485,12 +478,10 @@ static void sci_transmit_chars(struct uart_port *port) return; } -#ifndef SCI_ONLY - if (port->type == PORT_SCIF) - count = scif_txroom(port); - else -#endif + if (port->type == PORT_SCI) count = sci_txroom(port); + else + count = scif_txroom(port); do { unsigned char c; @@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port) } else { ctrl = sci_in(port, SCSCR); -#if !defined(SCI_ONLY) - if (port->type == PORT_SCIF) { + if (port->type != PORT_SCI) { sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); } -#endif ctrl |= SCI_CTRL_FLAGS_TIE; sci_out(port, SCSCR, ctrl); @@ -547,12 +536,10 @@ static inline void sci_receive_chars(struct uart_port *port) return; while (1) { -#if !defined(SCI_ONLY) - if (port->type == PORT_SCIF) - count = scif_rxroom(port); - else -#endif + if (port->type == PORT_SCI) count = sci_rxroom(port); + else + count = scif_rxroom(port); /* Don't copy more bytes than there is room for in the buffer */ count = tty_buffer_request_room(tty, count); @@ -727,7 +714,7 @@ static inline int sci_handle_breaks(struct uart_port *port) #if defined(SCIF_ORER) /* XXX: Handle SCIF overrun error */ - if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { + if (port->type != PORT_SCI && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { sci_out(port, SCLSR, 0); if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { copied++; @@ -810,26 +797,27 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr) static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) { - unsigned short ssr_status, scr_status; - struct uart_port *port = ptr; + unsigned short ssr_status, scr_status; + struct uart_port *port = ptr; + irqreturn_t ret = IRQ_NONE; ssr_status = sci_in(port,SCxSR); scr_status = sci_in(port,SCSCR); /* Tx Interrupt */ - if ((ssr_status & 0x0020) && (scr_status & 0x0080)) - sci_tx_interrupt(irq, ptr); + if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE)) + ret = sci_tx_interrupt(irq, ptr); /* Rx Interrupt */ - if ((ssr_status & 0x0002) && (scr_status & 0x0040)) - sci_rx_interrupt(irq, ptr); + if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE)) + ret = sci_rx_interrupt(irq, ptr); /* Error Interrupt */ - if ((ssr_status & 0x0080) && (scr_status & 0x0400)) - sci_er_interrupt(irq, ptr); + if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE)) + ret = sci_er_interrupt(irq, ptr); /* Break Interrupt */ - if ((ssr_status & 0x0010) && (scr_status & 0x0200)) - sci_br_interrupt(irq, ptr); + if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE)) + ret = sci_br_interrupt(irq, ptr); - return IRQ_HANDLED; + return ret; } #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) @@ -1054,10 +1042,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ -#if !defined(SCI_ONLY) - if (port->type == PORT_SCIF) + if (port->type != PORT_SCI) sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); -#endif smr_val = sci_in(port, SCSMR) & 3; if ((termios->c_cflag & CSIZE) == CS7) @@ -1099,6 +1085,7 @@ static const char *sci_type(struct uart_port *port) case PORT_SCI: return "sci"; case PORT_SCIF: return "scif"; case PORT_IRDA: return "irda"; + case PORT_SCIFA: return "scifa"; } return NULL; @@ -1126,6 +1113,7 @@ static void sci_config_port(struct uart_port *port, int flags) s->init_pins = sci_init_pins_sci; break; case PORT_SCIF: + case PORT_SCIFA: s->init_pins = sci_init_pins_scif; break; case PORT_IRDA: diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 7cd28b226800..9f33b064172e 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -16,7 +16,6 @@ # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ -# define SCI_AND_SCIF #elif defined(CONFIG_CPU_SUBTYPE_SH7705) # define SCIF0 0xA4400000 # define SCIF2 0xA4410000 @@ -30,17 +29,15 @@ * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output */ # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ -# define SCIF_ONLY #define SCIF_ORER 0x0200 /* overrun error bit */ #elif defined(CONFIG_SH_RTS7751R2D) +# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ @@ -53,28 +50,24 @@ # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) -# define SCI_AND_SCIF #elif defined(CONFIG_CPU_SUBTYPE_SH7760) # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define PACR 0xa4050100 # define PBCR 0xa4050102 # define SCSCR_INIT(port) 0x3B -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7343) # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7722) # define PADR 0xA4050120 # define PSDR 0xA405013e @@ -82,7 +75,6 @@ # define PSCR 0xA405011E # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7366) # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ # define SCSPTR0 SCPDR0 @@ -97,12 +89,10 @@ # define SCSPTR5 0xa4050128 # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) # define SCIF_BASE_ADDR 0x01030000 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR @@ -111,14 +101,11 @@ # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ -# define SCI_ONLY # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) #elif defined(CONFIG_H8S2678) # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ -# define SCI_ONLY # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) #elif defined(CONFIG_CPU_SUBTYPE_SH7763) # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ @@ -126,20 +113,17 @@ # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7770) # define SCSPTR0 0xff923020 /* 16 bit SCIF */ # define SCSPTR1 0xff924020 /* 16 bit SCIF */ # define SCSPTR2 0xff925020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7780) # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7785) # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ @@ -149,7 +133,6 @@ # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ # define SCIF_OPER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ defined(CONFIG_CPU_SUBTYPE_SH7206) || \ defined(CONFIG_CPU_SUBTYPE_SH7263) @@ -158,14 +141,12 @@ # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7619) # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SHX3) # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ @@ -173,7 +154,6 @@ # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -# define SCIF_ONLY #else # error CPU subtype not defined #endif @@ -186,6 +166,7 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ defined(CONFIG_CPU_SUBTYPE_SH7091) || \ defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ + defined(CONFIG_CPU_SUBTYPE_SH7722) || \ defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ defined(CONFIG_CPU_SUBTYPE_SH7751) || \ defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ @@ -244,55 +225,28 @@ # define SCIF_TXROOM_MAX 16 #endif -#if defined(SCI_ONLY) -# define SCxSR_TEND(port) SCI_TEND -# define SCxSR_ERRORS(port) SCI_ERRORS -# define SCxSR_RDxF(port) SCI_RDRF -# define SCxSR_TDxE(port) SCI_TDRE -# define SCxSR_ORER(port) SCI_ORER -# define SCxSR_FER(port) SCI_FER -# define SCxSR_PER(port) SCI_PER -# define SCxSR_BRK(port) 0x00 -# define SCxSR_RDxF_CLEAR(port) 0xbc -# define SCxSR_ERROR_CLEAR(port) 0xc4 -# define SCxSR_TDxE_CLEAR(port) 0x78 -# define SCxSR_BREAK_CLEAR(port) 0xc4 -#elif defined(SCIF_ONLY) -# define SCxSR_TEND(port) SCIF_TEND -# define SCxSR_ERRORS(port) SCIF_ERRORS -# define SCxSR_RDxF(port) SCIF_RDF -# define SCxSR_TDxE(port) SCIF_TDFE +#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) +#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) +#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) +#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) +#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) +#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) +#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) + #if defined(CONFIG_CPU_SUBTYPE_SH7705) -# define SCxSR_ORER(port) SCIF_ORER +# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) #else -# define SCxSR_ORER(port) 0x0000 +# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) #endif -# define SCxSR_FER(port) SCIF_FER -# define SCxSR_PER(port) SCIF_PER -# define SCxSR_BRK(port) SCIF_BRK + #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) -# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) -# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) -# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) -# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) -#else -/* SH7705 can also use this, clearing is same between 7705 and 7709 */ -# define SCxSR_RDxF_CLEAR(port) 0x00fc -# define SCxSR_ERROR_CLEAR(port) 0x0073 -# define SCxSR_TDxE_CLEAR(port) 0x00df -# define SCxSR_BREAK_CLEAR(port) 0x00e3 -#endif +# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) +# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) +# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) +# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) #else -# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) -# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) -# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) -# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) -# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) -# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) -# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) -# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) @@ -335,18 +289,18 @@ #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ static inline unsigned int sci_##name##_in(struct uart_port *port) \ { \ - if (port->type == PORT_SCI) { \ - SCI_IN(sci_size, sci_offset) \ - } else { \ - SCI_IN(scif_size, scif_offset); \ + if (port->type == PORT_SCIF) { \ + SCI_IN(scif_size, scif_offset) \ + } else { /* PORT_SCI or PORT_SCIFA */ \ + SCI_IN(sci_size, sci_offset); \ } \ } \ static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ { \ - if (port->type == PORT_SCI) { \ - SCI_OUT(sci_size, sci_offset, value) \ - } else { \ - SCI_OUT(scif_size, scif_offset, value); \ + if (port->type == PORT_SCIF) { \ + SCI_OUT(scif_size, scif_offset, value) \ + } else { /* PORT_SCI or PORT_SCIFA */ \ + SCI_OUT(sci_size, sci_offset, value); \ } \ } @@ -574,18 +528,20 @@ static inline int sci_rxd_in(struct uart_port *port) defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ - defined(CONFIG_CPU_SUBTYPE_SH7091) || \ - defined(CONFIG_CPU_SUBTYPE_SH4_202) + defined(CONFIG_CPU_SUBTYPE_SH7091) static inline int sci_rxd_in(struct uart_port *port) { -#ifndef SCIF_ONLY if (port->mapbase == 0xffe00000) return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ -#endif -#ifndef SCI_ONLY if (port->mapbase == 0xffe80000) return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ -#endif + return 1; +} +#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) +static inline int sci_rxd_in(struct uart_port *port) +{ + if (port->mapbase == 0xffe80000) + return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ return 1; } #elif defined(CONFIG_CPU_SUBTYPE_SH7760) @@ -651,7 +607,7 @@ static inline int sci_rxd_in(struct uart_port *port) #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) static inline int sci_rxd_in(struct uart_port *port) { - return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ + return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ } #elif defined(__H8300H__) || defined(__H8300S__) static inline int sci_rxd_in(struct uart_port *port) diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c index 6a3f8fb0c9dd..3317148a4b93 100644 --- a/drivers/serial/uartlite.c +++ b/drivers/serial/uartlite.c @@ -286,8 +286,8 @@ static void ulite_release_port(struct uart_port *port) static int ulite_request_port(struct uart_port *port) { - pr_debug("ulite console: port=%p; port->mapbase=%x\n", - port, port->mapbase); + pr_debug("ulite console: port=%p; port->mapbase=%llx\n", + port, (unsigned long long) port->mapbase); if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { dev_err(port->dev, "Memory region busy\n"); diff --git a/drivers/sh/maple/maple.c b/drivers/sh/maple/maple.c index d1812d32f47d..63f0de29aa14 100644 --- a/drivers/sh/maple/maple.c +++ b/drivers/sh/maple/maple.c @@ -827,7 +827,7 @@ static int __init maple_bus_init(void) maple_queue_cache = kmem_cache_create("maple_queue_cache", 0x400, 0, - SLAB_POISON|SLAB_HWCACHE_ALIGN, NULL); + SLAB_HWCACHE_ALIGN, NULL); if (!maple_queue_cache) goto cleanup_bothirqs; diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 02f9320f3efc..8abae4ad0fa5 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -766,6 +766,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev) /* Initialize the hardware */ clk_enable(clk); spi_writel(as, CR, SPI_BIT(SWRST)); + spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); spi_writel(as, CR, SPI_BIT(SPIEN)); @@ -782,6 +783,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev) out_reset_hw: spi_writel(as, CR, SPI_BIT(SWRST)); + spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ clk_disable(clk); free_irq(irq, master); out_unmap_regs: @@ -805,6 +807,7 @@ static int __exit atmel_spi_remove(struct platform_device *pdev) spin_lock_irq(&as->lock); as->stopping = 1; spi_writel(as, CR, SPI_BIT(SWRST)); + spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ spi_readl(as, SR); spin_unlock_irq(&as->lock); diff --git a/drivers/spi/au1550_spi.c b/drivers/spi/au1550_spi.c index 87b73e0169c5..b02f25c702fd 100644 --- a/drivers/spi/au1550_spi.c +++ b/drivers/spi/au1550_spi.c @@ -369,10 +369,23 @@ static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) dma_rx_addr = t->rx_dma; /* - * check if buffers are already dma mapped, map them otherwise + * check if buffers are already dma mapped, map them otherwise: + * - first map the TX buffer, so cache data gets written to memory + * - then map the RX buffer, so that cache entries (with + * soon-to-be-stale data) get removed * use rx buffer in place of tx if tx buffer was not provided * use temp rx buffer (preallocated or realloc to fit) for rx dma */ + if (t->tx_buf) { + if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ + dma_tx_addr = dma_map_single(hw->dev, + (void *)t->tx_buf, + t->len, DMA_TO_DEVICE); + if (dma_mapping_error(hw->dev, dma_tx_addr)) + dev_err(hw->dev, "tx dma map error\n"); + } + } + if (t->rx_buf) { if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ dma_rx_addr = dma_map_single(hw->dev, @@ -396,15 +409,8 @@ static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) dma_sync_single_for_device(hw->dev, dma_rx_addr, t->len, DMA_FROM_DEVICE); } - if (t->tx_buf) { - if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ - dma_tx_addr = dma_map_single(hw->dev, - (void *)t->tx_buf, - t->len, DMA_TO_DEVICE); - if (dma_mapping_error(hw->dev, dma_tx_addr)) - dev_err(hw->dev, "tx dma map error\n"); - } - } else { + + if (!t->tx_buf) { dma_sync_single_for_device(hw->dev, dma_rx_addr, t->len, DMA_BIDIRECTIONAL); hw->tx = hw->rx; diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c index 0debe11b67b4..3b97803e1d11 100644 --- a/drivers/spi/mpc52xx_psc_spi.c +++ b/drivers/spi/mpc52xx_psc_spi.c @@ -142,6 +142,7 @@ static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, unsigned rfalarm; unsigned send_at_once = MPC52xx_PSC_BUFSIZE; unsigned recv_at_once; + int last_block = 0; if (!t->tx_buf && !t->rx_buf && t->len) return -EINVAL; @@ -151,15 +152,17 @@ static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, while (rb < t->len) { if (t->len - rb > MPC52xx_PSC_BUFSIZE) { rfalarm = MPC52xx_PSC_RFALARM; + last_block = 0; } else { send_at_once = t->len - sb; rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb); + last_block = 1; } dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once); for (; send_at_once; sb++, send_at_once--) { /* set EOF flag before the last word is sent */ - if (send_at_once == 1) + if (send_at_once == 1 && last_block) out_8(&psc->ircr2, 0x01); if (tx_buf) diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index dae87b1a4c6e..cf12f2d84be2 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c @@ -352,21 +352,21 @@ static int map_dma_buffers(struct driver_data *drv_data) } else drv_data->tx_map_len = drv_data->len; - /* Stream map the rx buffer */ - drv_data->rx_dma = dma_map_single(dev, drv_data->rx, - drv_data->rx_map_len, - DMA_FROM_DEVICE); - if (dma_mapping_error(dev, drv_data->rx_dma)) - return 0; - - /* Stream map the tx buffer */ + /* Stream map the tx buffer. Always do DMA_TO_DEVICE first + * so we flush the cache *before* invalidating it, in case + * the tx and rx buffers overlap. + */ drv_data->tx_dma = dma_map_single(dev, drv_data->tx, - drv_data->tx_map_len, - DMA_TO_DEVICE); + drv_data->tx_map_len, DMA_TO_DEVICE); + if (dma_mapping_error(dev, drv_data->tx_dma)) + return 0; - if (dma_mapping_error(dev, drv_data->tx_dma)) { - dma_unmap_single(dev, drv_data->rx_dma, + /* Stream map the rx buffer */ + drv_data->rx_dma = dma_map_single(dev, drv_data->rx, drv_data->rx_map_len, DMA_FROM_DEVICE); + if (dma_mapping_error(dev, drv_data->rx_dma)) { + dma_unmap_single(dev, drv_data->tx_dma, + drv_data->tx_map_len, DMA_TO_DEVICE); return 0; } diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c index 61ba147e384d..269a55ec52ef 100644 --- a/drivers/spi/spi_imx.c +++ b/drivers/spi/spi_imx.c @@ -506,20 +506,6 @@ static int map_dma_buffers(struct driver_data *drv_data) if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) return -1; - /* NULL rx means write-only transfer and no map needed - since rx DMA will not be used */ - if (drv_data->rx) { - buf = drv_data->rx; - drv_data->rx_dma = dma_map_single( - dev, - buf, - drv_data->len, - DMA_FROM_DEVICE); - if (dma_mapping_error(dev, drv_data->rx_dma)) - return -1; - drv_data->rx_dma_needs_unmap = 1; - } - if (drv_data->tx == NULL) { /* Read only message --> use drv_data->dummy_dma_buf for dummy writes to achive reads */ @@ -533,18 +519,31 @@ static int map_dma_buffers(struct driver_data *drv_data) buf, drv_data->tx_map_len, DMA_TO_DEVICE); - if (dma_mapping_error(dev, drv_data->tx_dma)) { - if (drv_data->rx_dma) { - dma_unmap_single(dev, - drv_data->rx_dma, - drv_data->len, - DMA_FROM_DEVICE); - drv_data->rx_dma_needs_unmap = 0; - } + if (dma_mapping_error(dev, drv_data->tx_dma)) return -1; - } drv_data->tx_dma_needs_unmap = 1; + /* NULL rx means write-only transfer and no map needed + * since rx DMA will not be used */ + if (drv_data->rx) { + buf = drv_data->rx; + drv_data->rx_dma = dma_map_single(dev, + buf, + drv_data->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(dev, drv_data->rx_dma)) { + if (drv_data->tx_dma) { + dma_unmap_single(dev, + drv_data->tx_dma, + drv_data->tx_map_len, + DMA_TO_DEVICE); + drv_data->tx_dma_needs_unmap = 0; + } + return -1; + } + drv_data->rx_dma_needs_unmap = 1; + } + return 0; } @@ -1457,7 +1456,7 @@ static int __init spi_imx_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct spi_imx_master *platform_info; struct spi_master *master; - struct driver_data *drv_data = NULL; + struct driver_data *drv_data; struct resource *res; int irq, status = 0; @@ -1468,14 +1467,6 @@ static int __init spi_imx_probe(struct platform_device *pdev) goto err_no_pdata; } - drv_data->clk = clk_get(&pdev->dev, "perclk2"); - if (IS_ERR(drv_data->clk)) { - dev_err(&pdev->dev, "probe - cannot get get\n"); - status = PTR_ERR(drv_data->clk); - goto err_no_clk; - } - clk_enable(drv_data->clk); - /* Allocate master with space for drv_data */ master = spi_alloc_master(dev, sizeof(struct driver_data)); if (!master) { @@ -1496,6 +1487,14 @@ static int __init spi_imx_probe(struct platform_device *pdev) drv_data->dummy_dma_buf = SPI_DUMMY_u32; + drv_data->clk = clk_get(&pdev->dev, "perclk2"); + if (IS_ERR(drv_data->clk)) { + dev_err(&pdev->dev, "probe - cannot get clock\n"); + status = PTR_ERR(drv_data->clk); + goto err_no_clk; + } + clk_enable(drv_data->clk); + /* Find and map resources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -1631,12 +1630,13 @@ err_no_iomap: kfree(drv_data->ioarea); err_no_iores: - spi_master_put(master); - -err_no_pdata: clk_disable(drv_data->clk); clk_put(drv_data->clk); + err_no_clk: + spi_master_put(master); + +err_no_pdata: err_no_mem: return status; } diff --git a/drivers/spi/spi_s3c24xx_gpio.c b/drivers/spi/spi_s3c24xx_gpio.c index cc1f647f579b..f2447a5476bb 100644 --- a/drivers/spi/spi_s3c24xx_gpio.c +++ b/drivers/spi/spi_s3c24xx_gpio.c @@ -34,7 +34,7 @@ struct s3c2410_spigpio { static inline struct s3c2410_spigpio *spidev_to_sg(struct spi_device *spi) { - return spi->controller_data; + return spi_master_get_devdata(spi->master); } static inline void setsck(struct spi_device *dev, int on) @@ -118,6 +118,7 @@ static int s3c2410_spigpio_probe(struct platform_device *dev) /* setup spi bitbang adaptor */ sp->bitbang.master = spi_master_get(master); sp->bitbang.master->bus_num = info->bus_num; + sp->bitbang.master->num_chipselect = info->num_chipselect; sp->bitbang.chipselect = s3c2410_spigpio_chipselect; sp->bitbang.txrx_word[SPI_MODE_0] = s3c2410_spigpio_txrx_mode0; diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 89a43755a453..5d869c4d3eb2 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -597,7 +597,9 @@ static int spidev_probe(struct spi_device *spi) } mutex_unlock(&device_list_lock); - if (status != 0) + if (status == 0) + spi_set_drvdata(spi, spidev); + else kfree(spidev); return status; diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig index 307b1f62d949..b1b947edcf01 100644 --- a/drivers/ssb/Kconfig +++ b/drivers/ssb/Kconfig @@ -1,10 +1,11 @@ -menu "Sonics Silicon Backplane" - config SSB_POSSIBLE bool depends on HAS_IOMEM && HAS_DMA default y +menu "Sonics Silicon Backplane" + depends on SSB_POSSIBLE + config SSB tristate "Sonics Silicon Backplane support" depends on SSB_POSSIBLE diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index e1654f59eb70..5d457c96bd7e 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -21,8 +21,26 @@ menuconfig STAGING If in doubt, say N here. + if STAGING +config STAGING_EXCLUDE_BUILD + bool "Exclude Staging drivers from being built" if STAGING + default y + ---help--- + Are you sure you really want to build the staging drivers? + They taint your kernel, don't live up to the normal Linux + kernel quality standards, are a bit crufty around the edges, + and might go off and kick your dog when you aren't paying + attention. + + Say N here to be able to select and build the Staging drivers. + This option is primarily here to prevent them from being built + when selecting 'make allyesconfg' and 'make allmodconfig' so + don't be all that put off, your dog will be just fine. + +if !STAGING_EXCLUDE_BUILD + source "drivers/staging/et131x/Kconfig" source "drivers/staging/slicoss/Kconfig" @@ -45,4 +63,5 @@ source "drivers/staging/at76_usb/Kconfig" source "drivers/staging/poch/Kconfig" +endif # !STAGING_EXCLUDE_BUILD endif # STAGING diff --git a/drivers/staging/echo/echo.c b/drivers/staging/echo/echo.c index b8f2c5e9dee5..fd4007e329e7 100644 --- a/drivers/staging/echo/echo.c +++ b/drivers/staging/echo/echo.c @@ -106,7 +106,6 @@ #include /* We're doing kernel work */ #include -#include #include #include "bit_operations.h" diff --git a/drivers/staging/me4000/me4000.c b/drivers/staging/me4000/me4000.c index 0b33773bb4f6..0394e2709278 100644 --- a/drivers/staging/me4000/me4000.c +++ b/drivers/staging/me4000/me4000.c @@ -39,7 +39,6 @@ #include #include #include -#include /* Include-File for the Meilhaus ME-4000 I/O board */ #include "me4000.h" @@ -1633,9 +1632,6 @@ static int me4000_release(struct inode *inode_p, struct file *file_p) free_irq(ext_int_context->irq, ext_int_context); - /* Delete the fasync structure and free memory */ - me4000_ext_int_fasync(0, file_p, 0); - /* Mark as unused */ ext_int_context->in_use = 0; } else { diff --git a/drivers/staging/usbip/Kconfig b/drivers/staging/usbip/Kconfig index 7426235ccc44..217fb7e62c2f 100644 --- a/drivers/staging/usbip/Kconfig +++ b/drivers/staging/usbip/Kconfig @@ -1,6 +1,6 @@ config USB_IP_COMMON tristate "USB IP support (EXPERIMENTAL)" - depends on USB && EXPERIMENTAL + depends on USB && NET && EXPERIMENTAL default N ---help--- This enables pushing USB packets over IP to allow remote diff --git a/drivers/telephony/ixj.c b/drivers/telephony/ixj.c index 41b6530b8f25..a913efc69669 100644 --- a/drivers/telephony/ixj.c +++ b/drivers/telephony/ixj.c @@ -2328,7 +2328,6 @@ static int ixj_release(struct inode *inode, struct file *file_p) j->rec_codec = j->play_codec = 0; j->rec_frame_size = j->play_frame_size = 0; j->flags.cidsent = j->flags.cidring = 0; - ixj_fasync(-1, file_p, 0); /* remove from list of async notification */ if(j->cardtype == QTI_LINEJACK && !j->readers && !j->writers) { ixj_set_port(j, PORT_PSTN); diff --git a/drivers/telephony/phonedev.c b/drivers/telephony/phonedev.c index 37caf4d69037..b52cc830c0b4 100644 --- a/drivers/telephony/phonedev.c +++ b/drivers/telephony/phonedev.c @@ -8,7 +8,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * Author: Alan Cox, + * Author: Alan Cox, * * Fixes: Mar 01 2000 Thomas Sparr, * phone_register_device now works with unit!=PHONE_UNIT_ANY diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c index f9b4647255aa..2d2440cd57a9 100644 --- a/drivers/uio/uio.c +++ b/drivers/uio/uio.c @@ -367,9 +367,6 @@ static int uio_release(struct inode *inode, struct file *filep) ret = idev->info->release(idev->info, inode); module_put(idev->owner); - - if (filep->f_flags & FASYNC) - ret = uio_fasync(-1, filep, 0); kfree(listener); return ret; } diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c index 20104443081a..d50a99f70aee 100644 --- a/drivers/usb/class/cdc-acm.c +++ b/drivers/usb/class/cdc-acm.c @@ -158,16 +158,12 @@ static int acm_wb_is_avail(struct acm *acm) } /* - * Finish write. + * Finish write. Caller must hold acm->write_lock */ static void acm_write_done(struct acm *acm, struct acm_wb *wb) { - unsigned long flags; - - spin_lock_irqsave(&acm->write_lock, flags); wb->use = 0; acm->transmitting--; - spin_unlock_irqrestore(&acm->write_lock, flags); } /* @@ -482,6 +478,7 @@ static void acm_write_bulk(struct urb *urb) { struct acm_wb *wb = urb->context; struct acm *acm = wb->instance; + unsigned long flags; if (verbose || urb->status || (urb->actual_length != urb->transfer_buffer_length)) @@ -490,7 +487,9 @@ static void acm_write_bulk(struct urb *urb) urb->transfer_buffer_length, urb->status); + spin_lock_irqsave(&acm->write_lock, flags); acm_write_done(acm, wb); + spin_unlock_irqrestore(&acm->write_lock, flags); if (ACM_READY(acm)) schedule_work(&acm->work); else diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c index 543811f6e6e8..43a863c5cc43 100644 --- a/drivers/usb/class/usbtmc.c +++ b/drivers/usb/class/usbtmc.c @@ -51,6 +51,7 @@ static struct usb_device_id usbtmc_devices[] = { { USB_INTERFACE_INFO(USB_CLASS_APP_SPEC, 3, 0), }, { 0, } /* terminating entry */ }; +MODULE_DEVICE_TABLE(usb, usbtmc_devices); /* * This structure is the capabilities for the device @@ -133,7 +134,7 @@ static int usbtmc_release(struct inode *inode, struct file *file) static int usbtmc_ioctl_abort_bulk_in(struct usbtmc_device_data *data) { - char *buffer; + u8 *buffer; struct device *dev; int rv; int n; diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c index 3d7793d93031..8c081308b0e2 100644 --- a/drivers/usb/core/driver.c +++ b/drivers/usb/core/driver.c @@ -279,7 +279,9 @@ static int usb_unbind_interface(struct device *dev) * altsetting means creating new endpoint device entries). * When either of these happens, defer the Set-Interface. */ - if (!error && intf->dev.power.status == DPM_ON) + if (intf->cur_altsetting->desc.bAlternateSetting == 0) + ; /* Already in altsetting 0 so skip Set-Interface */ + else if (!error && intf->dev.power.status == DPM_ON) usb_set_interface(udev, intf->altsetting[0]. desc.bInterfaceNumber, 0); else diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c index fc9018e72a09..e1b42626d04d 100644 --- a/drivers/usb/core/hcd.c +++ b/drivers/usb/core/hcd.c @@ -106,6 +106,9 @@ static DEFINE_SPINLOCK(hcd_root_hub_lock); /* used when updating an endpoint's URB list */ static DEFINE_SPINLOCK(hcd_urb_list_lock); +/* used to protect against unlinking URBs after the device is gone */ +static DEFINE_SPINLOCK(hcd_urb_unlink_lock); + /* wait queue for synchronous unlinks */ DECLARE_WAIT_QUEUE_HEAD(usb_kill_urb_queue); @@ -1376,10 +1379,25 @@ static int unlink1(struct usb_hcd *hcd, struct urb *urb, int status) int usb_hcd_unlink_urb (struct urb *urb, int status) { struct usb_hcd *hcd; - int retval; + int retval = -EIDRM; + unsigned long flags; - hcd = bus_to_hcd(urb->dev->bus); - retval = unlink1(hcd, urb, status); + /* Prevent the device and bus from going away while + * the unlink is carried out. If they are already gone + * then urb->use_count must be 0, since disconnected + * devices can't have any active URBs. + */ + spin_lock_irqsave(&hcd_urb_unlink_lock, flags); + if (atomic_read(&urb->use_count) > 0) { + retval = 0; + usb_get_dev(urb->dev); + } + spin_unlock_irqrestore(&hcd_urb_unlink_lock, flags); + if (retval == 0) { + hcd = bus_to_hcd(urb->dev->bus); + retval = unlink1(hcd, urb, status); + usb_put_dev(urb->dev); + } if (retval == 0) retval = -EINPROGRESS; @@ -1528,6 +1546,17 @@ void usb_hcd_disable_endpoint(struct usb_device *udev, hcd->driver->endpoint_disable(hcd, ep); } +/* Protect against drivers that try to unlink URBs after the device + * is gone, by waiting until all unlinks for @udev are finished. + * Since we don't currently track URBs by device, simply wait until + * nothing is running in the locked region of usb_hcd_unlink_urb(). + */ +void usb_hcd_synchronize_unlinks(struct usb_device *udev) +{ + spin_lock_irq(&hcd_urb_unlink_lock); + spin_unlock_irq(&hcd_urb_unlink_lock); +} + /*-------------------------------------------------------------------------*/ /* called in any context */ diff --git a/drivers/usb/core/hcd.h b/drivers/usb/core/hcd.h index 2dcde61c465e..9465e70f4dd0 100644 --- a/drivers/usb/core/hcd.h +++ b/drivers/usb/core/hcd.h @@ -232,6 +232,7 @@ extern void usb_hcd_flush_endpoint(struct usb_device *udev, struct usb_host_endpoint *ep); extern void usb_hcd_disable_endpoint(struct usb_device *udev, struct usb_host_endpoint *ep); +extern void usb_hcd_synchronize_unlinks(struct usb_device *udev); extern int usb_hcd_get_frame_number(struct usb_device *udev); extern struct usb_hcd *usb_create_hcd(const struct hc_driver *driver, diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 9b3f16bd12cb..b19cbfcd51da 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -659,6 +659,9 @@ static void hub_activate(struct usb_hub *hub, enum hub_activation_type type) PREPARE_DELAYED_WORK(&hub->init_work, hub_init_func2); schedule_delayed_work(&hub->init_work, msecs_to_jiffies(delay)); + + /* Suppress autosuspend until init is done */ + to_usb_interface(hub->intfdev)->pm_usage_cnt = 1; return; /* Continues at init2: below */ } else { hub_power_on(hub, true); @@ -1429,6 +1432,7 @@ void usb_disconnect(struct usb_device **pdev) */ dev_dbg (&udev->dev, "unregistering device\n"); usb_disable_device(udev, 0); + usb_hcd_synchronize_unlinks(udev); usb_unlock_device(udev); diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c index 887738577b28..6d1048faf08e 100644 --- a/drivers/usb/core/message.c +++ b/drivers/usb/core/message.c @@ -1091,6 +1091,7 @@ void usb_disable_device(struct usb_device *dev, int skip_ep0) continue; dev_dbg(&dev->dev, "unregistering interface %s\n", dev_name(&interface->dev)); + interface->unregistering = 1; usb_remove_sysfs_intf_files(interface); device_del(&interface->dev); } diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c index f66fba11fbd5..4fb65fdc9dc3 100644 --- a/drivers/usb/core/sysfs.c +++ b/drivers/usb/core/sysfs.c @@ -840,7 +840,7 @@ int usb_create_sysfs_intf_files(struct usb_interface *intf) struct usb_host_interface *alt = intf->cur_altsetting; int retval; - if (intf->sysfs_files_created) + if (intf->sysfs_files_created || intf->unregistering) return 0; /* The interface string may be present in some altsettings diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c index f2638009a464..1f68af9db3f7 100644 --- a/drivers/usb/core/urb.c +++ b/drivers/usb/core/urb.c @@ -85,8 +85,8 @@ EXPORT_SYMBOL_GPL(usb_alloc_urb); * Must be called when a user of a urb is finished with it. When the last user * of the urb calls this function, the memory of the urb is freed. * - * Note: The transfer buffer associated with the urb is not freed, that must be - * done elsewhere. + * Note: The transfer buffer associated with the urb is not freed unless the + * URB_FREE_BUFFER transfer flag is set. */ void usb_free_urb(struct urb *urb) { @@ -474,6 +474,12 @@ EXPORT_SYMBOL_GPL(usb_submit_urb); * indicating that the request has been canceled (rather than any other * code). * + * Drivers should not call this routine or related routines, such as + * usb_kill_urb() or usb_unlink_anchored_urbs(), after their disconnect + * method has returned. The disconnect function should synchronize with + * a driver's I/O routines to insure that all URB-related activity has + * completed before it returns. + * * This request is always asynchronous. Success is indicated by * returning -EINPROGRESS, at which time the URB will probably not yet * have been given back to the device driver. When it is eventually @@ -550,6 +556,9 @@ EXPORT_SYMBOL_GPL(usb_unlink_urb); * This routine may not be used in an interrupt context (such as a bottom * half or a completion handler), or when holding a spinlock, or in other * situations where the caller can't schedule(). + * + * This routine should not be called by a driver after its disconnect + * method has returned. */ void usb_kill_urb(struct urb *urb) { @@ -588,6 +597,9 @@ EXPORT_SYMBOL_GPL(usb_kill_urb); * This routine may not be used in an interrupt context (such as a bottom * half or a completion handler), or when holding a spinlock, or in other * situations where the caller can't schedule(). + * + * This routine should not be called by a driver after its disconnect + * method has returned. */ void usb_poison_urb(struct urb *urb) { @@ -622,6 +634,9 @@ EXPORT_SYMBOL_GPL(usb_unpoison_urb); * * this allows all outstanding URBs to be killed starting * from the back of the queue + * + * This routine should not be called by a driver after its disconnect + * method has returned. */ void usb_kill_anchored_urbs(struct usb_anchor *anchor) { @@ -651,6 +666,9 @@ EXPORT_SYMBOL_GPL(usb_kill_anchored_urbs); * this allows all outstanding URBs to be poisoned starting * from the back of the queue. Newly added URBs will also be * poisoned + * + * This routine should not be called by a driver after its disconnect + * method has returned. */ void usb_poison_anchored_urbs(struct usb_anchor *anchor) { @@ -672,6 +690,7 @@ void usb_poison_anchored_urbs(struct usb_anchor *anchor) spin_unlock_irq(&anchor->lock); } EXPORT_SYMBOL_GPL(usb_poison_anchored_urbs); + /** * usb_unlink_anchored_urbs - asynchronously cancel transfer requests en masse * @anchor: anchor the requests are bound to @@ -680,6 +699,9 @@ EXPORT_SYMBOL_GPL(usb_poison_anchored_urbs); * from the back of the queue. This function is asynchronous. * The unlinking is just tiggered. It may happen after this * function has returned. + * + * This routine should not be called by a driver after its disconnect + * method has returned. */ void usb_unlink_anchored_urbs(struct usb_anchor *anchor) { diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c index 5ee1590b8e9c..c1d34df0b157 100644 --- a/drivers/usb/gadget/f_acm.c +++ b/drivers/usb/gadget/f_acm.c @@ -463,7 +463,11 @@ static int acm_cdc_notify(struct f_acm *acm, u8 type, u16 value, notify->wLength = cpu_to_le16(length); memcpy(buf, data, length); + /* ep_queue() can complete immediately if it fills the fifo... */ + spin_unlock(&acm->lock); status = usb_ep_queue(ep, req, GFP_ATOMIC); + spin_lock(&acm->lock); + if (status < 0) { ERROR(acm->port.func.config->cdev, "acm ttyGS%d can't notify serial state, %d\n", diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c index 659b3d9671c4..3a8bb53fc473 100644 --- a/drivers/usb/gadget/f_rndis.c +++ b/drivers/usb/gadget/f_rndis.c @@ -172,7 +172,6 @@ static struct usb_interface_descriptor rndis_data_intf __initdata = { .bDescriptorType = USB_DT_INTERFACE, /* .bInterfaceNumber = DYNAMIC */ - .bAlternateSetting = 1, .bNumEndpoints = 2, .bInterfaceClass = USB_CLASS_CDC_DATA, .bInterfaceSubClass = 0, @@ -303,7 +302,7 @@ static void rndis_response_available(void *_rndis) __le32 *data = req->buf; int status; - if (atomic_inc_return(&rndis->notify_count)) + if (atomic_inc_return(&rndis->notify_count) != 1) return; /* Send RNDIS RESPONSE_AVAILABLE notification; a @@ -652,6 +651,8 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f) fs_in_desc.bEndpointAddress; hs_out_desc.bEndpointAddress = fs_out_desc.bEndpointAddress; + hs_notify_desc.bEndpointAddress = + fs_notify_desc.bEndpointAddress; /* copy descriptors, and track endpoint copies */ f->hs_descriptors = usb_copy_descriptors(eth_hs_function); @@ -663,6 +664,8 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f) f->hs_descriptors, &hs_in_desc); rndis->hs.out = usb_find_endpoint(eth_hs_function, f->hs_descriptors, &hs_out_desc); + rndis->hs.notify = usb_find_endpoint(eth_hs_function, + f->hs_descriptors, &hs_notify_desc); } rndis->port.open = rndis_open; diff --git a/drivers/usb/gadget/fsl_qe_udc.c b/drivers/usb/gadget/fsl_qe_udc.c index 1fe8b44787b3..b3408ff39fba 100644 --- a/drivers/usb/gadget/fsl_qe_udc.c +++ b/drivers/usb/gadget/fsl_qe_udc.c @@ -2363,6 +2363,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) nuke(loop_ep, -ESHUTDOWN); spin_unlock_irqrestore(&udc_controller->lock, flags); + /* report disconnect; the controller is already quiesced */ + driver->disconnect(&udc_controller->gadget); + /* unbind gadget and unhook driver. */ driver->unbind(&udc_controller->gadget); udc_controller->gadget.dev.driver = NULL; diff --git a/drivers/usb/gadget/fsl_usb2_udc.c b/drivers/usb/gadget/fsl_usb2_udc.c index 091bb55c9aa7..f3c6703cffda 100644 --- a/drivers/usb/gadget/fsl_usb2_udc.c +++ b/drivers/usb/gadget/fsl_usb2_udc.c @@ -1836,6 +1836,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) nuke(loop_ep, -ESHUTDOWN); spin_unlock_irqrestore(&udc_controller->lock, flags); + /* report disconnect; the controller is already quiesced */ + driver->disconnect(&udc_controller->gadget); + /* unbind gadget and unhook driver. */ driver->unbind(&udc_controller->gadget); udc_controller->gadget.dev.driver = NULL; diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c index f4585d3e90d7..eeb26c0f88e5 100644 --- a/drivers/usb/gadget/inode.c +++ b/drivers/usb/gadget/inode.c @@ -1251,7 +1251,6 @@ dev_release (struct inode *inode, struct file *fd) * alternatively, all host requests will time out. */ - fasync_helper (-1, fd, 0, &dev->fasync); kfree (dev->buf); dev->buf = NULL; put_dev (dev); diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index da6e93c201d2..2dbc0db0b46c 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -141,7 +141,11 @@ static int is_vbus_present(void) if (mach->gpio_vbus) { int value = gpio_get_value(mach->gpio_vbus); - return mach->gpio_vbus_inverted ? !value : value; + + if (mach->gpio_vbus_inverted) + return !value; + else + return !!value; } if (mach->udc_is_connected) return mach->udc_is_connected(); @@ -982,7 +986,7 @@ static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) struct pxa25x_udc *udc; udc = container_of(_gadget, struct pxa25x_udc, gadget); - udc->vbus = (is_active != 0); + udc->vbus = is_active; DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); pullup(udc); return 0; @@ -1399,12 +1403,8 @@ lubbock_vbus_irq(int irq, void *_dev) static irqreturn_t udc_vbus_irq(int irq, void *_dev) { struct pxa25x_udc *dev = _dev; - int vbus = gpio_get_value(dev->mach->gpio_vbus); - if (dev->mach->gpio_vbus_inverted) - vbus = !vbus; - - pxa25x_udc_vbus_session(&dev->gadget, vbus); + pxa25x_udc_vbus_session(&dev->gadget, is_vbus_present()); return IRQ_HANDLED; } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 56f592dc0b36..f3a75a929e0a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -110,29 +110,18 @@ config USB_ISP116X_HCD config USB_ISP1760_HCD tristate "ISP 1760 HCD support" - depends on USB && EXPERIMENTAL + depends on USB && EXPERIMENTAL && (PCI || PPC_OF) ---help--- The ISP1760 chip is a USB 2.0 host controller. This driver does not support isochronous transfers or OTG. + This USB controller is usually attached to a non-DMA-Master + capable bus. NXP's eval kit brings this chip on PCI card + where the chip itself is behind a PLB to simulate such + a bus. To compile this driver as a module, choose M here: the - module will be called isp1760-hcd. - -config USB_ISP1760_PCI - bool "Support for the PCI bus" - depends on USB_ISP1760_HCD && PCI - ---help--- - Enables support for the device present on the PCI bus. - This should only be required if you happen to have the eval kit from - NXP and you are going to test it. - -config USB_ISP1760_OF - bool "Support for the OF platform bus" - depends on USB_ISP1760_HCD && PPC_OF - ---help--- - Enables support for the device present on the PowerPC - OpenFirmware platform bus. + module will be called isp1760. config USB_OHCI_HCD tristate "OHCI HCD support" diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 15a803b206b8..4725d15d096f 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -643,7 +643,7 @@ static int ehci_run (struct usb_hcd *hcd) static irqreturn_t ehci_irq (struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci (hcd); - u32 status, pcd_status = 0, cmd; + u32 status, masked_status, pcd_status = 0, cmd; int bh; spin_lock (&ehci->lock); @@ -656,14 +656,14 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) goto dead; } - status &= INTR_MASK; - if (!status) { /* irq sharing? */ + masked_status = status & INTR_MASK; + if (!masked_status) { /* irq sharing? */ spin_unlock(&ehci->lock); return IRQ_NONE; } /* clear (just) interrupts */ - ehci_writel(ehci, status, &ehci->regs->status); + ehci_writel(ehci, masked_status, &ehci->regs->status); cmd = ehci_readl(ehci, &ehci->regs->command); bh = 0; @@ -734,18 +734,17 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) /* PCI errors [4.15.2.4] */ if (unlikely ((status & STS_FATAL) != 0)) { + ehci_err(ehci, "fatal error\n"); dbg_cmd(ehci, "fatal", cmd); dbg_status(ehci, "fatal", status); - if (status & STS_HALT) { - ehci_err (ehci, "fatal error\n"); + ehci_halt(ehci); dead: - ehci_reset (ehci); - ehci_writel(ehci, 0, &ehci->regs->configured_flag); - /* generic layer kills/unlinks all urbs, then - * uses ehci_stop to clean up the rest - */ - bh = 1; - } + ehci_reset(ehci); + ehci_writel(ehci, 0, &ehci->regs->configured_flag); + /* generic layer kills/unlinks all urbs, then + * uses ehci_stop to clean up the rest + */ + bh = 1; } if (bh) diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index c46a58f9181d..36864f958444 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -66,6 +66,8 @@ static int ehci_pci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); struct pci_dev *pdev = to_pci_dev(hcd->self.controller); + struct pci_dev *p_smbus; + u8 rev; u32 temp; int retval; @@ -166,6 +168,28 @@ static int ehci_pci_setup(struct usb_hcd *hcd) pci_write_config_byte(pdev, 0x4b, tmp | 0x20); } break; + case PCI_VENDOR_ID_ATI: + /* SB600 and old version of SB700 have a bug in EHCI controller, + * which causes usb devices lose response in some cases. + */ + if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { + p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SBX00_SMBUS, + NULL); + if (!p_smbus) + break; + rev = p_smbus->revision; + if ((pdev->device == 0x4386) || (rev == 0x3a) + || (rev == 0x3b)) { + u8 tmp; + ehci_info(ehci, "applying AMD SB600/SB700 USB " + "freeze workaround\n"); + pci_read_config_byte(pdev, 0x53, &tmp); + pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); + } + pci_dev_put(p_smbus); + } + break; } ehci_reset(ehci); diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c index 0eba894bcb01..9c9da35abc6c 100644 --- a/drivers/usb/host/ehci-ps3.c +++ b/drivers/usb/host/ehci-ps3.c @@ -205,6 +205,7 @@ static int ps3_ehci_remove(struct ps3_system_bus_device *dev) tmp = hcd->irq; + ehci_shutdown(hcd); usb_remove_hcd(hcd); ps3_system_bus_set_driver_data(dev, NULL); diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c index 4a0c5a78b2ed..a081ee65bde6 100644 --- a/drivers/usb/host/ehci-sched.c +++ b/drivers/usb/host/ehci-sched.c @@ -918,7 +918,7 @@ iso_stream_init ( */ stream->usecs = HS_USECS_ISO (maxp); bandwidth = stream->usecs * 8; - bandwidth /= 1 << (interval - 1); + bandwidth /= interval; } else { u32 addr; @@ -951,7 +951,7 @@ iso_stream_init ( } else stream->raw_mask = smask_out [hs_transfers - 1]; bandwidth = stream->usecs + stream->c_usecs; - bandwidth /= 1 << (interval + 2); + bandwidth /= interval << 3; /* stream->splits gets created from raw_mask later */ stream->address = cpu_to_hc32(ehci, addr); diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index b11798d17ae5..c7d4b5a06bdb 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -183,16 +183,14 @@ timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) * the async ring; just the I/O watchdog. Note that if a * SHRINK were pending, OFF would never be requested. */ - enum ehci_timer_action oldactions = ehci->actions; + if (timer_pending(&ehci->watchdog) + && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) + & ehci->actions)) + return; if (!test_and_set_bit (action, &ehci->actions)) { unsigned long t; - if (timer_pending(&ehci->watchdog) - && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) - & oldactions)) - return; - switch (action) { case TIMER_IO_WATCHDOG: t = EHCI_IO_JIFFIES; @@ -208,7 +206,7 @@ timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; break; } - mod_timer(&ehci->watchdog, round_jiffies(t + jiffies)); + mod_timer(&ehci->watchdog, t + jiffies); } } diff --git a/drivers/usb/host/isp1760-if.c b/drivers/usb/host/isp1760-if.c index af849f596135..b87ca7cf4b37 100644 --- a/drivers/usb/host/isp1760-if.c +++ b/drivers/usb/host/isp1760-if.c @@ -14,16 +14,16 @@ #include "../core/hcd.h" #include "isp1760-hcd.h" -#ifdef CONFIG_USB_ISP1760_OF +#ifdef CONFIG_PPC_OF #include #include #endif -#ifdef CONFIG_USB_ISP1760_PCI +#ifdef CONFIG_PCI #include #endif -#ifdef CONFIG_USB_ISP1760_OF +#ifdef CONFIG_PPC_OF static int of_isp1760_probe(struct of_device *dev, const struct of_device_id *match) { @@ -128,7 +128,7 @@ static struct of_platform_driver isp1760_of_driver = { }; #endif -#ifdef CONFIG_USB_ISP1760_PCI +#ifdef CONFIG_PCI static u32 nxp_pci_io_base; static u32 iolength; static u32 pci_mem_phy0; @@ -288,28 +288,28 @@ static struct pci_driver isp1761_pci_driver = { static int __init isp1760_init(void) { - int ret = -ENODEV; + int ret; init_kmem_once(); -#ifdef CONFIG_USB_ISP1760_OF +#ifdef CONFIG_PPC_OF ret = of_register_platform_driver(&isp1760_of_driver); if (ret) { deinit_kmem_cache(); return ret; } #endif -#ifdef CONFIG_USB_ISP1760_PCI +#ifdef CONFIG_PCI ret = pci_register_driver(&isp1761_pci_driver); if (ret) goto unreg_of; #endif return ret; -#ifdef CONFIG_USB_ISP1760_PCI +#ifdef CONFIG_PCI unreg_of: #endif -#ifdef CONFIG_USB_ISP1760_OF +#ifdef CONFIG_PPC_OF of_unregister_platform_driver(&isp1760_of_driver); #endif deinit_kmem_cache(); @@ -319,10 +319,10 @@ module_init(isp1760_init); static void __exit isp1760_exit(void) { -#ifdef CONFIG_USB_ISP1760_OF +#ifdef CONFIG_PPC_OF of_unregister_platform_driver(&isp1760_of_driver); #endif -#ifdef CONFIG_USB_ISP1760_PCI +#ifdef CONFIG_PCI pci_unregister_driver(&isp1761_pci_driver); #endif deinit_kmem_cache(); diff --git a/drivers/usb/host/ohci-ps3.c b/drivers/usb/host/ohci-ps3.c index 2089d8a46c4b..3c1a3b5f89f1 100644 --- a/drivers/usb/host/ohci-ps3.c +++ b/drivers/usb/host/ohci-ps3.c @@ -192,7 +192,7 @@ fail_start: return result; } -static int ps3_ohci_remove (struct ps3_system_bus_device *dev) +static int ps3_ohci_remove(struct ps3_system_bus_device *dev) { unsigned int tmp; struct usb_hcd *hcd = @@ -205,6 +205,7 @@ static int ps3_ohci_remove (struct ps3_system_bus_device *dev) tmp = hcd->irq; + ohci_shutdown(hcd); usb_remove_hcd(hcd); ps3_system_bus_set_driver_data(dev, NULL); diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index c18d8790c410..2376f24f3c83 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -1763,11 +1763,12 @@ static void r8a66597_timer(unsigned long _r8a66597) { struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597; unsigned long flags; + int port; spin_lock_irqsave(&r8a66597->lock, flags); - r8a66597_root_hub_control(r8a66597, 0); - r8a66597_root_hub_control(r8a66597, 1); + for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) + r8a66597_root_hub_control(r8a66597, port); spin_unlock_irqrestore(&r8a66597->lock, flags); } diff --git a/drivers/usb/misc/sisusbvga/sisusb.c b/drivers/usb/misc/sisusbvga/sisusb.c index 69c34a58e205..b4ec716de7da 100644 --- a/drivers/usb/misc/sisusbvga/sisusb.c +++ b/drivers/usb/misc/sisusbvga/sisusb.c @@ -3270,6 +3270,7 @@ static struct usb_device_id sisusb_table [] = { { USB_DEVICE(0x0711, 0x0900) }, { USB_DEVICE(0x0711, 0x0901) }, { USB_DEVICE(0x0711, 0x0902) }, + { USB_DEVICE(0x0711, 0x0903) }, { USB_DEVICE(0x0711, 0x0918) }, { USB_DEVICE(0x182d, 0x021c) }, { USB_DEVICE(0x182d, 0x0269) }, diff --git a/drivers/usb/misc/vstusb.c b/drivers/usb/misc/vstusb.c index 8648470c81ca..63dff9ba73c5 100644 --- a/drivers/usb/misc/vstusb.c +++ b/drivers/usb/misc/vstusb.c @@ -620,7 +620,7 @@ static long vstusb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) __func__); retval = -EFAULT; } else { - dev_dbg(&dev->dev, "%s: recv %d bytes from pipe %d\n", + dev_dbg(&dev->dev, "%s: recv %zd bytes from pipe %d\n", __func__, usb_data.count, usb_data.pipe); } diff --git a/drivers/usb/mon/mon_bin.c b/drivers/usb/mon/mon_bin.c index c9de3f027aab..e06810aef2df 100644 --- a/drivers/usb/mon/mon_bin.c +++ b/drivers/usb/mon/mon_bin.c @@ -687,7 +687,10 @@ static ssize_t mon_bin_read(struct file *file, char __user *buf, } if (rp->b_read >= sizeof(struct mon_bin_hdr)) { - step_len = min(nbytes, (size_t)ep->len_cap); + step_len = ep->len_cap; + step_len -= rp->b_read - sizeof(struct mon_bin_hdr); + if (step_len > nbytes) + step_len = nbytes; offset = rp->b_out + PKT_SIZE; offset += rp->b_read - sizeof(struct mon_bin_hdr); if (offset >= rp->b_size) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 4a35745b30be..5280dba9b1fb 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -114,8 +114,8 @@ -unsigned debug; -module_param(debug, uint, S_IRUGO | S_IWUSR); +unsigned musb_debug; +module_param(musb_debug, uint, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" @@ -2248,7 +2248,7 @@ static int __init musb_init(void) "host" #endif ", debug=%d\n", - musb_driver_name, debug); + musb_driver_name, musb_debug); return platform_driver_probe(&musb_driver, musb_probe); } diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h index 4d2794441b15..9fc1db44c72c 100644 --- a/drivers/usb/musb/musb_debug.h +++ b/drivers/usb/musb/musb_debug.h @@ -48,11 +48,11 @@ __func__, __LINE__ , ## args); \ } } while (0) -extern unsigned debug; +extern unsigned musb_debug; static inline int _dbg_level(unsigned l) { - return debug >= l; + return musb_debug >= l; } #define DBG(level, fmt, args...) xprintk(level, KERN_DEBUG, fmt, ## args) diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 3133990f04ec..cc64462d4c4e 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -378,6 +378,19 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status) switch (qh->type) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + /* fifo policy for these lists, except that NAKing + * should rotate a qh to the end (for fairness). + */ + if (qh->mux == 1) { + head = qh->ring.prev; + list_del(&qh->ring); + kfree(qh); + qh = first_qh(head); + break; + } + case USB_ENDPOINT_XFER_ISOC: case USB_ENDPOINT_XFER_INT: /* this is where periodic bandwidth should be @@ -388,17 +401,6 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status) kfree(qh); qh = NULL; break; - - case USB_ENDPOINT_XFER_CONTROL: - case USB_ENDPOINT_XFER_BULK: - /* fifo policy for these lists, except that NAKing - * should rotate a qh to the end (for fairness). - */ - head = qh->ring.prev; - list_del(&qh->ring); - kfree(qh); - qh = first_qh(head); - break; } } return qh; @@ -1507,10 +1509,29 @@ void musb_host_rx(struct musb *musb, u8 epnum) musb_writew(hw_ep->regs, MUSB_RXCSR, val); #ifdef CONFIG_USB_INVENTRA_DMA + if (usb_pipeisoc(pipe)) { + struct usb_iso_packet_descriptor *d; + + d = urb->iso_frame_desc + qh->iso_idx; + d->actual_length = xfer_len; + + /* even if there was an error, we did the dma + * for iso_frame_desc->length + */ + if (d->status != EILSEQ && d->status != -EOVERFLOW) + d->status = 0; + + if (++qh->iso_idx >= urb->number_of_packets) + done = true; + else + done = false; + + } else { /* done if urb buffer is full or short packet is recd */ done = (urb->actual_length + xfer_len >= urb->transfer_buffer_length || dma->actual_len < qh->maxpacket); + } /* send IN token for next packet, without AUTOREQ */ if (!done) { @@ -1547,7 +1568,8 @@ void musb_host_rx(struct musb *musb, u8 epnum) if (dma) { struct dma_controller *c; u16 rx_count; - int ret; + int ret, length; + dma_addr_t buf; rx_count = musb_readw(epio, MUSB_RXCOUNT); @@ -1560,6 +1582,35 @@ void musb_host_rx(struct musb *musb, u8 epnum) c = musb->dma_controller; + if (usb_pipeisoc(pipe)) { + int status = 0; + struct usb_iso_packet_descriptor *d; + + d = urb->iso_frame_desc + qh->iso_idx; + + if (iso_err) { + status = -EILSEQ; + urb->error_count++; + } + if (rx_count > d->length) { + if (status == 0) { + status = -EOVERFLOW; + urb->error_count++; + } + DBG(2, "** OVERFLOW %d into %d\n",\ + rx_count, d->length); + + length = d->length; + } else + length = rx_count; + d->status = status; + buf = urb->transfer_dma + d->offset; + } else { + length = rx_count; + buf = urb->transfer_dma + + urb->actual_length; + } + dma->desired_mode = 0; #ifdef USE_MODE1 /* because of the issue below, mode 1 will @@ -1571,6 +1622,12 @@ void musb_host_rx(struct musb *musb, u8 epnum) urb->actual_length) > qh->maxpacket) dma->desired_mode = 1; + if (rx_count < hw_ep->max_packet_sz_rx) { + length = rx_count; + dma->bDesiredMode = 0; + } else { + length = urb->transfer_buffer_length; + } #endif /* Disadvantage of using mode 1: @@ -1608,12 +1665,7 @@ void musb_host_rx(struct musb *musb, u8 epnum) */ ret = c->channel_program( dma, qh->maxpacket, - dma->desired_mode, - urb->transfer_dma - + urb->actual_length, - (dma->desired_mode == 0) - ? rx_count - : urb->transfer_buffer_length); + dma->desired_mode, buf, length); if (!ret) { c->channel_release(dma); @@ -1631,19 +1683,6 @@ void musb_host_rx(struct musb *musb, u8 epnum) } } - if (dma && usb_pipeisoc(pipe)) { - struct usb_iso_packet_descriptor *d; - int iso_stat = status; - - d = urb->iso_frame_desc + qh->iso_idx; - d->actual_length += xfer_len; - if (iso_err) { - iso_stat = -EILSEQ; - urb->error_count++; - } - d->status = iso_stat; - } - finish: urb->actual_length += xfer_len; qh->offset += xfer_len; @@ -1671,22 +1710,9 @@ static int musb_schedule( struct list_head *head = NULL; /* use fixed hardware for control and bulk */ - switch (qh->type) { - case USB_ENDPOINT_XFER_CONTROL: + if (qh->type == USB_ENDPOINT_XFER_CONTROL) { head = &musb->control; hw_ep = musb->control_ep; - break; - case USB_ENDPOINT_XFER_BULK: - hw_ep = musb->bulk_ep; - if (is_in) - head = &musb->in_bulk; - else - head = &musb->out_bulk; - break; - } - if (head) { - idle = list_empty(head); - list_add_tail(&qh->ring, head); goto success; } @@ -1725,19 +1751,34 @@ static int musb_schedule( else diff = hw_ep->max_packet_sz_tx - qh->maxpacket; - if (diff > 0 && best_diff > diff) { + if (diff >= 0 && best_diff > diff) { best_diff = diff; best_end = epnum; } } - if (best_end < 0) + /* use bulk reserved ep1 if no other ep is free */ + if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { + hw_ep = musb->bulk_ep; + if (is_in) + head = &musb->in_bulk; + else + head = &musb->out_bulk; + goto success; + } else if (best_end < 0) { return -ENOSPC; + } idle = 1; + qh->mux = 0; hw_ep = musb->endpoints + best_end; musb->periodic[best_end] = qh; DBG(4, "qh %p periodic slot %d\n", qh, best_end); success: + if (head) { + idle = list_empty(head); + list_add_tail(&qh->ring, head); + qh->mux = 1; + } qh->hw_ep = hw_ep; qh->hep->hcpriv = qh; if (idle) @@ -2015,11 +2056,13 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) sched = &musb->control; break; case USB_ENDPOINT_XFER_BULK: - if (usb_pipein(urb->pipe)) - sched = &musb->in_bulk; - else - sched = &musb->out_bulk; - break; + if (qh->mux == 1) { + if (usb_pipein(urb->pipe)) + sched = &musb->in_bulk; + else + sched = &musb->out_bulk; + break; + } default: /* REVISIT when we get a schedule tree, periodic * transfers won't always be at the head of a @@ -2067,11 +2110,13 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) sched = &musb->control; break; case USB_ENDPOINT_XFER_BULK: - if (is_in) - sched = &musb->in_bulk; - else - sched = &musb->out_bulk; - break; + if (qh->mux == 1) { + if (is_in) + sched = &musb->in_bulk; + else + sched = &musb->out_bulk; + break; + } default: /* REVISIT when we get a schedule tree, periodic transfers * won't always be at the head of a singleton queue... diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h index 77bcdb9d5b32..0b7fbcd21963 100644 --- a/drivers/usb/musb/musb_host.h +++ b/drivers/usb/musb/musb_host.h @@ -53,6 +53,7 @@ struct musb_qh { struct list_head ring; /* of musb_qh */ /* struct musb_qh *next; */ /* for periodic tree */ + u8 mux; /* qh multiplexed to hw_ep */ unsigned offset; /* in urb->transfer_buffer */ unsigned segsize; /* current xfer fragment */ diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index 9d2dcb121c5e..ce6c162920f7 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -53,7 +53,9 @@ static void musb_do_idle(unsigned long _musb) { struct musb *musb = (void *)_musb; unsigned long flags; +#ifdef CONFIG_USB_MUSB_HDRC_HCD u8 power; +#endif u8 devctl; devctl = musb_readb(musb->mregs, MUSB_DEVCTL); diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c index b73b036f3d77..ee8fca92a4ac 100644 --- a/drivers/usb/musb/tusb6010.c +++ b/drivers/usb/musb/tusb6010.c @@ -605,7 +605,7 @@ void musb_platform_set_mode(struct musb *musb, u8 musb_mode) if (musb->board_mode != MUSB_OTG) { ERR("Changing mode currently only supported in OTG mode\n"); - return; + return -EINVAL; } otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c index 5b20de130e08..5b95009d2fbb 100644 --- a/drivers/usb/serial/console.c +++ b/drivers/usb/serial/console.c @@ -135,6 +135,7 @@ static int usb_console_setup(struct console *co, char *options) err("no more memory"); goto reset_open_count; } + kref_init(&tty->kref); termios = kzalloc(sizeof(*termios), GFP_KERNEL); if (!termios) { retval = -ENOMEM; diff --git a/drivers/usb/serial/cp2101.c b/drivers/usb/serial/cp2101.c index 8008d0bc80ad..cfaf1f085535 100644 --- a/drivers/usb/serial/cp2101.c +++ b/drivers/usb/serial/cp2101.c @@ -56,6 +56,7 @@ static void cp2101_shutdown(struct usb_serial *); static int debug; static struct usb_device_id id_table [] = { + { USB_DEVICE(0x0471, 0x066A) }, /* AKTAKOM ACE-1001 cable */ { USB_DEVICE(0x0489, 0xE000) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */ { USB_DEVICE(0x08e6, 0x5501) }, /* Gemalto Prox-PU/CU contactless smartcard reader */ { USB_DEVICE(0x0FCF, 0x1003) }, /* Dynastream ANT development board */ @@ -67,6 +68,7 @@ static struct usb_device_id id_table [] = { { USB_DEVICE(0x10C4, 0x800A) }, /* SPORTident BSM7-D-USB main station */ { USB_DEVICE(0x10C4, 0x803B) }, /* Pololu USB-serial converter */ { USB_DEVICE(0x10C4, 0x8053) }, /* Enfora EDG1228 */ + { USB_DEVICE(0x10C4, 0x8054) }, /* Enfora GSM2228 */ { USB_DEVICE(0x10C4, 0x8066) }, /* Argussoft In-System Programmer */ { USB_DEVICE(0x10C4, 0x807A) }, /* Crumb128 board */ { USB_DEVICE(0x10C4, 0x80CA) }, /* Degree Controls Inc */ @@ -85,6 +87,7 @@ static struct usb_device_id id_table [] = { { USB_DEVICE(0x10C4, 0x8218) }, /* Lipowsky Industrie Elektronik GmbH, HARP-1 */ { USB_DEVICE(0x10c4, 0x8293) }, /* Telegesys ETRX2USB */ { USB_DEVICE(0x10C4, 0x8341) }, /* Siemens MC35PU GPRS Modem */ + { USB_DEVICE(0x10C4, 0x83A8) }, /* Amber Wireless AMB2560 */ { USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */ { USB_DEVICE(0x10C4, 0xEA61) }, /* Silicon Labs factory default */ { USB_DEVICE(0x10C4, 0xF001) }, /* Elan Digital Systems USBscope50 */ diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c index 51d7bdea2869..fb6f2933b01b 100644 --- a/drivers/usb/serial/ftdi_sio.c +++ b/drivers/usb/serial/ftdi_sio.c @@ -143,6 +143,7 @@ static struct ftdi_sio_quirk ftdi_HE_TIRA1_quirk = { static struct usb_device_id id_table_combined [] = { { USB_DEVICE(FTDI_VID, FTDI_AMC232_PID) }, { USB_DEVICE(FTDI_VID, FTDI_CANUSB_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_CANDAPTER_PID) }, { USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_0_PID) }, { USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_1_PID) }, { USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_2_PID) }, @@ -166,6 +167,7 @@ static struct usb_device_id id_table_combined [] = { { USB_DEVICE(FTDI_VID, FTDI_OPENDCC_PID) }, { USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_IOBOARD_PID) }, { USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_MINI_IOBOARD_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_SPROG_II) }, { USB_DEVICE(FTDI_VID, FTDI_XF_632_PID) }, { USB_DEVICE(FTDI_VID, FTDI_XF_634_PID) }, { USB_DEVICE(FTDI_VID, FTDI_XF_547_PID) }, @@ -1498,7 +1500,7 @@ static int ftdi_open(struct tty_struct *tty, priv->interface, buf, 0, WDR_TIMEOUT); /* Termios defaults are set by usb_serial_init. We don't change - port->tty->termios - this would loose speed settings, etc. + port->tty->termios - this would lose speed settings, etc. This is same behaviour as serial.c/rs_open() - Kuba */ /* ftdi_set_termios will send usb control messages */ diff --git a/drivers/usb/serial/ftdi_sio.h b/drivers/usb/serial/ftdi_sio.h index 07a3992abad2..373ee09975bb 100644 --- a/drivers/usb/serial/ftdi_sio.h +++ b/drivers/usb/serial/ftdi_sio.h @@ -40,6 +40,9 @@ /* AlphaMicro Components AMC-232USB01 device */ #define FTDI_AMC232_PID 0xFF00 /* Product Id */ +/* www.candapter.com Ewert Energy Systems CANdapter device */ +#define FTDI_CANDAPTER_PID 0x9F80 /* Product Id */ + /* SCS HF Radio Modems PID's (http://www.scs-ptc.com) */ /* the VID is the standard ftdi vid (FTDI_VID) */ #define FTDI_SCS_DEVICE_0_PID 0xD010 /* SCS PTC-IIusb */ @@ -75,6 +78,9 @@ /* OpenDCC (www.opendcc.de) product id */ #define FTDI_OPENDCC_PID 0xBFD8 +/* Sprog II (Andrew Crosland's SprogII DCC interface) */ +#define FTDI_SPROG_II 0xF0C8 + /* www.crystalfontz.com devices - thanx for providing free devices for evaluation ! */ /* they use the ftdi chipset for the USB interface and the vendor id is the same */ #define FTDI_XF_632_PID 0xFC08 /* 632: 16x2 Character Display */ diff --git a/drivers/usb/serial/ir-usb.c b/drivers/usb/serial/ir-usb.c index b679a556b98d..4e2cda93da59 100644 --- a/drivers/usb/serial/ir-usb.c +++ b/drivers/usb/serial/ir-usb.c @@ -26,7 +26,7 @@ * Introduced common header to be used also in USB Gadget Framework. * Still needs some other style fixes. * - * 2007_Jun_21 Alan Cox + * 2007_Jun_21 Alan Cox * Minimal cleanups for some of the driver problens and tty layer abuse. * Still needs fixing to allow multiple dongles. * diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index bd07eaa300b9..809697b3c7fc 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -160,6 +160,11 @@ static int option_send_setup(struct tty_struct *tty, struct usb_serial_port *po #define NOVATELWIRELESS_VENDOR_ID 0x1410 +/* YISO PRODUCTS */ + +#define YISO_VENDOR_ID 0x0EAB +#define YISO_PRODUCT_U893 0xC893 + /* MERLIN EVDO PRODUCTS */ #define NOVATELWIRELESS_PRODUCT_V640 0x1100 #define NOVATELWIRELESS_PRODUCT_V620 0x1110 @@ -219,6 +224,7 @@ static int option_send_setup(struct tty_struct *tty, struct usb_serial_port *po #define ONDA_VENDOR_ID 0x19d2 #define ONDA_PRODUCT_MSA501HS 0x0001 #define ONDA_PRODUCT_ET502HS 0x0002 +#define ONDA_PRODUCT_MT503HS 0x0200 #define BANDRICH_VENDOR_ID 0x1A8D #define BANDRICH_PRODUCT_C100_1 0x1002 @@ -408,6 +414,41 @@ static struct usb_device_id option_ids[] = { { USB_DEVICE(AXESSTEL_VENDOR_ID, AXESSTEL_PRODUCT_MV110H) }, { USB_DEVICE(ONDA_VENDOR_ID, ONDA_PRODUCT_MSA501HS) }, { USB_DEVICE(ONDA_VENDOR_ID, ONDA_PRODUCT_ET502HS) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0003) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0004) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0005) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0006) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0007) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0008) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0009) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x000a) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x000b) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x000c) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x000d) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x000e) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x000f) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0010) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0011) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0012) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0013) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0014) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0015) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0016) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0017) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0018) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0019) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0020) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0021) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0022) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0023) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0024) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0025) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0026) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0027) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0028) }, + { USB_DEVICE(ONDA_VENDOR_ID, 0x0029) }, + { USB_DEVICE(ONDA_VENDOR_ID, ONDA_PRODUCT_MT503HS) }, + { USB_DEVICE(YISO_VENDOR_ID, YISO_PRODUCT_U893) }, { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_C100_1) }, { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_C100_2) }, { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1004) }, diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c index 491c8857b644..1aed584be5eb 100644 --- a/drivers/usb/serial/pl2303.c +++ b/drivers/usb/serial/pl2303.c @@ -91,6 +91,8 @@ static struct usb_device_id id_table [] = { { USB_DEVICE(WS002IN_VENDOR_ID, WS002IN_PRODUCT_ID) }, { USB_DEVICE(COREGA_VENDOR_ID, COREGA_PRODUCT_ID) }, { USB_DEVICE(YCCABLE_VENDOR_ID, YCCABLE_PRODUCT_ID) }, + { USB_DEVICE(SUPERIAL_VENDOR_ID, SUPERIAL_PRODUCT_ID) }, + { USB_DEVICE(HP_VENDOR_ID, HP_LD220_PRODUCT_ID) }, { } /* Terminating entry */ }; diff --git a/drivers/usb/serial/pl2303.h b/drivers/usb/serial/pl2303.h index a3bd039c78e9..54974f446a8c 100644 --- a/drivers/usb/serial/pl2303.h +++ b/drivers/usb/serial/pl2303.h @@ -110,3 +110,11 @@ /* Y.C. Cable U.S.A., Inc - USB to RS-232 */ #define YCCABLE_VENDOR_ID 0x05ad #define YCCABLE_PRODUCT_ID 0x0fba + +/* "Superial" USB - Serial */ +#define SUPERIAL_VENDOR_ID 0x5372 +#define SUPERIAL_PRODUCT_ID 0x2303 + +/* Hewlett-Packard LD220-HP POS Pole Display */ +#define HP_VENDOR_ID 0x03f0 +#define HP_LD220_PRODUCT_ID 0x3524 diff --git a/drivers/usb/serial/ti_usb_3410_5052.c b/drivers/usb/serial/ti_usb_3410_5052.c index 31c42d1cae13..01d0c70d60e9 100644 --- a/drivers/usb/serial/ti_usb_3410_5052.c +++ b/drivers/usb/serial/ti_usb_3410_5052.c @@ -16,56 +16,6 @@ * For questions or problems with this driver, contact Texas Instruments * technical support, or Al Borchers , or * Peter Berger . - * - * This driver needs this hotplug script in /etc/hotplug/usb/ti_usb_3410_5052 - * or in /etc/hotplug.d/usb/ti_usb_3410_5052.hotplug to set the device - * configuration. - * - * #!/bin/bash - * - * BOOT_CONFIG=1 - * ACTIVE_CONFIG=2 - * - * if [[ "$ACTION" != "add" ]] - * then - * exit - * fi - * - * CONFIG_PATH=/sys${DEVPATH%/?*}/bConfigurationValue - * - * if [[ 0`cat $CONFIG_PATH` -ne $BOOT_CONFIG ]] - * then - * exit - * fi - * - * PRODUCT=${PRODUCT%/?*} # delete version - * VENDOR_ID=`printf "%d" 0x${PRODUCT%/?*}` - * PRODUCT_ID=`printf "%d" 0x${PRODUCT#*?/}` - * - * PARAM_PATH=/sys/module/ti_usb_3410_5052/parameters - * - * function scan() { - * s=$1 - * shift - * for i - * do - * if [[ $s -eq $i ]] - * then - * return 0 - * fi - * done - * return 1 - * } - * - * IFS=$IFS, - * - * if (scan $VENDOR_ID 1105 `cat $PARAM_PATH/vendor_3410` && - * scan $PRODUCT_ID 13328 `cat $PARAM_PATH/product_3410`) || - * (scan $VENDOR_ID 1105 `cat $PARAM_PATH/vendor_5052` && - * scan $PRODUCT_ID 20562 20818 20570 20575 `cat $PARAM_PATH/product_5052`) - * then - * echo $ACTIVE_CONFIG > $CONFIG_PATH - * fi */ #include @@ -457,9 +407,10 @@ static int ti_startup(struct usb_serial *serial) goto free_tdev; } - /* the second configuration must be set (in sysfs by hotplug script) */ + /* the second configuration must be set */ if (dev->actconfig->desc.bConfigurationValue == TI_BOOT_CONFIG) { - status = -ENODEV; + status = usb_driver_set_configuration(dev, TI_ACTIVE_CONFIG); + status = status ? status : -ENODEV; goto free_tdev; } diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c index 8be3f39891c7..794b5ffe4397 100644 --- a/drivers/usb/serial/usb-serial.c +++ b/drivers/usb/serial/usb-serial.c @@ -281,6 +281,7 @@ static void serial_close(struct tty_struct *tty, struct file *filp) if (tty->driver_data) tty->driver_data = NULL; tty_port_tty_set(&port->port, NULL); + tty_kref_put(tty); } } diff --git a/drivers/usb/storage/Kconfig b/drivers/usb/storage/Kconfig index 3d9249632ae1..c68b738900bd 100644 --- a/drivers/usb/storage/Kconfig +++ b/drivers/usb/storage/Kconfig @@ -2,8 +2,8 @@ # USB Storage driver configuration # -comment "NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'" -comment "may also be needed; see USB_STORAGE Help for more information" +comment "NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;" +comment "see USB_STORAGE Help for more information" depends on USB config USB_STORAGE diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h index a2b9ebbef38e..bfcc1fe82518 100644 --- a/drivers/usb/storage/unusual_devs.h +++ b/drivers/usb/storage/unusual_devs.h @@ -167,6 +167,27 @@ UNUSUAL_DEV( 0x0421, 0x005d, 0x0001, 0x0600, US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_CAPACITY ), +/* Reported by Ozan Sener */ +UNUSUAL_DEV( 0x0421, 0x0060, 0x0551, 0x0551, + "Nokia", + "3500c", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY ), + +/* Reported by CSECSY Laszlo */ +UNUSUAL_DEV( 0x0421, 0x0063, 0x0001, 0x0601, + "Nokia", + "Nokia 3109c", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY ), + +/* Patch for Nokia 5310 capacity */ +UNUSUAL_DEV( 0x0421, 0x006a, 0x0000, 0x0701, + "Nokia", + "5310", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY ), + /* Reported by Mario Rettig */ UNUSUAL_DEV( 0x0421, 0x042e, 0x0100, 0x0100, "Nokia", @@ -233,14 +254,14 @@ UNUSUAL_DEV( 0x0421, 0x0495, 0x0370, 0x0370, US_FL_MAX_SECTORS_64 ), /* Reported by Cedric Godin */ -UNUSUAL_DEV( 0x0421, 0x04b9, 0x0551, 0x0551, +UNUSUAL_DEV( 0x0421, 0x04b9, 0x0500, 0x0551, "Nokia", "5300", US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_CAPACITY ), /* Reported by Richard Nauber */ -UNUSUAL_DEV( 0x0421, 0x04fa, 0x0601, 0x0601, +UNUSUAL_DEV( 0x0421, 0x04fa, 0x0550, 0x0660, "Nokia", "6300", US_SC_DEVICE, US_PR_DEVICE, NULL, @@ -253,6 +274,14 @@ UNUSUAL_DEV( 0x0421, 0x006a, 0x0000, 0x0591, US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_CAPACITY ), +/* Submitted by Ricky Wong Yung Fei */ +/* Nokia 7610 Supernova - Too many sectors reported in usb storage mode */ +UNUSUAL_DEV( 0x0421, 0x00f5, 0x0000, 0x0470, + "Nokia", + "7610 Supernova", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY ), + /* Reported by Olaf Hering from novell bug #105878 */ UNUSUAL_DEV( 0x0424, 0x0fdc, 0x0210, 0x0210, "SMSC", @@ -303,6 +332,18 @@ UNUSUAL_DEV( 0x045a, 0x5210, 0x0101, 0x0101, US_SC_SCSI, US_PR_KARMA, rio_karma_init, 0), #endif +/* Reported by Tamas Kerecsen + * Obviously the PROM has not been customized by the VAR; + * the Vendor and Product string descriptors are: + * Generic Mass Storage (PROTOTYPE--Remember to change idVendor) + * Generic Manufacturer (PROTOTYPE--Remember to change idVendor) + */ +UNUSUAL_DEV( 0x045e, 0xffff, 0x0000, 0x0000, + "Mitac", + "GPS", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_MAX_SECTORS_64 ), + /* * This virtual floppy is found in Sun equipment (x4600, x4200m2, etc.) * Reported by Pete Zaitcev @@ -333,6 +374,13 @@ UNUSUAL_DEV( 0x0482, 0x0103, 0x0100, 0x0100, "Finecam S5", US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_INQUIRY), +/* Patch submitted by Jens Taprogge */ +UNUSUAL_DEV( 0x0482, 0x0107, 0x0100, 0x0100, + "Kyocera", + "CONTAX SL300R T*", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY | US_FL_NOT_LOCKABLE), + /* Reported by Paul Stewart * This entry is needed because the device reports Sub=ff */ UNUSUAL_DEV( 0x04a4, 0x0004, 0x0001, 0x0001, @@ -355,6 +403,13 @@ UNUSUAL_DEV( 0x04b0, 0x0401, 0x0200, 0x0200, US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_CAPACITY), +/* Reported by Tobias Kunze Briseno */ +UNUSUAL_DEV( 0x04b0, 0x0403, 0x0200, 0x0200, + "NIKON", + "NIKON DSC D2H", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY), + /* Reported by Milinevsky Dmitry */ UNUSUAL_DEV( 0x04b0, 0x0409, 0x0100, 0x0100, "NIKON", @@ -411,6 +466,13 @@ UNUSUAL_DEV( 0x04b0, 0x0417, 0x0100, 0x0100, US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_CAPACITY), +/* Reported by paul ready */ +UNUSUAL_DEV( 0x04b0, 0x0419, 0x0100, 0x0200, + "NIKON", + "NIKON DSC D300", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY), + /* Reported by Doug Maxey (dwm@austin.ibm.com) */ UNUSUAL_DEV( 0x04b3, 0x4001, 0x0110, 0x0110, "IBM", @@ -1251,6 +1313,13 @@ UNUSUAL_DEV( 0x0839, 0x000a, 0x0001, 0x0001, US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_INQUIRY), +/* Reported by Luciano Rocha */ +UNUSUAL_DEV( 0x0840, 0x0082, 0x0001, 0x0001, + "Argosy", + "Storage", + US_SC_DEVICE, US_PR_DEVICE, NULL, + US_FL_FIX_CAPACITY), + /* Entry and supporting patch by Theodore Kilgore . * Flag will support Bulk devices which use a standards-violating 32-byte * Command Block Wrapper. Here, the "DC2MEGA" cameras (several brands) with diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 0f13448c6f79..3f3ce13fef43 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2083,6 +2083,38 @@ config FB_METRONOME controller. The pre-release name for this device was 8track and could also have been called by some vendors as PVI-nnnn. +config FB_MB862XX + tristate "Fujitsu MB862xx GDC support" + depends on FB + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers. + +config FB_MB862XX_PCI_GDC + bool "Carmine/Coral-P(A) GDC" + depends on PCI && FB_MB862XX + ---help--- + This enables framebuffer support for Fujitsu Carmine/Coral-P(A) + PCI graphics controller devices. + +config FB_MB862XX_LIME + bool "Lime GDC" + depends on FB_MB862XX + depends on OF && !FB_MB862XX_PCI_GDC + select FB_FOREIGN_ENDIAN + select FB_LITTLE_ENDIAN + ---help--- + Framebuffer support for Fujitsu Lime GDC on host CPU bus. + +config FB_PRE_INIT_FB + bool "Don't reinitialize, use bootloader's GDC/Display configuration" + depends on FB_MB862XX_LIME + ---help--- + Select this option if display contents should be inherited as set by + the bootloader. + source "drivers/video/omap/Kconfig" source "drivers/video/backlight/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 248bddc8d0b0..e39e33e797da 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -122,6 +122,7 @@ obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o obj-$(CONFIG_FB_OMAP) += omap/ obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o obj-$(CONFIG_FB_CARMINE) += carminefb.o +obj-$(CONFIG_FB_MB862XX) += mb862xx/ # Platform or fallback drivers go here obj-$(CONFIG_FB_UVESA) += uvesafb.o diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index f8d0a57a07cb..9a577a800db5 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -132,7 +132,7 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo) bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo, &atmel_lcdc_bl_ops); - if (IS_ERR(sinfo->backlight)) { + if (IS_ERR(bl)) { dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n", PTR_ERR(bl)); return; diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c index 8718f7349d6b..a469a3d6edcb 100644 --- a/drivers/video/aty/radeon_accel.c +++ b/drivers/video/aty/radeon_accel.c @@ -5,61 +5,61 @@ * --dte */ -#define FLUSH_CACHE_WORKAROUND 1 - -void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries) +static void radeon_fixup_offset(struct radeonfb_info *rinfo) { - int i; + u32 local_base; + + /* *** Ugly workaround *** */ + /* + * On some platforms, the video memory is mapped at 0 in radeon chip space + * (like PPCs) by the firmware. X will always move it up so that it's seen + * by the chip to be at the same address as the PCI BAR. + * That means that when switching back from X, there is a mismatch between + * the offsets programmed into the engine. This means that potentially, + * accel operations done before radeonfb has a chance to re-init the engine + * will have incorrect offsets, and potentially trash system memory ! + * + * The correct fix is for fbcon to never call any accel op before the engine + * has properly been re-initialized (by a call to set_var), but this is a + * complex fix. This workaround in the meantime, called before every accel + * operation, makes sure the offsets are in sync. + */ - for (i=0; i<2000000; i++) { - rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f; - if (rinfo->fifo_free >= entries) - return; - udelay(10); - } - printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); - /* XXX Todo: attempt to reset the engine */ -} + radeon_fifo_wait (1); + local_base = INREG(MC_FB_LOCATION) << 16; + if (local_base == rinfo->fb_local_base) + return; -static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) -{ - if (entries <= rinfo->fifo_free) - rinfo->fifo_free -= entries; - else - radeon_fifo_update_and_wait(rinfo, entries); -} + rinfo->fb_local_base = local_base; -static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg, - u32 *cache, u32 new_val) -{ - if (new_val == *cache) - return; - *cache = new_val; - radeon_fifo_wait(rinfo, 1); - OUTREG(reg, new_val); + radeon_fifo_wait (3); + OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | + (rinfo->fb_local_base >> 10)); + OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); + OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); } static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, const struct fb_fillrect *region) { - radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, - rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P); - radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, - DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); - radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache, - region->color); - - /* Ensure the dst cache is flushed and the engine idle before - * issuing the operation. - * - * This works around engine lockups on some cards - */ -#if FLUSH_CACHE_WORKAROUND - radeon_fifo_wait(rinfo, 2); + radeon_fifo_wait(4); + + OUTREG(DP_GUI_MASTER_CNTL, + rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */ + | GMC_BRUSH_SOLID_COLOR + | ROP3_P); + if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP) + OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]); + else + OUTREG(DP_BRUSH_FRGD_CLR, region->color); + OUTREG(DP_WRITE_MSK, 0xffffffff); + OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); + + radeon_fifo_wait(2); OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); -#endif - radeon_fifo_wait(rinfo, 2); + + radeon_fifo_wait(2); OUTREG(DST_Y_X, (region->dy << 16) | region->dx); OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); } @@ -70,14 +70,15 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region) struct fb_fillrect modded; int vxres, vyres; - WARN_ON(rinfo->gfx_mode); - if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode) + if (info->state != FBINFO_STATE_RUNNING) return; if (info->flags & FBINFO_HWACCEL_DISABLED) { cfb_fillrect(info, region); return; } + radeon_fixup_offset(rinfo); + vxres = info->var.xres_virtual; vyres = info->var.yres_virtual; @@ -90,10 +91,6 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region) if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR ) - modded.color = ((u32 *) (info->pseudo_palette))[region->color]; - radeonfb_prim_fillrect(rinfo, &modded); } @@ -112,22 +109,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo, if ( xdir < 0 ) { sx += w-1; dx += w-1; } if ( ydir < 0 ) { sy += h-1; dy += h-1; } - radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, - rinfo->dp_gui_mc_base | - GMC_BRUSH_NONE | - GMC_SRC_DATATYPE_COLOR | - ROP3_S | - DP_SRC_SOURCE_MEMORY); - radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, - (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) | - (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); - -#if FLUSH_CACHE_WORKAROUND - radeon_fifo_wait(rinfo, 2); + radeon_fifo_wait(3); + OUTREG(DP_GUI_MASTER_CNTL, + rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */ + | GMC_BRUSH_NONE + | GMC_SRC_DSTCOLOR + | ROP3_S + | DP_SRC_SOURCE_MEMORY ); + OUTREG(DP_WRITE_MSK, 0xffffffff); + OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) + | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); + + radeon_fifo_wait(2); OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); -#endif - radeon_fifo_wait(rinfo, 3); + + radeon_fifo_wait(3); OUTREG(SRC_Y_X, (sy << 16) | sx); OUTREG(DST_Y_X, (dy << 16) | dx); OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); @@ -146,14 +143,15 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) modded.width = area->width; modded.height = area->height; - WARN_ON(rinfo->gfx_mode); - if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode) + if (info->state != FBINFO_STATE_RUNNING) return; if (info->flags & FBINFO_HWACCEL_DISABLED) { cfb_copyarea(info, area); return; } + radeon_fixup_offset(rinfo); + vxres = info->var.xres_virtual; vyres = info->var.yres_virtual; @@ -170,112 +168,13 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) radeonfb_prim_copyarea(rinfo, &modded); } -static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo, - const struct fb_image *image, - u32 fg, u32 bg) -{ - unsigned int src_bytes, dwords; - u32 *bits; - - radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, - rinfo->dp_gui_mc_base | - GMC_BRUSH_NONE | - GMC_SRC_DATATYPE_MONO_FG_BG | - ROP3_S | - GMC_BYTE_ORDER_MSB_TO_LSB | - DP_SRC_SOURCE_HOST_DATA); - radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, - DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); - radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg); - radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg); - - radeon_fifo_wait(rinfo, 1); - OUTREG(DST_Y_X, (image->dy << 16) | image->dx); - - /* Ensure the dst cache is flushed and the engine idle before - * issuing the operation. - * - * This works around engine lockups on some cards - */ -#if FLUSH_CACHE_WORKAROUND - radeon_fifo_wait(rinfo, 2); - OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); - OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); -#endif - - /* X here pads width to a multiple of 32 and uses the clipper to - * adjust the result. Is that really necessary ? Things seem to - * work ok for me without that and the doco doesn't seem to imply - * there is such a restriction. - */ - OUTREG(DST_WIDTH_HEIGHT, (image->width << 16) | image->height); - - src_bytes = (((image->width * image->depth) + 7) / 8) * image->height; - dwords = (src_bytes + 3) / 4; - bits = (u32*)(image->data); - - while(dwords >= 8) { - radeon_fifo_wait(rinfo, 8); -#if BITS_PER_LONG == 64 - __raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0); - __raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2); - __raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4); - __raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6); - bits += 8; -#else - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7); -#endif - dwords -= 8; - } - while(dwords--) { - radeon_fifo_wait(rinfo, 1); - __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0); - } -} - void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image) { struct radeonfb_info *rinfo = info->par; - u32 fg, bg; - - WARN_ON(rinfo->gfx_mode); - if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode) - return; - if (!image->width || !image->height) + if (info->state != FBINFO_STATE_RUNNING) return; - - /* We only do 1 bpp color expansion for now */ - if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) - goto fallback; - - /* Fallback if running out of the screen. We may do clipping - * in the future */ - if ((image->dx + image->width) > info->var.xres_virtual || - (image->dy + image->height) > info->var.yres_virtual) - goto fallback; - - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) { - fg = ((u32*)(info->pseudo_palette))[image->fg_color]; - bg = ((u32*)(info->pseudo_palette))[image->bg_color]; - } else { - fg = image->fg_color; - bg = image->bg_color; - } - - radeonfb_prim_imageblit(rinfo, image, fg, bg); - return; - - fallback: - radeon_engine_idle(rinfo); + radeon_engine_idle(); cfb_imageblit(info, image); } @@ -286,8 +185,7 @@ int radeonfb_sync(struct fb_info *info) if (info->state != FBINFO_STATE_RUNNING) return 0; - - radeon_engine_idle(rinfo); + radeon_engine_idle(); return 0; } @@ -363,10 +261,9 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo) /* disable 3D engine */ OUTREG(RB3D_CNTL, 0); - rinfo->fifo_free = 0; radeonfb_engine_reset(rinfo); - radeon_fifo_wait(rinfo, 1); + radeon_fifo_wait (1); if (IS_R300_VARIANT(rinfo)) { OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | RB2D_DC_AUTOFLUSH_ENABLE | @@ -380,7 +277,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo) OUTREG(RB2D_DSTCACHE_MODE, 0); } - radeon_fifo_wait(rinfo, 3); + radeon_fifo_wait (3); /* We re-read MC_FB_LOCATION from card as it can have been * modified by XFree drivers (ouch !) */ @@ -391,57 +288,41 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo) OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); - radeon_fifo_wait(rinfo, 1); -#ifdef __BIG_ENDIAN + radeon_fifo_wait (1); +#if defined(__BIG_ENDIAN) OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); #else OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); #endif - radeon_fifo_wait(rinfo, 2); + radeon_fifo_wait (2); OUTREG(DEFAULT_SC_TOP_LEFT, 0); OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX)); - /* set default DP_GUI_MASTER_CNTL */ temp = radeon_get_dstbpp(rinfo->depth); - rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); + rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); - rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base | - GMC_BRUSH_SOLID_COLOR | - GMC_SRC_DATATYPE_COLOR; - radeon_fifo_wait(rinfo, 1); - OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache); + radeon_fifo_wait (1); + OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | + GMC_BRUSH_SOLID_COLOR | + GMC_SRC_DATATYPE_COLOR)); + radeon_fifo_wait (7); /* clear line drawing regs */ - radeon_fifo_wait(rinfo, 2); OUTREG(DST_LINE_START, 0); OUTREG(DST_LINE_END, 0); - /* set brush and source color regs */ - rinfo->dp_brush_fg_cache = 0xffffffff; - rinfo->dp_brush_bg_cache = 0x00000000; - rinfo->dp_src_fg_cache = 0xffffffff; - rinfo->dp_src_bg_cache = 0x00000000; - radeon_fifo_wait(rinfo, 4); - OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache); - OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache); - OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache); - OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache); - - /* Default direction */ - rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM; - radeon_fifo_wait(rinfo, 1); - OUTREG(DP_CNTL, rinfo->dp_cntl_cache); + /* set brush color regs */ + OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); + + /* set source color regs */ + OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(DP_SRC_BKGD_CLR, 0x00000000); /* default write mask */ - radeon_fifo_wait(rinfo, 1); OUTREG(DP_WRITE_MSK, 0xffffffff); - /* Default to no swapping of host data */ - radeon_fifo_wait(rinfo, 1); - OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE); - - /* Make sure it's settled */ - radeon_engine_idle(rinfo); + radeon_engine_idle (); } diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c index f343ba83f0ae..1a056adb61c8 100644 --- a/drivers/video/aty/radeon_backlight.c +++ b/drivers/video/aty/radeon_backlight.c @@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd) level = bd->props.brightness; del_timer_sync(&rinfo->lvds_timer); - radeon_engine_idle(rinfo); + radeon_engine_idle(); lvds_gen_cntl = INREG(LVDS_GEN_CNTL); if (level > 0) { diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c index 9a5821c65ebf..d0f1a7fc2c9d 100644 --- a/drivers/video/aty/radeon_base.c +++ b/drivers/video/aty/radeon_base.c @@ -852,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var, if (rinfo->asleep) return 0; + radeon_fifo_wait(2); OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) * var->bits_per_pixel / 8) & ~7); return 0; @@ -881,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, if (rc) return rc; + radeon_fifo_wait(2); if (value & 0x01) { tmp = INREG(LVDS_GEN_CNTL); @@ -938,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) if (rinfo->lock_blank) return 0; - radeon_engine_idle(rinfo); + radeon_engine_idle(); val = INREG(CRTC_EXT_CNTL); val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | @@ -1046,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info) if (rinfo->asleep) return 0; - + return radeon_screen_blank(rinfo, blank, 0); } @@ -1072,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, pindex = regno; if (!rinfo->asleep) { + radeon_fifo_wait(9); + if (rinfo->bpp == 16) { pindex = regno * 8; @@ -1240,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg { int i; + radeon_fifo_wait(20); + /* Workaround from XFree */ if (rinfo->is_mobility) { /* A temporal workaround for the occational blanking on certain laptop @@ -1335,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data) { struct radeonfb_info *rinfo = (struct radeonfb_info *)data; - radeon_engine_idle(rinfo); + radeon_engine_idle(); OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); } @@ -1353,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, if (nomodeset) return; - radeon_engine_idle(rinfo); - if (!regs_only) radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); + radeon_fifo_wait(31); for (i=0; i<10; i++) OUTREG(common_regs[i].reg, common_regs[i].val); @@ -1385,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, radeon_write_pll_regs(rinfo, mode); if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { + radeon_fifo_wait(10); OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); @@ -1399,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, if (!regs_only) radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); + radeon_fifo_wait(2); OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); return; @@ -1549,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info) /* We always want engine to be idle on a mode switch, even * if we won't actually change the mode */ - radeon_engine_idle(rinfo); + radeon_engine_idle(); hSyncStart = mode->xres + mode->right_margin; hSyncEnd = hSyncStart + mode->hsync_len; @@ -1844,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info) return 0; } + static struct fb_ops radeonfb_ops = { .owner = THIS_MODULE, .fb_check_var = radeonfb_check_var, @@ -1867,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo) info->par = rinfo; info->pseudo_palette = rinfo->pseudo_palette; info->flags = FBINFO_DEFAULT - | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_XPAN @@ -1999,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) u32 tom = INREG(NB_TOM); tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); + radeon_fifo_wait(6); OUTREG(MC_FB_LOCATION, tom); OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c index 3df5015f1d13..675abdafc2d8 100644 --- a/drivers/video/aty/radeon_pm.c +++ b/drivers/video/aty/radeon_pm.c @@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { /* Make sure engine is reset */ - radeon_engine_idle(rinfo); + radeon_engine_idle(); radeonfb_engine_reset(rinfo); - radeon_engine_idle(rinfo); + radeon_engine_idle(); } /* Blank display and LCD */ @@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev) rinfo->asleep = 0; } else - radeon_engine_idle(rinfo); + radeon_engine_idle(); /* Restore display & engine */ radeon_write_mode (rinfo, &rinfo->state, 1); diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h index ea0b5b47acaf..3ea1b00fdd22 100644 --- a/drivers/video/aty/radeonfb.h +++ b/drivers/video/aty/radeonfb.h @@ -336,15 +336,7 @@ struct radeonfb_info { int mon2_type; u8 *mon2_EDID; - /* accel bits */ - u32 dp_gui_mc_base; - u32 dp_gui_mc_cache; - u32 dp_cntl_cache; - u32 dp_brush_fg_cache; - u32 dp_brush_bg_cache; - u32 dp_src_fg_cache; - u32 dp_src_bg_cache; - u32 fifo_free; + u32 dp_gui_master_cntl; struct pll_info pll; @@ -356,7 +348,6 @@ struct radeonfb_info { int lock_blank; int dynclk; int no_schedule; - int gfx_mode; enum radeon_pm_mode pm_mode; reinit_function_ptr reinit_func; @@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) #define INREG16(addr) readw((rinfo->mmio_base)+addr) #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) - -#ifdef CONFIG_PPC -#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); }) -#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0) -#else #define INREG(addr) readl((rinfo->mmio_base)+addr) #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) -#endif static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) @@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth) * 2D Engine helper routines */ -extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries); +static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) +{ + int i; + + for (i=0; i<2000000; i++) { + if ((INREG(RBBM_STATUS) & 0x7f) >= entries) + return; + udelay(1); + } + printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); +} static inline void radeon_engine_flush (struct radeonfb_info *rinfo) { @@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) /* Ensure FIFO is empty, ie, make sure the flush commands * has reached the cache */ - radeon_fifo_update_and_wait(rinfo, 64); + _radeon_fifo_wait (rinfo, 64); /* Wait for the flush to complete */ for (i=0; i < 2000000; i++) { @@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) } -static inline void radeon_engine_idle(struct radeonfb_info *rinfo) +static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) { int i; /* ensure FIFO is empty before waiting for idle */ - radeon_fifo_update_and_wait (rinfo, 64); + _radeon_fifo_wait (rinfo, 64); for (i=0; i<2000000; i++) { if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { @@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo) } +#define radeon_engine_idle() _radeon_engine_idle(rinfo) +#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) @@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image); extern int radeonfb_sync(struct fb_info *info); extern void radeonfb_engine_init (struct radeonfb_info *rinfo); extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); -extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo); /* Other functions */ extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); diff --git a/drivers/video/backlight/corgi_lcd.c b/drivers/video/backlight/corgi_lcd.c index 2afd47eefe74..f8a4bb20f41a 100644 --- a/drivers/video/backlight/corgi_lcd.c +++ b/drivers/video/backlight/corgi_lcd.c @@ -439,7 +439,7 @@ static int corgi_bl_update_status(struct backlight_device *bd) return corgi_bl_set_intensity(lcd, intensity); } -void corgibl_limit_intensity(int limit) +void corgi_lcd_limit_intensity(int limit) { if (limit) corgibl_flags |= CORGIBL_BATTLOW; @@ -448,7 +448,7 @@ void corgibl_limit_intensity(int limit) backlight_update_status(the_corgi_lcd->bl_dev); } -EXPORT_SYMBOL(corgibl_limit_intensity); +EXPORT_SYMBOL(corgi_lcd_limit_intensity); static struct backlight_ops corgi_bl_ops = { .get_brightness = corgi_bl_get_intensity, diff --git a/drivers/video/backlight/da903x.c b/drivers/video/backlight/da903x.c index 242c38250166..93bb4340cc64 100644 --- a/drivers/video/backlight/da903x.c +++ b/drivers/video/backlight/da903x.c @@ -119,6 +119,7 @@ static int da903x_backlight_probe(struct platform_device *pdev) default: dev_err(&pdev->dev, "invalid backlight device ID(%d)\n", pdev->id); + kfree(data); return -EINVAL; } @@ -130,6 +131,7 @@ static int da903x_backlight_probe(struct platform_device *pdev) data, &da903x_backlight_ops); if (IS_ERR(bl)) { dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); return PTR_ERR(bl); } diff --git a/drivers/video/backlight/lcd.c b/drivers/video/backlight/lcd.c index 8e1731d3b228..680e57b616cd 100644 --- a/drivers/video/backlight/lcd.c +++ b/drivers/video/backlight/lcd.c @@ -42,10 +42,13 @@ static int fb_notifier_callback(struct notifier_block *self, mutex_lock(&ld->ops_lock); if (!ld->ops->check_fb || ld->ops->check_fb(ld, evdata->info)) { - if (event == FB_EVENT_BLANK) - ld->ops->set_power(ld, *(int *)evdata->data); - else - ld->ops->set_mode(ld, evdata->data); + if (event == FB_EVENT_BLANK) { + if (ld->ops->set_power) + ld->ops->set_power(ld, *(int *)evdata->data); + } else { + if (ld->ops->set_mode) + ld->ops->set_mode(ld, evdata->data); + } } mutex_unlock(&ld->ops_lock); return 0; diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c index 048b139f0e50..a2aa6ddffbe2 100644 --- a/drivers/video/cirrusfb.c +++ b/drivers/video/cirrusfb.c @@ -2049,7 +2049,7 @@ static void cirrusfb_pci_unmap(struct fb_info *info) #endif /* CONFIG_PCI */ #ifdef CONFIG_ZORRO -static void __devexit cirrusfb_zorro_unmap(struct fb_info *info) +static void cirrusfb_zorro_unmap(struct fb_info *info) { struct cirrusfb_info *cinfo = info->par; struct zorro_dev *zdev = to_zorro_dev(info->device); @@ -2462,8 +2462,7 @@ static int __init cirrusfb_init(void) #ifndef MODULE static int __init cirrusfb_setup(char *options) { - char *this_opt, s[32]; - int i; + char *this_opt; DPRINTK("ENTER\n"); diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index 64b3d30027b8..0b2adefe9e3d 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c @@ -2118,7 +2118,7 @@ static void fbcon_bmove_rec(struct vc_data *vc, struct display *p, int sy, int s height, width); } -static __inline__ void updatescrollmode(struct display *p, +static void updatescrollmode(struct display *p, struct fb_info *info, struct vc_data *vc) { @@ -2389,16 +2389,13 @@ static int fbcon_blank(struct vc_data *vc, int blank, int mode_switch) if (!fbcon_is_inactive(vc, info)) { if (ops->blank_state != blank) { - int ret = 1; - ops->blank_state = blank; fbcon_cursor(vc, blank ? CM_ERASE : CM_DRAW); ops->cursor_flash = (!blank); - if (info->fbops->fb_blank) - ret = info->fbops->fb_blank(blank, info); - if (ret) - fbcon_generic_blank(vc, info, blank); + if (!(info->flags & FBINFO_MISC_USEREVENT)) + if (fb_blank(info, blank)) + fbcon_generic_blank(vc, info, blank); } if (!blank) @@ -3534,12 +3531,18 @@ static void fbcon_exit(void) softback_buf = 0UL; for (i = 0; i < FB_MAX; i++) { + int pending; + mapped = 0; info = registered_fb[i]; if (info == NULL) continue; + pending = cancel_work_sync(&info->queue); + DPRINTK("fbcon: %s pending work\n", (pending ? "canceled" : + "no")); + for (j = first_fb_vc; j <= last_fb_vc; j++) { if (con2fb_map[j] == i) mapped = 1; diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index cd5f20da738a..3c65b0d67617 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -230,7 +230,7 @@ static void fb_set_logo_directpalette(struct fb_info *info, greenshift = info->var.green.offset; blueshift = info->var.blue.offset; - for (i = 32; i < logo->clutsize; i++) + for (i = 32; i < 32 + logo->clutsize; i++) palette[i] = i << redshift | i << greenshift | i << blueshift; } @@ -1002,13 +1002,9 @@ fb_blank(struct fb_info *info, int blank) return ret; } -static long -fb_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) +static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) { - struct inode *inode = file->f_path.dentry->d_inode; - int fbidx = iminor(inode); - struct fb_info *info; struct fb_ops *fb; struct fb_var_screeninfo var; struct fb_fix_screeninfo fix; @@ -1018,14 +1014,10 @@ fb_ioctl(struct file *file, unsigned int cmd, void __user *argp = (void __user *)arg; long ret = 0; - info = registered_fb[fbidx]; - mutex_lock(&info->lock); fb = info->fbops; - - if (!fb) { - mutex_unlock(&info->lock); + if (!fb) return -ENODEV; - } + switch (cmd) { case FBIOGET_VSCREENINFO: ret = copy_to_user(argp, &info->var, @@ -1126,6 +1118,21 @@ fb_ioctl(struct file *file, unsigned int cmd, else ret = fb->fb_ioctl(info, cmd, arg); } + return ret; +} + +static long fb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +__acquires(&info->lock) +__releases(&info->lock) +{ + struct inode *inode = file->f_path.dentry->d_inode; + int fbidx = iminor(inode); + struct fb_info *info; + long ret; + + info = registered_fb[fbidx]; + mutex_lock(&info->lock); + ret = do_fb_ioctl(info, cmd, arg); mutex_unlock(&info->lock); return ret; } @@ -1157,8 +1164,8 @@ struct fb_cmap32 { compat_caddr_t transp; }; -static int fb_getput_cmap(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static int fb_getput_cmap(struct fb_info *info, unsigned int cmd, + unsigned long arg) { struct fb_cmap_user __user *cmap; struct fb_cmap32 __user *cmap32; @@ -1181,7 +1188,7 @@ static int fb_getput_cmap(struct inode *inode, struct file *file, put_user(compat_ptr(data), &cmap->transp)) return -EFAULT; - err = fb_ioctl(file, cmd, (unsigned long) cmap); + err = do_fb_ioctl(info, cmd, (unsigned long) cmap); if (!err) { if (copy_in_user(&cmap32->start, @@ -1223,8 +1230,8 @@ static int do_fscreeninfo_to_user(struct fb_fix_screeninfo *fix, return err; } -static int fb_get_fscreeninfo(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static int fb_get_fscreeninfo(struct fb_info *info, unsigned int cmd, + unsigned long arg) { mm_segment_t old_fs; struct fb_fix_screeninfo fix; @@ -1235,7 +1242,7 @@ static int fb_get_fscreeninfo(struct inode *inode, struct file *file, old_fs = get_fs(); set_fs(KERNEL_DS); - err = fb_ioctl(file, cmd, (unsigned long) &fix); + err = do_fb_ioctl(info, cmd, (unsigned long) &fix); set_fs(old_fs); if (!err) @@ -1244,8 +1251,10 @@ static int fb_get_fscreeninfo(struct inode *inode, struct file *file, return err; } -static long -fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +static long fb_compat_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +__acquires(&info->lock) +__releases(&info->lock) { struct inode *inode = file->f_path.dentry->d_inode; int fbidx = iminor(inode); @@ -1262,16 +1271,16 @@ fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case FBIOPUT_CON2FBMAP: arg = (unsigned long) compat_ptr(arg); case FBIOBLANK: - ret = fb_ioctl(file, cmd, arg); + ret = do_fb_ioctl(info, cmd, arg); break; case FBIOGET_FSCREENINFO: - ret = fb_get_fscreeninfo(inode, file, cmd, arg); + ret = fb_get_fscreeninfo(info, cmd, arg); break; case FBIOGETCMAP: case FBIOPUTCMAP: - ret = fb_getput_cmap(inode, file, cmd, arg); + ret = fb_getput_cmap(info, cmd, arg); break; default: @@ -1286,6 +1295,8 @@ fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static int fb_mmap(struct file *file, struct vm_area_struct * vma) +__acquires(&info->lock) +__releases(&info->lock) { int fbidx = iminor(file->f_path.dentry->d_inode); struct fb_info *info = registered_fb[fbidx]; @@ -1339,6 +1350,8 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) static int fb_open(struct inode *inode, struct file *file) +__acquires(&info->lock) +__releases(&info->lock) { int fbidx = iminor(inode); struct fb_info *info; @@ -1374,6 +1387,8 @@ out: static int fb_release(struct inode *inode, struct file *file) +__acquires(&info->lock) +__releases(&info->lock) { struct fb_info * const info = file->private_data; diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c index b790ddff76f9..ee380d5f3410 100644 --- a/drivers/video/macfb.c +++ b/drivers/video/macfb.c @@ -164,7 +164,6 @@ static struct fb_var_screeninfo macfb_defined = { }; static struct fb_fix_screeninfo macfb_fix = { - .id = "Macintosh ", .type = FB_TYPE_PACKED_PIXELS, .accel = FB_ACCEL_NONE, }; @@ -760,22 +759,22 @@ static int __init macfb_init(void) switch(ndev->dr_hw) { case NUBUS_DRHW_APPLE_MDC: - strcat( macfb_fix.id, "Display Card" ); + strcpy(macfb_fix.id, "Mac Disp. Card"); macfb_setpalette = mdc_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; break; case NUBUS_DRHW_APPLE_TFB: - strcat( macfb_fix.id, "Toby" ); + strcpy(macfb_fix.id, "Toby"); macfb_setpalette = toby_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; break; case NUBUS_DRHW_APPLE_JET: - strcat( macfb_fix.id, "Jet"); + strcpy(macfb_fix.id, "Jet"); macfb_setpalette = jet_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; break; default: - strcat( macfb_fix.id, "Generic NuBus" ); + strcpy(macfb_fix.id, "Generic NuBus"); break; } } @@ -786,21 +785,11 @@ static int __init macfb_init(void) if (!video_is_nubus) switch( mac_bi_data.id ) { - /* These don't have onboard video. Eventually, we may - be able to write separate framebuffer drivers for - them (tobyfb.c, hiresfb.c, etc, etc) */ - case MAC_MODEL_II: - case MAC_MODEL_IIX: - case MAC_MODEL_IICX: - case MAC_MODEL_IIFX: - strcat( macfb_fix.id, "Generic NuBus" ); - break; - /* Valkyrie Quadras */ case MAC_MODEL_Q630: /* I'm not sure about this one */ case MAC_MODEL_P588: - strcat( macfb_fix.id, "Valkyrie built-in" ); + strcpy(macfb_fix.id, "Valkyrie"); macfb_setpalette = valkyrie_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; valkyrie_cmap_regs = ioremap(DAC_BASE, 0x1000); @@ -823,7 +812,7 @@ static int __init macfb_init(void) case MAC_MODEL_Q700: case MAC_MODEL_Q900: case MAC_MODEL_Q950: - strcat( macfb_fix.id, "DAFB built-in" ); + strcpy(macfb_fix.id, "DAFB"); macfb_setpalette = dafb_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; dafb_cmap_regs = ioremap(DAFB_BASE, 0x1000); @@ -831,7 +820,7 @@ static int __init macfb_init(void) /* LC II uses the V8 framebuffer */ case MAC_MODEL_LCII: - strcat( macfb_fix.id, "V8 built-in" ); + strcpy(macfb_fix.id, "V8"); macfb_setpalette = v8_brazil_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); @@ -843,7 +832,7 @@ static int __init macfb_init(void) case MAC_MODEL_IIVI: case MAC_MODEL_IIVX: case MAC_MODEL_P600: - strcat( macfb_fix.id, "Brazil built-in" ); + strcpy(macfb_fix.id, "Brazil"); macfb_setpalette = v8_brazil_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); @@ -860,7 +849,7 @@ static int __init macfb_init(void) case MAC_MODEL_P460: macfb_setpalette = v8_brazil_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; - strcat( macfb_fix.id, "Sonora built-in" ); + strcpy(macfb_fix.id, "Sonora"); v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); break; @@ -871,7 +860,7 @@ static int __init macfb_init(void) case MAC_MODEL_IISI: macfb_setpalette = rbv_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; - strcat( macfb_fix.id, "RBV built-in" ); + strcpy(macfb_fix.id, "RBV"); rbv_cmap_regs = ioremap(DAC_BASE, 0x1000); break; @@ -880,7 +869,7 @@ static int __init macfb_init(void) case MAC_MODEL_C660: macfb_setpalette = civic_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; - strcat( macfb_fix.id, "Civic built-in" ); + strcpy(macfb_fix.id, "Civic"); civic_cmap_regs = ioremap(CIVIC_BASE, 0x1000); break; @@ -901,7 +890,7 @@ static int __init macfb_init(void) v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); } - strcat( macfb_fix.id, "LC built-in" ); + strcpy(macfb_fix.id, "LC"); break; /* We think this may be like the LC II */ case MAC_MODEL_CCL: @@ -911,18 +900,18 @@ static int __init macfb_init(void) v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000); } - strcat( macfb_fix.id, "Color Classic built-in" ); + strcpy(macfb_fix.id, "Color Classic"); break; /* And we *do* mean "weirdos" */ case MAC_MODEL_TV: - strcat( macfb_fix.id, "Mac TV built-in" ); + strcpy(macfb_fix.id, "Mac TV"); break; /* These don't have colour, so no need to worry */ case MAC_MODEL_SE30: case MAC_MODEL_CLII: - strcat( macfb_fix.id, "Monochrome built-in" ); + strcpy(macfb_fix.id, "Monochrome"); break; /* Powerbooks are particularly difficult. Many of @@ -935,7 +924,7 @@ static int __init macfb_init(void) case MAC_MODEL_PB140: case MAC_MODEL_PB145: case MAC_MODEL_PB170: - strcat( macfb_fix.id, "DDC built-in" ); + strcpy(macfb_fix.id, "DDC"); break; /* Internal is GSC, External (if present) is ViSC */ @@ -945,13 +934,13 @@ static int __init macfb_init(void) case MAC_MODEL_PB180: case MAC_MODEL_PB210: case MAC_MODEL_PB230: - strcat( macfb_fix.id, "GSC built-in" ); + strcpy(macfb_fix.id, "GSC"); break; /* Internal is TIM, External is ViSC */ case MAC_MODEL_PB165C: case MAC_MODEL_PB180C: - strcat( macfb_fix.id, "TIM built-in" ); + strcpy(macfb_fix.id, "TIM"); break; /* Internal is CSC, External is Keystone+Ariel. */ @@ -963,12 +952,12 @@ static int __init macfb_init(void) case MAC_MODEL_PB280C: macfb_setpalette = csc_setpalette; macfb_defined.activate = FB_ACTIVATE_NOW; - strcat( macfb_fix.id, "CSC built-in" ); + strcpy(macfb_fix.id, "CSC"); csc_cmap_regs = ioremap(CSC_BASE, 0x1000); break; default: - strcat( macfb_fix.id, "Unknown/Unsupported built-in" ); + strcpy(macfb_fix.id, "Unknown"); break; } @@ -978,16 +967,23 @@ static int __init macfb_init(void) fb_info.pseudo_palette = pseudo_palette; fb_info.flags = FBINFO_DEFAULT; - fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0); + err = fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0); + if (err) + goto fail_unmap; err = register_framebuffer(&fb_info); - if (!err) - printk("fb%d: %s frame buffer device\n", - fb_info.node, fb_info.fix.id); - else { - iounmap(fb_info.screen_base); - iounmap_macfb(); - } + if (err) + goto fail_dealloc; + + printk("fb%d: %s frame buffer device\n", + fb_info.node, fb_info.fix.id); + return 0; + +fail_dealloc: + fb_dealloc_cmap(&fb_info.cmap); +fail_unmap: + iounmap(fb_info.screen_base); + iounmap_macfb(); return err; } diff --git a/drivers/video/mb862xx/Makefile b/drivers/video/mb862xx/Makefile new file mode 100644 index 000000000000..07664814bb1d --- /dev/null +++ b/drivers/video/mb862xx/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the MB862xx framebuffer driver +# + +obj-$(CONFIG_FB_MB862XX) := mb862xxfb.o diff --git a/drivers/video/mb862xx/mb862xx_reg.h b/drivers/video/mb862xx/mb862xx_reg.h new file mode 100644 index 000000000000..2ba65e118500 --- /dev/null +++ b/drivers/video/mb862xx/mb862xx_reg.h @@ -0,0 +1,138 @@ +/* + * Fujitsu MB862xx Graphics Controller Registers/Bits + */ + +#ifndef _MB862XX_REG_H +#define _MB862XX_REG_H + +#ifdef MB862XX_MMIO_BOTTOM +#define MB862XX_MMIO_BASE 0x03fc0000 +#else +#define MB862XX_MMIO_BASE 0x01fc0000 +#endif +#define MB862XX_I2C_BASE 0x0000c000 +#define MB862XX_DISP_BASE 0x00010000 +#define MB862XX_CAP_BASE 0x00018000 +#define MB862XX_DRAW_BASE 0x00030000 +#define MB862XX_GEO_BASE 0x00038000 +#define MB862XX_PIO_BASE 0x00038000 +#define MB862XX_MMIO_SIZE 0x40000 + +/* Host interface/pio registers */ +#define GC_IST 0x00000020 +#define GC_IMASK 0x00000024 +#define GC_SRST 0x0000002c +#define GC_CCF 0x00000038 +#define GC_CID 0x000000f0 +#define GC_REVISION 0x00000084 + +#define GC_CCF_CGE_100 0x00000000 +#define GC_CCF_CGE_133 0x00040000 +#define GC_CCF_CGE_166 0x00080000 +#define GC_CCF_COT_100 0x00000000 +#define GC_CCF_COT_133 0x00010000 +#define GC_CID_CNAME_MSK 0x0000ff00 +#define GC_CID_VERSION_MSK 0x000000ff + +/* define enabled interrupts hereby */ +#define GC_INT_EN 0x00000000 + +/* Memory interface mode register */ +#define GC_MMR 0x0000fffc + +/* Display Controller registers */ +#define GC_DCM0 0x00000000 +#define GC_HTP 0x00000004 +#define GC_HDB_HDP 0x00000008 +#define GC_VSW_HSW_HSP 0x0000000c +#define GC_VTR 0x00000010 +#define GC_VDP_VSP 0x00000014 +#define GC_WY_WX 0x00000018 +#define GC_WH_WW 0x0000001c +#define GC_L0M 0x00000020 +#define GC_L0OA0 0x00000024 +#define GC_L0DA0 0x00000028 +#define GC_L0DY_L0DX 0x0000002c +#define GC_DCM1 0x00000100 +#define GC_L0EM 0x00000110 +#define GC_L0WY_L0WX 0x00000114 +#define GC_L0WH_L0WW 0x00000118 +#define GC_DCM2 0x00000104 +#define GC_DCM3 0x00000108 +#define GC_CPM_CUTC 0x000000a0 +#define GC_CUOA0 0x000000a4 +#define GC_CUY0_CUX0 0x000000a8 +#define GC_CUOA1 0x000000ac +#define GC_CUY1_CUX1 0x000000b0 +#define GC_L0PAL0 0x00000400 + +#define GC_CPM_CEN0 0x00100000 +#define GC_CPM_CEN1 0x00200000 + +#define GC_DCM01_ESY 0x00000004 +#define GC_DCM01_SC 0x00003f00 +#define GC_DCM01_RESV 0x00004000 +#define GC_DCM01_CKS 0x00008000 +#define GC_DCM01_L0E 0x00010000 +#define GC_DCM01_DEN 0x80000000 +#define GC_L0M_L0C_8 0x00000000 +#define GC_L0M_L0C_16 0x80000000 +#define GC_L0EM_L0EC_24 0x40000000 +#define GC_L0M_L0W_UNIT 64 + +#define GC_DISP_REFCLK_400 400 + +/* Carmine specific */ +#define MB86297_DRAW_BASE 0x00020000 +#define MB86297_DISP0_BASE 0x00100000 +#define MB86297_DISP1_BASE 0x00140000 +#define MB86297_WRBACK_BASE 0x00180000 +#define MB86297_CAP0_BASE 0x00200000 +#define MB86297_CAP1_BASE 0x00280000 +#define MB86297_DRAMCTRL_BASE 0x00300000 +#define MB86297_CTRL_BASE 0x00400000 +#define MB86297_I2C_BASE 0x00500000 + +#define GC_CTRL_STATUS 0x00000000 +#define GC_CTRL_INT_MASK 0x00000004 +#define GC_CTRL_CLK_ENABLE 0x0000000c +#define GC_CTRL_SOFT_RST 0x00000010 + +#define GC_CTRL_CLK_EN_DRAM 0x00000001 +#define GC_CTRL_CLK_EN_2D3D 0x00000002 +#define GC_CTRL_CLK_EN_DISP0 0x00000020 +#define GC_CTRL_CLK_EN_DISP1 0x00000040 + +#define GC_2D3D_REV 0x000004b4 +#define GC_RE_REVISION 0x24240200 + +/* define enabled interrupts hereby */ +#define GC_CARMINE_INT_EN 0x00000004 + +/* DRAM controller */ +#define GC_DCTL_MODE_ADD 0x00000000 +#define GC_DCTL_SETTIME1_EMODE 0x00000004 +#define GC_DCTL_REFRESH_SETTIME2 0x00000008 +#define GC_DCTL_RSV0_STATES 0x0000000C +#define GC_DCTL_RSV2_RSV1 0x00000010 +#define GC_DCTL_DDRIF2_DDRIF1 0x00000014 +#define GC_DCTL_IOCONT1_IOCONT0 0x00000024 + +#define GC_DCTL_STATES_MSK 0x0000000f +#define GC_DCTL_INIT_WAIT_CNT 3000 +#define GC_DCTL_INIT_WAIT_INTERVAL 1 + +/* DRAM ctrl values for Carmine PCI Eval. board */ +#define GC_EVB_DCTL_MODE_ADD 0x012105c3 +#define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3 +#define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000 +#define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22 +#define GC_EVB_DCTL_RSV0_STATES 0x00200003 +#define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002 +#define GC_EVB_DCTL_RSV2_RSV1 0x0000000f +#define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646 +#define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555 + +#define GC_DISP_REFCLK_533 533 + +#endif diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c new file mode 100644 index 000000000000..fb64234a3825 --- /dev/null +++ b/drivers/video/mb862xx/mb862xxfb.c @@ -0,0 +1,1061 @@ +/* + * drivers/mb862xx/mb862xxfb.c + * + * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver + * + * (C) 2008 Anatolij Gustschin + * DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#if defined(CONFIG_PPC_OF) +#include +#endif +#include "mb862xxfb.h" +#include "mb862xx_reg.h" + +#define NR_PALETTE 256 +#define MB862XX_MEM_SIZE 0x1000000 +#define CORALP_MEM_SIZE 0x4000000 +#define CARMINE_MEM_SIZE 0x8000000 +#define DRV_NAME "mb862xxfb" + +#if defined(CONFIG_LWMON5) +static struct mb862xx_gc_mode lwmon5_gc_mode = { + /* Mode for Sharp LQ104V1DG61 TFT LCD Panel */ + { "640x480", 60, 640, 480, 40000, 48, 16, 32, 11, 96, 2, 0, 0, 0 }, + /* 16 bits/pixel, 32MB, 100MHz, SDRAM memory mode value */ + 16, 0x2000000, GC_CCF_COT_100, 0x414fb7f2 +}; +#endif + +#if defined(CONFIG_SOCRATES) +static struct mb862xx_gc_mode socrates_gc_mode = { + /* Mode for Prime View PM070WL4 TFT LCD Panel */ + { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 }, + /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */ + 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63 +}; +#endif + +/* Helpers */ +static inline int h_total(struct fb_var_screeninfo *var) +{ + return var->xres + var->left_margin + + var->right_margin + var->hsync_len; +} + +static inline int v_total(struct fb_var_screeninfo *var) +{ + return var->yres + var->upper_margin + + var->lower_margin + var->vsync_len; +} + +static inline int hsp(struct fb_var_screeninfo *var) +{ + return var->xres + var->right_margin - 1; +} + +static inline int vsp(struct fb_var_screeninfo *var) +{ + return var->yres + var->lower_margin - 1; +} + +static inline int d_pitch(struct fb_var_screeninfo *var) +{ + return var->xres * var->bits_per_pixel / 8; +} + +static inline unsigned int chan_to_field(unsigned int chan, + struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mb862xxfb_setcolreg(unsigned regno, + unsigned red, unsigned green, unsigned blue, + unsigned transp, struct fb_info *info) +{ + struct mb862xxfb_par *par = info->par; + unsigned int val; + + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + if (regno < 16) { + val = chan_to_field(red, &info->var.red); + val |= chan_to_field(green, &info->var.green); + val |= chan_to_field(blue, &info->var.blue); + par->pseudo_palette[regno] = val; + } + break; + case FB_VISUAL_PSEUDOCOLOR: + if (regno < 256) { + val = (red >> 8) << 16; + val |= (green >> 8) << 8; + val |= blue >> 8; + outreg(disp, GC_L0PAL0 + (regno * 4), val); + } + break; + default: + return 1; /* unsupported type */ + } + return 0; +} + +static int mb862xxfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *fbi) +{ + unsigned long tmp; + + if (fbi->dev) + dev_dbg(fbi->dev, "%s\n", __func__); + + /* check if these values fit into the registers */ + if (var->hsync_len > 255 || var->vsync_len > 255) + return -EINVAL; + + if ((var->xres + var->right_margin) >= 4096) + return -EINVAL; + + if ((var->yres + var->lower_margin) > 4096) + return -EINVAL; + + if (h_total(var) > 4096 || v_total(var) > 4096) + return -EINVAL; + + if (var->xres_virtual > 4096 || var->yres_virtual > 4096) + return -EINVAL; + + if (var->bits_per_pixel <= 8) + var->bits_per_pixel = 8; + else if (var->bits_per_pixel <= 16) + var->bits_per_pixel = 16; + else if (var->bits_per_pixel <= 32) + var->bits_per_pixel = 32; + + /* + * can cope with 8,16 or 24/32bpp if resulting + * pitch is divisible by 64 without remainder + */ + if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) { + int r; + + var->bits_per_pixel = 0; + do { + var->bits_per_pixel += 8; + r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT; + } while (r && var->bits_per_pixel <= 32); + + if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) + return -EINVAL; + } + + /* line length is going to be 128 bit aligned */ + tmp = (var->xres * var->bits_per_pixel) / 8; + if ((tmp & 15) != 0) + return -EINVAL; + + /* set r/g/b positions and validate bpp */ + switch (var->bits_per_pixel) { + case 8: + var->red.length = var->bits_per_pixel; + var->green.length = var->bits_per_pixel; + var->blue.length = var->bits_per_pixel; + var->red.offset = 0; + var->green.offset = 0; + var->blue.offset = 0; + var->transp.length = 0; + break; + case 16: + var->red.length = 5; + var->green.length = 5; + var->blue.length = 5; + var->red.offset = 10; + var->green.offset = 5; + var->blue.offset = 0; + var->transp.length = 0; + break; + case 24: + case 32: + var->transp.length = 8; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.offset = 24; + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * set display parameters + */ +static int mb862xxfb_set_par(struct fb_info *fbi) +{ + struct mb862xxfb_par *par = fbi->par; + unsigned long reg, sc; + + dev_dbg(par->dev, "%s\n", __func__); + + if (par->pre_init) + return 0; + + /* disp off */ + reg = inreg(disp, GC_DCM1); + reg &= ~GC_DCM01_DEN; + outreg(disp, GC_DCM1, reg); + + /* set display reference clock div. */ + sc = par->refclk / (1000000 / fbi->var.pixclock) - 1; + reg = inreg(disp, GC_DCM1); + reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC); + reg |= sc << 8; + outreg(disp, GC_DCM1, reg); + dev_dbg(par->dev, "SC 0x%lx\n", sc); + + /* disp dimension, format */ + reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT, + (fbi->var.yres - 1)); + if (fbi->var.bits_per_pixel == 16) + reg |= GC_L0M_L0C_16; + outreg(disp, GC_L0M, reg); + + if (fbi->var.bits_per_pixel == 32) { + reg = inreg(disp, GC_L0EM); + outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24); + } + outreg(disp, GC_WY_WX, 0); + reg = pack(fbi->var.yres - 1, fbi->var.xres); + outreg(disp, GC_WH_WW, reg); + outreg(disp, GC_L0OA0, 0); + outreg(disp, GC_L0DA0, 0); + outreg(disp, GC_L0DY_L0DX, 0); + outreg(disp, GC_L0WY_L0WX, 0); + outreg(disp, GC_L0WH_L0WW, reg); + + /* both HW-cursors off */ + reg = inreg(disp, GC_CPM_CUTC); + reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1); + outreg(disp, GC_CPM_CUTC, reg); + + /* timings */ + reg = pack(fbi->var.xres - 1, fbi->var.xres - 1); + outreg(disp, GC_HDB_HDP, reg); + reg = pack((fbi->var.yres - 1), vsp(&fbi->var)); + outreg(disp, GC_VDP_VSP, reg); + reg = ((fbi->var.vsync_len - 1) << 24) | + pack((fbi->var.hsync_len - 1), hsp(&fbi->var)); + outreg(disp, GC_VSW_HSW_HSP, reg); + outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0)); + outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0)); + + /* display on */ + reg = inreg(disp, GC_DCM1); + reg |= GC_DCM01_DEN | GC_DCM01_L0E; + reg &= ~GC_DCM01_ESY; + outreg(disp, GC_DCM1, reg); + return 0; +} + +static int mb862xxfb_pan(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct mb862xxfb_par *par = info->par; + unsigned long reg; + + reg = pack(var->yoffset, var->xoffset); + outreg(disp, GC_L0WY_L0WX, reg); + + reg = pack(var->yres_virtual, var->xres_virtual); + outreg(disp, GC_L0WH_L0WW, reg); + return 0; +} + +static int mb862xxfb_blank(int mode, struct fb_info *fbi) +{ + struct mb862xxfb_par *par = fbi->par; + unsigned long reg; + + dev_dbg(fbi->dev, "blank mode=%d\n", mode); + + switch (mode) { + case FB_BLANK_POWERDOWN: + reg = inreg(disp, GC_DCM1); + reg &= ~GC_DCM01_DEN; + outreg(disp, GC_DCM1, reg); + break; + case FB_BLANK_UNBLANK: + reg = inreg(disp, GC_DCM1); + reg |= GC_DCM01_DEN; + outreg(disp, GC_DCM1, reg); + break; + case FB_BLANK_NORMAL: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + default: + return 1; + } + return 0; +} + +/* framebuffer ops */ +static struct fb_ops mb862xxfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mb862xxfb_check_var, + .fb_set_par = mb862xxfb_set_par, + .fb_setcolreg = mb862xxfb_setcolreg, + .fb_blank = mb862xxfb_blank, + .fb_pan_display = mb862xxfb_pan, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +/* initialize fb_info data */ +static int mb862xxfb_init_fbinfo(struct fb_info *fbi) +{ + struct mb862xxfb_par *par = fbi->par; + struct mb862xx_gc_mode *mode = par->gc_mode; + unsigned long reg; + + fbi->fbops = &mb862xxfb_ops; + fbi->pseudo_palette = par->pseudo_palette; + fbi->screen_base = par->fb_base; + fbi->screen_size = par->mapped_vram; + + strcpy(fbi->fix.id, DRV_NAME); + fbi->fix.smem_start = (unsigned long)par->fb_base_phys; + fbi->fix.smem_len = par->mapped_vram; + fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys; + fbi->fix.mmio_len = par->mmio_len; + fbi->fix.accel = FB_ACCEL_NONE; + fbi->fix.type = FB_TYPE_PACKED_PIXELS; + fbi->fix.type_aux = 0; + fbi->fix.xpanstep = 1; + fbi->fix.ypanstep = 1; + fbi->fix.ywrapstep = 0; + + reg = inreg(disp, GC_DCM1); + if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) { + /* get the disp mode from active display cfg */ + unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1; + unsigned long hsp, vsp, ht, vt; + + dev_dbg(par->dev, "using bootloader's disp. mode\n"); + fbi->var.pixclock = (sc * 1000000) / par->refclk; + fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1; + reg = inreg(disp, GC_VDP_VSP); + fbi->var.yres = ((reg >> 16) & 0x0fff) + 1; + vsp = (reg & 0x0fff) + 1; + fbi->var.xres_virtual = fbi->var.xres; + fbi->var.yres_virtual = fbi->var.yres; + reg = inreg(disp, GC_L0EM); + if (reg & GC_L0EM_L0EC_24) { + fbi->var.bits_per_pixel = 32; + } else { + reg = inreg(disp, GC_L0M); + if (reg & GC_L0M_L0C_16) + fbi->var.bits_per_pixel = 16; + else + fbi->var.bits_per_pixel = 8; + } + reg = inreg(disp, GC_VSW_HSW_HSP); + fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1; + fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1; + hsp = (reg & 0xffff) + 1; + ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1; + fbi->var.right_margin = hsp - fbi->var.xres; + fbi->var.left_margin = ht - hsp - fbi->var.hsync_len; + vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1; + fbi->var.lower_margin = vsp - fbi->var.yres; + fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len; + } else if (mode) { + dev_dbg(par->dev, "using supplied mode\n"); + fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode); + fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8; + } else { + int ret; + + ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60", + NULL, 0, NULL, 16); + if (ret == 0 || ret == 4) { + dev_err(par->dev, + "failed to get initial mode\n"); + return -EINVAL; + } + } + + fbi->var.xoffset = 0; + fbi->var.yoffset = 0; + fbi->var.grayscale = 0; + fbi->var.nonstd = 0; + fbi->var.height = -1; + fbi->var.width = -1; + fbi->var.accel_flags = 0; + fbi->var.vmode = FB_VMODE_NONINTERLACED; + fbi->var.activate = FB_ACTIVATE_NOW; + fbi->flags = FBINFO_DEFAULT | +#ifdef __BIG_ENDIAN + FBINFO_FOREIGN_ENDIAN | +#endif + FBINFO_HWACCEL_XPAN | + FBINFO_HWACCEL_YPAN; + + /* check and possibly fix bpp */ + if ((fbi->fbops->fb_check_var)(&fbi->var, fbi)) + dev_err(par->dev, "check_var() failed on initial setup?\n"); + + fbi->fix.visual = fbi->var.bits_per_pixel == 8 ? + FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; + fbi->fix.line_length = (fbi->var.xres_virtual * + fbi->var.bits_per_pixel) / 8; + return 0; +} + +/* + * show some display controller and cursor registers + */ +static ssize_t mb862xxfb_show_dispregs(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fb_info *fbi = dev_get_drvdata(dev); + struct mb862xxfb_par *par = fbi->par; + char *ptr = buf; + unsigned int reg; + + for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4) + ptr += sprintf(ptr, "%08x = %08x\n", + reg, inreg(disp, reg)); + + for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4) + ptr += sprintf(ptr, "%08x = %08x\n", + reg, inreg(disp, reg)); + + for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4) + ptr += sprintf(ptr, "%08x = %08x\n", + reg, inreg(disp, reg)); + + return ptr - buf; +} + +static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL); + +irqreturn_t mb862xx_intr(int irq, void *dev_id) +{ + struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id; + unsigned long reg_ist, mask; + + if (!par) + return IRQ_NONE; + + if (par->type == BT_CARMINE) { + /* Get Interrupt Status */ + reg_ist = inreg(ctrl, GC_CTRL_STATUS); + mask = inreg(ctrl, GC_CTRL_INT_MASK); + if (reg_ist == 0) + return IRQ_HANDLED; + + reg_ist &= mask; + if (reg_ist == 0) + return IRQ_HANDLED; + + /* Clear interrupt status */ + outreg(ctrl, 0x0, reg_ist); + } else { + /* Get status */ + reg_ist = inreg(host, GC_IST); + mask = inreg(host, GC_IMASK); + + reg_ist &= mask; + if (reg_ist == 0) + return IRQ_HANDLED; + + /* Clear status */ + outreg(host, GC_IST, ~reg_ist); + } + return IRQ_HANDLED; +} + +#if defined(CONFIG_FB_MB862XX_LIME) +/* + * GDC (Lime, Coral(B/Q), Mint, ...) on host bus + */ +static int mb862xx_gdc_init(struct mb862xxfb_par *par) +{ + unsigned long ccf, mmr; + unsigned long ver, rev; + + if (!par) + return -ENODEV; + +#if defined(CONFIG_FB_PRE_INIT_FB) + par->pre_init = 1; +#endif + par->host = par->mmio_base; + par->i2c = par->mmio_base + MB862XX_I2C_BASE; + par->disp = par->mmio_base + MB862XX_DISP_BASE; + par->cap = par->mmio_base + MB862XX_CAP_BASE; + par->draw = par->mmio_base + MB862XX_DRAW_BASE; + par->geo = par->mmio_base + MB862XX_GEO_BASE; + par->pio = par->mmio_base + MB862XX_PIO_BASE; + + par->refclk = GC_DISP_REFCLK_400; + + ver = inreg(host, GC_CID); + rev = inreg(pio, GC_REVISION); + if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) { + dev_info(par->dev, "Fujitsu Lime v1.%d found\n", + (int)rev & 0xff); + par->type = BT_LIME; + ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100; + mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2; + } else { + dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev); + return -ENODEV; + } + + if (!par->pre_init) { + outreg(host, GC_CCF, ccf); + udelay(200); + outreg(host, GC_MMR, mmr); + udelay(10); + } + + /* interrupt status */ + outreg(host, GC_IST, 0); + outreg(host, GC_IMASK, GC_INT_EN); + return 0; +} + +static int __devinit of_platform_mb862xx_probe(struct of_device *ofdev, + const struct of_device_id *id) +{ + struct device_node *np = ofdev->node; + struct device *dev = &ofdev->dev; + struct mb862xxfb_par *par; + struct fb_info *info; + struct resource res; + resource_size_t res_size; + unsigned long ret = -ENODEV; + + if (of_address_to_resource(np, 0, &res)) { + dev_err(dev, "Invalid address\n"); + return -ENXIO; + } + + info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev); + if (info == NULL) { + dev_err(dev, "cannot allocate framebuffer\n"); + return -ENOMEM; + } + + par = info->par; + par->info = info; + par->dev = dev; + + par->irq = irq_of_parse_and_map(np, 0); + if (par->irq == NO_IRQ) { + dev_err(dev, "failed to map irq\n"); + ret = -ENODEV; + goto fbrel; + } + + res_size = 1 + res.end - res.start; + par->res = request_mem_region(res.start, res_size, DRV_NAME); + if (par->res == NULL) { + dev_err(dev, "Cannot claim framebuffer/mmio\n"); + ret = -ENXIO; + goto irqdisp; + } + +#if defined(CONFIG_LWMON5) + par->gc_mode = &lwmon5_gc_mode; +#endif + +#if defined(CONFIG_SOCRATES) + par->gc_mode = &socrates_gc_mode; +#endif + + par->fb_base_phys = res.start; + par->mmio_base_phys = res.start + MB862XX_MMIO_BASE; + par->mmio_len = MB862XX_MMIO_SIZE; + if (par->gc_mode) + par->mapped_vram = par->gc_mode->max_vram; + else + par->mapped_vram = MB862XX_MEM_SIZE; + + par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram); + if (par->fb_base == NULL) { + dev_err(dev, "Cannot map framebuffer\n"); + goto rel_reg; + } + + par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); + if (par->mmio_base == NULL) { + dev_err(dev, "Cannot map registers\n"); + goto fb_unmap; + } + + dev_dbg(dev, "fb phys 0x%llx 0x%lx\n", + (u64)par->fb_base_phys, (ulong)par->mapped_vram); + dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n", + (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq); + + if (mb862xx_gdc_init(par)) + goto io_unmap; + + if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED, + DRV_NAME, (void *)par)) { + dev_err(dev, "Cannot request irq\n"); + goto io_unmap; + } + + mb862xxfb_init_fbinfo(info); + + if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) { + dev_err(dev, "Could not allocate cmap for fb_info.\n"); + goto free_irq; + } + + if ((info->fbops->fb_set_par)(info)) + dev_err(dev, "set_var() failed on initial setup?\n"); + + if (register_framebuffer(info)) { + dev_err(dev, "failed to register framebuffer\n"); + goto rel_cmap; + } + + dev_set_drvdata(dev, info); + + if (device_create_file(dev, &dev_attr_dispregs)) + dev_err(dev, "Can't create sysfs regdump file\n"); + return 0; + +rel_cmap: + fb_dealloc_cmap(&info->cmap); +free_irq: + outreg(host, GC_IMASK, 0); + free_irq(par->irq, (void *)par); +io_unmap: + iounmap(par->mmio_base); +fb_unmap: + iounmap(par->fb_base); +rel_reg: + release_mem_region(res.start, res_size); +irqdisp: + irq_dispose_mapping(par->irq); +fbrel: + dev_set_drvdata(dev, NULL); + framebuffer_release(info); + return ret; +} + +static int __devexit of_platform_mb862xx_remove(struct of_device *ofdev) +{ + struct fb_info *fbi = dev_get_drvdata(&ofdev->dev); + struct mb862xxfb_par *par = fbi->par; + resource_size_t res_size = 1 + par->res->end - par->res->start; + unsigned long reg; + + dev_dbg(fbi->dev, "%s release\n", fbi->fix.id); + + /* display off */ + reg = inreg(disp, GC_DCM1); + reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E); + outreg(disp, GC_DCM1, reg); + + /* disable interrupts */ + outreg(host, GC_IMASK, 0); + + free_irq(par->irq, (void *)par); + irq_dispose_mapping(par->irq); + + device_remove_file(&ofdev->dev, &dev_attr_dispregs); + + unregister_framebuffer(fbi); + fb_dealloc_cmap(&fbi->cmap); + + iounmap(par->mmio_base); + iounmap(par->fb_base); + + dev_set_drvdata(&ofdev->dev, NULL); + release_mem_region(par->res->start, res_size); + framebuffer_release(fbi); + return 0; +} + +/* + * common types + */ +static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = { + { .compatible = "fujitsu,MB86276", }, + { .compatible = "fujitsu,lime", }, + { .compatible = "fujitsu,MB86277", }, + { .compatible = "fujitsu,mint", }, + { .compatible = "fujitsu,MB86293", }, + { .compatible = "fujitsu,MB86294", }, + { .compatible = "fujitsu,coral", }, + { /* end */ } +}; + +static struct of_platform_driver of_platform_mb862xxfb_driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .match_table = of_platform_mb862xx_tbl, + .probe = of_platform_mb862xx_probe, + .remove = __devexit_p(of_platform_mb862xx_remove), +}; +#endif + +#if defined(CONFIG_FB_MB862XX_PCI_GDC) +static int coralp_init(struct mb862xxfb_par *par) +{ + int cn, ver; + + par->host = par->mmio_base; + par->i2c = par->mmio_base + MB862XX_I2C_BASE; + par->disp = par->mmio_base + MB862XX_DISP_BASE; + par->cap = par->mmio_base + MB862XX_CAP_BASE; + par->draw = par->mmio_base + MB862XX_DRAW_BASE; + par->geo = par->mmio_base + MB862XX_GEO_BASE; + par->pio = par->mmio_base + MB862XX_PIO_BASE; + + par->refclk = GC_DISP_REFCLK_400; + + ver = inreg(host, GC_CID); + cn = (ver & GC_CID_CNAME_MSK) >> 8; + ver = ver & GC_CID_VERSION_MSK; + if (cn == 3) { + dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\ + (ver == 6) ? "P" : (ver == 8) ? "PA" : "?", + par->pdev->revision); + outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133); + udelay(200); + outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL); + udelay(10); + /* Clear interrupt status */ + outreg(host, GC_IST, 0); + } else { + return -ENODEV; + } + return 0; +} + +static int init_dram_ctrl(struct mb862xxfb_par *par) +{ + unsigned long i = 0; + + /* + * Set io mode first! Spec. says IC may be destroyed + * if not set to SSTL2/LVCMOS before init. + */ + outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0); + + /* DRAM init */ + outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD); + outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE); + outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2, + GC_EVB_DCTL_REFRESH_SETTIME2); + outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1); + outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1); + outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES); + + /* DLL reset done? */ + while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) { + udelay(GC_DCTL_INIT_WAIT_INTERVAL); + if (i++ > GC_DCTL_INIT_WAIT_CNT) { + dev_err(par->dev, "VRAM init failed.\n"); + return -EINVAL; + } + } + outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST); + outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST); + return 0; +} + +static int carmine_init(struct mb862xxfb_par *par) +{ + unsigned long reg; + + par->ctrl = par->mmio_base + MB86297_CTRL_BASE; + par->i2c = par->mmio_base + MB86297_I2C_BASE; + par->disp = par->mmio_base + MB86297_DISP0_BASE; + par->disp1 = par->mmio_base + MB86297_DISP1_BASE; + par->cap = par->mmio_base + MB86297_CAP0_BASE; + par->cap1 = par->mmio_base + MB86297_CAP1_BASE; + par->draw = par->mmio_base + MB86297_DRAW_BASE; + par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE; + par->wrback = par->mmio_base + MB86297_WRBACK_BASE; + + par->refclk = GC_DISP_REFCLK_533; + + /* warm up */ + reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0; + outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); + + /* check for engine module revision */ + if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION) + dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n", + par->pdev->revision); + else + goto err_init; + + reg &= ~GC_CTRL_CLK_EN_2D3D; + outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); + + /* set up vram */ + if (init_dram_ctrl(par) < 0) + goto err_init; + + outreg(ctrl, GC_CTRL_INT_MASK, 0); + return 0; + +err_init: + outreg(ctrl, GC_CTRL_CLK_ENABLE, 0); + return -EINVAL; +} + +static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par) +{ + switch (par->type) { + case BT_CORALP: + return coralp_init(par); + case BT_CARMINE: + return carmine_init(par); + default: + return -ENODEV; + } +} + +#define CHIP_ID(id) \ + { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) } + +static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = { + /* MB86295/MB86296 */ + CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP), + CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA), + /* MB86297 */ + CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE), + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl); + +static int __devinit mb862xx_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct mb862xxfb_par *par; + struct fb_info *info; + struct device *dev = &pdev->dev; + int ret; + + ret = pci_enable_device(pdev); + if (ret < 0) { + dev_err(dev, "Cannot enable PCI device\n"); + goto out; + } + + info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev); + if (!info) { + dev_err(dev, "framebuffer alloc failed\n"); + ret = -ENOMEM; + goto dis_dev; + } + + par = info->par; + par->info = info; + par->dev = dev; + par->pdev = pdev; + par->irq = pdev->irq; + + ret = pci_request_regions(pdev, DRV_NAME); + if (ret < 0) { + dev_err(dev, "Cannot reserve region(s) for PCI device\n"); + goto rel_fb; + } + + switch (pdev->device) { + case PCI_DEVICE_ID_FUJITSU_CORALP: + case PCI_DEVICE_ID_FUJITSU_CORALPA: + par->fb_base_phys = pci_resource_start(par->pdev, 0); + par->mapped_vram = CORALP_MEM_SIZE; + par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE; + par->mmio_len = MB862XX_MMIO_SIZE; + par->type = BT_CORALP; + break; + case PCI_DEVICE_ID_FUJITSU_CARMINE: + par->fb_base_phys = pci_resource_start(par->pdev, 2); + par->mmio_base_phys = pci_resource_start(par->pdev, 3); + par->mmio_len = pci_resource_len(par->pdev, 3); + par->mapped_vram = CARMINE_MEM_SIZE; + par->type = BT_CARMINE; + break; + default: + /* should never occur */ + goto rel_reg; + } + + par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram); + if (par->fb_base == NULL) { + dev_err(dev, "Cannot map framebuffer\n"); + goto rel_reg; + } + + par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); + if (par->mmio_base == NULL) { + dev_err(dev, "Cannot map registers\n"); + ret = -EIO; + goto fb_unmap; + } + + dev_dbg(dev, "fb phys 0x%llx 0x%lx\n", + (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram); + dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n", + (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len); + + if (mb862xx_pci_gdc_init(par)) + goto io_unmap; + + if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED | IRQF_SHARED, + DRV_NAME, (void *)par)) { + dev_err(dev, "Cannot request irq\n"); + goto io_unmap; + } + + mb862xxfb_init_fbinfo(info); + + if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) { + dev_err(dev, "Could not allocate cmap for fb_info.\n"); + ret = -ENOMEM; + goto free_irq; + } + + if ((info->fbops->fb_set_par)(info)) + dev_err(dev, "set_var() failed on initial setup?\n"); + + ret = register_framebuffer(info); + if (ret < 0) { + dev_err(dev, "failed to register framebuffer\n"); + goto rel_cmap; + } + + pci_set_drvdata(pdev, info); + + if (device_create_file(dev, &dev_attr_dispregs)) + dev_err(dev, "Can't create sysfs regdump file\n"); + + if (par->type == BT_CARMINE) + outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN); + else + outreg(host, GC_IMASK, GC_INT_EN); + + return 0; + +rel_cmap: + fb_dealloc_cmap(&info->cmap); +free_irq: + free_irq(par->irq, (void *)par); +io_unmap: + iounmap(par->mmio_base); +fb_unmap: + iounmap(par->fb_base); +rel_reg: + pci_release_regions(pdev); +rel_fb: + framebuffer_release(info); +dis_dev: + pci_disable_device(pdev); +out: + return ret; +} + +static void __devexit mb862xx_pci_remove(struct pci_dev *pdev) +{ + struct fb_info *fbi = pci_get_drvdata(pdev); + struct mb862xxfb_par *par = fbi->par; + unsigned long reg; + + dev_dbg(fbi->dev, "%s release\n", fbi->fix.id); + + /* display off */ + reg = inreg(disp, GC_DCM1); + reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E); + outreg(disp, GC_DCM1, reg); + + if (par->type == BT_CARMINE) { + outreg(ctrl, GC_CTRL_INT_MASK, 0); + outreg(ctrl, GC_CTRL_CLK_ENABLE, 0); + } else { + outreg(host, GC_IMASK, 0); + } + + device_remove_file(&pdev->dev, &dev_attr_dispregs); + + pci_set_drvdata(pdev, NULL); + unregister_framebuffer(fbi); + fb_dealloc_cmap(&fbi->cmap); + + free_irq(par->irq, (void *)par); + iounmap(par->mmio_base); + iounmap(par->fb_base); + + pci_release_regions(pdev); + framebuffer_release(fbi); + pci_disable_device(pdev); +} + +static struct pci_driver mb862xxfb_pci_driver = { + .name = DRV_NAME, + .id_table = mb862xx_pci_tbl, + .probe = mb862xx_pci_probe, + .remove = __devexit_p(mb862xx_pci_remove), +}; +#endif + +static int __devinit mb862xxfb_init(void) +{ + int ret = -ENODEV; + +#if defined(CONFIG_FB_MB862XX_LIME) + ret = of_register_platform_driver(&of_platform_mb862xxfb_driver); +#endif +#if defined(CONFIG_FB_MB862XX_PCI_GDC) + ret = pci_register_driver(&mb862xxfb_pci_driver); +#endif + return ret; +} + +static void __exit mb862xxfb_exit(void) +{ +#if defined(CONFIG_FB_MB862XX_LIME) + of_unregister_platform_driver(&of_platform_mb862xxfb_driver); +#endif +#if defined(CONFIG_FB_MB862XX_PCI_GDC) + pci_unregister_driver(&mb862xxfb_pci_driver); +#endif +} + +module_init(mb862xxfb_init); +module_exit(mb862xxfb_exit); + +MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver"); +MODULE_AUTHOR("Anatolij Gustschin "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/video/mb862xx/mb862xxfb.h b/drivers/video/mb862xx/mb862xxfb.h new file mode 100644 index 000000000000..c4c8f4dd2217 --- /dev/null +++ b/drivers/video/mb862xx/mb862xxfb.h @@ -0,0 +1,83 @@ +#ifndef __MB862XX_H__ +#define __MB862XX_H__ + +#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf +#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019 +#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e +#define PCI_DEVICE_ID_FUJITSU_CARMINE 0x202b + +#define GC_MMR_CORALP_EVB_VAL 0x11d7fa13 + +enum gdctype { + BT_NONE, + BT_LIME, + BT_MINT, + BT_CORAL, + BT_CORALP, + BT_CARMINE, +}; + +struct mb862xx_gc_mode { + struct fb_videomode def_mode; /* mode of connected display */ + unsigned int def_bpp; /* default depth */ + unsigned long max_vram; /* connected SDRAM size */ + unsigned long ccf; /* gdc clk */ + unsigned long mmr; /* memory mode for SDRAM */ +}; + +/* private data */ +struct mb862xxfb_par { + struct fb_info *info; /* fb info head */ + struct device *dev; + struct pci_dev *pdev; + struct resource *res; /* framebuffer/mmio resource */ + + resource_size_t fb_base_phys; /* fb base, 36-bit PPC440EPx */ + resource_size_t mmio_base_phys; /* io base addr */ + void __iomem *fb_base; /* remapped framebuffer */ + void __iomem *mmio_base; /* remapped registers */ + size_t mapped_vram; /* length of remapped vram */ + size_t mmio_len; /* length of register region */ + + void __iomem *host; /* relocatable reg. bases */ + void __iomem *i2c; + void __iomem *disp; + void __iomem *disp1; + void __iomem *cap; + void __iomem *cap1; + void __iomem *draw; + void __iomem *geo; + void __iomem *pio; + void __iomem *ctrl; + void __iomem *dram_ctrl; + void __iomem *wrback; + + unsigned int irq; + unsigned int type; /* GDC type */ + unsigned int refclk; /* disp. reference clock */ + struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */ + int pre_init; /* don't init display if 1 */ + + u32 pseudo_palette[16]; +}; + +#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC) +#error "Select Lime GDC or CoralP/Carmine support, but not both together" +#endif +#if defined(CONFIG_FB_MB862XX_LIME) +#define gdc_read __raw_readl +#define gdc_write __raw_writel +#else +#define gdc_read readl +#define gdc_write writel +#endif + +#define inreg(type, off) \ + gdc_read((par->type + (off))) + +#define outreg(type, off, val) \ + gdc_write((val), (par->type + (off))) + +#define pack(a, b) (((a) << 16) | (b)) + +#endif diff --git a/drivers/video/omap/Makefile b/drivers/video/omap/Makefile index 99da8b6d2c36..ed13889c1162 100644 --- a/drivers/video/omap/Makefile +++ b/drivers/video/omap/Makefile @@ -23,7 +23,6 @@ objs-y$(CONFIG_MACH_OMAP_PALMZ71) += lcd_palmz71.o objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o -objs-y$(CONFIG_MACH_SX1) += lcd_sx1.o omapfb-objs := $(objs-yy) diff --git a/drivers/video/omap/lcd_sx1.c b/drivers/video/omap/lcd_sx1.c deleted file mode 100644 index e55de201b8ff..000000000000 --- a/drivers/video/omap/lcd_sx1.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * LCD panel support for the Siemens SX1 mobile phone - * - * Current version : Vovan888@gmail.com, great help from FCA00000 - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * OMAP310 GPIO registers - */ -#define GPIO_DATA_INPUT 0xfffce000 -#define GPIO_DATA_OUTPUT 0xfffce004 -#define GPIO_DIR_CONTROL 0xfffce008 -#define GPIO_INT_CONTROL 0xfffce00c -#define GPIO_INT_MASK 0xfffce010 -#define GPIO_INT_STATUS 0xfffce014 -#define GPIO_PIN_CONTROL 0xfffce018 - - -#define A_LCD_SSC_RD 3 -#define A_LCD_SSC_SD 7 -#define _A_LCD_RESET 9 -#define _A_LCD_SSC_CS 12 -#define _A_LCD_SSC_A0 13 - -#define DSP_REG 0xE1017024 - -const unsigned char INIT_1[12] = { - 0x1C, 0x02, 0x88, 0x00, 0x1E, 0xE0, 0x00, 0xDC, 0x00, 0x02, 0x00 -}; - -const unsigned char INIT_2[127] = { - 0x15, 0x00, 0x29, 0x00, 0x3E, 0x00, 0x51, 0x00, - 0x65, 0x00, 0x7A, 0x00, 0x8D, 0x00, 0xA1, 0x00, - 0xB6, 0x00, 0xC7, 0x00, 0xD8, 0x00, 0xEB, 0x00, - 0xFB, 0x00, 0x0B, 0x01, 0x1B, 0x01, 0x27, 0x01, - 0x34, 0x01, 0x41, 0x01, 0x4C, 0x01, 0x55, 0x01, - 0x5F, 0x01, 0x68, 0x01, 0x70, 0x01, 0x78, 0x01, - 0x7E, 0x01, 0x86, 0x01, 0x8C, 0x01, 0x94, 0x01, - 0x9B, 0x01, 0xA1, 0x01, 0xA4, 0x01, 0xA9, 0x01, - 0xAD, 0x01, 0xB2, 0x01, 0xB7, 0x01, 0xBC, 0x01, - 0xC0, 0x01, 0xC4, 0x01, 0xC8, 0x01, 0xCB, 0x01, - 0xCF, 0x01, 0xD2, 0x01, 0xD5, 0x01, 0xD8, 0x01, - 0xDB, 0x01, 0xE0, 0x01, 0xE3, 0x01, 0xE6, 0x01, - 0xE8, 0x01, 0xEB, 0x01, 0xEE, 0x01, 0xF1, 0x01, - 0xF3, 0x01, 0xF8, 0x01, 0xF9, 0x01, 0xFC, 0x01, - 0x00, 0x02, 0x03, 0x02, 0x07, 0x02, 0x09, 0x02, - 0x0E, 0x02, 0x13, 0x02, 0x1C, 0x02, 0x00 -}; - -const unsigned char INIT_3[15] = { - 0x14, 0x26, 0x33, 0x3D, 0x45, 0x4D, 0x53, 0x59, - 0x5E, 0x63, 0x67, 0x6D, 0x71, 0x78, 0xFF -}; - -static void epson_sendbyte(int flag, unsigned char byte) -{ - int i, shifter = 0x80; - - if (!flag) - gpio_set_value(_A_LCD_SSC_A0, 0); - mdelay(2); - gpio_set_value(A_LCD_SSC_RD, 1); - - gpio_set_value(A_LCD_SSC_SD, flag); - - OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2200); - OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2202); - for (i = 0; i < 8; i++) { - OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2200); - gpio_set_value(A_LCD_SSC_SD, shifter & byte); - OMAP_MCBSP_WRITE(OMAP1510_MCBSP3_BASE, PCR0, 0x2202); - shifter >>= 1; - } - gpio_set_value(_A_LCD_SSC_A0, 1); -} - -static void init_system(void) -{ - omap_mcbsp_request(OMAP_MCBSP3); - omap_mcbsp_stop(OMAP_MCBSP3); -} - -static void setup_GPIO(void) -{ - /* new wave */ - gpio_request(A_LCD_SSC_RD, "lcd_ssc_rd"); - gpio_request(A_LCD_SSC_SD, "lcd_ssc_sd"); - gpio_request(_A_LCD_RESET, "lcd_reset"); - gpio_request(_A_LCD_SSC_CS, "lcd_ssc_cs"); - gpio_request(_A_LCD_SSC_A0, "lcd_ssc_a0"); - - /* set GPIOs to output, with initial data */ - gpio_direction_output(A_LCD_SSC_RD, 1); - gpio_direction_output(A_LCD_SSC_SD, 0); - gpio_direction_output(_A_LCD_RESET, 0); - gpio_direction_output(_A_LCD_SSC_CS, 1); - gpio_direction_output(_A_LCD_SSC_A0, 1); -} - -static void display_init(void) -{ - int i; - - omap_cfg_reg(MCBSP3_CLKX); - - mdelay(2); - setup_GPIO(); - mdelay(2); - - /* reset LCD */ - gpio_set_value(A_LCD_SSC_SD, 1); - epson_sendbyte(0, 0x25); - - gpio_set_value(_A_LCD_RESET, 0); - mdelay(10); - gpio_set_value(_A_LCD_RESET, 1); - - gpio_set_value(_A_LCD_SSC_CS, 1); - mdelay(2); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD, phase 1 */ - epson_sendbyte(0, 0xCA); - for (i = 0; i < 10; i++) - epson_sendbyte(1, INIT_1[i]); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 2 */ - epson_sendbyte(0, 0xCB); - for (i = 0; i < 125; i++) - epson_sendbyte(1, INIT_2[i]); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 2a */ - epson_sendbyte(0, 0xCC); - for (i = 0; i < 14; i++) - epson_sendbyte(1, INIT_3[i]); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 3 */ - epson_sendbyte(0, 0xBC); - epson_sendbyte(1, 0x08); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 4 */ - epson_sendbyte(0, 0x07); - epson_sendbyte(1, 0x05); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 5 */ - epson_sendbyte(0, 0x94); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 6 */ - epson_sendbyte(0, 0xC6); - epson_sendbyte(1, 0x80); - gpio_set_value(_A_LCD_SSC_CS, 1); - mdelay(100); /* used to be 1000 */ - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 7 */ - epson_sendbyte(0, 0x16); - epson_sendbyte(1, 0x02); - epson_sendbyte(1, 0x00); - epson_sendbyte(1, 0xB1); - epson_sendbyte(1, 0x00); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 8 */ - epson_sendbyte(0, 0x76); - epson_sendbyte(1, 0x00); - epson_sendbyte(1, 0x00); - epson_sendbyte(1, 0xDB); - epson_sendbyte(1, 0x00); - gpio_set_value(_A_LCD_SSC_CS, 1); - gpio_set_value(_A_LCD_SSC_CS, 0); - - /* init LCD phase 9 */ - epson_sendbyte(0, 0xAF); - gpio_set_value(_A_LCD_SSC_CS, 1); -} - -static int sx1_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev) -{ - return 0; -} - -static void sx1_panel_cleanup(struct lcd_panel *panel) -{ -} - -static void sx1_panel_disable(struct lcd_panel *panel) -{ - printk(KERN_INFO "SX1: LCD panel disable\n"); - sx1_setmmipower(0); - gpio_set_value(_A_LCD_SSC_CS, 1); - - epson_sendbyte(0, 0x25); - gpio_set_value(_A_LCD_SSC_CS, 0); - - epson_sendbyte(0, 0xAE); - gpio_set_value(_A_LCD_SSC_CS, 1); - mdelay(100); - gpio_set_value(_A_LCD_SSC_CS, 0); - - epson_sendbyte(0, 0x95); - gpio_set_value(_A_LCD_SSC_CS, 1); -} - -static int sx1_panel_enable(struct lcd_panel *panel) -{ - printk(KERN_INFO "lcd_sx1: LCD panel enable\n"); - init_system(); - display_init(); - - sx1_setmmipower(1); - sx1_setbacklight(0x18); - sx1_setkeylight (0x06); - return 0; -} - - -static unsigned long sx1_panel_get_caps(struct lcd_panel *panel) -{ - return 0; -} - -struct lcd_panel sx1_panel = { - .name = "sx1", - .config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC | - OMAP_LCDC_INV_HSYNC | OMAP_LCDC_INV_PIX_CLOCK | - OMAP_LCDC_INV_OUTPUT_EN, - - .x_res = 176, - .y_res = 220, - .data_lines = 16, - .bpp = 16, - .hsw = 5, - .hfp = 5, - .hbp = 5, - .vsw = 2, - .vfp = 1, - .vbp = 1, - .pixel_clock = 1500, - - .init = sx1_panel_init, - .cleanup = sx1_panel_cleanup, - .enable = sx1_panel_enable, - .disable = sx1_panel_disable, - .get_caps = sx1_panel_get_caps, -}; - -static int sx1_panel_probe(struct platform_device *pdev) -{ - omapfb_register_panel(&sx1_panel); - return 0; -} - -static int sx1_panel_remove(struct platform_device *pdev) -{ - return 0; -} - -static int sx1_panel_suspend(struct platform_device *pdev, pm_message_t mesg) -{ - return 0; -} - -static int sx1_panel_resume(struct platform_device *pdev) -{ - return 0; -} - -struct platform_driver sx1_panel_driver = { - .probe = sx1_panel_probe, - .remove = sx1_panel_remove, - .suspend = sx1_panel_suspend, - .resume = sx1_panel_resume, - .driver = { - .name = "lcd_sx1", - .owner = THIS_MODULE, - }, -}; - -static int sx1_panel_drv_init(void) -{ - return platform_driver_register(&sx1_panel_driver); -} - -static void sx1_panel_drv_cleanup(void) -{ - platform_driver_unregister(&sx1_panel_driver); -} - -module_init(sx1_panel_drv_init); -module_exit(sx1_panel_drv_cleanup); diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c index 5a5e407dc45f..1a49519dafa4 100644 --- a/drivers/video/omap/omapfb_main.c +++ b/drivers/video/omap/omapfb_main.c @@ -392,7 +392,7 @@ static void set_fb_fix(struct fb_info *fbi) int bpp; rg = &plane->fbdev->mem_desc.region[plane->idx]; - fbi->screen_base = (char __iomem *)rg->vaddr; + fbi->screen_base = rg->vaddr; fix->smem_start = rg->paddr; fix->smem_len = rg->size; diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 97204497d9f7..cc59c52e1103 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -804,6 +804,9 @@ static int pxafb_smart_thread(void *arg) static int pxafb_smart_init(struct pxafb_info *fbi) { + if (!(fbi->lccr0 | LCCR0_LCDT)) + return 0; + fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, "lcd_refresh"); if (IS_ERR(fbi->smart_thread)) { @@ -1372,7 +1375,7 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi, fbi->cmap_inverse = inf->cmap_inverse; fbi->cmap_static = inf->cmap_static; - switch (lcd_conn & 0xf) { + switch (lcd_conn & LCD_TYPE_MASK) { case LCD_TYPE_MONO_STN: fbi->lccr0 = LCCR0_CMS; break; diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c index 2a380011e9ba..7baf2dd12d50 100644 --- a/drivers/video/tmiofb.c +++ b/drivers/video/tmiofb.c @@ -222,6 +222,9 @@ static irqreturn_t tmiofb_irq(int irq, void *__info) unsigned int bbisc = tmio_ioread16(par->lcr + LCR_BBISC); + tmio_iowrite16(bbisc, par->lcr + LCR_BBISC); + +#ifdef CONFIG_FB_TMIO_ACCELL /* * We were in polling mode and now we got correct irq. * Switch back to IRQ-based sync of command FIFO @@ -231,9 +234,6 @@ static irqreturn_t tmiofb_irq(int irq, void *__info) par->use_polling = false; } - tmio_iowrite16(bbisc, par->lcr + LCR_BBISC); - -#ifdef CONFIG_FB_TMIO_ACCELL if (bbisc & 1) wake_up(&par->wait_acc); #endif @@ -938,7 +938,9 @@ static void tmiofb_dump_regs(struct platform_device *dev) static int tmiofb_suspend(struct platform_device *dev, pm_message_t state) { struct fb_info *info = platform_get_drvdata(dev); +#ifdef CONFIG_FB_TMIO_ACCELL struct tmiofb_par *par = info->par; +#endif struct mfd_cell *cell = dev->dev.platform_data; int retval = 0; @@ -950,12 +952,14 @@ static int tmiofb_suspend(struct platform_device *dev, pm_message_t state) info->fbops->fb_sync(info); +#ifdef CONFIG_FB_TMIO_ACCELL /* * The fb should be usable even if interrupts are disabled (and they are * during suspend/resume). Switch temporary to forced polling. */ printk(KERN_INFO "tmiofb: switching to polling\n"); par->use_polling = true; +#endif tmiofb_hw_stop(dev); if (cell->suspend) diff --git a/drivers/video/via/global.h b/drivers/video/via/global.h index 8e5263c5b812..7543d5f7e309 100644 --- a/drivers/video/via/global.h +++ b/drivers/video/via/global.h @@ -38,7 +38,6 @@ #include "iface.h" #include "viafbdev.h" #include "chip.h" -#include "debug.h" #include "accel.h" #include "share.h" #include "dvi.h" @@ -48,12 +47,10 @@ #include "lcd.h" #include "ioctl.h" -#include "viamode.h" #include "via_utility.h" #include "vt1636.h" #include "tblDPASetting.h" #include "tbl1636.h" -#include "viafbdev.h" /* External struct*/ diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c index 0132eae06f55..73ac754ad801 100644 --- a/drivers/video/via/viafbdev.c +++ b/drivers/video/via/viafbdev.c @@ -2036,30 +2036,30 @@ static int viafb_vt1636_proc_write(struct file *file, return count; } -static void viafb_init_proc(struct proc_dir_entry *viafb_entry) +static void viafb_init_proc(struct proc_dir_entry **viafb_entry) { struct proc_dir_entry *entry; - viafb_entry = proc_mkdir("viafb", NULL); + *viafb_entry = proc_mkdir("viafb", NULL); if (viafb_entry) { - entry = create_proc_entry("dvp0", 0, viafb_entry); + entry = create_proc_entry("dvp0", 0, *viafb_entry); if (entry) { entry->owner = THIS_MODULE; entry->read_proc = viafb_dvp0_proc_read; entry->write_proc = viafb_dvp0_proc_write; } - entry = create_proc_entry("dvp1", 0, viafb_entry); + entry = create_proc_entry("dvp1", 0, *viafb_entry); if (entry) { entry->owner = THIS_MODULE; entry->read_proc = viafb_dvp1_proc_read; entry->write_proc = viafb_dvp1_proc_write; } - entry = create_proc_entry("dfph", 0, viafb_entry); + entry = create_proc_entry("dfph", 0, *viafb_entry); if (entry) { entry->owner = THIS_MODULE; entry->read_proc = viafb_dfph_proc_read; entry->write_proc = viafb_dfph_proc_write; } - entry = create_proc_entry("dfpl", 0, viafb_entry); + entry = create_proc_entry("dfpl", 0, *viafb_entry); if (entry) { entry->owner = THIS_MODULE; entry->read_proc = viafb_dfpl_proc_read; @@ -2068,7 +2068,7 @@ static void viafb_init_proc(struct proc_dir_entry *viafb_entry) if (VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info. lvds_chip_name || VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { - entry = create_proc_entry("vt1636", 0, viafb_entry); + entry = create_proc_entry("vt1636", 0, *viafb_entry); if (entry) { entry->owner = THIS_MODULE; entry->read_proc = viafb_vt1636_proc_read; @@ -2087,6 +2087,7 @@ static void viafb_remove_proc(struct proc_dir_entry *viafb_entry) remove_proc_entry("dfpl", viafb_entry); remove_proc_entry("vt1636", viafb_entry); remove_proc_entry("vt1625", viafb_entry); + remove_proc_entry("viafb", NULL); } static int __devinit via_pci_probe(void) @@ -2348,7 +2349,7 @@ static int __devinit via_pci_probe(void) viafbinfo->node, viafbinfo->fix.id, default_var.xres, default_var.yres, default_var.bits_per_pixel); - viafb_init_proc(viaparinfo->proc_entry); + viafb_init_proc(&viaparinfo->proc_entry); viafb_init_dac(IGA2); return 0; } diff --git a/drivers/video/xen-fbfront.c b/drivers/video/xen-fbfront.c index a463b3dd837b..2493f05e9f61 100644 --- a/drivers/video/xen-fbfront.c +++ b/drivers/video/xen-fbfront.c @@ -668,7 +668,7 @@ static struct xenbus_device_id xenfb_ids[] = { { "" } }; -static struct xenbus_driver xenfb = { +static struct xenbus_driver xenfb_driver = { .name = "vfb", .owner = THIS_MODULE, .ids = xenfb_ids, @@ -687,12 +687,12 @@ static int __init xenfb_init(void) if (xen_initial_domain()) return -ENODEV; - return xenbus_register_frontend(&xenfb); + return xenbus_register_frontend(&xenfb_driver); } static void __exit xenfb_cleanup(void) { - xenbus_unregister_driver(&xenfb); + xenbus_unregister_driver(&xenfb_driver); } module_init(xenfb_init); diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index 5da3d2423cc0..40a3a2afbfe7 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -298,8 +298,9 @@ static int xilinxfb_assign(struct device *dev, unsigned long physaddr, /* Put a banner in the log (for DEBUG) */ dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs); - dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n", - (void*)drvdata->fb_phys, drvdata->fb_virt, fbsize); + dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n", + (unsigned long long) drvdata->fb_phys, drvdata->fb_virt, + fbsize); return 0; /* success */ diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig index c4493091c655..90616822cd20 100644 --- a/drivers/w1/masters/Kconfig +++ b/drivers/w1/masters/Kconfig @@ -36,7 +36,7 @@ config W1_MASTER_DS2482 config W1_MASTER_DS1WM tristate "Maxim DS1WM 1-wire busmaster" - depends on W1 && ARM + depends on W1 && ARM && HAVE_CLK help Say Y here to enable the DS1WM 1-wire driver, such as that in HP iPAQ devices like h5xxx, h2200, and ASIC3-based like @@ -52,5 +52,12 @@ config W1_MASTER_GPIO This support is also available as a module. If so, the module will be called w1-gpio.ko. +config HDQ_MASTER_OMAP + tristate "OMAP HDQ driver" + depends on ARCH_OMAP2430 || ARCH_OMAP34XX + help + Say Y here if you want support for the 1-wire or HDQ Interface + on an OMAP processor. + endmenu diff --git a/drivers/w1/masters/Makefile b/drivers/w1/masters/Makefile index 1420b5bbdda8..bc4714a75f3a 100644 --- a/drivers/w1/masters/Makefile +++ b/drivers/w1/masters/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_W1_MASTER_DS2490) += ds2490.o obj-$(CONFIG_W1_MASTER_DS2482) += ds2482.o obj-$(CONFIG_W1_MASTER_DS1WM) += ds1wm.o obj-$(CONFIG_W1_MASTER_GPIO) += w1-gpio.o +obj-$(CONFIG_HDQ_MASTER_OMAP) += omap_hdq.o diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c new file mode 100644 index 000000000000..c973889110c8 --- /dev/null +++ b/drivers/w1/masters/omap_hdq.c @@ -0,0 +1,725 @@ +/* + * drivers/w1/masters/omap_hdq.c + * + * Copyright (C) 2007 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../w1.h" +#include "../w1_int.h" + +#define MOD_NAME "OMAP_HDQ:" + +#define OMAP_HDQ_REVISION 0x00 +#define OMAP_HDQ_TX_DATA 0x04 +#define OMAP_HDQ_RX_DATA 0x08 +#define OMAP_HDQ_CTRL_STATUS 0x0c +#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1<<6) +#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1<<5) +#define OMAP_HDQ_CTRL_STATUS_GO (1<<4) +#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION (1<<2) +#define OMAP_HDQ_CTRL_STATUS_DIR (1<<1) +#define OMAP_HDQ_CTRL_STATUS_MODE (1<<0) +#define OMAP_HDQ_INT_STATUS 0x10 +#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1<<2) +#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1<<1) +#define OMAP_HDQ_INT_STATUS_TIMEOUT (1<<0) +#define OMAP_HDQ_SYSCONFIG 0x14 +#define OMAP_HDQ_SYSCONFIG_SOFTRESET (1<<1) +#define OMAP_HDQ_SYSCONFIG_AUTOIDLE (1<<0) +#define OMAP_HDQ_SYSSTATUS 0x18 +#define OMAP_HDQ_SYSSTATUS_RESETDONE (1<<0) + +#define OMAP_HDQ_FLAG_CLEAR 0 +#define OMAP_HDQ_FLAG_SET 1 +#define OMAP_HDQ_TIMEOUT (HZ/5) + +#define OMAP_HDQ_MAX_USER 4 + +static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue); +static int w1_id; + +struct hdq_data { + struct device *dev; + void __iomem *hdq_base; + /* lock status update */ + struct mutex hdq_mutex; + int hdq_usecount; + struct clk *hdq_ick; + struct clk *hdq_fck; + u8 hdq_irqstatus; + /* device lock */ + spinlock_t hdq_spinlock; + /* + * Used to control the call to omap_hdq_get and omap_hdq_put. + * HDQ Protocol: Write the CMD|REG_address first, followed by + * the data wrire or read. + */ + int init_trans; +}; + +static int __init omap_hdq_probe(struct platform_device *pdev); +static int omap_hdq_remove(struct platform_device *pdev); + +static struct platform_driver omap_hdq_driver = { + .probe = omap_hdq_probe, + .remove = omap_hdq_remove, + .driver = { + .name = "omap_hdq", + }, +}; + +static u8 omap_w1_read_byte(void *_hdq); +static void omap_w1_write_byte(void *_hdq, u8 byte); +static u8 omap_w1_reset_bus(void *_hdq); +static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev, + u8 search_type, w1_slave_found_callback slave_found); + + +static struct w1_bus_master omap_w1_master = { + .read_byte = omap_w1_read_byte, + .write_byte = omap_w1_write_byte, + .reset_bus = omap_w1_reset_bus, + .search = omap_w1_search_bus, +}; + +/* HDQ register I/O routines */ +static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset) +{ + return __raw_readb(hdq_data->hdq_base + offset); +} + +static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val) +{ + __raw_writeb(val, hdq_data->hdq_base + offset); +} + +static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset, + u8 val, u8 mask) +{ + u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask) + | (val & mask); + __raw_writeb(new_val, hdq_data->hdq_base + offset); + + return new_val; +} + +/* + * Wait for one or more bits in flag change. + * HDQ_FLAG_SET: wait until any bit in the flag is set. + * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared. + * return 0 on success and -ETIMEDOUT in the case of timeout. + */ +static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset, + u8 flag, u8 flag_set, u8 *status) +{ + int ret = 0; + unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT; + + if (flag_set == OMAP_HDQ_FLAG_CLEAR) { + /* wait for the flag clear */ + while (((*status = hdq_reg_in(hdq_data, offset)) & flag) + && time_before(jiffies, timeout)) { + schedule_timeout_uninterruptible(1); + } + if (*status & flag) + ret = -ETIMEDOUT; + } else if (flag_set == OMAP_HDQ_FLAG_SET) { + /* wait for the flag set */ + while (!((*status = hdq_reg_in(hdq_data, offset)) & flag) + && time_before(jiffies, timeout)) { + schedule_timeout_uninterruptible(1); + } + if (!(*status & flag)) + ret = -ETIMEDOUT; + } else + return -EINVAL; + + return ret; +} + +/* write out a byte and fill *status with HDQ_INT_STATUS */ +static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) +{ + int ret; + u8 tmp_status; + unsigned long irqflags; + + *status = 0; + + spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); + /* clear interrupt flags via a dummy read */ + hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); + /* ISR loads it with new INT_STATUS */ + hdq_data->hdq_irqstatus = 0; + spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); + + hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val); + + /* set the GO bit */ + hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO, + OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); + /* wait for the TXCOMPLETE bit */ + ret = wait_event_timeout(hdq_wait_queue, + hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); + if (ret == 0) { + dev_dbg(hdq_data->dev, "TX wait elapsed\n"); + goto out; + } + + *status = hdq_data->hdq_irqstatus; + /* check irqstatus */ + if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) { + dev_dbg(hdq_data->dev, "timeout waiting for" + "TXCOMPLETE/RXCOMPLETE, %x", *status); + ret = -ETIMEDOUT; + goto out; + } + + /* wait for the GO bit return to zero */ + ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_GO, + OMAP_HDQ_FLAG_CLEAR, &tmp_status); + if (ret) { + dev_dbg(hdq_data->dev, "timeout waiting GO bit" + "return to zero, %x", tmp_status); + } + +out: + return ret; +} + +/* HDQ Interrupt service routine */ +static irqreturn_t hdq_isr(int irq, void *_hdq) +{ + struct hdq_data *hdq_data = _hdq; + unsigned long irqflags; + + spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); + hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); + spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); + dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus); + + if (hdq_data->hdq_irqstatus & + (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE + | OMAP_HDQ_INT_STATUS_TIMEOUT)) { + /* wake up sleeping process */ + wake_up(&hdq_wait_queue); + } + + return IRQ_HANDLED; +} + +/* HDQ Mode: always return success */ +static u8 omap_w1_reset_bus(void *_hdq) +{ + return 0; +} + +/* W1 search callback function */ +static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev, + u8 search_type, w1_slave_found_callback slave_found) +{ + u64 module_id, rn_le, cs, id; + + if (w1_id) + module_id = w1_id; + else + module_id = 0x1; + + rn_le = cpu_to_le64(module_id); + /* + * HDQ might not obey truly the 1-wire spec. + * So calculate CRC based on module parameter. + */ + cs = w1_calc_crc8((u8 *)&rn_le, 7); + id = (cs << 56) | module_id; + + slave_found(master_dev, id); +} + +static int _omap_hdq_reset(struct hdq_data *hdq_data) +{ + int ret; + u8 tmp_status; + + hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET); + /* + * Select HDQ mode & enable clocks. + * It is observed that INT flags can't be cleared via a read and GO/INIT + * won't return to zero if interrupt is disabled. So we always enable + * interrupt. + */ + hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_CLOCKENABLE | + OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK); + + /* wait for reset to complete */ + ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS, + OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status); + if (ret) + dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x", + tmp_status); + else { + hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_CLOCKENABLE | + OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK); + hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, + OMAP_HDQ_SYSCONFIG_AUTOIDLE); + } + + return ret; +} + +/* Issue break pulse to the device */ +static int omap_hdq_break(struct hdq_data *hdq_data) +{ + int ret = 0; + u8 tmp_status; + unsigned long irqflags; + + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); + ret = -EINTR; + goto rtn; + } + + spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); + /* clear interrupt flags via a dummy read */ + hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); + /* ISR loads it with new INT_STATUS */ + hdq_data->hdq_irqstatus = 0; + spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); + + /* set the INIT and GO bit */ + hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO, + OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION | + OMAP_HDQ_CTRL_STATUS_GO); + + /* wait for the TIMEOUT bit */ + ret = wait_event_timeout(hdq_wait_queue, + hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); + if (ret == 0) { + dev_dbg(hdq_data->dev, "break wait elapsed\n"); + ret = -EINTR; + goto out; + } + + tmp_status = hdq_data->hdq_irqstatus; + /* check irqstatus */ + if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) { + dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x", + tmp_status); + ret = -ETIMEDOUT; + goto out; + } + /* + * wait for both INIT and GO bits rerurn to zero. + * zero wait time expected for interrupt mode. + */ + ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_INITIALIZATION | + OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR, + &tmp_status); + if (ret) + dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits" + "return to zero, %x", tmp_status); + +out: + mutex_unlock(&hdq_data->hdq_mutex); +rtn: + return ret; +} + +static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) +{ + int ret = 0; + u8 status; + unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT; + + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + ret = -EINTR; + goto rtn; + } + + if (!hdq_data->hdq_usecount) { + ret = -EINVAL; + goto out; + } + + if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { + hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO, + OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); + /* + * The RX comes immediately after TX. It + * triggers another interrupt before we + * sleep. So we have to wait for RXCOMPLETE bit. + */ + while (!(hdq_data->hdq_irqstatus + & OMAP_HDQ_INT_STATUS_RXCOMPLETE) + && time_before(jiffies, timeout)) { + schedule_timeout_uninterruptible(1); + } + hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0, + OMAP_HDQ_CTRL_STATUS_DIR); + status = hdq_data->hdq_irqstatus; + /* check irqstatus */ + if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { + dev_dbg(hdq_data->dev, "timeout waiting for" + "RXCOMPLETE, %x", status); + ret = -ETIMEDOUT; + goto out; + } + } + /* the data is ready. Read it in! */ + *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA); +out: + mutex_unlock(&hdq_data->hdq_mutex); +rtn: + return 0; + +} + +/* Enable clocks and set the controller to HDQ mode */ +static int omap_hdq_get(struct hdq_data *hdq_data) +{ + int ret = 0; + + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + ret = -EINTR; + goto rtn; + } + + if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) { + dev_dbg(hdq_data->dev, "attempt to exceed the max use count"); + ret = -EINVAL; + goto out; + } else { + hdq_data->hdq_usecount++; + try_module_get(THIS_MODULE); + if (1 == hdq_data->hdq_usecount) { + if (clk_enable(hdq_data->hdq_ick)) { + dev_dbg(hdq_data->dev, "Can not enable ick\n"); + ret = -ENODEV; + goto clk_err; + } + if (clk_enable(hdq_data->hdq_fck)) { + dev_dbg(hdq_data->dev, "Can not enable fck\n"); + clk_disable(hdq_data->hdq_ick); + ret = -ENODEV; + goto clk_err; + } + + /* make sure HDQ is out of reset */ + if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) & + OMAP_HDQ_SYSSTATUS_RESETDONE)) { + ret = _omap_hdq_reset(hdq_data); + if (ret) + /* back up the count */ + hdq_data->hdq_usecount--; + } else { + /* select HDQ mode & enable clocks */ + hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS, + OMAP_HDQ_CTRL_STATUS_CLOCKENABLE | + OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK); + hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, + OMAP_HDQ_SYSCONFIG_AUTOIDLE); + hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); + } + } + } + +clk_err: + clk_put(hdq_data->hdq_ick); + clk_put(hdq_data->hdq_fck); +out: + mutex_unlock(&hdq_data->hdq_mutex); +rtn: + return ret; +} + +/* Disable clocks to the module */ +static int omap_hdq_put(struct hdq_data *hdq_data) +{ + int ret = 0; + + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) + return -EINTR; + + if (0 == hdq_data->hdq_usecount) { + dev_dbg(hdq_data->dev, "attempt to decrement use count" + "when it is zero"); + ret = -EINVAL; + } else { + hdq_data->hdq_usecount--; + module_put(THIS_MODULE); + if (0 == hdq_data->hdq_usecount) { + clk_disable(hdq_data->hdq_ick); + clk_disable(hdq_data->hdq_fck); + } + } + mutex_unlock(&hdq_data->hdq_mutex); + + return ret; +} + +/* Read a byte of data from the device */ +static u8 omap_w1_read_byte(void *_hdq) +{ + struct hdq_data *hdq_data = _hdq; + u8 val = 0; + int ret; + + ret = hdq_read_byte(hdq_data, &val); + if (ret) { + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); + return -EINTR; + } + hdq_data->init_trans = 0; + mutex_unlock(&hdq_data->hdq_mutex); + omap_hdq_put(hdq_data); + return -1; + } + + /* Write followed by a read, release the module */ + if (hdq_data->init_trans) { + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); + return -EINTR; + } + hdq_data->init_trans = 0; + mutex_unlock(&hdq_data->hdq_mutex); + omap_hdq_put(hdq_data); + } + + return val; +} + +/* Write a byte of data to the device */ +static void omap_w1_write_byte(void *_hdq, u8 byte) +{ + struct hdq_data *hdq_data = _hdq; + int ret; + u8 status; + + /* First write to initialize the transfer */ + if (hdq_data->init_trans == 0) + omap_hdq_get(hdq_data); + + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); + return; + } + hdq_data->init_trans++; + mutex_unlock(&hdq_data->hdq_mutex); + + ret = hdq_write_byte(hdq_data, byte, &status); + if (ret == 0) { + dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status); + return; + } + + /* Second write, data transfered. Release the module */ + if (hdq_data->init_trans > 1) { + omap_hdq_put(hdq_data); + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); + return; + } + hdq_data->init_trans = 0; + mutex_unlock(&hdq_data->hdq_mutex); + } + + return; +} + +static int __init omap_hdq_probe(struct platform_device *pdev) +{ + struct hdq_data *hdq_data; + struct resource *res; + int ret, irq; + u8 rev; + + hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL); + if (!hdq_data) { + dev_dbg(&pdev->dev, "unable to allocate memory\n"); + ret = -ENOMEM; + goto err_kmalloc; + } + + hdq_data->dev = &pdev->dev; + platform_set_drvdata(pdev, hdq_data); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "unable to get resource\n"); + ret = -ENXIO; + goto err_resource; + } + + hdq_data->hdq_base = ioremap(res->start, SZ_4K); + if (!hdq_data->hdq_base) { + dev_dbg(&pdev->dev, "ioremap failed\n"); + ret = -EINVAL; + goto err_ioremap; + } + + /* get interface & functional clock objects */ + hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick"); + hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck"); + + if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) { + dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n"); + if (IS_ERR(hdq_data->hdq_ick)) { + ret = PTR_ERR(hdq_data->hdq_ick); + goto err_clk; + } + if (IS_ERR(hdq_data->hdq_fck)) { + ret = PTR_ERR(hdq_data->hdq_fck); + clk_put(hdq_data->hdq_ick); + goto err_clk; + } + } + + hdq_data->hdq_usecount = 0; + mutex_init(&hdq_data->hdq_mutex); + + if (clk_enable(hdq_data->hdq_ick)) { + dev_dbg(&pdev->dev, "Can not enable ick\n"); + ret = -ENODEV; + goto err_intfclk; + } + + if (clk_enable(hdq_data->hdq_fck)) { + dev_dbg(&pdev->dev, "Can not enable fck\n"); + ret = -ENODEV; + goto err_fnclk; + } + + rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION); + dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n", + (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt"); + + spin_lock_init(&hdq_data->hdq_spinlock); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = -ENXIO; + goto err_irq; + } + + ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data); + if (ret < 0) { + dev_dbg(&pdev->dev, "could not request irq\n"); + goto err_irq; + } + + omap_hdq_break(hdq_data); + + /* don't clock the HDQ until it is needed */ + clk_disable(hdq_data->hdq_ick); + clk_disable(hdq_data->hdq_fck); + + omap_w1_master.data = hdq_data; + + ret = w1_add_master_device(&omap_w1_master); + if (ret) { + dev_dbg(&pdev->dev, "Failure in registering w1 master\n"); + goto err_w1; + } + + return 0; + +err_w1: +err_irq: + clk_disable(hdq_data->hdq_fck); + +err_fnclk: + clk_disable(hdq_data->hdq_ick); + +err_intfclk: + clk_put(hdq_data->hdq_ick); + clk_put(hdq_data->hdq_fck); + +err_clk: + iounmap(hdq_data->hdq_base); + +err_ioremap: +err_resource: + platform_set_drvdata(pdev, NULL); + kfree(hdq_data); + +err_kmalloc: + return ret; + +} + +static int omap_hdq_remove(struct platform_device *pdev) +{ + struct hdq_data *hdq_data = platform_get_drvdata(pdev); + + mutex_lock(&hdq_data->hdq_mutex); + + if (hdq_data->hdq_usecount) { + dev_dbg(&pdev->dev, "removed when use count is not zero\n"); + return -EBUSY; + } + + mutex_unlock(&hdq_data->hdq_mutex); + + /* remove module dependency */ + clk_put(hdq_data->hdq_ick); + clk_put(hdq_data->hdq_fck); + free_irq(INT_24XX_HDQ_IRQ, hdq_data); + platform_set_drvdata(pdev, NULL); + iounmap(hdq_data->hdq_base); + kfree(hdq_data); + + return 0; +} + +static int __init +omap_hdq_init(void) +{ + return platform_driver_register(&omap_hdq_driver); +} +module_init(omap_hdq_init); + +static void __exit +omap_hdq_exit(void) +{ + platform_driver_unregister(&omap_hdq_driver); +} +module_exit(omap_hdq_exit); + +module_param(w1_id, int, S_IRUSR); +MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection"); + +MODULE_AUTHOR("Texas Instruments"); +MODULE_DESCRIPTION("HDQ driver Library"); +MODULE_LICENSE("GPL"); diff --git a/drivers/w1/slaves/Kconfig b/drivers/w1/slaves/Kconfig index 3df29a122f84..8d0b1fb1e52e 100644 --- a/drivers/w1/slaves/Kconfig +++ b/drivers/w1/slaves/Kconfig @@ -44,4 +44,11 @@ config W1_SLAVE_DS2760 If you are unsure, say N. +config W1_SLAVE_BQ27000 + tristate "BQ27000 slave support" + depends on W1 + help + Say Y here if you want to use a hdq + bq27000 slave support. + endmenu diff --git a/drivers/w1/slaves/Makefile b/drivers/w1/slaves/Makefile index a8eb7524df1d..990f400b6d22 100644 --- a/drivers/w1/slaves/Makefile +++ b/drivers/w1/slaves/Makefile @@ -6,4 +6,4 @@ obj-$(CONFIG_W1_SLAVE_THERM) += w1_therm.o obj-$(CONFIG_W1_SLAVE_SMEM) += w1_smem.o obj-$(CONFIG_W1_SLAVE_DS2433) += w1_ds2433.o obj-$(CONFIG_W1_SLAVE_DS2760) += w1_ds2760.o - +obj-$(CONFIG_W1_SLAVE_BQ27000) += w1_bq27000.o diff --git a/drivers/w1/slaves/w1_bq27000.c b/drivers/w1/slaves/w1_bq27000.c new file mode 100644 index 000000000000..8f4c91f6c680 --- /dev/null +++ b/drivers/w1/slaves/w1_bq27000.c @@ -0,0 +1,123 @@ +/* + * drivers/w1/slaves/w1_bq27000.c + * + * Copyright (C) 2007 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "../w1.h" +#include "../w1_int.h" +#include "../w1_family.h" + +#define HDQ_CMD_READ (0) +#define HDQ_CMD_WRITE (1<<7) + +static int F_ID; + +void w1_bq27000_write(struct device *dev, u8 buf, u8 reg) +{ + struct w1_slave *sl = container_of(dev, struct w1_slave, dev); + + if (!dev) { + pr_info("Could not obtain slave dev ptr\n"); + return; + } + + w1_write_8(sl->master, HDQ_CMD_WRITE | reg); + w1_write_8(sl->master, buf); +} +EXPORT_SYMBOL(w1_bq27000_write); + +int w1_bq27000_read(struct device *dev, u8 reg) +{ + u8 val; + struct w1_slave *sl = container_of(dev, struct w1_slave, dev); + + if (!dev) + return 0; + + w1_write_8(sl->master, HDQ_CMD_READ | reg); + val = w1_read_8(sl->master); + + return val; +} +EXPORT_SYMBOL(w1_bq27000_read); + +static int w1_bq27000_add_slave(struct w1_slave *sl) +{ + int ret; + int id = 1; + struct platform_device *pdev; + + pdev = platform_device_alloc("bq27000-battery", id); + if (!pdev) { + ret = -ENOMEM; + return ret; + } + pdev->dev.parent = &sl->dev; + + ret = platform_device_add(pdev); + if (ret) + goto pdev_add_failed; + + dev_set_drvdata(&sl->dev, pdev); + + goto success; + +pdev_add_failed: + platform_device_unregister(pdev); +success: + return ret; +} + +static void w1_bq27000_remove_slave(struct w1_slave *sl) +{ + struct platform_device *pdev = dev_get_drvdata(&sl->dev); + + platform_device_unregister(pdev); +} + +static struct w1_family_ops w1_bq27000_fops = { + .add_slave = w1_bq27000_add_slave, + .remove_slave = w1_bq27000_remove_slave, +}; + +static struct w1_family w1_bq27000_family = { + .fid = 1, + .fops = &w1_bq27000_fops, +}; + +static int __init w1_bq27000_init(void) +{ + if (F_ID) + w1_bq27000_family.fid = F_ID; + + return w1_register_family(&w1_bq27000_family); +} + +static void __exit w1_bq27000_exit(void) +{ + w1_unregister_family(&w1_bq27000_family); +} + + +module_init(w1_bq27000_init); +module_exit(w1_bq27000_exit); + +module_param(F_ID, int, S_IRUSR); +MODULE_PARM_DESC(F_ID, "1-wire slave FID for BQ device"); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Texas Instruments Ltd"); +MODULE_DESCRIPTION("HDQ/1-wire slave driver bq27000 battery monitor chip"); diff --git a/drivers/w1/w1.h b/drivers/w1/w1.h index cdaa6fffbfc7..97304bd83ec9 100644 --- a/drivers/w1/w1.h +++ b/drivers/w1/w1.h @@ -206,6 +206,7 @@ void w1_slave_detach(struct w1_slave *sl); u8 w1_triplet(struct w1_master *dev, int bdir); void w1_write_8(struct w1_master *, u8); +u8 w1_read_8(struct w1_master *); int w1_reset_bus(struct w1_master *); u8 w1_calc_crc8(u8 *, int); void w1_write_block(struct w1_master *, const u8 *, int); diff --git a/drivers/w1/w1_io.c b/drivers/w1/w1_io.c index f4f82f1f486e..0d15b0eaf79a 100644 --- a/drivers/w1/w1_io.c +++ b/drivers/w1/w1_io.c @@ -217,7 +217,7 @@ u8 w1_triplet(struct w1_master *dev, int bdir) * @param dev the master device * @return the byte read */ -static u8 w1_read_8(struct w1_master * dev) +u8 w1_read_8(struct w1_master *dev) { int i; u8 res = 0; @@ -230,6 +230,7 @@ static u8 w1_read_8(struct w1_master * dev) return res; } +EXPORT_SYMBOL_GPL(w1_read_8); /** * Writes a series of bytes. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 1a22fe782a27..4fd3fa5546b1 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -67,11 +67,11 @@ config AT91RM9200_WATCHDOG system when the timeout is reached. config AT91SAM9X_WATCHDOG - tristate "AT91SAM9X watchdog" - depends on WATCHDOG && (ARCH_AT91SAM9260 || ARCH_AT91SAM9261) + tristate "AT91SAM9X / AT91CAP9 watchdog" + depends on ARCH_AT91 && !ARCH_AT91RM9200 help - Watchdog timer embedded into AT91SAM9X chips. This will reboot your - system when the timeout is reached. + Watchdog timer embedded into AT91SAM9X and AT91CAP9 chips. This will + reboot your system when the timeout is reached. config 21285_WATCHDOG tristate "DC21285 watchdog" diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 6e46a551395c..3e57aa4d643a 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -3,8 +3,8 @@ * * Based on wdt.c. Original copyright messages: * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -15,7 +15,7 @@ * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * - * (c) Copyright 1995 Alan Cox + * (c) Copyright 1995 Alan Cox * * 14-Dec-2001 Matt Domsch * Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index a5110f93a755..a1d7856ea6e0 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c @@ -6,8 +6,8 @@ * Based on acquirewdt.c which is based on wdt.c. * Original copyright messages: * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,7 +18,7 @@ * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * - * (c) Copyright 1995 Alan Cox + * (c) Copyright 1995 Alan Cox * * 14-Dec-2001 Matt Domsch * Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index b4babfc31586..b1da287f90ec 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -30,7 +30,7 @@ #include #include -#include +#include #define DRV_NAME "AT91SAM9 Watchdog" diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 31b42253054e..067a57cb3f82 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -5,7 +5,7 @@ * Originally based on softdog.c * Copyright 2006-2007 Analog Devices Inc. * Copyright 2006-2007 Michele d'Amico - * Copyright 1996 Alan Cox + * Copyright 1996 Alan Cox * * Enter bugs at http://blackfin.uclinux.org/ * diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index c3b78a76f173..225398fd5049 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c @@ -42,8 +42,10 @@ u32 booke_wdt_period = WDT_PERIOD_DEFAULT; #ifdef CONFIG_FSL_BOOKE #define WDTP(x) ((((63-x)&0x3)<<30)|(((63-x)&0x3c)<<15)) +#define WDTP_MASK (WDTP(0)) #else #define WDTP(x) (TCR_WP(x)) +#define WDTP_MASK (TCR_WP_MASK) #endif static DEFINE_SPINLOCK(booke_wdt_lock); @@ -65,6 +67,7 @@ static void __booke_wdt_enable(void *data) /* clear status before enabling watchdog */ __booke_wdt_ping(NULL); val = mfspr(SPRN_TCR); + val &= ~WDTP_MASK; val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period)); mtspr(SPRN_TCR, val); @@ -114,7 +117,7 @@ static long booke_wdt_ioctl(struct file *file, case WDIOC_SETTIMEOUT: if (get_user(booke_wdt_period, p)) return -EFAULT; - mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WDTP(0)) | + mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WDTP_MASK) | WDTP(booke_wdt_period)); return 0; case WDIOC_GETTIMEOUT: diff --git a/drivers/watchdog/eurotechwdt.c b/drivers/watchdog/eurotechwdt.c index bbd14e34319f..a171fc6ae1cb 100644 --- a/drivers/watchdog/eurotechwdt.c +++ b/drivers/watchdog/eurotechwdt.c @@ -8,8 +8,8 @@ * Based on wdt.c. * Original copyright messages: * - * (c) Copyright 1996-1997 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996-1997 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index a3765e0be4a8..763c1ea5dce5 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c @@ -40,6 +40,7 @@ #include #include #include +#include #define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */ #define CRU_BIOS_SIGNATURE_VALUE 0x55524324 @@ -394,6 +395,8 @@ static void __devinit dmi_find_cru(const struct dmi_header *dm) smbios_cru64_ptr->double_offset; cru_rom_addr = ioremap(cru_physical_address, smbios_cru64_ptr->double_length); + set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK, + smbios_cru64_ptr->double_length >> PAGE_SHIFT); } } } @@ -482,7 +485,7 @@ static int hpwdt_pretimeout(struct notifier_block *nb, unsigned long ulReason, "Management Log for details.\n"); } - return NOTIFY_STOP; + return NOTIFY_OK; } /* diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index c13383f7fcb9..74f951c18b90 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -394,8 +394,7 @@ static unsigned char __init esb_getdevice(void) goto err_disable; } - BASEADDR = ioremap(pci_resource_start(esb_pci, 0), - pci_resource_len(esb_pci, 0)); + BASEADDR = pci_ioremap_bar(esb_pci, 0); if (BASEADDR == NULL) { /* Something's wrong here, BASEADDR has to be set */ printk(KERN_ERR PFX "failed to get BASEADDR\n"); diff --git a/drivers/watchdog/iTCO_vendor_support.c b/drivers/watchdog/iTCO_vendor_support.c index ca344a85eb95..2474ebca88f6 100644 --- a/drivers/watchdog/iTCO_vendor_support.c +++ b/drivers/watchdog/iTCO_vendor_support.c @@ -1,7 +1,7 @@ /* * intel TCO vendor specific watchdog driver support * - * (c) Copyright 2006 Wim Van Sebroeck . + * (c) Copyright 2006-2008 Wim Van Sebroeck . * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -19,8 +19,7 @@ /* Module and version information */ #define DRV_NAME "iTCO_vendor_support" -#define DRV_VERSION "1.01" -#define DRV_RELDATE "11-Nov-2006" +#define DRV_VERSION "1.02" #define PFX DRV_NAME ": " /* Includes */ @@ -78,24 +77,6 @@ MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (n * 20.6 seconds. */ -static void supermicro_old_pre_start(unsigned long acpibase) -{ - unsigned long val32; - - val32 = inl(SMI_EN); - val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ - outl(val32, SMI_EN); /* Needed to activate watchdog */ -} - -static void supermicro_old_pre_stop(unsigned long acpibase) -{ - unsigned long val32; - - val32 = inl(SMI_EN); - val32 &= 0x00002000; /* Turn on SMI clearing watchdog */ - outl(val32, SMI_EN); /* Needed to deactivate watchdog */ -} - static void supermicro_old_pre_keepalive(unsigned long acpibase) { /* Reload TCO Timer (done in iTCO_wdt_keepalive) + */ @@ -247,18 +228,14 @@ static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat) void iTCO_vendor_pre_start(unsigned long acpibase, unsigned int heartbeat) { - if (vendorsupport == SUPERMICRO_OLD_BOARD) - supermicro_old_pre_start(acpibase); - else if (vendorsupport == SUPERMICRO_NEW_BOARD) + if (vendorsupport == SUPERMICRO_NEW_BOARD) supermicro_new_pre_start(heartbeat); } EXPORT_SYMBOL(iTCO_vendor_pre_start); void iTCO_vendor_pre_stop(unsigned long acpibase) { - if (vendorsupport == SUPERMICRO_OLD_BOARD) - supermicro_old_pre_stop(acpibase); - else if (vendorsupport == SUPERMICRO_NEW_BOARD) + if (vendorsupport == SUPERMICRO_NEW_BOARD) supermicro_new_pre_stop(); } EXPORT_SYMBOL(iTCO_vendor_pre_stop); diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index bfb93bc2ca9f..5b395a4ddfdf 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -1,7 +1,7 @@ /* * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets) * - * (c) Copyright 2006-2007 Wim Van Sebroeck . + * (c) Copyright 2006-2008 Wim Van Sebroeck . * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,34 +20,41 @@ * 82801BAM (ICH2-M) : document number 290687-002, 298242-027, * 82801CA (ICH3-S) : document number 290733-003, 290739-013, * 82801CAM (ICH3-M) : document number 290716-001, 290718-007, - * 82801DB (ICH4) : document number 290744-001, 290745-020, - * 82801DBM (ICH4-M) : document number 252337-001, 252663-005, + * 82801DB (ICH4) : document number 290744-001, 290745-025, + * 82801DBM (ICH4-M) : document number 252337-001, 252663-008, * 82801E (C-ICH) : document number 273599-001, 273645-002, - * 82801EB (ICH5) : document number 252516-001, 252517-003, - * 82801ER (ICH5R) : document number 252516-001, 252517-003, - * 82801FB (ICH6) : document number 301473-002, 301474-007, - * 82801FR (ICH6R) : document number 301473-002, 301474-007, - * 82801FBM (ICH6-M) : document number 301473-002, 301474-007, - * 82801FW (ICH6W) : document number 301473-001, 301474-007, - * 82801FRW (ICH6RW) : document number 301473-001, 301474-007, - * 82801GB (ICH7) : document number 307013-002, 307014-009, - * 82801GR (ICH7R) : document number 307013-002, 307014-009, - * 82801GDH (ICH7DH) : document number 307013-002, 307014-009, - * 82801GBM (ICH7-M) : document number 307013-002, 307014-009, - * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009, - * 82801HB (ICH8) : document number 313056-003, 313057-009, - * 82801HR (ICH8R) : document number 313056-003, 313057-009, - * 82801HBM (ICH8M) : document number 313056-003, 313057-009, - * 82801HH (ICH8DH) : document number 313056-003, 313057-009, - * 82801HO (ICH8DO) : document number 313056-003, 313057-009, - * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009, - * 82801IB (ICH9) : document number 316972-001, 316973-006, - * 82801IR (ICH9R) : document number 316972-001, 316973-006, - * 82801IH (ICH9DH) : document number 316972-001, 316973-006, - * 82801IO (ICH9DO) : document number 316972-001, 316973-006, - * 6300ESB (6300ESB) : document number 300641-003, 300884-010, - * 631xESB (631xESB) : document number 313082-001, 313075-005, - * 632xESB (632xESB) : document number 313082-001, 313075-005 + * 82801EB (ICH5) : document number 252516-001, 252517-028, + * 82801ER (ICH5R) : document number 252516-001, 252517-028, + * 6300ESB (6300ESB) : document number 300641-004, 300884-013, + * 82801FB (ICH6) : document number 301473-002, 301474-026, + * 82801FR (ICH6R) : document number 301473-002, 301474-026, + * 82801FBM (ICH6-M) : document number 301473-002, 301474-026, + * 82801FW (ICH6W) : document number 301473-001, 301474-026, + * 82801FRW (ICH6RW) : document number 301473-001, 301474-026, + * 631xESB (631xESB) : document number 313082-001, 313075-006, + * 632xESB (632xESB) : document number 313082-001, 313075-006, + * 82801GB (ICH7) : document number 307013-003, 307014-024, + * 82801GR (ICH7R) : document number 307013-003, 307014-024, + * 82801GDH (ICH7DH) : document number 307013-003, 307014-024, + * 82801GBM (ICH7-M) : document number 307013-003, 307014-024, + * 82801GHM (ICH7-M DH) : document number 307013-003, 307014-024, + * 82801GU (ICH7-U) : document number 307013-003, 307014-024, + * 82801HB (ICH8) : document number 313056-003, 313057-017, + * 82801HR (ICH8R) : document number 313056-003, 313057-017, + * 82801HBM (ICH8M) : document number 313056-003, 313057-017, + * 82801HH (ICH8DH) : document number 313056-003, 313057-017, + * 82801HO (ICH8DO) : document number 313056-003, 313057-017, + * 82801HEM (ICH8M-E) : document number 313056-003, 313057-017, + * 82801IB (ICH9) : document number 316972-004, 316973-012, + * 82801IR (ICH9R) : document number 316972-004, 316973-012, + * 82801IH (ICH9DH) : document number 316972-004, 316973-012, + * 82801IO (ICH9DO) : document number 316972-004, 316973-012, + * 82801IBM (ICH9M) : document number 316972-004, 316973-012, + * 82801IEM (ICH9M-E) : document number 316972-004, 316973-012, + * 82801JIB (ICH10) : document number 319973-002, 319974-002, + * 82801JIR (ICH10R) : document number 319973-002, 319974-002, + * 82801JD (ICH10D) : document number 319973-002, 319974-002, + * 82801JDO (ICH10DO) : document number 319973-002, 319974-002 */ /* @@ -56,8 +63,7 @@ /* Module and version information */ #define DRV_NAME "iTCO_wdt" -#define DRV_VERSION "1.03" -#define DRV_RELDATE "30-Apr-2008" +#define DRV_VERSION "1.04" #define PFX DRV_NAME ": " /* Includes */ @@ -96,19 +102,26 @@ enum iTCO_chipsets { TCO_ICH6, /* ICH6 & ICH6R */ TCO_ICH6M, /* ICH6-M */ TCO_ICH6W, /* ICH6W & ICH6RW */ + TCO_631XESB, /* 631xESB/632xESB */ TCO_ICH7, /* ICH7 & ICH7R */ - TCO_ICH7M, /* ICH7-M */ + TCO_ICH7DH, /* ICH7DH */ + TCO_ICH7M, /* ICH7-M & ICH7-U */ TCO_ICH7MDH, /* ICH7-M DH */ TCO_ICH8, /* ICH8 & ICH8R */ - TCO_ICH8ME, /* ICH8M-E */ TCO_ICH8DH, /* ICH8DH */ TCO_ICH8DO, /* ICH8DO */ TCO_ICH8M, /* ICH8M */ + TCO_ICH8ME, /* ICH8M-E */ TCO_ICH9, /* ICH9 */ TCO_ICH9R, /* ICH9R */ TCO_ICH9DH, /* ICH9DH */ TCO_ICH9DO, /* ICH9DO */ - TCO_631XESB, /* 631xESB/632xESB */ + TCO_ICH9M, /* ICH9M */ + TCO_ICH9ME, /* ICH9M-E */ + TCO_ICH10, /* ICH10 */ + TCO_ICH10R, /* ICH10R */ + TCO_ICH10D, /* ICH10D */ + TCO_ICH10DO, /* ICH10DO */ }; static struct { @@ -129,19 +142,26 @@ static struct { {"ICH6 or ICH6R", 2}, {"ICH6-M", 2}, {"ICH6W or ICH6RW", 2}, + {"631xESB/632xESB", 2}, {"ICH7 or ICH7R", 2}, - {"ICH7-M", 2}, + {"ICH7DH", 2}, + {"ICH7-M or ICH7-U", 2}, {"ICH7-M DH", 2}, {"ICH8 or ICH8R", 2}, - {"ICH8M-E", 2}, {"ICH8DH", 2}, {"ICH8DO", 2}, {"ICH8M", 2}, + {"ICH8M-E", 2}, {"ICH9", 2}, {"ICH9R", 2}, {"ICH9DH", 2}, {"ICH9DO", 2}, - {"631xESB/632xESB", 2}, + {"ICH9M", 2}, + {"ICH9M-E", 2}, + {"ICH10", 2}, + {"ICH10R", 2}, + {"ICH10D", 2}, + {"ICH10DO", 2}, {NULL, 0} }; @@ -175,18 +195,6 @@ static struct pci_device_id iTCO_wdt_pci_tbl[] = { { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)}, { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)}, { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, - { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, - { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, @@ -203,6 +211,25 @@ static struct pci_device_id iTCO_wdt_pci_tbl[] = { { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)}, { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)}, { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, + { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, + { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, + { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)}, + { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)}, + { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)}, + { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)}, + { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)}, + { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)}, { 0, }, /* End of list */ }; MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl); @@ -311,6 +338,7 @@ static int iTCO_wdt_unset_NO_REBOOT_bit(void) static int iTCO_wdt_start(void) { unsigned int val; + unsigned long val32; spin_lock(&iTCO_wdt_private.io_lock); @@ -323,6 +351,18 @@ static int iTCO_wdt_start(void) return -EIO; } + /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ + val32 = inl(SMI_EN); + val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ + outl(val32, SMI_EN); + + /* Force the timer to its reload value by writing to the TCO_RLD + register */ + if (iTCO_wdt_private.iTCO_version == 2) + outw(0x01, TCO_RLD); + else if (iTCO_wdt_private.iTCO_version == 1) + outb(0x01, TCO_RLD); + /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ val = inw(TCO1_CNT); val &= 0xf7ff; @@ -338,6 +378,7 @@ static int iTCO_wdt_start(void) static int iTCO_wdt_stop(void) { unsigned int val; + unsigned long val32; spin_lock(&iTCO_wdt_private.io_lock); @@ -349,6 +390,11 @@ static int iTCO_wdt_stop(void) outw(val, TCO1_CNT); val = inw(TCO1_CNT); + /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */ + val32 = inl(SMI_EN); + val32 |= 0x00002000; + outl(val32, SMI_EN); + /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ iTCO_wdt_set_NO_REBOOT_bit(); @@ -459,7 +505,6 @@ static int iTCO_wdt_open(struct inode *inode, struct file *file) /* * Reload and activate timer */ - iTCO_wdt_keepalive(); iTCO_wdt_start(); return nonseekable_open(inode, file); } @@ -604,7 +649,6 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, int ret; u32 base_address; unsigned long RCBA; - unsigned long val32; /* * Find the ACPI/PM base I/O address which is the base @@ -644,17 +688,13 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ iTCO_wdt_set_NO_REBOOT_bit(); - /* Set the TCO_EN bit in SMI_EN register */ + /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ if (!request_region(SMI_EN, 4, "iTCO_wdt")) { printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", SMI_EN); ret = -EIO; goto out; } - val32 = inl(SMI_EN); - val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ - outl(val32, SMI_EN); - release_region(SMI_EN, 4); /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */ @@ -662,7 +702,7 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", TCOBASE); ret = -EIO; - goto out; + goto unreg_smi_en; } printk(KERN_INFO PFX @@ -672,8 +712,9 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, TCOBASE); /* Clear out the (probably old) status */ - outb(0, TCO1_STS); - outb(3, TCO2_STS); + outb(8, TCO1_STS); /* Clear the Time Out Status bit */ + outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */ + outb(4, TCO2_STS); /* Clear BOOT_STS bit */ /* Make sure the watchdog is not running */ iTCO_wdt_stop(); @@ -701,6 +742,8 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, unreg_region: release_region(TCOBASE, 0x20); +unreg_smi_en: + release_region(SMI_EN, 4); out: if (iTCO_wdt_private.iTCO_version == 2) iounmap(iTCO_wdt_private.gcs); @@ -718,6 +761,7 @@ static void __devexit iTCO_wdt_cleanup(void) /* Deregister */ misc_deregister(&iTCO_wdt_miscdev); release_region(TCOBASE, 0x20); + release_region(SMI_EN, 4); if (iTCO_wdt_private.iTCO_version == 2) iounmap(iTCO_wdt_private.gcs); pci_dev_put(iTCO_wdt_private.pdev); @@ -782,8 +826,8 @@ static int __init iTCO_wdt_init_module(void) { int err; - printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n", - DRV_VERSION, DRV_RELDATE); + printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n", + DRV_VERSION); err = platform_driver_register(&iTCO_wdt_driver); if (err) diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 8782ec1f5aa0..317ef2b16cff 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c @@ -11,8 +11,8 @@ * Based on acquirewdt.c which is based on wdt.c. * Original copyright messages: * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -23,7 +23,7 @@ * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * - * (c) Copyright 1995 Alan Cox + * (c) Copyright 1995 Alan Cox * * 14-Dec-2001 Matt Domsch * Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT diff --git a/drivers/watchdog/indydog.c b/drivers/watchdog/indydog.c index 73c9e7992feb..0f761db9a27c 100644 --- a/drivers/watchdog/indydog.c +++ b/drivers/watchdog/indydog.c @@ -9,7 +9,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * based on softdog.c by Alan Cox + * based on softdog.c by Alan Cox */ #include diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index 2a9bfa81f9d6..1130ad697ce2 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c @@ -4,8 +4,8 @@ * (c) Copyright 2004 ARM Limited * * Based on the SoftDog driver: - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index b4b7b0a4c119..3acce623f209 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c @@ -98,6 +98,8 @@ static void mtx1_wdt_reset(void) static void mtx1_wdt_start(void) { + unsigned long flags; + spin_lock_irqsave(&mtx1_wdt_device.lock, flags); if (!mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 1; @@ -110,6 +112,8 @@ static void mtx1_wdt_start(void) static int mtx1_wdt_stop(void) { + unsigned long flags; + spin_lock_irqsave(&mtx1_wdt_device.lock, flags); if (mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 0; diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7bcbb7f4745f..2f2ce7429f5b 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -16,7 +16,7 @@ * 20030527: George G. Davis * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c * (c) Copyright 2000 Oleg Drokin - * Based on SoftDog driver by Alan Cox + * Based on SoftDog driver by Alan Cox * * Copyright (c) 2004 Texas Instruments. * 1. Modified to support OMAP1610 32-KHz watchdog timer diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 90eb1d4271d7..5d76422c402c 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -6,7 +6,7 @@ * Based on source code of the following authors: * Ken Hollis , * Lindsay Harris , - * Alan Cox , + * Alan Cox , * Matt Domsch , * Rob Radez * diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index c1685c942de6..afb089695da8 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -5,7 +5,7 @@ * * Based on source code of the following authors: * Ken Hollis , - * Alan Cox , + * Alan Cox , * Matt Domsch , * Rob Radez , * Greg Kroah-Hartman diff --git a/drivers/watchdog/rc32434_wdt.c b/drivers/watchdog/rc32434_wdt.c index c9c73b69c5e5..57027f4653ce 100644 --- a/drivers/watchdog/rc32434_wdt.c +++ b/drivers/watchdog/rc32434_wdt.c @@ -7,7 +7,8 @@ * based on * SoftDog 0.05: A Software Watchdog Device * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 86d42801de45..f7f6ce82a5e2 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -6,7 +6,7 @@ * S3C2410 Watchdog Timer Support * * Based on, softdog.c by Alan Cox, - * (c) Copyright 1996 Alan Cox + * (c) Copyright 1996 Alan Cox * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index 31a48437dc3d..ed01e4c2beff 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c @@ -2,7 +2,7 @@ * Watchdog driver for the SA11x0/PXA2xx * * (c) Copyright 2000 Oleg Drokin - * Based on SoftDog driver by Alan Cox + * Based on SoftDog driver by Alan Cox * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index 27e526a07c9a..38f5831c9291 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c @@ -35,8 +35,8 @@ * Based on various other watchdog drivers, which are probably all * loosely based on something Alan Cox wrote years ago. * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/sbc8360.c b/drivers/watchdog/sbc8360.c index fd83dd052d8c..ae74f6bcfa23 100644 --- a/drivers/watchdog/sbc8360.c +++ b/drivers/watchdog/sbc8360.c @@ -16,8 +16,8 @@ * Based on acquirewdt.c which is based on wdt.c. * Original copyright messages: * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -28,7 +28,7 @@ * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * - * (c) Copyright 1995 Alan Cox + * (c) Copyright 1995 Alan Cox * * 14-Dec-2001 Matt Domsch * Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT diff --git a/drivers/watchdog/sbc_epx_c3.c b/drivers/watchdog/sbc_epx_c3.c index e5e470ca7759..06553debc7bc 100644 --- a/drivers/watchdog/sbc_epx_c3.c +++ b/drivers/watchdog/sbc_epx_c3.c @@ -10,7 +10,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * based on softdog.c by Alan Cox + * based on softdog.c by Alan Cox */ #include diff --git a/drivers/watchdog/smsc37b787_wdt.c b/drivers/watchdog/smsc37b787_wdt.c index 988ff1d5b4be..2e56cad77d19 100644 --- a/drivers/watchdog/smsc37b787_wdt.c +++ b/drivers/watchdog/smsc37b787_wdt.c @@ -1,7 +1,7 @@ /* * SMsC 37B787 Watchdog Timer driver for Linux 2.6.x.x * - * Based on acquirewdt.c by Alan Cox + * Based on acquirewdt.c by Alan Cox * and some other existing drivers * * This program is free software; you can redistribute it and/or diff --git a/drivers/watchdog/softdog.c b/drivers/watchdog/softdog.c index c650464c5c63..7204f9662114 100644 --- a/drivers/watchdog/softdog.c +++ b/drivers/watchdog/softdog.c @@ -1,8 +1,7 @@ /* * SoftDog 0.07: A Software Watchdog Device * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index 69396adaa5c3..916890abffdd 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c @@ -11,8 +11,8 @@ * * (c) Copyright 2000-2001 Marek Michalkiewicz * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -23,7 +23,7 @@ * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * - * (c) Copyright 1995 Alan Cox + * (c) Copyright 1995 Alan Cox */ #include diff --git a/drivers/watchdog/w83697hf_wdt.c b/drivers/watchdog/w83697hf_wdt.c index 445d30a01ed3..3c7aa412b1f3 100644 --- a/drivers/watchdog/w83697hf_wdt.c +++ b/drivers/watchdog/w83697hf_wdt.c @@ -12,8 +12,8 @@ * * (c) Copyright 2000-2001 Marek Michalkiewicz * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/wafer5823wdt.c b/drivers/watchdog/wafer5823wdt.c index 68377ae171ff..42e940c23891 100644 --- a/drivers/watchdog/wafer5823wdt.c +++ b/drivers/watchdog/wafer5823wdt.c @@ -10,8 +10,8 @@ * Based on advantechwdt.c which is based on wdt.c. * Original copyright messages: * - * (c) Copyright 1996-1997 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996-1997 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/wdt.c b/drivers/watchdog/wdt.c index deeebb2b13ea..eddb9187e7b6 100644 --- a/drivers/watchdog/wdt.c +++ b/drivers/watchdog/wdt.c @@ -1,8 +1,8 @@ /* * Industrial Computer Source WDT500/501 driver * - * (c) Copyright 1996-1997 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996-1997 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c index 191ea6302107..f55135662d78 100644 --- a/drivers/watchdog/wdt285.c +++ b/drivers/watchdog/wdt285.c @@ -6,7 +6,8 @@ * * SoftDog 0.05: A Software Watchdog Device * - * (c) Copyright 1996 Alan Cox , All Rights Reserved. + * (c) Copyright 1996 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/watchdog/wdt_pci.c b/drivers/watchdog/wdt_pci.c index ed02bdb38c09..c45839a4a34d 100644 --- a/drivers/watchdog/wdt_pci.c +++ b/drivers/watchdog/wdt_pci.c @@ -1,8 +1,8 @@ /* * Industrial Computer Source PCI-WDT500/501 driver * - * (c) Copyright 1996-1997 Alan Cox , All Rights Reserved. - * http://www.redhat.com + * (c) Copyright 1996-1997 Alan Cox , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/drivers/xen/balloon.c b/drivers/xen/balloon.c index 8c83abc73400..8dc7109d61b7 100644 --- a/drivers/xen/balloon.c +++ b/drivers/xen/balloon.c @@ -41,17 +41,18 @@ #include #include #include -#include #include #include -#include #include #include #include #include #include +#include +#include +#include #include #include #include @@ -123,14 +124,7 @@ static struct timer_list balloon_timer; static void scrub_page(struct page *page) { #ifdef CONFIG_XEN_SCRUB_PAGES - if (PageHighMem(page)) { - void *v = kmap(page); - clear_page(v); - kunmap(v); - } else { - void *v = page_address(page); - clear_page(v); - } + clear_highpage(page); #endif } diff --git a/drivers/xen/events.c b/drivers/xen/events.c index 9ce1ab6c268d..1e3b934a4cf7 100644 --- a/drivers/xen/events.c +++ b/drivers/xen/events.c @@ -774,7 +774,7 @@ void xen_poll_irq(int irq) poll.nr_ports = 1; poll.timeout = 0; - poll.ports = &evtchn; + set_xen_guest_handle(poll.ports, &evtchn); if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) BUG(); diff --git a/drivers/xen/features.c b/drivers/xen/features.c index 0707714e40d6..99eda169c779 100644 --- a/drivers/xen/features.c +++ b/drivers/xen/features.c @@ -8,7 +8,11 @@ #include #include #include -#include + +#include + +#include +#include #include u8 xen_features[XENFEAT_NR_SUBMAPS * 32] __read_mostly; diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c index 06592b9da83c..7d8f531fb8e8 100644 --- a/drivers/xen/grant-table.c +++ b/drivers/xen/grant-table.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include diff --git a/drivers/xen/manage.c b/drivers/xen/manage.c index d0e87cbe157c..9b91617b9582 100644 --- a/drivers/xen/manage.c +++ b/drivers/xen/manage.c @@ -39,8 +39,6 @@ static int xen_suspend(void *data) BUG_ON(!irqs_disabled()); - load_cr3(swapper_pg_dir); - err = device_power_down(PMSG_SUSPEND); if (err) { printk(KERN_ERR "xen_suspend: device_power_down failed: %d\n", diff --git a/drivers/xen/xencomm.c b/drivers/xen/xencomm.c index 797cb4e31f07..a240b2c20b99 100644 --- a/drivers/xen/xencomm.c +++ b/drivers/xen/xencomm.c @@ -23,13 +23,7 @@ #include #include #include -#ifdef __ia64__ -#include /* for is_kern_addr() */ -#endif - -#ifdef HAVE_XEN_PLATFORM_COMPAT_H -#include -#endif +#include /* for xencomm_is_phys_contiguous() */ static int xencomm_init(struct xencomm_desc *desc, void *buffer, unsigned long bytes) @@ -157,20 +151,11 @@ static int xencomm_create(void *buffer, unsigned long bytes, return 0; } -/* check if memory address is within VMALLOC region */ -static int is_phys_contiguous(unsigned long addr) -{ - if (!is_kernel_addr(addr)) - return 0; - - return (addr < VMALLOC_START) || (addr >= VMALLOC_END); -} - static struct xencomm_handle *xencomm_create_inline(void *ptr) { unsigned long paddr; - BUG_ON(!is_phys_contiguous((unsigned long)ptr)); + BUG_ON(!xencomm_is_phys_contiguous((unsigned long)ptr)); paddr = (unsigned long)xencomm_pa(ptr); BUG_ON(paddr & XENCOMM_INLINE_FLAG); @@ -202,7 +187,7 @@ struct xencomm_handle *xencomm_map(void *ptr, unsigned long bytes) int rc; struct xencomm_desc *desc; - if (is_phys_contiguous((unsigned long)ptr)) + if (xencomm_is_phys_contiguous((unsigned long)ptr)) return xencomm_create_inline(ptr); rc = xencomm_create(ptr, bytes, &desc, GFP_KERNEL); @@ -219,7 +204,7 @@ struct xencomm_handle *__xencomm_map_no_alloc(void *ptr, unsigned long bytes, int rc; struct xencomm_desc *desc = NULL; - if (is_phys_contiguous((unsigned long)ptr)) + if (xencomm_is_phys_contiguous((unsigned long)ptr)) return xencomm_create_inline(ptr); rc = xencomm_create_mini(ptr, bytes, xc_desc, diff --git a/fs/9p/fid.c b/fs/9p/fid.c index 3031e3233dd6..2a983d49d19c 100644 --- a/fs/9p/fid.c +++ b/fs/9p/fid.c @@ -45,7 +45,7 @@ int v9fs_fid_add(struct dentry *dentry, struct p9_fid *fid) struct v9fs_dentry *dent; P9_DPRINTK(P9_DEBUG_VFS, "fid %d dentry %s\n", - fid->fid, dentry->d_iname); + fid->fid, dentry->d_name.name); dent = dentry->d_fsdata; if (!dent) { @@ -79,7 +79,7 @@ static struct p9_fid *v9fs_fid_find(struct dentry *dentry, u32 uid, int any) struct p9_fid *fid, *ret; P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p) uid %d any %d\n", - dentry->d_iname, dentry, uid, any); + dentry->d_name.name, dentry, uid, any); dent = (struct v9fs_dentry *) dentry->d_fsdata; ret = NULL; if (dent) { diff --git a/fs/9p/v9fs.c b/fs/9p/v9fs.c index 24eb01087b6d..332b5ff02fec 100644 --- a/fs/9p/v9fs.c +++ b/fs/9p/v9fs.c @@ -160,7 +160,7 @@ static int v9fs_parse_options(struct v9fs_session_info *v9ses) v9ses->flags |= V9FS_ACCESS_ANY; else { v9ses->flags |= V9FS_ACCESS_SINGLE; - v9ses->uid = simple_strtol(s, &e, 10); + v9ses->uid = simple_strtoul(s, &e, 10); if (*e != '\0') v9ses->uid = ~0; } diff --git a/fs/9p/vfs_dentry.c b/fs/9p/vfs_dentry.c index f9534f18df0a..06dcc7c4f234 100644 --- a/fs/9p/vfs_dentry.c +++ b/fs/9p/vfs_dentry.c @@ -52,7 +52,8 @@ static int v9fs_dentry_delete(struct dentry *dentry) { - P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_iname, dentry); + P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_name.name, + dentry); return 1; } @@ -69,7 +70,8 @@ static int v9fs_dentry_delete(struct dentry *dentry) static int v9fs_cached_dentry_delete(struct dentry *dentry) { struct inode *inode = dentry->d_inode; - P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_iname, dentry); + P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_name.name, + dentry); if(!inode) return 1; @@ -88,7 +90,8 @@ void v9fs_dentry_release(struct dentry *dentry) struct v9fs_dentry *dent; struct p9_fid *temp, *current_fid; - P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_iname, dentry); + P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_name.name, + dentry); dent = dentry->d_fsdata; if (dent) { list_for_each_entry_safe(current_fid, temp, &dent->fidlist, diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 8314d3f43b71..2dfcf5487efe 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -963,7 +963,8 @@ static int v9fs_vfs_readlink(struct dentry *dentry, char __user * buffer, if (buflen > PATH_MAX) buflen = PATH_MAX; - P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_iname, dentry); + P9_DPRINTK(P9_DEBUG_VFS, " dentry: %s (%p)\n", dentry->d_name.name, + dentry); retval = v9fs_readlink(dentry, link, buflen); @@ -1022,7 +1023,8 @@ v9fs_vfs_put_link(struct dentry *dentry, struct nameidata *nd, void *p) { char *s = nd_get_link(nd); - P9_DPRINTK(P9_DEBUG_VFS, " %s %s\n", dentry->d_name.name, s); + P9_DPRINTK(P9_DEBUG_VFS, " %s %s\n", dentry->d_name.name, + IS_ERR(s) ? "" : s); if (!IS_ERR(s)) __putname(s); } diff --git a/fs/Makefile b/fs/Makefile index 2168c902d5ca..d9f8afe6f0c4 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -81,8 +81,6 @@ obj-$(CONFIG_HUGETLBFS) += hugetlbfs/ obj-$(CONFIG_CODA_FS) += coda/ obj-$(CONFIG_MINIX_FS) += minix/ obj-$(CONFIG_FAT_FS) += fat/ -obj-$(CONFIG_MSDOS_FS) += msdos/ -obj-$(CONFIG_VFAT_FS) += vfat/ obj-$(CONFIG_BFS_FS) += bfs/ obj-$(CONFIG_ISO9660_FS) += isofs/ obj-$(CONFIG_HFSPLUS_FS) += hfsplus/ # Before hfs to find wrapped HFS+ diff --git a/fs/autofs4/dev-ioctl.c b/fs/autofs4/dev-ioctl.c index 625abf5422e2..33bf8cbfd051 100644 --- a/fs/autofs4/dev-ioctl.c +++ b/fs/autofs4/dev-ioctl.c @@ -128,9 +128,10 @@ static inline void free_dev_ioctl(struct autofs_dev_ioctl *param) */ static int validate_dev_ioctl(int cmd, struct autofs_dev_ioctl *param) { - int err = -EINVAL; + int err; - if (check_dev_ioctl_version(cmd, param)) { + err = check_dev_ioctl_version(cmd, param); + if (err) { AUTOFS_WARN("invalid device control module version " "supplied for cmd(0x%08x)", cmd); goto out; diff --git a/fs/autofs4/expire.c b/fs/autofs4/expire.c index cde2f8e8935a..4b6fb3f628c0 100644 --- a/fs/autofs4/expire.c +++ b/fs/autofs4/expire.c @@ -56,12 +56,23 @@ static int autofs4_mount_busy(struct vfsmount *mnt, struct dentry *dentry) mntget(mnt); dget(dentry); - if (!autofs4_follow_mount(&mnt, &dentry)) + if (!follow_down(&mnt, &dentry)) goto done; - /* This is an autofs submount, we can't expire it */ - if (is_autofs4_dentry(dentry)) - goto done; + if (is_autofs4_dentry(dentry)) { + struct autofs_sb_info *sbi = autofs4_sbi(dentry->d_sb); + + /* This is an autofs submount, we can't expire it */ + if (sbi->type == AUTOFS_TYPE_INDIRECT) + goto done; + + /* + * Otherwise it's an offset mount and we need to check + * if we can umount its mount, if there is one. + */ + if (!d_mountpoint(dentry)) + goto done; + } /* Update the expiry counter if fs is busy */ if (!may_umount_tree(mnt)) { diff --git a/fs/block_dev.c b/fs/block_dev.c index 88a776fa0ef6..99e0ae1a4c78 100644 --- a/fs/block_dev.c +++ b/fs/block_dev.c @@ -986,7 +986,6 @@ static int __blkdev_put(struct block_device *bdev, fmode_t mode, int for_part); static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) { struct gendisk *disk; - struct hd_struct *part = NULL; int ret; int partno; int perm = 0; @@ -1004,24 +1003,25 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) return ret; } - ret = -ENXIO; - lock_kernel(); + ret = -ENXIO; disk = get_gendisk(bdev->bd_dev, &partno); if (!disk) goto out_unlock_kernel; - part = disk_get_part(disk, partno); - if (!part) - goto out_unlock_kernel; mutex_lock_nested(&bdev->bd_mutex, for_part); if (!bdev->bd_openers) { bdev->bd_disk = disk; - bdev->bd_part = part; bdev->bd_contains = bdev; if (!partno) { struct backing_dev_info *bdi; + + ret = -ENXIO; + bdev->bd_part = disk_get_part(disk, partno); + if (!bdev->bd_part) + goto out_clear; + if (disk->fops->open) { ret = disk->fops->open(bdev, mode); if (ret) @@ -1049,18 +1049,17 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) bdev->bd_contains = whole; bdev->bd_inode->i_data.backing_dev_info = whole->bd_inode->i_data.backing_dev_info; + bdev->bd_part = disk_get_part(disk, partno); if (!(disk->flags & GENHD_FL_UP) || - !part || !part->nr_sects) { + !bdev->bd_part || !bdev->bd_part->nr_sects) { ret = -ENXIO; goto out_clear; } - bd_set_size(bdev, (loff_t)part->nr_sects << 9); + bd_set_size(bdev, (loff_t)bdev->bd_part->nr_sects << 9); } } else { - disk_put_part(part); put_disk(disk); module_put(disk->fops->owner); - part = NULL; disk = NULL; if (bdev->bd_contains == bdev) { if (bdev->bd_disk->fops->open) { @@ -1080,6 +1079,7 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) return 0; out_clear: + disk_put_part(bdev->bd_part); bdev->bd_disk = NULL; bdev->bd_part = NULL; bdev->bd_inode->i_data.backing_dev_info = &default_backing_dev_info; @@ -1091,7 +1091,6 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part) out_unlock_kernel: unlock_kernel(); - disk_put_part(part); if (disk) module_put(disk->fops->owner); put_disk(disk); @@ -1136,12 +1135,15 @@ static int blkdev_open(struct inode * inode, struct file * filp) if (res) return res; - if (!(filp->f_mode & FMODE_EXCL)) - return 0; + if (filp->f_mode & FMODE_EXCL) { + res = bd_claim(bdev, filp); + if (res) + goto out_blkdev_put; + } - if (!(res = bd_claim(bdev, filp))) - return 0; + return 0; + out_blkdev_put: blkdev_put(bdev, filp->f_mode); return res; } @@ -1204,8 +1206,16 @@ static long block_ioctl(struct file *file, unsigned cmd, unsigned long arg) { struct block_device *bdev = I_BDEV(file->f_mapping->host); fmode_t mode = file->f_mode; + + /* + * O_NDELAY can be altered using fcntl(.., F_SETFL, ..), so we have + * to updated it before every ioctl. + */ if (file->f_flags & O_NDELAY) - mode |= FMODE_NDELAY_NOW; + mode |= FMODE_NDELAY; + else + mode &= ~FMODE_NDELAY; + return blkdev_ioctl(bdev, mode, cmd, arg); } diff --git a/fs/buffer.c b/fs/buffer.c index 6569fda5cfed..10179cfa1152 100644 --- a/fs/buffer.c +++ b/fs/buffer.c @@ -878,6 +878,7 @@ void invalidate_inode_buffers(struct inode *inode) spin_unlock(&buffer_mapping->private_lock); } } +EXPORT_SYMBOL(invalidate_inode_buffers); /* * Remove any clean buffers from the inode's buffer list. This is called diff --git a/fs/cifs/CHANGES b/fs/cifs/CHANGES index 8f528ea24c48..e078b7aea143 100644 --- a/fs/cifs/CHANGES +++ b/fs/cifs/CHANGES @@ -4,7 +4,15 @@ Various fixes to make delete of open files behavior more predictable (when delete of an open file fails we mark the file as "delete-on-close" in a way that more servers accept, but only if we can first rename the file to a temporary name). Add experimental support for more safely -handling fcntl(F_SETLEASE). +handling fcntl(F_SETLEASE). Convert cifs to using blocking tcp +sends, and also let tcp autotune the socket send and receive buffers. +This reduces the number of EAGAIN errors returned by TCP/IP in +high stress workloads (and the number of retries on socket writes +when sending large SMBWriteX requests). Fix case in which a portion of +data can in some cases not get written to the file on the server before the +file is closed. Fix DFS parsing to properly handle path consumed field, +and to handle certain codepage conversions better. Fix mount and +umount race that can cause oops in mount or umount or reconnect. Version 1.54 ------------ diff --git a/fs/cifs/cifs_debug.c b/fs/cifs/cifs_debug.c index 69a12aae91d3..490e34bbf27a 100644 --- a/fs/cifs/cifs_debug.c +++ b/fs/cifs/cifs_debug.c @@ -107,12 +107,13 @@ void cifs_dump_mids(struct TCP_Server_Info *server) #ifdef CONFIG_PROC_FS static int cifs_debug_data_proc_show(struct seq_file *m, void *v) { - struct list_head *tmp; - struct list_head *tmp1; + struct list_head *tmp1, *tmp2, *tmp3; struct mid_q_entry *mid_entry; + struct TCP_Server_Info *server; struct cifsSesInfo *ses; struct cifsTconInfo *tcon; - int i; + int i, j; + __u32 dev_type; seq_puts(m, "Display Internal CIFS Data Structures for Debugging\n" @@ -122,46 +123,78 @@ static int cifs_debug_data_proc_show(struct seq_file *m, void *v) seq_printf(m, "Servers:"); i = 0; - read_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalSMBSessionList) { + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp1, &cifs_tcp_ses_list) { + server = list_entry(tmp1, struct TCP_Server_Info, + tcp_ses_list); i++; - ses = list_entry(tmp, struct cifsSesInfo, cifsSessionList); - if ((ses->serverDomain == NULL) || (ses->serverOS == NULL) || - (ses->serverNOS == NULL)) { - seq_printf(m, "\nentry for %s not fully " - "displayed\n\t", ses->serverName); - } else { - seq_printf(m, - "\n%d) Name: %s Domain: %s Mounts: %d OS:" - " %s \n\tNOS: %s\tCapability: 0x%x\n\tSMB" + list_for_each(tmp2, &server->smb_ses_list) { + ses = list_entry(tmp2, struct cifsSesInfo, + smb_ses_list); + if ((ses->serverDomain == NULL) || + (ses->serverOS == NULL) || + (ses->serverNOS == NULL)) { + seq_printf(m, "\n%d) entry for %s not fully " + "displayed\n\t", i, ses->serverName); + } else { + seq_printf(m, + "\n%d) Name: %s Domain: %s Uses: %d OS:" + " %s\n\tNOS: %s\tCapability: 0x%x\n\tSMB" " session status: %d\t", i, ses->serverName, ses->serverDomain, - atomic_read(&ses->inUse), - ses->serverOS, ses->serverNOS, + ses->ses_count, ses->serverOS, ses->serverNOS, ses->capabilities, ses->status); - } - if (ses->server) { + } seq_printf(m, "TCP status: %d\n\tLocal Users To " - "Server: %d SecMode: 0x%x Req On Wire: %d", - ses->server->tcpStatus, - atomic_read(&ses->server->socketUseCount), - ses->server->secMode, - atomic_read(&ses->server->inFlight)); + "Server: %d SecMode: 0x%x Req On Wire: %d", + server->tcpStatus, server->srv_count, + server->secMode, + atomic_read(&server->inFlight)); #ifdef CONFIG_CIFS_STATS2 seq_printf(m, " In Send: %d In MaxReq Wait: %d", - atomic_read(&ses->server->inSend), - atomic_read(&ses->server->num_waiters)); + atomic_read(&server->inSend), + atomic_read(&server->num_waiters)); #endif - seq_puts(m, "\nMIDs:\n"); + seq_puts(m, "\n\tShares:"); + j = 0; + list_for_each(tmp3, &ses->tcon_list) { + tcon = list_entry(tmp3, struct cifsTconInfo, + tcon_list); + ++j; + dev_type = le32_to_cpu(tcon->fsDevInfo.DeviceType); + seq_printf(m, "\n\t%d) %s Mounts: %d ", j, + tcon->treeName, tcon->tc_count); + if (tcon->nativeFileSystem) { + seq_printf(m, "Type: %s ", + tcon->nativeFileSystem); + } + seq_printf(m, "DevInfo: 0x%x Attributes: 0x%x" + "\nPathComponentMax: %d Status: 0x%d", + le32_to_cpu(tcon->fsDevInfo.DeviceCharacteristics), + le32_to_cpu(tcon->fsAttrInfo.Attributes), + le32_to_cpu(tcon->fsAttrInfo.MaxPathNameComponentLength), + tcon->tidStatus); + if (dev_type == FILE_DEVICE_DISK) + seq_puts(m, " type: DISK "); + else if (dev_type == FILE_DEVICE_CD_ROM) + seq_puts(m, " type: CDROM "); + else + seq_printf(m, " type: %d ", dev_type); + + if (tcon->need_reconnect) + seq_puts(m, "\tDISCONNECTED "); + seq_putc(m, '\n'); + } + + seq_puts(m, "\n\tMIDs:\n"); spin_lock(&GlobalMid_Lock); - list_for_each(tmp1, &ses->server->pending_mid_q) { - mid_entry = list_entry(tmp1, struct - mid_q_entry, + list_for_each(tmp3, &server->pending_mid_q) { + mid_entry = list_entry(tmp3, struct mid_q_entry, qhead); - seq_printf(m, "State: %d com: %d pid:" + seq_printf(m, "\tState: %d com: %d pid:" " %d tsk: %p mid %d\n", mid_entry->midState, (int)mid_entry->command, @@ -171,44 +204,8 @@ static int cifs_debug_data_proc_show(struct seq_file *m, void *v) } spin_unlock(&GlobalMid_Lock); } - - } - read_unlock(&GlobalSMBSeslock); - seq_putc(m, '\n'); - - seq_puts(m, "Shares:"); - - i = 0; - read_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalTreeConnectionList) { - __u32 dev_type; - i++; - tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); - dev_type = le32_to_cpu(tcon->fsDevInfo.DeviceType); - seq_printf(m, "\n%d) %s Uses: %d ", i, - tcon->treeName, atomic_read(&tcon->useCount)); - if (tcon->nativeFileSystem) { - seq_printf(m, "Type: %s ", - tcon->nativeFileSystem); - } - seq_printf(m, "DevInfo: 0x%x Attributes: 0x%x" - "\nPathComponentMax: %d Status: %d", - le32_to_cpu(tcon->fsDevInfo.DeviceCharacteristics), - le32_to_cpu(tcon->fsAttrInfo.Attributes), - le32_to_cpu(tcon->fsAttrInfo.MaxPathNameComponentLength), - tcon->tidStatus); - if (dev_type == FILE_DEVICE_DISK) - seq_puts(m, " type: DISK "); - else if (dev_type == FILE_DEVICE_CD_ROM) - seq_puts(m, " type: CDROM "); - else - seq_printf(m, " type: %d ", dev_type); - - if (tcon->tidStatus == CifsNeedReconnect) - seq_puts(m, "\tDISCONNECTED "); } - read_unlock(&GlobalSMBSeslock); - + read_unlock(&cifs_tcp_ses_lock); seq_putc(m, '\n'); /* BB add code to dump additional info such as TCP session info now */ @@ -234,7 +231,9 @@ static ssize_t cifs_stats_proc_write(struct file *file, { char c; int rc; - struct list_head *tmp; + struct list_head *tmp1, *tmp2, *tmp3; + struct TCP_Server_Info *server; + struct cifsSesInfo *ses; struct cifsTconInfo *tcon; rc = get_user(c, buffer); @@ -242,33 +241,42 @@ static ssize_t cifs_stats_proc_write(struct file *file, return rc; if (c == '1' || c == 'y' || c == 'Y' || c == '0') { - read_lock(&GlobalSMBSeslock); #ifdef CONFIG_CIFS_STATS2 atomic_set(&totBufAllocCount, 0); atomic_set(&totSmBufAllocCount, 0); #endif /* CONFIG_CIFS_STATS2 */ - list_for_each(tmp, &GlobalTreeConnectionList) { - tcon = list_entry(tmp, struct cifsTconInfo, - cifsConnectionList); - atomic_set(&tcon->num_smbs_sent, 0); - atomic_set(&tcon->num_writes, 0); - atomic_set(&tcon->num_reads, 0); - atomic_set(&tcon->num_oplock_brks, 0); - atomic_set(&tcon->num_opens, 0); - atomic_set(&tcon->num_closes, 0); - atomic_set(&tcon->num_deletes, 0); - atomic_set(&tcon->num_mkdirs, 0); - atomic_set(&tcon->num_rmdirs, 0); - atomic_set(&tcon->num_renames, 0); - atomic_set(&tcon->num_t2renames, 0); - atomic_set(&tcon->num_ffirst, 0); - atomic_set(&tcon->num_fnext, 0); - atomic_set(&tcon->num_fclose, 0); - atomic_set(&tcon->num_hardlinks, 0); - atomic_set(&tcon->num_symlinks, 0); - atomic_set(&tcon->num_locks, 0); + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp1, &cifs_tcp_ses_list) { + server = list_entry(tmp1, struct TCP_Server_Info, + tcp_ses_list); + list_for_each(tmp2, &server->smb_ses_list) { + ses = list_entry(tmp2, struct cifsSesInfo, + smb_ses_list); + list_for_each(tmp3, &ses->tcon_list) { + tcon = list_entry(tmp3, + struct cifsTconInfo, + tcon_list); + atomic_set(&tcon->num_smbs_sent, 0); + atomic_set(&tcon->num_writes, 0); + atomic_set(&tcon->num_reads, 0); + atomic_set(&tcon->num_oplock_brks, 0); + atomic_set(&tcon->num_opens, 0); + atomic_set(&tcon->num_closes, 0); + atomic_set(&tcon->num_deletes, 0); + atomic_set(&tcon->num_mkdirs, 0); + atomic_set(&tcon->num_rmdirs, 0); + atomic_set(&tcon->num_renames, 0); + atomic_set(&tcon->num_t2renames, 0); + atomic_set(&tcon->num_ffirst, 0); + atomic_set(&tcon->num_fnext, 0); + atomic_set(&tcon->num_fclose, 0); + atomic_set(&tcon->num_hardlinks, 0); + atomic_set(&tcon->num_symlinks, 0); + atomic_set(&tcon->num_locks, 0); + } + } } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); } return count; @@ -277,7 +285,9 @@ static ssize_t cifs_stats_proc_write(struct file *file, static int cifs_stats_proc_show(struct seq_file *m, void *v) { int i; - struct list_head *tmp; + struct list_head *tmp1, *tmp2, *tmp3; + struct TCP_Server_Info *server; + struct cifsSesInfo *ses; struct cifsTconInfo *tcon; seq_printf(m, @@ -306,44 +316,55 @@ static int cifs_stats_proc_show(struct seq_file *m, void *v) GlobalCurrentXid, GlobalMaxActiveXid); i = 0; - read_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalTreeConnectionList) { - i++; - tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); - seq_printf(m, "\n%d) %s", i, tcon->treeName); - if (tcon->tidStatus == CifsNeedReconnect) - seq_puts(m, "\tDISCONNECTED "); - seq_printf(m, "\nSMBs: %d Oplock Breaks: %d", - atomic_read(&tcon->num_smbs_sent), - atomic_read(&tcon->num_oplock_brks)); - seq_printf(m, "\nReads: %d Bytes: %lld", - atomic_read(&tcon->num_reads), - (long long)(tcon->bytes_read)); - seq_printf(m, "\nWrites: %d Bytes: %lld", - atomic_read(&tcon->num_writes), - (long long)(tcon->bytes_written)); - seq_printf(m, - "\nLocks: %d HardLinks: %d Symlinks: %d", - atomic_read(&tcon->num_locks), - atomic_read(&tcon->num_hardlinks), - atomic_read(&tcon->num_symlinks)); - - seq_printf(m, "\nOpens: %d Closes: %d Deletes: %d", - atomic_read(&tcon->num_opens), - atomic_read(&tcon->num_closes), - atomic_read(&tcon->num_deletes)); - seq_printf(m, "\nMkdirs: %d Rmdirs: %d", - atomic_read(&tcon->num_mkdirs), - atomic_read(&tcon->num_rmdirs)); - seq_printf(m, "\nRenames: %d T2 Renames %d", - atomic_read(&tcon->num_renames), - atomic_read(&tcon->num_t2renames)); - seq_printf(m, "\nFindFirst: %d FNext %d FClose %d", - atomic_read(&tcon->num_ffirst), - atomic_read(&tcon->num_fnext), - atomic_read(&tcon->num_fclose)); + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp1, &cifs_tcp_ses_list) { + server = list_entry(tmp1, struct TCP_Server_Info, + tcp_ses_list); + list_for_each(tmp2, &server->smb_ses_list) { + ses = list_entry(tmp2, struct cifsSesInfo, + smb_ses_list); + list_for_each(tmp3, &ses->tcon_list) { + tcon = list_entry(tmp3, + struct cifsTconInfo, + tcon_list); + i++; + seq_printf(m, "\n%d) %s", i, tcon->treeName); + if (tcon->need_reconnect) + seq_puts(m, "\tDISCONNECTED "); + seq_printf(m, "\nSMBs: %d Oplock Breaks: %d", + atomic_read(&tcon->num_smbs_sent), + atomic_read(&tcon->num_oplock_brks)); + seq_printf(m, "\nReads: %d Bytes: %lld", + atomic_read(&tcon->num_reads), + (long long)(tcon->bytes_read)); + seq_printf(m, "\nWrites: %d Bytes: %lld", + atomic_read(&tcon->num_writes), + (long long)(tcon->bytes_written)); + seq_printf(m, "\nLocks: %d HardLinks: %d " + "Symlinks: %d", + atomic_read(&tcon->num_locks), + atomic_read(&tcon->num_hardlinks), + atomic_read(&tcon->num_symlinks)); + seq_printf(m, "\nOpens: %d Closes: %d" + "Deletes: %d", + atomic_read(&tcon->num_opens), + atomic_read(&tcon->num_closes), + atomic_read(&tcon->num_deletes)); + seq_printf(m, "\nMkdirs: %d Rmdirs: %d", + atomic_read(&tcon->num_mkdirs), + atomic_read(&tcon->num_rmdirs)); + seq_printf(m, "\nRenames: %d T2 Renames %d", + atomic_read(&tcon->num_renames), + atomic_read(&tcon->num_t2renames)); + seq_printf(m, "\nFindFirst: %d FNext %d " + "FClose %d", + atomic_read(&tcon->num_ffirst), + atomic_read(&tcon->num_fnext), + atomic_read(&tcon->num_fclose)); + } + } } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); seq_putc(m, '\n'); return 0; diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c index d2c8eef84f3c..e1c18362ba46 100644 --- a/fs/cifs/cifs_dfs_ref.c +++ b/fs/cifs/cifs_dfs_ref.c @@ -106,7 +106,8 @@ static char *cifs_get_share_name(const char *node_name) /** * compose_mount_options - creates mount options for refferral * @sb_mountdata: parent/root DFS mount options (template) - * @ref_unc: refferral server UNC + * @dentry: point where we are going to mount + * @ref: server's referral * @devname: pointer for saving device name * * creates mount options for submount based on template options sb_mountdata @@ -116,7 +117,8 @@ static char *cifs_get_share_name(const char *node_name) * Caller is responcible for freeing retunrned value if it is not error. */ static char *compose_mount_options(const char *sb_mountdata, - const char *ref_unc, + struct dentry *dentry, + const struct dfs_info3_param *ref, char **devname) { int rc; @@ -126,11 +128,12 @@ static char *compose_mount_options(const char *sb_mountdata, char *srvIP = NULL; char sep = ','; int off, noff; + char *fullpath; if (sb_mountdata == NULL) return ERR_PTR(-EINVAL); - *devname = cifs_get_share_name(ref_unc); + *devname = cifs_get_share_name(ref->node_name); rc = dns_resolve_server_name_to_ip(*devname, &srvIP); if (rc != 0) { cERROR(1, ("%s: Failed to resolve server part of %s to IP", @@ -138,7 +141,12 @@ static char *compose_mount_options(const char *sb_mountdata, mountdata = ERR_PTR(rc); goto compose_mount_options_out; } - md_len = strlen(sb_mountdata) + strlen(srvIP) + strlen(ref_unc) + 3; + /* md_len = strlen(...) + 12 for 'sep+prefixpath=' + * assuming that we have 'unc=' and 'ip=' in + * the original sb_mountdata + */ + md_len = strlen(sb_mountdata) + strlen(srvIP) + + strlen(ref->node_name) + 12; mountdata = kzalloc(md_len+1, GFP_KERNEL); if (mountdata == NULL) { mountdata = ERR_PTR(-ENOMEM); @@ -152,41 +160,56 @@ static char *compose_mount_options(const char *sb_mountdata, strncpy(mountdata, sb_mountdata, 5); off += 5; } - while ((tkn_e = strchr(sb_mountdata+off, sep))) { - noff = (tkn_e - (sb_mountdata+off)) + 1; - if (strnicmp(sb_mountdata+off, "unc=", 4) == 0) { + + do { + tkn_e = strchr(sb_mountdata + off, sep); + if (tkn_e == NULL) + noff = strlen(sb_mountdata + off); + else + noff = tkn_e - (sb_mountdata + off) + 1; + + if (strnicmp(sb_mountdata + off, "unc=", 4) == 0) { off += noff; continue; } - if (strnicmp(sb_mountdata+off, "ip=", 3) == 0) { + if (strnicmp(sb_mountdata + off, "ip=", 3) == 0) { off += noff; continue; } - if (strnicmp(sb_mountdata+off, "prefixpath=", 3) == 0) { + if (strnicmp(sb_mountdata + off, "prefixpath=", 11) == 0) { off += noff; continue; } - strncat(mountdata, sb_mountdata+off, noff); + strncat(mountdata, sb_mountdata + off, noff); off += noff; - } - strcat(mountdata, sb_mountdata+off); + } while (tkn_e); + strcat(mountdata, sb_mountdata + off); mountdata[md_len] = '\0'; /* copy new IP and ref share name */ - strcat(mountdata, ",ip="); + if (mountdata[strlen(mountdata) - 1] != sep) + strncat(mountdata, &sep, 1); + strcat(mountdata, "ip="); strcat(mountdata, srvIP); - strcat(mountdata, ",unc="); + strncat(mountdata, &sep, 1); + strcat(mountdata, "unc="); strcat(mountdata, *devname); /* find & copy prefixpath */ - tkn_e = strchr(ref_unc+2, '\\'); - if (tkn_e) { - tkn_e = strchr(tkn_e+1, '\\'); - if (tkn_e) { - strcat(mountdata, ",prefixpath="); - strcat(mountdata, tkn_e+1); - } + tkn_e = strchr(ref->node_name + 2, '\\'); + if (tkn_e == NULL) /* invalid unc, missing share name*/ + goto compose_mount_options_out; + + fullpath = build_path_from_dentry(dentry); + tkn_e = strchr(tkn_e + 1, '\\'); + if (tkn_e || strlen(fullpath) - (ref->path_consumed)) { + strncat(mountdata, &sep, 1); + strcat(mountdata, "prefixpath="); + if (tkn_e) + strcat(mountdata, tkn_e + 1); + strcat(mountdata, fullpath + (ref->path_consumed)); } + kfree(fullpath); /*cFYI(1,("%s: parent mountdata: %s", __func__,sb_mountdata));*/ /*cFYI(1, ("%s: submount mountdata: %s", __func__, mountdata ));*/ @@ -198,7 +221,7 @@ compose_mount_options_out: static struct vfsmount *cifs_dfs_do_refmount(const struct vfsmount *mnt_parent, - struct dentry *dentry, char *ref_unc) + struct dentry *dentry, const struct dfs_info3_param *ref) { struct cifs_sb_info *cifs_sb; struct vfsmount *mnt; @@ -207,7 +230,7 @@ static struct vfsmount *cifs_dfs_do_refmount(const struct vfsmount *mnt_parent, cifs_sb = CIFS_SB(dentry->d_inode->i_sb); mountdata = compose_mount_options(cifs_sb->mountdata, - ref_unc, &devname); + dentry, ref, &devname); if (IS_ERR(mountdata)) return (struct vfsmount *)mountdata; @@ -310,7 +333,7 @@ cifs_dfs_follow_mountpoint(struct dentry *dentry, struct nameidata *nd) } mnt = cifs_dfs_do_refmount(nd->path.mnt, nd->path.dentry, - referrals[i].node_name); + referrals + i); cFYI(1, ("%s: cifs_dfs_do_refmount:%s , mnt:%p", __func__, referrals[i].node_name, mnt)); diff --git a/fs/cifs/cifs_spnego.c b/fs/cifs/cifs_spnego.c index fcee9298b620..0ab2fb5afef1 100644 --- a/fs/cifs/cifs_spnego.c +++ b/fs/cifs/cifs_spnego.c @@ -73,8 +73,8 @@ struct key_type cifs_spnego_key_type = { * strlen(";sec=ntlmsspi") */ #define MAX_MECH_STR_LEN 13 -/* max possible addr len eg FEDC:BA98:7654:3210:FEDC:BA98:7654:3210/60 */ -#define MAX_IPV6_ADDR_LEN 42 +/* max possible addr len eg FEDC:BA98:7654:3210:FEDC:BA98:7654:3210/128 */ +#define MAX_IPV6_ADDR_LEN 43 /* strlen of "host=" */ #define HOST_KEY_LEN 5 diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index ac5915d61dca..d9cf467309e8 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -514,10 +514,11 @@ static void cifs_umount_begin(struct super_block *sb) tcon = cifs_sb->tcon; if (tcon == NULL) return; - down(&tcon->tconSem); - if (atomic_read(&tcon->useCount) == 1) + + read_lock(&cifs_tcp_ses_lock); + if (tcon->tc_count == 1) tcon->tidStatus = CifsExiting; - up(&tcon->tconSem); + read_unlock(&cifs_tcp_ses_lock); /* cancel_brl_requests(tcon); */ /* BB mark all brl mids as exiting */ /* cancel_notify_requests(tcon); */ @@ -1013,7 +1014,7 @@ static int cifs_oplock_thread(void *dummyarg) not bother sending an oplock release if session to server still is disconnected since oplock already released by the server in that case */ - if (pTcon->tidStatus != CifsNeedReconnect) { + if (!pTcon->need_reconnect) { rc = CIFSSMBLock(0, pTcon, netfid, 0 /* len */ , 0 /* offset */, 0, 0, LOCKING_ANDX_OPLOCK_RELEASE, @@ -1031,24 +1032,24 @@ static int cifs_oplock_thread(void *dummyarg) static int cifs_dnotify_thread(void *dummyarg) { struct list_head *tmp; - struct cifsSesInfo *ses; + struct TCP_Server_Info *server; do { if (try_to_freeze()) continue; set_current_state(TASK_INTERRUPTIBLE); schedule_timeout(15*HZ); - read_lock(&GlobalSMBSeslock); /* check if any stuck requests that need to be woken up and wakeq so the thread can wake up and error out */ - list_for_each(tmp, &GlobalSMBSessionList) { - ses = list_entry(tmp, struct cifsSesInfo, - cifsSessionList); - if (ses->server && atomic_read(&ses->server->inFlight)) - wake_up_all(&ses->server->response_q); + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &cifs_tcp_ses_list) { + server = list_entry(tmp, struct TCP_Server_Info, + tcp_ses_list); + if (atomic_read(&server->inFlight)) + wake_up_all(&server->response_q); } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); } while (!kthread_should_stop()); return 0; @@ -1059,9 +1060,7 @@ init_cifs(void) { int rc = 0; cifs_proc_init(); -/* INIT_LIST_HEAD(&GlobalServerList);*/ /* BB not implemented yet */ - INIT_LIST_HEAD(&GlobalSMBSessionList); - INIT_LIST_HEAD(&GlobalTreeConnectionList); + INIT_LIST_HEAD(&cifs_tcp_ses_list); INIT_LIST_HEAD(&GlobalOplock_Q); #ifdef CONFIG_CIFS_EXPERIMENTAL INIT_LIST_HEAD(&GlobalDnotifyReqList); @@ -1089,6 +1088,7 @@ init_cifs(void) GlobalMaxActiveXid = 0; memset(Local_System_Name, 0, 15); rwlock_init(&GlobalSMBSeslock); + rwlock_init(&cifs_tcp_ses_lock); spin_lock_init(&GlobalMid_Lock); if (cifs_max_pending < 2) { diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h index c791e5b5a914..c57c0565547f 100644 --- a/fs/cifs/cifsglob.h +++ b/fs/cifs/cifsglob.h @@ -85,8 +85,7 @@ enum securityEnum { }; enum protocolEnum { - IPV4 = 0, - IPV6, + TCP = 0, SCTP /* Netbios frames protocol not supported at this time */ }; @@ -122,6 +121,9 @@ struct cifs_cred { */ struct TCP_Server_Info { + struct list_head tcp_ses_list; + struct list_head smb_ses_list; + int srv_count; /* reference counter */ /* 15 character server name + 0x20 16th byte indicating type = srv */ char server_RFC1001_name[SERVER_NAME_LEN_WITH_NULL]; char unicode_server_Name[SERVER_NAME_LEN_WITH_NULL * 2]; @@ -141,7 +143,8 @@ struct TCP_Server_Info { char versionMajor; char versionMinor; bool svlocal:1; /* local server or remote */ - atomic_t socketUseCount; /* number of open cifs sessions on socket */ + bool noblocksnd; /* use blocking sendmsg */ + bool noautotune; /* do not autotune send buf sizes */ atomic_t inFlight; /* number of requests on the wire to server */ #ifdef CONFIG_CIFS_STATS2 atomic_t inSend; /* requests trying to send */ @@ -192,13 +195,14 @@ struct cifsUidInfo { * Session structure. One of these for each uid session with a particular host */ struct cifsSesInfo { - struct list_head cifsSessionList; + struct list_head smb_ses_list; + struct list_head tcon_list; struct semaphore sesSem; #if 0 struct cifsUidInfo *uidInfo; /* pointer to user info */ #endif struct TCP_Server_Info *server; /* pointer to server info */ - atomic_t inUse; /* # of mounts (tree connections) on this ses */ + int ses_count; /* reference counter */ enum statusEnum status; unsigned overrideSecFlg; /* if non-zero override global sec flags */ __u16 ipc_tid; /* special tid for connection to IPC share */ @@ -214,6 +218,7 @@ struct cifsSesInfo { char userName[MAX_USERNAME_SIZE + 1]; char *domainName; char *password; + bool need_reconnect:1; /* connection reset, uid now invalid */ }; /* no more than one of the following three session flags may be set */ #define CIFS_SES_NT4 1 @@ -228,16 +233,15 @@ struct cifsSesInfo { * session */ struct cifsTconInfo { - struct list_head cifsConnectionList; + struct list_head tcon_list; + int tc_count; struct list_head openFileList; - struct semaphore tconSem; struct cifsSesInfo *ses; /* pointer to session associated with */ char treeName[MAX_TREE_SIZE + 1]; /* UNC name of resource in ASCII */ char *nativeFileSystem; __u16 tid; /* The 2 byte tree id */ __u16 Flags; /* optional support bits */ enum statusEnum tidStatus; - atomic_t useCount; /* how many explicit/implicit mounts to share */ #ifdef CONFIG_CIFS_STATS atomic_t num_smbs_sent; atomic_t num_writes; @@ -286,6 +290,7 @@ struct cifsTconInfo { bool unix_ext:1; /* if false disable Linux extensions to CIFS protocol for this mount even if server would support */ bool local_lease:1; /* check leases (only) on local system not remote */ + bool need_reconnect:1; /* connection reset, tid now invalid */ /* BB add field for back pointer to sb struct(s)? */ }; @@ -586,22 +591,30 @@ require use of the stronger protocol */ #endif /* - * The list of servers that did not respond with NT LM 0.12. - * This list helps improve performance and eliminate the messages indicating - * that we had a communications error talking to the server in this list. + * the list of TCP_Server_Info structures, ie each of the sockets + * connecting our client to a distinct server (ip address), is + * chained together by cifs_tcp_ses_list. The list of all our SMB + * sessions (and from that the tree connections) can be found + * by iterating over cifs_tcp_ses_list */ -/* Feature not supported */ -/* GLOBAL_EXTERN struct servers_not_supported *NotSuppList; */ +GLOBAL_EXTERN struct list_head cifs_tcp_ses_list; /* - * The following is a hash table of all the users we know about. + * This lock protects the cifs_tcp_ses_list, the list of smb sessions per + * tcp session, and the list of tcon's per smb session. It also protects + * the reference counters for the server, smb session, and tcon. Finally, + * changes to the tcon->tidStatus should be done while holding this lock. */ -GLOBAL_EXTERN struct smbUidInfo *GlobalUidList[UID_HASH]; +GLOBAL_EXTERN rwlock_t cifs_tcp_ses_lock; -/* GLOBAL_EXTERN struct list_head GlobalServerList; BB not implemented yet */ -GLOBAL_EXTERN struct list_head GlobalSMBSessionList; -GLOBAL_EXTERN struct list_head GlobalTreeConnectionList; -GLOBAL_EXTERN rwlock_t GlobalSMBSeslock; /* protects list inserts on 3 above */ +/* + * This lock protects the cifs_file->llist and cifs_file->flist + * list operations, and updates to some flags (cifs_file->invalidHandle) + * It will be moved to either use the tcon->stat_lock or equivalent later. + * If cifs_tcp_ses_lock and the lock below are both needed to be held, then + * the cifs_tcp_ses_lock must be grabbed first and released last. + */ +GLOBAL_EXTERN rwlock_t GlobalSMBSeslock; GLOBAL_EXTERN struct list_head GlobalOplock_Q; diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h index 0cff7fe986e8..6f21ecb85ce5 100644 --- a/fs/cifs/cifsproto.h +++ b/fs/cifs/cifsproto.h @@ -36,7 +36,7 @@ extern void cifs_buf_release(void *); extern struct smb_hdr *cifs_small_buf_get(void); extern void cifs_small_buf_release(void *); extern int smb_send(struct socket *, struct smb_hdr *, - unsigned int /* length */ , struct sockaddr *); + unsigned int /* length */ , struct sockaddr *, bool); extern unsigned int _GetXid(void); extern void _FreeXid(unsigned int); #define GetXid() (int)_GetXid(); cFYI(1,("CIFS VFS: in %s as Xid: %d with uid: %d",__func__, xid,current->fsuid)); diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c index 843a85fb8b9a..6d51696dc762 100644 --- a/fs/cifs/cifssmb.c +++ b/fs/cifs/cifssmb.c @@ -190,10 +190,10 @@ small_smb_init(int smb_command, int wct, struct cifsTconInfo *tcon, /* need to prevent multiple threads trying to simultaneously reconnect the same SMB session */ down(&tcon->ses->sesSem); - if (tcon->ses->status == CifsNeedReconnect) + if (tcon->ses->need_reconnect) rc = cifs_setup_session(0, tcon->ses, nls_codepage); - if (!rc && (tcon->tidStatus == CifsNeedReconnect)) { + if (!rc && (tcon->need_reconnect)) { mark_open_files_invalid(tcon); rc = CIFSTCon(0, tcon->ses, tcon->treeName, tcon, nls_codepage); @@ -337,10 +337,10 @@ smb_init(int smb_command, int wct, struct cifsTconInfo *tcon, /* need to prevent multiple threads trying to simultaneously reconnect the same SMB session */ down(&tcon->ses->sesSem); - if (tcon->ses->status == CifsNeedReconnect) + if (tcon->ses->need_reconnect) rc = cifs_setup_session(0, tcon->ses, nls_codepage); - if (!rc && (tcon->tidStatus == CifsNeedReconnect)) { + if (!rc && (tcon->need_reconnect)) { mark_open_files_invalid(tcon); rc = CIFSTCon(0, tcon->ses, tcon->treeName, tcon, nls_codepage); @@ -664,8 +664,9 @@ CIFSSMBNegotiate(unsigned int xid, struct cifsSesInfo *ses) rc = -EIO; goto neg_err_exit; } - - if (server->socketUseCount.counter > 1) { + read_lock(&cifs_tcp_ses_lock); + if (server->srv_count > 1) { + read_unlock(&cifs_tcp_ses_lock); if (memcmp(server->server_GUID, pSMBr->u.extended_response. GUID, 16) != 0) { @@ -674,9 +675,11 @@ CIFSSMBNegotiate(unsigned int xid, struct cifsSesInfo *ses) pSMBr->u.extended_response.GUID, 16); } - } else + } else { + read_unlock(&cifs_tcp_ses_lock); memcpy(server->server_GUID, pSMBr->u.extended_response.GUID, 16); + } if (count == 16) { server->secType = RawNTLMSSP; @@ -739,50 +742,31 @@ CIFSSMBTDis(const int xid, struct cifsTconInfo *tcon) int rc = 0; cFYI(1, ("In tree disconnect")); - /* - * If last user of the connection and - * connection alive - disconnect it - * If this is the last connection on the server session disconnect it - * (and inside session disconnect we should check if tcp socket needs - * to be freed and kernel thread woken up). - */ - if (tcon) - down(&tcon->tconSem); - else - return -EIO; - atomic_dec(&tcon->useCount); - if (atomic_read(&tcon->useCount) > 0) { - up(&tcon->tconSem); - return -EBUSY; - } + /* BB: do we need to check this? These should never be NULL. */ + if ((tcon->ses == NULL) || (tcon->ses->server == NULL)) + return -EIO; - /* No need to return error on this operation if tid invalidated and - closed on server already e.g. due to tcp session crashing */ - if (tcon->tidStatus == CifsNeedReconnect) { - up(&tcon->tconSem); + /* + * No need to return error on this operation if tid invalidated and + * closed on server already e.g. due to tcp session crashing. Also, + * the tcon is no longer on the list, so no need to take lock before + * checking this. + */ + if (tcon->need_reconnect) return 0; - } - if ((tcon->ses == NULL) || (tcon->ses->server == NULL)) { - up(&tcon->tconSem); - return -EIO; - } rc = small_smb_init(SMB_COM_TREE_DISCONNECT, 0, tcon, (void **)&smb_buffer); - if (rc) { - up(&tcon->tconSem); + if (rc) return rc; - } rc = SendReceiveNoRsp(xid, tcon->ses, smb_buffer, 0); if (rc) cFYI(1, ("Tree disconnect failed %d", rc)); - up(&tcon->tconSem); - /* No need to return error on this operation if tid invalidated and - closed on server already e.g. due to tcp session crashing */ + closed on server already e.g. due to tcp session crashing */ if (rc == -EAGAIN) rc = 0; @@ -796,43 +780,36 @@ CIFSSMBLogoff(const int xid, struct cifsSesInfo *ses) int rc = 0; cFYI(1, ("In SMBLogoff for session disconnect")); - if (ses) - down(&ses->sesSem); - else + + /* + * BB: do we need to check validity of ses and server? They should + * always be valid since we have an active reference. If not, that + * should probably be a BUG() + */ + if (!ses || !ses->server) return -EIO; - atomic_dec(&ses->inUse); - if (atomic_read(&ses->inUse) > 0) { - up(&ses->sesSem); - return -EBUSY; - } + down(&ses->sesSem); + if (ses->need_reconnect) + goto session_already_dead; /* no need to send SMBlogoff if uid + already closed due to reconnect */ rc = small_smb_init(SMB_COM_LOGOFF_ANDX, 2, NULL, (void **)&pSMB); if (rc) { up(&ses->sesSem); return rc; } - if (ses->server) { - pSMB->hdr.Mid = GetNextMid(ses->server); + pSMB->hdr.Mid = GetNextMid(ses->server); - if (ses->server->secMode & + if (ses->server->secMode & (SECMODE_SIGN_REQUIRED | SECMODE_SIGN_ENABLED)) pSMB->hdr.Flags2 |= SMBFLG2_SECURITY_SIGNATURE; - } pSMB->hdr.Uid = ses->Suid; pSMB->AndXCommand = 0xFF; rc = SendReceiveNoRsp(xid, ses, (struct smb_hdr *) pSMB, 0); - if (ses->server) { - atomic_dec(&ses->server->socketUseCount); - if (atomic_read(&ses->server->socketUseCount) == 0) { - spin_lock(&GlobalMid_Lock); - ses->server->tcpStatus = CifsExiting; - spin_unlock(&GlobalMid_Lock); - rc = -ESHUTDOWN; - } - } +session_already_dead: up(&ses->sesSem); /* if session dead then we do not need to do ulogoff, @@ -1536,7 +1513,7 @@ CIFSSMBWrite(const int xid, struct cifsTconInfo *tcon, __u32 bytes_sent; __u16 byte_count; - /* cFYI(1,("write at %lld %d bytes",offset,count));*/ + /* cFYI(1, ("write at %lld %d bytes", offset, count));*/ if (tcon->ses == NULL) return -ECONNABORTED; @@ -3922,6 +3899,27 @@ GetInodeNumOut: return rc; } +/* computes length of UCS string converted to host codepage + * @src: UCS string + * @maxlen: length of the input string in UCS characters + * (not in bytes) + * + * return: size of input string in host codepage + */ +static int hostlen_fromUCS(const __le16 *src, const int maxlen, + const struct nls_table *nls_codepage) { + int i; + int hostlen = 0; + char to[4]; + int charlen; + for (i = 0; (i < maxlen) && src[i]; ++i) { + charlen = nls_codepage->uni2char(le16_to_cpu(src[i]), + to, NLS_MAX_CHARSET_SIZE); + hostlen += charlen > 0 ? charlen : 1; + } + return hostlen; +} + /* parses DFS refferal V3 structure * caller is responsible for freeing target_nodes * returns: @@ -3932,7 +3930,8 @@ static int parse_DFS_referrals(TRANSACTION2_GET_DFS_REFER_RSP *pSMBr, unsigned int *num_of_nodes, struct dfs_info3_param **target_nodes, - const struct nls_table *nls_codepage) + const struct nls_table *nls_codepage, int remap, + const char *searchName) { int i, rc = 0; char *data_end; @@ -3983,7 +3982,18 @@ parse_DFS_referrals(TRANSACTION2_GET_DFS_REFER_RSP *pSMBr, struct dfs_info3_param *node = (*target_nodes)+i; node->flags = le16_to_cpu(pSMBr->DFSFlags); - node->path_consumed = le16_to_cpu(pSMBr->PathConsumed); + if (is_unicode) { + __le16 *tmp = kmalloc(strlen(searchName)*2 + 2, + GFP_KERNEL); + cifsConvertToUCS((__le16 *) tmp, searchName, + PATH_MAX, nls_codepage, remap); + node->path_consumed = hostlen_fromUCS(tmp, + le16_to_cpu(pSMBr->PathConsumed)/2, + nls_codepage); + kfree(tmp); + } else + node->path_consumed = le16_to_cpu(pSMBr->PathConsumed); + node->server_type = le16_to_cpu(ref->ServerType); node->ref_flag = le16_to_cpu(ref->ReferralEntryFlags); @@ -4116,7 +4126,8 @@ getDFSRetry: /* parse returned result into more usable form */ rc = parse_DFS_referrals(pSMBr, num_of_nodes, - target_nodes, nls_codepage); + target_nodes, nls_codepage, remap, + searchName); GetDFSRefExit: cifs_buf_release(pSMB); diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c index 71b7661e2260..c7d341714586 100644 --- a/fs/cifs/connect.c +++ b/fs/cifs/connect.c @@ -92,6 +92,8 @@ struct smb_vol { bool seal:1; /* request transport encryption on share */ bool nodfs:1; /* Do not request DFS, even if available */ bool local_lease:1; /* check leases only on local system, not remote */ + bool noblocksnd:1; + bool noautotune:1; unsigned int rsize; unsigned int wsize; unsigned int sockopt; @@ -102,9 +104,11 @@ struct smb_vol { static int ipv4_connect(struct sockaddr_in *psin_server, struct socket **csocket, char *netb_name, - char *server_netb_name); + char *server_netb_name, + bool noblocksnd, + bool nosndbuf); /* ipv6 never set sndbuf size */ static int ipv6_connect(struct sockaddr_in6 *psin_server, - struct socket **csocket); + struct socket **csocket, bool noblocksnd); /* @@ -120,7 +124,7 @@ static int cifs_reconnect(struct TCP_Server_Info *server) { int rc = 0; - struct list_head *tmp; + struct list_head *tmp, *tmp2; struct cifsSesInfo *ses; struct cifsTconInfo *tcon; struct mid_q_entry *mid_entry; @@ -140,23 +144,17 @@ cifs_reconnect(struct TCP_Server_Info *server) /* before reconnecting the tcp session, mark the smb session (uid) and the tid bad so they are not used until reconnected */ - read_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalSMBSessionList) { - ses = list_entry(tmp, struct cifsSesInfo, cifsSessionList); - if (ses->server) { - if (ses->server == server) { - ses->status = CifsNeedReconnect; - ses->ipc_tid = 0; - } + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &server->smb_ses_list) { + ses = list_entry(tmp, struct cifsSesInfo, smb_ses_list); + ses->need_reconnect = true; + ses->ipc_tid = 0; + list_for_each(tmp2, &ses->tcon_list) { + tcon = list_entry(tmp2, struct cifsTconInfo, tcon_list); + tcon->need_reconnect = true; } - /* else tcp and smb sessions need reconnection */ - } - list_for_each(tmp, &GlobalTreeConnectionList) { - tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); - if ((tcon->ses) && (tcon->ses->server == server)) - tcon->tidStatus = CifsNeedReconnect; } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); /* do not want to be sending data on a socket we are freeing */ down(&server->tcpSem); if (server->ssocket) { @@ -189,14 +187,15 @@ cifs_reconnect(struct TCP_Server_Info *server) while ((server->tcpStatus != CifsExiting) && (server->tcpStatus != CifsGood)) { try_to_freeze(); - if (server->protocolType == IPV6) { + if (server->addr.sockAddr6.sin6_family == AF_INET6) { rc = ipv6_connect(&server->addr.sockAddr6, - &server->ssocket); + &server->ssocket, server->noautotune); } else { rc = ipv4_connect(&server->addr.sockAddr, &server->ssocket, server->workstation_RFC1001_name, - server->server_RFC1001_name); + server->server_RFC1001_name, + server->noblocksnd, server->noautotune); } if (rc) { cFYI(1, ("reconnect error %d", rc)); @@ -412,9 +411,14 @@ incomplete_rcv: msleep(1); /* minimum sleep to prevent looping allowing socket to clear and app threads to set tcpStatus CifsNeedReconnect if server hung */ - if (pdu_length < 4) + if (pdu_length < 4) { + iov.iov_base = (4 - pdu_length) + + (char *)smb_buffer; + iov.iov_len = pdu_length; + smb_msg.msg_control = NULL; + smb_msg.msg_controllen = 0; goto incomplete_rcv; - else + } else continue; } else if (length <= 0) { if (server->tcpStatus == CifsNew) { @@ -649,6 +653,11 @@ multi_t2_fnd: } } /* end while !EXITING */ + /* take it off the list, if it's not already */ + write_lock(&cifs_tcp_ses_lock); + list_del_init(&server->tcp_ses_list); + write_unlock(&cifs_tcp_ses_lock); + spin_lock(&GlobalMid_Lock); server->tcpStatus = CifsExiting; spin_unlock(&GlobalMid_Lock); @@ -681,29 +690,29 @@ multi_t2_fnd: if (smallbuf) /* no sense logging a debug message if NULL */ cifs_small_buf_release(smallbuf); - read_lock(&GlobalSMBSeslock); + /* + * BB: we shouldn't have to do any of this. It shouldn't be + * possible to exit from the thread with active SMB sessions + */ + read_lock(&cifs_tcp_ses_lock); if (list_empty(&server->pending_mid_q)) { /* loop through server session structures attached to this and mark them dead */ - list_for_each(tmp, &GlobalSMBSessionList) { - ses = - list_entry(tmp, struct cifsSesInfo, - cifsSessionList); - if (ses->server == server) { - ses->status = CifsExiting; - ses->server = NULL; - } + list_for_each(tmp, &server->smb_ses_list) { + ses = list_entry(tmp, struct cifsSesInfo, + smb_ses_list); + ses->status = CifsExiting; + ses->server = NULL; } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); } else { /* although we can not zero the server struct pointer yet, since there are active requests which may depnd on them, mark the corresponding SMB sessions as exiting too */ - list_for_each(tmp, &GlobalSMBSessionList) { + list_for_each(tmp, &server->smb_ses_list) { ses = list_entry(tmp, struct cifsSesInfo, - cifsSessionList); - if (ses->server == server) - ses->status = CifsExiting; + smb_ses_list); + ses->status = CifsExiting; } spin_lock(&GlobalMid_Lock); @@ -718,7 +727,7 @@ multi_t2_fnd: } } spin_unlock(&GlobalMid_Lock); - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); /* 1/8th of sec is more than enough time for them to exit */ msleep(125); } @@ -740,14 +749,13 @@ multi_t2_fnd: if there are any pointing to this (e.g if a crazy root user tried to kill cifsd kernel thread explicitly this might happen) */ - write_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalSMBSessionList) { - ses = list_entry(tmp, struct cifsSesInfo, - cifsSessionList); - if (ses->server == server) - ses->server = NULL; + /* BB: This shouldn't be necessary, see above */ + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &server->smb_ses_list) { + ses = list_entry(tmp, struct cifsSesInfo, smb_ses_list); + ses->server = NULL; } - write_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); kfree(server->hostname); task_to_wake = xchg(&server->tsk, NULL); @@ -1192,6 +1200,10 @@ cifs_parse_mount_options(char *options, const char *devname, /* ignore */ } else if (strnicmp(data, "rw", 2) == 0) { vol->rw = true; + } else if (strnicmp(data, "noblocksend", 11) == 0) { + vol->noblocksnd = 1; + } else if (strnicmp(data, "noautotune", 10) == 0) { + vol->noautotune = 1; } else if ((strnicmp(data, "suid", 4) == 0) || (strnicmp(data, "nosuid", 6) == 0) || (strnicmp(data, "exec", 4) == 0) || @@ -1343,94 +1355,158 @@ cifs_parse_mount_options(char *options, const char *devname, return 0; } -static struct cifsSesInfo * -cifs_find_tcp_session(struct in_addr *target_ip_addr, - struct in6_addr *target_ip6_addr, - char *userName, struct TCP_Server_Info **psrvTcp) +static struct TCP_Server_Info * +cifs_find_tcp_session(struct sockaddr *addr) { struct list_head *tmp; - struct cifsSesInfo *ses; - - *psrvTcp = NULL; + struct TCP_Server_Info *server; + struct sockaddr_in *addr4 = (struct sockaddr_in *) addr; + struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *) addr; + + write_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &cifs_tcp_ses_list) { + server = list_entry(tmp, struct TCP_Server_Info, + tcp_ses_list); + /* + * the demux thread can exit on its own while still in CifsNew + * so don't accept any sockets in that state. Since the + * tcpStatus never changes back to CifsNew it's safe to check + * for this without a lock. + */ + if (server->tcpStatus == CifsNew) + continue; - read_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalSMBSessionList) { - ses = list_entry(tmp, struct cifsSesInfo, cifsSessionList); - if (!ses->server) + if (addr->sa_family == AF_INET && + (addr4->sin_addr.s_addr != + server->addr.sockAddr.sin_addr.s_addr)) + continue; + else if (addr->sa_family == AF_INET6 && + memcmp(&server->addr.sockAddr6.sin6_addr, + &addr6->sin6_addr, sizeof(addr6->sin6_addr))) continue; - if (target_ip_addr && - ses->server->addr.sockAddr.sin_addr.s_addr != target_ip_addr->s_addr) - continue; - else if (target_ip6_addr && - memcmp(&ses->server->addr.sockAddr6.sin6_addr, - target_ip6_addr, sizeof(*target_ip6_addr))) - continue; - /* BB lock server and tcp session; increment use count here?? */ + ++server->srv_count; + write_unlock(&cifs_tcp_ses_lock); + cFYI(1, ("Existing tcp session with server found")); + return server; + } + write_unlock(&cifs_tcp_ses_lock); + return NULL; +} - /* found a match on the TCP session */ - *psrvTcp = ses->server; +static void +cifs_put_tcp_session(struct TCP_Server_Info *server) +{ + struct task_struct *task; - /* BB check if reconnection needed */ - if (strncmp(ses->userName, userName, MAX_USERNAME_SIZE) == 0) { - read_unlock(&GlobalSMBSeslock); - /* Found exact match on both TCP and - SMB sessions */ - return ses; - } - /* else tcp and smb sessions need reconnection */ + write_lock(&cifs_tcp_ses_lock); + if (--server->srv_count > 0) { + write_unlock(&cifs_tcp_ses_lock); + return; } - read_unlock(&GlobalSMBSeslock); - return NULL; + list_del_init(&server->tcp_ses_list); + write_unlock(&cifs_tcp_ses_lock); + + spin_lock(&GlobalMid_Lock); + server->tcpStatus = CifsExiting; + spin_unlock(&GlobalMid_Lock); + + task = xchg(&server->tsk, NULL); + if (task) + force_sig(SIGKILL, task); } -static struct cifsTconInfo * -find_unc(__be32 new_target_ip_addr, char *uncName, char *userName) +static struct cifsSesInfo * +cifs_find_smb_ses(struct TCP_Server_Info *server, char *username) { struct list_head *tmp; - struct cifsTconInfo *tcon; - __be32 old_ip; - - read_lock(&GlobalSMBSeslock); + struct cifsSesInfo *ses; - list_for_each(tmp, &GlobalTreeConnectionList) { - cFYI(1, ("Next tcon")); - tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); - if (!tcon->ses || !tcon->ses->server) + write_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &server->smb_ses_list) { + ses = list_entry(tmp, struct cifsSesInfo, smb_ses_list); + if (strncmp(ses->userName, username, MAX_USERNAME_SIZE)) continue; - old_ip = tcon->ses->server->addr.sockAddr.sin_addr.s_addr; - cFYI(1, ("old ip addr: %x == new ip %x ?", - old_ip, new_target_ip_addr)); + ++ses->ses_count; + write_unlock(&cifs_tcp_ses_lock); + return ses; + } + write_unlock(&cifs_tcp_ses_lock); + return NULL; +} + +static void +cifs_put_smb_ses(struct cifsSesInfo *ses) +{ + int xid; + struct TCP_Server_Info *server = ses->server; - if (old_ip != new_target_ip_addr) - continue; + write_lock(&cifs_tcp_ses_lock); + if (--ses->ses_count > 0) { + write_unlock(&cifs_tcp_ses_lock); + return; + } - /* BB lock tcon, server, tcp session and increment use count? */ - /* found a match on the TCP session */ - /* BB check if reconnection needed */ - cFYI(1, ("IP match, old UNC: %s new: %s", - tcon->treeName, uncName)); + list_del_init(&ses->smb_ses_list); + write_unlock(&cifs_tcp_ses_lock); - if (strncmp(tcon->treeName, uncName, MAX_TREE_SIZE)) - continue; + if (ses->status == CifsGood) { + xid = GetXid(); + CIFSSMBLogoff(xid, ses); + _FreeXid(xid); + } + sesInfoFree(ses); + cifs_put_tcp_session(server); +} - cFYI(1, ("and old usr: %s new: %s", - tcon->treeName, uncName)); +static struct cifsTconInfo * +cifs_find_tcon(struct cifsSesInfo *ses, const char *unc) +{ + struct list_head *tmp; + struct cifsTconInfo *tcon; - if (strncmp(tcon->ses->userName, userName, MAX_USERNAME_SIZE)) + write_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &ses->tcon_list) { + tcon = list_entry(tmp, struct cifsTconInfo, tcon_list); + if (tcon->tidStatus == CifsExiting) + continue; + if (strncmp(tcon->treeName, unc, MAX_TREE_SIZE)) continue; - /* matched smb session (user name) */ - read_unlock(&GlobalSMBSeslock); + ++tcon->tc_count; + write_unlock(&cifs_tcp_ses_lock); return tcon; } - - read_unlock(&GlobalSMBSeslock); + write_unlock(&cifs_tcp_ses_lock); return NULL; } +static void +cifs_put_tcon(struct cifsTconInfo *tcon) +{ + int xid; + struct cifsSesInfo *ses = tcon->ses; + + write_lock(&cifs_tcp_ses_lock); + if (--tcon->tc_count > 0) { + write_unlock(&cifs_tcp_ses_lock); + return; + } + + list_del_init(&tcon->tcon_list); + write_unlock(&cifs_tcp_ses_lock); + + xid = GetXid(); + CIFSSMBTDis(xid, tcon); + _FreeXid(xid); + + DeleteTconOplockQEntries(tcon); + tconInfoFree(tcon); + cifs_put_smb_ses(ses); +} + int get_dfs_path(int xid, struct cifsSesInfo *pSesInfo, const char *old_path, const struct nls_table *nls_codepage, unsigned int *pnum_referrals, @@ -1518,7 +1594,8 @@ static void rfc1002mangle(char *target, char *source, unsigned int length) static int ipv4_connect(struct sockaddr_in *psin_server, struct socket **csocket, - char *netbios_name, char *target_name) + char *netbios_name, char *target_name, + bool noblocksnd, bool noautotune) { int rc = 0; int connected = 0; @@ -1590,11 +1667,16 @@ ipv4_connect(struct sockaddr_in *psin_server, struct socket **csocket, (*csocket)->sk->sk_sndbuf, (*csocket)->sk->sk_rcvbuf, (*csocket)->sk->sk_rcvtimeo)); (*csocket)->sk->sk_rcvtimeo = 7 * HZ; + if (!noblocksnd) + (*csocket)->sk->sk_sndtimeo = 3 * HZ; + /* make the bufsizes depend on wsize/rsize and max requests */ - if ((*csocket)->sk->sk_sndbuf < (200 * 1024)) - (*csocket)->sk->sk_sndbuf = 200 * 1024; - if ((*csocket)->sk->sk_rcvbuf < (140 * 1024)) - (*csocket)->sk->sk_rcvbuf = 140 * 1024; + if (noautotune) { + if ((*csocket)->sk->sk_sndbuf < (200 * 1024)) + (*csocket)->sk->sk_sndbuf = 200 * 1024; + if ((*csocket)->sk->sk_rcvbuf < (140 * 1024)) + (*csocket)->sk->sk_rcvbuf = 140 * 1024; + } /* send RFC1001 sessinit */ if (psin_server->sin_port == htons(RFC1001_PORT)) { @@ -1631,7 +1713,7 @@ ipv4_connect(struct sockaddr_in *psin_server, struct socket **csocket, /* sizeof RFC1002_SESSION_REQUEST with no scope */ smb_buf->smb_buf_length = 0x81000044; rc = smb_send(*csocket, smb_buf, 0x44, - (struct sockaddr *)psin_server); + (struct sockaddr *)psin_server, noblocksnd); kfree(ses_init_buf); msleep(1); /* RFC1001 layer in at least one server requires very short break before negprot @@ -1651,7 +1733,8 @@ ipv4_connect(struct sockaddr_in *psin_server, struct socket **csocket, } static int -ipv6_connect(struct sockaddr_in6 *psin_server, struct socket **csocket) +ipv6_connect(struct sockaddr_in6 *psin_server, struct socket **csocket, + bool noblocksnd) { int rc = 0; int connected = 0; @@ -1720,6 +1803,9 @@ ipv6_connect(struct sockaddr_in6 *psin_server, struct socket **csocket) the default. sock_setsockopt not used because it expects user space buffer */ (*csocket)->sk->sk_rcvtimeo = 7 * HZ; + if (!noblocksnd) + (*csocket)->sk->sk_sndtimeo = 3 * HZ; + return rc; } @@ -1857,14 +1943,90 @@ convert_delimiter(char *path, char delim) } } -static void -kill_cifsd(struct TCP_Server_Info *server) +static void setup_cifs_sb(struct smb_vol *pvolume_info, + struct cifs_sb_info *cifs_sb) { - struct task_struct *task; - - task = xchg(&server->tsk, NULL); - if (task) - force_sig(SIGKILL, task); + if (pvolume_info->rsize > CIFSMaxBufSize) { + cERROR(1, ("rsize %d too large, using MaxBufSize", + pvolume_info->rsize)); + cifs_sb->rsize = CIFSMaxBufSize; + } else if ((pvolume_info->rsize) && + (pvolume_info->rsize <= CIFSMaxBufSize)) + cifs_sb->rsize = pvolume_info->rsize; + else /* default */ + cifs_sb->rsize = CIFSMaxBufSize; + + if (pvolume_info->wsize > PAGEVEC_SIZE * PAGE_CACHE_SIZE) { + cERROR(1, ("wsize %d too large, using 4096 instead", + pvolume_info->wsize)); + cifs_sb->wsize = 4096; + } else if (pvolume_info->wsize) + cifs_sb->wsize = pvolume_info->wsize; + else + cifs_sb->wsize = min_t(const int, + PAGEVEC_SIZE * PAGE_CACHE_SIZE, + 127*1024); + /* old default of CIFSMaxBufSize was too small now + that SMB Write2 can send multiple pages in kvec. + RFC1001 does not describe what happens when frame + bigger than 128K is sent so use that as max in + conjunction with 52K kvec constraint on arch with 4K + page size */ + + if (cifs_sb->rsize < 2048) { + cifs_sb->rsize = 2048; + /* Windows ME may prefer this */ + cFYI(1, ("readsize set to minimum: 2048")); + } + /* calculate prepath */ + cifs_sb->prepath = pvolume_info->prepath; + if (cifs_sb->prepath) { + cifs_sb->prepathlen = strlen(cifs_sb->prepath); + /* we can not convert the / to \ in the path + separators in the prefixpath yet because we do not + know (until reset_cifs_unix_caps is called later) + whether POSIX PATH CAP is available. We normalize + the / to \ after reset_cifs_unix_caps is called */ + pvolume_info->prepath = NULL; + } else + cifs_sb->prepathlen = 0; + cifs_sb->mnt_uid = pvolume_info->linux_uid; + cifs_sb->mnt_gid = pvolume_info->linux_gid; + cifs_sb->mnt_file_mode = pvolume_info->file_mode; + cifs_sb->mnt_dir_mode = pvolume_info->dir_mode; + cFYI(1, ("file mode: 0x%x dir mode: 0x%x", + cifs_sb->mnt_file_mode, cifs_sb->mnt_dir_mode)); + + if (pvolume_info->noperm) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_NO_PERM; + if (pvolume_info->setuids) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_SET_UID; + if (pvolume_info->server_ino) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_SERVER_INUM; + if (pvolume_info->remap) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_MAP_SPECIAL_CHR; + if (pvolume_info->no_xattr) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_NO_XATTR; + if (pvolume_info->sfu_emul) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_UNX_EMUL; + if (pvolume_info->nobrl) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_NO_BRL; + if (pvolume_info->cifs_acl) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_CIFS_ACL; + if (pvolume_info->override_uid) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_OVERR_UID; + if (pvolume_info->override_gid) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_OVERR_GID; + if (pvolume_info->dynperm) + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_DYNPERM; + if (pvolume_info->direct_io) { + cFYI(1, ("mounting share using direct i/o")); + cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_DIRECT_IO; + } + + if ((pvolume_info->cifs_acl) && (pvolume_info->dynperm)) + cERROR(1, ("mount option dynperm ignored if cifsacl " + "mount option supported")); } int @@ -1873,13 +2035,12 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, { int rc = 0; int xid; - int address_type = AF_INET; struct socket *csocket = NULL; - struct sockaddr_in sin_server; - struct sockaddr_in6 sin_server6; + struct sockaddr addr; + struct sockaddr_in *sin_server = (struct sockaddr_in *) &addr; + struct sockaddr_in6 *sin_server6 = (struct sockaddr_in6 *) &addr; struct smb_vol volume_info; struct cifsSesInfo *pSesInfo = NULL; - struct cifsSesInfo *existingCifsSes = NULL; struct cifsTconInfo *tcon = NULL; struct TCP_Server_Info *srvTcp = NULL; @@ -1887,6 +2048,7 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, /* cFYI(1, ("Entering cifs_mount. Xid: %d with: %s", xid, mount_data)); */ + memset(&addr, 0, sizeof(struct sockaddr)); memset(&volume_info, 0, sizeof(struct smb_vol)); if (cifs_parse_mount_options(mount_data, devname, &volume_info)) { rc = -EINVAL; @@ -1909,16 +2071,16 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, if (volume_info.UNCip && volume_info.UNC) { rc = cifs_inet_pton(AF_INET, volume_info.UNCip, - &sin_server.sin_addr.s_addr); + &sin_server->sin_addr.s_addr); if (rc <= 0) { /* not ipv4 address, try ipv6 */ rc = cifs_inet_pton(AF_INET6, volume_info.UNCip, - &sin_server6.sin6_addr.in6_u); + &sin_server6->sin6_addr.in6_u); if (rc > 0) - address_type = AF_INET6; + addr.sa_family = AF_INET6; } else { - address_type = AF_INET; + addr.sa_family = AF_INET; } if (rc <= 0) { @@ -1958,38 +2120,25 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, } } - if (address_type == AF_INET) - existingCifsSes = cifs_find_tcp_session(&sin_server.sin_addr, - NULL /* no ipv6 addr */, - volume_info.username, &srvTcp); - else if (address_type == AF_INET6) { - cFYI(1, ("looking for ipv6 address")); - existingCifsSes = cifs_find_tcp_session(NULL /* no ipv4 addr */, - &sin_server6.sin6_addr, - volume_info.username, &srvTcp); - } else { - rc = -EINVAL; - goto out; - } - - if (srvTcp) { - cFYI(1, ("Existing tcp session with server found")); - } else { /* create socket */ - if (volume_info.port) - sin_server.sin_port = htons(volume_info.port); - else - sin_server.sin_port = 0; - if (address_type == AF_INET6) { + srvTcp = cifs_find_tcp_session(&addr); + if (!srvTcp) { /* create socket */ + if (addr.sa_family == AF_INET6) { cFYI(1, ("attempting ipv6 connect")); /* BB should we allow ipv6 on port 139? */ /* other OS never observed in Wild doing 139 with v6 */ - rc = ipv6_connect(&sin_server6, &csocket); - } else - rc = ipv4_connect(&sin_server, &csocket, + sin_server6->sin6_port = htons(volume_info.port); + rc = ipv6_connect(sin_server6, &csocket, + volume_info.noblocksnd); + } else { + sin_server->sin_port = htons(volume_info.port); + rc = ipv4_connect(sin_server, &csocket, volume_info.source_rfc1001_name, - volume_info.target_rfc1001_name); + volume_info.target_rfc1001_name, + volume_info.noblocksnd, + volume_info.noautotune); + } if (rc < 0) { - cERROR(1, ("Error connecting to IPv4 socket. " + cERROR(1, ("Error connecting to socket. " "Aborting operation")); if (csocket != NULL) sock_release(csocket); @@ -2002,12 +2151,17 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, sock_release(csocket); goto out; } else { - memcpy(&srvTcp->addr.sockAddr, &sin_server, - sizeof(struct sockaddr_in)); + srvTcp->noblocksnd = volume_info.noblocksnd; + srvTcp->noautotune = volume_info.noautotune; + if (addr.sa_family == AF_INET6) + memcpy(&srvTcp->addr.sockAddr6, sin_server6, + sizeof(struct sockaddr_in6)); + else + memcpy(&srvTcp->addr.sockAddr, sin_server, + sizeof(struct sockaddr_in)); atomic_set(&srvTcp->inFlight, 0); /* BB Add code for ipv6 case too */ srvTcp->ssocket = csocket; - srvTcp->protocolType = IPV4; srvTcp->hostname = extract_hostname(volume_info.UNC); if (IS_ERR(srvTcp->hostname)) { rc = PTR_ERR(srvTcp->hostname); @@ -2037,15 +2191,28 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, memcpy(srvTcp->server_RFC1001_name, volume_info.target_rfc1001_name, 16); srvTcp->sequence_number = 0; + INIT_LIST_HEAD(&srvTcp->tcp_ses_list); + INIT_LIST_HEAD(&srvTcp->smb_ses_list); + ++srvTcp->srv_count; + write_lock(&cifs_tcp_ses_lock); + list_add(&srvTcp->tcp_ses_list, + &cifs_tcp_ses_list); + write_unlock(&cifs_tcp_ses_lock); } } - if (existingCifsSes) { - pSesInfo = existingCifsSes; + pSesInfo = cifs_find_smb_ses(srvTcp, volume_info.username); + if (pSesInfo) { cFYI(1, ("Existing smb sess found (status=%d)", pSesInfo->status)); + /* + * The existing SMB session already has a reference to srvTcp, + * so we can put back the extra one we got before + */ + cifs_put_tcp_session(srvTcp); + down(&pSesInfo->sesSem); - if (pSesInfo->status == CifsNeedReconnect) { + if (pSesInfo->need_reconnect) { cFYI(1, ("Session needs reconnect")); rc = cifs_setup_session(xid, pSesInfo, cifs_sb->local_nls); @@ -2054,187 +2221,101 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, } else if (!rc) { cFYI(1, ("Existing smb sess not found")); pSesInfo = sesInfoAlloc(); - if (pSesInfo == NULL) + if (pSesInfo == NULL) { rc = -ENOMEM; - else { - pSesInfo->server = srvTcp; - sprintf(pSesInfo->serverName, "%u.%u.%u.%u", - NIPQUAD(sin_server.sin_addr.s_addr)); - } + goto mount_fail_check; + } + + /* new SMB session uses our srvTcp ref */ + pSesInfo->server = srvTcp; + sprintf(pSesInfo->serverName, "%u.%u.%u.%u", + NIPQUAD(sin_server->sin_addr.s_addr)); + + write_lock(&cifs_tcp_ses_lock); + list_add(&pSesInfo->smb_ses_list, &srvTcp->smb_ses_list); + write_unlock(&cifs_tcp_ses_lock); + + /* volume_info.password freed at unmount */ + if (volume_info.password) { + pSesInfo->password = volume_info.password; + /* set to NULL to prevent freeing on exit */ + volume_info.password = NULL; + } + if (volume_info.username) + strncpy(pSesInfo->userName, volume_info.username, + MAX_USERNAME_SIZE); + if (volume_info.domainname) { + int len = strlen(volume_info.domainname); + pSesInfo->domainName = kmalloc(len + 1, GFP_KERNEL); + if (pSesInfo->domainName) + strcpy(pSesInfo->domainName, + volume_info.domainname); + } + pSesInfo->linux_uid = volume_info.linux_uid; + pSesInfo->overrideSecFlg = volume_info.secFlg; + down(&pSesInfo->sesSem); - if (!rc) { - /* volume_info.password freed at unmount */ - if (volume_info.password) { - pSesInfo->password = volume_info.password; - /* set to NULL to prevent freeing on exit */ - volume_info.password = NULL; - } - if (volume_info.username) - strncpy(pSesInfo->userName, - volume_info.username, - MAX_USERNAME_SIZE); - if (volume_info.domainname) { - int len = strlen(volume_info.domainname); - pSesInfo->domainName = - kmalloc(len + 1, GFP_KERNEL); - if (pSesInfo->domainName) - strcpy(pSesInfo->domainName, - volume_info.domainname); - } - pSesInfo->linux_uid = volume_info.linux_uid; - pSesInfo->overrideSecFlg = volume_info.secFlg; - down(&pSesInfo->sesSem); - /* BB FIXME need to pass vol->secFlgs BB */ - rc = cifs_setup_session(xid, pSesInfo, - cifs_sb->local_nls); - up(&pSesInfo->sesSem); - if (!rc) - atomic_inc(&srvTcp->socketUseCount); - } + /* BB FIXME need to pass vol->secFlgs BB */ + rc = cifs_setup_session(xid, pSesInfo, + cifs_sb->local_nls); + up(&pSesInfo->sesSem); } /* search for existing tcon to this server share */ if (!rc) { - if (volume_info.rsize > CIFSMaxBufSize) { - cERROR(1, ("rsize %d too large, using MaxBufSize", - volume_info.rsize)); - cifs_sb->rsize = CIFSMaxBufSize; - } else if ((volume_info.rsize) && - (volume_info.rsize <= CIFSMaxBufSize)) - cifs_sb->rsize = volume_info.rsize; - else /* default */ - cifs_sb->rsize = CIFSMaxBufSize; - - if (volume_info.wsize > PAGEVEC_SIZE * PAGE_CACHE_SIZE) { - cERROR(1, ("wsize %d too large, using 4096 instead", - volume_info.wsize)); - cifs_sb->wsize = 4096; - } else if (volume_info.wsize) - cifs_sb->wsize = volume_info.wsize; - else - cifs_sb->wsize = - min_t(const int, PAGEVEC_SIZE * PAGE_CACHE_SIZE, - 127*1024); - /* old default of CIFSMaxBufSize was too small now - that SMB Write2 can send multiple pages in kvec. - RFC1001 does not describe what happens when frame - bigger than 128K is sent so use that as max in - conjunction with 52K kvec constraint on arch with 4K - page size */ - - if (cifs_sb->rsize < 2048) { - cifs_sb->rsize = 2048; - /* Windows ME may prefer this */ - cFYI(1, ("readsize set to minimum: 2048")); - } - /* calculate prepath */ - cifs_sb->prepath = volume_info.prepath; - if (cifs_sb->prepath) { - cifs_sb->prepathlen = strlen(cifs_sb->prepath); - /* we can not convert the / to \ in the path - separators in the prefixpath yet because we do not - know (until reset_cifs_unix_caps is called later) - whether POSIX PATH CAP is available. We normalize - the / to \ after reset_cifs_unix_caps is called */ - volume_info.prepath = NULL; - } else - cifs_sb->prepathlen = 0; - cifs_sb->mnt_uid = volume_info.linux_uid; - cifs_sb->mnt_gid = volume_info.linux_gid; - cifs_sb->mnt_file_mode = volume_info.file_mode; - cifs_sb->mnt_dir_mode = volume_info.dir_mode; - cFYI(1, ("file mode: 0x%x dir mode: 0x%x", - cifs_sb->mnt_file_mode, cifs_sb->mnt_dir_mode)); - - if (volume_info.noperm) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_NO_PERM; - if (volume_info.setuids) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_SET_UID; - if (volume_info.server_ino) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_SERVER_INUM; - if (volume_info.remap) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_MAP_SPECIAL_CHR; - if (volume_info.no_xattr) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_NO_XATTR; - if (volume_info.sfu_emul) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_UNX_EMUL; - if (volume_info.nobrl) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_NO_BRL; - if (volume_info.cifs_acl) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_CIFS_ACL; - if (volume_info.override_uid) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_OVERR_UID; - if (volume_info.override_gid) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_OVERR_GID; - if (volume_info.dynperm) - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_DYNPERM; - if (volume_info.direct_io) { - cFYI(1, ("mounting share using direct i/o")); - cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_DIRECT_IO; - } - - if ((volume_info.cifs_acl) && (volume_info.dynperm)) - cERROR(1, ("mount option dynperm ignored if cifsacl " - "mount option supported")); + setup_cifs_sb(&volume_info, cifs_sb); - tcon = - find_unc(sin_server.sin_addr.s_addr, volume_info.UNC, - volume_info.username); + tcon = cifs_find_tcon(pSesInfo, volume_info.UNC); if (tcon) { cFYI(1, ("Found match on UNC path")); - /* we can have only one retry value for a connection - to a share so for resources mounted more than once - to the same server share the last value passed in - for the retry flag is used */ - tcon->retry = volume_info.retry; - tcon->nocase = volume_info.nocase; - tcon->local_lease = volume_info.local_lease; + /* existing tcon already has a reference */ + cifs_put_smb_ses(pSesInfo); if (tcon->seal != volume_info.seal) cERROR(1, ("transport encryption setting " "conflicts with existing tid")); } else { tcon = tconInfoAlloc(); - if (tcon == NULL) + if (tcon == NULL) { rc = -ENOMEM; - else { - /* check for null share name ie connecting to - * dfs root */ - - /* BB check if this works for exactly length - * three strings */ - if ((strchr(volume_info.UNC + 3, '\\') == NULL) - && (strchr(volume_info.UNC + 3, '/') == - NULL)) { -/* rc = connect_to_dfs_path(xid, pSesInfo, - "", cifs_sb->local_nls, - cifs_sb->mnt_cifs_flags & - CIFS_MOUNT_MAP_SPECIAL_CHR);*/ - cFYI(1, ("DFS root not supported")); - rc = -ENODEV; - goto out; - } else { - /* BB Do we need to wrap sesSem around - * this TCon call and Unix SetFS as - * we do on SessSetup and reconnect? */ - rc = CIFSTCon(xid, pSesInfo, - volume_info.UNC, - tcon, cifs_sb->local_nls); - cFYI(1, ("CIFS Tcon rc = %d", rc)); - if (volume_info.nodfs) { - tcon->Flags &= - ~SMB_SHARE_IS_IN_DFS; - cFYI(1, ("DFS disabled (%d)", - tcon->Flags)); - } - } - if (!rc) { - atomic_inc(&pSesInfo->inUse); - tcon->retry = volume_info.retry; - tcon->nocase = volume_info.nocase; - tcon->seal = volume_info.seal; + goto mount_fail_check; + } + tcon->ses = pSesInfo; + + /* check for null share name ie connect to dfs root */ + if ((strchr(volume_info.UNC + 3, '\\') == NULL) + && (strchr(volume_info.UNC + 3, '/') == NULL)) { + /* rc = connect_to_dfs_path(...) */ + cFYI(1, ("DFS root not supported")); + rc = -ENODEV; + goto mount_fail_check; + } else { + /* BB Do we need to wrap sesSem around + * this TCon call and Unix SetFS as + * we do on SessSetup and reconnect? */ + rc = CIFSTCon(xid, pSesInfo, volume_info.UNC, + tcon, cifs_sb->local_nls); + cFYI(1, ("CIFS Tcon rc = %d", rc)); + if (volume_info.nodfs) { + tcon->Flags &= ~SMB_SHARE_IS_IN_DFS; + cFYI(1, ("DFS disabled (%d)", + tcon->Flags)); } } - } + if (rc) + goto mount_fail_check; + tcon->seal = volume_info.seal; + write_lock(&cifs_tcp_ses_lock); + list_add(&tcon->tcon_list, &pSesInfo->tcon_list); + write_unlock(&cifs_tcp_ses_lock); + } + + /* we can have only one retry value for a connection + to a share so for resources mounted more than once + to the same server share the last value passed in + for the retry flag is used */ + tcon->retry = volume_info.retry; + tcon->nocase = volume_info.nocase; + tcon->local_lease = volume_info.local_lease; } if (pSesInfo) { if (pSesInfo->capabilities & CAP_LARGE_FILES) { @@ -2246,80 +2327,49 @@ cifs_mount(struct super_block *sb, struct cifs_sb_info *cifs_sb, /* BB FIXME fix time_gran to be larger for LANMAN sessions */ sb->s_time_gran = 100; -/* on error free sesinfo and tcon struct if needed */ +mount_fail_check: + /* on error free sesinfo and tcon struct if needed */ if (rc) { - /* if session setup failed, use count is zero but - we still need to free cifsd thread */ - if (atomic_read(&srvTcp->socketUseCount) == 0) { - spin_lock(&GlobalMid_Lock); - srvTcp->tcpStatus = CifsExiting; - spin_unlock(&GlobalMid_Lock); - kill_cifsd(srvTcp); - } - /* If find_unc succeeded then rc == 0 so we can not end */ - if (tcon) /* up accidently freeing someone elses tcon struct */ - tconInfoFree(tcon); - if (existingCifsSes == NULL) { - if (pSesInfo) { - if ((pSesInfo->server) && - (pSesInfo->status == CifsGood)) { - int temp_rc; - temp_rc = CIFSSMBLogoff(xid, pSesInfo); - /* if the socketUseCount is now zero */ - if ((temp_rc == -ESHUTDOWN) && - (pSesInfo->server)) - kill_cifsd(pSesInfo->server); - } else { - cFYI(1, ("No session or bad tcon")); - if (pSesInfo->server) { - spin_lock(&GlobalMid_Lock); - srvTcp->tcpStatus = CifsExiting; - spin_unlock(&GlobalMid_Lock); - kill_cifsd(pSesInfo->server); - } - } - sesInfoFree(pSesInfo); - /* pSesInfo = NULL; */ - } - } - } else { - atomic_inc(&tcon->useCount); - cifs_sb->tcon = tcon; - tcon->ses = pSesInfo; - - /* do not care if following two calls succeed - informational */ - if (!tcon->ipc) { - CIFSSMBQFSDeviceInfo(xid, tcon); - CIFSSMBQFSAttributeInfo(xid, tcon); - } - - /* tell server which Unix caps we support */ - if (tcon->ses->capabilities & CAP_UNIX) - /* reset of caps checks mount to see if unix extensions - disabled for just this mount */ - reset_cifs_unix_caps(xid, tcon, sb, &volume_info); + /* If find_unc succeeded then rc == 0 so we can not end */ + /* up accidently freeing someone elses tcon struct */ + if (tcon) + cifs_put_tcon(tcon); + else if (pSesInfo) + cifs_put_smb_ses(pSesInfo); else - tcon->unix_ext = 0; /* server does not support them */ + cifs_put_tcp_session(srvTcp); + goto out; + } + cifs_sb->tcon = tcon; - /* convert forward to back slashes in prepath here if needed */ - if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_POSIX_PATHS) == 0) - convert_delimiter(cifs_sb->prepath, - CIFS_DIR_SEP(cifs_sb)); + /* do not care if following two calls succeed - informational */ + if (!tcon->ipc) { + CIFSSMBQFSDeviceInfo(xid, tcon); + CIFSSMBQFSAttributeInfo(xid, tcon); + } - if ((tcon->unix_ext == 0) && (cifs_sb->rsize > (1024 * 127))) { - cifs_sb->rsize = 1024 * 127; - cFYI(DBG2, - ("no very large read support, rsize now 127K")); - } - if (!(tcon->ses->capabilities & CAP_LARGE_WRITE_X)) - cifs_sb->wsize = min(cifs_sb->wsize, - (tcon->ses->server->maxBuf - - MAX_CIFS_HDR_SIZE)); - if (!(tcon->ses->capabilities & CAP_LARGE_READ_X)) - cifs_sb->rsize = min(cifs_sb->rsize, - (tcon->ses->server->maxBuf - - MAX_CIFS_HDR_SIZE)); + /* tell server which Unix caps we support */ + if (tcon->ses->capabilities & CAP_UNIX) + /* reset of caps checks mount to see if unix extensions + disabled for just this mount */ + reset_cifs_unix_caps(xid, tcon, sb, &volume_info); + else + tcon->unix_ext = 0; /* server does not support them */ + + /* convert forward to back slashes in prepath here if needed */ + if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_POSIX_PATHS) == 0) + convert_delimiter(cifs_sb->prepath, CIFS_DIR_SEP(cifs_sb)); + + if ((tcon->unix_ext == 0) && (cifs_sb->rsize > (1024 * 127))) { + cifs_sb->rsize = 1024 * 127; + cFYI(DBG2, ("no very large read support, rsize now 127K")); } + if (!(tcon->ses->capabilities & CAP_LARGE_WRITE_X)) + cifs_sb->wsize = min(cifs_sb->wsize, + (tcon->ses->server->maxBuf - MAX_CIFS_HDR_SIZE)); + if (!(tcon->ses->capabilities & CAP_LARGE_READ_X)) + cifs_sb->rsize = min(cifs_sb->rsize, + (tcon->ses->server->maxBuf - MAX_CIFS_HDR_SIZE)); /* volume_info.password is freed above when existing session found (in which case it is not needed anymore) but when new sesion is created @@ -3489,6 +3539,7 @@ CIFSTCon(unsigned int xid, struct cifsSesInfo *ses, /* above now done in SendReceive */ if ((rc == 0) && (tcon != NULL)) { tcon->tidStatus = CifsGood; + tcon->need_reconnect = false; tcon->tid = smb_buffer_response->Tid; bcc_ptr = pByteArea(smb_buffer_response); length = strnlen(bcc_ptr, BCC(smb_buffer_response) - 2); @@ -3560,48 +3611,17 @@ int cifs_umount(struct super_block *sb, struct cifs_sb_info *cifs_sb) { int rc = 0; - int xid; - struct cifsSesInfo *ses = NULL; char *tmp; - xid = GetXid(); - - if (cifs_sb->tcon) { - ses = cifs_sb->tcon->ses; /* save ptr to ses before delete tcon!*/ - rc = CIFSSMBTDis(xid, cifs_sb->tcon); - if (rc == -EBUSY) { - FreeXid(xid); - return 0; - } - DeleteTconOplockQEntries(cifs_sb->tcon); - tconInfoFree(cifs_sb->tcon); - if ((ses) && (ses->server)) { - /* save off task so we do not refer to ses later */ - cFYI(1, ("About to do SMBLogoff ")); - rc = CIFSSMBLogoff(xid, ses); - if (rc == -EBUSY) { - FreeXid(xid); - return 0; - } else if (rc == -ESHUTDOWN) { - cFYI(1, ("Waking up socket by sending signal")); - if (ses->server) - kill_cifsd(ses->server); - rc = 0; - } /* else - we have an smb session - left on this socket do not kill cifsd */ - } else - cFYI(1, ("No session or bad tcon")); - } + if (cifs_sb->tcon) + cifs_put_tcon(cifs_sb->tcon); cifs_sb->tcon = NULL; tmp = cifs_sb->prepath; cifs_sb->prepathlen = 0; cifs_sb->prepath = NULL; kfree(tmp); - if (ses) - sesInfoFree(ses); - FreeXid(xid); return rc; } @@ -3717,6 +3737,7 @@ int cifs_setup_session(unsigned int xid, struct cifsSesInfo *pSesInfo, cFYI(1, ("CIFS Session Established successfully")); spin_lock(&GlobalMid_Lock); pSesInfo->status = CifsGood; + pSesInfo->need_reconnect = false; spin_unlock(&GlobalMid_Lock); } diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 62d8bd8f14c0..f0a81e631ae6 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -488,12 +488,13 @@ int cifs_close(struct inode *inode, struct file *file) pTcon = cifs_sb->tcon; if (pSMBFile) { struct cifsLockInfo *li, *tmp; - + write_lock(&GlobalSMBSeslock); pSMBFile->closePend = true; if (pTcon) { /* no sense reconnecting to close a file that is already closed */ - if (pTcon->tidStatus != CifsNeedReconnect) { + if (!pTcon->need_reconnect) { + write_unlock(&GlobalSMBSeslock); timeout = 2; while ((atomic_read(&pSMBFile->wrtPending) != 0) && (timeout <= 2048)) { @@ -510,12 +511,15 @@ int cifs_close(struct inode *inode, struct file *file) timeout *= 4; } if (atomic_read(&pSMBFile->wrtPending)) - cERROR(1, - ("close with pending writes")); - rc = CIFSSMBClose(xid, pTcon, + cERROR(1, ("close with pending write")); + if (!pTcon->need_reconnect && + !pSMBFile->invalidHandle) + rc = CIFSSMBClose(xid, pTcon, pSMBFile->netfid); - } - } + } else + write_unlock(&GlobalSMBSeslock); + } else + write_unlock(&GlobalSMBSeslock); /* Delete any outstanding lock records. We'll lose them when the file is closed anyway. */ @@ -587,15 +591,18 @@ int cifs_closedir(struct inode *inode, struct file *file) pTcon = cifs_sb->tcon; cFYI(1, ("Freeing private data in close dir")); + write_lock(&GlobalSMBSeslock); if (!pCFileStruct->srch_inf.endOfSearch && !pCFileStruct->invalidHandle) { pCFileStruct->invalidHandle = true; + write_unlock(&GlobalSMBSeslock); rc = CIFSFindClose(xid, pTcon, pCFileStruct->netfid); cFYI(1, ("Closing uncompleted readdir with rc %d", rc)); /* not much we can do if it fails anyway, ignore rc */ rc = 0; - } + } else + write_unlock(&GlobalSMBSeslock); ptmp = pCFileStruct->srch_inf.ntwrk_buf_start; if (ptmp) { cFYI(1, ("closedir free smb buf in srch struct")); @@ -1404,7 +1411,10 @@ retry: if ((wbc->nr_to_write -= n_iov) <= 0) done = 1; index = next; - } + } else + /* Need to re-find the pages we skipped */ + index = pvec.pages[0]->index + 1; + pagevec_release(&pvec); } if (!scanned && !done) { @@ -1465,7 +1475,11 @@ static int cifs_write_end(struct file *file, struct address_space *mapping, cFYI(1, ("write_end for page %p from pos %lld with %d bytes", page, pos, copied)); - if (!PageUptodate(page) && copied == PAGE_CACHE_SIZE) + if (PageChecked(page)) { + if (copied == len) + SetPageUptodate(page); + ClearPageChecked(page); + } else if (!PageUptodate(page) && copied == PAGE_CACHE_SIZE) SetPageUptodate(page); if (!PageUptodate(page)) { @@ -1824,7 +1838,7 @@ static int cifs_readpages(struct file *file, struct address_space *mapping, pTcon = cifs_sb->tcon; pagevec_init(&lru_pvec, 0); - cFYI(DBG2, ("rpages: num pages %d", num_pages)); + cFYI(DBG2, ("rpages: num pages %d", num_pages)); for (i = 0; i < num_pages; ) { unsigned contig_pages; struct page *tmp_page; @@ -2052,39 +2066,70 @@ static int cifs_write_begin(struct file *file, struct address_space *mapping, { pgoff_t index = pos >> PAGE_CACHE_SHIFT; loff_t offset = pos & (PAGE_CACHE_SIZE - 1); + loff_t page_start = pos & PAGE_MASK; + loff_t i_size; + struct page *page; + int rc = 0; cFYI(1, ("write_begin from %lld len %d", (long long)pos, len)); - *pagep = __grab_cache_page(mapping, index); - if (!*pagep) - return -ENOMEM; - - if (PageUptodate(*pagep)) - return 0; + page = __grab_cache_page(mapping, index); + if (!page) { + rc = -ENOMEM; + goto out; + } - /* If we are writing a full page it will be up to date, - no need to read from the server */ - if (len == PAGE_CACHE_SIZE && flags & AOP_FLAG_UNINTERRUPTIBLE) - return 0; + if (PageUptodate(page)) + goto out; - if ((file->f_flags & O_ACCMODE) != O_WRONLY) { - int rc; + /* + * If we write a full page it will be up to date, no need to read from + * the server. If the write is short, we'll end up doing a sync write + * instead. + */ + if (len == PAGE_CACHE_SIZE) + goto out; - /* might as well read a page, it is fast enough */ - rc = cifs_readpage_worker(file, *pagep, &offset); + /* + * optimize away the read when we have an oplock, and we're not + * expecting to use any of the data we'd be reading in. That + * is, when the page lies beyond the EOF, or straddles the EOF + * and the write will cover all of the existing data. + */ + if (CIFS_I(mapping->host)->clientCanCacheRead) { + i_size = i_size_read(mapping->host); + if (page_start >= i_size || + (offset == 0 && (pos + len) >= i_size)) { + zero_user_segments(page, 0, offset, + offset + len, + PAGE_CACHE_SIZE); + /* + * PageChecked means that the parts of the page + * to which we're not writing are considered up + * to date. Once the data is copied to the + * page, it can be set uptodate. + */ + SetPageChecked(page); + goto out; + } + } - /* we do not need to pass errors back - e.g. if we do not have read access to the file - because cifs_write_end will attempt synchronous writes - -- shaggy */ + if ((file->f_flags & O_ACCMODE) != O_WRONLY) { + /* + * might as well read a page, it is fast enough. If we get + * an error, we don't need to return it. cifs_write_end will + * do a sync write instead since PG_uptodate isn't set. + */ + cifs_readpage_worker(file, page, &page_start); } else { /* we could try using another file handle if there is one - but how would we lock it to prevent close of that handle racing with this read? In any case this will be written out by write_end so is fine */ } - - return 0; +out: + *pagep = page; + return rc; } const struct address_space_operations cifs_addr_ops = { diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index d54fa8aeaea9..ff8c68de4a92 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -1361,9 +1361,11 @@ int cifs_rename(struct inode *source_dir, struct dentry *source_dentry, CIFS_MOUNT_MAP_SPECIAL_CHR); if (tmprc == 0 && (info_buf_source->UniqueId == - info_buf_target->UniqueId)) + info_buf_target->UniqueId)) { /* same file, POSIX says that this is a noop */ + rc = 0; goto cifs_rename_exit; + } } /* else ... BB we could add the same check for Windows by checking the UniqueId via FILE_INTERNAL_INFO */ diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c index 88786ba02d27..9ee3f689c2b0 100644 --- a/fs/cifs/misc.c +++ b/fs/cifs/misc.c @@ -75,12 +75,12 @@ sesInfoAlloc(void) ret_buf = kzalloc(sizeof(struct cifsSesInfo), GFP_KERNEL); if (ret_buf) { - write_lock(&GlobalSMBSeslock); atomic_inc(&sesInfoAllocCount); ret_buf->status = CifsNew; - list_add(&ret_buf->cifsSessionList, &GlobalSMBSessionList); + ++ret_buf->ses_count; + INIT_LIST_HEAD(&ret_buf->smb_ses_list); + INIT_LIST_HEAD(&ret_buf->tcon_list); init_MUTEX(&ret_buf->sesSem); - write_unlock(&GlobalSMBSeslock); } return ret_buf; } @@ -93,10 +93,7 @@ sesInfoFree(struct cifsSesInfo *buf_to_free) return; } - write_lock(&GlobalSMBSeslock); atomic_dec(&sesInfoAllocCount); - list_del(&buf_to_free->cifsSessionList); - write_unlock(&GlobalSMBSeslock); kfree(buf_to_free->serverOS); kfree(buf_to_free->serverDomain); kfree(buf_to_free->serverNOS); @@ -111,17 +108,14 @@ tconInfoAlloc(void) struct cifsTconInfo *ret_buf; ret_buf = kzalloc(sizeof(struct cifsTconInfo), GFP_KERNEL); if (ret_buf) { - write_lock(&GlobalSMBSeslock); atomic_inc(&tconInfoAllocCount); - list_add(&ret_buf->cifsConnectionList, - &GlobalTreeConnectionList); ret_buf->tidStatus = CifsNew; + ++ret_buf->tc_count; INIT_LIST_HEAD(&ret_buf->openFileList); - init_MUTEX(&ret_buf->tconSem); + INIT_LIST_HEAD(&ret_buf->tcon_list); #ifdef CONFIG_CIFS_STATS spin_lock_init(&ret_buf->stat_lock); #endif - write_unlock(&GlobalSMBSeslock); } return ret_buf; } @@ -133,10 +127,7 @@ tconInfoFree(struct cifsTconInfo *buf_to_free) cFYI(1, ("Null buffer passed to tconInfoFree")); return; } - write_lock(&GlobalSMBSeslock); atomic_dec(&tconInfoAllocCount); - list_del(&buf_to_free->cifsConnectionList); - write_unlock(&GlobalSMBSeslock); kfree(buf_to_free->nativeFileSystem); kfree(buf_to_free); } @@ -350,9 +341,9 @@ header_assemble(struct smb_hdr *buffer, char smb_command /* command */ , if (current->fsuid != treeCon->ses->linux_uid) { cFYI(1, ("Multiuser mode and UID " "did not match tcon uid")); - read_lock(&GlobalSMBSeslock); - list_for_each(temp_item, &GlobalSMBSessionList) { - ses = list_entry(temp_item, struct cifsSesInfo, cifsSessionList); + read_lock(&cifs_tcp_ses_lock); + list_for_each(temp_item, &treeCon->ses->server->smb_ses_list) { + ses = list_entry(temp_item, struct cifsSesInfo, smb_ses_list); if (ses->linux_uid == current->fsuid) { if (ses->server == treeCon->ses->server) { cFYI(1, ("found matching uid substitute right smb_uid")); @@ -364,7 +355,7 @@ header_assemble(struct smb_hdr *buffer, char smb_command /* command */ , } } } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); } } } @@ -497,9 +488,10 @@ bool is_valid_oplock_break(struct smb_hdr *buf, struct TCP_Server_Info *srv) { struct smb_com_lock_req *pSMB = (struct smb_com_lock_req *)buf; - struct list_head *tmp; - struct list_head *tmp1; + struct list_head *tmp, *tmp1, *tmp2; + struct cifsSesInfo *ses; struct cifsTconInfo *tcon; + struct cifsInodeInfo *pCifsInode; struct cifsFileInfo *netfile; cFYI(1, ("Checking for oplock break or dnotify response")); @@ -554,42 +546,45 @@ is_valid_oplock_break(struct smb_hdr *buf, struct TCP_Server_Info *srv) return false; /* look up tcon based on tid & uid */ - read_lock(&GlobalSMBSeslock); - list_for_each(tmp, &GlobalTreeConnectionList) { - tcon = list_entry(tmp, struct cifsTconInfo, cifsConnectionList); - if ((tcon->tid == buf->Tid) && (srv == tcon->ses->server)) { + read_lock(&cifs_tcp_ses_lock); + list_for_each(tmp, &srv->smb_ses_list) { + ses = list_entry(tmp, struct cifsSesInfo, smb_ses_list); + list_for_each(tmp1, &ses->tcon_list) { + tcon = list_entry(tmp1, struct cifsTconInfo, tcon_list); + if (tcon->tid != buf->Tid) + continue; + cifs_stats_inc(&tcon->num_oplock_brks); - list_for_each(tmp1, &tcon->openFileList) { - netfile = list_entry(tmp1, struct cifsFileInfo, + write_lock(&GlobalSMBSeslock); + list_for_each(tmp2, &tcon->openFileList) { + netfile = list_entry(tmp2, struct cifsFileInfo, tlist); - if (pSMB->Fid == netfile->netfid) { - struct cifsInodeInfo *pCifsInode; - read_unlock(&GlobalSMBSeslock); - cFYI(1, - ("file id match, oplock break")); - pCifsInode = - CIFS_I(netfile->pInode); - pCifsInode->clientCanCacheAll = false; - if (pSMB->OplockLevel == 0) - pCifsInode->clientCanCacheRead - = false; - pCifsInode->oplockPending = true; - AllocOplockQEntry(netfile->pInode, - netfile->netfid, - tcon); - cFYI(1, - ("about to wake up oplock thread")); - if (oplockThread) - wake_up_process(oplockThread); - return true; - } + if (pSMB->Fid != netfile->netfid) + continue; + + write_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); + cFYI(1, ("file id match, oplock break")); + pCifsInode = CIFS_I(netfile->pInode); + pCifsInode->clientCanCacheAll = false; + if (pSMB->OplockLevel == 0) + pCifsInode->clientCanCacheRead = false; + pCifsInode->oplockPending = true; + AllocOplockQEntry(netfile->pInode, + netfile->netfid, tcon); + cFYI(1, ("about to wake up oplock thread")); + if (oplockThread) + wake_up_process(oplockThread); + + return true; } - read_unlock(&GlobalSMBSeslock); + write_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); cFYI(1, ("No matching file for oplock break")); return true; } } - read_unlock(&GlobalSMBSeslock); + read_unlock(&cifs_tcp_ses_lock); cFYI(1, ("Can not process oplock break for non-existent connection")); return true; } diff --git a/fs/cifs/readdir.c b/fs/cifs/readdir.c index 58d57299f2a0..9f51f9bf0292 100644 --- a/fs/cifs/readdir.c +++ b/fs/cifs/readdir.c @@ -741,11 +741,14 @@ static int find_cifs_entry(const int xid, struct cifsTconInfo *pTcon, (index_to_find < first_entry_in_buffer)) { /* close and restart search */ cFYI(1, ("search backing up - close and restart search")); + write_lock(&GlobalSMBSeslock); if (!cifsFile->srch_inf.endOfSearch && !cifsFile->invalidHandle) { cifsFile->invalidHandle = true; + write_unlock(&GlobalSMBSeslock); CIFSFindClose(xid, pTcon, cifsFile->netfid); - } + } else + write_unlock(&GlobalSMBSeslock); if (cifsFile->srch_inf.ntwrk_buf_start) { cFYI(1, ("freeing SMB ff cache buf on search rewind")); if (cifsFile->srch_inf.smallBuf) diff --git a/fs/cifs/transport.c b/fs/cifs/transport.c index bf0e6d8e382a..ff8243a8fe3e 100644 --- a/fs/cifs/transport.c +++ b/fs/cifs/transport.c @@ -161,7 +161,7 @@ void DeleteTconOplockQEntries(struct cifsTconInfo *tcon) int smb_send(struct socket *ssocket, struct smb_hdr *smb_buffer, - unsigned int smb_buf_length, struct sockaddr *sin) + unsigned int smb_buf_length, struct sockaddr *sin, bool noblocksnd) { int rc = 0; int i = 0; @@ -178,7 +178,10 @@ smb_send(struct socket *ssocket, struct smb_hdr *smb_buffer, smb_msg.msg_namelen = sizeof(struct sockaddr); smb_msg.msg_control = NULL; smb_msg.msg_controllen = 0; - smb_msg.msg_flags = MSG_DONTWAIT + MSG_NOSIGNAL; /* BB add more flags?*/ + if (noblocksnd) + smb_msg.msg_flags = MSG_DONTWAIT + MSG_NOSIGNAL; + else + smb_msg.msg_flags = MSG_NOSIGNAL; /* smb header is converted in header_assemble. bcc and rest of SMB word area, and byte area if necessary, is converted to littleendian in @@ -229,8 +232,8 @@ smb_send(struct socket *ssocket, struct smb_hdr *smb_buffer, } static int -smb_send2(struct socket *ssocket, struct kvec *iov, int n_vec, - struct sockaddr *sin) +smb_send2(struct TCP_Server_Info *server, struct kvec *iov, int n_vec, + struct sockaddr *sin, bool noblocksnd) { int rc = 0; int i = 0; @@ -240,6 +243,7 @@ smb_send2(struct socket *ssocket, struct kvec *iov, int n_vec, unsigned int total_len; int first_vec = 0; unsigned int smb_buf_length = smb_buffer->smb_buf_length; + struct socket *ssocket = server->ssocket; if (ssocket == NULL) return -ENOTSOCK; /* BB eventually add reconnect code here */ @@ -248,7 +252,10 @@ smb_send2(struct socket *ssocket, struct kvec *iov, int n_vec, smb_msg.msg_namelen = sizeof(struct sockaddr); smb_msg.msg_control = NULL; smb_msg.msg_controllen = 0; - smb_msg.msg_flags = MSG_DONTWAIT + MSG_NOSIGNAL; /* BB add more flags?*/ + if (noblocksnd) + smb_msg.msg_flags = MSG_DONTWAIT + MSG_NOSIGNAL; + else + smb_msg.msg_flags = MSG_NOSIGNAL; /* smb header is converted in header_assemble. bcc and rest of SMB word area, and byte area if necessary, is converted to littleendian in @@ -283,8 +290,11 @@ smb_send2(struct socket *ssocket, struct kvec *iov, int n_vec, if (rc < 0) break; - if (rc >= total_len) { - WARN_ON(rc > total_len); + if (rc == total_len) { + total_len = 0; + break; + } else if (rc > total_len) { + cERROR(1, ("sent %d requested %d", rc, total_len)); break; } if (rc == 0) { @@ -312,6 +322,16 @@ smb_send2(struct socket *ssocket, struct kvec *iov, int n_vec, i = 0; /* in case we get ENOSPC on the next send */ } + if ((total_len > 0) && (total_len != smb_buf_length + 4)) { + cFYI(1, ("partial send (%d remaining), terminating session", + total_len)); + /* If we have only sent part of an SMB then the next SMB + could be taken as the remainder of this one. We need + to kill the socket so the server throws away the partial + SMB */ + server->tcpStatus = CifsNeedReconnect; + } + if (rc < 0) { cERROR(1, ("Error %d sending data on socket to server", rc)); } else @@ -518,8 +538,9 @@ SendReceive2(const unsigned int xid, struct cifsSesInfo *ses, #ifdef CONFIG_CIFS_STATS2 atomic_inc(&ses->server->inSend); #endif - rc = smb_send2(ses->server->ssocket, iov, n_vec, - (struct sockaddr *) &(ses->server->addr.sockAddr)); + rc = smb_send2(ses->server, iov, n_vec, + (struct sockaddr *) &(ses->server->addr.sockAddr), + ses->server->noblocksnd); #ifdef CONFIG_CIFS_STATS2 atomic_dec(&ses->server->inSend); midQ->when_sent = jiffies; @@ -711,7 +732,8 @@ SendReceive(const unsigned int xid, struct cifsSesInfo *ses, atomic_inc(&ses->server->inSend); #endif rc = smb_send(ses->server->ssocket, in_buf, in_buf->smb_buf_length, - (struct sockaddr *) &(ses->server->addr.sockAddr)); + (struct sockaddr *) &(ses->server->addr.sockAddr), + ses->server->noblocksnd); #ifdef CONFIG_CIFS_STATS2 atomic_dec(&ses->server->inSend); midQ->when_sent = jiffies; @@ -851,7 +873,8 @@ send_nt_cancel(struct cifsTconInfo *tcon, struct smb_hdr *in_buf, return rc; } rc = smb_send(ses->server->ssocket, in_buf, in_buf->smb_buf_length, - (struct sockaddr *) &(ses->server->addr.sockAddr)); + (struct sockaddr *) &(ses->server->addr.sockAddr), + ses->server->noblocksnd); up(&ses->server->tcpSem); return rc; } @@ -941,7 +964,8 @@ SendReceiveBlockingLock(const unsigned int xid, struct cifsTconInfo *tcon, atomic_inc(&ses->server->inSend); #endif rc = smb_send(ses->server->ssocket, in_buf, in_buf->smb_buf_length, - (struct sockaddr *) &(ses->server->addr.sockAddr)); + (struct sockaddr *) &(ses->server->addr.sockAddr), + ses->server->noblocksnd); #ifdef CONFIG_CIFS_STATS2 atomic_dec(&ses->server->inSend); midQ->when_sent = jiffies; diff --git a/fs/coda/psdev.c b/fs/coda/psdev.c index cfd29da714d1..0376ac66c44a 100644 --- a/fs/coda/psdev.c +++ b/fs/coda/psdev.c @@ -2,7 +2,7 @@ * An implementation of a loadable kernel mode driver providing * multiple kernel/user space bidirectional communications links. * - * Author: Alan Cox + * Author: Alan Cox * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c index d910501de6d2..8d86b7960f0d 100644 --- a/fs/dlm/lockspace.c +++ b/fs/dlm/lockspace.c @@ -812,7 +812,7 @@ int dlm_release_lockspace(void *lockspace, int force) error = release_lockspace(ls, force); if (!error) ls_count--; - else if (!ls_count) + if (!ls_count) threads_stop(); mutex_unlock(&ls_lock); diff --git a/fs/ecryptfs/crypto.c b/fs/ecryptfs/crypto.c index 06db79d05c12..6046239465a1 100644 --- a/fs/ecryptfs/crypto.c +++ b/fs/ecryptfs/crypto.c @@ -1251,6 +1251,7 @@ struct kmem_cache *ecryptfs_header_cache_2; /** * ecryptfs_write_headers_virt * @page_virt: The virtual address to write the headers to + * @max: The size of memory allocated at page_virt * @size: Set to the number of bytes written by this function * @crypt_stat: The cryptographic context * @ecryptfs_dentry: The eCryptfs dentry @@ -1278,7 +1279,8 @@ struct kmem_cache *ecryptfs_header_cache_2; * * Returns zero on success */ -static int ecryptfs_write_headers_virt(char *page_virt, size_t *size, +static int ecryptfs_write_headers_virt(char *page_virt, size_t max, + size_t *size, struct ecryptfs_crypt_stat *crypt_stat, struct dentry *ecryptfs_dentry) { @@ -1296,7 +1298,7 @@ static int ecryptfs_write_headers_virt(char *page_virt, size_t *size, offset += written; rc = ecryptfs_generate_key_packet_set((page_virt + offset), crypt_stat, ecryptfs_dentry, &written, - PAGE_CACHE_SIZE - offset); + max - offset); if (rc) ecryptfs_printk(KERN_WARNING, "Error generating key packet " "set; rc = [%d]\n", rc); @@ -1368,14 +1370,14 @@ int ecryptfs_write_metadata(struct dentry *ecryptfs_dentry) goto out; } /* Released in this function */ - virt = kzalloc(crypt_stat->num_header_bytes_at_front, GFP_KERNEL); + virt = (char *)get_zeroed_page(GFP_KERNEL); if (!virt) { printk(KERN_ERR "%s: Out of memory\n", __func__); rc = -ENOMEM; goto out; } - rc = ecryptfs_write_headers_virt(virt, &size, crypt_stat, - ecryptfs_dentry); + rc = ecryptfs_write_headers_virt(virt, PAGE_CACHE_SIZE, &size, + crypt_stat, ecryptfs_dentry); if (unlikely(rc)) { printk(KERN_ERR "%s: Error whilst writing headers; rc = [%d]\n", __func__, rc); @@ -1393,8 +1395,7 @@ int ecryptfs_write_metadata(struct dentry *ecryptfs_dentry) goto out_free; } out_free: - memset(virt, 0, crypt_stat->num_header_bytes_at_front); - kfree(virt); + free_page((unsigned long)virt); out: return rc; } diff --git a/fs/ecryptfs/keystore.c b/fs/ecryptfs/keystore.c index e22bc3961345..0d713b691941 100644 --- a/fs/ecryptfs/keystore.c +++ b/fs/ecryptfs/keystore.c @@ -1037,17 +1037,14 @@ static int decrypt_passphrase_encrypted_session_key(struct ecryptfs_auth_tok *auth_tok, struct ecryptfs_crypt_stat *crypt_stat) { - struct scatterlist dst_sg; - struct scatterlist src_sg; + struct scatterlist dst_sg[2]; + struct scatterlist src_sg[2]; struct mutex *tfm_mutex; struct blkcipher_desc desc = { .flags = CRYPTO_TFM_REQ_MAY_SLEEP }; int rc = 0; - sg_init_table(&dst_sg, 1); - sg_init_table(&src_sg, 1); - if (unlikely(ecryptfs_verbosity > 0)) { ecryptfs_printk( KERN_DEBUG, "Session key encryption key (size [%d]):\n", @@ -1066,8 +1063,8 @@ decrypt_passphrase_encrypted_session_key(struct ecryptfs_auth_tok *auth_tok, } rc = virt_to_scatterlist(auth_tok->session_key.encrypted_key, auth_tok->session_key.encrypted_key_size, - &src_sg, 1); - if (rc != 1) { + src_sg, 2); + if (rc < 1 || rc > 2) { printk(KERN_ERR "Internal error whilst attempting to convert " "auth_tok->session_key.encrypted_key to scatterlist; " "expected rc = 1; got rc = [%d]. " @@ -1079,8 +1076,8 @@ decrypt_passphrase_encrypted_session_key(struct ecryptfs_auth_tok *auth_tok, auth_tok->session_key.encrypted_key_size; rc = virt_to_scatterlist(auth_tok->session_key.decrypted_key, auth_tok->session_key.decrypted_key_size, - &dst_sg, 1); - if (rc != 1) { + dst_sg, 2); + if (rc < 1 || rc > 2) { printk(KERN_ERR "Internal error whilst attempting to convert " "auth_tok->session_key.decrypted_key to scatterlist; " "expected rc = 1; got rc = [%d]\n", rc); @@ -1096,7 +1093,7 @@ decrypt_passphrase_encrypted_session_key(struct ecryptfs_auth_tok *auth_tok, rc = -EINVAL; goto out; } - rc = crypto_blkcipher_decrypt(&desc, &dst_sg, &src_sg, + rc = crypto_blkcipher_decrypt(&desc, dst_sg, src_sg, auth_tok->session_key.encrypted_key_size); mutex_unlock(tfm_mutex); if (unlikely(rc)) { @@ -1539,8 +1536,8 @@ write_tag_3_packet(char *dest, size_t *remaining_bytes, size_t i; size_t encrypted_session_key_valid = 0; char session_key_encryption_key[ECRYPTFS_MAX_KEY_BYTES]; - struct scatterlist dst_sg; - struct scatterlist src_sg; + struct scatterlist dst_sg[2]; + struct scatterlist src_sg[2]; struct mutex *tfm_mutex = NULL; u8 cipher_code; size_t packet_size_length; @@ -1619,8 +1616,8 @@ write_tag_3_packet(char *dest, size_t *remaining_bytes, ecryptfs_dump_hex(session_key_encryption_key, 16); } rc = virt_to_scatterlist(crypt_stat->key, key_rec->enc_key_size, - &src_sg, 1); - if (rc != 1) { + src_sg, 2); + if (rc < 1 || rc > 2) { ecryptfs_printk(KERN_ERR, "Error generating scatterlist " "for crypt_stat session key; expected rc = 1; " "got rc = [%d]. key_rec->enc_key_size = [%d]\n", @@ -1629,8 +1626,8 @@ write_tag_3_packet(char *dest, size_t *remaining_bytes, goto out; } rc = virt_to_scatterlist(key_rec->enc_key, key_rec->enc_key_size, - &dst_sg, 1); - if (rc != 1) { + dst_sg, 2); + if (rc < 1 || rc > 2) { ecryptfs_printk(KERN_ERR, "Error generating scatterlist " "for crypt_stat encrypted session key; " "expected rc = 1; got rc = [%d]. " @@ -1651,7 +1648,7 @@ write_tag_3_packet(char *dest, size_t *remaining_bytes, rc = 0; ecryptfs_printk(KERN_DEBUG, "Encrypting [%d] bytes of the key\n", crypt_stat->key_size); - rc = crypto_blkcipher_encrypt(&desc, &dst_sg, &src_sg, + rc = crypto_blkcipher_encrypt(&desc, dst_sg, src_sg, (*key_rec).enc_key_size); mutex_unlock(tfm_mutex); if (rc) { diff --git a/fs/eventpoll.c b/fs/eventpoll.c index aec5c13f6341..96355d505347 100644 --- a/fs/eventpoll.c +++ b/fs/eventpoll.c @@ -102,6 +102,8 @@ #define EP_UNACTIVE_PTR ((void *) -1L) +#define EP_ITEM_COST (sizeof(struct epitem) + sizeof(struct eppoll_entry)) + struct epoll_filefd { struct file *file; int fd; @@ -200,6 +202,9 @@ struct eventpoll { * holding ->lock. */ struct epitem *ovflist; + + /* The user that created the eventpoll descriptor */ + struct user_struct *user; }; /* Wait structure used by the poll hooks */ @@ -226,10 +231,18 @@ struct ep_pqueue { struct epitem *epi; }; +/* + * Configuration options available inside /proc/sys/fs/epoll/ + */ +/* Maximum number of epoll devices, per user */ +static int max_user_instances __read_mostly; +/* Maximum number of epoll watched descriptors, per user */ +static int max_user_watches __read_mostly; + /* * This mutex is used to serialize ep_free() and eventpoll_release_file(). */ -static struct mutex epmutex; +static DEFINE_MUTEX(epmutex); /* Safe wake up implementation */ static struct poll_safewake psw; @@ -240,6 +253,33 @@ static struct kmem_cache *epi_cache __read_mostly; /* Slab cache used to allocate "struct eppoll_entry" */ static struct kmem_cache *pwq_cache __read_mostly; +#ifdef CONFIG_SYSCTL + +#include + +static int zero; + +ctl_table epoll_table[] = { + { + .procname = "max_user_instances", + .data = &max_user_instances, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_dointvec_minmax, + .extra1 = &zero, + }, + { + .procname = "max_user_watches", + .data = &max_user_watches, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = &proc_dointvec_minmax, + .extra1 = &zero, + }, + { .ctl_name = 0 } +}; +#endif /* CONFIG_SYSCTL */ + /* Setup the structure that is used as key for the RB tree */ static inline void ep_set_ffd(struct epoll_filefd *ffd, @@ -402,6 +442,8 @@ static int ep_remove(struct eventpoll *ep, struct epitem *epi) /* At this point it is safe to free the eventpoll item */ kmem_cache_free(epi_cache, epi); + atomic_dec(&ep->user->epoll_watches); + DNPRINTK(3, (KERN_INFO "[%p] eventpoll: ep_remove(%p, %p)\n", current, ep, file)); @@ -449,6 +491,8 @@ static void ep_free(struct eventpoll *ep) mutex_unlock(&epmutex); mutex_destroy(&ep->mtx); + atomic_dec(&ep->user->epoll_devs); + free_uid(ep->user); kfree(ep); } @@ -532,10 +576,19 @@ void eventpoll_release_file(struct file *file) static int ep_alloc(struct eventpoll **pep) { - struct eventpoll *ep = kzalloc(sizeof(*ep), GFP_KERNEL); + int error; + struct user_struct *user; + struct eventpoll *ep; - if (!ep) - return -ENOMEM; + user = get_current_user(); + error = -EMFILE; + if (unlikely(atomic_read(&user->epoll_devs) >= + max_user_instances)) + goto free_uid; + error = -ENOMEM; + ep = kzalloc(sizeof(*ep), GFP_KERNEL); + if (unlikely(!ep)) + goto free_uid; spin_lock_init(&ep->lock); mutex_init(&ep->mtx); @@ -544,12 +597,17 @@ static int ep_alloc(struct eventpoll **pep) INIT_LIST_HEAD(&ep->rdllist); ep->rbr = RB_ROOT; ep->ovflist = EP_UNACTIVE_PTR; + ep->user = user; *pep = ep; DNPRINTK(3, (KERN_INFO "[%p] eventpoll: ep_alloc() ep=%p\n", current, ep)); return 0; + +free_uid: + free_uid(user); + return error; } /* @@ -703,9 +761,11 @@ static int ep_insert(struct eventpoll *ep, struct epoll_event *event, struct epitem *epi; struct ep_pqueue epq; - error = -ENOMEM; + if (unlikely(atomic_read(&ep->user->epoll_watches) >= + max_user_watches)) + return -ENOSPC; if (!(epi = kmem_cache_alloc(epi_cache, GFP_KERNEL))) - goto error_return; + return -ENOMEM; /* Item initialization follow here ... */ INIT_LIST_HEAD(&epi->rdllink); @@ -735,6 +795,7 @@ static int ep_insert(struct eventpoll *ep, struct epoll_event *event, * install process. Namely an allocation for a wait queue failed due * high memory pressure. */ + error = -ENOMEM; if (epi->nwait < 0) goto error_unregister; @@ -765,6 +826,8 @@ static int ep_insert(struct eventpoll *ep, struct epoll_event *event, spin_unlock_irqrestore(&ep->lock, flags); + atomic_inc(&ep->user->epoll_watches); + /* We have to call this outside the lock */ if (pwake) ep_poll_safewake(&psw, &ep->poll_wait); @@ -789,7 +852,7 @@ error_unregister: spin_unlock_irqrestore(&ep->lock, flags); kmem_cache_free(epi_cache, epi); -error_return: + return error; } @@ -1078,6 +1141,7 @@ asmlinkage long sys_epoll_create1(int flags) flags & O_CLOEXEC); if (fd < 0) ep_free(ep); + atomic_inc(&ep->user->epoll_devs); error_return: DNPRINTK(3, (KERN_INFO "[%p] eventpoll: sys_epoll_create(%d) = %d\n", @@ -1299,7 +1363,12 @@ asmlinkage long sys_epoll_pwait(int epfd, struct epoll_event __user *events, static int __init eventpoll_init(void) { - mutex_init(&epmutex); + struct sysinfo si; + + si_meminfo(&si); + max_user_instances = 128; + max_user_watches = (((si.totalram - si.totalhigh) / 32) << PAGE_SHIFT) / + EP_ITEM_COST; /* Initialize the structure used to perform safe poll wait head wake ups */ ep_poll_safewake_init(&psw); diff --git a/fs/exec.c b/fs/exec.c index 4e834f16d9da..ec5df9a38313 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -1159,6 +1159,7 @@ EXPORT_SYMBOL(remove_arg_zero); */ int search_binary_handler(struct linux_binprm *bprm,struct pt_regs *regs) { + unsigned int depth = bprm->recursion_depth; int try,retval; struct linux_binfmt *fmt; #ifdef __alpha__ @@ -1219,8 +1220,15 @@ int search_binary_handler(struct linux_binprm *bprm,struct pt_regs *regs) continue; read_unlock(&binfmt_lock); retval = fn(bprm, regs); + /* + * Restore the depth counter to its starting value + * in this call, so we don't have to rely on every + * load_binary function to restore it on return. + */ + bprm->recursion_depth = depth; if (retval >= 0) { - tracehook_report_exec(fmt, bprm, regs); + if (depth == 0) + tracehook_report_exec(fmt, bprm, regs); put_binfmt(fmt); allow_write_access(bprm->file); if (bprm->file) diff --git a/fs/exportfs/expfs.c b/fs/exportfs/expfs.c index 80246bad1b7f..890e01828817 100644 --- a/fs/exportfs/expfs.c +++ b/fs/exportfs/expfs.c @@ -367,6 +367,8 @@ struct dentry *exportfs_decode_fh(struct vfsmount *mnt, struct fid *fid, * Try to get any dentry for the given file handle from the filesystem. */ result = nop->fh_to_dentry(mnt->mnt_sb, fid, fh_len, fileid_type); + if (!result) + result = ERR_PTR(-ESTALE); if (IS_ERR(result)) return result; @@ -420,6 +422,8 @@ struct dentry *exportfs_decode_fh(struct vfsmount *mnt, struct fid *fid, target_dir = nop->fh_to_parent(mnt->mnt_sb, fid, fh_len, fileid_type); + if (!target_dir) + goto err_result; err = PTR_ERR(target_dir); if (IS_ERR(target_dir)) goto err_result; diff --git a/fs/ext3/super.c b/fs/ext3/super.c index 18eaa78ecb4e..f6c94f232ec1 100644 --- a/fs/ext3/super.c +++ b/fs/ext3/super.c @@ -281,7 +281,8 @@ void ext3_abort (struct super_block * sb, const char * function, EXT3_SB(sb)->s_mount_state |= EXT3_ERROR_FS; sb->s_flags |= MS_RDONLY; EXT3_SB(sb)->s_mount_opt |= EXT3_MOUNT_ABORT; - journal_abort(EXT3_SB(sb)->s_journal, -EIO); + if (EXT3_SB(sb)->s_journal) + journal_abort(EXT3_SB(sb)->s_journal, -EIO); } void ext3_warning (struct super_block * sb, const char * function, @@ -390,11 +391,14 @@ static void ext3_put_super (struct super_block * sb) { struct ext3_sb_info *sbi = EXT3_SB(sb); struct ext3_super_block *es = sbi->s_es; - int i; + int i, err; ext3_xattr_put_super(sb); - if (journal_destroy(sbi->s_journal) < 0) + err = journal_destroy(sbi->s_journal); + sbi->s_journal = NULL; + if (err < 0) ext3_abort(sb, __func__, "Couldn't clean up the journal"); + if (!(sb->s_flags & MS_RDONLY)) { EXT3_CLEAR_INCOMPAT_FEATURE(sb, EXT3_FEATURE_INCOMPAT_RECOVER); es->s_state = cpu_to_le16(sbi->s_mount_state); @@ -2371,12 +2375,9 @@ int ext3_force_commit(struct super_block *sb) /* * Ext3 always journals updates to the superblock itself, so we don't * have to propagate any other updates to the superblock on disk at this - * point. Just start an async writeback to get the buffers on their way - * to the disk. - * - * This implicitly triggers the writebehind on sync(). + * point. (We can probably nuke this function altogether, and remove + * any mention to sb->s_dirt in all of fs/ext3; eventual cleanup...) */ - static void ext3_write_super (struct super_block * sb) { if (mutex_trylock(&sb->s_lock) != 0) @@ -2386,13 +2387,12 @@ static void ext3_write_super (struct super_block * sb) static int ext3_sync_fs(struct super_block *sb, int wait) { - tid_t target; - sb->s_dirt = 0; - if (journal_start_commit(EXT3_SB(sb)->s_journal, &target)) { - if (wait) - log_wait_commit(EXT3_SB(sb)->s_journal, target); - } + if (wait) + ext3_force_commit(sb); + else + journal_start_commit(EXT3_SB(sb)->s_journal, NULL); + return 0; } diff --git a/fs/ext4/balloc.c b/fs/ext4/balloc.c index b9821be709bd..db35cfdb3c8b 100644 --- a/fs/ext4/balloc.c +++ b/fs/ext4/balloc.c @@ -589,26 +589,28 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode, return; } -int ext4_claim_free_blocks(struct ext4_sb_info *sbi, - s64 nblocks) +/** + * ext4_has_free_blocks() + * @sbi: in-core super block structure. + * @nblocks: number of needed blocks + * + * Check if filesystem has nblocks free & available for allocation. + * On success return 1, return 0 on failure. + */ +int ext4_has_free_blocks(struct ext4_sb_info *sbi, s64 nblocks) { - s64 free_blocks, dirty_blocks; - s64 root_blocks = 0; + s64 free_blocks, dirty_blocks, root_blocks; struct percpu_counter *fbc = &sbi->s_freeblocks_counter; struct percpu_counter *dbc = &sbi->s_dirtyblocks_counter; free_blocks = percpu_counter_read_positive(fbc); dirty_blocks = percpu_counter_read_positive(dbc); - - if (!capable(CAP_SYS_RESOURCE) && - sbi->s_resuid != current->fsuid && - (sbi->s_resgid == 0 || !in_group_p(sbi->s_resgid))) - root_blocks = ext4_r_blocks_count(sbi->s_es); + root_blocks = ext4_r_blocks_count(sbi->s_es); if (free_blocks - (nblocks + root_blocks + dirty_blocks) < EXT4_FREEBLOCKS_WATERMARK) { - free_blocks = percpu_counter_sum(fbc); - dirty_blocks = percpu_counter_sum(dbc); + free_blocks = percpu_counter_sum_positive(fbc); + dirty_blocks = percpu_counter_sum_positive(dbc); if (dirty_blocks < 0) { printk(KERN_CRIT "Dirty block accounting " "went wrong %lld\n", @@ -616,57 +618,32 @@ int ext4_claim_free_blocks(struct ext4_sb_info *sbi, } } /* Check whether we have space after - * accounting for current dirty blocks + * accounting for current dirty blocks & root reserved blocks. */ - if (free_blocks < ((root_blocks + nblocks) + dirty_blocks)) - /* we don't have free space */ - return -ENOSPC; + if (free_blocks >= ((root_blocks + nblocks) + dirty_blocks)) + return 1; + + /* Hm, nope. Are (enough) root reserved blocks available? */ + if (sbi->s_resuid == current->fsuid || + ((sbi->s_resgid != 0) && in_group_p(sbi->s_resgid)) || + capable(CAP_SYS_RESOURCE)) { + if (free_blocks >= (nblocks + dirty_blocks)) + return 1; + } - /* Add the blocks to nblocks */ - percpu_counter_add(dbc, nblocks); return 0; } -/** - * ext4_has_free_blocks() - * @sbi: in-core super block structure. - * @nblocks: number of neeed blocks - * - * Check if filesystem has free blocks available for allocation. - * Return the number of blocks avaible for allocation for this request - * On success, return nblocks - */ -ext4_fsblk_t ext4_has_free_blocks(struct ext4_sb_info *sbi, +int ext4_claim_free_blocks(struct ext4_sb_info *sbi, s64 nblocks) { - s64 free_blocks, dirty_blocks; - s64 root_blocks = 0; - struct percpu_counter *fbc = &sbi->s_freeblocks_counter; - struct percpu_counter *dbc = &sbi->s_dirtyblocks_counter; - - free_blocks = percpu_counter_read_positive(fbc); - dirty_blocks = percpu_counter_read_positive(dbc); - - if (!capable(CAP_SYS_RESOURCE) && - sbi->s_resuid != current->fsuid && - (sbi->s_resgid == 0 || !in_group_p(sbi->s_resgid))) - root_blocks = ext4_r_blocks_count(sbi->s_es); - - if (free_blocks - (nblocks + root_blocks + dirty_blocks) < - EXT4_FREEBLOCKS_WATERMARK) { - free_blocks = percpu_counter_sum(fbc); - dirty_blocks = percpu_counter_sum(dbc); - } - if (free_blocks <= (root_blocks + dirty_blocks)) - /* we don't have free space */ + if (ext4_has_free_blocks(sbi, nblocks)) { + percpu_counter_add(&sbi->s_dirtyblocks_counter, nblocks); return 0; - - if (free_blocks - (root_blocks + dirty_blocks) < nblocks) - return free_blocks - (root_blocks + dirty_blocks); - return nblocks; + } else + return -ENOSPC; } - /** * ext4_should_retry_alloc() * @sb: super block diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h index 4880cc3e6727..b0537c827024 100644 --- a/fs/ext4/ext4.h +++ b/fs/ext4/ext4.h @@ -1003,8 +1003,7 @@ extern ext4_fsblk_t ext4_new_blocks(handle_t *handle, struct inode *inode, ext4_lblk_t iblock, ext4_fsblk_t goal, unsigned long *count, int *errp); extern int ext4_claim_free_blocks(struct ext4_sb_info *sbi, s64 nblocks); -extern ext4_fsblk_t ext4_has_free_blocks(struct ext4_sb_info *sbi, - s64 nblocks); +extern int ext4_has_free_blocks(struct ext4_sb_info *sbi, s64 nblocks); extern void ext4_free_blocks(handle_t *handle, struct inode *inode, ext4_fsblk_t block, unsigned long count, int metadata); extern void ext4_free_blocks_sb(handle_t *handle, struct super_block *sb, diff --git a/fs/ext4/ialloc.c b/fs/ext4/ialloc.c index fe34d74cfb19..2a117e286e54 100644 --- a/fs/ext4/ialloc.c +++ b/fs/ext4/ialloc.c @@ -718,6 +718,8 @@ got: gdp->bg_flags &= cpu_to_le16(~EXT4_BG_BLOCK_UNINIT); free = ext4_free_blocks_after_init(sb, group, gdp); gdp->bg_free_blocks_count = cpu_to_le16(free); + gdp->bg_checksum = ext4_group_desc_csum(sbi, group, + gdp); } spin_unlock(sb_bgl_lock(sbi, group)); diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 8dbf6953845b..be21a5ae33cb 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -2329,6 +2329,8 @@ static int ext4_da_writepage(struct page *page, unlock_page(page); return 0; } + /* now mark the buffer_heads as dirty and uptodate */ + block_commit_write(page, 0, PAGE_CACHE_SIZE); } if (test_opt(inode->i_sb, NOBH) && ext4_should_writeback_data(inode)) @@ -4580,9 +4582,10 @@ static int ext4_indirect_trans_blocks(struct inode *inode, int nrblocks, static int ext4_index_trans_blocks(struct inode *inode, int nrblocks, int chunk) { if (!(EXT4_I(inode)->i_flags & EXT4_EXTENTS_FL)) - return ext4_indirect_trans_blocks(inode, nrblocks, 0); - return ext4_ext_index_trans_blocks(inode, nrblocks, 0); + return ext4_indirect_trans_blocks(inode, nrblocks, chunk); + return ext4_ext_index_trans_blocks(inode, nrblocks, chunk); } + /* * Account for index blocks, block groups bitmaps and block group * descriptor blocks if modify datablocks and index blocks diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index dfe17a134052..444ad998f72e 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -4441,6 +4441,7 @@ ext4_mb_free_metadata(handle_t *handle, struct ext4_buddy *e4b, else if (block >= (entry->start_blk + entry->count)) n = &(*n)->rb_right; else { + ext4_unlock_group(sb, group); ext4_error(sb, __func__, "Double free of blocks %d (%d %d)\n", block, entry->start_blk, entry->count); diff --git a/fs/ext4/super.c b/fs/ext4/super.c index bdddea14e782..e4a241c65dbe 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -333,7 +333,8 @@ void ext4_abort(struct super_block *sb, const char *function, EXT4_SB(sb)->s_mount_state |= EXT4_ERROR_FS; sb->s_flags |= MS_RDONLY; EXT4_SB(sb)->s_mount_opt |= EXT4_MOUNT_ABORT; - jbd2_journal_abort(EXT4_SB(sb)->s_journal, -EIO); + if (EXT4_SB(sb)->s_journal) + jbd2_journal_abort(EXT4_SB(sb)->s_journal, -EIO); } void ext4_warning(struct super_block *sb, const char *function, @@ -442,14 +443,16 @@ static void ext4_put_super(struct super_block *sb) { struct ext4_sb_info *sbi = EXT4_SB(sb); struct ext4_super_block *es = sbi->s_es; - int i; + int i, err; ext4_mb_release(sb); ext4_ext_release(sb); ext4_xattr_put_super(sb); - if (jbd2_journal_destroy(sbi->s_journal) < 0) - ext4_abort(sb, __func__, "Couldn't clean up the journal"); + err = jbd2_journal_destroy(sbi->s_journal); sbi->s_journal = NULL; + if (err < 0) + ext4_abort(sb, __func__, "Couldn't clean up the journal"); + if (!(sb->s_flags & MS_RDONLY)) { EXT4_CLEAR_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_RECOVER); es->s_state = cpu_to_le16(sbi->s_mount_state); @@ -1455,9 +1458,8 @@ static int ext4_fill_flex_info(struct super_block *sb) /* We allocate both existing and potentially added groups */ flex_group_count = ((sbi->s_groups_count + groups_per_flex - 1) + - ((sbi->s_es->s_reserved_gdt_blocks +1 ) << - EXT4_DESC_PER_BLOCK_BITS(sb))) / - groups_per_flex; + ((le16_to_cpu(sbi->s_es->s_reserved_gdt_blocks) + 1) << + EXT4_DESC_PER_BLOCK_BITS(sb))) / groups_per_flex; sbi->s_flex_groups = kzalloc(flex_group_count * sizeof(struct flex_groups), GFP_KERNEL); if (sbi->s_flex_groups == NULL) { @@ -2882,12 +2884,9 @@ int ext4_force_commit(struct super_block *sb) /* * Ext4 always journals updates to the superblock itself, so we don't * have to propagate any other updates to the superblock on disk at this - * point. Just start an async writeback to get the buffers on their way - * to the disk. - * - * This implicitly triggers the writebehind on sync(). + * point. (We can probably nuke this function altogether, and remove + * any mention to sb->s_dirt in all of fs/ext4; eventual cleanup...) */ - static void ext4_write_super(struct super_block *sb) { if (mutex_trylock(&sb->s_lock) != 0) @@ -2897,15 +2896,15 @@ static void ext4_write_super(struct super_block *sb) static int ext4_sync_fs(struct super_block *sb, int wait) { - tid_t target; + int ret = 0; trace_mark(ext4_sync_fs, "dev %s wait %d", sb->s_id, wait); sb->s_dirt = 0; - if (jbd2_journal_start_commit(EXT4_SB(sb)->s_journal, &target)) { - if (wait) - jbd2_log_wait_commit(EXT4_SB(sb)->s_journal, target); - } - return 0; + if (wait) + ret = ext4_force_commit(sb); + else + jbd2_journal_start_commit(EXT4_SB(sb)->s_journal, NULL); + return ret; } /* diff --git a/fs/fat/Makefile b/fs/fat/Makefile index bfb5f06cf2c8..e06190322c1c 100644 --- a/fs/fat/Makefile +++ b/fs/fat/Makefile @@ -3,5 +3,9 @@ # obj-$(CONFIG_FAT_FS) += fat.o +obj-$(CONFIG_VFAT_FS) += vfat.o +obj-$(CONFIG_MSDOS_FS) += msdos.o -fat-objs := cache.o dir.o fatent.o file.o inode.o misc.o +fat-y := cache.o dir.o fatent.o file.o inode.o misc.o +vfat-y := namei_vfat.o +msdos-y := namei_msdos.o diff --git a/fs/fat/cache.c b/fs/fat/cache.c index 3222f51c41cf..b42602298087 100644 --- a/fs/fat/cache.c +++ b/fs/fat/cache.c @@ -9,8 +9,8 @@ */ #include -#include #include +#include "fat.h" /* this must be > 0. */ #define FAT_MAX_CACHE 8 @@ -293,10 +293,12 @@ static int fat_bmap_cluster(struct inode *inode, int cluster) } int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys, - unsigned long *mapped_blocks) + unsigned long *mapped_blocks, int create) { struct super_block *sb = inode->i_sb; struct msdos_sb_info *sbi = MSDOS_SB(sb); + const unsigned long blocksize = sb->s_blocksize; + const unsigned char blocksize_bits = sb->s_blocksize_bits; sector_t last_block; int cluster, offset; @@ -309,10 +311,21 @@ int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys, } return 0; } - last_block = (MSDOS_I(inode)->mmu_private + (sb->s_blocksize - 1)) - >> sb->s_blocksize_bits; - if (sector >= last_block) - return 0; + + last_block = (i_size_read(inode) + (blocksize - 1)) >> blocksize_bits; + if (sector >= last_block) { + if (!create) + return 0; + + /* + * ->mmu_private can access on only allocation path. + * (caller must hold ->i_mutex) + */ + last_block = (MSDOS_I(inode)->mmu_private + (blocksize - 1)) + >> blocksize_bits; + if (sector >= last_block) + return 0; + } cluster = sector >> (sbi->cluster_bits - sb->s_blocksize_bits); offset = sector & (sbi->sec_per_clus - 1); diff --git a/fs/fat/dir.c b/fs/fat/dir.c index bae1c3292522..67e058357098 100644 --- a/fs/fat/dir.c +++ b/fs/fat/dir.c @@ -16,11 +16,11 @@ #include #include #include -#include #include #include #include #include +#include "fat.h" static inline loff_t fat_make_i_pos(struct super_block *sb, struct buffer_head *bh, @@ -77,7 +77,7 @@ next: *bh = NULL; iblock = *pos >> sb->s_blocksize_bits; - err = fat_bmap(dir, iblock, &phys, &mapped_blocks); + err = fat_bmap(dir, iblock, &phys, &mapped_blocks, 0); if (err || !phys) return -1; /* beyond EOF or error */ @@ -86,7 +86,7 @@ next: *bh = sb_bread(sb, phys); if (*bh == NULL) { printk(KERN_ERR "FAT: Directory bread(block %llu) failed\n", - (unsigned long long)phys); + (llu)phys); /* skip this block */ *pos = (iblock + 1) << sb->s_blocksize_bits; goto next; @@ -373,9 +373,10 @@ parse_record: if (de->attr == ATTR_EXT) { int status = fat_parse_long(inode, &cpos, &bh, &de, &unicode, &nr_slots); - if (status < 0) - return status; - else if (status == PARSE_INVALID) + if (status < 0) { + err = status; + goto end_of_dir; + } else if (status == PARSE_INVALID) continue; else if (status == PARSE_NOT_LONGNAME) goto parse_record; @@ -832,6 +833,7 @@ static long fat_compat_dir_ioctl(struct file *filp, unsigned cmd, #endif /* CONFIG_COMPAT */ const struct file_operations fat_dir_operations = { + .llseek = generic_file_llseek, .read = generic_read_dir, .readdir = fat_readdir, .ioctl = fat_dir_ioctl, @@ -1089,6 +1091,7 @@ int fat_alloc_new_dir(struct inode *dir, struct timespec *ts) struct msdos_dir_entry *de; sector_t blknr; __le16 date, time; + u8 time_cs; int err, cluster; err = fat_alloc_clusters(dir, &cluster, 1); @@ -1102,7 +1105,7 @@ int fat_alloc_new_dir(struct inode *dir, struct timespec *ts) goto error_free; } - fat_date_unix2dos(ts->tv_sec, &time, &date, sbi->options.tz_utc); + fat_time_unix2fat(sbi, ts, &time, &date, &time_cs); de = (struct msdos_dir_entry *)bhs[0]->b_data; /* filling the new directory slots ("." and ".." entries) */ @@ -1112,13 +1115,14 @@ int fat_alloc_new_dir(struct inode *dir, struct timespec *ts) de[0].lcase = de[1].lcase = 0; de[0].time = de[1].time = time; de[0].date = de[1].date = date; - de[0].ctime_cs = de[1].ctime_cs = 0; if (sbi->options.isvfat) { /* extra timestamps */ de[0].ctime = de[1].ctime = time; + de[0].ctime_cs = de[1].ctime_cs = time_cs; de[0].adate = de[0].cdate = de[1].adate = de[1].cdate = date; } else { de[0].ctime = de[1].ctime = 0; + de[0].ctime_cs = de[1].ctime_cs = 0; de[0].adate = de[0].cdate = de[1].adate = de[1].cdate = 0; } de[0].start = cpu_to_le16(cluster); diff --git a/fs/fat/fat.h b/fs/fat/fat.h new file mode 100644 index 000000000000..ea440d65819c --- /dev/null +++ b/fs/fat/fat.h @@ -0,0 +1,329 @@ +#ifndef _FAT_H +#define _FAT_H + +#include +#include +#include +#include +#include +#include + +/* + * vfat shortname flags + */ +#define VFAT_SFN_DISPLAY_LOWER 0x0001 /* convert to lowercase for display */ +#define VFAT_SFN_DISPLAY_WIN95 0x0002 /* emulate win95 rule for display */ +#define VFAT_SFN_DISPLAY_WINNT 0x0004 /* emulate winnt rule for display */ +#define VFAT_SFN_CREATE_WIN95 0x0100 /* emulate win95 rule for create */ +#define VFAT_SFN_CREATE_WINNT 0x0200 /* emulate winnt rule for create */ + +struct fat_mount_options { + uid_t fs_uid; + gid_t fs_gid; + unsigned short fs_fmask; + unsigned short fs_dmask; + unsigned short codepage; /* Codepage for shortname conversions */ + char *iocharset; /* Charset used for filename input/display */ + unsigned short shortname; /* flags for shortname display/create rule */ + unsigned char name_check; /* r = relaxed, n = normal, s = strict */ + unsigned short allow_utime;/* permission for setting the [am]time */ + unsigned quiet:1, /* set = fake successful chmods and chowns */ + showexec:1, /* set = only set x bit for com/exe/bat */ + sys_immutable:1, /* set = system files are immutable */ + dotsOK:1, /* set = hidden and system files are named '.filename' */ + isvfat:1, /* 0=no vfat long filename support, 1=vfat support */ + utf8:1, /* Use of UTF-8 character set (Default) */ + unicode_xlate:1, /* create escape sequences for unhandled Unicode */ + numtail:1, /* Does first alias have a numeric '~1' type tail? */ + flush:1, /* write things quickly */ + nocase:1, /* Does this need case conversion? 0=need case conversion*/ + usefree:1, /* Use free_clusters for FAT32 */ + tz_utc:1, /* Filesystem timestamps are in UTC */ + rodir:1; /* allow ATTR_RO for directory */ +}; + +#define FAT_HASH_BITS 8 +#define FAT_HASH_SIZE (1UL << FAT_HASH_BITS) + +/* + * MS-DOS file system in-core superblock data + */ +struct msdos_sb_info { + unsigned short sec_per_clus; /* sectors/cluster */ + unsigned short cluster_bits; /* log2(cluster_size) */ + unsigned int cluster_size; /* cluster size */ + unsigned char fats,fat_bits; /* number of FATs, FAT bits (12 or 16) */ + unsigned short fat_start; + unsigned long fat_length; /* FAT start & length (sec.) */ + unsigned long dir_start; + unsigned short dir_entries; /* root dir start & entries */ + unsigned long data_start; /* first data sector */ + unsigned long max_cluster; /* maximum cluster number */ + unsigned long root_cluster; /* first cluster of the root directory */ + unsigned long fsinfo_sector; /* sector number of FAT32 fsinfo */ + struct mutex fat_lock; + unsigned int prev_free; /* previously allocated cluster number */ + unsigned int free_clusters; /* -1 if undefined */ + unsigned int free_clus_valid; /* is free_clusters valid? */ + struct fat_mount_options options; + struct nls_table *nls_disk; /* Codepage used on disk */ + struct nls_table *nls_io; /* Charset used for input and display */ + const void *dir_ops; /* Opaque; default directory operations */ + int dir_per_block; /* dir entries per block */ + int dir_per_block_bits; /* log2(dir_per_block) */ + + int fatent_shift; + struct fatent_operations *fatent_ops; + + spinlock_t inode_hash_lock; + struct hlist_head inode_hashtable[FAT_HASH_SIZE]; +}; + +#define FAT_CACHE_VALID 0 /* special case for valid cache */ + +/* + * MS-DOS file system inode data in memory + */ +struct msdos_inode_info { + spinlock_t cache_lru_lock; + struct list_head cache_lru; + int nr_caches; + /* for avoiding the race between fat_free() and fat_get_cluster() */ + unsigned int cache_valid_id; + + /* NOTE: mmu_private is 64bits, so must hold ->i_mutex to access */ + loff_t mmu_private; /* physically allocated size */ + + int i_start; /* first cluster or 0 */ + int i_logstart; /* logical first cluster */ + int i_attrs; /* unused attribute bits */ + loff_t i_pos; /* on-disk position of directory entry or 0 */ + struct hlist_node i_fat_hash; /* hash by i_location */ + struct inode vfs_inode; +}; + +struct fat_slot_info { + loff_t i_pos; /* on-disk position of directory entry */ + loff_t slot_off; /* offset for slot or de start */ + int nr_slots; /* number of slots + 1(de) in filename */ + struct msdos_dir_entry *de; + struct buffer_head *bh; +}; + +static inline struct msdos_sb_info *MSDOS_SB(struct super_block *sb) +{ + return sb->s_fs_info; +} + +static inline struct msdos_inode_info *MSDOS_I(struct inode *inode) +{ + return container_of(inode, struct msdos_inode_info, vfs_inode); +} + +/* + * If ->i_mode can't hold S_IWUGO (i.e. ATTR_RO), we use ->i_attrs to + * save ATTR_RO instead of ->i_mode. + * + * If it's directory and !sbi->options.rodir, ATTR_RO isn't read-only + * bit, it's just used as flag for app. + */ +static inline int fat_mode_can_hold_ro(struct inode *inode) +{ + struct msdos_sb_info *sbi = MSDOS_SB(inode->i_sb); + mode_t mask; + + if (S_ISDIR(inode->i_mode)) { + if (!sbi->options.rodir) + return 0; + mask = ~sbi->options.fs_dmask; + } else + mask = ~sbi->options.fs_fmask; + + if (!(mask & S_IWUGO)) + return 0; + return 1; +} + +/* Convert attribute bits and a mask to the UNIX mode. */ +static inline mode_t fat_make_mode(struct msdos_sb_info *sbi, + u8 attrs, mode_t mode) +{ + if (attrs & ATTR_RO && !((attrs & ATTR_DIR) && !sbi->options.rodir)) + mode &= ~S_IWUGO; + + if (attrs & ATTR_DIR) + return (mode & ~sbi->options.fs_dmask) | S_IFDIR; + else + return (mode & ~sbi->options.fs_fmask) | S_IFREG; +} + +/* Return the FAT attribute byte for this inode */ +static inline u8 fat_make_attrs(struct inode *inode) +{ + u8 attrs = MSDOS_I(inode)->i_attrs; + if (S_ISDIR(inode->i_mode)) + attrs |= ATTR_DIR; + if (fat_mode_can_hold_ro(inode) && !(inode->i_mode & S_IWUGO)) + attrs |= ATTR_RO; + return attrs; +} + +static inline void fat_save_attrs(struct inode *inode, u8 attrs) +{ + if (fat_mode_can_hold_ro(inode)) + MSDOS_I(inode)->i_attrs = attrs & ATTR_UNUSED; + else + MSDOS_I(inode)->i_attrs = attrs & (ATTR_UNUSED | ATTR_RO); +} + +static inline unsigned char fat_checksum(const __u8 *name) +{ + unsigned char s = name[0]; + s = (s<<7) + (s>>1) + name[1]; s = (s<<7) + (s>>1) + name[2]; + s = (s<<7) + (s>>1) + name[3]; s = (s<<7) + (s>>1) + name[4]; + s = (s<<7) + (s>>1) + name[5]; s = (s<<7) + (s>>1) + name[6]; + s = (s<<7) + (s>>1) + name[7]; s = (s<<7) + (s>>1) + name[8]; + s = (s<<7) + (s>>1) + name[9]; s = (s<<7) + (s>>1) + name[10]; + return s; +} + +static inline sector_t fat_clus_to_blknr(struct msdos_sb_info *sbi, int clus) +{ + return ((sector_t)clus - FAT_START_ENT) * sbi->sec_per_clus + + sbi->data_start; +} + +static inline void fat16_towchar(wchar_t *dst, const __u8 *src, size_t len) +{ +#ifdef __BIG_ENDIAN + while (len--) { + *dst++ = src[0] | (src[1] << 8); + src += 2; + } +#else + memcpy(dst, src, len * 2); +#endif +} + +static inline void fatwchar_to16(__u8 *dst, const wchar_t *src, size_t len) +{ +#ifdef __BIG_ENDIAN + while (len--) { + dst[0] = *src & 0x00FF; + dst[1] = (*src & 0xFF00) >> 8; + dst += 2; + src++; + } +#else + memcpy(dst, src, len * 2); +#endif +} + +/* fat/cache.c */ +extern void fat_cache_inval_inode(struct inode *inode); +extern int fat_get_cluster(struct inode *inode, int cluster, + int *fclus, int *dclus); +extern int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys, + unsigned long *mapped_blocks, int create); + +/* fat/dir.c */ +extern const struct file_operations fat_dir_operations; +extern int fat_search_long(struct inode *inode, const unsigned char *name, + int name_len, struct fat_slot_info *sinfo); +extern int fat_dir_empty(struct inode *dir); +extern int fat_subdirs(struct inode *dir); +extern int fat_scan(struct inode *dir, const unsigned char *name, + struct fat_slot_info *sinfo); +extern int fat_get_dotdot_entry(struct inode *dir, struct buffer_head **bh, + struct msdos_dir_entry **de, loff_t *i_pos); +extern int fat_alloc_new_dir(struct inode *dir, struct timespec *ts); +extern int fat_add_entries(struct inode *dir, void *slots, int nr_slots, + struct fat_slot_info *sinfo); +extern int fat_remove_entries(struct inode *dir, struct fat_slot_info *sinfo); + +/* fat/fatent.c */ +struct fat_entry { + int entry; + union { + u8 *ent12_p[2]; + __le16 *ent16_p; + __le32 *ent32_p; + } u; + int nr_bhs; + struct buffer_head *bhs[2]; +}; + +static inline void fatent_init(struct fat_entry *fatent) +{ + fatent->nr_bhs = 0; + fatent->entry = 0; + fatent->u.ent32_p = NULL; + fatent->bhs[0] = fatent->bhs[1] = NULL; +} + +static inline void fatent_set_entry(struct fat_entry *fatent, int entry) +{ + fatent->entry = entry; + fatent->u.ent32_p = NULL; +} + +static inline void fatent_brelse(struct fat_entry *fatent) +{ + int i; + fatent->u.ent32_p = NULL; + for (i = 0; i < fatent->nr_bhs; i++) + brelse(fatent->bhs[i]); + fatent->nr_bhs = 0; + fatent->bhs[0] = fatent->bhs[1] = NULL; +} + +extern void fat_ent_access_init(struct super_block *sb); +extern int fat_ent_read(struct inode *inode, struct fat_entry *fatent, + int entry); +extern int fat_ent_write(struct inode *inode, struct fat_entry *fatent, + int new, int wait); +extern int fat_alloc_clusters(struct inode *inode, int *cluster, + int nr_cluster); +extern int fat_free_clusters(struct inode *inode, int cluster); +extern int fat_count_free_clusters(struct super_block *sb); + +/* fat/file.c */ +extern int fat_generic_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern const struct file_operations fat_file_operations; +extern const struct inode_operations fat_file_inode_operations; +extern int fat_setattr(struct dentry * dentry, struct iattr * attr); +extern void fat_truncate(struct inode *inode); +extern int fat_getattr(struct vfsmount *mnt, struct dentry *dentry, + struct kstat *stat); + +/* fat/inode.c */ +extern void fat_attach(struct inode *inode, loff_t i_pos); +extern void fat_detach(struct inode *inode); +extern struct inode *fat_iget(struct super_block *sb, loff_t i_pos); +extern struct inode *fat_build_inode(struct super_block *sb, + struct msdos_dir_entry *de, loff_t i_pos); +extern int fat_sync_inode(struct inode *inode); +extern int fat_fill_super(struct super_block *sb, void *data, int silent, + const struct inode_operations *fs_dir_inode_ops, int isvfat); + +extern int fat_flush_inodes(struct super_block *sb, struct inode *i1, + struct inode *i2); +/* fat/misc.c */ +extern void fat_fs_panic(struct super_block *s, const char *fmt, ...) + __attribute__ ((format (printf, 2, 3))) __cold; +extern void fat_clusters_flush(struct super_block *sb); +extern int fat_chain_add(struct inode *inode, int new_dclus, int nr_cluster); +extern void fat_time_fat2unix(struct msdos_sb_info *sbi, struct timespec *ts, + __le16 __time, __le16 __date, u8 time_cs); +extern void fat_time_unix2fat(struct msdos_sb_info *sbi, struct timespec *ts, + __le16 *time, __le16 *date, u8 *time_cs); +extern int fat_sync_bhs(struct buffer_head **bhs, int nr_bhs); + +int fat_cache_init(void); +void fat_cache_destroy(void); + +/* helper for printk */ +typedef unsigned long long llu; + +#endif /* !_FAT_H */ diff --git a/fs/fat/fatent.c b/fs/fat/fatent.c index fb98b3d847ed..da6eea47872f 100644 --- a/fs/fat/fatent.c +++ b/fs/fat/fatent.c @@ -7,6 +7,7 @@ #include #include #include +#include "fat.h" struct fatent_operations { void (*ent_blocknr)(struct super_block *, int, int *, sector_t *); @@ -92,8 +93,7 @@ static int fat12_ent_bread(struct super_block *sb, struct fat_entry *fatent, err_brelse: brelse(bhs[0]); err: - printk(KERN_ERR "FAT: FAT read failed (blocknr %llu)\n", - (unsigned long long)blocknr); + printk(KERN_ERR "FAT: FAT read failed (blocknr %llu)\n", (llu)blocknr); return -EIO; } @@ -106,7 +106,7 @@ static int fat_ent_bread(struct super_block *sb, struct fat_entry *fatent, fatent->bhs[0] = sb_bread(sb, blocknr); if (!fatent->bhs[0]) { printk(KERN_ERR "FAT: FAT read failed (blocknr %llu)\n", - (unsigned long long)blocknr); + (llu)blocknr); return -EIO; } fatent->nr_bhs = 1; @@ -316,10 +316,20 @@ static inline int fat_ent_update_ptr(struct super_block *sb, /* Is this fatent's blocks including this entry? */ if (!fatent->nr_bhs || bhs[0]->b_blocknr != blocknr) return 0; - /* Does this entry need the next block? */ - if (sbi->fat_bits == 12 && (offset + 1) >= sb->s_blocksize) { - if (fatent->nr_bhs != 2 || bhs[1]->b_blocknr != (blocknr + 1)) - return 0; + if (sbi->fat_bits == 12) { + if ((offset + 1) < sb->s_blocksize) { + /* This entry is on bhs[0]. */ + if (fatent->nr_bhs == 2) { + brelse(bhs[1]); + fatent->nr_bhs = 1; + } + } else { + /* This entry needs the next block. */ + if (fatent->nr_bhs != 2) + return 0; + if (bhs[1]->b_blocknr != (blocknr + 1)) + return 0; + } } ops->ent_set_ptr(fatent, offset); return 1; diff --git a/fs/fat/file.c b/fs/fat/file.c index ddde37025ca6..f06a4e525ece 100644 --- a/fs/fat/file.c +++ b/fs/fat/file.c @@ -10,13 +10,13 @@ #include #include #include -#include #include #include #include #include #include #include +#include "fat.h" int fat_generic_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) @@ -29,10 +29,9 @@ int fat_generic_ioctl(struct inode *inode, struct file *filp, { u32 attr; - if (inode->i_ino == MSDOS_ROOT_INO) - attr = ATTR_DIR; - else - attr = fat_attr(inode); + mutex_lock(&inode->i_mutex); + attr = fat_make_attrs(inode); + mutex_unlock(&inode->i_mutex); return put_user(attr, user_attr); } @@ -62,20 +61,16 @@ int fat_generic_ioctl(struct inode *inode, struct file *filp, /* Merge in ATTR_VOLUME and ATTR_DIR */ attr |= (MSDOS_I(inode)->i_attrs & ATTR_VOLUME) | (is_dir ? ATTR_DIR : 0); - oldattr = fat_attr(inode); + oldattr = fat_make_attrs(inode); /* Equivalent to a chmod() */ ia.ia_valid = ATTR_MODE | ATTR_CTIME; ia.ia_ctime = current_fs_time(inode->i_sb); - if (is_dir) { - ia.ia_mode = MSDOS_MKMODE(attr, - S_IRWXUGO & ~sbi->options.fs_dmask) - | S_IFDIR; - } else { - ia.ia_mode = MSDOS_MKMODE(attr, - (S_IRUGO | S_IWUGO | (inode->i_mode & S_IXUGO)) - & ~sbi->options.fs_fmask) - | S_IFREG; + if (is_dir) + ia.ia_mode = fat_make_mode(sbi, attr, S_IRWXUGO); + else { + ia.ia_mode = fat_make_mode(sbi, attr, + S_IRUGO | S_IWUGO | (inode->i_mode & S_IXUGO)); } /* The root directory has no attributes */ @@ -115,7 +110,7 @@ int fat_generic_ioctl(struct inode *inode, struct file *filp, inode->i_flags &= S_IMMUTABLE; } - MSDOS_I(inode)->i_attrs = attr & ATTR_UNUSED; + fat_save_attrs(inode, attr); mark_inode_dirty(inode); up: mnt_drop_write(filp->f_path.mnt); @@ -274,7 +269,7 @@ static int fat_sanitize_mode(const struct msdos_sb_info *sbi, /* * Note, the basic check is already done by a caller of - * (attr->ia_mode & ~MSDOS_VALID_MODE) + * (attr->ia_mode & ~FAT_VALID_MODE) */ if (S_ISREG(inode->i_mode)) @@ -287,11 +282,18 @@ static int fat_sanitize_mode(const struct msdos_sb_info *sbi, /* * Of the r and x bits, all (subject to umask) must be present. Of the * w bits, either all (subject to umask) or none must be present. + * + * If fat_mode_can_hold_ro(inode) is false, can't change w bits. */ if ((perm & (S_IRUGO | S_IXUGO)) != (inode->i_mode & (S_IRUGO|S_IXUGO))) return -EPERM; - if ((perm & S_IWUGO) && ((perm & S_IWUGO) != (S_IWUGO & ~mask))) - return -EPERM; + if (fat_mode_can_hold_ro(inode)) { + if ((perm & S_IWUGO) && ((perm & S_IWUGO) != (S_IWUGO & ~mask))) + return -EPERM; + } else { + if ((perm & S_IWUGO) != (S_IWUGO & ~mask)) + return -EPERM; + } *mode_ptr &= S_IFMT | perm; @@ -314,13 +316,15 @@ static int fat_allow_set_time(struct msdos_sb_info *sbi, struct inode *inode) } #define TIMES_SET_FLAGS (ATTR_MTIME_SET | ATTR_ATIME_SET | ATTR_TIMES_SET) +/* valid file mode bits */ +#define FAT_VALID_MODE (S_IFREG | S_IFDIR | S_IRWXUGO) int fat_setattr(struct dentry *dentry, struct iattr *attr) { struct msdos_sb_info *sbi = MSDOS_SB(dentry->d_sb); struct inode *inode = dentry->d_inode; - int error = 0; unsigned int ia_valid; + int error; /* * Expand the file. Since inode_setattr() updates ->i_size @@ -356,7 +360,7 @@ int fat_setattr(struct dentry *dentry, struct iattr *attr) ((attr->ia_valid & ATTR_GID) && (attr->ia_gid != sbi->options.fs_gid)) || ((attr->ia_valid & ATTR_MODE) && - (attr->ia_mode & ~MSDOS_VALID_MODE))) + (attr->ia_mode & ~FAT_VALID_MODE))) error = -EPERM; if (error) { @@ -374,7 +378,8 @@ int fat_setattr(struct dentry *dentry, struct iattr *attr) attr->ia_valid &= ~ATTR_MODE; } - error = inode_setattr(inode, attr); + if (attr->ia_valid) + error = inode_setattr(inode, attr); out: return error; } diff --git a/fs/fat/inode.c b/fs/fat/inode.c index 19eafbe3c379..bdd8fb7be2ca 100644 --- a/fs/fat/inode.c +++ b/fs/fat/inode.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -27,7 +26,9 @@ #include #include #include +#include #include +#include "fat.h" #ifndef CONFIG_FAT_DEFAULT_IOCHARSET /* if user don't select VFAT, this is undefined. */ @@ -63,7 +64,7 @@ static inline int __fat_get_block(struct inode *inode, sector_t iblock, sector_t phys; int err, offset; - err = fat_bmap(inode, iblock, &phys, &mapped_blocks); + err = fat_bmap(inode, iblock, &phys, &mapped_blocks, create); if (err) return err; if (phys) { @@ -93,7 +94,7 @@ static inline int __fat_get_block(struct inode *inode, sector_t iblock, *max_blocks = min(mapped_blocks, *max_blocks); MSDOS_I(inode)->mmu_private += *max_blocks << sb->s_blocksize_bits; - err = fat_bmap(inode, iblock, &phys, &mapped_blocks); + err = fat_bmap(inode, iblock, &phys, &mapped_blocks, create); if (err) return err; @@ -175,7 +176,7 @@ static ssize_t fat_direct_IO(int rw, struct kiocb *iocb, if (rw == WRITE) { /* - * FIXME: blockdev_direct_IO() doesn't use ->prepare_write(), + * FIXME: blockdev_direct_IO() doesn't use ->write_begin(), * so we need to update the ->mmu_private to block boundary. * * But we must fill the remaining area or hole by nul for @@ -198,7 +199,14 @@ static ssize_t fat_direct_IO(int rw, struct kiocb *iocb, static sector_t _fat_bmap(struct address_space *mapping, sector_t block) { - return generic_block_bmap(mapping, block, fat_get_block); + sector_t blocknr; + + /* fat_get_cluster() assumes the requested blocknr isn't truncated. */ + mutex_lock(&mapping->host->i_mutex); + blocknr = generic_block_bmap(mapping, block, fat_get_block); + mutex_unlock(&mapping->host->i_mutex); + + return blocknr; } static const struct address_space_operations fat_aops = { @@ -247,25 +255,21 @@ static void fat_hash_init(struct super_block *sb) INIT_HLIST_HEAD(&sbi->inode_hashtable[i]); } -static inline unsigned long fat_hash(struct super_block *sb, loff_t i_pos) +static inline unsigned long fat_hash(loff_t i_pos) { - unsigned long tmp = (unsigned long)i_pos | (unsigned long) sb; - tmp = tmp + (tmp >> FAT_HASH_BITS) + (tmp >> FAT_HASH_BITS * 2); - return tmp & FAT_HASH_MASK; + return hash_32(i_pos, FAT_HASH_BITS); } void fat_attach(struct inode *inode, loff_t i_pos) { - struct super_block *sb = inode->i_sb; - struct msdos_sb_info *sbi = MSDOS_SB(sb); + struct msdos_sb_info *sbi = MSDOS_SB(inode->i_sb); + struct hlist_head *head = sbi->inode_hashtable + fat_hash(i_pos); spin_lock(&sbi->inode_hash_lock); MSDOS_I(inode)->i_pos = i_pos; - hlist_add_head(&MSDOS_I(inode)->i_fat_hash, - sbi->inode_hashtable + fat_hash(sb, i_pos)); + hlist_add_head(&MSDOS_I(inode)->i_fat_hash, head); spin_unlock(&sbi->inode_hash_lock); } - EXPORT_SYMBOL_GPL(fat_attach); void fat_detach(struct inode *inode) @@ -276,13 +280,12 @@ void fat_detach(struct inode *inode) hlist_del_init(&MSDOS_I(inode)->i_fat_hash); spin_unlock(&sbi->inode_hash_lock); } - EXPORT_SYMBOL_GPL(fat_detach); struct inode *fat_iget(struct super_block *sb, loff_t i_pos) { struct msdos_sb_info *sbi = MSDOS_SB(sb); - struct hlist_head *head = sbi->inode_hashtable + fat_hash(sb, i_pos); + struct hlist_head *head = sbi->inode_hashtable + fat_hash(i_pos); struct hlist_node *_p; struct msdos_inode_info *i; struct inode *inode = NULL; @@ -341,8 +344,7 @@ static int fat_fill_inode(struct inode *inode, struct msdos_dir_entry *de) if ((de->attr & ATTR_DIR) && !IS_FREE(de->name)) { inode->i_generation &= ~1; - inode->i_mode = MSDOS_MKMODE(de->attr, - S_IRWXUGO & ~sbi->options.fs_dmask) | S_IFDIR; + inode->i_mode = fat_make_mode(sbi, de->attr, S_IRWXUGO); inode->i_op = sbi->dir_ops; inode->i_fop = &fat_dir_operations; @@ -359,10 +361,9 @@ static int fat_fill_inode(struct inode *inode, struct msdos_dir_entry *de) inode->i_nlink = fat_subdirs(inode); } else { /* not a directory */ inode->i_generation |= 1; - inode->i_mode = MSDOS_MKMODE(de->attr, - ((sbi->options.showexec && !is_exec(de->name + 8)) - ? S_IRUGO|S_IWUGO : S_IRWXUGO) - & ~sbi->options.fs_fmask) | S_IFREG; + inode->i_mode = fat_make_mode(sbi, de->attr, + ((sbi->options.showexec && !is_exec(de->name + 8)) + ? S_IRUGO|S_IWUGO : S_IRWXUGO)); MSDOS_I(inode)->i_start = le16_to_cpu(de->start); if (sbi->fat_bits == 32) MSDOS_I(inode)->i_start |= (le16_to_cpu(de->starthi) << 16); @@ -378,25 +379,16 @@ static int fat_fill_inode(struct inode *inode, struct msdos_dir_entry *de) if (sbi->options.sys_immutable) inode->i_flags |= S_IMMUTABLE; } - MSDOS_I(inode)->i_attrs = de->attr & ATTR_UNUSED; + fat_save_attrs(inode, de->attr); + inode->i_blocks = ((inode->i_size + (sbi->cluster_size - 1)) & ~((loff_t)sbi->cluster_size - 1)) >> 9; - inode->i_mtime.tv_sec = - date_dos2unix(le16_to_cpu(de->time), le16_to_cpu(de->date), - sbi->options.tz_utc); - inode->i_mtime.tv_nsec = 0; + + fat_time_fat2unix(sbi, &inode->i_mtime, de->time, de->date, 0); if (sbi->options.isvfat) { - int secs = de->ctime_cs / 100; - int csecs = de->ctime_cs % 100; - inode->i_ctime.tv_sec = - date_dos2unix(le16_to_cpu(de->ctime), - le16_to_cpu(de->cdate), - sbi->options.tz_utc) + secs; - inode->i_ctime.tv_nsec = csecs * 10000000; - inode->i_atime.tv_sec = - date_dos2unix(0, le16_to_cpu(de->adate), - sbi->options.tz_utc); - inode->i_atime.tv_nsec = 0; + fat_time_fat2unix(sbi, &inode->i_ctime, de->ctime, + de->cdate, de->ctime_cs); + fat_time_fat2unix(sbi, &inode->i_atime, 0, de->adate, 0); } else inode->i_ctime = inode->i_atime = inode->i_mtime; @@ -443,13 +435,8 @@ static void fat_delete_inode(struct inode *inode) static void fat_clear_inode(struct inode *inode) { - struct super_block *sb = inode->i_sb; - struct msdos_sb_info *sbi = MSDOS_SB(sb); - - spin_lock(&sbi->inode_hash_lock); fat_cache_inval_inode(inode); - hlist_del_init(&MSDOS_I(inode)->i_fat_hash); - spin_unlock(&sbi->inode_hash_lock); + fat_detach(inode); } static void fat_write_super(struct super_block *sb) @@ -555,6 +542,20 @@ static int fat_statfs(struct dentry *dentry, struct kstatfs *buf) return 0; } +static inline loff_t fat_i_pos_read(struct msdos_sb_info *sbi, + struct inode *inode) +{ + loff_t i_pos; +#if BITS_PER_LONG == 32 + spin_lock(&sbi->inode_hash_lock); +#endif + i_pos = MSDOS_I(inode)->i_pos; +#if BITS_PER_LONG == 32 + spin_unlock(&sbi->inode_hash_lock); +#endif + return i_pos; +} + static int fat_write_inode(struct inode *inode, int wait) { struct super_block *sb = inode->i_sb; @@ -564,9 +565,12 @@ static int fat_write_inode(struct inode *inode, int wait) loff_t i_pos; int err; + if (inode->i_ino == MSDOS_ROOT_INO) + return 0; + retry: - i_pos = MSDOS_I(inode)->i_pos; - if (inode->i_ino == MSDOS_ROOT_INO || !i_pos) + i_pos = fat_i_pos_read(sbi, inode); + if (!i_pos) return 0; bh = sb_bread(sb, i_pos >> sbi->dir_per_block_bits); @@ -588,19 +592,17 @@ retry: raw_entry->size = 0; else raw_entry->size = cpu_to_le32(inode->i_size); - raw_entry->attr = fat_attr(inode); + raw_entry->attr = fat_make_attrs(inode); raw_entry->start = cpu_to_le16(MSDOS_I(inode)->i_logstart); raw_entry->starthi = cpu_to_le16(MSDOS_I(inode)->i_logstart >> 16); - fat_date_unix2dos(inode->i_mtime.tv_sec, &raw_entry->time, - &raw_entry->date, sbi->options.tz_utc); + fat_time_unix2fat(sbi, &inode->i_mtime, &raw_entry->time, + &raw_entry->date, NULL); if (sbi->options.isvfat) { __le16 atime; - fat_date_unix2dos(inode->i_ctime.tv_sec, &raw_entry->ctime, - &raw_entry->cdate, sbi->options.tz_utc); - fat_date_unix2dos(inode->i_atime.tv_sec, &atime, - &raw_entry->adate, sbi->options.tz_utc); - raw_entry->ctime_cs = (inode->i_ctime.tv_sec & 1) * 100 + - inode->i_ctime.tv_nsec / 10000000; + fat_time_unix2fat(sbi, &inode->i_ctime, &raw_entry->ctime, + &raw_entry->cdate, &raw_entry->ctime_cs); + fat_time_unix2fat(sbi, &inode->i_atime, &atime, + &raw_entry->adate, NULL); } spin_unlock(&sbi->inode_hash_lock); mark_buffer_dirty(bh); @@ -819,8 +821,10 @@ static int fat_show_options(struct seq_file *m, struct vfsmount *mnt) seq_puts(m, ",uni_xlate"); if (!opts->numtail) seq_puts(m, ",nonumtail"); + if (opts->rodir) + seq_puts(m, ",rodir"); } - if (sbi->options.flush) + if (opts->flush) seq_puts(m, ",flush"); if (opts->tz_utc) seq_puts(m, ",tz=UTC"); @@ -836,7 +840,7 @@ enum { Opt_charset, Opt_shortname_lower, Opt_shortname_win95, Opt_shortname_winnt, Opt_shortname_mixed, Opt_utf8_no, Opt_utf8_yes, Opt_uni_xl_no, Opt_uni_xl_yes, Opt_nonumtail_no, Opt_nonumtail_yes, - Opt_obsolate, Opt_flush, Opt_tz_utc, Opt_err, + Opt_obsolate, Opt_flush, Opt_tz_utc, Opt_rodir, Opt_err, }; static const match_table_t fat_tokens = { @@ -908,6 +912,7 @@ static const match_table_t vfat_tokens = { {Opt_nonumtail_yes, "nonumtail=yes"}, {Opt_nonumtail_yes, "nonumtail=true"}, {Opt_nonumtail_yes, "nonumtail"}, + {Opt_rodir, "rodir"}, {Opt_err, NULL} }; @@ -927,10 +932,13 @@ static int parse_options(char *options, int is_vfat, int silent, int *debug, opts->allow_utime = -1; opts->codepage = fat_default_codepage; opts->iocharset = fat_default_iocharset; - if (is_vfat) + if (is_vfat) { opts->shortname = VFAT_SFN_DISPLAY_LOWER|VFAT_SFN_CREATE_WIN95; - else + opts->rodir = 0; + } else { opts->shortname = 0; + opts->rodir = 1; + } opts->name_check = 'n'; opts->quiet = opts->showexec = opts->sys_immutable = opts->dotsOK = 0; opts->utf8 = opts->unicode_xlate = 0; @@ -1081,6 +1089,9 @@ static int parse_options(char *options, int is_vfat, int silent, int *debug, case Opt_nonumtail_yes: /* empty or 1 or yes or true */ opts->numtail = 0; /* negated option */ break; + case Opt_rodir: + opts->rodir = 1; + break; /* obsolete mount options */ case Opt_obsolate: @@ -1126,7 +1137,7 @@ static int fat_read_root(struct inode *inode) inode->i_gid = sbi->options.fs_gid; inode->i_version++; inode->i_generation = 0; - inode->i_mode = (S_IRWXUGO & ~sbi->options.fs_dmask) | S_IFDIR; + inode->i_mode = fat_make_mode(sbi, ATTR_DIR, S_IRWXUGO); inode->i_op = sbi->dir_ops; inode->i_fop = &fat_dir_operations; if (sbi->fat_bits == 32) { @@ -1143,7 +1154,7 @@ static int fat_read_root(struct inode *inode) MSDOS_I(inode)->i_logstart = 0; MSDOS_I(inode)->mmu_private = inode->i_size; - MSDOS_I(inode)->i_attrs = ATTR_NONE; + fat_save_attrs(inode, ATTR_DIR); inode->i_mtime.tv_sec = inode->i_atime.tv_sec = inode->i_ctime.tv_sec = 0; inode->i_mtime.tv_nsec = inode->i_atime.tv_nsec = inode->i_ctime.tv_nsec = 0; inode->i_nlink = fat_subdirs(inode)+2; diff --git a/fs/fat/misc.c b/fs/fat/misc.c index 79fb98ad36d4..ac39ebcc1496 100644 --- a/fs/fat/misc.c +++ b/fs/fat/misc.c @@ -8,8 +8,8 @@ #include #include -#include #include +#include "fat.h" /* * fat_fs_panic reports a severe file system problem and sets the file system @@ -124,8 +124,9 @@ int fat_chain_add(struct inode *inode, int new_dclus, int nr_cluster) mark_inode_dirty(inode); } if (new_fclus != (inode->i_blocks >> (sbi->cluster_bits - 9))) { - fat_fs_panic(sb, "clusters badly computed (%d != %lu)", - new_fclus, inode->i_blocks >> (sbi->cluster_bits - 9)); + fat_fs_panic(sb, "clusters badly computed (%d != %llu)", + new_fclus, + (llu)(inode->i_blocks >> (sbi->cluster_bits - 9))); fat_cache_inval_inode(inode); } inode->i_blocks += nr_cluster << (sbi->cluster_bits - 9); @@ -135,65 +136,131 @@ int fat_chain_add(struct inode *inode, int new_dclus, int nr_cluster) extern struct timezone sys_tz; +/* + * The epoch of FAT timestamp is 1980. + * : bits : value + * date: 0 - 4: day (1 - 31) + * date: 5 - 8: month (1 - 12) + * date: 9 - 15: year (0 - 127) from 1980 + * time: 0 - 4: sec (0 - 29) 2sec counts + * time: 5 - 10: min (0 - 59) + * time: 11 - 15: hour (0 - 23) + */ +#define SECS_PER_MIN 60 +#define SECS_PER_HOUR (60 * 60) +#define SECS_PER_DAY (SECS_PER_HOUR * 24) +#define UNIX_SECS_1980 315532800L +#if BITS_PER_LONG == 64 +#define UNIX_SECS_2108 4354819200L +#endif +/* days between 1.1.70 and 1.1.80 (2 leap days) */ +#define DAYS_DELTA (365 * 10 + 2) +/* 120 (2100 - 1980) isn't leap year */ +#define YEAR_2100 120 +#define IS_LEAP_YEAR(y) (!((y) & 3) && (y) != YEAR_2100) + /* Linear day numbers of the respective 1sts in non-leap years. */ -static int day_n[] = { - /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ - 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 0, 0, 0, 0 +static time_t days_in_year[] = { + /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ + 0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 0, 0, 0, }; -/* Convert a MS-DOS time/date pair to a UNIX date (seconds since 1 1 70). */ -int date_dos2unix(unsigned short time, unsigned short date, int tz_utc) +/* Convert a FAT time/date pair to a UNIX date (seconds since 1 1 70). */ +void fat_time_fat2unix(struct msdos_sb_info *sbi, struct timespec *ts, + __le16 __time, __le16 __date, u8 time_cs) { - int month, year, secs; + u16 time = le16_to_cpu(__time), date = le16_to_cpu(__date); + time_t second, day, leap_day, month, year; - /* - * first subtract and mask after that... Otherwise, if - * date == 0, bad things happen - */ - month = ((date >> 5) - 1) & 15; - year = date >> 9; - secs = (time & 31)*2+60*((time >> 5) & 63)+(time >> 11)*3600+86400* - ((date & 31)-1+day_n[month]+(year/4)+year*365-((year & 3) == 0 && - month < 2 ? 1 : 0)+3653); - /* days since 1.1.70 plus 80's leap day */ - if (!tz_utc) - secs += sys_tz.tz_minuteswest*60; - return secs; + year = date >> 9; + month = max(1, (date >> 5) & 0xf); + day = max(1, date & 0x1f) - 1; + + leap_day = (year + 3) / 4; + if (year > YEAR_2100) /* 2100 isn't leap year */ + leap_day--; + if (IS_LEAP_YEAR(year) && month > 2) + leap_day++; + + second = (time & 0x1f) << 1; + second += ((time >> 5) & 0x3f) * SECS_PER_MIN; + second += (time >> 11) * SECS_PER_HOUR; + second += (year * 365 + leap_day + + days_in_year[month] + day + + DAYS_DELTA) * SECS_PER_DAY; + + if (!sbi->options.tz_utc) + second += sys_tz.tz_minuteswest * SECS_PER_MIN; + + if (time_cs) { + ts->tv_sec = second + (time_cs / 100); + ts->tv_nsec = (time_cs % 100) * 10000000; + } else { + ts->tv_sec = second; + ts->tv_nsec = 0; + } } -/* Convert linear UNIX date to a MS-DOS time/date pair. */ -void fat_date_unix2dos(int unix_date, __le16 *time, __le16 *date, int tz_utc) +/* Convert linear UNIX date to a FAT time/date pair. */ +void fat_time_unix2fat(struct msdos_sb_info *sbi, struct timespec *ts, + __le16 *time, __le16 *date, u8 *time_cs) { - int day, year, nl_day, month; + time_t second = ts->tv_sec; + time_t day, leap_day, month, year; - if (!tz_utc) - unix_date -= sys_tz.tz_minuteswest*60; + if (!sbi->options.tz_utc) + second -= sys_tz.tz_minuteswest * SECS_PER_MIN; /* Jan 1 GMT 00:00:00 1980. But what about another time zone? */ - if (unix_date < 315532800) - unix_date = 315532800; - - *time = cpu_to_le16((unix_date % 60)/2+(((unix_date/60) % 60) << 5)+ - (((unix_date/3600) % 24) << 11)); - day = unix_date/86400-3652; - year = day/365; - if ((year+3)/4+365*year > day) + if (second < UNIX_SECS_1980) { + *time = 0; + *date = cpu_to_le16((0 << 9) | (1 << 5) | 1); + if (time_cs) + *time_cs = 0; + return; + } +#if BITS_PER_LONG == 64 + if (second >= UNIX_SECS_2108) { + *time = cpu_to_le16((23 << 11) | (59 << 5) | 29); + *date = cpu_to_le16((127 << 9) | (12 << 5) | 31); + if (time_cs) + *time_cs = 199; + return; + } +#endif + + day = second / SECS_PER_DAY - DAYS_DELTA; + year = day / 365; + leap_day = (year + 3) / 4; + if (year > YEAR_2100) /* 2100 isn't leap year */ + leap_day--; + if (year * 365 + leap_day > day) year--; - day -= (year+3)/4+365*year; - if (day == 59 && !(year & 3)) { - nl_day = day; + leap_day = (year + 3) / 4; + if (year > YEAR_2100) /* 2100 isn't leap year */ + leap_day--; + day -= year * 365 + leap_day; + + if (IS_LEAP_YEAR(year) && day == days_in_year[3]) { month = 2; } else { - nl_day = (year & 3) || day <= 59 ? day : day-1; - for (month = 0; month < 12; month++) { - if (day_n[month] > nl_day) + if (IS_LEAP_YEAR(year) && day > days_in_year[3]) + day--; + for (month = 1; month < 12; month++) { + if (days_in_year[month + 1] > day) break; } } - *date = cpu_to_le16(nl_day-day_n[month-1]+1+(month << 5)+(year << 9)); -} + day -= days_in_year[month]; -EXPORT_SYMBOL_GPL(fat_date_unix2dos); + *time = cpu_to_le16(((second / SECS_PER_HOUR) % 24) << 11 + | ((second / SECS_PER_MIN) % 60) << 5 + | (second % SECS_PER_MIN) >> 1); + *date = cpu_to_le16((year << 9) | (month << 5) | (day + 1)); + if (time_cs) + *time_cs = (ts->tv_sec & 1) * 100 + ts->tv_nsec / 10000000; +} +EXPORT_SYMBOL_GPL(fat_time_unix2fat); int fat_sync_bhs(struct buffer_head **bhs, int nr_bhs) { diff --git a/fs/fat/namei_msdos.c b/fs/fat/namei_msdos.c new file mode 100644 index 000000000000..7ba03a4acbe0 --- /dev/null +++ b/fs/fat/namei_msdos.c @@ -0,0 +1,706 @@ +/* + * linux/fs/msdos/namei.c + * + * Written 1992,1993 by Werner Almesberger + * Hidden files 1995 by Albert Cahalan + * Rewritten for constant inumbers 1999 by Al Viro + */ + +#include +#include +#include +#include +#include "fat.h" + +/* Characters that are undesirable in an MS-DOS file name */ +static unsigned char bad_chars[] = "*?<>|\""; +static unsigned char bad_if_strict[] = "+=,; "; + +/***** Formats an MS-DOS file name. Rejects invalid names. */ +static int msdos_format_name(const unsigned char *name, int len, + unsigned char *res, struct fat_mount_options *opts) + /* + * name is the proposed name, len is its length, res is + * the resulting name, opts->name_check is either (r)elaxed, + * (n)ormal or (s)trict, opts->dotsOK allows dots at the + * beginning of name (for hidden files) + */ +{ + unsigned char *walk; + unsigned char c; + int space; + + if (name[0] == '.') { /* dotfile because . and .. already done */ + if (opts->dotsOK) { + /* Get rid of dot - test for it elsewhere */ + name++; + len--; + } else + return -EINVAL; + } + /* + * disallow names that _really_ start with a dot + */ + space = 1; + c = 0; + for (walk = res; len && walk - res < 8; walk++) { + c = *name++; + len--; + if (opts->name_check != 'r' && strchr(bad_chars, c)) + return -EINVAL; + if (opts->name_check == 's' && strchr(bad_if_strict, c)) + return -EINVAL; + if (c >= 'A' && c <= 'Z' && opts->name_check == 's') + return -EINVAL; + if (c < ' ' || c == ':' || c == '\\') + return -EINVAL; + /* + * 0xE5 is legal as a first character, but we must substitute + * 0x05 because 0xE5 marks deleted files. Yes, DOS really + * does this. + * It seems that Microsoft hacked DOS to support non-US + * characters after the 0xE5 character was already in use to + * mark deleted files. + */ + if ((res == walk) && (c == 0xE5)) + c = 0x05; + if (c == '.') + break; + space = (c == ' '); + *walk = (!opts->nocase && c >= 'a' && c <= 'z') ? c - 32 : c; + } + if (space) + return -EINVAL; + if (opts->name_check == 's' && len && c != '.') { + c = *name++; + len--; + if (c != '.') + return -EINVAL; + } + while (c != '.' && len--) + c = *name++; + if (c == '.') { + while (walk - res < 8) + *walk++ = ' '; + while (len > 0 && walk - res < MSDOS_NAME) { + c = *name++; + len--; + if (opts->name_check != 'r' && strchr(bad_chars, c)) + return -EINVAL; + if (opts->name_check == 's' && + strchr(bad_if_strict, c)) + return -EINVAL; + if (c < ' ' || c == ':' || c == '\\') + return -EINVAL; + if (c == '.') { + if (opts->name_check == 's') + return -EINVAL; + break; + } + if (c >= 'A' && c <= 'Z' && opts->name_check == 's') + return -EINVAL; + space = c == ' '; + if (!opts->nocase && c >= 'a' && c <= 'z') + *walk++ = c - 32; + else + *walk++ = c; + } + if (space) + return -EINVAL; + if (opts->name_check == 's' && len) + return -EINVAL; + } + while (walk - res < MSDOS_NAME) + *walk++ = ' '; + + return 0; +} + +/***** Locates a directory entry. Uses unformatted name. */ +static int msdos_find(struct inode *dir, const unsigned char *name, int len, + struct fat_slot_info *sinfo) +{ + struct msdos_sb_info *sbi = MSDOS_SB(dir->i_sb); + unsigned char msdos_name[MSDOS_NAME]; + int err; + + err = msdos_format_name(name, len, msdos_name, &sbi->options); + if (err) + return -ENOENT; + + err = fat_scan(dir, msdos_name, sinfo); + if (!err && sbi->options.dotsOK) { + if (name[0] == '.') { + if (!(sinfo->de->attr & ATTR_HIDDEN)) + err = -ENOENT; + } else { + if (sinfo->de->attr & ATTR_HIDDEN) + err = -ENOENT; + } + if (err) + brelse(sinfo->bh); + } + return err; +} + +/* + * Compute the hash for the msdos name corresponding to the dentry. + * Note: if the name is invalid, we leave the hash code unchanged so + * that the existing dentry can be used. The msdos fs routines will + * return ENOENT or EINVAL as appropriate. + */ +static int msdos_hash(struct dentry *dentry, struct qstr *qstr) +{ + struct fat_mount_options *options = &MSDOS_SB(dentry->d_sb)->options; + unsigned char msdos_name[MSDOS_NAME]; + int error; + + error = msdos_format_name(qstr->name, qstr->len, msdos_name, options); + if (!error) + qstr->hash = full_name_hash(msdos_name, MSDOS_NAME); + return 0; +} + +/* + * Compare two msdos names. If either of the names are invalid, + * we fall back to doing the standard name comparison. + */ +static int msdos_cmp(struct dentry *dentry, struct qstr *a, struct qstr *b) +{ + struct fat_mount_options *options = &MSDOS_SB(dentry->d_sb)->options; + unsigned char a_msdos_name[MSDOS_NAME], b_msdos_name[MSDOS_NAME]; + int error; + + error = msdos_format_name(a->name, a->len, a_msdos_name, options); + if (error) + goto old_compare; + error = msdos_format_name(b->name, b->len, b_msdos_name, options); + if (error) + goto old_compare; + error = memcmp(a_msdos_name, b_msdos_name, MSDOS_NAME); +out: + return error; + +old_compare: + error = 1; + if (a->len == b->len) + error = memcmp(a->name, b->name, a->len); + goto out; +} + +static struct dentry_operations msdos_dentry_operations = { + .d_hash = msdos_hash, + .d_compare = msdos_cmp, +}; + +/* + * AV. Wrappers for FAT sb operations. Is it wise? + */ + +/***** Get inode using directory and name */ +static struct dentry *msdos_lookup(struct inode *dir, struct dentry *dentry, + struct nameidata *nd) +{ + struct super_block *sb = dir->i_sb; + struct fat_slot_info sinfo; + struct inode *inode; + int err; + + lock_super(sb); + + err = msdos_find(dir, dentry->d_name.name, dentry->d_name.len, &sinfo); + if (err) { + if (err == -ENOENT) { + inode = NULL; + goto out; + } + goto error; + } + + inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); + brelse(sinfo.bh); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + goto error; + } +out: + unlock_super(sb); + dentry->d_op = &msdos_dentry_operations; + dentry = d_splice_alias(inode, dentry); + if (dentry) + dentry->d_op = &msdos_dentry_operations; + return dentry; + +error: + unlock_super(sb); + return ERR_PTR(err); +} + +/***** Creates a directory entry (name is already formatted). */ +static int msdos_add_entry(struct inode *dir, const unsigned char *name, + int is_dir, int is_hid, int cluster, + struct timespec *ts, struct fat_slot_info *sinfo) +{ + struct msdos_sb_info *sbi = MSDOS_SB(dir->i_sb); + struct msdos_dir_entry de; + __le16 time, date; + int err; + + memcpy(de.name, name, MSDOS_NAME); + de.attr = is_dir ? ATTR_DIR : ATTR_ARCH; + if (is_hid) + de.attr |= ATTR_HIDDEN; + de.lcase = 0; + fat_time_unix2fat(sbi, ts, &time, &date, NULL); + de.cdate = de.adate = 0; + de.ctime = 0; + de.ctime_cs = 0; + de.time = time; + de.date = date; + de.start = cpu_to_le16(cluster); + de.starthi = cpu_to_le16(cluster >> 16); + de.size = 0; + + err = fat_add_entries(dir, &de, 1, sinfo); + if (err) + return err; + + dir->i_ctime = dir->i_mtime = *ts; + if (IS_DIRSYNC(dir)) + (void)fat_sync_inode(dir); + else + mark_inode_dirty(dir); + + return 0; +} + +/***** Create a file */ +static int msdos_create(struct inode *dir, struct dentry *dentry, int mode, + struct nameidata *nd) +{ + struct super_block *sb = dir->i_sb; + struct inode *inode = NULL; + struct fat_slot_info sinfo; + struct timespec ts; + unsigned char msdos_name[MSDOS_NAME]; + int err, is_hid; + + lock_super(sb); + + err = msdos_format_name(dentry->d_name.name, dentry->d_name.len, + msdos_name, &MSDOS_SB(sb)->options); + if (err) + goto out; + is_hid = (dentry->d_name.name[0] == '.') && (msdos_name[0] != '.'); + /* Have to do it due to foo vs. .foo conflicts */ + if (!fat_scan(dir, msdos_name, &sinfo)) { + brelse(sinfo.bh); + err = -EINVAL; + goto out; + } + + ts = CURRENT_TIME_SEC; + err = msdos_add_entry(dir, msdos_name, 0, is_hid, 0, &ts, &sinfo); + if (err) + goto out; + inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); + brelse(sinfo.bh); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + goto out; + } + inode->i_mtime = inode->i_atime = inode->i_ctime = ts; + /* timestamp is already written, so mark_inode_dirty() is unneeded. */ + + d_instantiate(dentry, inode); +out: + unlock_super(sb); + if (!err) + err = fat_flush_inodes(sb, dir, inode); + return err; +} + +/***** Remove a directory */ +static int msdos_rmdir(struct inode *dir, struct dentry *dentry) +{ + struct super_block *sb = dir->i_sb; + struct inode *inode = dentry->d_inode; + struct fat_slot_info sinfo; + int err; + + lock_super(sb); + /* + * Check whether the directory is not in use, then check + * whether it is empty. + */ + err = fat_dir_empty(inode); + if (err) + goto out; + err = msdos_find(dir, dentry->d_name.name, dentry->d_name.len, &sinfo); + if (err) + goto out; + + err = fat_remove_entries(dir, &sinfo); /* and releases bh */ + if (err) + goto out; + drop_nlink(dir); + + clear_nlink(inode); + inode->i_ctime = CURRENT_TIME_SEC; + fat_detach(inode); +out: + unlock_super(sb); + if (!err) + err = fat_flush_inodes(sb, dir, inode); + + return err; +} + +/***** Make a directory */ +static int msdos_mkdir(struct inode *dir, struct dentry *dentry, int mode) +{ + struct super_block *sb = dir->i_sb; + struct fat_slot_info sinfo; + struct inode *inode; + unsigned char msdos_name[MSDOS_NAME]; + struct timespec ts; + int err, is_hid, cluster; + + lock_super(sb); + + err = msdos_format_name(dentry->d_name.name, dentry->d_name.len, + msdos_name, &MSDOS_SB(sb)->options); + if (err) + goto out; + is_hid = (dentry->d_name.name[0] == '.') && (msdos_name[0] != '.'); + /* foo vs .foo situation */ + if (!fat_scan(dir, msdos_name, &sinfo)) { + brelse(sinfo.bh); + err = -EINVAL; + goto out; + } + + ts = CURRENT_TIME_SEC; + cluster = fat_alloc_new_dir(dir, &ts); + if (cluster < 0) { + err = cluster; + goto out; + } + err = msdos_add_entry(dir, msdos_name, 1, is_hid, cluster, &ts, &sinfo); + if (err) + goto out_free; + inc_nlink(dir); + + inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); + brelse(sinfo.bh); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + /* the directory was completed, just return a error */ + goto out; + } + inode->i_nlink = 2; + inode->i_mtime = inode->i_atime = inode->i_ctime = ts; + /* timestamp is already written, so mark_inode_dirty() is unneeded. */ + + d_instantiate(dentry, inode); + + unlock_super(sb); + fat_flush_inodes(sb, dir, inode); + return 0; + +out_free: + fat_free_clusters(dir, cluster); +out: + unlock_super(sb); + return err; +} + +/***** Unlink a file */ +static int msdos_unlink(struct inode *dir, struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + struct super_block *sb= inode->i_sb; + struct fat_slot_info sinfo; + int err; + + lock_super(sb); + err = msdos_find(dir, dentry->d_name.name, dentry->d_name.len, &sinfo); + if (err) + goto out; + + err = fat_remove_entries(dir, &sinfo); /* and releases bh */ + if (err) + goto out; + clear_nlink(inode); + inode->i_ctime = CURRENT_TIME_SEC; + fat_detach(inode); +out: + unlock_super(sb); + if (!err) + err = fat_flush_inodes(sb, dir, inode); + + return err; +} + +static int do_msdos_rename(struct inode *old_dir, unsigned char *old_name, + struct dentry *old_dentry, + struct inode *new_dir, unsigned char *new_name, + struct dentry *new_dentry, int is_hid) +{ + struct buffer_head *dotdot_bh; + struct msdos_dir_entry *dotdot_de; + struct inode *old_inode, *new_inode; + struct fat_slot_info old_sinfo, sinfo; + struct timespec ts; + loff_t dotdot_i_pos, new_i_pos; + int err, old_attrs, is_dir, update_dotdot, corrupt = 0; + + old_sinfo.bh = sinfo.bh = dotdot_bh = NULL; + old_inode = old_dentry->d_inode; + new_inode = new_dentry->d_inode; + + err = fat_scan(old_dir, old_name, &old_sinfo); + if (err) { + err = -EIO; + goto out; + } + + is_dir = S_ISDIR(old_inode->i_mode); + update_dotdot = (is_dir && old_dir != new_dir); + if (update_dotdot) { + if (fat_get_dotdot_entry(old_inode, &dotdot_bh, &dotdot_de, + &dotdot_i_pos) < 0) { + err = -EIO; + goto out; + } + } + + old_attrs = MSDOS_I(old_inode)->i_attrs; + err = fat_scan(new_dir, new_name, &sinfo); + if (!err) { + if (!new_inode) { + /* "foo" -> ".foo" case. just change the ATTR_HIDDEN */ + if (sinfo.de != old_sinfo.de) { + err = -EINVAL; + goto out; + } + if (is_hid) + MSDOS_I(old_inode)->i_attrs |= ATTR_HIDDEN; + else + MSDOS_I(old_inode)->i_attrs &= ~ATTR_HIDDEN; + if (IS_DIRSYNC(old_dir)) { + err = fat_sync_inode(old_inode); + if (err) { + MSDOS_I(old_inode)->i_attrs = old_attrs; + goto out; + } + } else + mark_inode_dirty(old_inode); + + old_dir->i_version++; + old_dir->i_ctime = old_dir->i_mtime = CURRENT_TIME_SEC; + if (IS_DIRSYNC(old_dir)) + (void)fat_sync_inode(old_dir); + else + mark_inode_dirty(old_dir); + goto out; + } + } + + ts = CURRENT_TIME_SEC; + if (new_inode) { + if (err) + goto out; + if (is_dir) { + err = fat_dir_empty(new_inode); + if (err) + goto out; + } + new_i_pos = MSDOS_I(new_inode)->i_pos; + fat_detach(new_inode); + } else { + err = msdos_add_entry(new_dir, new_name, is_dir, is_hid, 0, + &ts, &sinfo); + if (err) + goto out; + new_i_pos = sinfo.i_pos; + } + new_dir->i_version++; + + fat_detach(old_inode); + fat_attach(old_inode, new_i_pos); + if (is_hid) + MSDOS_I(old_inode)->i_attrs |= ATTR_HIDDEN; + else + MSDOS_I(old_inode)->i_attrs &= ~ATTR_HIDDEN; + if (IS_DIRSYNC(new_dir)) { + err = fat_sync_inode(old_inode); + if (err) + goto error_inode; + } else + mark_inode_dirty(old_inode); + + if (update_dotdot) { + int start = MSDOS_I(new_dir)->i_logstart; + dotdot_de->start = cpu_to_le16(start); + dotdot_de->starthi = cpu_to_le16(start >> 16); + mark_buffer_dirty(dotdot_bh); + if (IS_DIRSYNC(new_dir)) { + err = sync_dirty_buffer(dotdot_bh); + if (err) + goto error_dotdot; + } + drop_nlink(old_dir); + if (!new_inode) + inc_nlink(new_dir); + } + + err = fat_remove_entries(old_dir, &old_sinfo); /* and releases bh */ + old_sinfo.bh = NULL; + if (err) + goto error_dotdot; + old_dir->i_version++; + old_dir->i_ctime = old_dir->i_mtime = ts; + if (IS_DIRSYNC(old_dir)) + (void)fat_sync_inode(old_dir); + else + mark_inode_dirty(old_dir); + + if (new_inode) { + drop_nlink(new_inode); + if (is_dir) + drop_nlink(new_inode); + new_inode->i_ctime = ts; + } +out: + brelse(sinfo.bh); + brelse(dotdot_bh); + brelse(old_sinfo.bh); + return err; + +error_dotdot: + /* data cluster is shared, serious corruption */ + corrupt = 1; + + if (update_dotdot) { + int start = MSDOS_I(old_dir)->i_logstart; + dotdot_de->start = cpu_to_le16(start); + dotdot_de->starthi = cpu_to_le16(start >> 16); + mark_buffer_dirty(dotdot_bh); + corrupt |= sync_dirty_buffer(dotdot_bh); + } +error_inode: + fat_detach(old_inode); + fat_attach(old_inode, old_sinfo.i_pos); + MSDOS_I(old_inode)->i_attrs = old_attrs; + if (new_inode) { + fat_attach(new_inode, new_i_pos); + if (corrupt) + corrupt |= fat_sync_inode(new_inode); + } else { + /* + * If new entry was not sharing the data cluster, it + * shouldn't be serious corruption. + */ + int err2 = fat_remove_entries(new_dir, &sinfo); + if (corrupt) + corrupt |= err2; + sinfo.bh = NULL; + } + if (corrupt < 0) { + fat_fs_panic(new_dir->i_sb, + "%s: Filesystem corrupted (i_pos %lld)", + __func__, sinfo.i_pos); + } + goto out; +} + +/***** Rename, a wrapper for rename_same_dir & rename_diff_dir */ +static int msdos_rename(struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry) +{ + struct super_block *sb = old_dir->i_sb; + unsigned char old_msdos_name[MSDOS_NAME], new_msdos_name[MSDOS_NAME]; + int err, is_hid; + + lock_super(sb); + + err = msdos_format_name(old_dentry->d_name.name, + old_dentry->d_name.len, old_msdos_name, + &MSDOS_SB(old_dir->i_sb)->options); + if (err) + goto out; + err = msdos_format_name(new_dentry->d_name.name, + new_dentry->d_name.len, new_msdos_name, + &MSDOS_SB(new_dir->i_sb)->options); + if (err) + goto out; + + is_hid = + (new_dentry->d_name.name[0] == '.') && (new_msdos_name[0] != '.'); + + err = do_msdos_rename(old_dir, old_msdos_name, old_dentry, + new_dir, new_msdos_name, new_dentry, is_hid); +out: + unlock_super(sb); + if (!err) + err = fat_flush_inodes(sb, old_dir, new_dir); + return err; +} + +static const struct inode_operations msdos_dir_inode_operations = { + .create = msdos_create, + .lookup = msdos_lookup, + .unlink = msdos_unlink, + .mkdir = msdos_mkdir, + .rmdir = msdos_rmdir, + .rename = msdos_rename, + .setattr = fat_setattr, + .getattr = fat_getattr, +}; + +static int msdos_fill_super(struct super_block *sb, void *data, int silent) +{ + int res; + + res = fat_fill_super(sb, data, silent, &msdos_dir_inode_operations, 0); + if (res) + return res; + + sb->s_flags |= MS_NOATIME; + sb->s_root->d_op = &msdos_dentry_operations; + return 0; +} + +static int msdos_get_sb(struct file_system_type *fs_type, + int flags, const char *dev_name, + void *data, struct vfsmount *mnt) +{ + return get_sb_bdev(fs_type, flags, dev_name, data, msdos_fill_super, + mnt); +} + +static struct file_system_type msdos_fs_type = { + .owner = THIS_MODULE, + .name = "msdos", + .get_sb = msdos_get_sb, + .kill_sb = kill_block_super, + .fs_flags = FS_REQUIRES_DEV, +}; + +static int __init init_msdos_fs(void) +{ + return register_filesystem(&msdos_fs_type); +} + +static void __exit exit_msdos_fs(void) +{ + unregister_filesystem(&msdos_fs_type); +} + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Werner Almesberger"); +MODULE_DESCRIPTION("MS-DOS filesystem support"); + +module_init(init_msdos_fs) +module_exit(exit_msdos_fs) diff --git a/fs/fat/namei_vfat.c b/fs/fat/namei_vfat.c new file mode 100644 index 000000000000..bf326d4356a3 --- /dev/null +++ b/fs/fat/namei_vfat.c @@ -0,0 +1,1098 @@ +/* + * linux/fs/vfat/namei.c + * + * Written 1992,1993 by Werner Almesberger + * + * Windows95/Windows NT compatible extended MSDOS filesystem + * by Gordon Chaffee Copyright (C) 1995. Send bug reports for the + * VFAT filesystem to . Specify + * what file operation caused you trouble and if you can duplicate + * the problem, send a script that demonstrates it. + * + * Short name translation 1999, 2001 by Wolfram Pienkoss + * + * Support Multibyte characters and cleanup by + * OGAWA Hirofumi + */ + +#include +#include +#include +#include +#include +#include +#include +#include "fat.h" + +/* + * If new entry was created in the parent, it could create the 8.3 + * alias (the shortname of logname). So, the parent may have the + * negative-dentry which matches the created 8.3 alias. + * + * If it happened, the negative dentry isn't actually negative + * anymore. So, drop it. + */ +static int vfat_revalidate_shortname(struct dentry *dentry) +{ + int ret = 1; + spin_lock(&dentry->d_lock); + if (dentry->d_time != dentry->d_parent->d_inode->i_version) + ret = 0; + spin_unlock(&dentry->d_lock); + return ret; +} + +static int vfat_revalidate(struct dentry *dentry, struct nameidata *nd) +{ + /* This is not negative dentry. Always valid. */ + if (dentry->d_inode) + return 1; + return vfat_revalidate_shortname(dentry); +} + +static int vfat_revalidate_ci(struct dentry *dentry, struct nameidata *nd) +{ + /* + * This is not negative dentry. Always valid. + * + * Note, rename() to existing directory entry will have ->d_inode, + * and will use existing name which isn't specified name by user. + * + * We may be able to drop this positive dentry here. But dropping + * positive dentry isn't good idea. So it's unsupported like + * rename("filename", "FILENAME") for now. + */ + if (dentry->d_inode) + return 1; + + /* + * This may be nfsd (or something), anyway, we can't see the + * intent of this. So, since this can be for creation, drop it. + */ + if (!nd) + return 0; + + /* + * Drop the negative dentry, in order to make sure to use the + * case sensitive name which is specified by user if this is + * for creation. + */ + if (!(nd->flags & (LOOKUP_CONTINUE | LOOKUP_PARENT))) { + if (nd->flags & LOOKUP_CREATE) + return 0; + } + + return vfat_revalidate_shortname(dentry); +} + +/* returns the length of a struct qstr, ignoring trailing dots */ +static unsigned int vfat_striptail_len(struct qstr *qstr) +{ + unsigned int len = qstr->len; + + while (len && qstr->name[len - 1] == '.') + len--; + return len; +} + +/* + * Compute the hash for the vfat name corresponding to the dentry. + * Note: if the name is invalid, we leave the hash code unchanged so + * that the existing dentry can be used. The vfat fs routines will + * return ENOENT or EINVAL as appropriate. + */ +static int vfat_hash(struct dentry *dentry, struct qstr *qstr) +{ + qstr->hash = full_name_hash(qstr->name, vfat_striptail_len(qstr)); + return 0; +} + +/* + * Compute the hash for the vfat name corresponding to the dentry. + * Note: if the name is invalid, we leave the hash code unchanged so + * that the existing dentry can be used. The vfat fs routines will + * return ENOENT or EINVAL as appropriate. + */ +static int vfat_hashi(struct dentry *dentry, struct qstr *qstr) +{ + struct nls_table *t = MSDOS_SB(dentry->d_inode->i_sb)->nls_io; + const unsigned char *name; + unsigned int len; + unsigned long hash; + + name = qstr->name; + len = vfat_striptail_len(qstr); + + hash = init_name_hash(); + while (len--) + hash = partial_name_hash(nls_tolower(t, *name++), hash); + qstr->hash = end_name_hash(hash); + + return 0; +} + +/* + * Case insensitive compare of two vfat names. + */ +static int vfat_cmpi(struct dentry *dentry, struct qstr *a, struct qstr *b) +{ + struct nls_table *t = MSDOS_SB(dentry->d_inode->i_sb)->nls_io; + unsigned int alen, blen; + + /* A filename cannot end in '.' or we treat it like it has none */ + alen = vfat_striptail_len(a); + blen = vfat_striptail_len(b); + if (alen == blen) { + if (nls_strnicmp(t, a->name, b->name, alen) == 0) + return 0; + } + return 1; +} + +/* + * Case sensitive compare of two vfat names. + */ +static int vfat_cmp(struct dentry *dentry, struct qstr *a, struct qstr *b) +{ + unsigned int alen, blen; + + /* A filename cannot end in '.' or we treat it like it has none */ + alen = vfat_striptail_len(a); + blen = vfat_striptail_len(b); + if (alen == blen) { + if (strncmp(a->name, b->name, alen) == 0) + return 0; + } + return 1; +} + +static struct dentry_operations vfat_ci_dentry_ops = { + .d_revalidate = vfat_revalidate_ci, + .d_hash = vfat_hashi, + .d_compare = vfat_cmpi, +}; + +static struct dentry_operations vfat_dentry_ops = { + .d_revalidate = vfat_revalidate, + .d_hash = vfat_hash, + .d_compare = vfat_cmp, +}; + +/* Characters that are undesirable in an MS-DOS file name */ + +static inline wchar_t vfat_bad_char(wchar_t w) +{ + return (w < 0x0020) + || (w == '*') || (w == '?') || (w == '<') || (w == '>') + || (w == '|') || (w == '"') || (w == ':') || (w == '/') + || (w == '\\'); +} + +static inline wchar_t vfat_replace_char(wchar_t w) +{ + return (w == '[') || (w == ']') || (w == ';') || (w == ',') + || (w == '+') || (w == '='); +} + +static wchar_t vfat_skip_char(wchar_t w) +{ + return (w == '.') || (w == ' '); +} + +static inline int vfat_is_used_badchars(const wchar_t *s, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (vfat_bad_char(s[i])) + return -EINVAL; + + if (s[i - 1] == ' ') /* last character cannot be space */ + return -EINVAL; + + return 0; +} + +static int vfat_find_form(struct inode *dir, unsigned char *name) +{ + struct fat_slot_info sinfo; + int err = fat_scan(dir, name, &sinfo); + if (err) + return -ENOENT; + brelse(sinfo.bh); + return 0; +} + +/* + * 1) Valid characters for the 8.3 format alias are any combination of + * letters, uppercase alphabets, digits, any of the + * following special characters: + * $ % ' ` - @ { } ~ ! # ( ) & _ ^ + * In this case Longfilename is not stored in disk. + * + * WinNT's Extension: + * File name and extension name is contain uppercase/lowercase + * only. And it is expressed by CASE_LOWER_BASE and CASE_LOWER_EXT. + * + * 2) File name is 8.3 format, but it contain the uppercase and + * lowercase char, muliti bytes char, etc. In this case numtail is not + * added, but Longfilename is stored. + * + * 3) When the one except for the above, or the following special + * character are contained: + * . [ ] ; , + = + * numtail is added, and Longfilename must be stored in disk . + */ +struct shortname_info { + unsigned char lower:1, + upper:1, + valid:1; +}; +#define INIT_SHORTNAME_INFO(x) do { \ + (x)->lower = 1; \ + (x)->upper = 1; \ + (x)->valid = 1; \ +} while (0) + +static inline int to_shortname_char(struct nls_table *nls, + unsigned char *buf, int buf_size, + wchar_t *src, struct shortname_info *info) +{ + int len; + + if (vfat_skip_char(*src)) { + info->valid = 0; + return 0; + } + if (vfat_replace_char(*src)) { + info->valid = 0; + buf[0] = '_'; + return 1; + } + + len = nls->uni2char(*src, buf, buf_size); + if (len <= 0) { + info->valid = 0; + buf[0] = '_'; + len = 1; + } else if (len == 1) { + unsigned char prev = buf[0]; + + if (buf[0] >= 0x7F) { + info->lower = 0; + info->upper = 0; + } + + buf[0] = nls_toupper(nls, buf[0]); + if (isalpha(buf[0])) { + if (buf[0] == prev) + info->lower = 0; + else + info->upper = 0; + } + } else { + info->lower = 0; + info->upper = 0; + } + + return len; +} + +/* + * Given a valid longname, create a unique shortname. Make sure the + * shortname does not exist + * Returns negative number on error, 0 for a normal + * return, and 1 for valid shortname + */ +static int vfat_create_shortname(struct inode *dir, struct nls_table *nls, + wchar_t *uname, int ulen, + unsigned char *name_res, unsigned char *lcase) +{ + struct fat_mount_options *opts = &MSDOS_SB(dir->i_sb)->options; + wchar_t *ip, *ext_start, *end, *name_start; + unsigned char base[9], ext[4], buf[8], *p; + unsigned char charbuf[NLS_MAX_CHARSET_SIZE]; + int chl, chi; + int sz = 0, extlen, baselen, i, numtail_baselen, numtail2_baselen; + int is_shortname; + struct shortname_info base_info, ext_info; + + is_shortname = 1; + INIT_SHORTNAME_INFO(&base_info); + INIT_SHORTNAME_INFO(&ext_info); + + /* Now, we need to create a shortname from the long name */ + ext_start = end = &uname[ulen]; + while (--ext_start >= uname) { + if (*ext_start == 0x002E) { /* is `.' */ + if (ext_start == end - 1) { + sz = ulen; + ext_start = NULL; + } + break; + } + } + + if (ext_start == uname - 1) { + sz = ulen; + ext_start = NULL; + } else if (ext_start) { + /* + * Names which start with a dot could be just + * an extension eg. "...test". In this case Win95 + * uses the extension as the name and sets no extension. + */ + name_start = &uname[0]; + while (name_start < ext_start) { + if (!vfat_skip_char(*name_start)) + break; + name_start++; + } + if (name_start != ext_start) { + sz = ext_start - uname; + ext_start++; + } else { + sz = ulen; + ext_start = NULL; + } + } + + numtail_baselen = 6; + numtail2_baselen = 2; + for (baselen = i = 0, p = base, ip = uname; i < sz; i++, ip++) { + chl = to_shortname_char(nls, charbuf, sizeof(charbuf), + ip, &base_info); + if (chl == 0) + continue; + + if (baselen < 2 && (baselen + chl) > 2) + numtail2_baselen = baselen; + if (baselen < 6 && (baselen + chl) > 6) + numtail_baselen = baselen; + for (chi = 0; chi < chl; chi++) { + *p++ = charbuf[chi]; + baselen++; + if (baselen >= 8) + break; + } + if (baselen >= 8) { + if ((chi < chl - 1) || (ip + 1) - uname < sz) + is_shortname = 0; + break; + } + } + if (baselen == 0) { + return -EINVAL; + } + + extlen = 0; + if (ext_start) { + for (p = ext, ip = ext_start; extlen < 3 && ip < end; ip++) { + chl = to_shortname_char(nls, charbuf, sizeof(charbuf), + ip, &ext_info); + if (chl == 0) + continue; + + if ((extlen + chl) > 3) { + is_shortname = 0; + break; + } + for (chi = 0; chi < chl; chi++) { + *p++ = charbuf[chi]; + extlen++; + } + if (extlen >= 3) { + if (ip + 1 != end) + is_shortname = 0; + break; + } + } + } + ext[extlen] = '\0'; + base[baselen] = '\0'; + + /* Yes, it can happen. ".\xe5" would do it. */ + if (base[0] == DELETED_FLAG) + base[0] = 0x05; + + /* OK, at this point we know that base is not longer than 8 symbols, + * ext is not longer than 3, base is nonempty, both don't contain + * any bad symbols (lowercase transformed to uppercase). + */ + + memset(name_res, ' ', MSDOS_NAME); + memcpy(name_res, base, baselen); + memcpy(name_res + 8, ext, extlen); + *lcase = 0; + if (is_shortname && base_info.valid && ext_info.valid) { + if (vfat_find_form(dir, name_res) == 0) + return -EEXIST; + + if (opts->shortname & VFAT_SFN_CREATE_WIN95) { + return (base_info.upper && ext_info.upper); + } else if (opts->shortname & VFAT_SFN_CREATE_WINNT) { + if ((base_info.upper || base_info.lower) && + (ext_info.upper || ext_info.lower)) { + if (!base_info.upper && base_info.lower) + *lcase |= CASE_LOWER_BASE; + if (!ext_info.upper && ext_info.lower) + *lcase |= CASE_LOWER_EXT; + return 1; + } + return 0; + } else { + BUG(); + } + } + + if (opts->numtail == 0) + if (vfat_find_form(dir, name_res) < 0) + return 0; + + /* + * Try to find a unique extension. This used to + * iterate through all possibilities sequentially, + * but that gave extremely bad performance. Windows + * only tries a few cases before using random + * values for part of the base. + */ + + if (baselen > 6) { + baselen = numtail_baselen; + name_res[7] = ' '; + } + name_res[baselen] = '~'; + for (i = 1; i < 10; i++) { + name_res[baselen + 1] = i + '0'; + if (vfat_find_form(dir, name_res) < 0) + return 0; + } + + i = jiffies & 0xffff; + sz = (jiffies >> 16) & 0x7; + if (baselen > 2) { + baselen = numtail2_baselen; + name_res[7] = ' '; + } + name_res[baselen + 4] = '~'; + name_res[baselen + 5] = '1' + sz; + while (1) { + sprintf(buf, "%04X", i); + memcpy(&name_res[baselen], buf, 4); + if (vfat_find_form(dir, name_res) < 0) + break; + i -= 11; + } + return 0; +} + +/* Translate a string, including coded sequences into Unicode */ +static int +xlate_to_uni(const unsigned char *name, int len, unsigned char *outname, + int *longlen, int *outlen, int escape, int utf8, + struct nls_table *nls) +{ + const unsigned char *ip; + unsigned char nc; + unsigned char *op; + unsigned int ec; + int i, k, fill; + int charlen; + + if (utf8) { + int name_len = strlen(name); + + *outlen = utf8_mbstowcs((wchar_t *)outname, name, PATH_MAX); + + /* + * We stripped '.'s before and set len appropriately, + * but utf8_mbstowcs doesn't care about len + */ + *outlen -= (name_len - len); + + if (*outlen > 255) + return -ENAMETOOLONG; + + op = &outname[*outlen * sizeof(wchar_t)]; + } else { + if (nls) { + for (i = 0, ip = name, op = outname, *outlen = 0; + i < len && *outlen <= 255; + *outlen += 1) + { + if (escape && (*ip == ':')) { + if (i > len - 5) + return -EINVAL; + ec = 0; + for (k = 1; k < 5; k++) { + nc = ip[k]; + ec <<= 4; + if (nc >= '0' && nc <= '9') { + ec |= nc - '0'; + continue; + } + if (nc >= 'a' && nc <= 'f') { + ec |= nc - ('a' - 10); + continue; + } + if (nc >= 'A' && nc <= 'F') { + ec |= nc - ('A' - 10); + continue; + } + return -EINVAL; + } + *op++ = ec & 0xFF; + *op++ = ec >> 8; + ip += 5; + i += 5; + } else { + if ((charlen = nls->char2uni(ip, len - i, (wchar_t *)op)) < 0) + return -EINVAL; + ip += charlen; + i += charlen; + op += 2; + } + } + if (i < len) + return -ENAMETOOLONG; + } else { + for (i = 0, ip = name, op = outname, *outlen = 0; + i < len && *outlen <= 255; + i++, *outlen += 1) + { + *op++ = *ip++; + *op++ = 0; + } + if (i < len) + return -ENAMETOOLONG; + } + } + + *longlen = *outlen; + if (*outlen % 13) { + *op++ = 0; + *op++ = 0; + *outlen += 1; + if (*outlen % 13) { + fill = 13 - (*outlen % 13); + for (i = 0; i < fill; i++) { + *op++ = 0xff; + *op++ = 0xff; + } + *outlen += fill; + } + } + + return 0; +} + +static int vfat_build_slots(struct inode *dir, const unsigned char *name, + int len, int is_dir, int cluster, + struct timespec *ts, + struct msdos_dir_slot *slots, int *nr_slots) +{ + struct msdos_sb_info *sbi = MSDOS_SB(dir->i_sb); + struct fat_mount_options *opts = &sbi->options; + struct msdos_dir_slot *ps; + struct msdos_dir_entry *de; + unsigned char cksum, lcase; + unsigned char msdos_name[MSDOS_NAME]; + wchar_t *uname; + __le16 time, date; + u8 time_cs; + int err, ulen, usize, i; + loff_t offset; + + *nr_slots = 0; + + uname = __getname(); + if (!uname) + return -ENOMEM; + + err = xlate_to_uni(name, len, (unsigned char *)uname, &ulen, &usize, + opts->unicode_xlate, opts->utf8, sbi->nls_io); + if (err) + goto out_free; + + err = vfat_is_used_badchars(uname, ulen); + if (err) + goto out_free; + + err = vfat_create_shortname(dir, sbi->nls_disk, uname, ulen, + msdos_name, &lcase); + if (err < 0) + goto out_free; + else if (err == 1) { + de = (struct msdos_dir_entry *)slots; + err = 0; + goto shortname; + } + + /* build the entry of long file name */ + cksum = fat_checksum(msdos_name); + + *nr_slots = usize / 13; + for (ps = slots, i = *nr_slots; i > 0; i--, ps++) { + ps->id = i; + ps->attr = ATTR_EXT; + ps->reserved = 0; + ps->alias_checksum = cksum; + ps->start = 0; + offset = (i - 1) * 13; + fatwchar_to16(ps->name0_4, uname + offset, 5); + fatwchar_to16(ps->name5_10, uname + offset + 5, 6); + fatwchar_to16(ps->name11_12, uname + offset + 11, 2); + } + slots[0].id |= 0x40; + de = (struct msdos_dir_entry *)ps; + +shortname: + /* build the entry of 8.3 alias name */ + (*nr_slots)++; + memcpy(de->name, msdos_name, MSDOS_NAME); + de->attr = is_dir ? ATTR_DIR : ATTR_ARCH; + de->lcase = lcase; + fat_time_unix2fat(sbi, ts, &time, &date, &time_cs); + de->time = de->ctime = time; + de->date = de->cdate = de->adate = date; + de->ctime_cs = time_cs; + de->start = cpu_to_le16(cluster); + de->starthi = cpu_to_le16(cluster >> 16); + de->size = 0; +out_free: + __putname(uname); + return err; +} + +static int vfat_add_entry(struct inode *dir, struct qstr *qname, int is_dir, + int cluster, struct timespec *ts, + struct fat_slot_info *sinfo) +{ + struct msdos_dir_slot *slots; + unsigned int len; + int err, nr_slots; + + len = vfat_striptail_len(qname); + if (len == 0) + return -ENOENT; + + slots = kmalloc(sizeof(*slots) * MSDOS_SLOTS, GFP_NOFS); + if (slots == NULL) + return -ENOMEM; + + err = vfat_build_slots(dir, qname->name, len, is_dir, cluster, ts, + slots, &nr_slots); + if (err) + goto cleanup; + + err = fat_add_entries(dir, slots, nr_slots, sinfo); + if (err) + goto cleanup; + + /* update timestamp */ + dir->i_ctime = dir->i_mtime = dir->i_atime = *ts; + if (IS_DIRSYNC(dir)) + (void)fat_sync_inode(dir); + else + mark_inode_dirty(dir); +cleanup: + kfree(slots); + return err; +} + +static int vfat_find(struct inode *dir, struct qstr *qname, + struct fat_slot_info *sinfo) +{ + unsigned int len = vfat_striptail_len(qname); + if (len == 0) + return -ENOENT; + return fat_search_long(dir, qname->name, len, sinfo); +} + +static struct dentry *vfat_lookup(struct inode *dir, struct dentry *dentry, + struct nameidata *nd) +{ + struct super_block *sb = dir->i_sb; + struct fat_slot_info sinfo; + struct inode *inode; + struct dentry *alias; + int err; + + lock_super(sb); + + err = vfat_find(dir, &dentry->d_name, &sinfo); + if (err) { + if (err == -ENOENT) { + inode = NULL; + goto out; + } + goto error; + } + + inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); + brelse(sinfo.bh); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + goto error; + } + + alias = d_find_alias(inode); + if (alias && !(alias->d_flags & DCACHE_DISCONNECTED)) { + /* + * This inode has non DCACHE_DISCONNECTED dentry. This + * means, the user did ->lookup() by an another name + * (longname vs 8.3 alias of it) in past. + * + * Switch to new one for reason of locality if possible. + */ + BUG_ON(d_unhashed(alias)); + if (!S_ISDIR(inode->i_mode)) + d_move(alias, dentry); + iput(inode); + unlock_super(sb); + return alias; + } +out: + unlock_super(sb); + dentry->d_op = sb->s_root->d_op; + dentry->d_time = dentry->d_parent->d_inode->i_version; + dentry = d_splice_alias(inode, dentry); + if (dentry) { + dentry->d_op = sb->s_root->d_op; + dentry->d_time = dentry->d_parent->d_inode->i_version; + } + return dentry; + +error: + unlock_super(sb); + return ERR_PTR(err); +} + +static int vfat_create(struct inode *dir, struct dentry *dentry, int mode, + struct nameidata *nd) +{ + struct super_block *sb = dir->i_sb; + struct inode *inode; + struct fat_slot_info sinfo; + struct timespec ts; + int err; + + lock_super(sb); + + ts = CURRENT_TIME_SEC; + err = vfat_add_entry(dir, &dentry->d_name, 0, 0, &ts, &sinfo); + if (err) + goto out; + dir->i_version++; + + inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); + brelse(sinfo.bh); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + goto out; + } + inode->i_version++; + inode->i_mtime = inode->i_atime = inode->i_ctime = ts; + /* timestamp is already written, so mark_inode_dirty() is unneeded. */ + + dentry->d_time = dentry->d_parent->d_inode->i_version; + d_instantiate(dentry, inode); +out: + unlock_super(sb); + return err; +} + +static int vfat_rmdir(struct inode *dir, struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + struct super_block *sb = dir->i_sb; + struct fat_slot_info sinfo; + int err; + + lock_super(sb); + + err = fat_dir_empty(inode); + if (err) + goto out; + err = vfat_find(dir, &dentry->d_name, &sinfo); + if (err) + goto out; + + err = fat_remove_entries(dir, &sinfo); /* and releases bh */ + if (err) + goto out; + drop_nlink(dir); + + clear_nlink(inode); + inode->i_mtime = inode->i_atime = CURRENT_TIME_SEC; + fat_detach(inode); +out: + unlock_super(sb); + + return err; +} + +static int vfat_unlink(struct inode *dir, struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + struct super_block *sb = dir->i_sb; + struct fat_slot_info sinfo; + int err; + + lock_super(sb); + + err = vfat_find(dir, &dentry->d_name, &sinfo); + if (err) + goto out; + + err = fat_remove_entries(dir, &sinfo); /* and releases bh */ + if (err) + goto out; + clear_nlink(inode); + inode->i_mtime = inode->i_atime = CURRENT_TIME_SEC; + fat_detach(inode); +out: + unlock_super(sb); + + return err; +} + +static int vfat_mkdir(struct inode *dir, struct dentry *dentry, int mode) +{ + struct super_block *sb = dir->i_sb; + struct inode *inode; + struct fat_slot_info sinfo; + struct timespec ts; + int err, cluster; + + lock_super(sb); + + ts = CURRENT_TIME_SEC; + cluster = fat_alloc_new_dir(dir, &ts); + if (cluster < 0) { + err = cluster; + goto out; + } + err = vfat_add_entry(dir, &dentry->d_name, 1, cluster, &ts, &sinfo); + if (err) + goto out_free; + dir->i_version++; + inc_nlink(dir); + + inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); + brelse(sinfo.bh); + if (IS_ERR(inode)) { + err = PTR_ERR(inode); + /* the directory was completed, just return a error */ + goto out; + } + inode->i_version++; + inode->i_nlink = 2; + inode->i_mtime = inode->i_atime = inode->i_ctime = ts; + /* timestamp is already written, so mark_inode_dirty() is unneeded. */ + + dentry->d_time = dentry->d_parent->d_inode->i_version; + d_instantiate(dentry, inode); + + unlock_super(sb); + return 0; + +out_free: + fat_free_clusters(dir, cluster); +out: + unlock_super(sb); + return err; +} + +static int vfat_rename(struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry) +{ + struct buffer_head *dotdot_bh; + struct msdos_dir_entry *dotdot_de; + struct inode *old_inode, *new_inode; + struct fat_slot_info old_sinfo, sinfo; + struct timespec ts; + loff_t dotdot_i_pos, new_i_pos; + int err, is_dir, update_dotdot, corrupt = 0; + struct super_block *sb = old_dir->i_sb; + + old_sinfo.bh = sinfo.bh = dotdot_bh = NULL; + old_inode = old_dentry->d_inode; + new_inode = new_dentry->d_inode; + lock_super(sb); + err = vfat_find(old_dir, &old_dentry->d_name, &old_sinfo); + if (err) + goto out; + + is_dir = S_ISDIR(old_inode->i_mode); + update_dotdot = (is_dir && old_dir != new_dir); + if (update_dotdot) { + if (fat_get_dotdot_entry(old_inode, &dotdot_bh, &dotdot_de, + &dotdot_i_pos) < 0) { + err = -EIO; + goto out; + } + } + + ts = CURRENT_TIME_SEC; + if (new_inode) { + if (is_dir) { + err = fat_dir_empty(new_inode); + if (err) + goto out; + } + new_i_pos = MSDOS_I(new_inode)->i_pos; + fat_detach(new_inode); + } else { + err = vfat_add_entry(new_dir, &new_dentry->d_name, is_dir, 0, + &ts, &sinfo); + if (err) + goto out; + new_i_pos = sinfo.i_pos; + } + new_dir->i_version++; + + fat_detach(old_inode); + fat_attach(old_inode, new_i_pos); + if (IS_DIRSYNC(new_dir)) { + err = fat_sync_inode(old_inode); + if (err) + goto error_inode; + } else + mark_inode_dirty(old_inode); + + if (update_dotdot) { + int start = MSDOS_I(new_dir)->i_logstart; + dotdot_de->start = cpu_to_le16(start); + dotdot_de->starthi = cpu_to_le16(start >> 16); + mark_buffer_dirty(dotdot_bh); + if (IS_DIRSYNC(new_dir)) { + err = sync_dirty_buffer(dotdot_bh); + if (err) + goto error_dotdot; + } + drop_nlink(old_dir); + if (!new_inode) + inc_nlink(new_dir); + } + + err = fat_remove_entries(old_dir, &old_sinfo); /* and releases bh */ + old_sinfo.bh = NULL; + if (err) + goto error_dotdot; + old_dir->i_version++; + old_dir->i_ctime = old_dir->i_mtime = ts; + if (IS_DIRSYNC(old_dir)) + (void)fat_sync_inode(old_dir); + else + mark_inode_dirty(old_dir); + + if (new_inode) { + drop_nlink(new_inode); + if (is_dir) + drop_nlink(new_inode); + new_inode->i_ctime = ts; + } +out: + brelse(sinfo.bh); + brelse(dotdot_bh); + brelse(old_sinfo.bh); + unlock_super(sb); + + return err; + +error_dotdot: + /* data cluster is shared, serious corruption */ + corrupt = 1; + + if (update_dotdot) { + int start = MSDOS_I(old_dir)->i_logstart; + dotdot_de->start = cpu_to_le16(start); + dotdot_de->starthi = cpu_to_le16(start >> 16); + mark_buffer_dirty(dotdot_bh); + corrupt |= sync_dirty_buffer(dotdot_bh); + } +error_inode: + fat_detach(old_inode); + fat_attach(old_inode, old_sinfo.i_pos); + if (new_inode) { + fat_attach(new_inode, new_i_pos); + if (corrupt) + corrupt |= fat_sync_inode(new_inode); + } else { + /* + * If new entry was not sharing the data cluster, it + * shouldn't be serious corruption. + */ + int err2 = fat_remove_entries(new_dir, &sinfo); + if (corrupt) + corrupt |= err2; + sinfo.bh = NULL; + } + if (corrupt < 0) { + fat_fs_panic(new_dir->i_sb, + "%s: Filesystem corrupted (i_pos %lld)", + __func__, sinfo.i_pos); + } + goto out; +} + +static const struct inode_operations vfat_dir_inode_operations = { + .create = vfat_create, + .lookup = vfat_lookup, + .unlink = vfat_unlink, + .mkdir = vfat_mkdir, + .rmdir = vfat_rmdir, + .rename = vfat_rename, + .setattr = fat_setattr, + .getattr = fat_getattr, +}; + +static int vfat_fill_super(struct super_block *sb, void *data, int silent) +{ + int res; + + res = fat_fill_super(sb, data, silent, &vfat_dir_inode_operations, 1); + if (res) + return res; + + if (MSDOS_SB(sb)->options.name_check != 's') + sb->s_root->d_op = &vfat_ci_dentry_ops; + else + sb->s_root->d_op = &vfat_dentry_ops; + + return 0; +} + +static int vfat_get_sb(struct file_system_type *fs_type, + int flags, const char *dev_name, + void *data, struct vfsmount *mnt) +{ + return get_sb_bdev(fs_type, flags, dev_name, data, vfat_fill_super, + mnt); +} + +static struct file_system_type vfat_fs_type = { + .owner = THIS_MODULE, + .name = "vfat", + .get_sb = vfat_get_sb, + .kill_sb = kill_block_super, + .fs_flags = FS_REQUIRES_DEV, +}; + +static int __init init_vfat_fs(void) +{ + return register_filesystem(&vfat_fs_type); +} + +static void __exit exit_vfat_fs(void) +{ + unregister_filesystem(&vfat_fs_type); +} + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("VFAT filesystem support"); +MODULE_AUTHOR("Gordon Chaffee"); + +module_init(init_vfat_fs) +module_exit(exit_vfat_fs) diff --git a/fs/fcntl.c b/fs/fcntl.c index ac4f7db9f134..549daf8005fb 100644 --- a/fs/fcntl.c +++ b/fs/fcntl.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -175,6 +176,11 @@ static int setfl(int fd, struct file * filp, unsigned long arg) if (error) return error; + /* + * We still need a lock here for now to keep multiple FASYNC calls + * from racing with each other. + */ + lock_kernel(); if ((arg ^ filp->f_flags) & FASYNC) { if (filp->f_op && filp->f_op->fasync) { error = filp->f_op->fasync(fd, filp, (arg & FASYNC) != 0); @@ -185,6 +191,7 @@ static int setfl(int fd, struct file * filp, unsigned long arg) filp->f_flags = (arg & SETFL_MASK) | (filp->f_flags & ~SETFL_MASK); out: + unlock_kernel(); return error; } diff --git a/fs/file_table.c b/fs/file_table.c index efc06faede6c..5ad0eca6eea2 100644 --- a/fs/file_table.c +++ b/fs/file_table.c @@ -269,6 +269,10 @@ void __fput(struct file *file) eventpoll_release(file); locks_remove_flock(file); + if (unlikely(file->f_flags & FASYNC)) { + if (file->f_op && file->f_op->fasync) + file->f_op->fasync(-1, file, 0); + } if (file->f_op && file->f_op->release) file->f_op->release(inode, file); security_file_free(file); diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index 87250b6a8682..b72361479be2 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -1056,7 +1056,6 @@ static int fuse_dev_release(struct inode *inode, struct file *file) end_requests(fc, &fc->pending); end_requests(fc, &fc->processing); spin_unlock(&fc->lock); - fasync_helper(-1, file, 0, &fc->fasync); fuse_conn_put(fc); } diff --git a/fs/hostfs/hostfs.h b/fs/hostfs/hostfs.h index 6ae9011b95eb..2f34f8f2134b 100644 --- a/fs/hostfs/hostfs.h +++ b/fs/hostfs/hostfs.h @@ -81,7 +81,7 @@ extern int do_rmdir(const char *file); extern int do_mknod(const char *file, int mode, unsigned int major, unsigned int minor); extern int link_file(const char *from, const char *to); -extern int do_readlink(char *file, char *buf, int size); +extern int hostfs_do_readlink(char *file, char *buf, int size); extern int rename_file(char *from, char *to); extern int do_statfs(char *root, long *bsize_out, long long *blocks_out, long long *bfree_out, long long *bavail_out, diff --git a/fs/hostfs/hostfs_kern.c b/fs/hostfs/hostfs_kern.c index 7f34f4385de0..3a31451ac170 100644 --- a/fs/hostfs/hostfs_kern.c +++ b/fs/hostfs/hostfs_kern.c @@ -168,7 +168,7 @@ static char *follow_link(char *link) if (name == NULL) goto out; - n = do_readlink(link, name, len); + n = hostfs_do_readlink(link, name, len); if (n < len) break; len *= 2; @@ -943,7 +943,7 @@ int hostfs_link_readpage(struct file *file, struct page *page) name = inode_name(page->mapping->host, 0); if (name == NULL) return -ENOMEM; - err = do_readlink(name, buffer, PAGE_CACHE_SIZE); + err = hostfs_do_readlink(name, buffer, PAGE_CACHE_SIZE); kfree(name); if (err == PAGE_CACHE_SIZE) err = -E2BIG; diff --git a/fs/hostfs/hostfs_user.c b/fs/hostfs/hostfs_user.c index 53fd0a67c11a..b79424f93282 100644 --- a/fs/hostfs/hostfs_user.c +++ b/fs/hostfs/hostfs_user.c @@ -377,7 +377,7 @@ int link_file(const char *to, const char *from) return 0; } -int do_readlink(char *file, char *buf, int size) +int hostfs_do_readlink(char *file, char *buf, int size) { int n; diff --git a/fs/inotify.c b/fs/inotify.c index 690e72595e6e..dae3f28f30d4 100644 --- a/fs/inotify.c +++ b/fs/inotify.c @@ -106,6 +106,20 @@ void get_inotify_watch(struct inotify_watch *watch) } EXPORT_SYMBOL_GPL(get_inotify_watch); +int pin_inotify_watch(struct inotify_watch *watch) +{ + struct super_block *sb = watch->inode->i_sb; + spin_lock(&sb_lock); + if (sb->s_count >= S_BIAS) { + atomic_inc(&sb->s_active); + spin_unlock(&sb_lock); + atomic_inc(&watch->count); + return 1; + } + spin_unlock(&sb_lock); + return 0; +} + /** * put_inotify_watch - decrements the ref count on a given watch. cleans up * watch references if the count reaches zero. inotify_watch is freed by @@ -124,6 +138,13 @@ void put_inotify_watch(struct inotify_watch *watch) } EXPORT_SYMBOL_GPL(put_inotify_watch); +void unpin_inotify_watch(struct inotify_watch *watch) +{ + struct super_block *sb = watch->inode->i_sb; + put_inotify_watch(watch); + deactivate_super(sb); +} + /* * inotify_handle_get_wd - returns the next WD for use by the given handle * @@ -407,11 +428,13 @@ void inotify_unmount_inodes(struct list_head *list) watches = &inode->inotify_watches; list_for_each_entry_safe(watch, next_w, watches, i_list) { struct inotify_handle *ih= watch->ih; + get_inotify_watch(watch); mutex_lock(&ih->mutex); ih->in_ops->handle_event(watch, watch->wd, IN_UNMOUNT, 0, NULL, NULL); inotify_remove_watch_locked(ih, watch); mutex_unlock(&ih->mutex); + put_inotify_watch(watch); } mutex_unlock(&inode->inotify_mutex); iput(inode); @@ -479,6 +502,112 @@ void inotify_init_watch(struct inotify_watch *watch) } EXPORT_SYMBOL_GPL(inotify_init_watch); +/* + * Watch removals suck violently. To kick the watch out we need (in this + * order) inode->inotify_mutex and ih->mutex. That's fine if we have + * a hold on inode; however, for all other cases we need to make damn sure + * we don't race with umount. We can *NOT* just grab a reference to a + * watch - inotify_unmount_inodes() will happily sail past it and we'll end + * with reference to inode potentially outliving its superblock. Ideally + * we just want to grab an active reference to superblock if we can; that + * will make sure we won't go into inotify_umount_inodes() until we are + * done. Cleanup is just deactivate_super(). However, that leaves a messy + * case - what if we *are* racing with umount() and active references to + * superblock can't be acquired anymore? We can bump ->s_count, grab + * ->s_umount, which will almost certainly wait until the superblock is shut + * down and the watch in question is pining for fjords. That's fine, but + * there is a problem - we might have hit the window between ->s_active + * getting to 0 / ->s_count - below S_BIAS (i.e. the moment when superblock + * is past the point of no return and is heading for shutdown) and the + * moment when deactivate_super() acquires ->s_umount. We could just do + * drop_super() yield() and retry, but that's rather antisocial and this + * stuff is luser-triggerable. OTOH, having grabbed ->s_umount and having + * found that we'd got there first (i.e. that ->s_root is non-NULL) we know + * that we won't race with inotify_umount_inodes(). So we could grab a + * reference to watch and do the rest as above, just with drop_super() instead + * of deactivate_super(), right? Wrong. We had to drop ih->mutex before we + * could grab ->s_umount. So the watch could've been gone already. + * + * That still can be dealt with - we need to save watch->wd, do idr_find() + * and compare its result with our pointer. If they match, we either have + * the damn thing still alive or we'd lost not one but two races at once, + * the watch had been killed and a new one got created with the same ->wd + * at the same address. That couldn't have happened in inotify_destroy(), + * but inotify_rm_wd() could run into that. Still, "new one got created" + * is not a problem - we have every right to kill it or leave it alone, + * whatever's more convenient. + * + * So we can use idr_find(...) == watch && watch->inode->i_sb == sb as + * "grab it and kill it" check. If it's been our original watch, we are + * fine, if it's a newcomer - nevermind, just pretend that we'd won the + * race and kill the fscker anyway; we are safe since we know that its + * superblock won't be going away. + * + * And yes, this is far beyond mere "not very pretty"; so's the entire + * concept of inotify to start with. + */ + +/** + * pin_to_kill - pin the watch down for removal + * @ih: inotify handle + * @watch: watch to kill + * + * Called with ih->mutex held, drops it. Possible return values: + * 0 - nothing to do, it has died + * 1 - remove it, drop the reference and deactivate_super() + * 2 - remove it, drop the reference and drop_super(); we tried hard to avoid + * that variant, since it involved a lot of PITA, but that's the best that + * could've been done. + */ +static int pin_to_kill(struct inotify_handle *ih, struct inotify_watch *watch) +{ + struct super_block *sb = watch->inode->i_sb; + s32 wd = watch->wd; + + spin_lock(&sb_lock); + if (sb->s_count >= S_BIAS) { + atomic_inc(&sb->s_active); + spin_unlock(&sb_lock); + get_inotify_watch(watch); + mutex_unlock(&ih->mutex); + return 1; /* the best outcome */ + } + sb->s_count++; + spin_unlock(&sb_lock); + mutex_unlock(&ih->mutex); /* can't grab ->s_umount under it */ + down_read(&sb->s_umount); + if (likely(!sb->s_root)) { + /* fs is already shut down; the watch is dead */ + drop_super(sb); + return 0; + } + /* raced with the final deactivate_super() */ + mutex_lock(&ih->mutex); + if (idr_find(&ih->idr, wd) != watch || watch->inode->i_sb != sb) { + /* the watch is dead */ + mutex_unlock(&ih->mutex); + drop_super(sb); + return 0; + } + /* still alive or freed and reused with the same sb and wd; kill */ + get_inotify_watch(watch); + mutex_unlock(&ih->mutex); + return 2; +} + +static void unpin_and_kill(struct inotify_watch *watch, int how) +{ + struct super_block *sb = watch->inode->i_sb; + put_inotify_watch(watch); + switch (how) { + case 1: + deactivate_super(sb); + break; + case 2: + drop_super(sb); + } +} + /** * inotify_destroy - clean up and destroy an inotify instance * @ih: inotify handle @@ -490,11 +619,15 @@ void inotify_destroy(struct inotify_handle *ih) * pretty. We cannot do a simple iteration over the list, because we * do not know the inode until we iterate to the watch. But we need to * hold inode->inotify_mutex before ih->mutex. The following works. + * + * AV: it had to become even uglier to start working ;-/ */ while (1) { struct inotify_watch *watch; struct list_head *watches; + struct super_block *sb; struct inode *inode; + int how; mutex_lock(&ih->mutex); watches = &ih->watches; @@ -503,8 +636,10 @@ void inotify_destroy(struct inotify_handle *ih) break; } watch = list_first_entry(watches, struct inotify_watch, h_list); - get_inotify_watch(watch); - mutex_unlock(&ih->mutex); + sb = watch->inode->i_sb; + how = pin_to_kill(ih, watch); + if (!how) + continue; inode = watch->inode; mutex_lock(&inode->inotify_mutex); @@ -518,7 +653,7 @@ void inotify_destroy(struct inotify_handle *ih) mutex_unlock(&ih->mutex); mutex_unlock(&inode->inotify_mutex); - put_inotify_watch(watch); + unpin_and_kill(watch, how); } /* free this handle: the put matching the get in inotify_init() */ @@ -719,7 +854,9 @@ void inotify_evict_watch(struct inotify_watch *watch) int inotify_rm_wd(struct inotify_handle *ih, u32 wd) { struct inotify_watch *watch; + struct super_block *sb; struct inode *inode; + int how; mutex_lock(&ih->mutex); watch = idr_find(&ih->idr, wd); @@ -727,9 +864,12 @@ int inotify_rm_wd(struct inotify_handle *ih, u32 wd) mutex_unlock(&ih->mutex); return -EINVAL; } - get_inotify_watch(watch); + sb = watch->inode->i_sb; + how = pin_to_kill(ih, watch); + if (!how) + return 0; + inode = watch->inode; - mutex_unlock(&ih->mutex); mutex_lock(&inode->inotify_mutex); mutex_lock(&ih->mutex); @@ -740,7 +880,7 @@ int inotify_rm_wd(struct inotify_handle *ih, u32 wd) mutex_unlock(&ih->mutex); mutex_unlock(&inode->inotify_mutex); - put_inotify_watch(watch); + unpin_and_kill(watch, how); return 0; } diff --git a/fs/inotify_user.c b/fs/inotify_user.c index d85c7d931cdf..d367e9b92862 100644 --- a/fs/inotify_user.c +++ b/fs/inotify_user.c @@ -537,9 +537,6 @@ static int inotify_release(struct inode *ignored, struct file *file) inotify_dev_event_dequeue(dev); mutex_unlock(&dev->ev_mutex); - if (file->f_flags & FASYNC) - inotify_fasync(-1, file, 0); - /* free this device: the put matching the get in inotify_init() */ put_inotify_dev(dev); diff --git a/fs/ioctl.c b/fs/ioctl.c index d152856c371b..43e8b2c0664b 100644 --- a/fs/ioctl.c +++ b/fs/ioctl.c @@ -400,11 +400,9 @@ static int ioctl_fioasync(unsigned int fd, struct file *filp, /* Did FASYNC state change ? */ if ((flag ^ filp->f_flags) & FASYNC) { - if (filp->f_op && filp->f_op->fasync) { - lock_kernel(); + if (filp->f_op && filp->f_op->fasync) error = filp->f_op->fasync(fd, filp, on); - unlock_kernel(); - } else + else error = -ENOTTY; } if (error) @@ -440,11 +438,17 @@ int do_vfs_ioctl(struct file *filp, unsigned int fd, unsigned int cmd, break; case FIONBIO: + /* BKL needed to avoid races tweaking f_flags */ + lock_kernel(); error = ioctl_fionbio(filp, argp); + unlock_kernel(); break; case FIOASYNC: + /* BKL needed to avoid races tweaking f_flags */ + lock_kernel(); error = ioctl_fioasync(fd, filp, argp); + unlock_kernel(); break; case FIOQSIZE: diff --git a/fs/jbd/checkpoint.c b/fs/jbd/checkpoint.c index 1bd8d4acc6f2..61f32f3868cd 100644 --- a/fs/jbd/checkpoint.c +++ b/fs/jbd/checkpoint.c @@ -115,7 +115,7 @@ static int __try_to_free_cp_buf(struct journal_head *jh) */ void __log_wait_for_space(journal_t *journal) { - int nblocks; + int nblocks, space_left; assert_spin_locked(&journal->j_state_lock); nblocks = jbd_space_needed(journal); @@ -128,25 +128,42 @@ void __log_wait_for_space(journal_t *journal) /* * Test again, another process may have checkpointed while we * were waiting for the checkpoint lock. If there are no - * outstanding transactions there is nothing to checkpoint and - * we can't make progress. Abort the journal in this case. + * transactions ready to be checkpointed, try to recover + * journal space by calling cleanup_journal_tail(), and if + * that doesn't work, by waiting for the currently committing + * transaction to complete. If there is absolutely no way + * to make progress, this is either a BUG or corrupted + * filesystem, so abort the journal and leave a stack + * trace for forensic evidence. */ spin_lock(&journal->j_state_lock); spin_lock(&journal->j_list_lock); nblocks = jbd_space_needed(journal); - if (__log_space_left(journal) < nblocks) { + space_left = __log_space_left(journal); + if (space_left < nblocks) { int chkpt = journal->j_checkpoint_transactions != NULL; + tid_t tid = 0; + if (journal->j_committing_transaction) + tid = journal->j_committing_transaction->t_tid; spin_unlock(&journal->j_list_lock); spin_unlock(&journal->j_state_lock); if (chkpt) { log_do_checkpoint(journal); + } else if (cleanup_journal_tail(journal) == 0) { + /* We were able to recover space; yay! */ + ; + } else if (tid) { + log_wait_commit(journal, tid); } else { - printk(KERN_ERR "%s: no transactions\n", - __func__); + printk(KERN_ERR "%s: needed %d blocks and " + "only had %d space available\n", + __func__, nblocks, space_left); + printk(KERN_ERR "%s: no way to get more " + "journal space\n", __func__); + WARN_ON(1); journal_abort(journal, 0); } - spin_lock(&journal->j_state_lock); } else { spin_unlock(&journal->j_list_lock); diff --git a/fs/jbd/transaction.c b/fs/jbd/transaction.c index d15cd6e7251e..60d4c32c8808 100644 --- a/fs/jbd/transaction.c +++ b/fs/jbd/transaction.c @@ -860,7 +860,6 @@ out: * int journal_get_undo_access() - Notify intent to modify metadata with non-rewindable consequences * @handle: transaction * @bh: buffer to undo - * @credits: store the number of taken credits here (if not NULL) * * Sometimes there is a need to distinguish between metadata which has * been committed to disk and that which has not. The ext3fs code uses diff --git a/fs/jbd2/checkpoint.c b/fs/jbd2/checkpoint.c index 9203c3332f17..9497718fe920 100644 --- a/fs/jbd2/checkpoint.c +++ b/fs/jbd2/checkpoint.c @@ -116,7 +116,7 @@ static int __try_to_free_cp_buf(struct journal_head *jh) */ void __jbd2_log_wait_for_space(journal_t *journal) { - int nblocks; + int nblocks, space_left; assert_spin_locked(&journal->j_state_lock); nblocks = jbd_space_needed(journal); @@ -129,25 +129,43 @@ void __jbd2_log_wait_for_space(journal_t *journal) /* * Test again, another process may have checkpointed while we * were waiting for the checkpoint lock. If there are no - * outstanding transactions there is nothing to checkpoint and - * we can't make progress. Abort the journal in this case. + * transactions ready to be checkpointed, try to recover + * journal space by calling cleanup_journal_tail(), and if + * that doesn't work, by waiting for the currently committing + * transaction to complete. If there is absolutely no way + * to make progress, this is either a BUG or corrupted + * filesystem, so abort the journal and leave a stack + * trace for forensic evidence. */ spin_lock(&journal->j_state_lock); spin_lock(&journal->j_list_lock); nblocks = jbd_space_needed(journal); - if (__jbd2_log_space_left(journal) < nblocks) { + space_left = __jbd2_log_space_left(journal); + if (space_left < nblocks) { int chkpt = journal->j_checkpoint_transactions != NULL; + tid_t tid = 0; + if (journal->j_committing_transaction) + tid = journal->j_committing_transaction->t_tid; spin_unlock(&journal->j_list_lock); spin_unlock(&journal->j_state_lock); if (chkpt) { jbd2_log_do_checkpoint(journal); + } else if (jbd2_cleanup_journal_tail(journal) == 0) { + /* We were able to recover space; yay! */ + ; + } else if (tid) { + jbd2_log_wait_commit(journal, tid); } else { - printk(KERN_ERR "%s: no transactions\n", - __func__); + printk(KERN_ERR "%s: needed %d blocks and " + "only had %d space available\n", + __func__, nblocks, space_left); + printk(KERN_ERR "%s: no way to get more " + "journal space in %s\n", __func__, + journal->j_devname); + WARN_ON(1); jbd2_journal_abort(journal, 0); } - spin_lock(&journal->j_state_lock); } else { spin_unlock(&journal->j_list_lock); diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c index 8b119e16aa36..ebc667bc54a8 100644 --- a/fs/jbd2/commit.c +++ b/fs/jbd2/commit.c @@ -974,6 +974,9 @@ restart_loop: journal->j_committing_transaction = NULL; spin_unlock(&journal->j_state_lock); + if (journal->j_commit_callback) + journal->j_commit_callback(journal, commit_transaction); + if (commit_transaction->t_checkpoint_list == NULL && commit_transaction->t_checkpoint_io_list == NULL) { __jbd2_journal_drop_transaction(journal, commit_transaction); @@ -995,11 +998,8 @@ restart_loop: } spin_unlock(&journal->j_list_lock); - if (journal->j_commit_callback) - journal->j_commit_callback(journal, commit_transaction); - trace_mark(jbd2_end_commit, "dev %s transaction %d head %d", - journal->j_devname, commit_transaction->t_tid, + journal->j_devname, journal->j_commit_sequence, journal->j_tail_sequence); jbd_debug(1, "JBD: commit %d complete, head %d\n", journal->j_commit_sequence, journal->j_tail_sequence); diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c index 783de118de92..e70d657a19f8 100644 --- a/fs/jbd2/journal.c +++ b/fs/jbd2/journal.c @@ -1089,6 +1089,7 @@ journal_t * jbd2_journal_init_inode (struct inode *inode) if (!journal->j_wbuf) { printk(KERN_ERR "%s: Cant allocate bhs for commit thread\n", __func__); + jbd2_stats_proc_exit(journal); kfree(journal); return NULL; } @@ -1098,6 +1099,7 @@ journal_t * jbd2_journal_init_inode (struct inode *inode) if (err) { printk(KERN_ERR "%s: Cannnot locate journal superblock\n", __func__); + jbd2_stats_proc_exit(journal); kfree(journal); return NULL; } diff --git a/fs/jffs2/background.c b/fs/jffs2/background.c index 8adebd3e43c6..3cceef4ad2b7 100644 --- a/fs/jffs2/background.c +++ b/fs/jffs2/background.c @@ -85,15 +85,15 @@ static int jffs2_garbage_collect_thread(void *_c) for (;;) { allow_signal(SIGHUP); again: + spin_lock(&c->erase_completion_lock); if (!jffs2_thread_should_wake(c)) { set_current_state (TASK_INTERRUPTIBLE); + spin_unlock(&c->erase_completion_lock); D1(printk(KERN_DEBUG "jffs2_garbage_collect_thread sleeping...\n")); - /* Yes, there's a race here; we checked jffs2_thread_should_wake() - before setting current->state to TASK_INTERRUPTIBLE. But it doesn't - matter - We don't care if we miss a wakeup, because the GC thread - is only an optimisation anyway. */ schedule(); - } + } else + spin_unlock(&c->erase_completion_lock); + /* This thread is purely an optimisation. But if it runs when other things could be running, it actually makes things a diff --git a/fs/jffs2/compr_lzo.c b/fs/jffs2/compr_lzo.c index 47b045797e42..90cb60d09787 100644 --- a/fs/jffs2/compr_lzo.c +++ b/fs/jffs2/compr_lzo.c @@ -19,7 +19,7 @@ static void *lzo_mem; static void *lzo_compress_buf; -static DEFINE_MUTEX(deflate_mutex); +static DEFINE_MUTEX(deflate_mutex); /* for lzo_mem and lzo_compress_buf */ static void free_workspace(void) { @@ -49,18 +49,21 @@ static int jffs2_lzo_compress(unsigned char *data_in, unsigned char *cpage_out, mutex_lock(&deflate_mutex); ret = lzo1x_1_compress(data_in, *sourcelen, lzo_compress_buf, &compress_size, lzo_mem); - mutex_unlock(&deflate_mutex); - if (ret != LZO_E_OK) - return -1; + goto fail; if (compress_size > *dstlen) - return -1; + goto fail; memcpy(cpage_out, lzo_compress_buf, compress_size); - *dstlen = compress_size; + mutex_unlock(&deflate_mutex); + *dstlen = compress_size; return 0; + + fail: + mutex_unlock(&deflate_mutex); + return -1; } static int jffs2_lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, diff --git a/fs/jffs2/nodemgmt.c b/fs/jffs2/nodemgmt.c index 0875b60b4bf7..21a052915aa9 100644 --- a/fs/jffs2/nodemgmt.c +++ b/fs/jffs2/nodemgmt.c @@ -261,9 +261,11 @@ static int jffs2_find_nextblock(struct jffs2_sb_info *c) jffs2_sum_reset_collected(c->summary); /* reset collected summary */ +#ifdef CONFIG_JFFS2_FS_WRITEBUFFER /* adjust write buffer offset, else we get a non contiguous write bug */ if (!(c->wbuf_ofs % c->sector_size) && !c->wbuf_len) c->wbuf_ofs = 0xffffffff; +#endif D1(printk(KERN_DEBUG "jffs2_find_nextblock(): new nextblock = 0x%08x\n", c->nextblock->offset)); diff --git a/fs/libfs.c b/fs/libfs.c index 74688598bcf7..e960a8321902 100644 --- a/fs/libfs.c +++ b/fs/libfs.c @@ -814,7 +814,7 @@ EXPORT_SYMBOL(simple_getattr); EXPORT_SYMBOL(simple_link); EXPORT_SYMBOL(simple_lookup); EXPORT_SYMBOL(simple_pin_fs); -EXPORT_SYMBOL(simple_prepare_write); +EXPORT_UNUSED_SYMBOL(simple_prepare_write); EXPORT_SYMBOL(simple_readpage); EXPORT_SYMBOL(simple_release_fs); EXPORT_SYMBOL(simple_rename); diff --git a/fs/lockd/host.c b/fs/lockd/host.c index 9fd8889097b7..70fc63a1727b 100644 --- a/fs/lockd/host.c +++ b/fs/lockd/host.c @@ -167,7 +167,8 @@ static struct nlm_host *nlm_lookup_host(struct nlm_lookup_host_info *ni) continue; if (host->h_server != ni->server) continue; - if (!nlm_cmp_addr(nlm_srcaddr(host), ni->src_sap)) + if (ni->server && + !nlm_cmp_addr(nlm_srcaddr(host), ni->src_sap)) continue; /* Move to head of hash chain. */ diff --git a/fs/lockd/svc.c b/fs/lockd/svc.c index c631a83931ce..56b076736b56 100644 --- a/fs/lockd/svc.c +++ b/fs/lockd/svc.c @@ -181,6 +181,7 @@ lockd(void *vrqstp) } flush_signals(current); cancel_delayed_work_sync(&grace_period_end); + locks_end_grace(&lockd_manager); if (nlmsvc_ops) nlmsvc_invalidate_all(); nlm_shutdown_hosts(); diff --git a/fs/lockd/svc4proc.c b/fs/lockd/svc4proc.c index 014f6ce48172..4dfdcbc6bf68 100644 --- a/fs/lockd/svc4proc.c +++ b/fs/lockd/svc4proc.c @@ -434,6 +434,7 @@ nlm4svc_proc_sm_notify(struct svc_rqst *rqstp, struct nlm_reboot *argp, * reclaim all locks we hold on this server. */ memset(&saddr, 0, sizeof(saddr)); + saddr.sin_family = AF_INET; saddr.sin_addr.s_addr = argp->addr; nlm_host_rebooted(&saddr, argp->mon, argp->len, argp->state); diff --git a/fs/lockd/svcproc.c b/fs/lockd/svcproc.c index 548b0bb2b84d..3ca89e2a9381 100644 --- a/fs/lockd/svcproc.c +++ b/fs/lockd/svcproc.c @@ -466,6 +466,7 @@ nlmsvc_proc_sm_notify(struct svc_rqst *rqstp, struct nlm_reboot *argp, * reclaim all locks we hold on this server. */ memset(&saddr, 0, sizeof(saddr)); + saddr.sin_family = AF_INET; saddr.sin_addr.s_addr = argp->addr; nlm_host_rebooted(&saddr, argp->mon, argp->len, argp->state); diff --git a/fs/msdos/Makefile b/fs/msdos/Makefile deleted file mode 100644 index ea67646fcb95..000000000000 --- a/fs/msdos/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for the Linux msdos filesystem routines. -# - -obj-$(CONFIG_MSDOS_FS) += msdos.o - -msdos-y := namei.o diff --git a/fs/msdos/namei.c b/fs/msdos/namei.c deleted file mode 100644 index e844b9809d27..000000000000 --- a/fs/msdos/namei.c +++ /dev/null @@ -1,702 +0,0 @@ -/* - * linux/fs/msdos/namei.c - * - * Written 1992,1993 by Werner Almesberger - * Hidden files 1995 by Albert Cahalan - * Rewritten for constant inumbers 1999 by Al Viro - */ - -#include -#include -#include -#include -#include - -/* Characters that are undesirable in an MS-DOS file name */ -static unsigned char bad_chars[] = "*?<>|\""; -static unsigned char bad_if_strict[] = "+=,; "; - -/***** Formats an MS-DOS file name. Rejects invalid names. */ -static int msdos_format_name(const unsigned char *name, int len, - unsigned char *res, struct fat_mount_options *opts) - /* - * name is the proposed name, len is its length, res is - * the resulting name, opts->name_check is either (r)elaxed, - * (n)ormal or (s)trict, opts->dotsOK allows dots at the - * beginning of name (for hidden files) - */ -{ - unsigned char *walk; - unsigned char c; - int space; - - if (name[0] == '.') { /* dotfile because . and .. already done */ - if (opts->dotsOK) { - /* Get rid of dot - test for it elsewhere */ - name++; - len--; - } else - return -EINVAL; - } - /* - * disallow names that _really_ start with a dot - */ - space = 1; - c = 0; - for (walk = res; len && walk - res < 8; walk++) { - c = *name++; - len--; - if (opts->name_check != 'r' && strchr(bad_chars, c)) - return -EINVAL; - if (opts->name_check == 's' && strchr(bad_if_strict, c)) - return -EINVAL; - if (c >= 'A' && c <= 'Z' && opts->name_check == 's') - return -EINVAL; - if (c < ' ' || c == ':' || c == '\\') - return -EINVAL; - /* - * 0xE5 is legal as a first character, but we must substitute - * 0x05 because 0xE5 marks deleted files. Yes, DOS really - * does this. - * It seems that Microsoft hacked DOS to support non-US - * characters after the 0xE5 character was already in use to - * mark deleted files. - */ - if ((res == walk) && (c == 0xE5)) - c = 0x05; - if (c == '.') - break; - space = (c == ' '); - *walk = (!opts->nocase && c >= 'a' && c <= 'z') ? c - 32 : c; - } - if (space) - return -EINVAL; - if (opts->name_check == 's' && len && c != '.') { - c = *name++; - len--; - if (c != '.') - return -EINVAL; - } - while (c != '.' && len--) - c = *name++; - if (c == '.') { - while (walk - res < 8) - *walk++ = ' '; - while (len > 0 && walk - res < MSDOS_NAME) { - c = *name++; - len--; - if (opts->name_check != 'r' && strchr(bad_chars, c)) - return -EINVAL; - if (opts->name_check == 's' && - strchr(bad_if_strict, c)) - return -EINVAL; - if (c < ' ' || c == ':' || c == '\\') - return -EINVAL; - if (c == '.') { - if (opts->name_check == 's') - return -EINVAL; - break; - } - if (c >= 'A' && c <= 'Z' && opts->name_check == 's') - return -EINVAL; - space = c == ' '; - if (!opts->nocase && c >= 'a' && c <= 'z') - *walk++ = c - 32; - else - *walk++ = c; - } - if (space) - return -EINVAL; - if (opts->name_check == 's' && len) - return -EINVAL; - } - while (walk - res < MSDOS_NAME) - *walk++ = ' '; - - return 0; -} - -/***** Locates a directory entry. Uses unformatted name. */ -static int msdos_find(struct inode *dir, const unsigned char *name, int len, - struct fat_slot_info *sinfo) -{ - struct msdos_sb_info *sbi = MSDOS_SB(dir->i_sb); - unsigned char msdos_name[MSDOS_NAME]; - int err; - - err = msdos_format_name(name, len, msdos_name, &sbi->options); - if (err) - return -ENOENT; - - err = fat_scan(dir, msdos_name, sinfo); - if (!err && sbi->options.dotsOK) { - if (name[0] == '.') { - if (!(sinfo->de->attr & ATTR_HIDDEN)) - err = -ENOENT; - } else { - if (sinfo->de->attr & ATTR_HIDDEN) - err = -ENOENT; - } - if (err) - brelse(sinfo->bh); - } - return err; -} - -/* - * Compute the hash for the msdos name corresponding to the dentry. - * Note: if the name is invalid, we leave the hash code unchanged so - * that the existing dentry can be used. The msdos fs routines will - * return ENOENT or EINVAL as appropriate. - */ -static int msdos_hash(struct dentry *dentry, struct qstr *qstr) -{ - struct fat_mount_options *options = &MSDOS_SB(dentry->d_sb)->options; - unsigned char msdos_name[MSDOS_NAME]; - int error; - - error = msdos_format_name(qstr->name, qstr->len, msdos_name, options); - if (!error) - qstr->hash = full_name_hash(msdos_name, MSDOS_NAME); - return 0; -} - -/* - * Compare two msdos names. If either of the names are invalid, - * we fall back to doing the standard name comparison. - */ -static int msdos_cmp(struct dentry *dentry, struct qstr *a, struct qstr *b) -{ - struct fat_mount_options *options = &MSDOS_SB(dentry->d_sb)->options; - unsigned char a_msdos_name[MSDOS_NAME], b_msdos_name[MSDOS_NAME]; - int error; - - error = msdos_format_name(a->name, a->len, a_msdos_name, options); - if (error) - goto old_compare; - error = msdos_format_name(b->name, b->len, b_msdos_name, options); - if (error) - goto old_compare; - error = memcmp(a_msdos_name, b_msdos_name, MSDOS_NAME); -out: - return error; - -old_compare: - error = 1; - if (a->len == b->len) - error = memcmp(a->name, b->name, a->len); - goto out; -} - -static struct dentry_operations msdos_dentry_operations = { - .d_hash = msdos_hash, - .d_compare = msdos_cmp, -}; - -/* - * AV. Wrappers for FAT sb operations. Is it wise? - */ - -/***** Get inode using directory and name */ -static struct dentry *msdos_lookup(struct inode *dir, struct dentry *dentry, - struct nameidata *nd) -{ - struct super_block *sb = dir->i_sb; - struct fat_slot_info sinfo; - struct inode *inode = NULL; - int res; - - dentry->d_op = &msdos_dentry_operations; - - lock_super(sb); - res = msdos_find(dir, dentry->d_name.name, dentry->d_name.len, &sinfo); - if (res == -ENOENT) - goto add; - if (res < 0) - goto out; - inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); - brelse(sinfo.bh); - if (IS_ERR(inode)) { - res = PTR_ERR(inode); - goto out; - } -add: - res = 0; - dentry = d_splice_alias(inode, dentry); - if (dentry) - dentry->d_op = &msdos_dentry_operations; -out: - unlock_super(sb); - if (!res) - return dentry; - return ERR_PTR(res); -} - -/***** Creates a directory entry (name is already formatted). */ -static int msdos_add_entry(struct inode *dir, const unsigned char *name, - int is_dir, int is_hid, int cluster, - struct timespec *ts, struct fat_slot_info *sinfo) -{ - struct msdos_sb_info *sbi = MSDOS_SB(dir->i_sb); - struct msdos_dir_entry de; - __le16 time, date; - int err; - - memcpy(de.name, name, MSDOS_NAME); - de.attr = is_dir ? ATTR_DIR : ATTR_ARCH; - if (is_hid) - de.attr |= ATTR_HIDDEN; - de.lcase = 0; - fat_date_unix2dos(ts->tv_sec, &time, &date, sbi->options.tz_utc); - de.cdate = de.adate = 0; - de.ctime = 0; - de.ctime_cs = 0; - de.time = time; - de.date = date; - de.start = cpu_to_le16(cluster); - de.starthi = cpu_to_le16(cluster >> 16); - de.size = 0; - - err = fat_add_entries(dir, &de, 1, sinfo); - if (err) - return err; - - dir->i_ctime = dir->i_mtime = *ts; - if (IS_DIRSYNC(dir)) - (void)fat_sync_inode(dir); - else - mark_inode_dirty(dir); - - return 0; -} - -/***** Create a file */ -static int msdos_create(struct inode *dir, struct dentry *dentry, int mode, - struct nameidata *nd) -{ - struct super_block *sb = dir->i_sb; - struct inode *inode = NULL; - struct fat_slot_info sinfo; - struct timespec ts; - unsigned char msdos_name[MSDOS_NAME]; - int err, is_hid; - - lock_super(sb); - - err = msdos_format_name(dentry->d_name.name, dentry->d_name.len, - msdos_name, &MSDOS_SB(sb)->options); - if (err) - goto out; - is_hid = (dentry->d_name.name[0] == '.') && (msdos_name[0] != '.'); - /* Have to do it due to foo vs. .foo conflicts */ - if (!fat_scan(dir, msdos_name, &sinfo)) { - brelse(sinfo.bh); - err = -EINVAL; - goto out; - } - - ts = CURRENT_TIME_SEC; - err = msdos_add_entry(dir, msdos_name, 0, is_hid, 0, &ts, &sinfo); - if (err) - goto out; - inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); - brelse(sinfo.bh); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - inode->i_mtime = inode->i_atime = inode->i_ctime = ts; - /* timestamp is already written, so mark_inode_dirty() is unneeded. */ - - d_instantiate(dentry, inode); -out: - unlock_super(sb); - if (!err) - err = fat_flush_inodes(sb, dir, inode); - return err; -} - -/***** Remove a directory */ -static int msdos_rmdir(struct inode *dir, struct dentry *dentry) -{ - struct super_block *sb = dir->i_sb; - struct inode *inode = dentry->d_inode; - struct fat_slot_info sinfo; - int err; - - lock_super(sb); - /* - * Check whether the directory is not in use, then check - * whether it is empty. - */ - err = fat_dir_empty(inode); - if (err) - goto out; - err = msdos_find(dir, dentry->d_name.name, dentry->d_name.len, &sinfo); - if (err) - goto out; - - err = fat_remove_entries(dir, &sinfo); /* and releases bh */ - if (err) - goto out; - drop_nlink(dir); - - clear_nlink(inode); - inode->i_ctime = CURRENT_TIME_SEC; - fat_detach(inode); -out: - unlock_super(sb); - if (!err) - err = fat_flush_inodes(sb, dir, inode); - - return err; -} - -/***** Make a directory */ -static int msdos_mkdir(struct inode *dir, struct dentry *dentry, int mode) -{ - struct super_block *sb = dir->i_sb; - struct fat_slot_info sinfo; - struct inode *inode; - unsigned char msdos_name[MSDOS_NAME]; - struct timespec ts; - int err, is_hid, cluster; - - lock_super(sb); - - err = msdos_format_name(dentry->d_name.name, dentry->d_name.len, - msdos_name, &MSDOS_SB(sb)->options); - if (err) - goto out; - is_hid = (dentry->d_name.name[0] == '.') && (msdos_name[0] != '.'); - /* foo vs .foo situation */ - if (!fat_scan(dir, msdos_name, &sinfo)) { - brelse(sinfo.bh); - err = -EINVAL; - goto out; - } - - ts = CURRENT_TIME_SEC; - cluster = fat_alloc_new_dir(dir, &ts); - if (cluster < 0) { - err = cluster; - goto out; - } - err = msdos_add_entry(dir, msdos_name, 1, is_hid, cluster, &ts, &sinfo); - if (err) - goto out_free; - inc_nlink(dir); - - inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); - brelse(sinfo.bh); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - /* the directory was completed, just return a error */ - goto out; - } - inode->i_nlink = 2; - inode->i_mtime = inode->i_atime = inode->i_ctime = ts; - /* timestamp is already written, so mark_inode_dirty() is unneeded. */ - - d_instantiate(dentry, inode); - - unlock_super(sb); - fat_flush_inodes(sb, dir, inode); - return 0; - -out_free: - fat_free_clusters(dir, cluster); -out: - unlock_super(sb); - return err; -} - -/***** Unlink a file */ -static int msdos_unlink(struct inode *dir, struct dentry *dentry) -{ - struct inode *inode = dentry->d_inode; - struct super_block *sb= inode->i_sb; - struct fat_slot_info sinfo; - int err; - - lock_super(sb); - err = msdos_find(dir, dentry->d_name.name, dentry->d_name.len, &sinfo); - if (err) - goto out; - - err = fat_remove_entries(dir, &sinfo); /* and releases bh */ - if (err) - goto out; - clear_nlink(inode); - inode->i_ctime = CURRENT_TIME_SEC; - fat_detach(inode); -out: - unlock_super(sb); - if (!err) - err = fat_flush_inodes(sb, dir, inode); - - return err; -} - -static int do_msdos_rename(struct inode *old_dir, unsigned char *old_name, - struct dentry *old_dentry, - struct inode *new_dir, unsigned char *new_name, - struct dentry *new_dentry, int is_hid) -{ - struct buffer_head *dotdot_bh; - struct msdos_dir_entry *dotdot_de; - struct inode *old_inode, *new_inode; - struct fat_slot_info old_sinfo, sinfo; - struct timespec ts; - loff_t dotdot_i_pos, new_i_pos; - int err, old_attrs, is_dir, update_dotdot, corrupt = 0; - - old_sinfo.bh = sinfo.bh = dotdot_bh = NULL; - old_inode = old_dentry->d_inode; - new_inode = new_dentry->d_inode; - - err = fat_scan(old_dir, old_name, &old_sinfo); - if (err) { - err = -EIO; - goto out; - } - - is_dir = S_ISDIR(old_inode->i_mode); - update_dotdot = (is_dir && old_dir != new_dir); - if (update_dotdot) { - if (fat_get_dotdot_entry(old_inode, &dotdot_bh, &dotdot_de, - &dotdot_i_pos) < 0) { - err = -EIO; - goto out; - } - } - - old_attrs = MSDOS_I(old_inode)->i_attrs; - err = fat_scan(new_dir, new_name, &sinfo); - if (!err) { - if (!new_inode) { - /* "foo" -> ".foo" case. just change the ATTR_HIDDEN */ - if (sinfo.de != old_sinfo.de) { - err = -EINVAL; - goto out; - } - if (is_hid) - MSDOS_I(old_inode)->i_attrs |= ATTR_HIDDEN; - else - MSDOS_I(old_inode)->i_attrs &= ~ATTR_HIDDEN; - if (IS_DIRSYNC(old_dir)) { - err = fat_sync_inode(old_inode); - if (err) { - MSDOS_I(old_inode)->i_attrs = old_attrs; - goto out; - } - } else - mark_inode_dirty(old_inode); - - old_dir->i_version++; - old_dir->i_ctime = old_dir->i_mtime = CURRENT_TIME_SEC; - if (IS_DIRSYNC(old_dir)) - (void)fat_sync_inode(old_dir); - else - mark_inode_dirty(old_dir); - goto out; - } - } - - ts = CURRENT_TIME_SEC; - if (new_inode) { - if (err) - goto out; - if (is_dir) { - err = fat_dir_empty(new_inode); - if (err) - goto out; - } - new_i_pos = MSDOS_I(new_inode)->i_pos; - fat_detach(new_inode); - } else { - err = msdos_add_entry(new_dir, new_name, is_dir, is_hid, 0, - &ts, &sinfo); - if (err) - goto out; - new_i_pos = sinfo.i_pos; - } - new_dir->i_version++; - - fat_detach(old_inode); - fat_attach(old_inode, new_i_pos); - if (is_hid) - MSDOS_I(old_inode)->i_attrs |= ATTR_HIDDEN; - else - MSDOS_I(old_inode)->i_attrs &= ~ATTR_HIDDEN; - if (IS_DIRSYNC(new_dir)) { - err = fat_sync_inode(old_inode); - if (err) - goto error_inode; - } else - mark_inode_dirty(old_inode); - - if (update_dotdot) { - int start = MSDOS_I(new_dir)->i_logstart; - dotdot_de->start = cpu_to_le16(start); - dotdot_de->starthi = cpu_to_le16(start >> 16); - mark_buffer_dirty(dotdot_bh); - if (IS_DIRSYNC(new_dir)) { - err = sync_dirty_buffer(dotdot_bh); - if (err) - goto error_dotdot; - } - drop_nlink(old_dir); - if (!new_inode) - inc_nlink(new_dir); - } - - err = fat_remove_entries(old_dir, &old_sinfo); /* and releases bh */ - old_sinfo.bh = NULL; - if (err) - goto error_dotdot; - old_dir->i_version++; - old_dir->i_ctime = old_dir->i_mtime = ts; - if (IS_DIRSYNC(old_dir)) - (void)fat_sync_inode(old_dir); - else - mark_inode_dirty(old_dir); - - if (new_inode) { - drop_nlink(new_inode); - if (is_dir) - drop_nlink(new_inode); - new_inode->i_ctime = ts; - } -out: - brelse(sinfo.bh); - brelse(dotdot_bh); - brelse(old_sinfo.bh); - return err; - -error_dotdot: - /* data cluster is shared, serious corruption */ - corrupt = 1; - - if (update_dotdot) { - int start = MSDOS_I(old_dir)->i_logstart; - dotdot_de->start = cpu_to_le16(start); - dotdot_de->starthi = cpu_to_le16(start >> 16); - mark_buffer_dirty(dotdot_bh); - corrupt |= sync_dirty_buffer(dotdot_bh); - } -error_inode: - fat_detach(old_inode); - fat_attach(old_inode, old_sinfo.i_pos); - MSDOS_I(old_inode)->i_attrs = old_attrs; - if (new_inode) { - fat_attach(new_inode, new_i_pos); - if (corrupt) - corrupt |= fat_sync_inode(new_inode); - } else { - /* - * If new entry was not sharing the data cluster, it - * shouldn't be serious corruption. - */ - int err2 = fat_remove_entries(new_dir, &sinfo); - if (corrupt) - corrupt |= err2; - sinfo.bh = NULL; - } - if (corrupt < 0) { - fat_fs_panic(new_dir->i_sb, - "%s: Filesystem corrupted (i_pos %lld)", - __func__, sinfo.i_pos); - } - goto out; -} - -/***** Rename, a wrapper for rename_same_dir & rename_diff_dir */ -static int msdos_rename(struct inode *old_dir, struct dentry *old_dentry, - struct inode *new_dir, struct dentry *new_dentry) -{ - struct super_block *sb = old_dir->i_sb; - unsigned char old_msdos_name[MSDOS_NAME], new_msdos_name[MSDOS_NAME]; - int err, is_hid; - - lock_super(sb); - - err = msdos_format_name(old_dentry->d_name.name, - old_dentry->d_name.len, old_msdos_name, - &MSDOS_SB(old_dir->i_sb)->options); - if (err) - goto out; - err = msdos_format_name(new_dentry->d_name.name, - new_dentry->d_name.len, new_msdos_name, - &MSDOS_SB(new_dir->i_sb)->options); - if (err) - goto out; - - is_hid = - (new_dentry->d_name.name[0] == '.') && (new_msdos_name[0] != '.'); - - err = do_msdos_rename(old_dir, old_msdos_name, old_dentry, - new_dir, new_msdos_name, new_dentry, is_hid); -out: - unlock_super(sb); - if (!err) - err = fat_flush_inodes(sb, old_dir, new_dir); - return err; -} - -static const struct inode_operations msdos_dir_inode_operations = { - .create = msdos_create, - .lookup = msdos_lookup, - .unlink = msdos_unlink, - .mkdir = msdos_mkdir, - .rmdir = msdos_rmdir, - .rename = msdos_rename, - .setattr = fat_setattr, - .getattr = fat_getattr, -}; - -static int msdos_fill_super(struct super_block *sb, void *data, int silent) -{ - int res; - - res = fat_fill_super(sb, data, silent, &msdos_dir_inode_operations, 0); - if (res) - return res; - - sb->s_flags |= MS_NOATIME; - sb->s_root->d_op = &msdos_dentry_operations; - return 0; -} - -static int msdos_get_sb(struct file_system_type *fs_type, - int flags, const char *dev_name, - void *data, struct vfsmount *mnt) -{ - return get_sb_bdev(fs_type, flags, dev_name, data, msdos_fill_super, - mnt); -} - -static struct file_system_type msdos_fs_type = { - .owner = THIS_MODULE, - .name = "msdos", - .get_sb = msdos_get_sb, - .kill_sb = kill_block_super, - .fs_flags = FS_REQUIRES_DEV, -}; - -static int __init init_msdos_fs(void) -{ - return register_filesystem(&msdos_fs_type); -} - -static void __exit exit_msdos_fs(void) -{ - unregister_filesystem(&msdos_fs_type); -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Werner Almesberger"); -MODULE_DESCRIPTION("MS-DOS filesystem support"); - -module_init(init_msdos_fs) -module_exit(exit_msdos_fs) diff --git a/fs/namei.c b/fs/namei.c index 09ce58e49e72..d34e0f9681c6 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -1378,7 +1378,7 @@ static int may_delete(struct inode *dir,struct dentry *victim,int isdir) if (IS_APPEND(dir)) return -EPERM; if (check_sticky(dir, victim->d_inode)||IS_APPEND(victim->d_inode)|| - IS_IMMUTABLE(victim->d_inode)) + IS_IMMUTABLE(victim->d_inode) || IS_SWAPFILE(victim->d_inode)) return -EPERM; if (isdir) { if (!S_ISDIR(victim->d_inode->i_mode)) diff --git a/fs/namespace.c b/fs/namespace.c index cce46702d33c..65b3dc844c87 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -1815,8 +1815,8 @@ static void shrink_submounts(struct vfsmount *mnt, struct list_head *umounts) while (!list_empty(&graveyard)) { m = list_first_entry(&graveyard, struct vfsmount, mnt_expire); - touch_mnt_namespace(mnt->mnt_ns); - umount_tree(mnt, 1, umounts); + touch_mnt_namespace(m->mnt_ns); + umount_tree(m, 1, umounts); } } } diff --git a/fs/nfs/inode.c b/fs/nfs/inode.c index b9195c02a863..d22eb383e1cf 100644 --- a/fs/nfs/inode.c +++ b/fs/nfs/inode.c @@ -5,7 +5,7 @@ * * nfs inode and superblock handling functions * - * Modularised by Alan Cox , while hacking some + * Modularised by Alan Cox , while hacking some * experimental NFS changes. Modularisation taken straight from SYS5 fs. * * Change to nfs_read_super() to permit NFS mounts to multi-homed hosts. @@ -908,21 +908,16 @@ static int nfs_size_need_update(const struct inode *inode, const struct nfs_fatt return nfs_size_to_loff_t(fattr->size) > i_size_read(inode); } -static unsigned long nfs_attr_generation_counter; +static atomic_long_t nfs_attr_generation_counter; static unsigned long nfs_read_attr_generation_counter(void) { - smp_rmb(); - return nfs_attr_generation_counter; + return atomic_long_read(&nfs_attr_generation_counter); } unsigned long nfs_inc_attr_generation_counter(void) { - unsigned long ret; - smp_rmb(); - ret = ++nfs_attr_generation_counter; - smp_wmb(); - return ret; + return atomic_long_inc_return(&nfs_attr_generation_counter); } void nfs_fattr_init(struct nfs_fattr *fattr) diff --git a/fs/nfs/super.c b/fs/nfs/super.c index a3b0061dfd45..f48db679a1c6 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -5,7 +5,7 @@ * * nfs superblock handling functions * - * Modularised by Alan Cox , while hacking some + * Modularised by Alan Cox , while hacking some * experimental NFS changes. Modularisation taken straight from SYS5 fs. * * Change to nfs_read_super() to permit NFS mounts to multi-homed hosts. diff --git a/fs/nfsd/nfs4recover.c b/fs/nfsd/nfs4recover.c index bb93946ace22..b79ec930d9f1 100644 --- a/fs/nfsd/nfs4recover.c +++ b/fs/nfsd/nfs4recover.c @@ -225,12 +225,12 @@ nfsd4_list_rec_dir(struct dentry *dir, recdir_func *f) return 0; nfs4_save_user(&uid, &gid); + INIT_LIST_HEAD(dentries); filp = dentry_open(dget(dir), mntget(rec_dir.mnt), O_RDONLY); status = PTR_ERR(filp); if (IS_ERR(filp)) goto out; - INIT_LIST_HEAD(dentries); status = vfs_readdir(filp, nfsd4_build_dentrylist, &dla); fput(filp); while (!list_empty(dentries)) { diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index b0bebc552a11..1a052ac2bde9 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -3261,6 +3261,7 @@ nfs4_state_shutdown(void) { cancel_rearming_delayed_workqueue(laundry_wq, &laundromat_work); destroy_workqueue(laundry_wq); + locks_end_grace(&nfsd4_manager); nfs4_lock_state(); nfs4_release_reclaim(); __nfs4_state_shutdown(); diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c index 0bc56f6d9276..4433c8f00163 100644 --- a/fs/nfsd/vfs.c +++ b/fs/nfsd/vfs.c @@ -1875,11 +1875,11 @@ static int nfsd_buffered_readdir(struct file *file, filldir_t func, return -ENOMEM; offset = *offsetp; - cdp->err = nfserr_eof; /* will be cleared on successful read */ while (1) { unsigned int reclen; + cdp->err = nfserr_eof; /* will be cleared on successful read */ buf.used = 0; buf.full = 0; @@ -1912,8 +1912,6 @@ static int nfsd_buffered_readdir(struct file *file, filldir_t func, de = (struct buffered_dirent *)((char *)de + reclen); } offset = vfs_llseek(file, 0, SEEK_CUR); - if (!buf.full) - break; } done: diff --git a/fs/ntfs/debug.h b/fs/ntfs/debug.h index 5e6724c1afd1..2142b1c68b61 100644 --- a/fs/ntfs/debug.h +++ b/fs/ntfs/debug.h @@ -30,7 +30,8 @@ extern int debug_msgs; -#if 0 /* Fool kernel-doc since it doesn't do macros yet */ +extern void __ntfs_debug(const char *file, int line, const char *function, + const char *format, ...) __attribute__ ((format (printf, 4, 5))); /** * ntfs_debug - write a debug level message to syslog * @f: a printf format string containing the message @@ -39,11 +40,6 @@ extern int debug_msgs; * ntfs_debug() writes a DEBUG level message to the syslog but only if the * driver was compiled with -DDEBUG. Otherwise, the call turns into a NOP. */ -static void ntfs_debug(const char *f, ...); -#endif - -extern void __ntfs_debug (const char *file, int line, const char *function, - const char *format, ...) __attribute__ ((format (printf, 4, 5))); #define ntfs_debug(f, a...) \ __ntfs_debug(__FILE__, __LINE__, __func__, f, ##a) diff --git a/fs/ocfs2/buffer_head_io.c b/fs/ocfs2/buffer_head_io.c index 7e947c672469..3a178ec48d7c 100644 --- a/fs/ocfs2/buffer_head_io.c +++ b/fs/ocfs2/buffer_head_io.c @@ -112,7 +112,7 @@ int ocfs2_read_blocks_sync(struct ocfs2_super *osb, u64 block, bh = bhs[i]; if (buffer_jbd(bh)) { - mlog(ML_ERROR, + mlog(ML_BH_IO, "trying to sync read a jbd " "managed bh (blocknr = %llu), skipping\n", (unsigned long long)bh->b_blocknr); @@ -147,15 +147,10 @@ int ocfs2_read_blocks_sync(struct ocfs2_super *osb, u64 block, for (i = nr; i > 0; i--) { bh = bhs[i - 1]; - if (buffer_jbd(bh)) { - mlog(ML_ERROR, - "the journal got the buffer while it was " - "locked for io! (blocknr = %llu)\n", - (unsigned long long)bh->b_blocknr); - BUG(); - } + /* No need to wait on the buffer if it's managed by JBD. */ + if (!buffer_jbd(bh)) + wait_on_buffer(bh); - wait_on_buffer(bh); if (!buffer_uptodate(bh)) { /* Status won't be cleared from here on out, * so we can safely record this and loop back @@ -251,8 +246,6 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, ignore_cache = 1; } - /* XXX: Can we ever get this and *not* have the cached - * flag set? */ if (buffer_jbd(bh)) { if (ignore_cache) mlog(ML_BH_IO, "trying to sync read a jbd " diff --git a/fs/ocfs2/dlm/dlmfs.c b/fs/ocfs2/dlm/dlmfs.c index 533a789c3ef8..ba962d71b34d 100644 --- a/fs/ocfs2/dlm/dlmfs.c +++ b/fs/ocfs2/dlm/dlmfs.c @@ -608,8 +608,10 @@ static int __init init_dlmfs_fs(void) 0, (SLAB_HWCACHE_ALIGN|SLAB_RECLAIM_ACCOUNT| SLAB_MEM_SPREAD), dlmfs_init_once); - if (!dlmfs_inode_cache) + if (!dlmfs_inode_cache) { + status = -ENOMEM; goto bail; + } cleanup_inode = 1; user_dlm_worker = create_singlethread_workqueue("user_dlm"); diff --git a/fs/ocfs2/dlm/userdlm.h b/fs/ocfs2/dlm/userdlm.h index 39ec27738499..0c3cc03c61fa 100644 --- a/fs/ocfs2/dlm/userdlm.h +++ b/fs/ocfs2/dlm/userdlm.h @@ -33,7 +33,7 @@ #include /* user_lock_res->l_flags flags. */ -#define USER_LOCK_ATTACHED (0x00000001) /* have we initialized +#define USER_LOCK_ATTACHED (0x00000001) /* we have initialized * the lvb */ #define USER_LOCK_BUSY (0x00000002) /* we are currently in * dlm_lock */ diff --git a/fs/ocfs2/dlmglue.c b/fs/ocfs2/dlmglue.c index ec684426034b..6e6cc0a2e5f7 100644 --- a/fs/ocfs2/dlmglue.c +++ b/fs/ocfs2/dlmglue.c @@ -2841,9 +2841,8 @@ static void ocfs2_unlock_ast(void *opaque, int error) lockres_clear_flags(lockres, OCFS2_LOCK_BUSY); lockres->l_unlock_action = OCFS2_UNLOCK_INVALID; - spin_unlock_irqrestore(&lockres->l_lock, flags); - wake_up(&lockres->l_event); + spin_unlock_irqrestore(&lockres->l_lock, flags); mlog_exit_void(); } diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 8d3225a78073..e2570a3bc2b2 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -247,8 +247,8 @@ int ocfs2_update_inode_atime(struct inode *inode, mlog_entry_void(); handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS); - if (handle == NULL) { - ret = -ENOMEM; + if (IS_ERR(handle)) { + ret = PTR_ERR(handle); mlog_errno(ret); goto out; } @@ -312,8 +312,8 @@ static int ocfs2_simple_size_update(struct inode *inode, handle_t *handle = NULL; handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS); - if (handle == NULL) { - ret = -ENOMEM; + if (IS_ERR(handle)) { + ret = PTR_ERR(handle); mlog_errno(ret); goto out; } @@ -679,8 +679,7 @@ leave: /* Some parts of this taken from generic_cont_expand, which turned out * to be too fragile to do exactly what we need without us having to - * worry about recursive locking in ->prepare_write() and - * ->commit_write(). */ + * worry about recursive locking in ->write_begin() and ->write_end(). */ static int ocfs2_write_zero_page(struct inode *inode, u64 size) { @@ -1056,8 +1055,8 @@ static int __ocfs2_write_remove_suid(struct inode *inode, (unsigned long long)OCFS2_I(inode)->ip_blkno, inode->i_mode); handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS); - if (handle == NULL) { - ret = -ENOMEM; + if (IS_ERR(handle)) { + ret = PTR_ERR(handle); mlog_errno(ret); goto out; } @@ -1260,8 +1259,8 @@ static int __ocfs2_remove_inode_range(struct inode *inode, } handle = ocfs2_start_trans(osb, OCFS2_REMOVE_EXTENT_CREDITS); - if (handle == NULL) { - ret = -ENOMEM; + if (IS_ERR(handle)) { + ret = PTR_ERR(handle); mlog_errno(ret); goto out; } @@ -1353,8 +1352,8 @@ static int ocfs2_zero_partial_clusters(struct inode *inode, goto out; handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS); - if (handle == NULL) { - ret = -ENOMEM; + if (IS_ERR(handle)) { + ret = PTR_ERR(handle); mlog_errno(ret); goto out; } @@ -1867,6 +1866,13 @@ relock: written = generic_file_direct_write(iocb, iov, &nr_segs, *ppos, ppos, count, ocount); if (written < 0) { + /* + * direct write may have instantiated a few + * blocks outside i_size. Trim these off again. + * Don't need i_size_read because we hold i_mutex. + */ + if (*ppos + count > inode->i_size) + vmtruncate(inode, inode->i_size); ret = written; goto out_dio; } diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 4903688f72a9..7aa00d511874 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -1106,6 +1106,12 @@ void ocfs2_clear_inode(struct inode *inode) oi->ip_last_trans = 0; oi->ip_dir_start_lookup = 0; oi->ip_blkno = 0ULL; + + /* + * ip_jinode is used to track txns against this inode. We ensure that + * the journal is flushed before journal shutdown. Thus it is safe to + * have inodes get cleaned up after journal shutdown. + */ jbd2_journal_release_jbd_inode(OCFS2_SB(inode->i_sb)->journal->j_journal, &oi->ip_jinode); diff --git a/fs/ocfs2/journal.c b/fs/ocfs2/journal.c index 81e40677eecb..99fe9d584f3c 100644 --- a/fs/ocfs2/journal.c +++ b/fs/ocfs2/journal.c @@ -690,6 +690,7 @@ void ocfs2_journal_shutdown(struct ocfs2_super *osb) /* Shutdown the kernel journal system */ jbd2_journal_destroy(journal->j_journal); + journal->j_journal = NULL; OCFS2_I(inode)->ip_open_count--; diff --git a/fs/ocfs2/mmap.c b/fs/ocfs2/mmap.c index 3dc18d67557c..eea1d24713ea 100644 --- a/fs/ocfs2/mmap.c +++ b/fs/ocfs2/mmap.c @@ -113,7 +113,11 @@ static int __ocfs2_page_mkwrite(struct inode *inode, struct buffer_head *di_bh, * ocfs2_write_begin_nolock(). */ if (!PageUptodate(page) || page->mapping != inode->i_mapping) { - ret = -EINVAL; + /* + * the page has been umapped in ocfs2_data_downconvert_worker. + * So return 0 here and let VFS retry. + */ + ret = 0; goto out; } diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index 485a6aa0ad39..f4967e634ffd 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -378,8 +378,8 @@ static int ocfs2_mknod_locked(struct ocfs2_super *osb, } inode = new_inode(dir->i_sb); - if (IS_ERR(inode)) { - status = PTR_ERR(inode); + if (!inode) { + status = -ENOMEM; mlog(ML_ERROR, "new_inode failed!\n"); goto leave; } @@ -491,8 +491,10 @@ leave: brelse(*new_fe_bh); *new_fe_bh = NULL; } - if (inode) + if (inode) { + clear_nlink(inode); iput(inode); + } } mlog_exit(status); diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index a21a465490c4..3fed9e3d8992 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -85,7 +85,7 @@ enum ocfs2_unlock_action { }; /* ocfs2_lock_res->l_flags flags. */ -#define OCFS2_LOCK_ATTACHED (0x00000001) /* have we initialized +#define OCFS2_LOCK_ATTACHED (0x00000001) /* we have initialized * the lvb */ #define OCFS2_LOCK_BUSY (0x00000002) /* we are currently in * dlm_lock */ @@ -473,6 +473,9 @@ static inline int ocfs2_uses_extended_slot_map(struct ocfs2_super *osb) (____gd)->bg_signature); \ } while (0) +#define OCFS2_IS_VALID_XATTR_BLOCK(ptr) \ + (!strcmp((ptr)->xb_signature, OCFS2_XATTR_BLOCK_SIGNATURE)) + static inline unsigned long ino_from_blkno(struct super_block *sb, u64 blkno) { diff --git a/fs/ocfs2/ocfs2_fs.h b/fs/ocfs2/ocfs2_fs.h index f24ce3d3f956..5e0c0d0aef7d 100644 --- a/fs/ocfs2/ocfs2_fs.h +++ b/fs/ocfs2/ocfs2_fs.h @@ -86,7 +86,8 @@ #define OCFS2_CLEAR_INCOMPAT_FEATURE(sb,mask) \ OCFS2_SB(sb)->s_feature_incompat &= ~(mask) -#define OCFS2_FEATURE_COMPAT_SUPP OCFS2_FEATURE_COMPAT_BACKUP_SB +#define OCFS2_FEATURE_COMPAT_SUPP (OCFS2_FEATURE_COMPAT_BACKUP_SB \ + | OCFS2_FEATURE_COMPAT_JBD2_SB) #define OCFS2_FEATURE_INCOMPAT_SUPP (OCFS2_FEATURE_INCOMPAT_LOCAL_MOUNT \ | OCFS2_FEATURE_INCOMPAT_SPARSE_ALLOC \ | OCFS2_FEATURE_INCOMPAT_INLINE_DATA \ @@ -152,6 +153,11 @@ */ #define OCFS2_FEATURE_COMPAT_BACKUP_SB 0x0001 +/* + * The filesystem will correctly handle journal feature bits. + */ +#define OCFS2_FEATURE_COMPAT_JBD2_SB 0x0002 + /* * Unwritten extents support. */ @@ -742,12 +748,12 @@ struct ocfs2_group_desc */ struct ocfs2_xattr_entry { __le32 xe_name_hash; /* hash value of xattr prefix+suffix. */ - __le16 xe_name_offset; /* byte offset from the 1st etnry in the local + __le16 xe_name_offset; /* byte offset from the 1st entry in the local xattr storage(inode, xattr block or xattr bucket). */ __u8 xe_name_len; /* xattr name len, does't include prefix. */ - __u8 xe_type; /* the low 7 bits indicates the name prefix's - * type and the highest 1 bits indicate whether + __u8 xe_type; /* the low 7 bits indicate the name prefix + * type and the highest bit indicates whether * the EA is stored in the local storage. */ __le64 xe_value_size; /* real xattr value length. */ }; @@ -766,9 +772,10 @@ struct ocfs2_xattr_header { xattr. */ __le16 xh_name_value_len; /* total length of name/value length in this bucket. */ - __le16 xh_num_buckets; /* bucket nums in one extent - record, only valid in the - first bucket. */ + __le16 xh_num_buckets; /* Number of xattr buckets + in this extent record, + only valid in the first + bucket. */ __le64 xh_csum; struct ocfs2_xattr_entry xh_entries[0]; /* xattr entry list. */ }; @@ -776,8 +783,8 @@ struct ocfs2_xattr_header { /* * On disk structure for xattr value root. * - * It is used when one extended attribute's size is larger, and we will save it - * in an outside cluster. It will stored in a b-tree like file content. + * When an xattr's value is large enough, it is stored in an external + * b-tree like file data. The xattr value root points to this structure. */ struct ocfs2_xattr_value_root { /*00*/ __le32 xr_clusters; /* clusters covered by xattr value. */ diff --git a/fs/ocfs2/stack_user.c b/fs/ocfs2/stack_user.c index faec2d879357..9b76d41a8ac6 100644 --- a/fs/ocfs2/stack_user.c +++ b/fs/ocfs2/stack_user.c @@ -740,6 +740,9 @@ static int user_dlm_lock_status(union ocfs2_dlm_lksb *lksb) static void *user_dlm_lvb(union ocfs2_dlm_lksb *lksb) { + if (!lksb->lksb_fsdlm.sb_lvbptr) + lksb->lksb_fsdlm.sb_lvbptr = (char *)lksb + + sizeof(struct dlm_lksb); return (void *)(lksb->lksb_fsdlm.sb_lvbptr); } diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 802c41492214..74d7367ade13 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -3,25 +3,20 @@ * * xattr.c * - * Copyright (C) 2008 Oracle. All rights reserved. + * Copyright (C) 2004, 2008 Oracle. All rights reserved. * * CREDITS: - * Lots of code in this file is taken from ext3. + * Lots of code in this file is copy from linux/fs/ext3/xattr.c. + * Copyright (C) 2001-2003 Andreas Gruenbacher, * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. + * License version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write to the - * Free Software Foundation, Inc., 59 Temple Place - Suite 330, - * Boston, MA 021110-1307, USA. */ #include @@ -83,7 +78,7 @@ struct xattr_handler *ocfs2_xattr_handlers[] = { NULL }; -static struct xattr_handler *ocfs2_xattr_handler_map[] = { +static struct xattr_handler *ocfs2_xattr_handler_map[OCFS2_XATTR_MAX] = { [OCFS2_XATTR_INDEX_USER] = &ocfs2_xattr_user_handler, [OCFS2_XATTR_INDEX_TRUSTED] = &ocfs2_xattr_trusted_handler, }; @@ -116,6 +111,10 @@ static int ocfs2_xattr_bucket_get_name_value(struct inode *inode, int *block_off, int *new_offset); +static int ocfs2_xattr_block_find(struct inode *inode, + int name_index, + const char *name, + struct ocfs2_xattr_search *xs); static int ocfs2_xattr_index_block_find(struct inode *inode, struct buffer_head *root_bh, int name_index, @@ -137,6 +136,24 @@ static int ocfs2_xattr_set_entry_index_block(struct inode *inode, static int ocfs2_delete_xattr_index_block(struct inode *inode, struct buffer_head *xb_bh); +static inline u16 ocfs2_xattr_buckets_per_cluster(struct ocfs2_super *osb) +{ + return (1 << osb->s_clustersize_bits) / OCFS2_XATTR_BUCKET_SIZE; +} + +static inline u16 ocfs2_blocks_per_xattr_bucket(struct super_block *sb) +{ + return OCFS2_XATTR_BUCKET_SIZE / (1 << sb->s_blocksize_bits); +} + +static inline u16 ocfs2_xattr_max_xe_in_bucket(struct super_block *sb) +{ + u16 len = sb->s_blocksize - + offsetof(struct ocfs2_xattr_header, xh_entries); + + return len / sizeof(struct ocfs2_xattr_entry); +} + static inline const char *ocfs2_xattr_prefix(int name_index) { struct xattr_handler *handler = NULL; @@ -542,14 +559,12 @@ static int ocfs2_xattr_block_list(struct inode *inode, mlog_errno(ret); return ret; } - /*Verify the signature of xattr block*/ - if (memcmp((void *)blk_bh->b_data, OCFS2_XATTR_BLOCK_SIGNATURE, - strlen(OCFS2_XATTR_BLOCK_SIGNATURE))) { - ret = -EFAULT; - goto cleanup; - } xb = (struct ocfs2_xattr_block *)blk_bh->b_data; + if (!OCFS2_IS_VALID_XATTR_BLOCK(xb)) { + ret = -EIO; + goto cleanup; + } if (!(le16_to_cpu(xb->xb_flags) & OCFS2_XATTR_INDEXED)) { struct ocfs2_xattr_header *header = &xb->xb_attrs.xb_header; @@ -749,47 +764,25 @@ static int ocfs2_xattr_block_get(struct inode *inode, size_t buffer_size, struct ocfs2_xattr_search *xs) { - struct ocfs2_dinode *di = (struct ocfs2_dinode *)xs->inode_bh->b_data; - struct buffer_head *blk_bh = NULL; struct ocfs2_xattr_block *xb; struct ocfs2_xattr_value_root *xv; size_t size; int ret = -ENODATA, name_offset, name_len, block_off, i; - if (!di->i_xattr_loc) - return ret; - memset(&xs->bucket, 0, sizeof(xs->bucket)); - ret = ocfs2_read_block(inode, le64_to_cpu(di->i_xattr_loc), &blk_bh); - if (ret < 0) { + ret = ocfs2_xattr_block_find(inode, name_index, name, xs); + if (ret) { mlog_errno(ret); - return ret; - } - /*Verify the signature of xattr block*/ - if (memcmp((void *)blk_bh->b_data, OCFS2_XATTR_BLOCK_SIGNATURE, - strlen(OCFS2_XATTR_BLOCK_SIGNATURE))) { - ret = -EFAULT; goto cleanup; } - xs->xattr_bh = blk_bh; - xb = (struct ocfs2_xattr_block *)blk_bh->b_data; - - if (!(le16_to_cpu(xb->xb_flags) & OCFS2_XATTR_INDEXED)) { - xs->header = &xb->xb_attrs.xb_header; - xs->base = (void *)xs->header; - xs->end = (void *)(blk_bh->b_data) + blk_bh->b_size; - xs->here = xs->header->xh_entries; - - ret = ocfs2_xattr_find_entry(name_index, name, xs); - } else - ret = ocfs2_xattr_index_block_find(inode, blk_bh, - name_index, - name, xs); - - if (ret) + if (xs->not_found) { + ret = -ENODATA; goto cleanup; + } + + xb = (struct ocfs2_xattr_block *)xs->xattr_bh->b_data; size = le64_to_cpu(xs->here->xe_value_size); if (buffer) { ret = -ERANGE; @@ -828,7 +821,8 @@ cleanup: brelse(xs->bucket.bhs[i]); memset(&xs->bucket, 0, sizeof(xs->bucket)); - brelse(blk_bh); + brelse(xs->xattr_bh); + xs->xattr_bh = NULL; return ret; } @@ -837,11 +831,11 @@ cleanup: * Copy an extended attribute into the buffer provided. * Buffer is NULL to compute the size of buffer required. */ -int ocfs2_xattr_get(struct inode *inode, - int name_index, - const char *name, - void *buffer, - size_t buffer_size) +static int ocfs2_xattr_get(struct inode *inode, + int name_index, + const char *name, + void *buffer, + size_t buffer_size) { int ret; struct ocfs2_dinode *di = NULL; @@ -871,7 +865,7 @@ int ocfs2_xattr_get(struct inode *inode, down_read(&oi->ip_xattr_sem); ret = ocfs2_xattr_ibody_get(inode, name_index, name, buffer, buffer_size, &xis); - if (ret == -ENODATA) + if (ret == -ENODATA && di->i_xattr_loc) ret = ocfs2_xattr_block_get(inode, name_index, name, buffer, buffer_size, &xbs); up_read(&oi->ip_xattr_sem); @@ -1229,7 +1223,7 @@ static int ocfs2_xattr_set_entry(struct inode *inode, free = min_offs - ((void *)last - xs->base) - sizeof(__u32); if (free < 0) - return -EFAULT; + return -EIO; if (!xs->not_found) { size_t size = 0; @@ -1514,10 +1508,9 @@ static int ocfs2_xattr_free_block(struct inode *inode, goto out; } - /*Verify the signature of xattr block*/ - if (memcmp((void *)blk_bh->b_data, OCFS2_XATTR_BLOCK_SIGNATURE, - strlen(OCFS2_XATTR_BLOCK_SIGNATURE))) { - ret = -EFAULT; + xb = (struct ocfs2_xattr_block *)blk_bh->b_data; + if (!OCFS2_IS_VALID_XATTR_BLOCK(xb)) { + ret = -EIO; goto out; } @@ -1527,7 +1520,6 @@ static int ocfs2_xattr_free_block(struct inode *inode, goto out; } - xb = (struct ocfs2_xattr_block *)blk_bh->b_data; blk = le64_to_cpu(xb->xb_blkno); bit = le16_to_cpu(xb->xb_suballoc_bit); bg_blkno = ocfs2_which_suballoc_group(blk, bit); @@ -1771,15 +1763,14 @@ static int ocfs2_xattr_block_find(struct inode *inode, mlog_errno(ret); return ret; } - /*Verify the signature of xattr block*/ - if (memcmp((void *)blk_bh->b_data, OCFS2_XATTR_BLOCK_SIGNATURE, - strlen(OCFS2_XATTR_BLOCK_SIGNATURE))) { - ret = -EFAULT; - goto cleanup; + + xb = (struct ocfs2_xattr_block *)blk_bh->b_data; + if (!OCFS2_IS_VALID_XATTR_BLOCK(xb)) { + ret = -EIO; + goto cleanup; } xs->xattr_bh = blk_bh; - xb = (struct ocfs2_xattr_block *)blk_bh->b_data; if (!(le16_to_cpu(xb->xb_flags) & OCFS2_XATTR_INDEXED)) { xs->header = &xb->xb_attrs.xb_header; @@ -1805,52 +1796,6 @@ cleanup: return ret; } -/* - * When all the xattrs are deleted from index btree, the ocfs2_xattr_tree - * will be erased and ocfs2_xattr_block will have its ocfs2_xattr_header - * re-initialized. - */ -static int ocfs2_restore_xattr_block(struct inode *inode, - struct ocfs2_xattr_search *xs) -{ - int ret; - handle_t *handle; - struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); - struct ocfs2_xattr_block *xb = - (struct ocfs2_xattr_block *)xs->xattr_bh->b_data; - struct ocfs2_extent_list *el = &xb->xb_attrs.xb_root.xt_list; - u16 xb_flags = le16_to_cpu(xb->xb_flags); - - BUG_ON(!(xb_flags & OCFS2_XATTR_INDEXED) || - le16_to_cpu(el->l_next_free_rec) != 0); - - handle = ocfs2_start_trans(osb, OCFS2_XATTR_BLOCK_UPDATE_CREDITS); - if (IS_ERR(handle)) { - ret = PTR_ERR(handle); - handle = NULL; - goto out; - } - - ret = ocfs2_journal_access(handle, inode, xs->xattr_bh, - OCFS2_JOURNAL_ACCESS_WRITE); - if (ret < 0) { - mlog_errno(ret); - goto out_commit; - } - - memset(&xb->xb_attrs, 0, inode->i_sb->s_blocksize - - offsetof(struct ocfs2_xattr_block, xb_attrs)); - - xb->xb_flags = cpu_to_le16(xb_flags & ~OCFS2_XATTR_INDEXED); - - ocfs2_journal_dirty(handle, xs->xattr_bh); - -out_commit: - ocfs2_commit_trans(osb, handle); -out: - return ret; -} - /* * ocfs2_xattr_block_set() * @@ -1961,8 +1906,6 @@ out: } ret = ocfs2_xattr_set_entry_index_block(inode, xi, xs); - if (!ret && xblk->xb_attrs.xb_root.xt_list.l_next_free_rec == 0) - ret = ocfs2_restore_xattr_block(inode, xs); end: @@ -2398,7 +2341,8 @@ static int ocfs2_xattr_index_block_find(struct inode *inode, BUG_ON(p_blkno == 0 || num_clusters == 0 || first_hash > name_hash); mlog(0, "find xattr extent rec %u clusters from %llu, the first hash " - "in the rec is %u\n", num_clusters, p_blkno, first_hash); + "in the rec is %u\n", num_clusters, (unsigned long long)p_blkno, + first_hash); ret = ocfs2_xattr_bucket_find(inode, name_index, name, name_hash, p_blkno, first_hash, num_clusters, xs); @@ -2422,7 +2366,7 @@ static int ocfs2_iterate_xattr_buckets(struct inode *inode, memset(&bucket, 0, sizeof(bucket)); mlog(0, "iterating xattr buckets in %u clusters starting from %llu\n", - clusters, blkno); + clusters, (unsigned long long)blkno); for (i = 0; i < num_buckets; i++, blkno += blk_per_bucket) { ret = ocfs2_read_blocks(inode, blkno, blk_per_bucket, @@ -2440,7 +2384,8 @@ static int ocfs2_iterate_xattr_buckets(struct inode *inode, if (i == 0) num_buckets = le16_to_cpu(bucket.xh->xh_num_buckets); - mlog(0, "iterating xattr bucket %llu, first hash %u\n", blkno, + mlog(0, "iterating xattr bucket %llu, first hash %u\n", + (unsigned long long)blkno, le32_to_cpu(bucket.xh->xh_entries[0].xe_name_hash)); if (func) { ret = func(inode, &bucket, para); @@ -2700,9 +2645,9 @@ static int ocfs2_xattr_update_xattr_search(struct inode *inode, return ret; } - i = xs->here - old_xh->xh_entries; - xs->here = &xs->header->xh_entries[i]; } + i = xs->here - old_xh->xh_entries; + xs->here = &xs->header->xh_entries[i]; } return ret; @@ -2776,7 +2721,8 @@ static int ocfs2_xattr_create_index_block(struct inode *inode, */ blkno = ocfs2_clusters_to_blocks(inode->i_sb, bit_off); - mlog(0, "allocate 1 cluster from %llu to xattr block\n", blkno); + mlog(0, "allocate 1 cluster from %llu to xattr block\n", + (unsigned long long)blkno); xh_bh = sb_getblk(inode->i_sb, blkno); if (!xh_bh) { @@ -2818,7 +2764,11 @@ static int ocfs2_xattr_create_index_block(struct inode *inode, if (data_bh) ocfs2_journal_dirty(handle, data_bh); - ocfs2_xattr_update_xattr_search(inode, xs, xb_bh, xh_bh); + ret = ocfs2_xattr_update_xattr_search(inode, xs, xb_bh, xh_bh); + if (ret) { + mlog_errno(ret); + goto out_commit; + } /* Change from ocfs2_xattr_header to ocfs2_xattr_tree_root */ memset(&xb->xb_attrs, 0, inode->i_sb->s_blocksize - @@ -2941,8 +2891,8 @@ static int ocfs2_defrag_xattr_bucket(struct inode *inode, mlog(0, "adjust xattr bucket in %llu, count = %u, " "xh_free_start = %u, xh_name_value_len = %u.\n", - blkno, le16_to_cpu(xh->xh_count), xh_free_start, - le16_to_cpu(xh->xh_name_value_len)); + (unsigned long long)blkno, le16_to_cpu(xh->xh_count), + xh_free_start, le16_to_cpu(xh->xh_name_value_len)); /* * sort all the entries by their offset. @@ -3058,7 +3008,7 @@ static int ocfs2_mv_xattr_bucket_cross_cluster(struct inode *inode, prev_blkno += (num_clusters - 1) * bpc + bpc / 2; mlog(0, "move half of xattrs in cluster %llu to %llu\n", - prev_blkno, new_blkno); + (unsigned long long)prev_blkno, (unsigned long long)new_blkno); /* * We need to update the 1st half of the new cluster and @@ -3168,26 +3118,74 @@ static int ocfs2_read_xattr_bucket(struct inode *inode, } /* - * Move half num of the xattrs in old bucket(blk) to new bucket(new_blk). + * Find the suitable pos when we divide a bucket into 2. + * We have to make sure the xattrs with the same hash value exist + * in the same bucket. + * + * If this ocfs2_xattr_header covers more than one hash value, find a + * place where the hash value changes. Try to find the most even split. + * The most common case is that all entries have different hash values, + * and the first check we make will find a place to split. + */ +static int ocfs2_xattr_find_divide_pos(struct ocfs2_xattr_header *xh) +{ + struct ocfs2_xattr_entry *entries = xh->xh_entries; + int count = le16_to_cpu(xh->xh_count); + int delta, middle = count / 2; + + /* + * We start at the middle. Each step gets farther away in both + * directions. We therefore hit the change in hash value + * nearest to the middle. Note that this loop does not execute for + * count < 2. + */ + for (delta = 0; delta < middle; delta++) { + /* Let's check delta earlier than middle */ + if (cmp_xe(&entries[middle - delta - 1], + &entries[middle - delta])) + return middle - delta; + + /* For even counts, don't walk off the end */ + if ((middle + delta + 1) == count) + continue; + + /* Now try delta past middle */ + if (cmp_xe(&entries[middle + delta], + &entries[middle + delta + 1])) + return middle + delta + 1; + } + + /* Every entry had the same hash */ + return count; +} + +/* + * Move some xattrs in old bucket(blk) to new bucket(new_blk). * first_hash will record the 1st hash of the new bucket. + * + * Normally half of the xattrs will be moved. But we have to make + * sure that the xattrs with the same hash value are stored in the + * same bucket. If all the xattrs in this bucket have the same hash + * value, the new bucket will be initialized as an empty one and the + * first_hash will be initialized as (hash_value+1). */ -static int ocfs2_half_xattr_bucket(struct inode *inode, - handle_t *handle, - u64 blk, - u64 new_blk, - u32 *first_hash, - int new_bucket_head) +static int ocfs2_divide_xattr_bucket(struct inode *inode, + handle_t *handle, + u64 blk, + u64 new_blk, + u32 *first_hash, + int new_bucket_head) { int ret, i; - u16 count, start, len, name_value_len, xe_len, name_offset; + int count, start, len, name_value_len = 0, xe_len, name_offset = 0; u16 blk_per_bucket = ocfs2_blocks_per_xattr_bucket(inode->i_sb); struct buffer_head **s_bhs, **t_bhs = NULL; struct ocfs2_xattr_header *xh; struct ocfs2_xattr_entry *xe; int blocksize = inode->i_sb->s_blocksize; - mlog(0, "move half of xattrs from bucket %llu to %llu\n", - blk, new_blk); + mlog(0, "move some of xattrs from bucket %llu to %llu\n", + (unsigned long long)blk, (unsigned long long)new_blk); s_bhs = kcalloc(blk_per_bucket, sizeof(struct buffer_head *), GFP_NOFS); if (!s_bhs) @@ -3220,21 +3218,44 @@ static int ocfs2_half_xattr_bucket(struct inode *inode, for (i = 0; i < blk_per_bucket; i++) { ret = ocfs2_journal_access(handle, inode, t_bhs[i], - OCFS2_JOURNAL_ACCESS_CREATE); + new_bucket_head ? + OCFS2_JOURNAL_ACCESS_CREATE : + OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); goto out; } } + xh = (struct ocfs2_xattr_header *)s_bhs[0]->b_data; + count = le16_to_cpu(xh->xh_count); + start = ocfs2_xattr_find_divide_pos(xh); + + if (start == count) { + xe = &xh->xh_entries[start-1]; + + /* + * initialized a new empty bucket here. + * The hash value is set as one larger than + * that of the last entry in the previous bucket. + */ + for (i = 0; i < blk_per_bucket; i++) + memset(t_bhs[i]->b_data, 0, blocksize); + + xh = (struct ocfs2_xattr_header *)t_bhs[0]->b_data; + xh->xh_free_start = cpu_to_le16(blocksize); + xh->xh_entries[0].xe_name_hash = xe->xe_name_hash; + le32_add_cpu(&xh->xh_entries[0].xe_name_hash, 1); + + goto set_num_buckets; + } + /* copy the whole bucket to the new first. */ for (i = 0; i < blk_per_bucket; i++) memcpy(t_bhs[i]->b_data, s_bhs[i]->b_data, blocksize); /* update the new bucket. */ xh = (struct ocfs2_xattr_header *)t_bhs[0]->b_data; - count = le16_to_cpu(xh->xh_count); - start = count / 2; /* * Calculate the total name/value len and xh_free_start for @@ -3291,6 +3312,7 @@ static int ocfs2_half_xattr_bucket(struct inode *inode, xh->xh_free_start = xe->xe_name_offset; } +set_num_buckets: /* set xh->xh_num_buckets for the new xh. */ if (new_bucket_head) xh->xh_num_buckets = cpu_to_le16(1); @@ -3308,9 +3330,13 @@ static int ocfs2_half_xattr_bucket(struct inode *inode, *first_hash = le32_to_cpu(xh->xh_entries[0].xe_name_hash); /* - * Now only update the 1st block of the old bucket. - * Please note that the entry has been sorted already above. + * Now only update the 1st block of the old bucket. If we + * just added a new empty bucket, there is no need to modify + * it. */ + if (start == count) + goto out; + xh = (struct ocfs2_xattr_header *)s_bhs[0]->b_data; memset(&xh->xh_entries[start], 0, sizeof(struct ocfs2_xattr_entry) * (count - start)); @@ -3358,7 +3384,8 @@ static int ocfs2_cp_xattr_bucket(struct inode *inode, BUG_ON(s_blkno == t_blkno); mlog(0, "cp bucket %llu to %llu, target is %d\n", - s_blkno, t_blkno, t_is_new); + (unsigned long long)s_blkno, (unsigned long long)t_blkno, + t_is_new); s_bhs = kzalloc(sizeof(struct buffer_head *) * blk_per_bucket, GFP_NOFS); @@ -3382,6 +3409,8 @@ static int ocfs2_cp_xattr_bucket(struct inode *inode, for (i = 0; i < blk_per_bucket; i++) { ret = ocfs2_journal_access(handle, inode, t_bhs[i], + t_is_new ? + OCFS2_JOURNAL_ACCESS_CREATE : OCFS2_JOURNAL_ACCESS_WRITE); if (ret) goto out; @@ -3428,7 +3457,8 @@ static int ocfs2_cp_xattr_cluster(struct inode *inode, struct ocfs2_xattr_header *xh; u64 to_blk_start = to_blk; - mlog(0, "cp xattrs from cluster %llu to %llu\n", src_blk, to_blk); + mlog(0, "cp xattrs from cluster %llu to %llu\n", + (unsigned long long)src_blk, (unsigned long long)to_blk); /* * We need to update the new cluster and 1 more for the update of @@ -3493,15 +3523,15 @@ out: } /* - * Move half of the xattrs in this cluster to the new cluster. + * Move some xattrs in this cluster to the new cluster. * This function should only be called when bucket size == cluster size. * Otherwise ocfs2_mv_xattr_bucket_cross_cluster should be used instead. */ -static int ocfs2_half_xattr_cluster(struct inode *inode, - handle_t *handle, - u64 prev_blk, - u64 new_blk, - u32 *first_hash) +static int ocfs2_divide_xattr_cluster(struct inode *inode, + handle_t *handle, + u64 prev_blk, + u64 new_blk, + u32 *first_hash) { u16 blk_per_bucket = ocfs2_blocks_per_xattr_bucket(inode->i_sb); int ret, credits = 2 * blk_per_bucket; @@ -3515,8 +3545,8 @@ static int ocfs2_half_xattr_cluster(struct inode *inode, } /* Move half of the xattr in start_blk to the next bucket. */ - return ocfs2_half_xattr_bucket(inode, handle, prev_blk, - new_blk, first_hash, 1); + return ocfs2_divide_xattr_bucket(inode, handle, prev_blk, + new_blk, first_hash, 1); } /* @@ -3559,7 +3589,8 @@ static int ocfs2_adjust_xattr_cross_cluster(struct inode *inode, int bpc = ocfs2_clusters_to_blocks(inode->i_sb, 1); mlog(0, "adjust xattrs from cluster %llu len %u to %llu\n", - prev_blk, prev_clusters, new_blk); + (unsigned long long)prev_blk, prev_clusters, + (unsigned long long)new_blk); if (ocfs2_xattr_buckets_per_cluster(OCFS2_SB(inode->i_sb)) > 1) ret = ocfs2_mv_xattr_bucket_cross_cluster(inode, @@ -3578,9 +3609,9 @@ static int ocfs2_adjust_xattr_cross_cluster(struct inode *inode, last_blk, new_blk, v_start); else { - ret = ocfs2_half_xattr_cluster(inode, handle, - last_blk, new_blk, - v_start); + ret = ocfs2_divide_xattr_cluster(inode, handle, + last_blk, new_blk, + v_start); if ((*header_bh)->b_blocknr == last_blk && extend) *extend = 0; @@ -3629,7 +3660,7 @@ static int ocfs2_add_new_xattr_cluster(struct inode *inode, mlog(0, "Add new xattr cluster for %llu, previous xattr hash = %u, " "previous xattr blkno = %llu\n", (unsigned long long)OCFS2_I(inode)->ip_blkno, - prev_cpos, prev_blkno); + prev_cpos, (unsigned long long)prev_blkno); ocfs2_init_xattr_tree_extent_tree(&et, inode, root_bh); @@ -3716,7 +3747,7 @@ static int ocfs2_add_new_xattr_cluster(struct inode *inode, } } mlog(0, "Insert %u clusters at block %llu for xattr at %u\n", - num_bits, block, v_start); + num_bits, (unsigned long long)block, v_start); ret = ocfs2_insert_extent(osb, handle, inode, &et, v_start, block, num_bits, 0, meta_ac); if (ret < 0) { @@ -3761,7 +3792,7 @@ static int ocfs2_extend_xattr_bucket(struct inode *inode, u16 bucket = le16_to_cpu(first_xh->xh_num_buckets); mlog(0, "extend xattr bucket in %llu, xattr extend rec starting " - "from %llu, len = %u\n", start_blk, + "from %llu, len = %u\n", (unsigned long long)start_blk, (unsigned long long)first_bh->b_blocknr, num_clusters); BUG_ON(bucket >= num_buckets); @@ -3797,8 +3828,8 @@ static int ocfs2_extend_xattr_bucket(struct inode *inode, } /* Move half of the xattr in start_blk to the next bucket. */ - ret = ocfs2_half_xattr_bucket(inode, handle, start_blk, - start_blk + blk_per_bucket, NULL, 0); + ret = ocfs2_divide_xattr_bucket(inode, handle, start_blk, + start_blk + blk_per_bucket, NULL, 0); le16_add_cpu(&first_xh->xh_num_buckets, 1); ocfs2_journal_dirty(handle, first_bh); @@ -4146,7 +4177,7 @@ static int ocfs2_xattr_value_update_size(struct inode *inode, handle_t *handle = NULL; handle = ocfs2_start_trans(osb, 1); - if (handle == NULL) { + if (IS_ERR(handle)) { ret = -ENOMEM; mlog_errno(ret); goto out; @@ -4313,7 +4344,7 @@ static int ocfs2_rm_xattr_cluster(struct inode *inode, } handle = ocfs2_start_trans(osb, OCFS2_REMOVE_EXTENT_CREDITS); - if (handle == NULL) { + if (IS_ERR(handle)) { ret = -ENOMEM; mlog_errno(ret); goto out; @@ -4489,11 +4520,21 @@ out: return ret; } -/* check whether the xattr bucket is filled up with the same hash value. */ +/* + * check whether the xattr bucket is filled up with the same hash value. + * If we want to insert the xattr with the same hash, return -ENOSPC. + * If we want to insert a xattr with different hash value, go ahead + * and ocfs2_divide_xattr_bucket will handle this. + */ static int ocfs2_check_xattr_bucket_collision(struct inode *inode, - struct ocfs2_xattr_bucket *bucket) + struct ocfs2_xattr_bucket *bucket, + const char *name) { struct ocfs2_xattr_header *xh = bucket->xh; + u32 name_hash = ocfs2_xattr_name_hash(inode, name, strlen(name)); + + if (name_hash != le32_to_cpu(xh->xh_entries[0].xe_name_hash)) + return 0; if (xh->xh_entries[le16_to_cpu(xh->xh_count) - 1].xe_name_hash == xh->xh_entries[0].xe_name_hash) { @@ -4616,7 +4657,9 @@ try_again: * one bucket's worth, so check it here whether we need to * add a new bucket for the insert. */ - ret = ocfs2_check_xattr_bucket_collision(inode, &xs->bucket); + ret = ocfs2_check_xattr_bucket_collision(inode, + &xs->bucket, + xi->name); if (ret) { mlog_errno(ret); goto out; @@ -4727,14 +4770,11 @@ out: /* * 'trusted' attributes support */ - -#define XATTR_TRUSTED_PREFIX "trusted." - static size_t ocfs2_xattr_trusted_list(struct inode *inode, char *list, size_t list_size, const char *name, size_t name_len) { - const size_t prefix_len = sizeof(XATTR_TRUSTED_PREFIX) - 1; + const size_t prefix_len = XATTR_TRUSTED_PREFIX_LEN; const size_t total_len = prefix_len + name_len + 1; if (list && total_len <= list_size) { @@ -4771,18 +4811,14 @@ struct xattr_handler ocfs2_xattr_trusted_handler = { .set = ocfs2_xattr_trusted_set, }; - /* * 'user' attributes support */ - -#define XATTR_USER_PREFIX "user." - static size_t ocfs2_xattr_user_list(struct inode *inode, char *list, size_t list_size, const char *name, size_t name_len) { - const size_t prefix_len = sizeof(XATTR_USER_PREFIX) - 1; + const size_t prefix_len = XATTR_USER_PREFIX_LEN; const size_t total_len = prefix_len + name_len + 1; struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); diff --git a/fs/ocfs2/xattr.h b/fs/ocfs2/xattr.h index c25c7c62a059..1d8314c7656d 100644 --- a/fs/ocfs2/xattr.h +++ b/fs/ocfs2/xattr.h @@ -3,24 +3,16 @@ * * xattr.h * - * Function prototypes - * - * Copyright (C) 2008 Oracle. All rights reserved. + * Copyright (C) 2004, 2008 Oracle. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. + * License version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write to the - * Free Software Foundation, Inc., 59 Temple Place - Suite 330, - * Boston, MA 021110-1307, USA. */ #ifndef OCFS2_XATTR_H @@ -40,29 +32,11 @@ enum ocfs2_xattr_type { extern struct xattr_handler ocfs2_xattr_user_handler; extern struct xattr_handler ocfs2_xattr_trusted_handler; - -extern ssize_t ocfs2_listxattr(struct dentry *, char *, size_t); -extern int ocfs2_xattr_get(struct inode *, int, const char *, void *, size_t); -extern int ocfs2_xattr_set(struct inode *, int, const char *, const void *, - size_t, int); -extern int ocfs2_xattr_remove(struct inode *inode, struct buffer_head *di_bh); extern struct xattr_handler *ocfs2_xattr_handlers[]; -static inline u16 ocfs2_xattr_buckets_per_cluster(struct ocfs2_super *osb) -{ - return (1 << osb->s_clustersize_bits) / OCFS2_XATTR_BUCKET_SIZE; -} - -static inline u16 ocfs2_blocks_per_xattr_bucket(struct super_block *sb) -{ - return OCFS2_XATTR_BUCKET_SIZE / (1 << sb->s_blocksize_bits); -} - -static inline u16 ocfs2_xattr_max_xe_in_bucket(struct super_block *sb) -{ - u16 len = sb->s_blocksize - - offsetof(struct ocfs2_xattr_header, xh_entries); +ssize_t ocfs2_listxattr(struct dentry *, char *, size_t); +int ocfs2_xattr_set(struct inode *, int, const char *, const void *, + size_t, int); +int ocfs2_xattr_remove(struct inode *, struct buffer_head *); - return len / sizeof(struct ocfs2_xattr_entry); -} #endif /* OCFS2_XATTR_H */ diff --git a/fs/partitions/check.c b/fs/partitions/check.c index 633f7a0ebb2c..6d5b213b8a9b 100644 --- a/fs/partitions/check.c +++ b/fs/partitions/check.c @@ -348,8 +348,8 @@ static ssize_t whole_disk_show(struct device *dev, static DEVICE_ATTR(whole_disk, S_IRUSR | S_IRGRP | S_IROTH, whole_disk_show, NULL); -int add_partition(struct gendisk *disk, int partno, - sector_t start, sector_t len, int flags) +struct hd_struct *add_partition(struct gendisk *disk, int partno, + sector_t start, sector_t len, int flags) { struct hd_struct *p; dev_t devt = MKDEV(0, 0); @@ -361,15 +361,15 @@ int add_partition(struct gendisk *disk, int partno, err = disk_expand_part_tbl(disk, partno); if (err) - return err; + return ERR_PTR(err); ptbl = disk->part_tbl; if (ptbl->part[partno]) - return -EBUSY; + return ERR_PTR(-EBUSY); p = kzalloc(sizeof(*p), GFP_KERNEL); if (!p) - return -ENOMEM; + return ERR_PTR(-EBUSY); if (!init_part_stats(p)) { err = -ENOMEM; @@ -395,7 +395,7 @@ int add_partition(struct gendisk *disk, int partno, err = blk_alloc_devt(p, &devt); if (err) - goto out_free; + goto out_free_stats; pdev->devt = devt; /* delay uevent until 'holders' subdir is created */ @@ -424,18 +424,20 @@ int add_partition(struct gendisk *disk, int partno, if (!ddev->uevent_suppress) kobject_uevent(&pdev->kobj, KOBJ_ADD); - return 0; + return p; +out_free_stats: + free_part_stats(p); out_free: kfree(p); - return err; + return ERR_PTR(err); out_del: kobject_put(p->holder_dir); device_del(pdev); out_put: put_device(pdev); blk_free_devt(devt); - return err; + return ERR_PTR(err); } /* Not exported, helper to add_disk(). */ @@ -566,15 +568,16 @@ int rescan_partitions(struct gendisk *disk, struct block_device *bdev) disk->disk_name, p, (unsigned long long) size); size = get_capacity(disk) - from; } - res = add_partition(disk, p, from, size, state->parts[p].flags); - if (res) { - printk(KERN_ERR " %s: p%d could not be added: %d\n", - disk->disk_name, p, -res); + part = add_partition(disk, p, from, size, + state->parts[p].flags); + if (IS_ERR(part)) { + printk(KERN_ERR " %s: p%d could not be added: %ld\n", + disk->disk_name, p, -PTR_ERR(part)); continue; } #ifdef CONFIG_BLK_DEV_MD if (state->parts[p].flags & ADDPART_FLAG_RAID) - md_autodetect_dev(bdev->bd_dev+p); + md_autodetect_dev(part_to_dev(part)->devt); #endif } kfree(state); diff --git a/fs/pipe.c b/fs/pipe.c index fcba6542b8d0..7aea8b89baac 100644 --- a/fs/pipe.c +++ b/fs/pipe.c @@ -717,14 +717,12 @@ pipe_rdwr_fasync(int fd, struct file *filp, int on) static int pipe_read_release(struct inode *inode, struct file *filp) { - pipe_read_fasync(-1, filp, 0); return pipe_release(inode, 1, 0); } static int pipe_write_release(struct inode *inode, struct file *filp) { - pipe_write_fasync(-1, filp, 0); return pipe_release(inode, 0, 1); } @@ -733,7 +731,6 @@ pipe_rdwr_release(struct inode *inode, struct file *filp) { int decr, decw; - pipe_rdwr_fasync(-1, filp, 0); decr = (filp->f_mode & FMODE_READ) != 0; decw = (filp->f_mode & FMODE_WRITE) != 0; return pipe_release(inode, decr, decw); diff --git a/fs/proc/array.c b/fs/proc/array.c index bb9f4b05703d..6af7fba7abb1 100644 --- a/fs/proc/array.c +++ b/fs/proc/array.c @@ -40,7 +40,7 @@ * * * Alan Cox : security fixes. - * + * * * Al Viro : safe handling of mm_struct * diff --git a/fs/proc/base.c b/fs/proc/base.c index 486cf3fe7139..d4677603c889 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -371,7 +371,7 @@ static int lstats_show_proc(struct seq_file *m, void *v) task->latency_record[i].time, task->latency_record[i].max); for (q = 0; q < LT_BACKTRACEDEPTH; q++) { - char sym[KSYM_NAME_LEN]; + char sym[KSYM_SYMBOL_LEN]; char *c; if (!task->latency_record[i].backtrace[q]) break; diff --git a/fs/proc/proc_sysctl.c b/fs/proc/proc_sysctl.c index 94fcfff6863a..06ed10b7da9e 100644 --- a/fs/proc/proc_sysctl.c +++ b/fs/proc/proc_sysctl.c @@ -31,6 +31,7 @@ static struct inode *proc_sys_make_inode(struct super_block *sb, inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME; inode->i_flags |= S_PRIVATE; /* tell selinux to ignore this inode */ inode->i_mode = table->mode; + inode->i_uid = inode->i_gid = 0; if (!table->child) { inode->i_mode |= S_IFREG; inode->i_op = &proc_sys_inode_operations; diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c index b770c095e45c..3a8bdd7f5756 100644 --- a/fs/proc/task_mmu.c +++ b/fs/proc/task_mmu.c @@ -557,9 +557,9 @@ static u64 swap_pte_to_pagemap_entry(pte_t pte) return swp_type(e) | (swp_offset(e) << MAX_SWAPFILES_SHIFT); } -static unsigned long pte_to_pagemap_entry(pte_t pte) +static u64 pte_to_pagemap_entry(pte_t pte) { - unsigned long pme = 0; + u64 pme = 0; if (is_swap_pte(pte)) pme = PM_PFRAME(swap_pte_to_pagemap_entry(pte)) | PM_PSHIFT(PAGE_SHIFT) | PM_SWAP; diff --git a/fs/proc/uptime.c b/fs/proc/uptime.c index 0c10a0b3f146..df26aa88fa47 100644 --- a/fs/proc/uptime.c +++ b/fs/proc/uptime.c @@ -1,43 +1,45 @@ -#include #include #include #include -#include #include #include -static int uptime_proc_show(struct seq_file *m, void *v) +static int proc_calc_metrics(char *page, char **start, off_t off, + int count, int *eof, int len) +{ + if (len <= off + count) + *eof = 1; + *start = page + off; + len -= off; + if (len > count) + len = count; + if (len < 0) + len = 0; + return len; +} + +static int uptime_read_proc(char *page, char **start, off_t off, int count, + int *eof, void *data) { struct timespec uptime; struct timespec idle; + int len; cputime_t idletime = cputime_add(init_task.utime, init_task.stime); do_posix_clock_monotonic_gettime(&uptime); monotonic_to_bootbased(&uptime); cputime_to_timespec(idletime, &idle); - seq_printf(m, "%lu.%02lu %lu.%02lu\n", + len = sprintf(page, "%lu.%02lu %lu.%02lu\n", (unsigned long) uptime.tv_sec, (uptime.tv_nsec / (NSEC_PER_SEC / 100)), (unsigned long) idle.tv_sec, (idle.tv_nsec / (NSEC_PER_SEC / 100))); - return 0; + return proc_calc_metrics(page, start, off, count, eof, len); } -static int uptime_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, uptime_proc_show, NULL); -} - -static const struct file_operations uptime_proc_fops = { - .open = uptime_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - static int __init proc_uptime_init(void) { - proc_create("uptime", 0, NULL, &uptime_proc_fops); + create_proc_read_entry("uptime", 0, NULL, uptime_read_proc, NULL); return 0; } module_init(proc_uptime_init); diff --git a/fs/splice.c b/fs/splice.c index a1e701c27156..1abab5cee4ba 100644 --- a/fs/splice.c +++ b/fs/splice.c @@ -731,8 +731,8 @@ ssize_t splice_from_pipe(struct pipe_inode_info *pipe, struct file *out, }; /* - * The actor worker might be calling ->prepare_write and - * ->commit_write. Most of the time, these expect i_mutex to + * The actor worker might be calling ->write_begin and + * ->write_end. Most of the time, these expect i_mutex to * be held. Since this may result in an ABBA deadlock with * pipe->inode, we have to order lock acquiry here. */ diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c index 0a6aa2cc78f0..b49884c8c10e 100644 --- a/fs/ubifs/commit.c +++ b/fs/ubifs/commit.c @@ -234,8 +234,8 @@ int ubifs_bg_thread(void *info) int err; struct ubifs_info *c = info; - ubifs_msg("background thread \"%s\" started, PID %d", - c->bgt_name, current->pid); + dbg_msg("background thread \"%s\" started, PID %d", + c->bgt_name, current->pid); set_freezable(); while (1) { diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index 7186400750e7..510ffa0bbda4 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -101,21 +101,24 @@ static void sprintf_key(const struct ubifs_info *c, const union ubifs_key *key, if (c->key_fmt == UBIFS_SIMPLE_KEY_FMT) { switch (type) { case UBIFS_INO_KEY: - sprintf(p, "(%lu, %s)", key_inum(c, key), + sprintf(p, "(%lu, %s)", (unsigned long)key_inum(c, key), get_key_type(type)); break; case UBIFS_DENT_KEY: case UBIFS_XENT_KEY: - sprintf(p, "(%lu, %s, %#08x)", key_inum(c, key), + sprintf(p, "(%lu, %s, %#08x)", + (unsigned long)key_inum(c, key), get_key_type(type), key_hash(c, key)); break; case UBIFS_DATA_KEY: - sprintf(p, "(%lu, %s, %u)", key_inum(c, key), + sprintf(p, "(%lu, %s, %u)", + (unsigned long)key_inum(c, key), get_key_type(type), key_block(c, key)); break; case UBIFS_TRUN_KEY: sprintf(p, "(%lu, %s)", - key_inum(c, key), get_key_type(type)); + (unsigned long)key_inum(c, key), + get_key_type(type)); break; default: sprintf(p, "(bad key type: %#08x, %#08x)", @@ -364,8 +367,8 @@ void dbg_dump_node(const struct ubifs_info *c, const void *node) le32_to_cpu(mst->ihead_lnum)); printk(KERN_DEBUG "\tihead_offs %u\n", le32_to_cpu(mst->ihead_offs)); - printk(KERN_DEBUG "\tindex_size %u\n", - le32_to_cpu(mst->index_size)); + printk(KERN_DEBUG "\tindex_size %llu\n", + (unsigned long long)le64_to_cpu(mst->index_size)); printk(KERN_DEBUG "\tlpt_lnum %u\n", le32_to_cpu(mst->lpt_lnum)); printk(KERN_DEBUG "\tlpt_offs %u\n", @@ -1589,7 +1592,7 @@ static struct fsck_inode *add_inode(struct ubifs_info *c, if (inum > c->highest_inum) { ubifs_err("too high inode number, max. is %lu", - c->highest_inum); + (unsigned long)c->highest_inum); return ERR_PTR(-EINVAL); } @@ -1668,16 +1671,18 @@ static struct fsck_inode *read_add_inode(struct ubifs_info *c, ino_key_init(c, &key, inum); err = ubifs_lookup_level0(c, &key, &znode, &n); if (!err) { - ubifs_err("inode %lu not found in index", inum); + ubifs_err("inode %lu not found in index", (unsigned long)inum); return ERR_PTR(-ENOENT); } else if (err < 0) { - ubifs_err("error %d while looking up inode %lu", err, inum); + ubifs_err("error %d while looking up inode %lu", + err, (unsigned long)inum); return ERR_PTR(err); } zbr = &znode->zbranch[n]; if (zbr->len < UBIFS_INO_NODE_SZ) { - ubifs_err("bad node %lu node length %d", inum, zbr->len); + ubifs_err("bad node %lu node length %d", + (unsigned long)inum, zbr->len); return ERR_PTR(-EINVAL); } @@ -1697,7 +1702,7 @@ static struct fsck_inode *read_add_inode(struct ubifs_info *c, kfree(ino); if (IS_ERR(fscki)) { ubifs_err("error %ld while adding inode %lu node", - PTR_ERR(fscki), inum); + PTR_ERR(fscki), (unsigned long)inum); return fscki; } @@ -1786,7 +1791,8 @@ static int check_leaf(struct ubifs_info *c, struct ubifs_zbranch *zbr, if (IS_ERR(fscki)) { err = PTR_ERR(fscki); ubifs_err("error %d while processing data node and " - "trying to find inode node %lu", err, inum); + "trying to find inode node %lu", + err, (unsigned long)inum); goto out_dump; } @@ -1819,7 +1825,8 @@ static int check_leaf(struct ubifs_info *c, struct ubifs_zbranch *zbr, if (IS_ERR(fscki)) { err = PTR_ERR(fscki); ubifs_err("error %d while processing entry node and " - "trying to find inode node %lu", err, inum); + "trying to find inode node %lu", + err, (unsigned long)inum); goto out_dump; } @@ -1832,7 +1839,7 @@ static int check_leaf(struct ubifs_info *c, struct ubifs_zbranch *zbr, err = PTR_ERR(fscki); ubifs_err("error %d while processing entry node and " "trying to find parent inode node %lu", - err, inum); + err, (unsigned long)inum); goto out_dump; } @@ -1923,7 +1930,8 @@ static int check_inodes(struct ubifs_info *c, struct fsck_data *fsckd) fscki->references != 1) { ubifs_err("directory inode %lu has %d " "direntries which refer it, but " - "should be 1", fscki->inum, + "should be 1", + (unsigned long)fscki->inum, fscki->references); goto out_dump; } @@ -1931,27 +1939,29 @@ static int check_inodes(struct ubifs_info *c, struct fsck_data *fsckd) fscki->references != 0) { ubifs_err("root inode %lu has non-zero (%d) " "direntries which refer it", - fscki->inum, fscki->references); + (unsigned long)fscki->inum, + fscki->references); goto out_dump; } if (fscki->calc_sz != fscki->size) { ubifs_err("directory inode %lu size is %lld, " "but calculated size is %lld", - fscki->inum, fscki->size, - fscki->calc_sz); + (unsigned long)fscki->inum, + fscki->size, fscki->calc_sz); goto out_dump; } if (fscki->calc_cnt != fscki->nlink) { ubifs_err("directory inode %lu nlink is %d, " "but calculated nlink is %d", - fscki->inum, fscki->nlink, - fscki->calc_cnt); + (unsigned long)fscki->inum, + fscki->nlink, fscki->calc_cnt); goto out_dump; } } else { if (fscki->references != fscki->nlink) { ubifs_err("inode %lu nlink is %d, but " - "calculated nlink is %d", fscki->inum, + "calculated nlink is %d", + (unsigned long)fscki->inum, fscki->nlink, fscki->references); goto out_dump; } @@ -1959,20 +1969,21 @@ static int check_inodes(struct ubifs_info *c, struct fsck_data *fsckd) if (fscki->xattr_sz != fscki->calc_xsz) { ubifs_err("inode %lu has xattr size %u, but " "calculated size is %lld", - fscki->inum, fscki->xattr_sz, + (unsigned long)fscki->inum, fscki->xattr_sz, fscki->calc_xsz); goto out_dump; } if (fscki->xattr_cnt != fscki->calc_xcnt) { ubifs_err("inode %lu has %u xattrs, but " - "calculated count is %lld", fscki->inum, + "calculated count is %lld", + (unsigned long)fscki->inum, fscki->xattr_cnt, fscki->calc_xcnt); goto out_dump; } if (fscki->xattr_nms != fscki->calc_xnms) { ubifs_err("inode %lu has xattr names' size %u, but " "calculated names' size is %lld", - fscki->inum, fscki->xattr_nms, + (unsigned long)fscki->inum, fscki->xattr_nms, fscki->calc_xnms); goto out_dump; } @@ -1985,11 +1996,12 @@ out_dump: ino_key_init(c, &key, fscki->inum); err = ubifs_lookup_level0(c, &key, &znode, &n); if (!err) { - ubifs_err("inode %lu not found in index", fscki->inum); + ubifs_err("inode %lu not found in index", + (unsigned long)fscki->inum); return -ENOENT; } else if (err < 0) { ubifs_err("error %d while looking up inode %lu", - err, fscki->inum); + err, (unsigned long)fscki->inum); return err; } @@ -2007,7 +2019,7 @@ out_dump: } ubifs_msg("dump of the inode %lu sitting in LEB %d:%d", - fscki->inum, zbr->lnum, zbr->offs); + (unsigned long)fscki->inum, zbr->lnum, zbr->offs); dbg_dump_node(c, ino); kfree(ino); return -EINVAL; diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index 526c01ec8003..0422c98e1793 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -161,7 +161,7 @@ struct inode *ubifs_new_inode(struct ubifs_info *c, const struct inode *dir, return ERR_PTR(-EINVAL); } ubifs_warn("running out of inode numbers (current %lu, max %d)", - c->highest_inum, INUM_WATERMARK); + (unsigned long)c->highest_inum, INUM_WATERMARK); } inode->i_ino = ++c->highest_inum; @@ -428,7 +428,8 @@ static int ubifs_readdir(struct file *file, void *dirent, filldir_t filldir) dbg_gen("feed '%s', ino %llu, new f_pos %#x", dent->name, (unsigned long long)le64_to_cpu(dent->inum), key_hash_flash(c, &dent->key)); - ubifs_assert(dent->ch.sqnum > ubifs_inode(dir)->creat_sqnum); + ubifs_assert(le64_to_cpu(dent->ch.sqnum) > + ubifs_inode(dir)->creat_sqnum); nm.len = le16_to_cpu(dent->nlen); over = filldir(dirent, dent->name, nm.len, file->f_pos, diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index 51cf511d44d9..2624411d9758 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -72,7 +72,7 @@ static int read_block(struct inode *inode, void *addr, unsigned int block, return err; } - ubifs_assert(dn->ch.sqnum > ubifs_inode(inode)->creat_sqnum); + ubifs_assert(le64_to_cpu(dn->ch.sqnum) > ubifs_inode(inode)->creat_sqnum); len = le32_to_cpu(dn->size); if (len <= 0 || len > UBIFS_BLOCK_SIZE) @@ -626,7 +626,7 @@ static int populate_page(struct ubifs_info *c, struct page *page, dn = bu->buf + (bu->zbranch[nn].offs - offs); - ubifs_assert(dn->ch.sqnum > + ubifs_assert(le64_to_cpu(dn->ch.sqnum) > ubifs_inode(inode)->creat_sqnum); len = le32_to_cpu(dn->size); @@ -691,32 +691,22 @@ out_err: /** * ubifs_do_bulk_read - do bulk-read. * @c: UBIFS file-system description object - * @page1: first page + * @bu: bulk-read information + * @page1: first page to read * * This function returns %1 if the bulk-read is done, otherwise %0 is returned. */ -static int ubifs_do_bulk_read(struct ubifs_info *c, struct page *page1) +static int ubifs_do_bulk_read(struct ubifs_info *c, struct bu_info *bu, + struct page *page1) { pgoff_t offset = page1->index, end_index; struct address_space *mapping = page1->mapping; struct inode *inode = mapping->host; struct ubifs_inode *ui = ubifs_inode(inode); - struct bu_info *bu; int err, page_idx, page_cnt, ret = 0, n = 0; + int allocate = bu->buf ? 0 : 1; loff_t isize; - bu = kmalloc(sizeof(struct bu_info), GFP_NOFS); - if (!bu) - return 0; - - bu->buf_len = c->bulk_read_buf_size; - bu->buf = kmalloc(bu->buf_len, GFP_NOFS); - if (!bu->buf) - goto out_free; - - data_key_init(c, &bu->key, inode->i_ino, - offset << UBIFS_BLOCKS_PER_PAGE_SHIFT); - err = ubifs_tnc_get_bu_keys(c, bu); if (err) goto out_warn; @@ -735,12 +725,25 @@ static int ubifs_do_bulk_read(struct ubifs_info *c, struct page *page1) * together. If all the pages were like this, bulk-read would * reduce performance, so we turn it off for a while. */ - ui->read_in_a_row = 0; - ui->bulk_read = 0; - goto out_free; + goto out_bu_off; } if (bu->cnt) { + if (allocate) { + /* + * Allocate bulk-read buffer depending on how many data + * nodes we are going to read. + */ + bu->buf_len = bu->zbranch[bu->cnt - 1].offs + + bu->zbranch[bu->cnt - 1].len - + bu->zbranch[0].offs; + ubifs_assert(bu->buf_len > 0); + ubifs_assert(bu->buf_len <= c->leb_size); + bu->buf = kmalloc(bu->buf_len, GFP_NOFS | __GFP_NOWARN); + if (!bu->buf) + goto out_bu_off; + } + err = ubifs_tnc_bulk_read(c, bu); if (err) goto out_warn; @@ -779,13 +782,17 @@ static int ubifs_do_bulk_read(struct ubifs_info *c, struct page *page1) ui->last_page_read = offset + page_idx - 1; out_free: - kfree(bu->buf); - kfree(bu); + if (allocate) + kfree(bu->buf); return ret; out_warn: ubifs_warn("ignoring error %d and skipping bulk-read", err); goto out_free; + +out_bu_off: + ui->read_in_a_row = ui->bulk_read = 0; + goto out_free; } /** @@ -803,18 +810,20 @@ static int ubifs_bulk_read(struct page *page) struct ubifs_info *c = inode->i_sb->s_fs_info; struct ubifs_inode *ui = ubifs_inode(inode); pgoff_t index = page->index, last_page_read = ui->last_page_read; - int ret = 0; + struct bu_info *bu; + int err = 0, allocated = 0; ui->last_page_read = index; - if (!c->bulk_read) return 0; + /* - * Bulk-read is protected by ui_mutex, but it is an optimization, so - * don't bother if we cannot lock the mutex. + * Bulk-read is protected by @ui->ui_mutex, but it is an optimization, + * so don't bother if we cannot lock the mutex. */ if (!mutex_trylock(&ui->ui_mutex)) return 0; + if (index != last_page_read + 1) { /* Turn off bulk-read if we stop reading sequentially */ ui->read_in_a_row = 1; @@ -822,6 +831,7 @@ static int ubifs_bulk_read(struct page *page) ui->bulk_read = 0; goto out_unlock; } + if (!ui->bulk_read) { ui->read_in_a_row += 1; if (ui->read_in_a_row < 3) @@ -829,10 +839,35 @@ static int ubifs_bulk_read(struct page *page) /* Three reads in a row, so switch on bulk-read */ ui->bulk_read = 1; } - ret = ubifs_do_bulk_read(c, page); + + /* + * If possible, try to use pre-allocated bulk-read information, which + * is protected by @c->bu_mutex. + */ + if (mutex_trylock(&c->bu_mutex)) + bu = &c->bu; + else { + bu = kmalloc(sizeof(struct bu_info), GFP_NOFS | __GFP_NOWARN); + if (!bu) + goto out_unlock; + + bu->buf = NULL; + allocated = 1; + } + + bu->buf_len = c->max_bu_buf_len; + data_key_init(c, &bu->key, inode->i_ino, + page->index << UBIFS_BLOCKS_PER_PAGE_SHIFT); + err = ubifs_do_bulk_read(c, bu, page); + + if (!allocated) + mutex_unlock(&c->bu_mutex); + else + kfree(bu); + out_unlock: mutex_unlock(&ui->ui_mutex); - return ret; + return err; } static int ubifs_readpage(struct file *file, struct page *page) diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c index 22993f867d19..f91b745908ea 100644 --- a/fs/ubifs/journal.c +++ b/fs/ubifs/journal.c @@ -690,8 +690,9 @@ int ubifs_jnl_write_data(struct ubifs_info *c, const struct inode *inode, int dlen = UBIFS_DATA_NODE_SZ + UBIFS_BLOCK_SIZE * WORST_COMPR_FACTOR; struct ubifs_inode *ui = ubifs_inode(inode); - dbg_jnl("ino %lu, blk %u, len %d, key %s", key_inum(c, key), - key_block(c, key), len, DBGKEY(key)); + dbg_jnl("ino %lu, blk %u, len %d, key %s", + (unsigned long)key_inum(c, key), key_block(c, key), len, + DBGKEY(key)); ubifs_assert(len <= UBIFS_BLOCK_SIZE); data = kmalloc(dlen, GFP_NOFS); @@ -1128,7 +1129,8 @@ int ubifs_jnl_truncate(struct ubifs_info *c, const struct inode *inode, ino_t inum = inode->i_ino; unsigned int blk; - dbg_jnl("ino %lu, size %lld -> %lld", inum, old_size, new_size); + dbg_jnl("ino %lu, size %lld -> %lld", + (unsigned long)inum, old_size, new_size); ubifs_assert(!ui->data_len); ubifs_assert(S_ISREG(inode->i_mode)); ubifs_assert(mutex_is_locked(&ui->ui_mutex)); diff --git a/fs/ubifs/key.h b/fs/ubifs/key.h index 9ee65086f627..3f1f16bc25c9 100644 --- a/fs/ubifs/key.h +++ b/fs/ubifs/key.h @@ -345,7 +345,7 @@ static inline int key_type_flash(const struct ubifs_info *c, const void *k) { const union ubifs_key *key = k; - return le32_to_cpu(key->u32[1]) >> UBIFS_S_KEY_BLOCK_BITS; + return le32_to_cpu(key->j32[1]) >> UBIFS_S_KEY_BLOCK_BITS; } /** @@ -416,7 +416,7 @@ static inline unsigned int key_block_flash(const struct ubifs_info *c, { const union ubifs_key *key = k; - return le32_to_cpu(key->u32[1]) & UBIFS_S_KEY_BLOCK_MASK; + return le32_to_cpu(key->j32[1]) & UBIFS_S_KEY_BLOCK_MASK; } /** diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c index eed5a0025d63..a41434b42785 100644 --- a/fs/ubifs/lpt_commit.c +++ b/fs/ubifs/lpt_commit.c @@ -571,8 +571,6 @@ static struct ubifs_pnode *next_pnode(struct ubifs_info *c, /* We assume here that LEB zero is never an LPT LEB */ if (nnode->nbranch[iip].lnum) return ubifs_get_pnode(c, nnode, iip); - else - return NULL; } /* Go up while can't go right */ diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index 02d3462f4d3e..9bd5a43d4526 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -105,7 +105,7 @@ int ubifs_add_orphan(struct ubifs_info *c, ino_t inum) list_add_tail(&orphan->list, &c->orph_list); list_add_tail(&orphan->new_list, &c->orph_new); spin_unlock(&c->orphan_lock); - dbg_gen("ino %lu", inum); + dbg_gen("ino %lu", (unsigned long)inum); return 0; } @@ -132,14 +132,16 @@ void ubifs_delete_orphan(struct ubifs_info *c, ino_t inum) else { if (o->dnext) { spin_unlock(&c->orphan_lock); - dbg_gen("deleted twice ino %lu", inum); + dbg_gen("deleted twice ino %lu", + (unsigned long)inum); return; } if (o->cnext) { o->dnext = c->orph_dnext; c->orph_dnext = o; spin_unlock(&c->orphan_lock); - dbg_gen("delete later ino %lu", inum); + dbg_gen("delete later ino %lu", + (unsigned long)inum); return; } rb_erase(p, &c->orph_tree); @@ -151,12 +153,12 @@ void ubifs_delete_orphan(struct ubifs_info *c, ino_t inum) } spin_unlock(&c->orphan_lock); kfree(o); - dbg_gen("inum %lu", inum); + dbg_gen("inum %lu", (unsigned long)inum); return; } } spin_unlock(&c->orphan_lock); - dbg_err("missing orphan ino %lu", inum); + dbg_err("missing orphan ino %lu", (unsigned long)inum); dbg_dump_stack(); } @@ -448,7 +450,7 @@ static void erase_deleted(struct ubifs_info *c) rb_erase(&orphan->rb, &c->orph_tree); list_del(&orphan->list); c->tot_orphans -= 1; - dbg_gen("deleting orphan ino %lu", orphan->inum); + dbg_gen("deleting orphan ino %lu", (unsigned long)orphan->inum); kfree(orphan); } c->orph_dnext = NULL; @@ -536,8 +538,8 @@ static int insert_dead_orphan(struct ubifs_info *c, ino_t inum) list_add_tail(&orphan->list, &c->orph_list); orphan->dnext = c->orph_dnext; c->orph_dnext = orphan; - dbg_mnt("ino %lu, new %d, tot %d", - inum, c->new_orphans, c->tot_orphans); + dbg_mnt("ino %lu, new %d, tot %d", (unsigned long)inum, + c->new_orphans, c->tot_orphans); return 0; } @@ -609,7 +611,8 @@ static int do_kill_orphans(struct ubifs_info *c, struct ubifs_scan_leb *sleb, n = (le32_to_cpu(orph->ch.len) - UBIFS_ORPH_NODE_SZ) >> 3; for (i = 0; i < n; i++) { inum = le64_to_cpu(orph->inos[i]); - dbg_rcvry("deleting orphaned inode %lu", inum); + dbg_rcvry("deleting orphaned inode %lu", + (unsigned long)inum); err = ubifs_tnc_remove_ino(c, inum); if (err) return err; @@ -840,8 +843,8 @@ static int dbg_orphan_check(struct ubifs_info *c, struct ubifs_zbranch *zbr, if (inum != ci->last_ino) { /* Lowest node type is the inode node, so it comes first */ if (key_type(c, &zbr->key) != UBIFS_INO_KEY) - ubifs_err("found orphan node ino %lu, type %d", inum, - key_type(c, &zbr->key)); + ubifs_err("found orphan node ino %lu, type %d", + (unsigned long)inum, key_type(c, &zbr->key)); ci->last_ino = inum; ci->tot_inos += 1; err = ubifs_tnc_read_node(c, zbr, ci->node); @@ -853,7 +856,8 @@ static int dbg_orphan_check(struct ubifs_info *c, struct ubifs_zbranch *zbr, /* Must be recorded as an orphan */ if (!dbg_find_check_orphan(&ci->root, inum) && !dbg_find_orphan(c, inum)) { - ubifs_err("missing orphan, ino %lu", inum); + ubifs_err("missing orphan, ino %lu", + (unsigned long)inum); ci->missing += 1; } } diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index 77d26c141cf6..90acac603e63 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -168,12 +168,12 @@ static int write_rcvrd_mst_node(struct ubifs_info *c, struct ubifs_mst_node *mst) { int err = 0, lnum = UBIFS_MST_LNUM, sz = c->mst_node_alsz; - uint32_t save_flags; + __le32 save_flags; dbg_rcvry("recovery"); save_flags = mst->flags; - mst->flags = cpu_to_le32(le32_to_cpu(mst->flags) | UBIFS_MST_RCVRY); + mst->flags |= cpu_to_le32(UBIFS_MST_RCVRY); ubifs_prepare_node(c, mst, UBIFS_MST_NODE_SZ, 1); err = ubi_leb_change(c->ubi, lnum, mst, sz, UBI_SHORTTERM); @@ -1435,13 +1435,13 @@ static int fix_size_in_place(struct ubifs_info *c, struct size_entry *e) err = ubi_leb_change(c->ubi, lnum, c->sbuf, len, UBI_UNKNOWN); if (err) goto out; - dbg_rcvry("inode %lu at %d:%d size %lld -> %lld ", e->inum, lnum, offs, - i_size, e->d_size); + dbg_rcvry("inode %lu at %d:%d size %lld -> %lld ", + (unsigned long)e->inum, lnum, offs, i_size, e->d_size); return 0; out: ubifs_warn("inode %lu failed to fix size %lld -> %lld error %d", - e->inum, e->i_size, e->d_size, err); + (unsigned long)e->inum, e->i_size, e->d_size, err); return err; } @@ -1472,7 +1472,8 @@ int ubifs_recover_size(struct ubifs_info *c) return err; if (err == -ENOENT) { /* Remove data nodes that have no inode */ - dbg_rcvry("removing ino %lu", e->inum); + dbg_rcvry("removing ino %lu", + (unsigned long)e->inum); err = ubifs_tnc_remove_ino(c, e->inum); if (err) return err; @@ -1493,8 +1494,8 @@ int ubifs_recover_size(struct ubifs_info *c) return PTR_ERR(inode); if (inode->i_size < e->d_size) { dbg_rcvry("ino %lu size %lld -> %lld", - e->inum, e->d_size, - inode->i_size); + (unsigned long)e->inum, + e->d_size, inode->i_size); inode->i_size = e->d_size; ubifs_inode(inode)->ui_size = e->d_size; e->inode = inode; diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index 7399692af859..21f7d047c306 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -1065,7 +1065,7 @@ int ubifs_replay_journal(struct ubifs_info *c) ubifs_assert(c->bud_bytes <= c->max_bud_bytes || c->need_recovery); dbg_mnt("finished, log head LEB %d:%d, max_sqnum %llu, " "highest_inum %lu", c->lhead_lnum, c->lhead_offs, c->max_sqnum, - c->highest_inum); + (unsigned long)c->highest_inum); out: destroy_replay_tree(c); destroy_bud_list(c); diff --git a/fs/ubifs/sb.c b/fs/ubifs/sb.c index 2bf753b38889..0f392351dc5a 100644 --- a/fs/ubifs/sb.c +++ b/fs/ubifs/sb.c @@ -81,6 +81,7 @@ static int create_default_filesystem(struct ubifs_info *c) int lpt_lebs, lpt_first, orph_lebs, big_lpt, ino_waste, sup_flags = 0; int min_leb_cnt = UBIFS_MIN_LEB_CNT; uint64_t tmp64, main_bytes; + __le64 tmp_le64; /* Some functions called from here depend on the @c->key_len filed */ c->key_len = UBIFS_SK_LEN; @@ -295,10 +296,10 @@ static int create_default_filesystem(struct ubifs_info *c) ino->ch.node_type = UBIFS_INO_NODE; ino->creat_sqnum = cpu_to_le64(++c->max_sqnum); ino->nlink = cpu_to_le32(2); - tmp = cpu_to_le64(CURRENT_TIME_SEC.tv_sec); - ino->atime_sec = tmp; - ino->ctime_sec = tmp; - ino->mtime_sec = tmp; + tmp_le64 = cpu_to_le64(CURRENT_TIME_SEC.tv_sec); + ino->atime_sec = tmp_le64; + ino->ctime_sec = tmp_le64; + ino->mtime_sec = tmp_le64; ino->atime_nsec = 0; ino->ctime_nsec = 0; ino->mtime_nsec = 0; diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 8780efbf40ac..d80b2aef42b6 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -36,6 +36,12 @@ #include #include "ubifs.h" +/* + * Maximum amount of memory we may 'kmalloc()' without worrying that we are + * allocating too much. + */ +#define UBIFS_KMALLOC_OK (128*1024) + /* Slab cache for UBIFS inodes */ struct kmem_cache *ubifs_inode_slab; @@ -561,18 +567,11 @@ static int init_constants_early(struct ubifs_info *c) * calculations when reporting free space. */ c->leb_overhead = c->leb_size % UBIFS_MAX_DATA_NODE_SZ; - /* Buffer size for bulk-reads */ - c->bulk_read_buf_size = UBIFS_MAX_BULK_READ * UBIFS_MAX_DATA_NODE_SZ; - if (c->bulk_read_buf_size > c->leb_size) - c->bulk_read_buf_size = c->leb_size; - if (c->bulk_read_buf_size > 128 * 1024) { - /* Check if we can kmalloc more than 128KiB */ - void *try = kmalloc(c->bulk_read_buf_size, GFP_KERNEL); - kfree(try); - if (!try) - c->bulk_read_buf_size = 128 * 1024; - } + /* Buffer size for bulk-reads */ + c->max_bu_buf_len = UBIFS_MAX_BULK_READ * UBIFS_MAX_DATA_NODE_SZ; + if (c->max_bu_buf_len > c->leb_size) + c->max_bu_buf_len = c->leb_size; return 0; } @@ -991,6 +990,34 @@ static void destroy_journal(struct ubifs_info *c) free_buds(c); } +/** + * bu_init - initialize bulk-read information. + * @c: UBIFS file-system description object + */ +static void bu_init(struct ubifs_info *c) +{ + ubifs_assert(c->bulk_read == 1); + + if (c->bu.buf) + return; /* Already initialized */ + +again: + c->bu.buf = kmalloc(c->max_bu_buf_len, GFP_KERNEL | __GFP_NOWARN); + if (!c->bu.buf) { + if (c->max_bu_buf_len > UBIFS_KMALLOC_OK) { + c->max_bu_buf_len = UBIFS_KMALLOC_OK; + goto again; + } + + /* Just disable bulk-read */ + ubifs_warn("Cannot allocate %d bytes of memory for bulk-read, " + "disabling it", c->max_bu_buf_len); + c->mount_opts.bulk_read = 1; + c->bulk_read = 0; + return; + } +} + /** * mount_ubifs - mount UBIFS file-system. * @c: UBIFS file-system description object @@ -1059,6 +1086,13 @@ static int mount_ubifs(struct ubifs_info *c) goto out_free; } + if (c->bulk_read == 1) + bu_init(c); + + /* + * We have to check all CRCs, even for data nodes, when we mount the FS + * (specifically, when we are replaying). + */ c->always_chk_crc = 1; err = ubifs_read_superblock(c); @@ -1289,6 +1323,7 @@ out_cbuf: out_dereg: dbg_failure_mode_deregistration(c); out_free: + kfree(c->bu.buf); vfree(c->ileb_buf); vfree(c->sbuf); kfree(c->bottom_up_buf); @@ -1325,10 +1360,11 @@ static void ubifs_umount(struct ubifs_info *c) kfree(c->cbuf); kfree(c->rcvrd_mst_node); kfree(c->mst_node); + kfree(c->bu.buf); + vfree(c->ileb_buf); vfree(c->sbuf); kfree(c->bottom_up_buf); UBIFS_DBG(vfree(c->dbg_buf)); - vfree(c->ileb_buf); dbg_failure_mode_deregistration(c); } @@ -1626,6 +1662,7 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) ubifs_err("invalid or unknown remount parameter"); return err; } + if ((sb->s_flags & MS_RDONLY) && !(*flags & MS_RDONLY)) { err = ubifs_remount_rw(c); if (err) @@ -1633,6 +1670,14 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) } else if (!(sb->s_flags & MS_RDONLY) && (*flags & MS_RDONLY)) ubifs_remount_ro(c); + if (c->bulk_read == 1) + bu_init(c); + else { + dbg_gen("disable bulk-read"); + kfree(c->bu.buf); + c->bu.buf = NULL; + } + return 0; } @@ -1723,6 +1768,7 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) mutex_init(&c->log_mutex); mutex_init(&c->mst_mutex); mutex_init(&c->umount_mutex); + mutex_init(&c->bu_mutex); init_waitqueue_head(&c->cmt_wq); c->buds = RB_ROOT; c->old_idx = RB_ROOT; diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index d27fd918b9c9..6eef5344a145 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -1501,7 +1501,12 @@ out: * @bu: bulk-read parameters and results * * Lookup consecutive data node keys for the same inode that reside - * consecutively in the same LEB. + * consecutively in the same LEB. This function returns zero in case of success + * and a negative error code in case of failure. + * + * Note, if the bulk-read buffer length (@bu->buf_len) is known, this function + * makes sure bulk-read nodes fit the buffer. Otherwise, this function prepares + * maxumum possible amount of nodes for bulk-read. */ int ubifs_tnc_get_bu_keys(struct ubifs_info *c, struct bu_info *bu) { @@ -2677,7 +2682,7 @@ int ubifs_tnc_remove_ino(struct ubifs_info *c, ino_t inum) struct ubifs_dent_node *xent, *pxent = NULL; struct qstr nm = { .name = NULL }; - dbg_tnc("ino %lu", inum); + dbg_tnc("ino %lu", (unsigned long)inum); /* * Walk all extended attribute entries and remove them together with @@ -2697,7 +2702,8 @@ int ubifs_tnc_remove_ino(struct ubifs_info *c, ino_t inum) } xattr_inum = le64_to_cpu(xent->inum); - dbg_tnc("xent '%s', ino %lu", xent->name, xattr_inum); + dbg_tnc("xent '%s', ino %lu", xent->name, + (unsigned long)xattr_inum); nm.name = xent->name; nm.len = le16_to_cpu(xent->nlen); diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index a7bd32fa15b9..46b172560a06 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -753,7 +753,7 @@ struct ubifs_znode { }; /** - * struct bu_info - bulk-read information + * struct bu_info - bulk-read information. * @key: first data node key * @zbranch: zbranches of data nodes to bulk read * @buf: buffer to read into @@ -969,7 +969,10 @@ struct ubifs_mount_opts { * @mst_node: master node * @mst_offs: offset of valid master node * @mst_mutex: protects the master node area, @mst_node, and @mst_offs - * @bulk_read_buf_size: buffer size for bulk-reads + * + * @max_bu_buf_len: maximum bulk-read buffer length + * @bu_mutex: protects the pre-allocated bulk-read buffer and @c->bu + * @bu: pre-allocated bulk-read information * * @log_lebs: number of logical eraseblocks in the log * @log_bytes: log size in bytes @@ -1217,7 +1220,10 @@ struct ubifs_info { struct ubifs_mst_node *mst_node; int mst_offs; struct mutex mst_mutex; - int bulk_read_buf_size; + + int max_bu_buf_len; + struct mutex bu_mutex; + struct bu_info bu; int log_lebs; long long log_bytes; diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 6e74b117aaf0..30ebde490f7f 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -106,6 +106,7 @@ void udf_clear_inode(struct inode *inode) udf_truncate_tail_extent(inode); unlock_kernel(); write_inode_now(inode, 0); + invalidate_inode_buffers(inode); } iinfo = UDF_I(inode); kfree(iinfo->i_ext.i_data); diff --git a/fs/vfat/Makefile b/fs/vfat/Makefile deleted file mode 100644 index 40f2798a4f08..000000000000 --- a/fs/vfat/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for the linux vfat-filesystem routines. -# - -obj-$(CONFIG_VFAT_FS) += vfat.o - -vfat-y := namei.o diff --git a/fs/vfat/namei.c b/fs/vfat/namei.c deleted file mode 100644 index 155c10b4adbd..000000000000 --- a/fs/vfat/namei.c +++ /dev/null @@ -1,1055 +0,0 @@ -/* - * linux/fs/vfat/namei.c - * - * Written 1992,1993 by Werner Almesberger - * - * Windows95/Windows NT compatible extended MSDOS filesystem - * by Gordon Chaffee Copyright (C) 1995. Send bug reports for the - * VFAT filesystem to . Specify - * what file operation caused you trouble and if you can duplicate - * the problem, send a script that demonstrates it. - * - * Short name translation 1999, 2001 by Wolfram Pienkoss - * - * Support Multibyte characters and cleanup by - * OGAWA Hirofumi - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -static int vfat_revalidate(struct dentry *dentry, struct nameidata *nd) -{ - int ret = 1; - - if (!dentry->d_inode && - nd && !(nd->flags & LOOKUP_CONTINUE) && (nd->flags & LOOKUP_CREATE)) - /* - * negative dentry is dropped, in order to make sure - * to use the name which a user desires if this is - * create path. - */ - ret = 0; - else { - spin_lock(&dentry->d_lock); - if (dentry->d_time != dentry->d_parent->d_inode->i_version) - ret = 0; - spin_unlock(&dentry->d_lock); - } - return ret; -} - -/* returns the length of a struct qstr, ignoring trailing dots */ -static unsigned int vfat_striptail_len(struct qstr *qstr) -{ - unsigned int len = qstr->len; - - while (len && qstr->name[len - 1] == '.') - len--; - return len; -} - -/* - * Compute the hash for the vfat name corresponding to the dentry. - * Note: if the name is invalid, we leave the hash code unchanged so - * that the existing dentry can be used. The vfat fs routines will - * return ENOENT or EINVAL as appropriate. - */ -static int vfat_hash(struct dentry *dentry, struct qstr *qstr) -{ - qstr->hash = full_name_hash(qstr->name, vfat_striptail_len(qstr)); - return 0; -} - -/* - * Compute the hash for the vfat name corresponding to the dentry. - * Note: if the name is invalid, we leave the hash code unchanged so - * that the existing dentry can be used. The vfat fs routines will - * return ENOENT or EINVAL as appropriate. - */ -static int vfat_hashi(struct dentry *dentry, struct qstr *qstr) -{ - struct nls_table *t = MSDOS_SB(dentry->d_inode->i_sb)->nls_io; - const unsigned char *name; - unsigned int len; - unsigned long hash; - - name = qstr->name; - len = vfat_striptail_len(qstr); - - hash = init_name_hash(); - while (len--) - hash = partial_name_hash(nls_tolower(t, *name++), hash); - qstr->hash = end_name_hash(hash); - - return 0; -} - -/* - * Case insensitive compare of two vfat names. - */ -static int vfat_cmpi(struct dentry *dentry, struct qstr *a, struct qstr *b) -{ - struct nls_table *t = MSDOS_SB(dentry->d_inode->i_sb)->nls_io; - unsigned int alen, blen; - - /* A filename cannot end in '.' or we treat it like it has none */ - alen = vfat_striptail_len(a); - blen = vfat_striptail_len(b); - if (alen == blen) { - if (nls_strnicmp(t, a->name, b->name, alen) == 0) - return 0; - } - return 1; -} - -/* - * Case sensitive compare of two vfat names. - */ -static int vfat_cmp(struct dentry *dentry, struct qstr *a, struct qstr *b) -{ - unsigned int alen, blen; - - /* A filename cannot end in '.' or we treat it like it has none */ - alen = vfat_striptail_len(a); - blen = vfat_striptail_len(b); - if (alen == blen) { - if (strncmp(a->name, b->name, alen) == 0) - return 0; - } - return 1; -} - -static struct dentry_operations vfat_dentry_ops[4] = { - { - .d_hash = vfat_hashi, - .d_compare = vfat_cmpi, - }, - { - .d_revalidate = vfat_revalidate, - .d_hash = vfat_hashi, - .d_compare = vfat_cmpi, - }, - { - .d_hash = vfat_hash, - .d_compare = vfat_cmp, - }, - { - .d_revalidate = vfat_revalidate, - .d_hash = vfat_hash, - .d_compare = vfat_cmp, - } -}; - -/* Characters that are undesirable in an MS-DOS file name */ - -static inline wchar_t vfat_bad_char(wchar_t w) -{ - return (w < 0x0020) - || (w == '*') || (w == '?') || (w == '<') || (w == '>') - || (w == '|') || (w == '"') || (w == ':') || (w == '/') - || (w == '\\'); -} - -static inline wchar_t vfat_replace_char(wchar_t w) -{ - return (w == '[') || (w == ']') || (w == ';') || (w == ',') - || (w == '+') || (w == '='); -} - -static wchar_t vfat_skip_char(wchar_t w) -{ - return (w == '.') || (w == ' '); -} - -static inline int vfat_is_used_badchars(const wchar_t *s, int len) -{ - int i; - - for (i = 0; i < len; i++) - if (vfat_bad_char(s[i])) - return -EINVAL; - - if (s[i - 1] == ' ') /* last character cannot be space */ - return -EINVAL; - - return 0; -} - -static int vfat_find_form(struct inode *dir, unsigned char *name) -{ - struct fat_slot_info sinfo; - int err = fat_scan(dir, name, &sinfo); - if (err) - return -ENOENT; - brelse(sinfo.bh); - return 0; -} - -/* - * 1) Valid characters for the 8.3 format alias are any combination of - * letters, uppercase alphabets, digits, any of the - * following special characters: - * $ % ' ` - @ { } ~ ! # ( ) & _ ^ - * In this case Longfilename is not stored in disk. - * - * WinNT's Extension: - * File name and extension name is contain uppercase/lowercase - * only. And it is expressed by CASE_LOWER_BASE and CASE_LOWER_EXT. - * - * 2) File name is 8.3 format, but it contain the uppercase and - * lowercase char, muliti bytes char, etc. In this case numtail is not - * added, but Longfilename is stored. - * - * 3) When the one except for the above, or the following special - * character are contained: - * . [ ] ; , + = - * numtail is added, and Longfilename must be stored in disk . - */ -struct shortname_info { - unsigned char lower:1, - upper:1, - valid:1; -}; -#define INIT_SHORTNAME_INFO(x) do { \ - (x)->lower = 1; \ - (x)->upper = 1; \ - (x)->valid = 1; \ -} while (0) - -static inline int to_shortname_char(struct nls_table *nls, - unsigned char *buf, int buf_size, - wchar_t *src, struct shortname_info *info) -{ - int len; - - if (vfat_skip_char(*src)) { - info->valid = 0; - return 0; - } - if (vfat_replace_char(*src)) { - info->valid = 0; - buf[0] = '_'; - return 1; - } - - len = nls->uni2char(*src, buf, buf_size); - if (len <= 0) { - info->valid = 0; - buf[0] = '_'; - len = 1; - } else if (len == 1) { - unsigned char prev = buf[0]; - - if (buf[0] >= 0x7F) { - info->lower = 0; - info->upper = 0; - } - - buf[0] = nls_toupper(nls, buf[0]); - if (isalpha(buf[0])) { - if (buf[0] == prev) - info->lower = 0; - else - info->upper = 0; - } - } else { - info->lower = 0; - info->upper = 0; - } - - return len; -} - -/* - * Given a valid longname, create a unique shortname. Make sure the - * shortname does not exist - * Returns negative number on error, 0 for a normal - * return, and 1 for valid shortname - */ -static int vfat_create_shortname(struct inode *dir, struct nls_table *nls, - wchar_t *uname, int ulen, - unsigned char *name_res, unsigned char *lcase) -{ - struct fat_mount_options *opts = &MSDOS_SB(dir->i_sb)->options; - wchar_t *ip, *ext_start, *end, *name_start; - unsigned char base[9], ext[4], buf[8], *p; - unsigned char charbuf[NLS_MAX_CHARSET_SIZE]; - int chl, chi; - int sz = 0, extlen, baselen, i, numtail_baselen, numtail2_baselen; - int is_shortname; - struct shortname_info base_info, ext_info; - - is_shortname = 1; - INIT_SHORTNAME_INFO(&base_info); - INIT_SHORTNAME_INFO(&ext_info); - - /* Now, we need to create a shortname from the long name */ - ext_start = end = &uname[ulen]; - while (--ext_start >= uname) { - if (*ext_start == 0x002E) { /* is `.' */ - if (ext_start == end - 1) { - sz = ulen; - ext_start = NULL; - } - break; - } - } - - if (ext_start == uname - 1) { - sz = ulen; - ext_start = NULL; - } else if (ext_start) { - /* - * Names which start with a dot could be just - * an extension eg. "...test". In this case Win95 - * uses the extension as the name and sets no extension. - */ - name_start = &uname[0]; - while (name_start < ext_start) { - if (!vfat_skip_char(*name_start)) - break; - name_start++; - } - if (name_start != ext_start) { - sz = ext_start - uname; - ext_start++; - } else { - sz = ulen; - ext_start = NULL; - } - } - - numtail_baselen = 6; - numtail2_baselen = 2; - for (baselen = i = 0, p = base, ip = uname; i < sz; i++, ip++) { - chl = to_shortname_char(nls, charbuf, sizeof(charbuf), - ip, &base_info); - if (chl == 0) - continue; - - if (baselen < 2 && (baselen + chl) > 2) - numtail2_baselen = baselen; - if (baselen < 6 && (baselen + chl) > 6) - numtail_baselen = baselen; - for (chi = 0; chi < chl; chi++) { - *p++ = charbuf[chi]; - baselen++; - if (baselen >= 8) - break; - } - if (baselen >= 8) { - if ((chi < chl - 1) || (ip + 1) - uname < sz) - is_shortname = 0; - break; - } - } - if (baselen == 0) { - return -EINVAL; - } - - extlen = 0; - if (ext_start) { - for (p = ext, ip = ext_start; extlen < 3 && ip < end; ip++) { - chl = to_shortname_char(nls, charbuf, sizeof(charbuf), - ip, &ext_info); - if (chl == 0) - continue; - - if ((extlen + chl) > 3) { - is_shortname = 0; - break; - } - for (chi = 0; chi < chl; chi++) { - *p++ = charbuf[chi]; - extlen++; - } - if (extlen >= 3) { - if (ip + 1 != end) - is_shortname = 0; - break; - } - } - } - ext[extlen] = '\0'; - base[baselen] = '\0'; - - /* Yes, it can happen. ".\xe5" would do it. */ - if (base[0] == DELETED_FLAG) - base[0] = 0x05; - - /* OK, at this point we know that base is not longer than 8 symbols, - * ext is not longer than 3, base is nonempty, both don't contain - * any bad symbols (lowercase transformed to uppercase). - */ - - memset(name_res, ' ', MSDOS_NAME); - memcpy(name_res, base, baselen); - memcpy(name_res + 8, ext, extlen); - *lcase = 0; - if (is_shortname && base_info.valid && ext_info.valid) { - if (vfat_find_form(dir, name_res) == 0) - return -EEXIST; - - if (opts->shortname & VFAT_SFN_CREATE_WIN95) { - return (base_info.upper && ext_info.upper); - } else if (opts->shortname & VFAT_SFN_CREATE_WINNT) { - if ((base_info.upper || base_info.lower) && - (ext_info.upper || ext_info.lower)) { - if (!base_info.upper && base_info.lower) - *lcase |= CASE_LOWER_BASE; - if (!ext_info.upper && ext_info.lower) - *lcase |= CASE_LOWER_EXT; - return 1; - } - return 0; - } else { - BUG(); - } - } - - if (opts->numtail == 0) - if (vfat_find_form(dir, name_res) < 0) - return 0; - - /* - * Try to find a unique extension. This used to - * iterate through all possibilities sequentially, - * but that gave extremely bad performance. Windows - * only tries a few cases before using random - * values for part of the base. - */ - - if (baselen > 6) { - baselen = numtail_baselen; - name_res[7] = ' '; - } - name_res[baselen] = '~'; - for (i = 1; i < 10; i++) { - name_res[baselen + 1] = i + '0'; - if (vfat_find_form(dir, name_res) < 0) - return 0; - } - - i = jiffies & 0xffff; - sz = (jiffies >> 16) & 0x7; - if (baselen > 2) { - baselen = numtail2_baselen; - name_res[7] = ' '; - } - name_res[baselen + 4] = '~'; - name_res[baselen + 5] = '1' + sz; - while (1) { - sprintf(buf, "%04X", i); - memcpy(&name_res[baselen], buf, 4); - if (vfat_find_form(dir, name_res) < 0) - break; - i -= 11; - } - return 0; -} - -/* Translate a string, including coded sequences into Unicode */ -static int -xlate_to_uni(const unsigned char *name, int len, unsigned char *outname, - int *longlen, int *outlen, int escape, int utf8, - struct nls_table *nls) -{ - const unsigned char *ip; - unsigned char nc; - unsigned char *op; - unsigned int ec; - int i, k, fill; - int charlen; - - if (utf8) { - int name_len = strlen(name); - - *outlen = utf8_mbstowcs((wchar_t *)outname, name, PATH_MAX); - - /* - * We stripped '.'s before and set len appropriately, - * but utf8_mbstowcs doesn't care about len - */ - *outlen -= (name_len - len); - - if (*outlen > 255) - return -ENAMETOOLONG; - - op = &outname[*outlen * sizeof(wchar_t)]; - } else { - if (nls) { - for (i = 0, ip = name, op = outname, *outlen = 0; - i < len && *outlen <= 255; - *outlen += 1) - { - if (escape && (*ip == ':')) { - if (i > len - 5) - return -EINVAL; - ec = 0; - for (k = 1; k < 5; k++) { - nc = ip[k]; - ec <<= 4; - if (nc >= '0' && nc <= '9') { - ec |= nc - '0'; - continue; - } - if (nc >= 'a' && nc <= 'f') { - ec |= nc - ('a' - 10); - continue; - } - if (nc >= 'A' && nc <= 'F') { - ec |= nc - ('A' - 10); - continue; - } - return -EINVAL; - } - *op++ = ec & 0xFF; - *op++ = ec >> 8; - ip += 5; - i += 5; - } else { - if ((charlen = nls->char2uni(ip, len - i, (wchar_t *)op)) < 0) - return -EINVAL; - ip += charlen; - i += charlen; - op += 2; - } - } - if (i < len) - return -ENAMETOOLONG; - } else { - for (i = 0, ip = name, op = outname, *outlen = 0; - i < len && *outlen <= 255; - i++, *outlen += 1) - { - *op++ = *ip++; - *op++ = 0; - } - if (i < len) - return -ENAMETOOLONG; - } - } - - *longlen = *outlen; - if (*outlen % 13) { - *op++ = 0; - *op++ = 0; - *outlen += 1; - if (*outlen % 13) { - fill = 13 - (*outlen % 13); - for (i = 0; i < fill; i++) { - *op++ = 0xff; - *op++ = 0xff; - } - *outlen += fill; - } - } - - return 0; -} - -static int vfat_build_slots(struct inode *dir, const unsigned char *name, - int len, int is_dir, int cluster, - struct timespec *ts, - struct msdos_dir_slot *slots, int *nr_slots) -{ - struct msdos_sb_info *sbi = MSDOS_SB(dir->i_sb); - struct fat_mount_options *opts = &sbi->options; - struct msdos_dir_slot *ps; - struct msdos_dir_entry *de; - unsigned char cksum, lcase; - unsigned char msdos_name[MSDOS_NAME]; - wchar_t *uname; - __le16 time, date; - int err, ulen, usize, i; - loff_t offset; - - *nr_slots = 0; - - uname = __getname(); - if (!uname) - return -ENOMEM; - - err = xlate_to_uni(name, len, (unsigned char *)uname, &ulen, &usize, - opts->unicode_xlate, opts->utf8, sbi->nls_io); - if (err) - goto out_free; - - err = vfat_is_used_badchars(uname, ulen); - if (err) - goto out_free; - - err = vfat_create_shortname(dir, sbi->nls_disk, uname, ulen, - msdos_name, &lcase); - if (err < 0) - goto out_free; - else if (err == 1) { - de = (struct msdos_dir_entry *)slots; - err = 0; - goto shortname; - } - - /* build the entry of long file name */ - cksum = fat_checksum(msdos_name); - - *nr_slots = usize / 13; - for (ps = slots, i = *nr_slots; i > 0; i--, ps++) { - ps->id = i; - ps->attr = ATTR_EXT; - ps->reserved = 0; - ps->alias_checksum = cksum; - ps->start = 0; - offset = (i - 1) * 13; - fatwchar_to16(ps->name0_4, uname + offset, 5); - fatwchar_to16(ps->name5_10, uname + offset + 5, 6); - fatwchar_to16(ps->name11_12, uname + offset + 11, 2); - } - slots[0].id |= 0x40; - de = (struct msdos_dir_entry *)ps; - -shortname: - /* build the entry of 8.3 alias name */ - (*nr_slots)++; - memcpy(de->name, msdos_name, MSDOS_NAME); - de->attr = is_dir ? ATTR_DIR : ATTR_ARCH; - de->lcase = lcase; - fat_date_unix2dos(ts->tv_sec, &time, &date, sbi->options.tz_utc); - de->time = de->ctime = time; - de->date = de->cdate = de->adate = date; - de->ctime_cs = 0; - de->start = cpu_to_le16(cluster); - de->starthi = cpu_to_le16(cluster >> 16); - de->size = 0; -out_free: - __putname(uname); - return err; -} - -static int vfat_add_entry(struct inode *dir, struct qstr *qname, int is_dir, - int cluster, struct timespec *ts, - struct fat_slot_info *sinfo) -{ - struct msdos_dir_slot *slots; - unsigned int len; - int err, nr_slots; - - len = vfat_striptail_len(qname); - if (len == 0) - return -ENOENT; - - slots = kmalloc(sizeof(*slots) * MSDOS_SLOTS, GFP_NOFS); - if (slots == NULL) - return -ENOMEM; - - err = vfat_build_slots(dir, qname->name, len, is_dir, cluster, ts, - slots, &nr_slots); - if (err) - goto cleanup; - - err = fat_add_entries(dir, slots, nr_slots, sinfo); - if (err) - goto cleanup; - - /* update timestamp */ - dir->i_ctime = dir->i_mtime = dir->i_atime = *ts; - if (IS_DIRSYNC(dir)) - (void)fat_sync_inode(dir); - else - mark_inode_dirty(dir); -cleanup: - kfree(slots); - return err; -} - -static int vfat_find(struct inode *dir, struct qstr *qname, - struct fat_slot_info *sinfo) -{ - unsigned int len = vfat_striptail_len(qname); - if (len == 0) - return -ENOENT; - return fat_search_long(dir, qname->name, len, sinfo); -} - -static struct dentry *vfat_lookup(struct inode *dir, struct dentry *dentry, - struct nameidata *nd) -{ - struct super_block *sb = dir->i_sb; - struct fat_slot_info sinfo; - struct inode *inode = NULL; - struct dentry *alias; - int err, table; - - lock_super(sb); - table = (MSDOS_SB(sb)->options.name_check == 's') ? 2 : 0; - dentry->d_op = &vfat_dentry_ops[table]; - - err = vfat_find(dir, &dentry->d_name, &sinfo); - if (err) { - table++; - goto error; - } - inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); - brelse(sinfo.bh); - if (IS_ERR(inode)) { - unlock_super(sb); - return ERR_CAST(inode); - } - alias = d_find_alias(inode); - if (alias) { - if (d_invalidate(alias) == 0) - dput(alias); - else { - iput(inode); - unlock_super(sb); - return alias; - } - - } -error: - unlock_super(sb); - dentry->d_op = &vfat_dentry_ops[table]; - dentry->d_time = dentry->d_parent->d_inode->i_version; - dentry = d_splice_alias(inode, dentry); - if (dentry) { - dentry->d_op = &vfat_dentry_ops[table]; - dentry->d_time = dentry->d_parent->d_inode->i_version; - } - return dentry; -} - -static int vfat_create(struct inode *dir, struct dentry *dentry, int mode, - struct nameidata *nd) -{ - struct super_block *sb = dir->i_sb; - struct inode *inode; - struct fat_slot_info sinfo; - struct timespec ts; - int err; - - lock_super(sb); - - ts = CURRENT_TIME_SEC; - err = vfat_add_entry(dir, &dentry->d_name, 0, 0, &ts, &sinfo); - if (err) - goto out; - dir->i_version++; - - inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); - brelse(sinfo.bh); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - inode->i_version++; - inode->i_mtime = inode->i_atime = inode->i_ctime = ts; - /* timestamp is already written, so mark_inode_dirty() is unneeded. */ - - dentry->d_time = dentry->d_parent->d_inode->i_version; - d_instantiate(dentry, inode); -out: - unlock_super(sb); - return err; -} - -static int vfat_rmdir(struct inode *dir, struct dentry *dentry) -{ - struct inode *inode = dentry->d_inode; - struct super_block *sb = dir->i_sb; - struct fat_slot_info sinfo; - int err; - - lock_super(sb); - - err = fat_dir_empty(inode); - if (err) - goto out; - err = vfat_find(dir, &dentry->d_name, &sinfo); - if (err) - goto out; - - err = fat_remove_entries(dir, &sinfo); /* and releases bh */ - if (err) - goto out; - drop_nlink(dir); - - clear_nlink(inode); - inode->i_mtime = inode->i_atime = CURRENT_TIME_SEC; - fat_detach(inode); -out: - unlock_super(sb); - - return err; -} - -static int vfat_unlink(struct inode *dir, struct dentry *dentry) -{ - struct inode *inode = dentry->d_inode; - struct super_block *sb = dir->i_sb; - struct fat_slot_info sinfo; - int err; - - lock_super(sb); - - err = vfat_find(dir, &dentry->d_name, &sinfo); - if (err) - goto out; - - err = fat_remove_entries(dir, &sinfo); /* and releases bh */ - if (err) - goto out; - clear_nlink(inode); - inode->i_mtime = inode->i_atime = CURRENT_TIME_SEC; - fat_detach(inode); -out: - unlock_super(sb); - - return err; -} - -static int vfat_mkdir(struct inode *dir, struct dentry *dentry, int mode) -{ - struct super_block *sb = dir->i_sb; - struct inode *inode; - struct fat_slot_info sinfo; - struct timespec ts; - int err, cluster; - - lock_super(sb); - - ts = CURRENT_TIME_SEC; - cluster = fat_alloc_new_dir(dir, &ts); - if (cluster < 0) { - err = cluster; - goto out; - } - err = vfat_add_entry(dir, &dentry->d_name, 1, cluster, &ts, &sinfo); - if (err) - goto out_free; - dir->i_version++; - inc_nlink(dir); - - inode = fat_build_inode(sb, sinfo.de, sinfo.i_pos); - brelse(sinfo.bh); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - /* the directory was completed, just return a error */ - goto out; - } - inode->i_version++; - inode->i_nlink = 2; - inode->i_mtime = inode->i_atime = inode->i_ctime = ts; - /* timestamp is already written, so mark_inode_dirty() is unneeded. */ - - dentry->d_time = dentry->d_parent->d_inode->i_version; - d_instantiate(dentry, inode); - - unlock_super(sb); - return 0; - -out_free: - fat_free_clusters(dir, cluster); -out: - unlock_super(sb); - return err; -} - -static int vfat_rename(struct inode *old_dir, struct dentry *old_dentry, - struct inode *new_dir, struct dentry *new_dentry) -{ - struct buffer_head *dotdot_bh; - struct msdos_dir_entry *dotdot_de; - struct inode *old_inode, *new_inode; - struct fat_slot_info old_sinfo, sinfo; - struct timespec ts; - loff_t dotdot_i_pos, new_i_pos; - int err, is_dir, update_dotdot, corrupt = 0; - struct super_block *sb = old_dir->i_sb; - - old_sinfo.bh = sinfo.bh = dotdot_bh = NULL; - old_inode = old_dentry->d_inode; - new_inode = new_dentry->d_inode; - lock_super(sb); - err = vfat_find(old_dir, &old_dentry->d_name, &old_sinfo); - if (err) - goto out; - - is_dir = S_ISDIR(old_inode->i_mode); - update_dotdot = (is_dir && old_dir != new_dir); - if (update_dotdot) { - if (fat_get_dotdot_entry(old_inode, &dotdot_bh, &dotdot_de, - &dotdot_i_pos) < 0) { - err = -EIO; - goto out; - } - } - - ts = CURRENT_TIME_SEC; - if (new_inode) { - if (is_dir) { - err = fat_dir_empty(new_inode); - if (err) - goto out; - } - new_i_pos = MSDOS_I(new_inode)->i_pos; - fat_detach(new_inode); - } else { - err = vfat_add_entry(new_dir, &new_dentry->d_name, is_dir, 0, - &ts, &sinfo); - if (err) - goto out; - new_i_pos = sinfo.i_pos; - } - new_dir->i_version++; - - fat_detach(old_inode); - fat_attach(old_inode, new_i_pos); - if (IS_DIRSYNC(new_dir)) { - err = fat_sync_inode(old_inode); - if (err) - goto error_inode; - } else - mark_inode_dirty(old_inode); - - if (update_dotdot) { - int start = MSDOS_I(new_dir)->i_logstart; - dotdot_de->start = cpu_to_le16(start); - dotdot_de->starthi = cpu_to_le16(start >> 16); - mark_buffer_dirty(dotdot_bh); - if (IS_DIRSYNC(new_dir)) { - err = sync_dirty_buffer(dotdot_bh); - if (err) - goto error_dotdot; - } - drop_nlink(old_dir); - if (!new_inode) - inc_nlink(new_dir); - } - - err = fat_remove_entries(old_dir, &old_sinfo); /* and releases bh */ - old_sinfo.bh = NULL; - if (err) - goto error_dotdot; - old_dir->i_version++; - old_dir->i_ctime = old_dir->i_mtime = ts; - if (IS_DIRSYNC(old_dir)) - (void)fat_sync_inode(old_dir); - else - mark_inode_dirty(old_dir); - - if (new_inode) { - drop_nlink(new_inode); - if (is_dir) - drop_nlink(new_inode); - new_inode->i_ctime = ts; - } -out: - brelse(sinfo.bh); - brelse(dotdot_bh); - brelse(old_sinfo.bh); - unlock_super(sb); - - return err; - -error_dotdot: - /* data cluster is shared, serious corruption */ - corrupt = 1; - - if (update_dotdot) { - int start = MSDOS_I(old_dir)->i_logstart; - dotdot_de->start = cpu_to_le16(start); - dotdot_de->starthi = cpu_to_le16(start >> 16); - mark_buffer_dirty(dotdot_bh); - corrupt |= sync_dirty_buffer(dotdot_bh); - } -error_inode: - fat_detach(old_inode); - fat_attach(old_inode, old_sinfo.i_pos); - if (new_inode) { - fat_attach(new_inode, new_i_pos); - if (corrupt) - corrupt |= fat_sync_inode(new_inode); - } else { - /* - * If new entry was not sharing the data cluster, it - * shouldn't be serious corruption. - */ - int err2 = fat_remove_entries(new_dir, &sinfo); - if (corrupt) - corrupt |= err2; - sinfo.bh = NULL; - } - if (corrupt < 0) { - fat_fs_panic(new_dir->i_sb, - "%s: Filesystem corrupted (i_pos %lld)", - __func__, sinfo.i_pos); - } - goto out; -} - -static const struct inode_operations vfat_dir_inode_operations = { - .create = vfat_create, - .lookup = vfat_lookup, - .unlink = vfat_unlink, - .mkdir = vfat_mkdir, - .rmdir = vfat_rmdir, - .rename = vfat_rename, - .setattr = fat_setattr, - .getattr = fat_getattr, -}; - -static int vfat_fill_super(struct super_block *sb, void *data, int silent) -{ - int res; - - res = fat_fill_super(sb, data, silent, &vfat_dir_inode_operations, 1); - if (res) - return res; - - if (MSDOS_SB(sb)->options.name_check != 's') - sb->s_root->d_op = &vfat_dentry_ops[0]; - else - sb->s_root->d_op = &vfat_dentry_ops[2]; - - return 0; -} - -static int vfat_get_sb(struct file_system_type *fs_type, - int flags, const char *dev_name, - void *data, struct vfsmount *mnt) -{ - return get_sb_bdev(fs_type, flags, dev_name, data, vfat_fill_super, - mnt); -} - -static struct file_system_type vfat_fs_type = { - .owner = THIS_MODULE, - .name = "vfat", - .get_sb = vfat_get_sb, - .kill_sb = kill_block_super, - .fs_flags = FS_REQUIRES_DEV, -}; - -static int __init init_vfat_fs(void) -{ - return register_filesystem(&vfat_fs_type); -} - -static void __exit exit_vfat_fs(void) -{ - unregister_filesystem(&vfat_fs_type); -} - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("VFAT filesystem support"); -MODULE_AUTHOR("Gordon Chaffee"); - -module_init(init_vfat_fs) -module_exit(exit_vfat_fs) diff --git a/fs/xfs/xfs_da_btree.c b/fs/xfs/xfs_da_btree.c index 9e561a9cefca..a11a8390bf6c 100644 --- a/fs/xfs/xfs_da_btree.c +++ b/fs/xfs/xfs_da_btree.c @@ -1566,11 +1566,14 @@ xfs_da_grow_inode(xfs_da_args_t *args, xfs_dablk_t *new_blkno) int nmap, error, w, count, c, got, i, mapi; xfs_trans_t *tp; xfs_mount_t *mp; + xfs_drfsbno_t nblks; dp = args->dp; mp = dp->i_mount; w = args->whichfork; tp = args->trans; + nblks = dp->i_d.di_nblocks; + /* * For new directories adjust the file offset and block count. */ @@ -1647,6 +1650,8 @@ xfs_da_grow_inode(xfs_da_args_t *args, xfs_dablk_t *new_blkno) } if (mapp != &map) kmem_free(mapp); + /* account for newly allocated blocks in reserved blocks total */ + args->total -= dp->i_d.di_nblocks - nblks; *new_blkno = (xfs_dablk_t)bno; return 0; } diff --git a/fs/xfs/xfs_dir2.c b/fs/xfs/xfs_dir2.c index 80e0dc51361c..1afb12278b8d 100644 --- a/fs/xfs/xfs_dir2.c +++ b/fs/xfs/xfs_dir2.c @@ -525,11 +525,13 @@ xfs_dir2_grow_inode( xfs_mount_t *mp; int nmap; /* number of bmap entries */ xfs_trans_t *tp; + xfs_drfsbno_t nblks; xfs_dir2_trace_args_s("grow_inode", args, space); dp = args->dp; tp = args->trans; mp = dp->i_mount; + nblks = dp->i_d.di_nblocks; /* * Set lowest possible block in the space requested. */ @@ -622,7 +624,11 @@ xfs_dir2_grow_inode( */ if (mapp != &map) kmem_free(mapp); + + /* account for newly allocated blocks in reserved blocks total */ + args->total -= dp->i_d.di_nblocks - nblks; *dbp = xfs_dir2_da_to_db(mp, (xfs_dablk_t)bno); + /* * Update file's size if this is the data space and it grew. */ diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c index dbd9cef852ec..a391b955df01 100644 --- a/fs/xfs/xfs_inode.c +++ b/fs/xfs/xfs_inode.c @@ -1414,7 +1414,7 @@ xfs_itruncate_start( mp = ip->i_mount; /* wait for the completion of any pending DIOs */ - if (new_size < ip->i_size) + if (new_size == 0 || new_size < ip->i_size) vn_iowait(ip); /* diff --git a/fs/xfs/xfs_log.c b/fs/xfs/xfs_log.c index 0b02c6443551..3608a0f0a5f6 100644 --- a/fs/xfs/xfs_log.c +++ b/fs/xfs/xfs_log.c @@ -563,6 +563,11 @@ xfs_log_mount( } mp->m_log = xlog_alloc_log(mp, log_target, blk_offset, num_bblks); + if (!mp->m_log) { + cmn_err(CE_WARN, "XFS: Log allocation failed: No memory!"); + error = ENOMEM; + goto out; + } /* * Initialize the AIL now we have a log. @@ -601,6 +606,7 @@ xfs_log_mount( return 0; error: xfs_log_unmount_dealloc(mp); +out: return error; } /* xfs_log_mount */ @@ -1217,7 +1223,9 @@ xlog_alloc_log(xfs_mount_t *mp, int i; int iclogsize; - log = (xlog_t *)kmem_zalloc(sizeof(xlog_t), KM_SLEEP); + log = kmem_zalloc(sizeof(xlog_t), KM_MAYFAIL); + if (!log) + return NULL; log->l_mp = mp; log->l_targ = log_target; @@ -1249,6 +1257,8 @@ xlog_alloc_log(xfs_mount_t *mp, xlog_get_iclog_buffer_size(mp, log); bp = xfs_buf_get_empty(log->l_iclog_size, mp->m_logdev_targp); + if (!bp) + goto out_free_log; XFS_BUF_SET_IODONE_FUNC(bp, xlog_iodone); XFS_BUF_SET_BDSTRAT_FUNC(bp, xlog_bdstrat_cb); XFS_BUF_SET_FSPRIVATE2(bp, (unsigned long)1); @@ -1275,13 +1285,17 @@ xlog_alloc_log(xfs_mount_t *mp, iclogsize = log->l_iclog_size; ASSERT(log->l_iclog_size >= 4096); for (i=0; i < log->l_iclog_bufs; i++) { - *iclogp = (xlog_in_core_t *) - kmem_zalloc(sizeof(xlog_in_core_t), KM_SLEEP); + *iclogp = kmem_zalloc(sizeof(xlog_in_core_t), KM_MAYFAIL); + if (!*iclogp) + goto out_free_iclog; + iclog = *iclogp; iclog->ic_prev = prev_iclog; prev_iclog = iclog; bp = xfs_buf_get_noaddr(log->l_iclog_size, mp->m_logdev_targp); + if (!bp) + goto out_free_iclog; if (!XFS_BUF_CPSEMA(bp)) ASSERT(0); XFS_BUF_SET_IODONE_FUNC(bp, xlog_iodone); @@ -1323,6 +1337,25 @@ xlog_alloc_log(xfs_mount_t *mp, log->l_iclog->ic_prev = prev_iclog; /* re-write 1st prev ptr */ return log; + +out_free_iclog: + for (iclog = log->l_iclog; iclog; iclog = prev_iclog) { + prev_iclog = iclog->ic_next; + if (iclog->ic_bp) { + sv_destroy(&iclog->ic_force_wait); + sv_destroy(&iclog->ic_write_wait); + xfs_buf_free(iclog->ic_bp); + xlog_trace_iclog_dealloc(iclog); + } + kmem_free(iclog); + } + spinlock_destroy(&log->l_icloglock); + spinlock_destroy(&log->l_grant_lock); + xlog_trace_loggrant_dealloc(log); + xfs_buf_free(log->l_xbuf); +out_free_log: + kmem_free(log); + return NULL; } /* xlog_alloc_log */ diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c index 82d46ce69d5f..70e3ba32e6be 100644 --- a/fs/xfs/xfs_log_recover.c +++ b/fs/xfs/xfs_log_recover.c @@ -1419,7 +1419,13 @@ xlog_recover_add_to_trans( return 0; item = trans->r_itemq; if (item == NULL) { - ASSERT(*(uint *)dp == XFS_TRANS_HEADER_MAGIC); + /* we need to catch log corruptions here */ + if (*(uint *)dp != XFS_TRANS_HEADER_MAGIC) { + xlog_warn("XFS: xlog_recover_add_to_trans: " + "bad header magic number"); + ASSERT(0); + return XFS_ERROR(EIO); + } if (len == sizeof(xfs_trans_header_t)) xlog_recover_add_item(&trans->r_itemq); memcpy(&trans->r_theader, dp, len); /* d, s, l */ diff --git a/fs/xfs/xfs_mount.c b/fs/xfs/xfs_mount.c index a4503f5e9497..15f5dd22fbb2 100644 --- a/fs/xfs/xfs_mount.c +++ b/fs/xfs/xfs_mount.c @@ -1245,6 +1245,9 @@ xfs_unmountfs( XFS_QM_DQPURGEALL(mp, XFS_QMOPT_QUOTALL | XFS_QMOPT_UMOUNTING); + if (mp->m_quotainfo) + XFS_QM_DONE(mp); + /* * Flush out the log synchronously so that we know for sure * that nothing is pinned. This is important because bflush() @@ -1297,8 +1300,6 @@ xfs_unmountfs( xfs_errortag_clearall(mp, 0); #endif xfs_free_perag(mp); - if (mp->m_quotainfo) - XFS_QM_DONE(mp); } STATIC void diff --git a/fs/xfs/xfs_rename.c b/fs/xfs/xfs_rename.c index d700dacdb10e..c903130be7fd 100644 --- a/fs/xfs/xfs_rename.c +++ b/fs/xfs/xfs_rename.c @@ -212,7 +212,7 @@ xfs_rename( if (unlikely((target_dp->i_d.di_flags & XFS_DIFLAG_PROJINHERIT) && (target_dp->i_d.di_projid != src_ip->i_d.di_projid))) { error = XFS_ERROR(EXDEV); - xfs_rename_unlock4(inodes, XFS_ILOCK_SHARED); + xfs_rename_unlock4(inodes, XFS_ILOCK_EXCL); xfs_trans_cancel(tp, cancel_flags); goto std_return; } diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 54a279e44c9a..e9f6574930ef 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -380,6 +380,8 @@ struct acpi_bus_type { int register_acpi_bus_type(struct acpi_bus_type *); int unregister_acpi_bus_type(struct acpi_bus_type *); struct device *acpi_get_physical_device(acpi_handle); +struct device *acpi_get_physical_pci_device(acpi_handle); + /* helper */ acpi_handle acpi_get_child(acpi_handle, acpi_integer); acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index cf04c6011c2a..5fc1bb0f4a90 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -31,8 +31,24 @@ #define ACPI_MAX_STRING 80 +/* + * Please update drivers/acpi/debug.c and Documentation/acpi/debug.txt + * if you add to this list. + */ #define ACPI_BUS_COMPONENT 0x00010000 +#define ACPI_AC_COMPONENT 0x00020000 +#define ACPI_BATTERY_COMPONENT 0x00040000 +#define ACPI_BUTTON_COMPONENT 0x00080000 +#define ACPI_SBS_COMPONENT 0x00100000 +#define ACPI_FAN_COMPONENT 0x00200000 +#define ACPI_PCI_COMPONENT 0x00400000 +#define ACPI_POWER_COMPONENT 0x00800000 +#define ACPI_CONTAINER_COMPONENT 0x01000000 #define ACPI_SYSTEM_COMPONENT 0x02000000 +#define ACPI_THERMAL_COMPONENT 0x04000000 +#define ACPI_MEMORY_DEVICE_COMPONENT 0x08000000 +#define ACPI_VIDEO_COMPONENT 0x10000000 +#define ACPI_PROCESSOR_COMPONENT 0x20000000 /* * _HID definitions @@ -41,6 +57,7 @@ */ #define ACPI_POWER_HID "LNXPOWER" +#define ACPI_PROCESSOR_OBJECT_HID "ACPI_CPU" #define ACPI_PROCESSOR_HID "ACPI0007" #define ACPI_SYSTEM_HID "LNXSYSTM" #define ACPI_THERMAL_HID "LNXTHERM" @@ -54,7 +71,6 @@ PCI -------------------------------------------------------------------------- */ -#define ACPI_PCI_COMPONENT 0x00400000 /* ACPI PCI Interrupt Link (pci_link.c) */ @@ -86,7 +102,6 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain, Power Resource -------------------------------------------------------------------------- */ -#ifdef CONFIG_ACPI_POWER int acpi_device_sleep_wake(struct acpi_device *dev, int enable, int sleep_state, int dev_state); int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state); @@ -94,15 +109,12 @@ int acpi_disable_wakeup_device_power(struct acpi_device *dev); int acpi_power_get_inferred_state(struct acpi_device *device); int acpi_power_transition(struct acpi_device *device, int state); extern int acpi_power_nocheck; -#endif /* -------------------------------------------------------------------------- Embedded Controller -------------------------------------------------------------------------- */ -#ifdef CONFIG_ACPI_EC int acpi_ec_ecdt_probe(void); int acpi_boot_ec_enable(void); -#endif /* -------------------------------------------------------------------------- Processor diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 94d94e126e9f..33bc0e3b1954 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -252,9 +252,9 @@ acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status); acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type); -acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags); +acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number); -acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags); +acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number); acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags); diff --git a/include/acpi/acpredef.h b/include/acpi/acpredef.h index 619fb75f8861..16a9ca9a66e4 100644 --- a/include/acpi/acpredef.h +++ b/include/acpi/acpredef.h @@ -167,7 +167,7 @@ static const union acpi_predefined_info predefined_names[] = { {.info = {"_BFS", 1, 0}}, {.info = {"_BIF", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 9, - ACPI_RTYPE_STRING, 4, 0}}, /* fixed (9 Int),(4 Str) */ + ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER, 4, 0}}, /* fixed (9 Int),(4 Str) */ {.info = {"_BLT", 3, 0}}, {.info = {"_BMC", 1, 0}}, {.info = {"_BMD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}}, /* fixed (5 Int) */ @@ -346,7 +346,7 @@ static const union acpi_predefined_info predefined_names[] = { /* Acpi 1.0 defined _WAK with no return value. Later, it was changed to return a package */ - {.info = {"_WAK", 1, ACPI_RTYPE_NONE | ACPI_RTYPE_PACKAGE}}, + {.info = {"_WAK", 1, ACPI_RTYPE_NONE | ACPI_RTYPE_INTEGER | ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2, 0, 0, 0}}, /* fixed (2 Int), but is optional */ {.ret_info = {0, 0, 0, 0, 0, 0}} /* Table terminator */ }; diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index e8936ab59627..7220361790b3 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -525,6 +525,7 @@ typedef u32 acpi_event_status; #define ACPI_EVENT_FLAG_ENABLED (acpi_event_status) 0x01 #define ACPI_EVENT_FLAG_WAKE_ENABLED (acpi_event_status) 0x02 #define ACPI_EVENT_FLAG_SET (acpi_event_status) 0x04 +#define ACPI_EVENT_FLAG_HANDLE (acpi_event_status) 0x08 /* * General Purpose Events (GPE) diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild deleted file mode 100644 index d5b631935ec8..000000000000 --- a/include/asm-cris/Kbuild +++ /dev/null @@ -1,11 +0,0 @@ -include include/asm-generic/Kbuild.asm - -header-y += arch-v10/ -header-y += arch-v32/ - -header-y += ethernet.h -header-y += rtc.h -header-y += sync_serial.h - -unifdef-y += etraxgpio.h -unifdef-y += rs485.h diff --git a/include/asm-cris/arch-v10/Kbuild b/include/asm-cris/arch-v10/Kbuild deleted file mode 100644 index 7a192e1290b1..000000000000 --- a/include/asm-cris/arch-v10/Kbuild +++ /dev/null @@ -1,4 +0,0 @@ -header-y += user.h -header-y += svinto.h -header-y += sv_addr_ag.h -header-y += sv_addr.agh diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h deleted file mode 100644 index 6ef5e7d09024..000000000000 --- a/include/asm-cris/arch-v10/atomic.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_ATOMIC__ -#define __ASM_CRIS_ARCH_ATOMIC__ - -#define cris_atomic_save(addr, flags) local_irq_save(flags); -#define cris_atomic_restore(addr, flags) local_irq_restore(flags); - -#endif diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h deleted file mode 100644 index be85f6de25d3..000000000000 --- a/include/asm-cris/arch-v10/bitops.h +++ /dev/null @@ -1,73 +0,0 @@ -/* asm/arch/bitops.h for Linux/CRISv10 */ - -#ifndef _CRIS_ARCH_BITOPS_H -#define _CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions, wrapping the - * syntactically awkward asms. The asms compute the number of leading - * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped - * number. They differ in that the first function also inverts all bits - * in the input. - */ -static inline unsigned long cris_swapnwbrlz(unsigned long w) -{ - /* Let's just say we return the result in the same register as the - input. Saying we clobber the input but can return the result - in another register: - ! __asm__ ("swapnwbr %2\n\tlz %2,%0" - ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); - confuses gcc (sched.c, gcc from cris-dist-1.14). */ - - unsigned long res; - __asm__ ("swapnwbr %0 \n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - return res; -} - -static inline unsigned long cris_swapwbrlz(unsigned long w) -{ - unsigned res; - __asm__ ("swapwbr %0 \n\t" - "lz %0,%0" - : "=r" (res) - : "0" (w)); - return res; -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/** - * __ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline unsigned long __ffs(unsigned long word) -{ - return cris_swapnwbrlz(~word); -} - -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -static inline unsigned long kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif diff --git a/include/asm-cris/arch-v10/bug.h b/include/asm-cris/arch-v10/bug.h deleted file mode 100644 index 3485d6b34bb0..000000000000 --- a/include/asm-cris/arch-v10/bug.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __ASM_CRISv10_ARCH_BUG_H -#define __ASM_CRISv10_ARCH_BUG_H - -#include - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -/* The BUG() macro is used for marking obviously incorrect code paths. - * It will cause a message with the file name and line number to be printed, - * and then cause an oops. The message is actually printed by handle_BUG() - * in arch/cris/kernel/traps.c, and the reason we use this method of storing - * the file name and line number is that we do not want to affect the registers - * by calling printk() before causing the oops. - */ - -#define BUG_PREFIX 0x0D7F -#define BUG_MAGIC 0x00001234 - -struct bug_frame { - unsigned short prefix; - unsigned int magic; - unsigned short clear; - unsigned short movu; - unsigned short line; - unsigned short jump; - unsigned char *filename; -}; - -#if 0 -/* Unfortunately this version of the macro does not work due to a problem - * with the compiler (aka a bug) when compiling with -O2, which sometimes - * erroneously causes the second input to be stored in a register... - */ -#define BUG() \ - __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ - "movu.w %0,$r0\n\t" \ - "jump %1\n\t" \ - : : "i" (__LINE__), "i" (__FILE__)) -#else -/* This version will have to do for now, until the compiler is fixed. - * The drawbacks of this version are that the file name will appear multiple - * times in the .rodata section, and that __LINE__ and __FILE__ can probably - * not be used like this with newer versions of gcc. - */ -#define BUG() \ - __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ - "movu.w " __stringify(__LINE__) ",$r0\n\t"\ - "jump 0f\n\t" \ - ".section .rodata\n" \ - "0:\t.string \"" __FILE__ "\"\n\t" \ - ".previous") -#endif - -#else - -/* This just causes an oops. */ -#define BUG() (*(int *)0 = 0) - -#endif - -#define HAVE_ARCH_BUG -#endif - -#include - -#endif diff --git a/include/asm-cris/arch-v10/byteorder.h b/include/asm-cris/arch-v10/byteorder.h deleted file mode 100644 index 255b646b7fa8..000000000000 --- a/include/asm-cris/arch-v10/byteorder.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _CRIS_ARCH_BYTEORDER_H -#define _CRIS_ARCH_BYTEORDER_H - -#include -#include - -/* we just define these two (as we can do the swap in a single - * asm instruction in CRIS) and the arch-independent files will put - * them together into ntohl etc. - */ - -static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); - - return(x); -} - -static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - __asm__ ("swapb %0" : "=r" (x) : "0" (x)); - - return(x); -} - -#endif diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h deleted file mode 100644 index aea27184d2d2..000000000000 --- a/include/asm-cris/arch-v10/cache.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASM_ARCH_CACHE_H -#define _ASM_ARCH_CACHE_H - -/* Etrax 100LX have 32-byte cache-lines. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 - -#endif /* _ASM_ARCH_CACHE_H */ diff --git a/include/asm-cris/arch-v10/checksum.h b/include/asm-cris/arch-v10/checksum.h deleted file mode 100644 index b8000c5d7fe1..000000000000 --- a/include/asm-cris/arch-v10/checksum.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _CRIS_ARCH_CHECKSUM_H -#define _CRIS_ARCH_CHECKSUM_H - -/* Checksum some values used in TCP/UDP headers. - * - * The gain by doing this in asm is that C will not generate carry-additions - * for the 32-bit components of the checksum, so otherwise we would have had - * to split all of those into 16-bit components, then add. - */ - -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, - unsigned short proto, __wsum sum) -{ - __wsum res; - __asm__ ("add.d %2, %0\n\t" - "ax\n\t" - "add.d %3, %0\n\t" - "ax\n\t" - "add.d %4, %0\n\t" - "ax\n\t" - "addq 0, %0\n" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8)); - - return res; -} - -#endif diff --git a/include/asm-cris/arch-v10/delay.h b/include/asm-cris/arch-v10/delay.h deleted file mode 100644 index 39481f6e0c30..000000000000 --- a/include/asm-cris/arch-v10/delay.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _CRIS_ARCH_DELAY_H -#define _CRIS_ARCH_DELAY_H - -static inline void __delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0,$r9\n\t" - "beq 2f\n\t" - "subq 1,$r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1,$r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* defined(_CRIS_ARCH_DELAY_H) */ - - - diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h deleted file mode 100644 index ecb9dba6fa4f..000000000000 --- a/include/asm-cris/arch-v10/dma.h +++ /dev/null @@ -1,74 +0,0 @@ -/* Defines for using and allocating dma channels. */ - -#ifndef _ASM_ARCH_DMA_H -#define _ASM_ARCH_DMA_H - -#define MAX_DMA_CHANNELS 10 - -/* dma0 and dma1 used for network (ethernet) */ -#define NETWORK_TX_DMA_NBR 0 -#define NETWORK_RX_DMA_NBR 1 - -/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ -#define PAR0_TX_DMA_NBR 2 -#define PAR0_RX_DMA_NBR 3 -#define SCSI0_TX_DMA_NBR 2 -#define SCSI0_RX_DMA_NBR 3 -#define SER2_TX_DMA_NBR 2 -#define SER2_RX_DMA_NBR 3 -#define ATA_TX_DMA_NBR 2 -#define ATA_RX_DMA_NBR 3 - -/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ -#define PAR1_TX_DMA_NBR 4 -#define PAR1_RX_DMA_NBR 5 -#define SCSI1_TX_DMA_NBR 4 -#define SCSI1_RX_DMA_NBR 5 -#define SER3_TX_DMA_NBR 4 -#define SER3_RX_DMA_NBR 5 -#define EXTDMA0_TX_DMA_NBR 4 -#define EXTDMA0_RX_DMA_NBR 5 - -/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ -#define SER0_TX_DMA_NBR 6 -#define SER0_RX_DMA_NBR 7 -#define EXTDMA1_TX_DMA_NBR 6 -#define EXTDMA1_RX_DMA_NBR 7 -#define MEM2MEM_TX_DMA_NBR 6 -#define MEM2MEM_RX_DMA_NBR 7 - -/* dma8 and dma9 shared by ser1 and usb */ -#define SER1_TX_DMA_NBR 8 -#define SER1_RX_DMA_NBR 9 -#define USB_TX_DMA_NBR 8 -#define USB_RX_DMA_NBR 9 - -#endif - -enum dma_owner -{ - dma_eth, - dma_ser0, - dma_ser1, /* Async and sync */ - dma_ser2, - dma_ser3, /* Async and sync */ - dma_ata, - dma_par0, - dma_par1, - dma_ext0, - dma_ext1, - dma_int6, - dma_int7, - dma_usb, - dma_scsi0, - dma_scsi1 -}; - -/* Masks used by cris_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR (1<<0) -#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) - -int cris_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, enum dma_owner owner); - -void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h deleted file mode 100644 index 1c38ee728b17..000000000000 --- a/include/asm-cris/arch-v10/elf.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef __ASMCRIS_ARCH_ELF_H -#define __ASMCRIS_ARCH_ELF_H - -#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* - * ELF register definitions.. - */ - -#include - -/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program - starts (a register; assume first param register for CRIS) - contains a pointer to a function which might be - registered using `atexit'. This provides a mean for the - dynamic linker to call DT_FINI functions for shared libraries - that have been loaded before the code runs. - - A value of 0 tells we have no such handler. */ - -/* Explicitly set registers to 0 to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ -} while (0) - -/* The additional layer below is because the stack pointer is missing in - the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, - and should be filled in according to the layout of the user_regs_struct - struct; regs is a pt_regs struct. We dump all registers, though several are - obviously unnecessary. That way there's less need for intelligence at - the receiving end (i.e. gdb). */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* sp */ \ - pr_reg[15] = regs->irp; /* pc */ \ - pr_reg[16] = 0; /* p0 */ \ - pr_reg[17] = rdvr(); /* vr */ \ - pr_reg[18] = 0; /* p2 */ \ - pr_reg[19] = 0; /* p3 */ \ - pr_reg[20] = 0; /* p4 */ \ - pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ - pr_reg[22] = 0; /* p6 */ \ - pr_reg[23] = regs->mof; /* mof */ \ - pr_reg[24] = 0; /* p8 */ \ - pr_reg[25] = 0; /* ibr */ \ - pr_reg[26] = 0; /* irp */ \ - pr_reg[27] = regs->srp; /* srp */ \ - pr_reg[28] = 0; /* bar */ \ - pr_reg[29] = regs->dccr; /* dccr */ \ - pr_reg[30] = 0; /* brp */ \ - pr_reg[31] = rdusp(); /* usp */ \ - pr_reg[32] = 0; /* csrinstr */ \ - pr_reg[33] = 0; /* csraddr */ \ - pr_reg[34] = 0; /* csrdata */ - - -#endif diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h deleted file mode 100644 index c08c24265299..000000000000 --- a/include/asm-cris/arch-v10/io.h +++ /dev/null @@ -1,199 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_IO_H -#define _ASM_ARCH_CRIS_IO_H - -#include - -/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ - -extern unsigned long gen_config_ii_shadow; -extern unsigned long port_g_data_shadow; -extern unsigned char port_pa_dir_shadow; -extern unsigned char port_pa_data_shadow; -extern unsigned char port_pb_i2c_shadow; -extern unsigned char port_pb_config_shadow; -extern unsigned char port_pb_dir_shadow; -extern unsigned char port_pb_data_shadow; -extern unsigned long r_timer_ctrl_shadow; - -extern unsigned long port_cse1_shadow; -extern unsigned long port_csp0_shadow; -extern unsigned long port_csp4_shadow; - -extern volatile unsigned long *port_cse1_addr; -extern volatile unsigned long *port_csp0_addr; -extern volatile unsigned long *port_csp4_addr; - -/* macro for setting regs through a shadow - - * r = register name (like R_PORT_PA_DATA) - * s = shadow name (like port_pa_data_shadow) - * b = bit number - * v = value (0 or 1) - */ - -#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) - -/* The LED's on various Etrax-based products are set differently. */ - -#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM) -#undef CONFIG_ETRAX_PA_LEDS -#undef CONFIG_ETRAX_PB_LEDS -#undef CONFIG_ETRAX_CSP0_LEDS -#define CRIS_LED_NETWORK_SET_G(x) -#define CRIS_LED_NETWORK_SET_R(x) -#define CRIS_LED_ACTIVE_SET_G(x) -#define CRIS_LED_ACTIVE_SET_R(x) -#define CRIS_LED_DISK_WRITE(x) -#define CRIS_LED_DISK_READ(x) -#endif - -#if !defined(CONFIG_ETRAX_CSP0_LEDS) -#define CRIS_LED_BIT_SET(x) -#define CRIS_LED_BIT_CLR(x) -#endif - -#define CRIS_LED_OFF 0x00 -#define CRIS_LED_GREEN 0x01 -#define CRIS_LED_RED 0x02 -#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) - -#if defined(CONFIG_ETRAX_NO_LEDS) -#define CRIS_LED_NETWORK_SET(x) -#else -#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R -#define CRIS_LED_NETWORK_SET(x) \ - do { \ - CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ - } while (0) -#else -#define CRIS_LED_NETWORK_SET(x) \ - do { \ - CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#endif -#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - } while (0) -#else -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#endif -#endif - -#ifdef CONFIG_ETRAX_PA_LEDS -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ - CONFIG_ETRAX_LED3G, !(x)) -#endif - -#ifdef CONFIG_ETRAX_PB_LEDS -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ - CONFIG_ETRAX_LED3G, !(x)) -#endif - -#ifdef CONFIG_ETRAX_CSP0_LEDS -#define CONFIGURABLE_LEDS\ - ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ - (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ - (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ - (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ - (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ - (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ - (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ - (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ - (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ - (1 << CONFIG_ETRAX_LED12R )) - -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) -#define CRIS_LED_BIT_SET(x)\ - do{\ - if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ - }while(0) -#define CRIS_LED_BIT_CLR(x)\ - do{\ - if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ - }while(0) -#endif - -# -#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN -#define SOFT_SHUTDOWN() \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) -#else -#define SOFT_SHUTDOWN() -#endif - -/* Console I/O for simulated etrax100. Use #ifdef so erroneous - use will be evident. */ -#ifdef CONFIG_SVINTO_SIM - /* Let's use the ucsim interface since it lets us do write(2, ...) */ -#define SIMCOUT(s,len) \ - asm ("moveq 4,$r9 \n\t" \ - "moveq 2,$r10 \n\t" \ - "move.d %0,$r11 \n\t" \ - "move.d %1,$r12 \n\t" \ - "push $irp \n\t" \ - "move 0f,$irp \n\t" \ - "jump -6809 \n" \ - "0: \n\t" \ - "pop $irp" \ - : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory") -#define TRACE_ON() __extension__ \ - ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \ - (255)); _Foofoo; }) - -#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0) -#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0) -#define CRIS_CYCLES() __extension__ \ - ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;}) -#endif /* ! defined CONFIG_SVINTO_SIM */ - -#endif diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h deleted file mode 100644 index d92500080883..000000000000 --- a/include/asm-cris/arch-v10/io_interface_mux.h +++ /dev/null @@ -1,75 +0,0 @@ -/* IO interface mux allocator for ETRAX100LX. - * Copyright 2004, Axis Communications AB - * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ - */ - - -#ifndef _IO_INTERFACE_MUX_H -#define _IO_INTERFACE_MUX_H - - -/* C.f. ETRAX100LX Designer's Reference 20.9 */ - -/* The order in enum must match the order of interfaces[] in - * io_interface_mux.c */ -enum cris_io_interface { - /* Begin Non-multiplexed interfaces */ - if_eth = 0, - if_serial_0, - /* End Non-multiplexed interfaces */ - if_serial_1, - if_serial_2, - if_serial_3, - if_sync_serial_1, - if_sync_serial_3, - if_shared_ram, - if_shared_ram_w, - if_par_0, - if_par_1, - if_par_w, - if_scsi8_0, - if_scsi8_1, - if_scsi_w, - if_ata, - if_csp, - if_i2c, - if_usb_1, - if_usb_2, - /* GPIO pins */ - if_gpio_grp_a, - if_gpio_grp_b, - if_gpio_grp_c, - if_gpio_grp_d, - if_gpio_grp_e, - if_gpio_grp_f, - if_max_interfaces, - if_unclaimed -}; - -int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); - -void cris_free_io_interface(enum cris_io_interface ioif); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_free_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -#endif /* _IO_INTERFACE_MUX_H */ diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h deleted file mode 100644 index b1128a9984ae..000000000000 --- a/include/asm-cris/arch-v10/irq.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Interrupt handling assembler and defines for Linux/CRISv10 - */ - -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include - -#define NR_IRQS 32 - -/* The first vector number used for IRQs in v10 is really 0x20 */ -/* but all the code and constants are offseted to make 0 the first */ -#define FIRST_IRQ 0 - -#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ -#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ -#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ -#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ -/* mio, ata, par0, scsi0 on 4 */ -/* par1, scsi1 on 5 */ -#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ - -#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ -#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ -/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ -#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) -#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) - -/* dma0-9 is irq 16..25 */ -/* 16,17: network */ -#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) -#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) -#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR -#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR - -/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ -#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) -#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) -#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR -#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR - -/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ -#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) -#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) -#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR -#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR - -/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ -#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) -#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) -#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR -#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR -#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR -#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR - -/* 24,25: dma8 and dma9 shared by ser1 and usb */ -#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) -#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) -#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR -#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR -#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR -#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR - -/* usb: controller at irq 31 + uses DMA8 and DMA9 */ -#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) - -/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ - -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; -void set_int_vector(int n, irqvectptr addr); -void set_break_vector(int n, irqvectptr addr); - -#define __STR(x) #x -#define STR(x) __STR(x) - -/* SAVE_ALL saves registers so they match pt_regs */ - -#define SAVE_ALL \ - "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ - "push $srp\n\t" /* push subroutine return pointer */ \ - "push $dccr\n\t" /* push condition codes */ \ - "push $mof\n\t" /* push multiply overflow reg */ \ - "di\n\t" /* need to disable irq's at this point */\ - "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ - "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ - "push $r10\n\t" /* push orig_r10 */ \ - "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ - - /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */ - -#define BLOCK_IRQ(mask,nr) \ - "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000d8]\n\t" - -#define UNBLOCK_IRQ(mask) \ - "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000dc]\n\t" - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) -#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) -#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) - - /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls - * do_IRQ (with irq disabled still). after that it unblocks and jumps to - * ret_from_intr (entry.S) - * - * The reason the IRQ is blocked is to allow an sti() before the handler which - * will acknowledge the interrupt is run. - */ - -#define BUILD_IRQ(nr,mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ - "moveq "#nr",$r10\n\t" \ - "move.d $sp,$r11\n\t" \ - "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ - UNBLOCK_IRQ(mask) \ - "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); - -/* This is subtle. The timer interrupt is crucial and it should not be disabled for - * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would - * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. - * If the softirq's take too much time to run, the timer irq won't run and the - * watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq - * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed - * it here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt is - * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not - * be an sti() before the timer irq handler is run to acknowledge the interrupt. - */ - -#define BUILD_TIMER_IRQ(nr,mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - "moveq "#nr",$r10\n\t" \ - "move.d $sp,$r11\n\t" \ - "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ - "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); - -#endif diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h deleted file mode 100644 index 13f3b971407f..000000000000 --- a/include/asm-cris/arch-v10/memmap.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h deleted file mode 100644 index df84f1716e6b..000000000000 --- a/include/asm-cris/arch-v10/mmu.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * CRIS MMU constants and PTE layout - */ - -#ifndef _CRIS_ARCH_MMU_H -#define _CRIS_ARCH_MMU_H - -/* type used in struct mm to couple an MMU context to an active mm */ - -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* kernel memory segments */ - -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* CRIS PTE bits (see R_TLB_LO in the register description) - * - * Bit: 31-13 12-------4 3 2 1 0 - * ________________________________________________ - * | pfn | reserved | global | valid | kernel | we | - * |_____|__________|________|_______|________|_____| - * - * (pfn = physical frame number) - */ - -/* Real HW-based PTE bits. We use some synonym names so that - * things become less confusing in combination with the SW-based - * bits further below. - * - */ - -#define _PAGE_WE (1<<0) /* page is write-enabled */ -#define _PAGE_SILENT_WRITE (1<<0) /* synonym */ -#define _PAGE_KERNEL (1<<1) /* page is kernel only */ -#define _PAGE_VALID (1<<2) /* page is valid */ -#define _PAGE_SILENT_READ (1<<2) /* synonym */ -#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ - -/* Bits the HW doesn't care about but the kernel uses them in SW */ - -#define _PAGE_PRESENT (1<<4) /* page present in memory */ -#define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */ -#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ -#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ -#define _PAGE_READ (1<<7) /* read-enabled */ -#define _PAGE_WRITE (1<<8) /* write-enabled */ - -/* Define some higher level generic page attributes. */ - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* - * CRIS can't do page protection for execute, and considers read the same. - * Also, write permissions imply read permissions. This is the closest we can - * get.. - */ - -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED - -#define PTE_FILE_MAX_BITS 26 - -#endif diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h deleted file mode 100644 index 675b51d85639..000000000000 --- a/include/asm-cris/arch-v10/offset.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 8 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 12 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 16 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 20 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 24 /* offsetof(struct pt_regs, r9) */ -#define PT_mof 64 /* offsetof(struct pt_regs, mof) */ -#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ -#define PT_srp 72 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ - -#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h deleted file mode 100644 index ffafc99c3472..000000000000 --- a/include/asm-cris/arch-v10/page.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _CRIS_ARCH_PAGE_H -#define _CRIS_ARCH_PAGE_H - - -#ifdef __KERNEL__ - -/* This handles the memory map.. */ -#ifdef CONFIG_CRIS_LOW_MAP -#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ -#else -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ -#endif - -/* macros to convert between really physical and virtual addresses - * by stripping a selected bit, we can convert between KSEG_x and - * 0x40000000 where the DRAM really resides - */ - -#ifdef CONFIG_CRIS_LOW_MAP -/* we have DRAM virtually at 0x6 */ -#define __pa(x) ((unsigned long)(x) & 0xdfffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) -#else -/* we have DRAM virtually at 0xc */ -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) -#endif - -#endif -#endif diff --git a/include/asm-cris/arch-v10/pgtable.h b/include/asm-cris/arch-v10/pgtable.h deleted file mode 100644 index 2a2576d1fc97..000000000000 --- a/include/asm-cris/arch-v10/pgtable.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _CRIS_ARCH_PGTABLE_H -#define _CRIS_ARCH_PGTABLE_H - -/* - * Kernels own virtual memory area. - */ - -#ifdef CONFIG_CRIS_LOW_MAP -#define VMALLOC_START KSEG_7 -#define VMALLOC_END KSEG_8 -#else -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#endif - -#endif - diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h deleted file mode 100644 index cc692c7a0660..000000000000 --- a/include/asm-cris/arch-v10/processor.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_PROCESSOR_H -#define __ASM_CRIS_ARCH_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) - -/* CRIS has no problems with write protection */ -#define wp_works_ok 1 - -/* CRIS thread_struct. this really has nothing to do with the processor itself, since - * CRIS does not do any hardware task-switching, but it's here for legacy reasons. - * The thread_struct here is used when task-switching using _resume defined in entry.S. - * The offsets here are hardcoded into _resume - if you change this struct, you need to - * change them as well!!! -*/ - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned long dccr; /* saved flag register */ -}; - -/* - * User space process size. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ - -#ifdef CONFIG_CRIS_LOW_MAP -#define TASK_SIZE (0x50000000UL) /* 1.25 GB */ -#else -#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ -#endif - -#define INIT_THREAD { \ - 0, 0, 0x20 } /* ccr = int enable, nothing else */ - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)task_pt_regs(tsk); \ - if (regs > PAGE_SIZE && \ - virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->irp; \ - eip; \ -}) - -/* give the thread a program location - * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) - * switch user-stackpointer - */ - -#define start_thread(regs, ip, usp) do { \ - set_fs(USER_DS); \ - regs->irp = ip; \ - regs->dccr |= 1 << U_DCCR_BITNR; \ - wrusp(usp); \ -} while(0) - -/* Called when handling a kernel bus fault fixup. - * - * After a fixup we do not want to return by restoring the CPU-state - * anymore, so switch frame-types (see ptrace.h) - */ -#define arch_fixup(regs) \ - regs->frametype = CRIS_FRAME_NORMAL; - -#endif diff --git a/include/asm-cris/arch-v10/ptrace.h b/include/asm-cris/arch-v10/ptrace.h deleted file mode 100644 index 2f464eab3a51..000000000000 --- a/include/asm-cris/arch-v10/ptrace.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Frame types */ - -#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ -#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return - path */ - -/* Register numbers in the ptrace system call interface */ - -#define PT_FRAMETYPE 0 -#define PT_ORIG_R10 1 -#define PT_R13 2 -#define PT_R12 3 -#define PT_R11 4 -#define PT_R10 5 -#define PT_R9 6 -#define PT_R8 7 -#define PT_R7 8 -#define PT_R6 9 -#define PT_R5 10 -#define PT_R4 11 -#define PT_R3 12 -#define PT_R2 13 -#define PT_R1 14 -#define PT_R0 15 -#define PT_MOF 16 -#define PT_DCCR 17 -#define PT_SRP 18 -#define PT_IRP 19 /* This is actually the debugged process' PC */ -#define PT_CSRINSTR 20 /* CPU Status record remnants - - valid if frametype == busfault */ -#define PT_CSRADDR 21 -#define PT_CSRDATA 22 -#define PT_USP 23 /* special case - USP is not in the pt_regs */ -#define PT_MAX 23 - -/* Condition code bit numbers. The same numbers apply to CCR of course, - but we use DCCR everywhere else, so let's try and be consistent. */ -#define C_DCCR_BITNR 0 -#define V_DCCR_BITNR 1 -#define Z_DCCR_BITNR 2 -#define N_DCCR_BITNR 3 -#define X_DCCR_BITNR 4 -#define I_DCCR_BITNR 5 -#define B_DCCR_BITNR 6 -#define M_DCCR_BITNR 7 -#define U_DCCR_BITNR 8 -#define P_DCCR_BITNR 9 -#define F_DCCR_BITNR 10 - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long frametype; /* type of stackframe */ - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ - unsigned long r13; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long mof; - unsigned long dccr; - unsigned long srp; - unsigned long irp; /* This is actually the debugged process' PC */ - unsigned long csrinstr; - unsigned long csraddr; - unsigned long csrdata; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -/* bit 8 is user-mode flag */ -#define user_mode(regs) (((regs)->dccr & 0x100) != 0) -#define instruction_pointer(regs) ((regs)->irp) -#define profile_pc(regs) instruction_pointer(regs) -extern void show_regs(struct pt_regs *); - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/arch-v10/sv_addr.agh b/include/asm-cris/arch-v10/sv_addr.agh deleted file mode 100644 index 6ac3a7bc9760..000000000000 --- a/include/asm-cris/arch-v10/sv_addr.agh +++ /dev/null @@ -1,7306 +0,0 @@ -/* -!* This file was automatically generated by /n/asic/bin/reg_macro_gen -!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. -!* Editing within this file is thus not recommended, -!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. -!*/ - - -/* -!* Bus interface configuration registers -!*/ - -#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_zw__WIDTH 2 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_ew__WIDTH 2 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__sram_lw__WIDTH 4 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_zw__WIDTH 2 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_ew__WIDTH 2 -#define R_WAITSTATES__flash_lw__BITNR 0 -#define R_WAITSTATES__flash_lw__WIDTH 4 - -#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__sram_type__WIDTH 1 -#define R_BUS_CONFIG__sram_type__cwe 1 -#define R_BUS_CONFIG__sram_type__bwe 0 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__dma_burst__WIDTH 1 -#define R_BUS_CONFIG__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__sram_wr__WIDTH 1 -#define R_BUS_CONFIG__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__flash_wr__WIDTH 1 -#define R_BUS_CONFIG__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__sram_bw__WIDTH 1 -#define R_BUS_CONFIG__sram_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__BITNR 0 -#define R_BUS_CONFIG__flash_bw__WIDTH 1 -#define R_BUS_CONFIG__flash_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__bw16 0 - -#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 -#define R_BUS_STATUS__pll_lock_tm__expired 0 -#define R_BUS_STATUS__pll_lock_tm__counting 1 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__both_faults__WIDTH 1 -#define R_BUS_STATUS__both_faults__no 0 -#define R_BUS_STATUS__both_faults__yes 1 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__bsen___WIDTH 1 -#define R_BUS_STATUS__bsen___enable 0 -#define R_BUS_STATUS__bsen___disable 1 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__boot__WIDTH 2 -#define R_BUS_STATUS__boot__uncached 0 -#define R_BUS_STATUS__boot__serial 1 -#define R_BUS_STATUS__boot__network 2 -#define R_BUS_STATUS__boot__parallel 3 -#define R_BUS_STATUS__flashw__BITNR 0 -#define R_BUS_STATUS__flashw__WIDTH 1 -#define R_BUS_STATUS__flashw__bw32 1 -#define R_BUS_STATUS__flashw__bw16 0 - -#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__sdram__WIDTH 1 -#define R_DRAM_TIMING__sdram__enable 1 -#define R_DRAM_TIMING__sdram__disable 0 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__ref__WIDTH 2 -#define R_DRAM_TIMING__ref__e52us 0 -#define R_DRAM_TIMING__ref__e13us 1 -#define R_DRAM_TIMING__ref__e8700ns 2 -#define R_DRAM_TIMING__ref__disable 3 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rp__WIDTH 2 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rs__WIDTH 2 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__rh__WIDTH 2 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__w__WIDTH 1 -#define R_DRAM_TIMING__w__norm 0 -#define R_DRAM_TIMING__w__ext 1 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__c__WIDTH 1 -#define R_DRAM_TIMING__c__norm 0 -#define R_DRAM_TIMING__c__ext 1 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cz__WIDTH 2 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cp__WIDTH 2 -#define R_DRAM_TIMING__cw__BITNR 0 -#define R_DRAM_TIMING__cw__WIDTH 2 - -#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__sdram__WIDTH 1 -#define R_SDRAM_TIMING__sdram__enable 1 -#define R_SDRAM_TIMING__sdram__disable 0 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__mrs_data__WIDTH 15 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ref__WIDTH 2 -#define R_SDRAM_TIMING__ref__e52us 0 -#define R_SDRAM_TIMING__ref__e13us 1 -#define R_SDRAM_TIMING__ref__e6500ns 2 -#define R_SDRAM_TIMING__ref__disable 3 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__ddr__WIDTH 1 -#define R_SDRAM_TIMING__ddr__on 1 -#define R_SDRAM_TIMING__ddr__off 0 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__clk100__WIDTH 1 -#define R_SDRAM_TIMING__clk100__on 1 -#define R_SDRAM_TIMING__clk100__off 0 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__ps__WIDTH 1 -#define R_SDRAM_TIMING__ps__on 1 -#define R_SDRAM_TIMING__ps__off 0 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__cmd__WIDTH 2 -#define R_SDRAM_TIMING__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__ref 2 -#define R_SDRAM_TIMING__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__nop 0 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__pde__WIDTH 1 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rc__WIDTH 2 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rp__WIDTH 2 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__rcd__WIDTH 2 -#define R_SDRAM_TIMING__cl__BITNR 0 -#define R_SDRAM_TIMING__cl__WIDTH 2 - -#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm1__WIDTH 1 -#define R_DRAM_CONFIG__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__wmm0__WIDTH 1 -#define R_DRAM_CONFIG__wmm0__wmm 1 -#define R_DRAM_CONFIG__wmm0__norm 0 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh1__WIDTH 3 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__sh0__WIDTH 3 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__w__WIDTH 1 -#define R_DRAM_CONFIG__w__bw16 0 -#define R_DRAM_CONFIG__w__bw32 1 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__c__WIDTH 1 -#define R_DRAM_CONFIG__c__byte 0 -#define R_DRAM_CONFIG__c__bank 1 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__e__WIDTH 1 -#define R_DRAM_CONFIG__e__fast 0 -#define R_DRAM_CONFIG__e__edo 1 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__group_sel__WIDTH 5 -#define R_DRAM_CONFIG__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__grp1 1 -#define R_DRAM_CONFIG__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__bit29 29 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__ca1__WIDTH 3 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__bank23sel__WIDTH 5 -#define R_DRAM_CONFIG__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bit29 29 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__ca0__WIDTH 3 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 -#define R_DRAM_CONFIG__bank01sel__WIDTH 5 -#define R_DRAM_CONFIG__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bit29 29 - -#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm1__WIDTH 1 -#define R_SDRAM_CONFIG__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__wmm0__WIDTH 1 -#define R_SDRAM_CONFIG__wmm0__wmm 1 -#define R_SDRAM_CONFIG__wmm0__norm 0 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh1__WIDTH 3 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__sh0__WIDTH 3 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__w__WIDTH 1 -#define R_SDRAM_CONFIG__w__bw16 0 -#define R_SDRAM_CONFIG__w__bw32 1 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type1__WIDTH 1 -#define R_SDRAM_CONFIG__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__type0__WIDTH 1 -#define R_SDRAM_CONFIG__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__group_sel__WIDTH 5 -#define R_SDRAM_CONFIG__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__grp1 1 -#define R_SDRAM_CONFIG__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__bit29 29 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__ca1__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__ca0__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 -#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel0__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bit29 29 - -/* -!* External DMA registers -!*/ - -#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_0_CMD__cnt__enable 1 -#define R_EXT_DMA_0_CMD__cnt__disable 0 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__apol__WIDTH 1 -#define R_EXT_DMA_0_CMD__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_0_CMD__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__wid__WIDTH 2 -#define R_EXT_DMA_0_CMD__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__word 1 -#define R_EXT_DMA_0_CMD__wid__dword 2 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__dir__WIDTH 1 -#define R_EXT_DMA_0_CMD__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__output 1 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__run__WIDTH 1 -#define R_EXT_DMA_0_CMD__run__start 1 -#define R_EXT_DMA_0_CMD__run__stop 0 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__run__WIDTH 1 -#define R_EXT_DMA_0_STAT__run__start 1 -#define R_EXT_DMA_0_STAT__run__stop 0 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 - -#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_1_CMD__cnt__enable 1 -#define R_EXT_DMA_1_CMD__cnt__disable 0 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__apol__WIDTH 1 -#define R_EXT_DMA_1_CMD__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_1_CMD__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__wid__WIDTH 2 -#define R_EXT_DMA_1_CMD__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__word 1 -#define R_EXT_DMA_1_CMD__wid__dword 2 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__dir__WIDTH 1 -#define R_EXT_DMA_1_CMD__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__output 1 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__run__WIDTH 1 -#define R_EXT_DMA_1_CMD__run__start 1 -#define R_EXT_DMA_1_CMD__run__stop 0 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__run__WIDTH 1 -#define R_EXT_DMA_1_STAT__run__start 1 -#define R_EXT_DMA_1_STAT__run__stop 0 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 - -/* -!* Timer registers -!*/ - -#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv1__WIDTH 8 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__timerdiv0__WIDTH 8 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__presc_timer1__WIDTH 1 -#define R_TIMER_CTRL__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__i1__WIDTH 1 -#define R_TIMER_CTRL__i1__clr 1 -#define R_TIMER_CTRL__i1__nop 0 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__tm1__WIDTH 2 -#define R_TIMER_CTRL__tm1__stop_ld 0 -#define R_TIMER_CTRL__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__run 2 -#define R_TIMER_CTRL__tm1__reserved 3 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__clksel1__WIDTH 4 -#define R_TIMER_CTRL__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__presc_ext__WIDTH 1 -#define R_TIMER_CTRL__presc_ext__prescale 0 -#define R_TIMER_CTRL__presc_ext__external 1 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__i0__WIDTH 1 -#define R_TIMER_CTRL__i0__clr 1 -#define R_TIMER_CTRL__i0__nop 0 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__tm0__WIDTH 2 -#define R_TIMER_CTRL__tm0__stop_ld 0 -#define R_TIMER_CTRL__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__run 2 -#define R_TIMER_CTRL__tm0__reserved 3 -#define R_TIMER_CTRL__clksel0__BITNR 0 -#define R_TIMER_CTRL__clksel0__WIDTH 4 -#define R_TIMER_CTRL__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__flexible 15 - -#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer1__WIDTH 8 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__timer0__WIDTH 8 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_high__WIDTH 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 -#define R_TIMER_DATA__clkdiv_low__WIDTH 8 - -#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) -#define R_TIMER01_DATA__count__BITNR 0 -#define R_TIMER01_DATA__count__WIDTH 16 - -#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) -#define R_TIMER0_DATA__count__BITNR 0 -#define R_TIMER0_DATA__count__WIDTH 8 - -#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) -#define R_TIMER1_DATA__count__BITNR 0 -#define R_TIMER1_DATA__count__WIDTH 8 - -#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__key__WIDTH 3 -#define R_WATCHDOG__enable__BITNR 0 -#define R_WATCHDOG__enable__WIDTH 1 -#define R_WATCHDOG__enable__stop 0 -#define R_WATCHDOG__enable__start 1 - -#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 -#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 - -#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 -#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 - -#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 -#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 - -#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__ser_status__WIDTH 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 -#define R_PRESCALE_STATUS__tim_status__WIDTH 16 - -#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 -#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 - -#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 -#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 - -#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 - -/* -!* Shared RAM interface registers -!*/ - -#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__width__WIDTH 1 -#define R_SHARED_RAM_CONFIG__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 -#define R_SHARED_RAM_CONFIG__enable__yes 1 -#define R_SHARED_RAM_CONFIG__enable__no 0 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 -#define R_SHARED_RAM_CONFIG__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 -#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 -#define R_SHARED_RAM_CONFIG__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__nop 0 - -#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 -#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 - -/* -!* General config registers -!*/ - -#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__par_w__WIDTH 1 -#define R_GEN_CONFIG__par_w__select 1 -#define R_GEN_CONFIG__par_w__disable 0 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb2__WIDTH 1 -#define R_GEN_CONFIG__usb2__select 1 -#define R_GEN_CONFIG__usb2__disable 0 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__usb1__WIDTH 1 -#define R_GEN_CONFIG__usb1__select 1 -#define R_GEN_CONFIG__usb1__disable 0 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g24dir__WIDTH 1 -#define R_GEN_CONFIG__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_23dir__WIDTH 1 -#define R_GEN_CONFIG__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__out 1 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g8_15dir__WIDTH 1 -#define R_GEN_CONFIG__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__g0dir__WIDTH 1 -#define R_GEN_CONFIG__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__out 1 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma9__WIDTH 1 -#define R_GEN_CONFIG__dma9__usb 0 -#define R_GEN_CONFIG__dma9__serial1 1 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma8__WIDTH 1 -#define R_GEN_CONFIG__dma8__usb 0 -#define R_GEN_CONFIG__dma8__serial1 1 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma7__WIDTH 2 -#define R_GEN_CONFIG__dma7__unused 0 -#define R_GEN_CONFIG__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__intdma6 3 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma6__WIDTH 2 -#define R_GEN_CONFIG__dma6__unused 0 -#define R_GEN_CONFIG__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__intdma7 3 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma5__WIDTH 2 -#define R_GEN_CONFIG__dma5__par1 0 -#define R_GEN_CONFIG__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__serial3 2 -#define R_GEN_CONFIG__dma5__extdma0 3 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma4__WIDTH 2 -#define R_GEN_CONFIG__dma4__par1 0 -#define R_GEN_CONFIG__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__serial3 2 -#define R_GEN_CONFIG__dma4__extdma0 3 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma3__WIDTH 2 -#define R_GEN_CONFIG__dma3__par0 0 -#define R_GEN_CONFIG__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__serial2 2 -#define R_GEN_CONFIG__dma3__ata 3 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__dma2__WIDTH 2 -#define R_GEN_CONFIG__dma2__par0 0 -#define R_GEN_CONFIG__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__serial2 2 -#define R_GEN_CONFIG__dma2__ata 3 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__mio_w__WIDTH 1 -#define R_GEN_CONFIG__mio_w__select 1 -#define R_GEN_CONFIG__mio_w__disable 0 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__ser3__WIDTH 1 -#define R_GEN_CONFIG__ser3__select 1 -#define R_GEN_CONFIG__ser3__disable 0 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__par1__WIDTH 1 -#define R_GEN_CONFIG__par1__select 1 -#define R_GEN_CONFIG__par1__disable 0 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi0w__WIDTH 1 -#define R_GEN_CONFIG__scsi0w__select 1 -#define R_GEN_CONFIG__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__scsi1__WIDTH 1 -#define R_GEN_CONFIG__scsi1__select 1 -#define R_GEN_CONFIG__scsi1__disable 0 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__mio__WIDTH 1 -#define R_GEN_CONFIG__mio__select 1 -#define R_GEN_CONFIG__mio__disable 0 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__ser2__WIDTH 1 -#define R_GEN_CONFIG__ser2__select 1 -#define R_GEN_CONFIG__ser2__disable 0 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__par0__WIDTH 1 -#define R_GEN_CONFIG__par0__select 1 -#define R_GEN_CONFIG__par0__disable 0 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__ata__WIDTH 1 -#define R_GEN_CONFIG__ata__select 1 -#define R_GEN_CONFIG__ata__disable 0 -#define R_GEN_CONFIG__scsi0__BITNR 0 -#define R_GEN_CONFIG__scsi0__WIDTH 1 -#define R_GEN_CONFIG__scsi0__select 1 -#define R_GEN_CONFIG__scsi0__disable 0 - -#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode3__WIDTH 1 -#define R_GEN_CONFIG_II__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__sermode1__WIDTH 1 -#define R_GEN_CONFIG_II__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 -#define R_GEN_CONFIG_II__ext_clk__select 1 -#define R_GEN_CONFIG_II__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ser2__BITNR 1 -#define R_GEN_CONFIG_II__ser2__WIDTH 1 -#define R_GEN_CONFIG_II__ser2__select 1 -#define R_GEN_CONFIG_II__ser2__disable 0 -#define R_GEN_CONFIG_II__ser3__BITNR 0 -#define R_GEN_CONFIG_II__ser3__WIDTH 1 -#define R_GEN_CONFIG_II__ser3__select 1 -#define R_GEN_CONFIG_II__ser3__disable 0 - -#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__data__BITNR 0 -#define R_PORT_G_DATA__data__WIDTH 32 - -/* -!* General port configuration registers -!*/ - -#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir7__WIDTH 1 -#define R_PORT_PA_SET__dir7__input 0 -#define R_PORT_PA_SET__dir7__output 1 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir6__WIDTH 1 -#define R_PORT_PA_SET__dir6__input 0 -#define R_PORT_PA_SET__dir6__output 1 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir5__WIDTH 1 -#define R_PORT_PA_SET__dir5__input 0 -#define R_PORT_PA_SET__dir5__output 1 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir4__WIDTH 1 -#define R_PORT_PA_SET__dir4__input 0 -#define R_PORT_PA_SET__dir4__output 1 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir3__WIDTH 1 -#define R_PORT_PA_SET__dir3__input 0 -#define R_PORT_PA_SET__dir3__output 1 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir2__WIDTH 1 -#define R_PORT_PA_SET__dir2__input 0 -#define R_PORT_PA_SET__dir2__output 1 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir1__WIDTH 1 -#define R_PORT_PA_SET__dir1__input 0 -#define R_PORT_PA_SET__dir1__output 1 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__dir0__WIDTH 1 -#define R_PORT_PA_SET__dir0__input 0 -#define R_PORT_PA_SET__dir0__output 1 -#define R_PORT_PA_SET__data_out__BITNR 0 -#define R_PORT_PA_SET__data_out__WIDTH 8 - -#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) -#define R_PORT_PA_DATA__data_out__BITNR 0 -#define R_PORT_PA_DATA__data_out__WIDTH 8 - -#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir7__WIDTH 1 -#define R_PORT_PA_DIR__dir7__input 0 -#define R_PORT_PA_DIR__dir7__output 1 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir6__WIDTH 1 -#define R_PORT_PA_DIR__dir6__input 0 -#define R_PORT_PA_DIR__dir6__output 1 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir5__WIDTH 1 -#define R_PORT_PA_DIR__dir5__input 0 -#define R_PORT_PA_DIR__dir5__output 1 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir4__WIDTH 1 -#define R_PORT_PA_DIR__dir4__input 0 -#define R_PORT_PA_DIR__dir4__output 1 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir3__WIDTH 1 -#define R_PORT_PA_DIR__dir3__input 0 -#define R_PORT_PA_DIR__dir3__output 1 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir2__WIDTH 1 -#define R_PORT_PA_DIR__dir2__input 0 -#define R_PORT_PA_DIR__dir2__output 1 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir1__WIDTH 1 -#define R_PORT_PA_DIR__dir1__input 0 -#define R_PORT_PA_DIR__dir1__output 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 -#define R_PORT_PA_DIR__dir0__WIDTH 1 -#define R_PORT_PA_DIR__dir0__input 0 -#define R_PORT_PA_DIR__dir0__output 1 - -#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) -#define R_PORT_PA_READ__data_in__BITNR 0 -#define R_PORT_PA_READ__data_in__WIDTH 8 - -#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser3__WIDTH 1 -#define R_PORT_PB_SET__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__syncser1__WIDTH 1 -#define R_PORT_PB_SET__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_en__WIDTH 1 -#define R_PORT_PB_SET__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_d__WIDTH 1 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_clk__WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__i2c_oe___WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___enable 0 -#define R_PORT_PB_SET__i2c_oe___disable 1 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs7__WIDTH 1 -#define R_PORT_PB_SET__cs7__port 0 -#define R_PORT_PB_SET__cs7__cs 1 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs6__WIDTH 1 -#define R_PORT_PB_SET__cs6__port 0 -#define R_PORT_PB_SET__cs6__cs 1 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs5__WIDTH 1 -#define R_PORT_PB_SET__cs5__port 0 -#define R_PORT_PB_SET__cs5__cs 1 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs4__WIDTH 1 -#define R_PORT_PB_SET__cs4__port 0 -#define R_PORT_PB_SET__cs4__cs 1 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs3__WIDTH 1 -#define R_PORT_PB_SET__cs3__port 0 -#define R_PORT_PB_SET__cs3__cs 1 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__cs2__WIDTH 1 -#define R_PORT_PB_SET__cs2__port 0 -#define R_PORT_PB_SET__cs2__cs 1 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi1__WIDTH 1 -#define R_PORT_PB_SET__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi1__enph 1 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__scsi0__WIDTH 1 -#define R_PORT_PB_SET__scsi0__port_cs 0 -#define R_PORT_PB_SET__scsi0__enph 1 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir7__WIDTH 1 -#define R_PORT_PB_SET__dir7__input 0 -#define R_PORT_PB_SET__dir7__output 1 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir6__WIDTH 1 -#define R_PORT_PB_SET__dir6__input 0 -#define R_PORT_PB_SET__dir6__output 1 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir5__WIDTH 1 -#define R_PORT_PB_SET__dir5__input 0 -#define R_PORT_PB_SET__dir5__output 1 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir4__WIDTH 1 -#define R_PORT_PB_SET__dir4__input 0 -#define R_PORT_PB_SET__dir4__output 1 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir3__WIDTH 1 -#define R_PORT_PB_SET__dir3__input 0 -#define R_PORT_PB_SET__dir3__output 1 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir2__WIDTH 1 -#define R_PORT_PB_SET__dir2__input 0 -#define R_PORT_PB_SET__dir2__output 1 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir1__WIDTH 1 -#define R_PORT_PB_SET__dir1__input 0 -#define R_PORT_PB_SET__dir1__output 1 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__dir0__WIDTH 1 -#define R_PORT_PB_SET__dir0__input 0 -#define R_PORT_PB_SET__dir0__output 1 -#define R_PORT_PB_SET__data_out__BITNR 0 -#define R_PORT_PB_SET__data_out__WIDTH 8 - -#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) -#define R_PORT_PB_DATA__data_out__BITNR 0 -#define R_PORT_PB_DATA__data_out__WIDTH 8 - -#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir7__WIDTH 1 -#define R_PORT_PB_DIR__dir7__input 0 -#define R_PORT_PB_DIR__dir7__output 1 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir6__WIDTH 1 -#define R_PORT_PB_DIR__dir6__input 0 -#define R_PORT_PB_DIR__dir6__output 1 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir5__WIDTH 1 -#define R_PORT_PB_DIR__dir5__input 0 -#define R_PORT_PB_DIR__dir5__output 1 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir4__WIDTH 1 -#define R_PORT_PB_DIR__dir4__input 0 -#define R_PORT_PB_DIR__dir4__output 1 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir3__WIDTH 1 -#define R_PORT_PB_DIR__dir3__input 0 -#define R_PORT_PB_DIR__dir3__output 1 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir2__WIDTH 1 -#define R_PORT_PB_DIR__dir2__input 0 -#define R_PORT_PB_DIR__dir2__output 1 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir1__WIDTH 1 -#define R_PORT_PB_DIR__dir1__input 0 -#define R_PORT_PB_DIR__dir1__output 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 -#define R_PORT_PB_DIR__dir0__WIDTH 1 -#define R_PORT_PB_DIR__dir0__input 0 -#define R_PORT_PB_DIR__dir0__output 1 - -#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs7__WIDTH 1 -#define R_PORT_PB_CONFIG__cs7__port 0 -#define R_PORT_PB_CONFIG__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs6__WIDTH 1 -#define R_PORT_PB_CONFIG__cs6__port 0 -#define R_PORT_PB_CONFIG__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs5__WIDTH 1 -#define R_PORT_PB_CONFIG__cs5__port 0 -#define R_PORT_PB_CONFIG__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs4__WIDTH 1 -#define R_PORT_PB_CONFIG__cs4__port 0 -#define R_PORT_PB_CONFIG__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs3__WIDTH 1 -#define R_PORT_PB_CONFIG__cs3__port 0 -#define R_PORT_PB_CONFIG__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__cs2__WIDTH 1 -#define R_PORT_PB_CONFIG__cs2__port 0 -#define R_PORT_PB_CONFIG__cs2__cs 1 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 -#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi0__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__enph 1 - -#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser3__WIDTH 1 -#define R_PORT_PB_I2C__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__syncser1__WIDTH 1 -#define R_PORT_PB_I2C__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_en__WIDTH 1 -#define R_PORT_PB_I2C__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_d__WIDTH 1 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 -#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___enable 0 -#define R_PORT_PB_I2C__i2c_oe___disable 1 - -#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) -#define R_PORT_PB_READ__data_in__BITNR 0 -#define R_PORT_PB_READ__data_in__WIDTH 8 - -/* -!* Serial port registers -!*/ - -#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__reserved 15 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__reserved 15 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_CTRL__dma_err__stop 0 -#define R_SERIAL0_CTRL__dma_err__ignore 1 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_CTRL__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__rts___WIDTH 1 -#define R_SERIAL0_CTRL__rts___active 0 -#define R_SERIAL0_CTRL__rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_CTRL__sampling__middle 0 -#define R_SERIAL0_CTRL__sampling__majority 1 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__txd__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__auto_cts__active 1 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__data_out__BITNR 0 -#define R_SERIAL0_CTRL__data_out__WIDTH 8 - -#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__reserved 15 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 -#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__reserved 15 - -#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_REC_CTRL__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL0_REC_CTRL__rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_REC_CTRL__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 -#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__xoff_detect__WIDTH 1 -#define R_SERIAL0_READ__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__cts___WIDTH 1 -#define R_SERIAL0_READ__cts___active 0 -#define R_SERIAL0_READ__cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__tr_ready__WIDTH 1 -#define R_SERIAL0_READ__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__ready 1 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__rxd__WIDTH 1 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__overrun__WIDTH 1 -#define R_SERIAL0_READ__overrun__no 0 -#define R_SERIAL0_READ__overrun__yes 1 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__par_err__WIDTH 1 -#define R_SERIAL0_READ__par_err__no 0 -#define R_SERIAL0_READ__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__framing_err__WIDTH 1 -#define R_SERIAL0_READ__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_avail__WIDTH 1 -#define R_SERIAL0_READ__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__yes 1 -#define R_SERIAL0_READ__data_in__BITNR 0 -#define R_SERIAL0_READ__data_in__WIDTH 8 - -#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__cts___WIDTH 1 -#define R_SERIAL0_STATUS__cts___active 0 -#define R_SERIAL0_STATUS__cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL0_STATUS__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__ready 1 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__rxd__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__overrun__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__par_err__WIDTH 1 -#define R_SERIAL0_STATUS__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__framing_err__WIDTH 1 -#define R_SERIAL0_STATUS__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 -#define R_SERIAL0_STATUS__data_avail__WIDTH 1 -#define R_SERIAL0_STATUS__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__yes 1 - -#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 -#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL0_XOFF__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL0_XOFF__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__enable 1 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 -#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__reserved 15 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_CTRL__dma_err__stop 0 -#define R_SERIAL1_CTRL__dma_err__ignore 1 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__rts___WIDTH 1 -#define R_SERIAL1_CTRL__rts___active 0 -#define R_SERIAL1_CTRL__rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_CTRL__sampling__middle 0 -#define R_SERIAL1_CTRL__sampling__majority 1 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__txd__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__auto_cts__active 1 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__data_out__BITNR 0 -#define R_SERIAL1_CTRL__data_out__WIDTH 8 - -#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__reserved 15 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 -#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__reserved 15 - -#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_REC_CTRL__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL1_REC_CTRL__rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_REC_CTRL__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__xoff_detect__WIDTH 1 -#define R_SERIAL1_READ__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__cts___WIDTH 1 -#define R_SERIAL1_READ__cts___active 0 -#define R_SERIAL1_READ__cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__tr_ready__WIDTH 1 -#define R_SERIAL1_READ__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__ready 1 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__rxd__WIDTH 1 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__overrun__WIDTH 1 -#define R_SERIAL1_READ__overrun__no 0 -#define R_SERIAL1_READ__overrun__yes 1 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__par_err__WIDTH 1 -#define R_SERIAL1_READ__par_err__no 0 -#define R_SERIAL1_READ__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__framing_err__WIDTH 1 -#define R_SERIAL1_READ__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_avail__WIDTH 1 -#define R_SERIAL1_READ__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__yes 1 -#define R_SERIAL1_READ__data_in__BITNR 0 -#define R_SERIAL1_READ__data_in__WIDTH 8 - -#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__cts___WIDTH 1 -#define R_SERIAL1_STATUS__cts___active 0 -#define R_SERIAL1_STATUS__cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL1_STATUS__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__rxd__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__par_err__WIDTH 1 -#define R_SERIAL1_STATUS__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__framing_err__WIDTH 1 -#define R_SERIAL1_STATUS__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 -#define R_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SERIAL1_STATUS__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__yes 1 - -#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL1_XOFF__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL1_XOFF__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__enable 1 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 -#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__reserved 15 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__reserved 15 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_CTRL__dma_err__stop 0 -#define R_SERIAL2_CTRL__dma_err__ignore 1 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_CTRL__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__rts___WIDTH 1 -#define R_SERIAL2_CTRL__rts___active 0 -#define R_SERIAL2_CTRL__rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_CTRL__sampling__middle 0 -#define R_SERIAL2_CTRL__sampling__majority 1 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__txd__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__auto_cts__active 1 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__data_out__BITNR 0 -#define R_SERIAL2_CTRL__data_out__WIDTH 8 - -#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__reserved 15 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 -#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__reserved 15 - -#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_REC_CTRL__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL2_REC_CTRL__rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_REC_CTRL__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 -#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__xoff_detect__WIDTH 1 -#define R_SERIAL2_READ__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__cts___WIDTH 1 -#define R_SERIAL2_READ__cts___active 0 -#define R_SERIAL2_READ__cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__tr_ready__WIDTH 1 -#define R_SERIAL2_READ__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__ready 1 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__rxd__WIDTH 1 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__overrun__WIDTH 1 -#define R_SERIAL2_READ__overrun__no 0 -#define R_SERIAL2_READ__overrun__yes 1 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__par_err__WIDTH 1 -#define R_SERIAL2_READ__par_err__no 0 -#define R_SERIAL2_READ__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__framing_err__WIDTH 1 -#define R_SERIAL2_READ__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_avail__WIDTH 1 -#define R_SERIAL2_READ__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__yes 1 -#define R_SERIAL2_READ__data_in__BITNR 0 -#define R_SERIAL2_READ__data_in__WIDTH 8 - -#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__cts___WIDTH 1 -#define R_SERIAL2_STATUS__cts___active 0 -#define R_SERIAL2_STATUS__cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL2_STATUS__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__ready 1 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__rxd__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__overrun__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__par_err__WIDTH 1 -#define R_SERIAL2_STATUS__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__framing_err__WIDTH 1 -#define R_SERIAL2_STATUS__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 -#define R_SERIAL2_STATUS__data_avail__WIDTH 1 -#define R_SERIAL2_STATUS__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__yes 1 - -#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 -#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL2_XOFF__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL2_XOFF__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__enable 1 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 -#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__reserved 15 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_CTRL__dma_err__stop 0 -#define R_SERIAL3_CTRL__dma_err__ignore 1 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__rts___WIDTH 1 -#define R_SERIAL3_CTRL__rts___active 0 -#define R_SERIAL3_CTRL__rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_CTRL__sampling__middle 0 -#define R_SERIAL3_CTRL__sampling__majority 1 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__txd__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__auto_cts__active 1 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__data_out__BITNR 0 -#define R_SERIAL3_CTRL__data_out__WIDTH 8 - -#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__reserved 15 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 -#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__reserved 15 - -#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_REC_CTRL__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL3_REC_CTRL__rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_REC_CTRL__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__xoff_detect__WIDTH 1 -#define R_SERIAL3_READ__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__cts___WIDTH 1 -#define R_SERIAL3_READ__cts___active 0 -#define R_SERIAL3_READ__cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__tr_ready__WIDTH 1 -#define R_SERIAL3_READ__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__ready 1 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__rxd__WIDTH 1 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__overrun__WIDTH 1 -#define R_SERIAL3_READ__overrun__no 0 -#define R_SERIAL3_READ__overrun__yes 1 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__par_err__WIDTH 1 -#define R_SERIAL3_READ__par_err__no 0 -#define R_SERIAL3_READ__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__framing_err__WIDTH 1 -#define R_SERIAL3_READ__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_avail__WIDTH 1 -#define R_SERIAL3_READ__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__yes 1 -#define R_SERIAL3_READ__data_in__BITNR 0 -#define R_SERIAL3_READ__data_in__WIDTH 8 - -#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__cts___WIDTH 1 -#define R_SERIAL3_STATUS__cts___active 0 -#define R_SERIAL3_STATUS__cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL3_STATUS__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__rxd__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__par_err__WIDTH 1 -#define R_SERIAL3_STATUS__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__framing_err__WIDTH 1 -#define R_SERIAL3_STATUS__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 -#define R_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SERIAL3_STATUS__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__yes 1 - -#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL3_XOFF__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL3_XOFF__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__enable 1 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 -#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 - -#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 - -/* -!* Network interface registers -!*/ - -#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) -#define R_NETWORK_SA_0__ma0_low__BITNR 0 -#define R_NETWORK_SA_0__ma0_low__WIDTH 32 - -#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma1_low__WIDTH 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 -#define R_NETWORK_SA_1__ma0_high__WIDTH 16 - -#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) -#define R_NETWORK_SA_2__ma1_high__BITNR 0 -#define R_NETWORK_SA_2__ma1_high__WIDTH 32 - -#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) -#define R_NETWORK_GA_0__ga_low__BITNR 0 -#define R_NETWORK_GA_0__ga_low__WIDTH 32 - -#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) -#define R_NETWORK_GA_1__ga_high__BITNR 0 -#define R_NETWORK_GA_1__ga_high__WIDTH 32 - -#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 -#define R_NETWORK_REC_CONFIG__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 -#define R_NETWORK_REC_CONFIG__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 -#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 -#define R_NETWORK_REC_CONFIG__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 -#define R_NETWORK_REC_CONFIG__individual__receive 1 -#define R_NETWORK_REC_CONFIG__individual__discard 0 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 -#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma0__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__disable 0 - -#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__vg__on 1 -#define R_NETWORK_GEN_CONFIG__vg__off 0 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 -#define R_NETWORK_GEN_CONFIG__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 -#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__enable__on 1 -#define R_NETWORK_GEN_CONFIG__enable__off 0 - -#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 -#define R_NETWORK_TR_CTRL__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__delay__WIDTH 1 -#define R_NETWORK_TR_CTRL__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 -#define R_NETWORK_TR_CTRL__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__cd__WIDTH 1 -#define R_NETWORK_TR_CTRL__cd__enable 0 -#define R_NETWORK_TR_CTRL__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__retry__WIDTH 1 -#define R_NETWORK_TR_CTRL__retry__enable 0 -#define R_NETWORK_TR_CTRL__retry__disable 1 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__pad__WIDTH 1 -#define R_NETWORK_TR_CTRL__pad__enable 1 -#define R_NETWORK_TR_CTRL__pad__disable 0 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 -#define R_NETWORK_TR_CTRL__crc__WIDTH 1 -#define R_NETWORK_TR_CTRL__crc__enable 0 -#define R_NETWORK_TR_CTRL__crc__disable 1 - -#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__enable 1 -#define R_NETWORK_MGM_CTRL__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 -#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 - -#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxd_pins__WIDTH 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__rxer__WIDTH 1 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__underrun__WIDTH 1 -#define R_NETWORK_STAT__underrun__yes 1 -#define R_NETWORK_STAT__underrun__no 0 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__exc_col__WIDTH 1 -#define R_NETWORK_STAT__exc_col__yes 1 -#define R_NETWORK_STAT__exc_col__no 0 -#define R_NETWORK_STAT__mdio__BITNR 0 -#define R_NETWORK_STAT__mdio__WIDTH 1 - -#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__congestion__WIDTH 8 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__oversize__WIDTH 8 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__alignment_error__WIDTH 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 -#define R_REC_COUNTERS__crc_error__WIDTH 8 - -#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__deferred__WIDTH 8 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__late_col__WIDTH 8 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__multiple_col__WIDTH 8 -#define R_TR_COUNTERS__single_col__BITNR 0 -#define R_TR_COUNTERS__single_col__WIDTH 8 - -#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 -#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 - -/* -!* Parallel printer port registers -!*/ - -#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR0_CTRL_DATA__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__oe__WIDTH 1 -#define R_PAR0_CTRL_DATA__oe__enable 1 -#define R_PAR0_CTRL_DATA__oe__disable 0 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__seli__WIDTH 1 -#define R_PAR0_CTRL_DATA__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR0_CTRL_DATA__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__strb__WIDTH 1 -#define R_PAR0_CTRL_DATA__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__init__WIDTH 1 -#define R_PAR0_CTRL_DATA__init__active 1 -#define R_PAR0_CTRL_DATA__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR0_CTRL_DATA__data__BITNR 0 -#define R_PAR0_CTRL_DATA__data__WIDTH 8 - -#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) -#define R_PAR0_CTRL__ctrl__BITNR 0 -#define R_PAR0_CTRL__ctrl__WIDTH 5 - -#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__mode__WIDTH 3 -#define R_PAR0_STATUS_DATA__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__off 7 -#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__perr__WIDTH 1 -#define R_PAR0_STATUS_DATA__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__ack__WIDTH 1 -#define R_PAR0_STATUS_DATA__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__busy__WIDTH 1 -#define R_PAR0_STATUS_DATA__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__fault__WIDTH 1 -#define R_PAR0_STATUS_DATA__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__sel__WIDTH 1 -#define R_PAR0_STATUS_DATA__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR0_STATUS_DATA__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__dav__WIDTH 1 -#define R_PAR0_STATUS_DATA__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR0_STATUS_DATA__data__BITNR 0 -#define R_PAR0_STATUS_DATA__data__WIDTH 8 - -#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__mode__WIDTH 3 -#define R_PAR0_STATUS__mode__manual 0 -#define R_PAR0_STATUS__mode__centronics 1 -#define R_PAR0_STATUS__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__nibble 3 -#define R_PAR0_STATUS__mode__byte 4 -#define R_PAR0_STATUS__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__off 7 -#define R_PAR0_STATUS__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__epp_rd 0 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__perr__WIDTH 1 -#define R_PAR0_STATUS__perr__active 1 -#define R_PAR0_STATUS__perr__inactive 0 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__ack__WIDTH 1 -#define R_PAR0_STATUS__ack__active 0 -#define R_PAR0_STATUS__ack__inactive 1 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__busy__WIDTH 1 -#define R_PAR0_STATUS__busy__active 1 -#define R_PAR0_STATUS__busy__inactive 0 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__fault__WIDTH 1 -#define R_PAR0_STATUS__fault__active 0 -#define R_PAR0_STATUS__fault__inactive 1 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__sel__WIDTH 1 -#define R_PAR0_STATUS__sel__active 1 -#define R_PAR0_STATUS__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ext_mode__WIDTH 1 -#define R_PAR0_STATUS__ext_mode__enable 1 -#define R_PAR0_STATUS__ext_mode__disable 0 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__ecp_16__WIDTH 1 -#define R_PAR0_STATUS__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS__tr_rdy__ready 1 -#define R_PAR0_STATUS__tr_rdy__busy 0 -#define R_PAR0_STATUS__dav__BITNR 0 -#define R_PAR0_STATUS__dav__WIDTH 1 -#define R_PAR0_STATUS__dav__data 1 -#define R_PAR0_STATUS__dav__nodata 0 - -#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__data__BITNR 0 -#define R_PAR_ECP16_DATA__data__WIDTH 16 - -#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__ioe__WIDTH 1 -#define R_PAR0_CONFIG__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iseli__WIDTH 1 -#define R_PAR0_CONFIG__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__iautofd__WIDTH 1 -#define R_PAR0_CONFIG__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__istrb__WIDTH 1 -#define R_PAR0_CONFIG__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iinit__WIDTH 1 -#define R_PAR0_CONFIG__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iperr__WIDTH 1 -#define R_PAR0_CONFIG__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__iack__WIDTH 1 -#define R_PAR0_CONFIG__iack__inv 1 -#define R_PAR0_CONFIG__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ibusy__WIDTH 1 -#define R_PAR0_CONFIG__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__ifault__WIDTH 1 -#define R_PAR0_CONFIG__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__isel__WIDTH 1 -#define R_PAR0_CONFIG__isel__inv 1 -#define R_PAR0_CONFIG__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__ext_mode__WIDTH 1 -#define R_PAR0_CONFIG__ext_mode__enable 1 -#define R_PAR0_CONFIG__ext_mode__disable 0 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__wide__WIDTH 1 -#define R_PAR0_CONFIG__wide__enable 1 -#define R_PAR0_CONFIG__wide__disable 0 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__dma__WIDTH 1 -#define R_PAR0_CONFIG__dma__enable 1 -#define R_PAR0_CONFIG__dma__disable 0 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_in__WIDTH 1 -#define R_PAR0_CONFIG__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__rle_out__WIDTH 1 -#define R_PAR0_CONFIG__rle_out__enable 1 -#define R_PAR0_CONFIG__rle_out__disable 0 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__enable__WIDTH 1 -#define R_PAR0_CONFIG__enable__on 1 -#define R_PAR0_CONFIG__enable__reset 0 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__force__WIDTH 1 -#define R_PAR0_CONFIG__force__on 1 -#define R_PAR0_CONFIG__force__off 0 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__ign_ack__WIDTH 1 -#define R_PAR0_CONFIG__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__oe_ack__WIDTH 1 -#define R_PAR0_CONFIG__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__mode__BITNR 0 -#define R_PAR0_CONFIG__mode__WIDTH 3 -#define R_PAR0_CONFIG__mode__manual 0 -#define R_PAR0_CONFIG__mode__centronics 1 -#define R_PAR0_CONFIG__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__nibble 3 -#define R_PAR0_CONFIG__mode__byte 4 -#define R_PAR0_CONFIG__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__off 7 -#define R_PAR0_CONFIG__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__epp_rd 0 - -#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__fine_hold__WIDTH 3 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__hold__WIDTH 5 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__fine_strb__WIDTH 3 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__strobe__WIDTH 5 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__fine_setup__WIDTH 3 -#define R_PAR0_DELAY__setup__BITNR 0 -#define R_PAR0_DELAY__setup__WIDTH 5 - -#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR1_CTRL_DATA__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__oe__WIDTH 1 -#define R_PAR1_CTRL_DATA__oe__enable 1 -#define R_PAR1_CTRL_DATA__oe__disable 0 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__seli__WIDTH 1 -#define R_PAR1_CTRL_DATA__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR1_CTRL_DATA__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__strb__WIDTH 1 -#define R_PAR1_CTRL_DATA__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__init__WIDTH 1 -#define R_PAR1_CTRL_DATA__init__active 1 -#define R_PAR1_CTRL_DATA__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR1_CTRL_DATA__data__BITNR 0 -#define R_PAR1_CTRL_DATA__data__WIDTH 8 - -#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) -#define R_PAR1_CTRL__ctrl__BITNR 0 -#define R_PAR1_CTRL__ctrl__WIDTH 5 - -#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__mode__WIDTH 3 -#define R_PAR1_STATUS_DATA__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__off 7 -#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__perr__WIDTH 1 -#define R_PAR1_STATUS_DATA__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__ack__WIDTH 1 -#define R_PAR1_STATUS_DATA__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__busy__WIDTH 1 -#define R_PAR1_STATUS_DATA__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__fault__WIDTH 1 -#define R_PAR1_STATUS_DATA__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__sel__WIDTH 1 -#define R_PAR1_STATUS_DATA__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR1_STATUS_DATA__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__dav__WIDTH 1 -#define R_PAR1_STATUS_DATA__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR1_STATUS_DATA__data__BITNR 0 -#define R_PAR1_STATUS_DATA__data__WIDTH 8 - -#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__mode__WIDTH 3 -#define R_PAR1_STATUS__mode__manual 0 -#define R_PAR1_STATUS__mode__centronics 1 -#define R_PAR1_STATUS__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__nibble 3 -#define R_PAR1_STATUS__mode__byte 4 -#define R_PAR1_STATUS__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__off 7 -#define R_PAR1_STATUS__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__epp_rd 0 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__perr__WIDTH 1 -#define R_PAR1_STATUS__perr__active 1 -#define R_PAR1_STATUS__perr__inactive 0 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__ack__WIDTH 1 -#define R_PAR1_STATUS__ack__active 0 -#define R_PAR1_STATUS__ack__inactive 1 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__busy__WIDTH 1 -#define R_PAR1_STATUS__busy__active 1 -#define R_PAR1_STATUS__busy__inactive 0 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__fault__WIDTH 1 -#define R_PAR1_STATUS__fault__active 0 -#define R_PAR1_STATUS__fault__inactive 1 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__sel__WIDTH 1 -#define R_PAR1_STATUS__sel__active 1 -#define R_PAR1_STATUS__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__ext_mode__WIDTH 1 -#define R_PAR1_STATUS__ext_mode__enable 1 -#define R_PAR1_STATUS__ext_mode__disable 0 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS__tr_rdy__ready 1 -#define R_PAR1_STATUS__tr_rdy__busy 0 -#define R_PAR1_STATUS__dav__BITNR 0 -#define R_PAR1_STATUS__dav__WIDTH 1 -#define R_PAR1_STATUS__dav__data 1 -#define R_PAR1_STATUS__dav__nodata 0 - -#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__ioe__WIDTH 1 -#define R_PAR1_CONFIG__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iseli__WIDTH 1 -#define R_PAR1_CONFIG__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__iautofd__WIDTH 1 -#define R_PAR1_CONFIG__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__istrb__WIDTH 1 -#define R_PAR1_CONFIG__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iinit__WIDTH 1 -#define R_PAR1_CONFIG__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iperr__WIDTH 1 -#define R_PAR1_CONFIG__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__iack__WIDTH 1 -#define R_PAR1_CONFIG__iack__inv 1 -#define R_PAR1_CONFIG__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ibusy__WIDTH 1 -#define R_PAR1_CONFIG__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__ifault__WIDTH 1 -#define R_PAR1_CONFIG__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__isel__WIDTH 1 -#define R_PAR1_CONFIG__isel__inv 1 -#define R_PAR1_CONFIG__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__ext_mode__WIDTH 1 -#define R_PAR1_CONFIG__ext_mode__enable 1 -#define R_PAR1_CONFIG__ext_mode__disable 0 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__dma__WIDTH 1 -#define R_PAR1_CONFIG__dma__enable 1 -#define R_PAR1_CONFIG__dma__disable 0 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_in__WIDTH 1 -#define R_PAR1_CONFIG__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__rle_out__WIDTH 1 -#define R_PAR1_CONFIG__rle_out__enable 1 -#define R_PAR1_CONFIG__rle_out__disable 0 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__enable__WIDTH 1 -#define R_PAR1_CONFIG__enable__on 1 -#define R_PAR1_CONFIG__enable__reset 0 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__force__WIDTH 1 -#define R_PAR1_CONFIG__force__on 1 -#define R_PAR1_CONFIG__force__off 0 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__ign_ack__WIDTH 1 -#define R_PAR1_CONFIG__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__oe_ack__WIDTH 1 -#define R_PAR1_CONFIG__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__mode__BITNR 0 -#define R_PAR1_CONFIG__mode__WIDTH 3 -#define R_PAR1_CONFIG__mode__manual 0 -#define R_PAR1_CONFIG__mode__centronics 1 -#define R_PAR1_CONFIG__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__nibble 3 -#define R_PAR1_CONFIG__mode__byte 4 -#define R_PAR1_CONFIG__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__off 7 -#define R_PAR1_CONFIG__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__epp_rd 0 - -#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__fine_hold__WIDTH 3 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__hold__WIDTH 5 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__fine_strb__WIDTH 3 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__strobe__WIDTH 5 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__fine_setup__WIDTH 3 -#define R_PAR1_DELAY__setup__BITNR 0 -#define R_PAR1_DELAY__setup__WIDTH 5 - -/* -!* ATA interface registers -!*/ - -#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__sel__WIDTH 2 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs1__WIDTH 1 -#define R_ATA_CTRL_DATA__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__cs0__WIDTH 1 -#define R_ATA_CTRL_DATA__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__inactive 0 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__addr__WIDTH 3 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__rw__WIDTH 1 -#define R_ATA_CTRL_DATA__rw__read 1 -#define R_ATA_CTRL_DATA__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 -#define R_ATA_CTRL_DATA__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__handsh__WIDTH 1 -#define R_ATA_CTRL_DATA__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__multi__WIDTH 1 -#define R_ATA_CTRL_DATA__multi__on 1 -#define R_ATA_CTRL_DATA__multi__off 0 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 -#define R_ATA_CTRL_DATA__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__word 0 -#define R_ATA_CTRL_DATA__data__BITNR 0 -#define R_ATA_CTRL_DATA__data__WIDTH 16 - -#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__busy__WIDTH 1 -#define R_ATA_STATUS_DATA__busy__yes 1 -#define R_ATA_STATUS_DATA__busy__no 0 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_ATA_STATUS_DATA__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__dav__WIDTH 1 -#define R_ATA_STATUS_DATA__dav__data 1 -#define R_ATA_STATUS_DATA__dav__nodata 0 -#define R_ATA_STATUS_DATA__data__BITNR 0 -#define R_ATA_STATUS_DATA__data__WIDTH 16 - -#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__enable__WIDTH 1 -#define R_ATA_CONFIG__enable__on 1 -#define R_ATA_CONFIG__enable__off 0 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_strobe__WIDTH 5 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__dma_hold__WIDTH 5 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_setup__WIDTH 5 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_strobe__WIDTH 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 -#define R_ATA_CONFIG__pio_hold__WIDTH 5 - -#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__count__BITNR 0 -#define R_ATA_TRANSFER_CNT__count__WIDTH 17 - -/* -!* SCSI registers -!*/ - -#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__id_type__WIDTH 1 -#define R_SCSI0_CTRL__id_type__software 1 -#define R_SCSI0_CTRL__id_type__hardware 0 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__synch_per__WIDTH 8 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__rst__WIDTH 1 -#define R_SCSI0_CTRL__rst__yes 1 -#define R_SCSI0_CTRL__rst__no 0 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__atn__WIDTH 1 -#define R_SCSI0_CTRL__atn__yes 1 -#define R_SCSI0_CTRL__atn__no 0 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__my_id__WIDTH 4 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__target_id__WIDTH 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__fast_20__WIDTH 1 -#define R_SCSI0_CTRL__fast_20__yes 1 -#define R_SCSI0_CTRL__fast_20__no 0 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__bus_width__WIDTH 1 -#define R_SCSI0_CTRL__bus_width__wide 1 -#define R_SCSI0_CTRL__bus_width__narrow 0 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__synch__WIDTH 1 -#define R_SCSI0_CTRL__synch__synch 1 -#define R_SCSI0_CTRL__synch__asynch 0 -#define R_SCSI0_CTRL__enable__BITNR 0 -#define R_SCSI0_CTRL__enable__WIDTH 1 -#define R_SCSI0_CTRL__enable__on 1 -#define R_SCSI0_CTRL__enable__off 0 - -#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI0_CMD_DATA__parity_in__on 0 -#define R_SCSI0_CMD_DATA__parity_in__off 1 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__skip__WIDTH 1 -#define R_SCSI0_CMD_DATA__skip__on 1 -#define R_SCSI0_CMD_DATA__skip__off 0 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI0_CMD_DATA__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__command__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__resel_stat 5 -#define R_SCSI0_CMD_DATA__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__man_rat 13 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 -#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA__data_out__BITNR 0 -#define R_SCSI0_DATA__data_out__WIDTH 16 - -#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD__command__BITNR 0 -#define R_SCSI0_CMD__command__WIDTH 4 -#define R_SCSI0_CMD__command__full_din_1 0 -#define R_SCSI0_CMD__command__full_dout_1 1 -#define R_SCSI0_CMD__command__full_stat_1 2 -#define R_SCSI0_CMD__command__resel_din 3 -#define R_SCSI0_CMD__command__resel_dout 4 -#define R_SCSI0_CMD__command__resel_stat 5 -#define R_SCSI0_CMD__command__arb_only 6 -#define R_SCSI0_CMD__command__full_din_3 8 -#define R_SCSI0_CMD__command__full_dout_3 9 -#define R_SCSI0_CMD__command__full_stat_3 10 -#define R_SCSI0_CMD__command__man_data_in 11 -#define R_SCSI0_CMD__command__man_data_out 12 -#define R_SCSI0_CMD__command__man_rat 13 - -#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__skip__on 1 -#define R_SCSI0_STATUS_CTRL__skip__off 0 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__tst_resel__WIDTH 1 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__parity_error__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__bus_reset__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__yes 1 -#define R_SCSI0_STATUS__bus_reset__no 0 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel_target__WIDTH 4 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__resel__WIDTH 1 -#define R_SCSI0_STATUS__resel__yes 1 -#define R_SCSI0_STATUS__resel__no 0 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__curr_phase__WIDTH 3 -#define R_SCSI0_STATUS__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__valid_status__WIDTH 1 -#define R_SCSI0_STATUS__valid_status__yes 1 -#define R_SCSI0_STATUS__valid_status__no 0 -#define R_SCSI0_STATUS__seq_status__BITNR 0 -#define R_SCSI0_STATUS__seq_status__WIDTH 5 -#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__data_in__BITNR 0 -#define R_SCSI0_DATA_IN__data_in__WIDTH 16 - -#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__id_type__WIDTH 1 -#define R_SCSI1_CTRL__id_type__software 1 -#define R_SCSI1_CTRL__id_type__hardware 0 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__synch_per__WIDTH 8 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__rst__WIDTH 1 -#define R_SCSI1_CTRL__rst__yes 1 -#define R_SCSI1_CTRL__rst__no 0 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__atn__WIDTH 1 -#define R_SCSI1_CTRL__atn__yes 1 -#define R_SCSI1_CTRL__atn__no 0 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__my_id__WIDTH 4 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__target_id__WIDTH 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__fast_20__WIDTH 1 -#define R_SCSI1_CTRL__fast_20__yes 1 -#define R_SCSI1_CTRL__fast_20__no 0 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__bus_width__WIDTH 1 -#define R_SCSI1_CTRL__bus_width__wide 1 -#define R_SCSI1_CTRL__bus_width__narrow 0 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__synch__WIDTH 1 -#define R_SCSI1_CTRL__synch__synch 1 -#define R_SCSI1_CTRL__synch__asynch 0 -#define R_SCSI1_CTRL__enable__BITNR 0 -#define R_SCSI1_CTRL__enable__WIDTH 1 -#define R_SCSI1_CTRL__enable__on 1 -#define R_SCSI1_CTRL__enable__off 0 - -#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI1_CMD_DATA__parity_in__on 0 -#define R_SCSI1_CMD_DATA__parity_in__off 1 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__skip__WIDTH 1 -#define R_SCSI1_CMD_DATA__skip__on 1 -#define R_SCSI1_CMD_DATA__skip__off 0 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI1_CMD_DATA__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__command__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__resel_stat 5 -#define R_SCSI1_CMD_DATA__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__man_rat 13 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 -#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA__data_out__BITNR 0 -#define R_SCSI1_DATA__data_out__WIDTH 16 - -#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD__command__BITNR 0 -#define R_SCSI1_CMD__command__WIDTH 4 -#define R_SCSI1_CMD__command__full_din_1 0 -#define R_SCSI1_CMD__command__full_dout_1 1 -#define R_SCSI1_CMD__command__full_stat_1 2 -#define R_SCSI1_CMD__command__resel_din 3 -#define R_SCSI1_CMD__command__resel_dout 4 -#define R_SCSI1_CMD__command__resel_stat 5 -#define R_SCSI1_CMD__command__arb_only 6 -#define R_SCSI1_CMD__command__full_din_3 8 -#define R_SCSI1_CMD__command__full_dout_3 9 -#define R_SCSI1_CMD__command__full_stat_3 10 -#define R_SCSI1_CMD__command__man_data_in 11 -#define R_SCSI1_CMD__command__man_data_out 12 -#define R_SCSI1_CMD__command__man_rat 13 - -#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__skip__on 1 -#define R_SCSI1_STATUS_CTRL__skip__off 0 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__tst_resel__WIDTH 1 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__parity_error__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__bus_reset__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__yes 1 -#define R_SCSI1_STATUS__bus_reset__no 0 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel_target__WIDTH 4 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__resel__WIDTH 1 -#define R_SCSI1_STATUS__resel__yes 1 -#define R_SCSI1_STATUS__resel__no 0 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__curr_phase__WIDTH 3 -#define R_SCSI1_STATUS__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__valid_status__WIDTH 1 -#define R_SCSI1_STATUS__valid_status__yes 1 -#define R_SCSI1_STATUS__valid_status__no 0 -#define R_SCSI1_STATUS__seq_status__BITNR 0 -#define R_SCSI1_STATUS__seq_status__WIDTH 5 -#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__data_in__BITNR 0 -#define R_SCSI1_DATA_IN__data_in__WIDTH 16 - -/* -!* Interrupt mask and status registers -!*/ - -#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_RD__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_RD__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_RD__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__deferred__WIDTH 1 -#define R_IRQ_MASK0_RD__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__late_col__WIDTH 1 -#define R_IRQ_MASK0_RD__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_RD__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__single_col__WIDTH 1 -#define R_IRQ_MASK0_RD__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__congestion__WIDTH 1 -#define R_IRQ_MASK0_RD__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__oversize__WIDTH 1 -#define R_IRQ_MASK0_RD__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_RD__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 -#define R_IRQ_MASK0_RD__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__overrun__WIDTH 1 -#define R_IRQ_MASK0_RD__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__underrun__WIDTH 1 -#define R_IRQ_MASK0_RD__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_RD__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__mdio__WIDTH 1 -#define R_IRQ_MASK0_RD__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__mio__WIDTH 1 -#define R_IRQ_MASK0_RD__mio__active 1 -#define R_IRQ_MASK0_RD__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 -#define R_IRQ_MASK0_RD__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer1__WIDTH 1 -#define R_IRQ_MASK0_RD__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 -#define R_IRQ_MASK0_RD__timer0__WIDTH 1 -#define R_IRQ_MASK0_RD__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__inactive 0 - -#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 -#define R_IRQ_MASK0_CLR__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 -#define R_IRQ_MASK0_CLR__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 -#define R_IRQ_MASK0_CLR__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 -#define R_IRQ_MASK0_CLR__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 -#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__nop 0 - -#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__nmi_pin__WIDTH 1 -#define R_IRQ_READ0__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 -#define R_IRQ_READ0__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__sqe_test_error__WIDTH 1 -#define R_IRQ_READ0__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__carrier_loss__WIDTH 1 -#define R_IRQ_READ0__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__deferred__WIDTH 1 -#define R_IRQ_READ0__deferred__active 1 -#define R_IRQ_READ0__deferred__inactive 0 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__late_col__WIDTH 1 -#define R_IRQ_READ0__late_col__active 1 -#define R_IRQ_READ0__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__multiple_col__WIDTH 1 -#define R_IRQ_READ0__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__single_col__WIDTH 1 -#define R_IRQ_READ0__single_col__active 1 -#define R_IRQ_READ0__single_col__inactive 0 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__congestion__WIDTH 1 -#define R_IRQ_READ0__congestion__active 1 -#define R_IRQ_READ0__congestion__inactive 0 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__oversize__WIDTH 1 -#define R_IRQ_READ0__oversize__active 1 -#define R_IRQ_READ0__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__alignment_error__WIDTH 1 -#define R_IRQ_READ0__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__crc_error__WIDTH 1 -#define R_IRQ_READ0__crc_error__active 1 -#define R_IRQ_READ0__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__overrun__WIDTH 1 -#define R_IRQ_READ0__overrun__active 1 -#define R_IRQ_READ0__overrun__inactive 0 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__underrun__WIDTH 1 -#define R_IRQ_READ0__underrun__active 1 -#define R_IRQ_READ0__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__excessive_col__WIDTH 1 -#define R_IRQ_READ0__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__mdio__WIDTH 1 -#define R_IRQ_READ0__mdio__active 1 -#define R_IRQ_READ0__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq3__WIDTH 1 -#define R_IRQ_READ0__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq2__WIDTH 1 -#define R_IRQ_READ0__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq1__WIDTH 1 -#define R_IRQ_READ0__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__ata_drq0__WIDTH 1 -#define R_IRQ_READ0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_READ0__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__ata_irq3__WIDTH 1 -#define R_IRQ_READ0__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__par0_peri__WIDTH 1 -#define R_IRQ_READ0__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__ata_irq2__WIDTH 1 -#define R_IRQ_READ0__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__par0_data__WIDTH 1 -#define R_IRQ_READ0__par0_data__active 1 -#define R_IRQ_READ0__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__ata_irq1__WIDTH 1 -#define R_IRQ_READ0__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__par0_ready__WIDTH 1 -#define R_IRQ_READ0__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__ata_irq0__WIDTH 1 -#define R_IRQ_READ0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__mio__WIDTH 1 -#define R_IRQ_READ0__mio__active 1 -#define R_IRQ_READ0__mio__inactive 0 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__scsi0__WIDTH 1 -#define R_IRQ_READ0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__ata_dmaend__WIDTH 1 -#define R_IRQ_READ0__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma1__WIDTH 1 -#define R_IRQ_READ0__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__ext_dma0__WIDTH 1 -#define R_IRQ_READ0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer1__WIDTH 1 -#define R_IRQ_READ0__timer1__active 1 -#define R_IRQ_READ0__timer1__inactive 0 -#define R_IRQ_READ0__timer0__BITNR 0 -#define R_IRQ_READ0__timer0__WIDTH 1 -#define R_IRQ_READ0__timer0__active 1 -#define R_IRQ_READ0__timer0__inactive 0 - -#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_SET__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_SET__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_SET__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__deferred__WIDTH 1 -#define R_IRQ_MASK0_SET__deferred__set 1 -#define R_IRQ_MASK0_SET__deferred__nop 0 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__late_col__WIDTH 1 -#define R_IRQ_MASK0_SET__late_col__set 1 -#define R_IRQ_MASK0_SET__late_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_SET__multiple_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__single_col__WIDTH 1 -#define R_IRQ_MASK0_SET__single_col__set 1 -#define R_IRQ_MASK0_SET__single_col__nop 0 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__congestion__WIDTH 1 -#define R_IRQ_MASK0_SET__congestion__set 1 -#define R_IRQ_MASK0_SET__congestion__nop 0 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__oversize__WIDTH 1 -#define R_IRQ_MASK0_SET__oversize__set 1 -#define R_IRQ_MASK0_SET__oversize__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_SET__alignment_error__set 1 -#define R_IRQ_MASK0_SET__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 -#define R_IRQ_MASK0_SET__crc_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__nop 0 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__overrun__WIDTH 1 -#define R_IRQ_MASK0_SET__overrun__set 1 -#define R_IRQ_MASK0_SET__overrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__underrun__WIDTH 1 -#define R_IRQ_MASK0_SET__underrun__set 1 -#define R_IRQ_MASK0_SET__underrun__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_SET__excessive_col__set 1 -#define R_IRQ_MASK0_SET__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__mdio__WIDTH 1 -#define R_IRQ_MASK0_SET__mdio__set 1 -#define R_IRQ_MASK0_SET__mdio__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_peri__set 1 -#define R_IRQ_MASK0_SET__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_data__set 1 -#define R_IRQ_MASK0_SET__par0_data__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ready__set 1 -#define R_IRQ_MASK0_SET__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__mio__WIDTH 1 -#define R_IRQ_MASK0_SET__mio__set 1 -#define R_IRQ_MASK0_SET__mio__nop 0 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 -#define R_IRQ_MASK0_SET__scsi0__set 1 -#define R_IRQ_MASK0_SET__scsi0__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer1__WIDTH 1 -#define R_IRQ_MASK0_SET__timer1__set 1 -#define R_IRQ_MASK0_SET__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 -#define R_IRQ_MASK0_SET__timer0__WIDTH 1 -#define R_IRQ_MASK0_SET__timer0__set 1 -#define R_IRQ_MASK0_SET__timer0__nop 0 - -#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 -#define R_IRQ_MASK1_RD__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa7__WIDTH 1 -#define R_IRQ_MASK1_RD__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa6__WIDTH 1 -#define R_IRQ_MASK1_RD__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa5__WIDTH 1 -#define R_IRQ_MASK1_RD__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa4__WIDTH 1 -#define R_IRQ_MASK1_RD__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa3__WIDTH 1 -#define R_IRQ_MASK1_RD__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa2__WIDTH 1 -#define R_IRQ_MASK1_RD__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa1__WIDTH 1 -#define R_IRQ_MASK1_RD__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 -#define R_IRQ_MASK1_RD__pa0__WIDTH 1 -#define R_IRQ_MASK1_RD__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__inactive 0 - -#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 -#define R_IRQ_MASK1_CLR__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 -#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__nop 0 - -#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int7__WIDTH 1 -#define R_IRQ_READ1__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int6__WIDTH 1 -#define R_IRQ_READ1__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int5__WIDTH 1 -#define R_IRQ_READ1__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int4__WIDTH 1 -#define R_IRQ_READ1__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int3__WIDTH 1 -#define R_IRQ_READ1__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int2__WIDTH 1 -#define R_IRQ_READ1__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int1__WIDTH 1 -#define R_IRQ_READ1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__sw_int0__WIDTH 1 -#define R_IRQ_READ1__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_READ1__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_peri__WIDTH 1 -#define R_IRQ_READ1__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_data__WIDTH 1 -#define R_IRQ_READ1__par1_data__active 1 -#define R_IRQ_READ1__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__par1_ready__WIDTH 1 -#define R_IRQ_READ1__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__scsi1__WIDTH 1 -#define R_IRQ_READ1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_ready__WIDTH 1 -#define R_IRQ_READ1__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser3_data__WIDTH 1 -#define R_IRQ_READ1__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_ready__WIDTH 1 -#define R_IRQ_READ1__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser2_data__WIDTH 1 -#define R_IRQ_READ1__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_ready__WIDTH 1 -#define R_IRQ_READ1__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser1_data__WIDTH 1 -#define R_IRQ_READ1__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_ready__WIDTH 1 -#define R_IRQ_READ1__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__ser0_data__WIDTH 1 -#define R_IRQ_READ1__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa7__WIDTH 1 -#define R_IRQ_READ1__pa7__active 1 -#define R_IRQ_READ1__pa7__inactive 0 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa6__WIDTH 1 -#define R_IRQ_READ1__pa6__active 1 -#define R_IRQ_READ1__pa6__inactive 0 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa5__WIDTH 1 -#define R_IRQ_READ1__pa5__active 1 -#define R_IRQ_READ1__pa5__inactive 0 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa4__WIDTH 1 -#define R_IRQ_READ1__pa4__active 1 -#define R_IRQ_READ1__pa4__inactive 0 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa3__WIDTH 1 -#define R_IRQ_READ1__pa3__active 1 -#define R_IRQ_READ1__pa3__inactive 0 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa2__WIDTH 1 -#define R_IRQ_READ1__pa2__active 1 -#define R_IRQ_READ1__pa2__inactive 0 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa1__WIDTH 1 -#define R_IRQ_READ1__pa1__active 1 -#define R_IRQ_READ1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__BITNR 0 -#define R_IRQ_READ1__pa0__WIDTH 1 -#define R_IRQ_READ1__pa0__active 1 -#define R_IRQ_READ1__pa0__inactive 0 - -#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int0__set 1 -#define R_IRQ_MASK1_SET__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ready__set 1 -#define R_IRQ_MASK1_SET__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 -#define R_IRQ_MASK1_SET__scsi1__set 1 -#define R_IRQ_MASK1_SET__scsi1__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_data__set 1 -#define R_IRQ_MASK1_SET__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa7__WIDTH 1 -#define R_IRQ_MASK1_SET__pa7__set 1 -#define R_IRQ_MASK1_SET__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa6__WIDTH 1 -#define R_IRQ_MASK1_SET__pa6__set 1 -#define R_IRQ_MASK1_SET__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa5__WIDTH 1 -#define R_IRQ_MASK1_SET__pa5__set 1 -#define R_IRQ_MASK1_SET__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa4__WIDTH 1 -#define R_IRQ_MASK1_SET__pa4__set 1 -#define R_IRQ_MASK1_SET__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa3__WIDTH 1 -#define R_IRQ_MASK1_SET__pa3__set 1 -#define R_IRQ_MASK1_SET__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa2__WIDTH 1 -#define R_IRQ_MASK1_SET__pa2__set 1 -#define R_IRQ_MASK1_SET__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa1__WIDTH 1 -#define R_IRQ_MASK1_SET__pa1__set 1 -#define R_IRQ_MASK1_SET__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 -#define R_IRQ_MASK1_SET__pa0__WIDTH 1 -#define R_IRQ_MASK1_SET__pa0__set 1 -#define R_IRQ_MASK1_SET__pa0__nop 0 - -#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 - -#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_eop__WIDTH 1 -#define R_IRQ_READ2__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma9_descr__WIDTH 1 -#define R_IRQ_READ2__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_eop__WIDTH 1 -#define R_IRQ_READ2__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma8_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_eop__WIDTH 1 -#define R_IRQ_READ2__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma7_descr__WIDTH 1 -#define R_IRQ_READ2__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_eop__WIDTH 1 -#define R_IRQ_READ2__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma6_descr__WIDTH 1 -#define R_IRQ_READ2__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_eop__WIDTH 1 -#define R_IRQ_READ2__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma5_descr__WIDTH 1 -#define R_IRQ_READ2__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_eop__WIDTH 1 -#define R_IRQ_READ2__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma4_descr__WIDTH 1 -#define R_IRQ_READ2__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_eop__WIDTH 1 -#define R_IRQ_READ2__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma3_descr__WIDTH 1 -#define R_IRQ_READ2__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_eop__WIDTH 1 -#define R_IRQ_READ2__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma2_descr__WIDTH 1 -#define R_IRQ_READ2__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_eop__WIDTH 1 -#define R_IRQ_READ2__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma1_descr__WIDTH 1 -#define R_IRQ_READ2__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_eop__WIDTH 1 -#define R_IRQ_READ2__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__BITNR 0 -#define R_IRQ_READ2__dma0_descr__WIDTH 1 -#define R_IRQ_READ2__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__nop 0 - -#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__usb__WIDTH 1 -#define R_VECT_MASK_RD__usb__active 1 -#define R_VECT_MASK_RD__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma9__WIDTH 1 -#define R_VECT_MASK_RD__dma9__active 1 -#define R_VECT_MASK_RD__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma8__WIDTH 1 -#define R_VECT_MASK_RD__dma8__active 1 -#define R_VECT_MASK_RD__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma7__WIDTH 1 -#define R_VECT_MASK_RD__dma7__active 1 -#define R_VECT_MASK_RD__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma6__WIDTH 1 -#define R_VECT_MASK_RD__dma6__active 1 -#define R_VECT_MASK_RD__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma5__WIDTH 1 -#define R_VECT_MASK_RD__dma5__active 1 -#define R_VECT_MASK_RD__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma4__WIDTH 1 -#define R_VECT_MASK_RD__dma4__active 1 -#define R_VECT_MASK_RD__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma3__WIDTH 1 -#define R_VECT_MASK_RD__dma3__active 1 -#define R_VECT_MASK_RD__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma2__WIDTH 1 -#define R_VECT_MASK_RD__dma2__active 1 -#define R_VECT_MASK_RD__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma1__WIDTH 1 -#define R_VECT_MASK_RD__dma1__active 1 -#define R_VECT_MASK_RD__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__dma0__WIDTH 1 -#define R_VECT_MASK_RD__dma0__active 1 -#define R_VECT_MASK_RD__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__pa__WIDTH 1 -#define R_VECT_MASK_RD__pa__active 1 -#define R_VECT_MASK_RD__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 -#define R_VECT_MASK_RD__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__sw__WIDTH 1 -#define R_VECT_MASK_RD__sw__active 1 -#define R_VECT_MASK_RD__sw__inactive 0 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__serial__WIDTH 1 -#define R_VECT_MASK_RD__serial__active 1 -#define R_VECT_MASK_RD__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__snmp__WIDTH 1 -#define R_VECT_MASK_RD__snmp__active 1 -#define R_VECT_MASK_RD__snmp__inactive 0 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__network__WIDTH 1 -#define R_VECT_MASK_RD__network__active 1 -#define R_VECT_MASK_RD__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__scsi1__WIDTH 1 -#define R_VECT_MASK_RD__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__par1__WIDTH 1 -#define R_VECT_MASK_RD__par1__active 1 -#define R_VECT_MASK_RD__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__scsi0__WIDTH 1 -#define R_VECT_MASK_RD__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__par0__WIDTH 1 -#define R_VECT_MASK_RD__par0__active 1 -#define R_VECT_MASK_RD__par0__inactive 0 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__ata__WIDTH 1 -#define R_VECT_MASK_RD__ata__active 1 -#define R_VECT_MASK_RD__ata__inactive 0 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__mio__WIDTH 1 -#define R_VECT_MASK_RD__mio__active 1 -#define R_VECT_MASK_RD__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer1__WIDTH 1 -#define R_VECT_MASK_RD__timer1__active 1 -#define R_VECT_MASK_RD__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__timer0__WIDTH 1 -#define R_VECT_MASK_RD__timer0__active 1 -#define R_VECT_MASK_RD__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__nmi__WIDTH 1 -#define R_VECT_MASK_RD__nmi__active 1 -#define R_VECT_MASK_RD__nmi__inactive 0 -#define R_VECT_MASK_RD__some__BITNR 0 -#define R_VECT_MASK_RD__some__WIDTH 1 -#define R_VECT_MASK_RD__some__active 1 -#define R_VECT_MASK_RD__some__inactive 0 - -#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__usb__WIDTH 1 -#define R_VECT_MASK_CLR__usb__clr 1 -#define R_VECT_MASK_CLR__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma9__WIDTH 1 -#define R_VECT_MASK_CLR__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma8__WIDTH 1 -#define R_VECT_MASK_CLR__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma7__WIDTH 1 -#define R_VECT_MASK_CLR__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma6__WIDTH 1 -#define R_VECT_MASK_CLR__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma5__WIDTH 1 -#define R_VECT_MASK_CLR__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma4__WIDTH 1 -#define R_VECT_MASK_CLR__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma3__WIDTH 1 -#define R_VECT_MASK_CLR__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma2__WIDTH 1 -#define R_VECT_MASK_CLR__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma1__WIDTH 1 -#define R_VECT_MASK_CLR__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__dma0__WIDTH 1 -#define R_VECT_MASK_CLR__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__pa__WIDTH 1 -#define R_VECT_MASK_CLR__pa__clr 1 -#define R_VECT_MASK_CLR__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 -#define R_VECT_MASK_CLR__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__sw__WIDTH 1 -#define R_VECT_MASK_CLR__sw__clr 1 -#define R_VECT_MASK_CLR__sw__nop 0 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__serial__WIDTH 1 -#define R_VECT_MASK_CLR__serial__clr 1 -#define R_VECT_MASK_CLR__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__snmp__WIDTH 1 -#define R_VECT_MASK_CLR__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__nop 0 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__network__WIDTH 1 -#define R_VECT_MASK_CLR__network__clr 1 -#define R_VECT_MASK_CLR__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__scsi1__WIDTH 1 -#define R_VECT_MASK_CLR__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__par1__WIDTH 1 -#define R_VECT_MASK_CLR__par1__clr 1 -#define R_VECT_MASK_CLR__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__scsi0__WIDTH 1 -#define R_VECT_MASK_CLR__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__par0__WIDTH 1 -#define R_VECT_MASK_CLR__par0__clr 1 -#define R_VECT_MASK_CLR__par0__nop 0 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__ata__WIDTH 1 -#define R_VECT_MASK_CLR__ata__clr 1 -#define R_VECT_MASK_CLR__ata__nop 0 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__mio__WIDTH 1 -#define R_VECT_MASK_CLR__mio__clr 1 -#define R_VECT_MASK_CLR__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer1__WIDTH 1 -#define R_VECT_MASK_CLR__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__timer0__WIDTH 1 -#define R_VECT_MASK_CLR__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__nmi__WIDTH 1 -#define R_VECT_MASK_CLR__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nop 0 -#define R_VECT_MASK_CLR__some__BITNR 0 -#define R_VECT_MASK_CLR__some__WIDTH 1 -#define R_VECT_MASK_CLR__some__clr 1 -#define R_VECT_MASK_CLR__some__nop 0 - -#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__usb__WIDTH 1 -#define R_VECT_READ__usb__active 1 -#define R_VECT_READ__usb__inactive 0 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma9__WIDTH 1 -#define R_VECT_READ__dma9__active 1 -#define R_VECT_READ__dma9__inactive 0 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma8__WIDTH 1 -#define R_VECT_READ__dma8__active 1 -#define R_VECT_READ__dma8__inactive 0 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma7__WIDTH 1 -#define R_VECT_READ__dma7__active 1 -#define R_VECT_READ__dma7__inactive 0 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma6__WIDTH 1 -#define R_VECT_READ__dma6__active 1 -#define R_VECT_READ__dma6__inactive 0 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma5__WIDTH 1 -#define R_VECT_READ__dma5__active 1 -#define R_VECT_READ__dma5__inactive 0 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma4__WIDTH 1 -#define R_VECT_READ__dma4__active 1 -#define R_VECT_READ__dma4__inactive 0 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma3__WIDTH 1 -#define R_VECT_READ__dma3__active 1 -#define R_VECT_READ__dma3__inactive 0 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma2__WIDTH 1 -#define R_VECT_READ__dma2__active 1 -#define R_VECT_READ__dma2__inactive 0 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma1__WIDTH 1 -#define R_VECT_READ__dma1__active 1 -#define R_VECT_READ__dma1__inactive 0 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__dma0__WIDTH 1 -#define R_VECT_READ__dma0__active 1 -#define R_VECT_READ__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma1__WIDTH 1 -#define R_VECT_READ__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__ext_dma0__WIDTH 1 -#define R_VECT_READ__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__inactive 0 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__pa__WIDTH 1 -#define R_VECT_READ__pa__active 1 -#define R_VECT_READ__pa__inactive 0 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__irq_intnr__WIDTH 1 -#define R_VECT_READ__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__inactive 0 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__sw__WIDTH 1 -#define R_VECT_READ__sw__active 1 -#define R_VECT_READ__sw__inactive 0 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__serial__WIDTH 1 -#define R_VECT_READ__serial__active 1 -#define R_VECT_READ__serial__inactive 0 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__snmp__WIDTH 1 -#define R_VECT_READ__snmp__active 1 -#define R_VECT_READ__snmp__inactive 0 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__network__WIDTH 1 -#define R_VECT_READ__network__active 1 -#define R_VECT_READ__network__inactive 0 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__scsi1__WIDTH 1 -#define R_VECT_READ__scsi1__active 1 -#define R_VECT_READ__scsi1__inactive 0 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__par1__WIDTH 1 -#define R_VECT_READ__par1__active 1 -#define R_VECT_READ__par1__inactive 0 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__scsi0__WIDTH 1 -#define R_VECT_READ__scsi0__active 1 -#define R_VECT_READ__scsi0__inactive 0 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__par0__WIDTH 1 -#define R_VECT_READ__par0__active 1 -#define R_VECT_READ__par0__inactive 0 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__ata__WIDTH 1 -#define R_VECT_READ__ata__active 1 -#define R_VECT_READ__ata__inactive 0 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__mio__WIDTH 1 -#define R_VECT_READ__mio__active 1 -#define R_VECT_READ__mio__inactive 0 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer1__WIDTH 1 -#define R_VECT_READ__timer1__active 1 -#define R_VECT_READ__timer1__inactive 0 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__timer0__WIDTH 1 -#define R_VECT_READ__timer0__active 1 -#define R_VECT_READ__timer0__inactive 0 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__nmi__WIDTH 1 -#define R_VECT_READ__nmi__active 1 -#define R_VECT_READ__nmi__inactive 0 -#define R_VECT_READ__some__BITNR 0 -#define R_VECT_READ__some__WIDTH 1 -#define R_VECT_READ__some__active 1 -#define R_VECT_READ__some__inactive 0 - -#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__usb__WIDTH 1 -#define R_VECT_MASK_SET__usb__set 1 -#define R_VECT_MASK_SET__usb__nop 0 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma9__WIDTH 1 -#define R_VECT_MASK_SET__dma9__set 1 -#define R_VECT_MASK_SET__dma9__nop 0 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma8__WIDTH 1 -#define R_VECT_MASK_SET__dma8__set 1 -#define R_VECT_MASK_SET__dma8__nop 0 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma7__WIDTH 1 -#define R_VECT_MASK_SET__dma7__set 1 -#define R_VECT_MASK_SET__dma7__nop 0 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma6__WIDTH 1 -#define R_VECT_MASK_SET__dma6__set 1 -#define R_VECT_MASK_SET__dma6__nop 0 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma5__WIDTH 1 -#define R_VECT_MASK_SET__dma5__set 1 -#define R_VECT_MASK_SET__dma5__nop 0 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma4__WIDTH 1 -#define R_VECT_MASK_SET__dma4__set 1 -#define R_VECT_MASK_SET__dma4__nop 0 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma3__WIDTH 1 -#define R_VECT_MASK_SET__dma3__set 1 -#define R_VECT_MASK_SET__dma3__nop 0 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma2__WIDTH 1 -#define R_VECT_MASK_SET__dma2__set 1 -#define R_VECT_MASK_SET__dma2__nop 0 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma1__WIDTH 1 -#define R_VECT_MASK_SET__dma1__set 1 -#define R_VECT_MASK_SET__dma1__nop 0 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__dma0__WIDTH 1 -#define R_VECT_MASK_SET__dma0__set 1 -#define R_VECT_MASK_SET__dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma0__set 1 -#define R_VECT_MASK_SET__ext_dma0__nop 0 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__pa__WIDTH 1 -#define R_VECT_MASK_SET__pa__set 1 -#define R_VECT_MASK_SET__pa__nop 0 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 -#define R_VECT_MASK_SET__irq_intnr__set 1 -#define R_VECT_MASK_SET__irq_intnr__nop 0 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__sw__WIDTH 1 -#define R_VECT_MASK_SET__sw__set 1 -#define R_VECT_MASK_SET__sw__nop 0 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__serial__WIDTH 1 -#define R_VECT_MASK_SET__serial__set 1 -#define R_VECT_MASK_SET__serial__nop 0 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__snmp__WIDTH 1 -#define R_VECT_MASK_SET__snmp__set 1 -#define R_VECT_MASK_SET__snmp__nop 0 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__network__WIDTH 1 -#define R_VECT_MASK_SET__network__set 1 -#define R_VECT_MASK_SET__network__nop 0 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__scsi1__WIDTH 1 -#define R_VECT_MASK_SET__scsi1__set 1 -#define R_VECT_MASK_SET__scsi1__nop 0 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__par1__WIDTH 1 -#define R_VECT_MASK_SET__par1__set 1 -#define R_VECT_MASK_SET__par1__nop 0 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__scsi0__WIDTH 1 -#define R_VECT_MASK_SET__scsi0__set 1 -#define R_VECT_MASK_SET__scsi0__nop 0 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__par0__WIDTH 1 -#define R_VECT_MASK_SET__par0__set 1 -#define R_VECT_MASK_SET__par0__nop 0 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__ata__WIDTH 1 -#define R_VECT_MASK_SET__ata__set 1 -#define R_VECT_MASK_SET__ata__nop 0 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__mio__WIDTH 1 -#define R_VECT_MASK_SET__mio__set 1 -#define R_VECT_MASK_SET__mio__nop 0 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer1__WIDTH 1 -#define R_VECT_MASK_SET__timer1__set 1 -#define R_VECT_MASK_SET__timer1__nop 0 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__timer0__WIDTH 1 -#define R_VECT_MASK_SET__timer0__set 1 -#define R_VECT_MASK_SET__timer0__nop 0 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__nmi__WIDTH 1 -#define R_VECT_MASK_SET__nmi__set 1 -#define R_VECT_MASK_SET__nmi__nop 0 -#define R_VECT_MASK_SET__some__BITNR 0 -#define R_VECT_MASK_SET__some__WIDTH 1 -#define R_VECT_MASK_SET__some__set 1 -#define R_VECT_MASK_SET__some__nop 0 - -/* -!* DMA registers -!*/ - -#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch9_eop__WIDTH 1 -#define R_SET_EOP__ch9_eop__set 1 -#define R_SET_EOP__ch9_eop__nop 0 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch7_eop__WIDTH 1 -#define R_SET_EOP__ch7_eop__set 1 -#define R_SET_EOP__ch7_eop__nop 0 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch5_eop__WIDTH 1 -#define R_SET_EOP__ch5_eop__set 1 -#define R_SET_EOP__ch5_eop__nop 0 -#define R_SET_EOP__ch3_eop__BITNR 0 -#define R_SET_EOP__ch3_eop__WIDTH 1 -#define R_SET_EOP__ch3_eop__set 1 -#define R_SET_EOP__ch3_eop__nop 0 - -#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__hw__WIDTH 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 -#define R_DMA_CH0_HWSW__sw__WIDTH 16 - -#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__descr__BITNR 0 -#define R_DMA_CH0_DESCR__descr__WIDTH 32 - -#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__next__BITNR 0 -#define R_DMA_CH0_NEXT__next__WIDTH 32 - -#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__buf__BITNR 0 -#define R_DMA_CH0_BUF__buf__WIDTH 32 - -#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__first__BITNR 0 -#define R_DMA_CH0_FIRST__first__WIDTH 32 - -#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__cmd__BITNR 0 -#define R_DMA_CH0_CMD__cmd__WIDTH 3 -#define R_DMA_CH0_CMD__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__start 1 -#define R_DMA_CH0_CMD__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__reset 4 - -#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__avail__BITNR 0 -#define R_DMA_CH0_STATUS__avail__WIDTH 7 - -#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__hw__WIDTH 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 -#define R_DMA_CH1_HWSW__sw__WIDTH 16 - -#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__descr__BITNR 0 -#define R_DMA_CH1_DESCR__descr__WIDTH 32 - -#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__next__BITNR 0 -#define R_DMA_CH1_NEXT__next__WIDTH 32 - -#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__buf__BITNR 0 -#define R_DMA_CH1_BUF__buf__WIDTH 32 - -#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__first__BITNR 0 -#define R_DMA_CH1_FIRST__first__WIDTH 32 - -#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__cmd__BITNR 0 -#define R_DMA_CH1_CMD__cmd__WIDTH 3 -#define R_DMA_CH1_CMD__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__start 1 -#define R_DMA_CH1_CMD__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__reset 4 - -#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__avail__BITNR 0 -#define R_DMA_CH1_STATUS__avail__WIDTH 7 - -#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__hw__WIDTH 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 -#define R_DMA_CH2_HWSW__sw__WIDTH 16 - -#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__descr__BITNR 0 -#define R_DMA_CH2_DESCR__descr__WIDTH 32 - -#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__next__BITNR 0 -#define R_DMA_CH2_NEXT__next__WIDTH 32 - -#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__buf__BITNR 0 -#define R_DMA_CH2_BUF__buf__WIDTH 32 - -#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__first__BITNR 0 -#define R_DMA_CH2_FIRST__first__WIDTH 32 - -#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__cmd__BITNR 0 -#define R_DMA_CH2_CMD__cmd__WIDTH 3 -#define R_DMA_CH2_CMD__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__start 1 -#define R_DMA_CH2_CMD__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__reset 4 - -#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__avail__BITNR 0 -#define R_DMA_CH2_STATUS__avail__WIDTH 7 - -#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__hw__WIDTH 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 -#define R_DMA_CH3_HWSW__sw__WIDTH 16 - -#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__descr__BITNR 0 -#define R_DMA_CH3_DESCR__descr__WIDTH 32 - -#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__next__BITNR 0 -#define R_DMA_CH3_NEXT__next__WIDTH 32 - -#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__buf__BITNR 0 -#define R_DMA_CH3_BUF__buf__WIDTH 32 - -#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__first__BITNR 0 -#define R_DMA_CH3_FIRST__first__WIDTH 32 - -#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__cmd__BITNR 0 -#define R_DMA_CH3_CMD__cmd__WIDTH 3 -#define R_DMA_CH3_CMD__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__start 1 -#define R_DMA_CH3_CMD__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__reset 4 - -#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__avail__BITNR 0 -#define R_DMA_CH3_STATUS__avail__WIDTH 7 - -#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__hw__WIDTH 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 -#define R_DMA_CH4_HWSW__sw__WIDTH 16 - -#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__descr__BITNR 0 -#define R_DMA_CH4_DESCR__descr__WIDTH 32 - -#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__next__BITNR 0 -#define R_DMA_CH4_NEXT__next__WIDTH 32 - -#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__buf__BITNR 0 -#define R_DMA_CH4_BUF__buf__WIDTH 32 - -#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__first__BITNR 0 -#define R_DMA_CH4_FIRST__first__WIDTH 32 - -#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__cmd__BITNR 0 -#define R_DMA_CH4_CMD__cmd__WIDTH 3 -#define R_DMA_CH4_CMD__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__start 1 -#define R_DMA_CH4_CMD__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__reset 4 - -#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__avail__BITNR 0 -#define R_DMA_CH4_STATUS__avail__WIDTH 7 - -#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__hw__WIDTH 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 -#define R_DMA_CH5_HWSW__sw__WIDTH 16 - -#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__descr__BITNR 0 -#define R_DMA_CH5_DESCR__descr__WIDTH 32 - -#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__next__BITNR 0 -#define R_DMA_CH5_NEXT__next__WIDTH 32 - -#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__buf__BITNR 0 -#define R_DMA_CH5_BUF__buf__WIDTH 32 - -#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__first__BITNR 0 -#define R_DMA_CH5_FIRST__first__WIDTH 32 - -#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__cmd__BITNR 0 -#define R_DMA_CH5_CMD__cmd__WIDTH 3 -#define R_DMA_CH5_CMD__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__start 1 -#define R_DMA_CH5_CMD__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__reset 4 - -#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__avail__BITNR 0 -#define R_DMA_CH5_STATUS__avail__WIDTH 7 - -#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__hw__WIDTH 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 -#define R_DMA_CH6_HWSW__sw__WIDTH 16 - -#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__descr__BITNR 0 -#define R_DMA_CH6_DESCR__descr__WIDTH 32 - -#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__next__BITNR 0 -#define R_DMA_CH6_NEXT__next__WIDTH 32 - -#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__buf__BITNR 0 -#define R_DMA_CH6_BUF__buf__WIDTH 32 - -#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__first__BITNR 0 -#define R_DMA_CH6_FIRST__first__WIDTH 32 - -#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__cmd__BITNR 0 -#define R_DMA_CH6_CMD__cmd__WIDTH 3 -#define R_DMA_CH6_CMD__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__start 1 -#define R_DMA_CH6_CMD__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__reset 4 - -#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__avail__BITNR 0 -#define R_DMA_CH6_STATUS__avail__WIDTH 7 - -#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__hw__WIDTH 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 -#define R_DMA_CH7_HWSW__sw__WIDTH 16 - -#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__descr__BITNR 0 -#define R_DMA_CH7_DESCR__descr__WIDTH 32 - -#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__next__BITNR 0 -#define R_DMA_CH7_NEXT__next__WIDTH 32 - -#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__buf__BITNR 0 -#define R_DMA_CH7_BUF__buf__WIDTH 32 - -#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__first__BITNR 0 -#define R_DMA_CH7_FIRST__first__WIDTH 32 - -#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__cmd__BITNR 0 -#define R_DMA_CH7_CMD__cmd__WIDTH 3 -#define R_DMA_CH7_CMD__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__start 1 -#define R_DMA_CH7_CMD__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__reset 4 - -#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__avail__BITNR 0 -#define R_DMA_CH7_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__hw__WIDTH 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 -#define R_DMA_CH8_HWSW__sw__WIDTH 16 - -#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__descr__BITNR 0 -#define R_DMA_CH8_DESCR__descr__WIDTH 32 - -#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__next__BITNR 0 -#define R_DMA_CH8_NEXT__next__WIDTH 32 - -#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__buf__BITNR 0 -#define R_DMA_CH8_BUF__buf__WIDTH 32 - -#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__first__BITNR 0 -#define R_DMA_CH8_FIRST__first__WIDTH 32 - -#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__cmd__BITNR 0 -#define R_DMA_CH8_CMD__cmd__WIDTH 3 -#define R_DMA_CH8_CMD__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__start 1 -#define R_DMA_CH8_CMD__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__reset 4 - -#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__avail__BITNR 0 -#define R_DMA_CH8_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__sub__BITNR 0 -#define R_DMA_CH8_SUB__sub__WIDTH 32 - -#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__nep__BITNR 0 -#define R_DMA_CH8_NEP__nep__WIDTH 32 - -#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB0_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB1_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB2_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB3_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__hw__WIDTH 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 -#define R_DMA_CH9_HWSW__sw__WIDTH 16 - -#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__descr__BITNR 0 -#define R_DMA_CH9_DESCR__descr__WIDTH 32 - -#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__next__BITNR 0 -#define R_DMA_CH9_NEXT__next__WIDTH 32 - -#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__buf__BITNR 0 -#define R_DMA_CH9_BUF__buf__WIDTH 32 - -#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__first__BITNR 0 -#define R_DMA_CH9_FIRST__first__WIDTH 32 - -#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__cmd__BITNR 0 -#define R_DMA_CH9_CMD__cmd__WIDTH 3 -#define R_DMA_CH9_CMD__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__start 1 -#define R_DMA_CH9_CMD__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__reset 4 - -#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__avail__BITNR 0 -#define R_DMA_CH9_STATUS__avail__WIDTH 7 - -/* -!* Test mode registers -!*/ - -#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__single_step__WIDTH 1 -#define R_TEST_MODE__single_step__on 1 -#define R_TEST_MODE__single_step__off 0 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_wr__WIDTH 1 -#define R_TEST_MODE__step_wr__on 1 -#define R_TEST_MODE__step_wr__off 0 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_rd__WIDTH 1 -#define R_TEST_MODE__step_rd__on 1 -#define R_TEST_MODE__step_rd__off 0 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__step_fetch__WIDTH 1 -#define R_TEST_MODE__step_fetch__on 1 -#define R_TEST_MODE__step_fetch__off 0 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__mmu_test__WIDTH 1 -#define R_TEST_MODE__mmu_test__on 1 -#define R_TEST_MODE__mmu_test__off 0 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__usb_test__WIDTH 1 -#define R_TEST_MODE__usb_test__on 1 -#define R_TEST_MODE__usb_test__off 0 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__scsi_timer_test__WIDTH 1 -#define R_TEST_MODE__scsi_timer_test__on 1 -#define R_TEST_MODE__scsi_timer_test__off 0 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__backoff__WIDTH 1 -#define R_TEST_MODE__backoff__on 1 -#define R_TEST_MODE__backoff__off 0 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_test__WIDTH 1 -#define R_TEST_MODE__snmp_test__on 1 -#define R_TEST_MODE__snmp_test__off 0 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__snmp_inc__WIDTH 1 -#define R_TEST_MODE__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__ser_loop__WIDTH 1 -#define R_TEST_MODE__ser_loop__on 1 -#define R_TEST_MODE__ser_loop__off 0 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__baudrate__WIDTH 1 -#define R_TEST_MODE__baudrate__on 1 -#define R_TEST_MODE__baudrate__off 0 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__timer__WIDTH 2 -#define R_TEST_MODE__timer__off 0 -#define R_TEST_MODE__timer__even 1 -#define R_TEST_MODE__timer__odd 2 -#define R_TEST_MODE__timer__all 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__cache_test__WIDTH 1 -#define R_TEST_MODE__cache_test__normal 0 -#define R_TEST_MODE__cache_test__test 1 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__tag_test__WIDTH 1 -#define R_TEST_MODE__tag_test__normal 0 -#define R_TEST_MODE__tag_test__test 1 -#define R_TEST_MODE__cache_enable__BITNR 0 -#define R_TEST_MODE__cache_enable__WIDTH 1 -#define R_TEST_MODE__cache_enable__enable 1 -#define R_TEST_MODE__cache_enable__disable 0 - -#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__single_step__WIDTH 1 -#define R_SINGLE_STEP__single_step__on 1 -#define R_SINGLE_STEP__single_step__off 0 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_wr__WIDTH 1 -#define R_SINGLE_STEP__step_wr__on 1 -#define R_SINGLE_STEP__step_wr__off 0 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_rd__WIDTH 1 -#define R_SINGLE_STEP__step_rd__on 1 -#define R_SINGLE_STEP__step_rd__off 0 -#define R_SINGLE_STEP__step_fetch__BITNR 0 -#define R_SINGLE_STEP__step_fetch__WIDTH 1 -#define R_SINGLE_STEP__step_fetch__on 1 -#define R_SINGLE_STEP__step_fetch__off 0 - -/* -!* USB interface control registers -!*/ - -#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__major__WIDTH 4 -#define R_USB_REVISION__minor__BITNR 0 -#define R_USB_REVISION__minor__WIDTH 4 - -#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_sel__WIDTH 2 -#define R_USB_COMMAND__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port2 2 -#define R_USB_COMMAND__port_sel__both 3 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__port_cmd__WIDTH 2 -#define R_USB_COMMAND__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__suspend 2 -#define R_USB_COMMAND__port_cmd__resume 3 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__busy__WIDTH 1 -#define R_USB_COMMAND__busy__no 0 -#define R_USB_COMMAND__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__reset 1 -#define R_USB_COMMAND__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__host_stop 7 - -#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 -#define R_USB_COMMAND_DEV__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 -#define R_USB_COMMAND_DEV__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__busy__WIDTH 1 -#define R_USB_COMMAND_DEV__busy__no 0 -#define R_USB_COMMAND_DEV__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 - -#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__ourun__WIDTH 1 -#define R_USB_STATUS__ourun__no 0 -#define R_USB_STATUS__ourun__yes 1 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__perror__WIDTH 1 -#define R_USB_STATUS__perror__no 0 -#define R_USB_STATUS__perror__yes 1 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__device_mode__WIDTH 1 -#define R_USB_STATUS__device_mode__no 0 -#define R_USB_STATUS__device_mode__yes 1 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__host_mode__WIDTH 1 -#define R_USB_STATUS__host_mode__no 0 -#define R_USB_STATUS__host_mode__yes 1 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__started__WIDTH 1 -#define R_USB_STATUS__started__no 0 -#define R_USB_STATUS__started__yes 1 -#define R_USB_STATUS__running__BITNR 0 -#define R_USB_STATUS__running__WIDTH 1 -#define R_USB_STATUS__running__no 0 -#define R_USB_STATUS__running__yes 1 - -#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 - -#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__sof__WIDTH 1 -#define R_USB_IRQ_READ__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__pend 1 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__port_status__WIDTH 1 -#define R_USB_IRQ_READ__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 - -#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 - -#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__value__BITNR 0 -#define R_USB_FM_NUMBER__value__WIDTH 32 - -#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__fixed__WIDTH 8 -#define R_USB_FM_INTERVAL__adj__BITNR 0 -#define R_USB_FM_INTERVAL__adj__WIDTH 6 - -#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__value__BITNR 0 -#define R_USB_FM_REMAINING__value__WIDTH 14 - -#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__value__BITNR 0 -#define R_USB_FM_PSTART__value__WIDTH 14 - -#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble2__WIDTH 1 -#define R_USB_RH_STATUS__babble2__no 0 -#define R_USB_RH_STATUS__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__babble1__WIDTH 1 -#define R_USB_RH_STATUS__babble1__no 0 -#define R_USB_RH_STATUS__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus1__WIDTH 2 -#define R_USB_RH_STATUS__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__bus2__WIDTH 2 -#define R_USB_RH_STATUS__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__SE1 3 -#define R_USB_RH_STATUS__nports__BITNR 0 -#define R_USB_RH_STATUS__nports__WIDTH 2 - -#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__yes 1 - -#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__yes 1 - -#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__value__BITNR 0 -#define R_USB_EPT_INDEX__value__WIDTH 5 - -#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__valid__WIDTH 1 -#define R_USB_EPT_DATA__valid__no 0 -#define R_USB_EPT_DATA__valid__yes 1 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__hold__WIDTH 1 -#define R_USB_EPT_DATA__hold__no 0 -#define R_USB_EPT_DATA__hold__yes 1 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__error_count_in__WIDTH 2 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__t_in__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__low_speed__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__yes 1 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__port__WIDTH 2 -#define R_USB_EPT_DATA__port__any 0 -#define R_USB_EPT_DATA__port__p1 1 -#define R_USB_EPT_DATA__port__p2 2 -#define R_USB_EPT_DATA__port__undef 3 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__error_code__WIDTH 2 -#define R_USB_EPT_DATA__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__stall 1 -#define R_USB_EPT_DATA__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__buffer_error 3 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__t_out__WIDTH 1 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__error_count_out__WIDTH 2 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__max_len__WIDTH 7 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__ep__WIDTH 4 -#define R_USB_EPT_DATA__dev__BITNR 0 -#define R_USB_EPT_DATA__dev__WIDTH 7 - -#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 -#define R_USB_EPT_DATA_ISO__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__port__WIDTH 2 -#define R_USB_EPT_DATA_ISO__port__any 0 -#define R_USB_EPT_DATA_ISO__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 -#define R_USB_EPT_DATA_ISO__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__stall 1 -#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 -#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 - -#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 -#define R_USB_EPT_DATA_DEV__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 -#define R_USB_EPT_DATA_DEV__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 -#define R_USB_EPT_DATA_DEV__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 -#define R_USB_EPT_DATA_DEV__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__yes 1 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__port__WIDTH 2 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__t__WIDTH 1 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 -#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 - -#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__value__BITNR 0 -#define R_USB_SNMP_TERROR__value__WIDTH 32 - -#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__value__BITNR 0 -#define R_USB_EPID_ATTN__value__WIDTH 32 - -#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) -#define R_USB_PORT1_DISABLE__disable__BITNR 0 -#define R_USB_PORT1_DISABLE__disable__WIDTH 1 -#define R_USB_PORT1_DISABLE__disable__yes 0 -#define R_USB_PORT1_DISABLE__disable__no 1 - -#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) -#define R_USB_PORT2_DISABLE__disable__BITNR 0 -#define R_USB_PORT2_DISABLE__disable__WIDTH 1 -#define R_USB_PORT2_DISABLE__disable__yes 0 -#define R_USB_PORT2_DISABLE__disable__no 1 - -/* -!* MMU registers -!*/ - -#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__mmu_enable__WIDTH 1 -#define R_MMU_CONFIG__mmu_enable__enable 1 -#define R_MMU_CONFIG__mmu_enable__disable 0 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__inv_excp__WIDTH 1 -#define R_MMU_CONFIG__inv_excp__enable 1 -#define R_MMU_CONFIG__inv_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__acc_excp__WIDTH 1 -#define R_MMU_CONFIG__acc_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__disable 0 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__we_excp__WIDTH 1 -#define R_MMU_CONFIG__we_excp__enable 1 -#define R_MMU_CONFIG__we_excp__disable 0 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_f__WIDTH 1 -#define R_MMU_CONFIG__seg_f__seg 1 -#define R_MMU_CONFIG__seg_f__page 0 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_e__WIDTH 1 -#define R_MMU_CONFIG__seg_e__seg 1 -#define R_MMU_CONFIG__seg_e__page 0 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_d__WIDTH 1 -#define R_MMU_CONFIG__seg_d__seg 1 -#define R_MMU_CONFIG__seg_d__page 0 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_c__WIDTH 1 -#define R_MMU_CONFIG__seg_c__seg 1 -#define R_MMU_CONFIG__seg_c__page 0 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_b__WIDTH 1 -#define R_MMU_CONFIG__seg_b__seg 1 -#define R_MMU_CONFIG__seg_b__page 0 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_a__WIDTH 1 -#define R_MMU_CONFIG__seg_a__seg 1 -#define R_MMU_CONFIG__seg_a__page 0 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_9__WIDTH 1 -#define R_MMU_CONFIG__seg_9__seg 1 -#define R_MMU_CONFIG__seg_9__page 0 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_8__WIDTH 1 -#define R_MMU_CONFIG__seg_8__seg 1 -#define R_MMU_CONFIG__seg_8__page 0 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_7__WIDTH 1 -#define R_MMU_CONFIG__seg_7__seg 1 -#define R_MMU_CONFIG__seg_7__page 0 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_6__WIDTH 1 -#define R_MMU_CONFIG__seg_6__seg 1 -#define R_MMU_CONFIG__seg_6__page 0 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_5__WIDTH 1 -#define R_MMU_CONFIG__seg_5__seg 1 -#define R_MMU_CONFIG__seg_5__page 0 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_4__WIDTH 1 -#define R_MMU_CONFIG__seg_4__seg 1 -#define R_MMU_CONFIG__seg_4__page 0 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_3__WIDTH 1 -#define R_MMU_CONFIG__seg_3__seg 1 -#define R_MMU_CONFIG__seg_3__page 0 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_2__WIDTH 1 -#define R_MMU_CONFIG__seg_2__seg 1 -#define R_MMU_CONFIG__seg_2__page 0 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_1__WIDTH 1 -#define R_MMU_CONFIG__seg_1__seg 1 -#define R_MMU_CONFIG__seg_1__page 0 -#define R_MMU_CONFIG__seg_0__BITNR 0 -#define R_MMU_CONFIG__seg_0__WIDTH 1 -#define R_MMU_CONFIG__seg_0__seg 1 -#define R_MMU_CONFIG__seg_0__page 0 - -#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_f__WIDTH 1 -#define R_MMU_KSEG__seg_f__seg 1 -#define R_MMU_KSEG__seg_f__page 0 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_e__WIDTH 1 -#define R_MMU_KSEG__seg_e__seg 1 -#define R_MMU_KSEG__seg_e__page 0 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_d__WIDTH 1 -#define R_MMU_KSEG__seg_d__seg 1 -#define R_MMU_KSEG__seg_d__page 0 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_c__WIDTH 1 -#define R_MMU_KSEG__seg_c__seg 1 -#define R_MMU_KSEG__seg_c__page 0 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_b__WIDTH 1 -#define R_MMU_KSEG__seg_b__seg 1 -#define R_MMU_KSEG__seg_b__page 0 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_a__WIDTH 1 -#define R_MMU_KSEG__seg_a__seg 1 -#define R_MMU_KSEG__seg_a__page 0 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_9__WIDTH 1 -#define R_MMU_KSEG__seg_9__seg 1 -#define R_MMU_KSEG__seg_9__page 0 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_8__WIDTH 1 -#define R_MMU_KSEG__seg_8__seg 1 -#define R_MMU_KSEG__seg_8__page 0 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_7__WIDTH 1 -#define R_MMU_KSEG__seg_7__seg 1 -#define R_MMU_KSEG__seg_7__page 0 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_6__WIDTH 1 -#define R_MMU_KSEG__seg_6__seg 1 -#define R_MMU_KSEG__seg_6__page 0 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_5__WIDTH 1 -#define R_MMU_KSEG__seg_5__seg 1 -#define R_MMU_KSEG__seg_5__page 0 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_4__WIDTH 1 -#define R_MMU_KSEG__seg_4__seg 1 -#define R_MMU_KSEG__seg_4__page 0 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_3__WIDTH 1 -#define R_MMU_KSEG__seg_3__seg 1 -#define R_MMU_KSEG__seg_3__page 0 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_2__WIDTH 1 -#define R_MMU_KSEG__seg_2__seg 1 -#define R_MMU_KSEG__seg_2__page 0 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_1__WIDTH 1 -#define R_MMU_KSEG__seg_1__seg 1 -#define R_MMU_KSEG__seg_1__page 0 -#define R_MMU_KSEG__seg_0__BITNR 0 -#define R_MMU_KSEG__seg_0__WIDTH 1 -#define R_MMU_KSEG__seg_0__seg 1 -#define R_MMU_KSEG__seg_0__page 0 - -#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__inv_excp__WIDTH 1 -#define R_MMU_CTRL__inv_excp__enable 1 -#define R_MMU_CTRL__inv_excp__disable 0 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__acc_excp__WIDTH 1 -#define R_MMU_CTRL__acc_excp__enable 1 -#define R_MMU_CTRL__acc_excp__disable 0 -#define R_MMU_CTRL__we_excp__BITNR 0 -#define R_MMU_CTRL__we_excp__WIDTH 1 -#define R_MMU_CTRL__we_excp__enable 1 -#define R_MMU_CTRL__we_excp__disable 0 - -#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) -#define R_MMU_ENABLE__mmu_enable__BITNR 7 -#define R_MMU_ENABLE__mmu_enable__WIDTH 1 -#define R_MMU_ENABLE__mmu_enable__enable 1 -#define R_MMU_ENABLE__mmu_enable__disable 0 - -#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_7__WIDTH 4 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_6__WIDTH 4 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_5__WIDTH 4 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_4__WIDTH 4 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_3__WIDTH 4 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_2__WIDTH 4 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_1__WIDTH 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 -#define R_MMU_KBASE_LO__base_0__WIDTH 4 - -#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_f__WIDTH 4 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_e__WIDTH 4 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_d__WIDTH 4 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_c__WIDTH 4 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_b__WIDTH 4 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_a__WIDTH 4 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_9__WIDTH 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 -#define R_MMU_KBASE_HI__base_8__WIDTH 4 - -#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__page_id__BITNR 0 -#define R_MMU_CONTEXT__page_id__WIDTH 6 - -#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__vpn__WIDTH 19 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__miss_excp__WIDTH 1 -#define R_MMU_CAUSE__miss_excp__yes 1 -#define R_MMU_CAUSE__miss_excp__no 0 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__inv_excp__WIDTH 1 -#define R_MMU_CAUSE__inv_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__no 0 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__acc_excp__WIDTH 1 -#define R_MMU_CAUSE__acc_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__no 0 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__we_excp__WIDTH 1 -#define R_MMU_CAUSE__we_excp__yes 1 -#define R_MMU_CAUSE__we_excp__no 0 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__wr_rd__WIDTH 1 -#define R_MMU_CAUSE__wr_rd__write 1 -#define R_MMU_CAUSE__wr_rd__read 0 -#define R_MMU_CAUSE__page_id__BITNR 0 -#define R_MMU_CAUSE__page_id__WIDTH 6 - -#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__index__BITNR 0 -#define R_TLB_SELECT__index__WIDTH 6 - -#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__pfn__WIDTH 19 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__global__WIDTH 1 -#define R_TLB_LO__global__yes 1 -#define R_TLB_LO__global__no 0 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__valid__WIDTH 1 -#define R_TLB_LO__valid__yes 1 -#define R_TLB_LO__valid__no 0 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__kernel__WIDTH 1 -#define R_TLB_LO__kernel__yes 1 -#define R_TLB_LO__kernel__no 0 -#define R_TLB_LO__we__BITNR 0 -#define R_TLB_LO__we__WIDTH 1 -#define R_TLB_LO__we__yes 1 -#define R_TLB_LO__we__no 0 - -#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__vpn__WIDTH 19 -#define R_TLB_HI__page_id__BITNR 0 -#define R_TLB_HI__page_id__WIDTH 6 - -/* -!* Syncrounous serial port registers -!*/ - -#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 - -#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 - diff --git a/include/asm-cris/arch-v10/sv_addr_ag.h b/include/asm-cris/arch-v10/sv_addr_ag.h deleted file mode 100644 index e4a6b68b8982..000000000000 --- a/include/asm-cris/arch-v10/sv_addr_ag.h +++ /dev/null @@ -1,139 +0,0 @@ -/*!************************************************************************** -*! -*! MACROS: -*! IO_MASK(reg,field) -*! IO_STATE(reg,field,state) -*! IO_EXTRACT(reg,field,val) -*! IO_STATE_VALUE(reg,field,state) -*! IO_BITNR(reg,field) -*! IO_WIDTH(reg,field) -*! IO_FIELD(reg,field,val) -*! IO_RD(reg) -*! All moderegister addresses and fields of these. -*! -*!**************************************************************************/ - -#ifndef __sv_addr_ag_h__ -#define __sv_addr_ag_h__ - - -#define __test_sv_addr__ 0 - -/*------------------------------------------------------------ -!* General macros to manipulate moderegisters. -!*-----------------------------------------------------------*/ - -/* IO_MASK returns a mask for a specified bitfield in a register. - Note that this macro doesn't work when field width is 32 bits. */ -#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) -#define IO_MASK_(reg_, field_) \ - ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) - -/* IO_STATE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Shifted to correct position) */ -#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) -#define IO_STATE_(reg_, field_, _state) \ - ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) - -/* IO_EXTRACT returns the masked and shifted value corresponding to the - bitfield can have. */ -#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) -#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ - - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) - -/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Not shifted) */ -#define IO_STATE_VALUE(reg, field, state) \ - IO_STATE_VALUE_ (reg##_, field##_, _##state) -#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) - -/* IO_FIELD shifts the val parameter to be aligned with the bitfield - specified. */ -#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) -#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) - -/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is - LSB and the returned bitnumber is LSB of the field. */ -#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) -#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) - -/* IO_WIDTH returns the width, in bits, of a bitfield. */ -#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) -#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) - -/*--- Obsolete. Kept for backw compatibility. ---*/ -/* Reads (or writes) a byte/uword/udword from the specified mode - register. */ -#define IO_RD(reg) (*(volatile u32*)(reg)) -#define IO_RD_B(reg) (*(volatile u8*)(reg)) -#define IO_RD_W(reg) (*(volatile u16*)(reg)) -#define IO_RD_D(reg) (*(volatile u32*)(reg)) - -/*------------------------------------------------------------ -!* Start addresses of the different memory areas. -!*-----------------------------------------------------------*/ - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -/*------------------------------------------------------------ -!* Type casts used in mode register macros, making pointer -!* dereferencing possible. Empty in assembler. -!*-----------------------------------------------------------*/ - -#ifndef __ASSEMBLER__ -# define IO_TYPECAST_UDWORD (volatile u32*) -# define IO_TYPECAST_RO_UDWORD (const volatile u32*) -# define IO_TYPECAST_UWORD (volatile u16*) -# define IO_TYPECAST_RO_UWORD (const volatile u16*) -# define IO_TYPECAST_BYTE (volatile u8*) -# define IO_TYPECAST_RO_BYTE (const volatile u8*) -#else -# define IO_TYPECAST_UDWORD -# define IO_TYPECAST_RO_UDWORD -# define IO_TYPECAST_UWORD -# define IO_TYPECAST_RO_UWORD -# define IO_TYPECAST_BYTE -# define IO_TYPECAST_RO_BYTE -#endif - -/*------------------------------------------------------------*/ - -#include "sv_addr.agh" - -#if __test_sv_addr__ -/* IO_MASK( R_BUS_CONFIG , CE ) */ -IO_MASK( R_WAITSTATES , SRAM_WS ) -IO_MASK( R_TEST , W32 ) - -IO_STATE( R_BUS_CONFIG, CE, DISABLE ) -IO_STATE( R_BUS_CONFIG, CE, ENABLE ) - -IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) - -IO_MASK( R_DRAM_TIMING, REF ) - -IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) - -IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) - == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) -#endif - - -#endif /* ifndef __sv_addr_ag_h__ */ - diff --git a/include/asm-cris/arch-v10/svinto.h b/include/asm-cris/arch-v10/svinto.h deleted file mode 100644 index 0881a1af7cee..000000000000 --- a/include/asm-cris/arch-v10/svinto.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CRIS_SVINTO_H -#define _ASM_CRIS_SVINTO_H - -#include "sv_addr_ag.h" - -extern unsigned int genconfig_shadow; /* defined and set in head.S */ - -/* dma stuff */ - -enum { /* Available in: */ - d_eol = (1 << 0), /* flags */ - d_eop = (1 << 1), /* flags & status */ - d_wait = (1 << 2), /* flags */ - d_int = (1 << 3), /* flags */ - d_txerr = (1 << 4), /* flags */ - d_stop = (1 << 4), /* status */ - d_ecp = (1 << 4), /* flags & status */ - d_pri = (1 << 5), /* flags & status */ - d_alignerr = (1 << 6), /* status */ - d_crcerr = (1 << 7) /* status */ -}; - -/* Do remember that DMA does not go through the MMU and needs - * a real physical address, not an address virtually mapped or - * paged. Therefore the buf/next ptrs below are unsigned long instead - * of void * to give a warning if you try to put a pointer directly - * to them instead of going through virt_to_phys/phys_to_virt. - */ - -typedef struct etrax_dma_descr { - unsigned short sw_len; /* 0-1 */ - unsigned short ctrl; /* 2-3 */ - unsigned long next; /* 4-7 */ - unsigned long buf; /* 8-11 */ - unsigned short hw_len; /* 12-13 */ - unsigned char status; /* 14 */ - unsigned char fifo_len; /* 15 */ -} etrax_dma_descr; - - -/* Use this for constant numbers only */ -#define RESET_DMA_NUM( n ) \ - *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) - -/* Use this for constant numbers or symbols, - * having two macros makes it possible to use constant expressions. - */ -#define RESET_DMA( n ) RESET_DMA_NUM( n ) - - -/* Use this for constant numbers only */ -#define WAIT_DMA_NUM( n ) \ - while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ - IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) - -/* Use this for constant numbers or symbols - * having two macros makes it possible to use constant expressions. - */ -#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) - -extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); -extern void flush_etrax_cache(void); - -#endif diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h deleted file mode 100644 index 4a9cd36c9e16..000000000000 --- a/include/asm-cris/arch-v10/system.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_SYSTEM_H -#define __ASM_CRIS_ARCH_SYSTEM_H - - -/* read the CPU version register */ - -static inline unsigned long rdvr(void) { - unsigned char vr; - __asm__ volatile ("move $vr,%0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "cris" - -/* read/write the user-mode stackpointer */ - -static inline unsigned long rdusp(void) { - unsigned long usp; - __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); - return usp; -} - -#define wrusp(usp) \ - __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) - -/* read the current stackpointer */ - -static inline unsigned long rdsp(void) { - unsigned long sp; - __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); - return sp; -} - -static inline unsigned long _get_base(char * addr) -{ - return 0; -} - -#define nop() __asm__ __volatile__ ("nop"); - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* interrupt control.. */ -#define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory"); -#define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory"); -#define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory"); -#define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - !(flags & (1<<5)); \ -}) - -/* For spinlocks etc */ -#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory"); - -#endif diff --git a/include/asm-cris/arch-v10/thread_info.h b/include/asm-cris/arch-v10/thread_info.h deleted file mode 100644 index 218f4152d3e5..000000000000 --- a/include/asm-cris/arch-v10/thread_info.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_ARCH_THREAD_INFO_H -#define _ASM_ARCH_THREAD_INFO_H - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif diff --git a/include/asm-cris/arch-v10/timex.h b/include/asm-cris/arch-v10/timex.h deleted file mode 100644 index e48447d94faf..000000000000 --- a/include/asm-cris/arch-v10/timex.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Use prescale timer at 25000 Hz instead of the baudrate timer at - * 19200 to get rid of the 64ppm to fast timer (and we get better - * resolution within a jiffie as well. - */ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ -/* If you change anything here you must check time.c as well... */ -#define PRESCALE_FREQ 25000000 -#define PRESCALE_VALUE 1000 -#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ -/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_CLKSEL flexible -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - - -#define GET_JIFFIES_USEC() \ - ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) - -unsigned long get_ns_in_jiffie(void); - -static inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie()/1000; -} - -#endif diff --git a/include/asm-cris/arch-v10/tlb.h b/include/asm-cris/arch-v10/tlb.h deleted file mode 100644 index 31525bbe75c3..000000000000 --- a/include/asm-cris/arch-v10/tlb.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* The TLB can host up to 64 different mm contexts at the same time. - * The last page_id is never running - it is used as an invalid page_id - * so we can make TLB entries that will never match. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 64 -#define INVALID_PAGEID 63 -#define NO_CONTEXT -1 - -#endif diff --git a/include/asm-cris/arch-v10/uaccess.h b/include/asm-cris/arch-v10/uaccess.h deleted file mode 100644 index 65b02d9b605a..000000000000 --- a/include/asm-cris/arch-v10/uaccess.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Authors: Bjorn Wesen (bjornw@axis.com) - * Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *after* the faulting - * instruction. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - " "op" %1,[%2]\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) \ - __asm__ __volatile__( \ - " move.d %M1,[%2]\n" \ - "2: move.d %H1,[%2+4]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - " "op" [%2],%1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " moveq 0,%1\n" \ - " jump 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) \ - __asm__ __volatile__( \ - " move.d [%2],%M1\n" \ - "2: move.d [%2+4],%H1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " moveq 0,%1\n" \ - " jump 4b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -static inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3 - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - " move.b [%2+],$r9\n" - "1: beq 2f\n" - " move.b $r9,[%1+]\n" - - " subq 1,%0\n" - " bne 1b\n" - " move.b [%2+],$r9\n" - - "2: sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - - /* There's one address for a fault at the first move, and - two possible PC values for a fault at the second move, - being a delay-slot filler. However, the branch-target - for the second move is the same as the first address. - Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 1b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "r9"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address *after* the insn. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " jump 1b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=r" (to), "=r" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "r9", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "2: move.b $r9,[%0+]\n", \ - "3: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "2: move.w $r9,[%0+]\n" COPY, \ - "3: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "4: move.b $r9,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "2: move.d $r9,[%0+]\n" COPY, \ - "3: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "4: move.b $r9,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "4: move.w $r9,[%0+]\n" COPY, \ - "5: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "6: move.b $r9,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "4: move.d $r9,[%0+]\n" COPY, \ - "5: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "6: move.b $r9,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "6: move.w $r9,[%0+]\n" COPY, \ - "7: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "8: move.b $r9,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "6: move.d $r9,[%0+]\n" COPY, \ - "7: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "8: move.b $r9,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "8: move.w $r9,[%0+]\n" COPY, \ - "9: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "10: move.b $r9,[%0+]\n", \ - "11: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "8: move.d $r9,[%0+]\n" COPY, \ - "9: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "10: move.d $r9,[%0+]\n" COPY, \ - "11: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "12: move.d $r9,[%0+]\n" COPY, \ - "13: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n2:\n", \ - "3: addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n2:\n" COPY, \ - "3: addq 2,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n4:\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n2:\n" COPY, \ - "3: addq 4,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n4:\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n4:\n" COPY, \ - "5: addq 2,%2\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n6:\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n4:\n" COPY, \ - "5: addq 4,%2\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n6:\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n6:\n" COPY, \ - "7: addq 2,%2\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n8:\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n6:\n" COPY, \ - "7: addq 4,%2\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n8:\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n8:\n" COPY, \ - "9: addq 2,%2\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n10:\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n8:\n" COPY, \ - "9: addq 4,%2\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n10:\n" COPY, \ - "11: addq 4,%2\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n12:\n" COPY, \ - "13: addq 4,%2\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " jump 1b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=r" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - " clear.b [%0+]\n2:\n", \ - "3: addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - " clear.w [%0+]\n2:\n", \ - "3: addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - " clear.w [%0+]\n" \ - "2: clear.b [%0+]\n3:\n", \ - "4: addq 2,%1\n" \ - "5: addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - " clear.d [%0+]\n2:\n" CLEAR, \ - "3: addq 4,%1\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - " clear.d [%0+]\n4:\n" CLEAR, \ - "5: addq 4,%1\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - " clear.d [%0+]\n6:\n" CLEAR, \ - "7: addq 4,%1\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - " clear.d [%0+]\n8:\n" CLEAR, \ - "9: addq 4,%1\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - " clear.d [%0+]\n10:\n" CLEAR, \ - "11: addq 4,%1\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - " clear.d [%0+]\n12:\n" CLEAR, \ - "13: addq 4,%1\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -static inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$r9\n" - "0:\n" - " ble 1f\n" - " subq 1,$r9\n" - - " test.b [%0+]\n" - " bne 0b\n" - " test.d $r9\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $r9,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: clear.d %0\n" - " jump 2b\n" - - /* There's one address for a fault at the first move, and - two possible PC values for a fault at the second move, - being a delay-slot filler. However, the branch-target - for the second move is the same as the first address. - Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 0b,3b\n" - " .dword 1b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "r9"); - - return res; -} - -#endif diff --git a/include/asm-cris/arch-v10/unistd.h b/include/asm-cris/arch-v10/unistd.h deleted file mode 100644 index d1a38b9e6264..000000000000 --- a/include/asm-cris/arch-v10/unistd.h +++ /dev/null @@ -1,148 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "move %6,$mof\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "g" (arg5)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "move %6,$mof\n\tmove %7,$srp\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ - : "srp"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/include/asm-cris/arch-v10/user.h b/include/asm-cris/arch-v10/user.h deleted file mode 100644 index 9303ea77c915..000000000000 --- a/include/asm-cris/arch-v10/user.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_USER_H -#define __ASM_CRIS_ARCH_USER_H - -/* User mode registers, used for core dumps. In order to keep ELF_NGREG - sensible we let all registers be 32 bits. The csr registers are included - for future use. */ -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* Stack pointer. */ - unsigned long pc; /* Program counter. */ - unsigned long p0; /* Constant zero (only 8 bits). */ - unsigned long vr; /* Version register (only 8 bits). */ - unsigned long p2; /* Reserved. */ - unsigned long p3; /* Reserved. */ - unsigned long p4; /* Constant zero (only 16 bits). */ - unsigned long ccr; /* Condition code register (only 16 bits). */ - unsigned long p6; /* Reserved. */ - unsigned long mof; /* Multiply overflow register. */ - unsigned long p8; /* Constant zero. */ - unsigned long ibr; /* Not accessible. */ - unsigned long irp; /* Not accessible. */ - unsigned long srp; /* Subroutine return pointer. */ - unsigned long bar; /* Not accessible. */ - unsigned long dccr; /* Dword condition code register. */ - unsigned long brp; /* Not accessible. */ - unsigned long usp; /* User-mode stack pointer. Same as sp when - in user mode. */ - unsigned long csrinstr; /* Internal status registers. */ - unsigned long csraddr; - unsigned long csrdata; -}; - -#endif diff --git a/include/asm-cris/arch-v32/Kbuild b/include/asm-cris/arch-v32/Kbuild deleted file mode 100644 index 35f2fc4f993e..000000000000 --- a/include/asm-cris/arch-v32/Kbuild +++ /dev/null @@ -1,2 +0,0 @@ -header-y += user.h -header-y += cryptocop.h diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h deleted file mode 100644 index 081a911d7af1..000000000000 --- a/include/asm-cris/arch-v32/arbiter.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum -{ - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum -{ - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback* cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h deleted file mode 100644 index 852ceff8013f..000000000000 --- a/include/asm-cris/arch-v32/atomic.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_ATOMIC__ -#define __ASM_CRIS_ARCH_ATOMIC__ - -#include - -extern void cris_spin_unlock(void *l, int val); -extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void* l); - -#ifndef CONFIG_SMP -#define cris_atomic_save(addr, flags) local_irq_save(flags); -#define cris_atomic_restore(addr, flags) local_irq_restore(flags); -#else - -extern spinlock_t cris_atomic_locks[]; -#define LOCK_COUNT 128 -#define HASH_ADDR(a) (((int)a) & 127) - -#define cris_atomic_save(addr, flags) \ - local_irq_save(flags); \ - cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock); - -#define cris_atomic_restore(addr, flags) \ - { \ - spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ - __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->raw_lock.slock) \ - : "r" (1) \ - : "memory"); \ - local_irq_restore(flags); \ - } - -#endif - -#endif - diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h deleted file mode 100644 index 147689d6b624..000000000000 --- a/include/asm-cris/arch-v32/bitops.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_BITOPS_H -#define _ASM_CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions. They compute the - * number of leading zeroes of a bits-in-byte, byte-in-word and - * word-in-dword-swapped number. They differ in that the first function also - * inverts all bits in the input. - */ - -static inline unsigned long -cris_swapnwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapnwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -static inline unsigned long -cris_swapwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -/* - * Find First Zero in word. Undefined if no zero exist, so the caller should - * check against ~0 first. - */ -static inline unsigned long -ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/* - * Find First Set bit in word. Undefined if no 1 exist, so the caller - * should check against 0 first. - */ -static inline unsigned long -__ffs(unsigned long w) -{ - return cris_swapnwbrlz(~w); -} - -/* - * Find First Bit that is set. - */ -static inline unsigned long -kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/include/asm-cris/arch-v32/bug.h b/include/asm-cris/arch-v32/bug.h deleted file mode 100644 index 0f211e135248..000000000000 --- a/include/asm-cris/arch-v32/bug.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_CRISv32_ARCH_BUG_H -#define __ASM_CRISv32_ARCH_BUG_H - -#include - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -/* - * The penalty for the in-band code path will be the size of break 14. - * All other stuff is done out-of-band with exception handlers. - */ -#define BUG() \ - __asm__ __volatile__ ("0: break 14\n\t" \ - ".section .fixup,\"ax\"\n" \ - "1:\n\t" \ - "move.d %0, $r10\n\t" \ - "move.d %1, $r11\n\t" \ - "jump do_BUG\n\t" \ - "nop\n\t" \ - ".previous\n\t" \ - ".section __ex_table,\"a\"\n\t" \ - ".dword 0b, 1b\n\t" \ - ".previous\n\t" \ - : : "ri" (__FILE__), "i" (__LINE__)) -#else -#define BUG() __asm__ __volatile__ ("break 14\n\t") -#endif - -#define HAVE_ARCH_BUG -#endif - -#include -#endif diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h deleted file mode 100644 index 6ef8fb4a35f2..000000000000 --- a/include/asm-cris/arch-v32/byteorder.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_BYTEORDER_H -#define _ASM_CRIS_ARCH_BYTEORDER_H - -#include - -static inline __const__ __u32 -___arch__swab32(__u32 x) -{ - __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); - return (x); -} - -static inline __const__ __u16 -___arch__swab16(__u16 x) -{ - __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); - return (x); -} - -#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */ diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h deleted file mode 100644 index b3d752dfe15b..000000000000 --- a/include/asm-cris/arch-v32/cache.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_CACHE_H -#define _ASM_CRIS_ARCH_CACHE_H - -#include - -/* A cache-line is 32 bytes. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 - -void flush_dma_list(dma_descr_data *descr); -void flush_dma_descr(dma_descr_data *descr, int flush_buf); - -#define flush_dma_context(c) \ - flush_dma_list(phys_to_virt((c)->saved_data)); - -void cris_flush_cache_range(void *buf, unsigned long len); -void cris_flush_cache(void); - -#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h deleted file mode 100644 index e5dcfce6e0dc..000000000000 --- a/include/asm-cris/arch-v32/checksum.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_CHECKSUM_H -#define _ASM_CRIS_ARCH_CHECKSUM_H - -/* - * Check values used in TCP/UDP headers. - * - * The gain of doing this in assembler instead of C, is that C doesn't - * generate carry-additions for the 32-bit components of the - * checksum. Which means it would be necessary to split all those into - * 16-bit components and then add. - */ -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, - unsigned short len, unsigned short proto, __wsum sum) -{ - __wsum res; - - __asm__ __volatile__ ("add.d %2, %0\n\t" - "addc %3, %0\n\t" - "addc %4, %0\n\t" - "addc 0, %0\n\t" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), \ - "r" ((len + proto) << 8)); - - return res; -} - -#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h deleted file mode 100644 index dfa1f66fb987..000000000000 --- a/include/asm-cris/arch-v32/cryptocop.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * The device /dev/cryptocop is accessible using this driver using - * CRYPTOCOP_MAJOR (254) and minor number 0. - */ - -#ifndef CRYPTOCOP_H -#define CRYPTOCOP_H - -#include - - -#define CRYPTOCOP_SESSION_ID_NONE (0) - -typedef unsigned long long int cryptocop_session_id; - -/* cryptocop ioctls */ -#define ETRAXCRYPTOCOP_IOCTYPE (250) - -#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) -#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) -#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) -#define CRYPTOCOP_IO_MAXNR (3) - -typedef enum { - cryptocop_cipher_des = 0, - cryptocop_cipher_3des = 1, - cryptocop_cipher_aes = 2, - cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ - cryptocop_cipher_none -} cryptocop_cipher_type; - -typedef enum { - cryptocop_digest_sha1 = 0, - cryptocop_digest_md5 = 1, - cryptocop_digest_none -} cryptocop_digest_type; - -typedef enum { - cryptocop_csum_le = 0, - cryptocop_csum_be = 1, - cryptocop_csum_none -} cryptocop_csum_type; - -typedef enum { - cryptocop_cipher_mode_ecb = 0, - cryptocop_cipher_mode_cbc, - cryptocop_cipher_mode_none -} cryptocop_cipher_mode; - -typedef enum { - cryptocop_3des_eee = 0, - cryptocop_3des_eed = 1, - cryptocop_3des_ede = 2, - cryptocop_3des_edd = 3, - cryptocop_3des_dee = 4, - cryptocop_3des_ded = 5, - cryptocop_3des_dde = 6, - cryptocop_3des_ddd = 7 -} cryptocop_3des_mode; - -/* Usermode accessible (ioctl) operations. */ -struct strcop_session_op{ - cryptocop_session_id ses_id; - - cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ - - cryptocop_cipher_mode cmode; /* ECB, CBC, none */ - cryptocop_3des_mode des3_mode; - - cryptocop_digest_type digest; /* MD5, SHA1, none */ - - cryptocop_csum_type csum; /* BE, LE, none */ - - unsigned char *key; - size_t keylen; -}; - -#define CRYPTOCOP_CSUM_LENGTH (2) -#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ -#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ -#define CRYPTOCOP_MAX_KEY_LENGTH (32) - -struct strcop_crypto_op{ - cryptocop_session_id ses_id; - - /* Indata. */ - unsigned char *indata; - size_t inlen; /* Total indata length. */ - - /* Cipher configuration. */ - unsigned char do_cipher:1; - unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ - unsigned char cipher_explicit:1; - size_t cipher_start; - size_t cipher_len; - /* cipher_iv is used if do_cipher and cipher_explicit and the cipher - mode is CBC. The length is controlled by the type of cipher, - e.g. DES/3DES 8 octets and AES 16 octets. */ - unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; - /* Outdata. */ - unsigned char *cipher_outdata; - size_t cipher_outlen; - - /* digest configuration. */ - unsigned char do_digest:1; - size_t digest_start; - size_t digest_len; - /* Outdata. The actual length is determined by the type of the digest. */ - unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; - - /* Checksum configuration. */ - unsigned char do_csum:1; - size_t csum_start; - size_t csum_len; - /* Outdata. */ - unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; -}; - - - -#ifdef __KERNEL__ - -/********** The API to use from inside the kernel. ************/ - -#include - -typedef enum { - cryptocop_alg_csum = 0, - cryptocop_alg_mem2mem, - cryptocop_alg_md5, - cryptocop_alg_sha1, - cryptocop_alg_des, - cryptocop_alg_3des, - cryptocop_alg_aes, - cryptocop_no_alg, -} cryptocop_algorithm; - -typedef u8 cryptocop_tfrm_id; - - -struct cryptocop_operation; - -typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); - -struct cryptocop_transform_init { - cryptocop_algorithm alg; - /* Keydata for ciphers. */ - unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; - unsigned int keylen; - cryptocop_cipher_mode cipher_mode; - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ - - cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ - struct cryptocop_transform_init *next; -}; - - -typedef enum { - cryptocop_source_dma = 0, - cryptocop_source_des, - cryptocop_source_3des, - cryptocop_source_aes, - cryptocop_source_md5, - cryptocop_source_sha1, - cryptocop_source_csum, - cryptocop_source_none, -} cryptocop_source; - - -struct cryptocop_desc_cfg { - cryptocop_tfrm_id tid; - cryptocop_source src; - unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ - struct cryptocop_desc_cfg *next; -}; - -struct cryptocop_desc { - size_t length; - struct cryptocop_desc_cfg *cfg; - struct cryptocop_desc *next; -}; - - -/* Flags for cryptocop_tfrm_cfg */ -#define CRYPTOCOP_NO_FLAG (0x00) -#define CRYPTOCOP_ENCRYPT (0x01) -#define CRYPTOCOP_DECRYPT (0x02) -#define CRYPTOCOP_EXPLICIT_IV (0x04) - -struct cryptocop_tfrm_cfg { - cryptocop_tfrm_id tid; - - unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ - - /* CBC initialisation vector for cihers. */ - u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; - - /* The position in output where to write the transform output. The order - in which the driver writes the output is unspecified, hence if several - transforms write on the same positions in the output the result is - unspecified. */ - size_t inject_ix; - - struct cryptocop_tfrm_cfg *next; -}; - - - -struct cryptocop_dma_list_operation{ - /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in - struct cryptocop_operation must be set for the driver to use them. outlist, - out_data_buf, inlist and in_data_buf must all be physical addresses since they will - be loaded to DMA . */ - dma_descr_data *outlist; /* Out from memory to the co-processor. */ - char *out_data_buf; - dma_descr_data *inlist; /* In from the co-processor to memory. */ - char *in_data_buf; - - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; -}; - - -struct cryptocop_tfrm_operation{ - /* Operation configuration, if not 'use_dmalists' is set. */ - struct cryptocop_tfrm_cfg *tfrm_cfg; - struct cryptocop_desc *desc; - - struct iovec *indata; - size_t incount; - size_t inlen; /* Total inlength. */ - - struct iovec *outdata; - size_t outcount; - size_t outlen; /* Total outlength. */ -}; - - -struct cryptocop_operation { - cryptocop_callback *cb; - void *cb_data; - - cryptocop_session_id sid; - - /* The status of the operation when returned to consumer. */ - int operation_status; /* 0, -EAGAIN */ - - /* Flags */ - unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ - unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ - unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ - - union{ - struct cryptocop_dma_list_operation list_op; - struct cryptocop_tfrm_operation tfrm_op; - }; -}; - - -int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); -int cryptocop_free_session(cryptocop_session_id sid); - -int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); - -#endif /* __KERNEL__ */ - -#endif /* CRYPTOCOP_H */ diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h deleted file mode 100644 index e9fda03810a9..000000000000 --- a/include/asm-cris/arch-v32/delay.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_DELAY_H -#define _ASM_CRIS_ARCH_DELAY_H - -extern void cris_delay10ns(u32 n10ns); -#define udelay(u) cris_delay10ns((u)*100) -#define ndelay(n) cris_delay10ns(((n)+9)/10) - -/* - * Not used anymore for udelay or ndelay. Referenced by - * e.g. init/calibrate.c. All other references are likely bugs; - * should be replaced by mdelay, udelay or ndelay. - */ - -static inline void -__delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0, $r9\n\t" - "beq 2f\n\t" - "subq 1, $r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1, $r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h deleted file mode 100644 index 3674081389fd..000000000000 --- a/include/asm-cris/arch-v32/dma.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 10 - -#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ -#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ - -#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ -#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ - -#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ -#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ - -#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ -#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ - -#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ -#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ - -#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ -#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ - -#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ -#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ - -#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ -#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ - -#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ -#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ - -#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ -#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ - -#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ -#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ - -#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ -#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ - -#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ -#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ - -#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ -#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ - -enum dma_owner -{ - dma_eth0, - dma_eth1, - dma_iop0, - dma_iop1, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_sser0, - dma_sser1, - dma_ata, - dma_strp, - dma_ext0, - dma_ext1, - dma_ext2, - dma_ext3 -}; - -int crisv32_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, unsigned bandwidth, enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h deleted file mode 100644 index 1324e505a4d8..000000000000 --- a/include/asm-cris/arch-v32/elf.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef _ASM_CRIS_ELF_H -#define _ASM_CRIS_ELF_H - -#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* CRISv32 ELF register definitions. */ - -#include - -/* Explicitly zero out registers to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ - (_r)->acr = 0; \ -} while (0) - -/* - * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. - */ -#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) - -/* - * This is basically a pt_regs with the additional definition - * of the stack pointer since it's needed in a core dump. - * pr_regs is a elf_gregset_t and should be filled according - * to the layout of user_regs_struct. - */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* SP */ \ - pr_reg[15] = regs->acr; /* ACR */ \ - pr_reg[16] = 0; /* BZ */ \ - pr_reg[17] = rdvr(); /* VR */ \ - pr_reg[18] = 0; /* PID */ \ - pr_reg[19] = regs->srs; /* SRS */ \ - pr_reg[20] = 0; /* WZ */ \ - pr_reg[21] = regs->exs; /* EXS */ \ - pr_reg[22] = regs->eda; /* EDA */ \ - pr_reg[23] = regs->mof; /* MOF */ \ - pr_reg[24] = 0; /* DZ */ \ - pr_reg[25] = 0; /* EBP */ \ - pr_reg[26] = regs->erp; /* ERP */ \ - pr_reg[27] = regs->srp; /* SRP */ \ - pr_reg[28] = 0; /* NRP */ \ - pr_reg[29] = regs->ccs; /* CCS */ \ - pr_reg[30] = rdusp(); /* USP */ \ - pr_reg[31] = regs->spc; /* SPC */ \ - -#endif /* _ASM_CRIS_ELF_H */ diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile deleted file mode 100644 index f9a05d2aa061..000000000000 --- a/include/asm-cris/arch-v32/hwregs/Makefile +++ /dev/null @@ -1,186 +0,0 @@ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The offical place for these files is at: -RELEASE ?= r1_alfa5 -OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -# which is updated on each new release. -INCL_ASMFILES = -INCL_FILES = ata_defs.h -INCL_FILES += bif_core_defs.h -INCL_ASMFILES += bif_core_defs_asm.h -INCL_FILES += bif_slave_defs.h -#INCL_FILES += bif_slave_ext_defs.h -INCL_FILES += config_defs.h -INCL_ASMFILES += config_defs_asm.h -INCL_FILES += cpu_vect.h -#INCL_FILES += cris_defs.h -#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h -INCL_FILES += dma.h -INCL_FILES += dma_defs.h -INCL_FILES += eth_defs.h -INCL_FILES += extmem_defs.h -INCL_FILES += gio_defs.h -INCL_ASMFILES += gio_defs_asm.h -INCL_FILES += intr_vect.h -INCL_FILES += intr_vect_defs.h -INCL_ASMFILES += intr_vect_defs_asm.h -INCL_FILES += marb_bp_defs.h -INCL_FILES += marb_defs.h -INCL_ASMFILES += mmu_defs_asm.h -#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h -#INCL_FILES += par_defs.h # No useful content -INCL_FILES += pinmux_defs.h -INCL_FILES += reg_map.h -INCL_ASMFILES += reg_map_asm.h -INCL_FILES += reg_rdwr.h -INCL_FILES += ser_defs.h -#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h -INCL_FILES += sser_defs.h -INCL_FILES += strcop_defs.h -#INCL_FILES += strcop.h # Where is this? -INCL_FILES += strmux_defs.h -#INCL_FILES += supp_reg.h # Handcrafted instead -INCL_FILES += timer_defs.h - -REGDESC = -REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r -#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r -REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r -REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r -REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r -REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r -REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r -REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r -REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r -#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r -REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r -REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r -REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r -REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r -REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r -#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - - -BASEDIR = /n/asic/design -DESIGNDIR = /n/asic/projects/guinness/design -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -# Disable implicit rule that may generate deleted files from RCS/ directory. -%.r: - -%.h: - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(INCL_FILES) $(INCL_ASMFILES) - -ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r - $(RDES2C) $< -config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) $< -config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) -asm $< -# Can't generate cpu_vect.h yet -#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? -# $(RDES2INTR) $< -cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r - $(RDES2C) $< -$(BASEDIR)/core/dma/sw/dma.h: -dma.h: $(BASEDIR)/core/dma/sw/dma.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r - $(RDES2C) $< -extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r - $(RDES2C) $< -gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r - $(RDES2C) $< -intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) $< -intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) -asm $< -# Can't generate intr_vect.h yet -#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -# $(RDES2INTR) $< -intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r - $(RDES2C) -asm $< -par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r - $(RDES2C) $< - -# From /n/asic/projects/guinness/design/ -reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 $^ -reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ - -reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r - $(RDES2C) $< -strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r - $(RDES2C) $< -strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r - $(RDES2C) $< -timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r - $(RDES2C) $< -usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - $(RDES2C) $< - -## copy - Copy files from official location -copy: - @for HFILE in $(INCL_FILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(INCL_ASMFILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done -## ls_official - List official location -ls_official: - (cd $(OFFICIAL_INCDIR); ls -l *.h ) - -## diff_official - Diff current directory with official location -diff_official: - diff . $(OFFICIAL_INCDIR) - -## doc - Generate .axw files from register description. -doc: $(REGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming ir .r files. -%.axw: axw - @for RDES in $(REGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(INCL_FILES) *.axw - diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h deleted file mode 100644 index 866191418f9c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef __ata_defs_asm_h -#define __ata_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ctrl0, scope ata, type rw */ -#define reg_ata_rw_ctrl0___pio_hold___lsb 0 -#define reg_ata_rw_ctrl0___pio_hold___width 6 -#define reg_ata_rw_ctrl0___pio_strb___lsb 6 -#define reg_ata_rw_ctrl0___pio_strb___width 6 -#define reg_ata_rw_ctrl0___pio_setup___lsb 12 -#define reg_ata_rw_ctrl0___pio_setup___width 6 -#define reg_ata_rw_ctrl0___dma_hold___lsb 18 -#define reg_ata_rw_ctrl0___dma_hold___width 6 -#define reg_ata_rw_ctrl0___dma_strb___lsb 24 -#define reg_ata_rw_ctrl0___dma_strb___width 6 -#define reg_ata_rw_ctrl0___rst___lsb 30 -#define reg_ata_rw_ctrl0___rst___width 1 -#define reg_ata_rw_ctrl0___rst___bit 30 -#define reg_ata_rw_ctrl0___en___lsb 31 -#define reg_ata_rw_ctrl0___en___width 1 -#define reg_ata_rw_ctrl0___en___bit 31 -#define reg_ata_rw_ctrl0_offset 12 - -/* Register rw_ctrl1, scope ata, type rw */ -#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 -#define reg_ata_rw_ctrl1___udma_tcyc___width 4 -#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 -#define reg_ata_rw_ctrl1___udma_tdvs___width 4 -#define reg_ata_rw_ctrl1_offset 16 - -/* Register rw_ctrl2, scope ata, type rw */ -#define reg_ata_rw_ctrl2___data___lsb 0 -#define reg_ata_rw_ctrl2___data___width 16 -#define reg_ata_rw_ctrl2___dma_size___lsb 19 -#define reg_ata_rw_ctrl2___dma_size___width 1 -#define reg_ata_rw_ctrl2___dma_size___bit 19 -#define reg_ata_rw_ctrl2___multi___lsb 20 -#define reg_ata_rw_ctrl2___multi___width 1 -#define reg_ata_rw_ctrl2___multi___bit 20 -#define reg_ata_rw_ctrl2___hsh___lsb 21 -#define reg_ata_rw_ctrl2___hsh___width 2 -#define reg_ata_rw_ctrl2___trf_mode___lsb 23 -#define reg_ata_rw_ctrl2___trf_mode___width 1 -#define reg_ata_rw_ctrl2___trf_mode___bit 23 -#define reg_ata_rw_ctrl2___rw___lsb 24 -#define reg_ata_rw_ctrl2___rw___width 1 -#define reg_ata_rw_ctrl2___rw___bit 24 -#define reg_ata_rw_ctrl2___addr___lsb 25 -#define reg_ata_rw_ctrl2___addr___width 3 -#define reg_ata_rw_ctrl2___cs0___lsb 28 -#define reg_ata_rw_ctrl2___cs0___width 1 -#define reg_ata_rw_ctrl2___cs0___bit 28 -#define reg_ata_rw_ctrl2___cs1___lsb 29 -#define reg_ata_rw_ctrl2___cs1___width 1 -#define reg_ata_rw_ctrl2___cs1___bit 29 -#define reg_ata_rw_ctrl2___sel___lsb 30 -#define reg_ata_rw_ctrl2___sel___width 2 -#define reg_ata_rw_ctrl2_offset 0 - -/* Register rs_stat_data, scope ata, type rs */ -#define reg_ata_rs_stat_data___data___lsb 0 -#define reg_ata_rs_stat_data___data___width 16 -#define reg_ata_rs_stat_data___dav___lsb 16 -#define reg_ata_rs_stat_data___dav___width 1 -#define reg_ata_rs_stat_data___dav___bit 16 -#define reg_ata_rs_stat_data___busy___lsb 17 -#define reg_ata_rs_stat_data___busy___width 1 -#define reg_ata_rs_stat_data___busy___bit 17 -#define reg_ata_rs_stat_data_offset 4 - -/* Register r_stat_data, scope ata, type r */ -#define reg_ata_r_stat_data___data___lsb 0 -#define reg_ata_r_stat_data___data___width 16 -#define reg_ata_r_stat_data___dav___lsb 16 -#define reg_ata_r_stat_data___dav___width 1 -#define reg_ata_r_stat_data___dav___bit 16 -#define reg_ata_r_stat_data___busy___lsb 17 -#define reg_ata_r_stat_data___busy___width 1 -#define reg_ata_r_stat_data___busy___bit 17 -#define reg_ata_r_stat_data_offset 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -#define reg_ata_rw_trf_cnt___cnt___lsb 0 -#define reg_ata_rw_trf_cnt___cnt___width 17 -#define reg_ata_rw_trf_cnt_offset 20 - -/* Register r_stat_misc, scope ata, type r */ -#define reg_ata_r_stat_misc___crc___lsb 0 -#define reg_ata_r_stat_misc___crc___width 16 -#define reg_ata_r_stat_misc_offset 24 - -/* Register rw_intr_mask, scope ata, type rw */ -#define reg_ata_rw_intr_mask___bus0___lsb 0 -#define reg_ata_rw_intr_mask___bus0___width 1 -#define reg_ata_rw_intr_mask___bus0___bit 0 -#define reg_ata_rw_intr_mask___bus1___lsb 1 -#define reg_ata_rw_intr_mask___bus1___width 1 -#define reg_ata_rw_intr_mask___bus1___bit 1 -#define reg_ata_rw_intr_mask___bus2___lsb 2 -#define reg_ata_rw_intr_mask___bus2___width 1 -#define reg_ata_rw_intr_mask___bus2___bit 2 -#define reg_ata_rw_intr_mask___bus3___lsb 3 -#define reg_ata_rw_intr_mask___bus3___width 1 -#define reg_ata_rw_intr_mask___bus3___bit 3 -#define reg_ata_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope ata, type rw */ -#define reg_ata_rw_ack_intr___bus0___lsb 0 -#define reg_ata_rw_ack_intr___bus0___width 1 -#define reg_ata_rw_ack_intr___bus0___bit 0 -#define reg_ata_rw_ack_intr___bus1___lsb 1 -#define reg_ata_rw_ack_intr___bus1___width 1 -#define reg_ata_rw_ack_intr___bus1___bit 1 -#define reg_ata_rw_ack_intr___bus2___lsb 2 -#define reg_ata_rw_ack_intr___bus2___width 1 -#define reg_ata_rw_ack_intr___bus2___bit 2 -#define reg_ata_rw_ack_intr___bus3___lsb 3 -#define reg_ata_rw_ack_intr___bus3___width 1 -#define reg_ata_rw_ack_intr___bus3___bit 3 -#define reg_ata_rw_ack_intr_offset 32 - -/* Register r_intr, scope ata, type r */ -#define reg_ata_r_intr___bus0___lsb 0 -#define reg_ata_r_intr___bus0___width 1 -#define reg_ata_r_intr___bus0___bit 0 -#define reg_ata_r_intr___bus1___lsb 1 -#define reg_ata_r_intr___bus1___width 1 -#define reg_ata_r_intr___bus1___bit 1 -#define reg_ata_r_intr___bus2___lsb 2 -#define reg_ata_r_intr___bus2___width 1 -#define reg_ata_r_intr___bus2___bit 2 -#define reg_ata_r_intr___bus3___lsb 3 -#define reg_ata_r_intr___bus3___width 1 -#define reg_ata_r_intr___bus3___bit 3 -#define reg_ata_r_intr_offset 36 - -/* Register r_masked_intr, scope ata, type r */ -#define reg_ata_r_masked_intr___bus0___lsb 0 -#define reg_ata_r_masked_intr___bus0___width 1 -#define reg_ata_r_masked_intr___bus0___bit 0 -#define reg_ata_r_masked_intr___bus1___lsb 1 -#define reg_ata_r_masked_intr___bus1___width 1 -#define reg_ata_r_masked_intr___bus1___bit 1 -#define reg_ata_r_masked_intr___bus2___lsb 2 -#define reg_ata_r_masked_intr___bus2___width 1 -#define reg_ata_r_masked_intr___bus2___bit 2 -#define reg_ata_r_masked_intr___bus3___lsb 3 -#define reg_ata_r_masked_intr___bus3___width 1 -#define reg_ata_r_masked_intr___bus3___bit 3 -#define reg_ata_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_ata_active 0x00000001 -#define regk_ata_byte 0x00000001 -#define regk_ata_data 0x00000001 -#define regk_ata_dma 0x00000001 -#define regk_ata_inactive 0x00000000 -#define regk_ata_no 0x00000000 -#define regk_ata_nodata 0x00000000 -#define regk_ata_pio 0x00000000 -#define regk_ata_rd 0x00000001 -#define regk_ata_reg 0x00000000 -#define regk_ata_rw_ctrl0_default 0x00000000 -#define regk_ata_rw_ctrl2_default 0x00000000 -#define regk_ata_rw_intr_mask_default 0x00000000 -#define regk_ata_udma 0x00000002 -#define regk_ata_word 0x00000000 -#define regk_ata_wr 0x00000000 -#define regk_ata_yes 0x00000001 -#endif /* __ata_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index c686cb335621..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,319 +0,0 @@ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h deleted file mode 100644 index 71532aa18168..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h +++ /dev/null @@ -1,495 +0,0 @@ -#ifndef __bif_dma_defs_asm_h -#define __bif_dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch0_ctrl_offset 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch0_addr___addr___width 32 -#define reg_bif_dma_rw_ch0_addr_offset 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_start___run___lsb 0 -#define reg_bif_dma_rw_ch0_start___run___width 1 -#define reg_bif_dma_rw_ch0_start___run___bit 0 -#define reg_bif_dma_rw_ch0_start_offset 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch0_cnt_offset 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch0_stat___cnt___width 16 -#define reg_bif_dma_r_ch0_stat___run___lsb 31 -#define reg_bif_dma_r_ch0_stat___run___width 1 -#define reg_bif_dma_r_ch0_stat___run___bit 31 -#define reg_bif_dma_r_ch0_stat_offset 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch1_ctrl_offset 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch1_addr___addr___width 32 -#define reg_bif_dma_rw_ch1_addr_offset 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_start___run___lsb 0 -#define reg_bif_dma_rw_ch1_start___run___width 1 -#define reg_bif_dma_rw_ch1_start___run___bit 0 -#define reg_bif_dma_rw_ch1_start_offset 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch1_cnt_offset 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch1_stat___cnt___width 16 -#define reg_bif_dma_r_ch1_stat___run___lsb 31 -#define reg_bif_dma_r_ch1_stat___run___width 1 -#define reg_bif_dma_r_ch1_stat___run___bit 31 -#define reg_bif_dma_r_ch1_stat_offset 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch2_ctrl_offset 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch2_addr___addr___width 32 -#define reg_bif_dma_rw_ch2_addr_offset 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_start___run___lsb 0 -#define reg_bif_dma_rw_ch2_start___run___width 1 -#define reg_bif_dma_rw_ch2_start___run___bit 0 -#define reg_bif_dma_rw_ch2_start_offset 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch2_cnt_offset 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch2_stat___cnt___width 16 -#define reg_bif_dma_r_ch2_stat___run___lsb 31 -#define reg_bif_dma_r_ch2_stat___run___width 1 -#define reg_bif_dma_r_ch2_stat___run___bit 31 -#define reg_bif_dma_r_ch2_stat_offset 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch3_ctrl_offset 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch3_addr___addr___width 32 -#define reg_bif_dma_rw_ch3_addr_offset 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_start___run___lsb 0 -#define reg_bif_dma_rw_ch3_start___run___width 1 -#define reg_bif_dma_rw_ch3_start___run___bit 0 -#define reg_bif_dma_rw_ch3_start_offset 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch3_cnt_offset 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch3_stat___cnt___width 16 -#define reg_bif_dma_r_ch3_stat___run___lsb 31 -#define reg_bif_dma_r_ch3_stat___run___width 1 -#define reg_bif_dma_r_ch3_stat___run___bit 31 -#define reg_bif_dma_r_ch3_stat_offset 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 -#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 -#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 -#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 -#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 -#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 -#define reg_bif_dma_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 -#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 -#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 -#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 -#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 -#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 -#define reg_bif_dma_rw_ack_intr_offset 132 - -/* Register r_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_intr___ext_dma0___width 1 -#define reg_bif_dma_r_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_intr___ext_dma1___width 1 -#define reg_bif_dma_r_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_intr___ext_dma2___width 1 -#define reg_bif_dma_r_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_intr___ext_dma3___width 1 -#define reg_bif_dma_r_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_intr_offset 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_masked_intr_offset 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg_offset 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg_offset 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg_offset 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg_offset 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg_offset 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg_offset 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg_offset 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg_offset 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_pin_stat___pin0___lsb 0 -#define reg_bif_dma_r_pin_stat___pin0___width 1 -#define reg_bif_dma_r_pin_stat___pin0___bit 0 -#define reg_bif_dma_r_pin_stat___pin1___lsb 1 -#define reg_bif_dma_r_pin_stat___pin1___width 1 -#define reg_bif_dma_r_pin_stat___pin1___bit 1 -#define reg_bif_dma_r_pin_stat___pin2___lsb 2 -#define reg_bif_dma_r_pin_stat___pin2___width 1 -#define reg_bif_dma_r_pin_stat___pin2___bit 2 -#define reg_bif_dma_r_pin_stat___pin3___lsb 3 -#define reg_bif_dma_r_pin_stat___pin3___width 1 -#define reg_bif_dma_r_pin_stat___pin3___bit 3 -#define reg_bif_dma_r_pin_stat___pin4___lsb 4 -#define reg_bif_dma_r_pin_stat___pin4___width 1 -#define reg_bif_dma_r_pin_stat___pin4___bit 4 -#define reg_bif_dma_r_pin_stat___pin5___lsb 5 -#define reg_bif_dma_r_pin_stat___pin5___width 1 -#define reg_bif_dma_r_pin_stat___pin5___bit 5 -#define reg_bif_dma_r_pin_stat___pin6___lsb 6 -#define reg_bif_dma_r_pin_stat___pin6___width 1 -#define reg_bif_dma_r_pin_stat___pin6___bit 6 -#define reg_bif_dma_r_pin_stat___pin7___lsb 7 -#define reg_bif_dma_r_pin_stat___pin7___width 1 -#define reg_bif_dma_r_pin_stat___pin7___bit 7 -#define reg_bif_dma_r_pin_stat_offset 192 - - -/* Constants */ -#define regk_bif_dma_as_master 0x00000001 -#define regk_bif_dma_as_slave 0x00000001 -#define regk_bif_dma_burst1 0x00000000 -#define regk_bif_dma_burst8 0x00000001 -#define regk_bif_dma_bw16 0x00000001 -#define regk_bif_dma_bw32 0x00000002 -#define regk_bif_dma_bw8 0x00000000 -#define regk_bif_dma_dack 0x00000006 -#define regk_bif_dma_dack_inv 0x00000007 -#define regk_bif_dma_force 0x00000001 -#define regk_bif_dma_hi 0x00000003 -#define regk_bif_dma_inv 0x00000003 -#define regk_bif_dma_lo 0x00000002 -#define regk_bif_dma_master 0x00000001 -#define regk_bif_dma_no 0x00000000 -#define regk_bif_dma_norm 0x00000002 -#define regk_bif_dma_off 0x00000000 -#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch0_start_default 0x00000000 -#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch1_start_default 0x00000000 -#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch2_start_default 0x00000000 -#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch3_start_default 0x00000000 -#define regk_bif_dma_rw_intr_mask_default 0x00000000 -#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 -#define regk_bif_dma_slave 0x00000002 -#define regk_bif_dma_sreq 0x00000006 -#define regk_bif_dma_sreq_inv 0x00000007 -#define regk_bif_dma_tc 0x00000004 -#define regk_bif_dma_tc_inv 0x00000005 -#define regk_bif_dma_yes 0x00000001 -#endif /* __bif_dma_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h deleted file mode 100644 index 031f33a365bb..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_asm_h -#define __bif_slave_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 -#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 -#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 -#define reg_bif_slave_rw_slave_cfg___loopback___width 1 -#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 -#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 -#define reg_bif_slave_rw_slave_cfg___dis___width 1 -#define reg_bif_slave_rw_slave_cfg___dis___bit 6 -#define reg_bif_slave_rw_slave_cfg_offset 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 -#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 -#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 -#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 -#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 -#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 -#define reg_bif_slave_r_slave_mode_offset 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch0_cfg_offset 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch1_cfg_offset 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch2_cfg_offset 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch3_cfg_offset 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 -#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 -#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 -#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 -#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 -#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___release___lsb 7 -#define reg_bif_slave_rw_arb_cfg___release___width 2 -#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 -#define reg_bif_slave_rw_arb_cfg___acquire___width 1 -#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 -#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 -#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 -#define reg_bif_slave_rw_arb_cfg_offset 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 -#define reg_bif_slave_r_arb_stat___init_mode___width 1 -#define reg_bif_slave_r_arb_stat___init_mode___bit 0 -#define reg_bif_slave_r_arb_stat___mode___lsb 1 -#define reg_bif_slave_r_arb_stat___mode___width 1 -#define reg_bif_slave_r_arb_stat___mode___bit 1 -#define reg_bif_slave_r_arb_stat___brin___lsb 2 -#define reg_bif_slave_r_arb_stat___brin___width 1 -#define reg_bif_slave_r_arb_stat___brin___bit 2 -#define reg_bif_slave_r_arb_stat___brout___lsb 3 -#define reg_bif_slave_r_arb_stat___brout___width 1 -#define reg_bif_slave_r_arb_stat___brout___bit 3 -#define reg_bif_slave_r_arb_stat___bg___lsb 4 -#define reg_bif_slave_r_arb_stat___bg___width 1 -#define reg_bif_slave_r_arb_stat___bg___bit 4 -#define reg_bif_slave_r_arb_stat_offset 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 -#define reg_bif_slave_rw_intr_mask___bus_release___width 1 -#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 -#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 -#define reg_bif_slave_rw_intr_mask_offset 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 -#define reg_bif_slave_rw_ack_intr___bus_release___width 1 -#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 -#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 -#define reg_bif_slave_rw_ack_intr_offset 68 - -/* Register r_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_intr___bus_release___lsb 0 -#define reg_bif_slave_r_intr___bus_release___width 1 -#define reg_bif_slave_r_intr___bus_release___bit 0 -#define reg_bif_slave_r_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_intr___bus_acquire___width 1 -#define reg_bif_slave_r_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_intr_offset 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 -#define reg_bif_slave_r_masked_intr___bus_release___width 1 -#define reg_bif_slave_r_masked_intr___bus_release___bit 0 -#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_masked_intr_offset 76 - - -/* Constants */ -#define regk_bif_slave_active_hi 0x00000003 -#define regk_bif_slave_active_lo 0x00000002 -#define regk_bif_slave_addr 0x00000000 -#define regk_bif_slave_always 0x00000001 -#define regk_bif_slave_at_idle 0x00000002 -#define regk_bif_slave_burst_end 0x00000003 -#define regk_bif_slave_dma 0x00000001 -#define regk_bif_slave_hi 0x00000003 -#define regk_bif_slave_inv 0x00000001 -#define regk_bif_slave_lo 0x00000002 -#define regk_bif_slave_local 0x00000001 -#define regk_bif_slave_master 0x00000000 -#define regk_bif_slave_mode_reg 0x00000001 -#define regk_bif_slave_no 0x00000000 -#define regk_bif_slave_norm 0x00000000 -#define regk_bif_slave_on_access 0x00000000 -#define regk_bif_slave_rw_arb_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 -#define regk_bif_slave_rw_intr_mask_default 0x00000000 -#define regk_bif_slave_rw_slave_cfg_default 0x00000000 -#define regk_bif_slave_shared 0x00000000 -#define regk_bif_slave_slave 0x00000001 -#define regk_bif_slave_t0ns 0x00000003 -#define regk_bif_slave_t10ns 0x00000002 -#define regk_bif_slave_t20ns 0x00000003 -#define regk_bif_slave_t30ns 0x00000002 -#define regk_bif_slave_t40ns 0x00000001 -#define regk_bif_slave_t50ns 0x00000000 -#define regk_bif_slave_yes 0x00000001 -#define regk_bif_slave_z 0x00000004 -#endif /* __bif_slave_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h deleted file mode 100644 index e98476332e1f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h deleted file mode 100644 index 7f768db272e2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef __cris_defs_asm_h -#define __cris_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/crisp/doc/cris.r - * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp - * last modfied: Mon Apr 11 16:06:39 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r - * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gc_cfg, scope cris, type rw */ -#define reg_cris_rw_gc_cfg___ic___lsb 0 -#define reg_cris_rw_gc_cfg___ic___width 1 -#define reg_cris_rw_gc_cfg___ic___bit 0 -#define reg_cris_rw_gc_cfg___dc___lsb 1 -#define reg_cris_rw_gc_cfg___dc___width 1 -#define reg_cris_rw_gc_cfg___dc___bit 1 -#define reg_cris_rw_gc_cfg___im___lsb 2 -#define reg_cris_rw_gc_cfg___im___width 1 -#define reg_cris_rw_gc_cfg___im___bit 2 -#define reg_cris_rw_gc_cfg___dm___lsb 3 -#define reg_cris_rw_gc_cfg___dm___width 1 -#define reg_cris_rw_gc_cfg___dm___bit 3 -#define reg_cris_rw_gc_cfg___gb___lsb 4 -#define reg_cris_rw_gc_cfg___gb___width 1 -#define reg_cris_rw_gc_cfg___gb___bit 4 -#define reg_cris_rw_gc_cfg___gk___lsb 5 -#define reg_cris_rw_gc_cfg___gk___width 1 -#define reg_cris_rw_gc_cfg___gk___bit 5 -#define reg_cris_rw_gc_cfg___gp___lsb 6 -#define reg_cris_rw_gc_cfg___gp___width 1 -#define reg_cris_rw_gc_cfg___gp___bit 6 -#define reg_cris_rw_gc_cfg_offset 0 - -/* Register rw_gc_ccs, scope cris, type rw */ -#define reg_cris_rw_gc_ccs_offset 4 - -/* Register rw_gc_srs, scope cris, type rw */ -#define reg_cris_rw_gc_srs___srs___lsb 0 -#define reg_cris_rw_gc_srs___srs___width 8 -#define reg_cris_rw_gc_srs_offset 8 - -/* Register rw_gc_nrp, scope cris, type rw */ -#define reg_cris_rw_gc_nrp_offset 12 - -/* Register rw_gc_exs, scope cris, type rw */ -#define reg_cris_rw_gc_exs_offset 16 - -/* Register rw_gc_eda, scope cris, type rw */ -#define reg_cris_rw_gc_eda_offset 20 - -/* Register rw_gc_r0, scope cris, type rw */ -#define reg_cris_rw_gc_r0_offset 32 - -/* Register rw_gc_r1, scope cris, type rw */ -#define reg_cris_rw_gc_r1_offset 36 - -/* Register rw_gc_r2, scope cris, type rw */ -#define reg_cris_rw_gc_r2_offset 40 - -/* Register rw_gc_r3, scope cris, type rw */ -#define reg_cris_rw_gc_r3_offset 44 - - -/* Constants */ -#define regk_cris_no 0x00000000 -#define regk_cris_rw_gc_cfg_default 0x00000000 -#define regk_cris_yes 0x00000001 -#endif /* __cris_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h deleted file mode 100644 index 7d3689a6f80d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h +++ /dev/null @@ -1,10 +0,0 @@ -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_EDA 5 -#define RW_GC_R0 8 -#define RW_GC_R1 9 -#define RW_GC_R2 10 -#define RW_GC_R3 11 diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h deleted file mode 100644 index 0cb71bc127ae..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h +++ /dev/null @@ -1,368 +0,0 @@ -#ifndef __dma_defs_asm_h -#define __dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope dma, type rw */ -#define reg_dma_rw_data_offset 0 - -/* Register rw_data_next, scope dma, type rw */ -#define reg_dma_rw_data_next_offset 4 - -/* Register rw_data_buf, scope dma, type rw */ -#define reg_dma_rw_data_buf_offset 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -#define reg_dma_rw_data_ctrl___eol___lsb 0 -#define reg_dma_rw_data_ctrl___eol___width 1 -#define reg_dma_rw_data_ctrl___eol___bit 0 -#define reg_dma_rw_data_ctrl___out_eop___lsb 3 -#define reg_dma_rw_data_ctrl___out_eop___width 1 -#define reg_dma_rw_data_ctrl___out_eop___bit 3 -#define reg_dma_rw_data_ctrl___intr___lsb 4 -#define reg_dma_rw_data_ctrl___intr___width 1 -#define reg_dma_rw_data_ctrl___intr___bit 4 -#define reg_dma_rw_data_ctrl___wait___lsb 5 -#define reg_dma_rw_data_ctrl___wait___width 1 -#define reg_dma_rw_data_ctrl___wait___bit 5 -#define reg_dma_rw_data_ctrl_offset 12 - -/* Register rw_data_stat, scope dma, type rw */ -#define reg_dma_rw_data_stat___in_eop___lsb 3 -#define reg_dma_rw_data_stat___in_eop___width 1 -#define reg_dma_rw_data_stat___in_eop___bit 3 -#define reg_dma_rw_data_stat_offset 16 - -/* Register rw_data_md, scope dma, type rw */ -#define reg_dma_rw_data_md___md___lsb 0 -#define reg_dma_rw_data_md___md___width 16 -#define reg_dma_rw_data_md_offset 20 - -/* Register rw_data_md_s, scope dma, type rw */ -#define reg_dma_rw_data_md_s___md_s___lsb 0 -#define reg_dma_rw_data_md_s___md_s___width 16 -#define reg_dma_rw_data_md_s_offset 24 - -/* Register rw_data_after, scope dma, type rw */ -#define reg_dma_rw_data_after_offset 28 - -/* Register rw_ctxt, scope dma, type rw */ -#define reg_dma_rw_ctxt_offset 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -#define reg_dma_rw_ctxt_next_offset 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 -#define reg_dma_rw_ctxt_ctrl___eol___width 1 -#define reg_dma_rw_ctxt_ctrl___eol___bit 0 -#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 -#define reg_dma_rw_ctxt_ctrl___intr___width 1 -#define reg_dma_rw_ctxt_ctrl___intr___bit 4 -#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 -#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 -#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 -#define reg_dma_rw_ctxt_ctrl___en___lsb 7 -#define reg_dma_rw_ctxt_ctrl___en___width 1 -#define reg_dma_rw_ctxt_ctrl___en___bit 7 -#define reg_dma_rw_ctxt_ctrl_offset 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -#define reg_dma_rw_ctxt_stat___dis___lsb 7 -#define reg_dma_rw_ctxt_stat___dis___width 1 -#define reg_dma_rw_ctxt_stat___dis___bit 7 -#define reg_dma_rw_ctxt_stat_offset 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0___md0___lsb 0 -#define reg_dma_rw_ctxt_md0___md0___width 16 -#define reg_dma_rw_ctxt_md0_offset 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 -#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 -#define reg_dma_rw_ctxt_md0_s_offset 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_offset 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_s_offset 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_offset 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_s_offset 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_offset 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_s_offset 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_offset 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_s_offset 84 - -/* Register rw_saved_data, scope dma, type rw */ -#define reg_dma_rw_saved_data_offset 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -#define reg_dma_rw_saved_data_buf_offset 92 - -/* Register rw_group, scope dma, type rw */ -#define reg_dma_rw_group_offset 96 - -/* Register rw_group_next, scope dma, type rw */ -#define reg_dma_rw_group_next_offset 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -#define reg_dma_rw_group_ctrl___eol___lsb 0 -#define reg_dma_rw_group_ctrl___eol___width 1 -#define reg_dma_rw_group_ctrl___eol___bit 0 -#define reg_dma_rw_group_ctrl___tol___lsb 1 -#define reg_dma_rw_group_ctrl___tol___width 1 -#define reg_dma_rw_group_ctrl___tol___bit 1 -#define reg_dma_rw_group_ctrl___bol___lsb 2 -#define reg_dma_rw_group_ctrl___bol___width 1 -#define reg_dma_rw_group_ctrl___bol___bit 2 -#define reg_dma_rw_group_ctrl___intr___lsb 4 -#define reg_dma_rw_group_ctrl___intr___width 1 -#define reg_dma_rw_group_ctrl___intr___bit 4 -#define reg_dma_rw_group_ctrl___en___lsb 7 -#define reg_dma_rw_group_ctrl___en___width 1 -#define reg_dma_rw_group_ctrl___en___bit 7 -#define reg_dma_rw_group_ctrl_offset 104 - -/* Register rw_group_stat, scope dma, type rw */ -#define reg_dma_rw_group_stat___dis___lsb 7 -#define reg_dma_rw_group_stat___dis___width 1 -#define reg_dma_rw_group_stat___dis___bit 7 -#define reg_dma_rw_group_stat_offset 108 - -/* Register rw_group_md, scope dma, type rw */ -#define reg_dma_rw_group_md___md___lsb 0 -#define reg_dma_rw_group_md___md___width 16 -#define reg_dma_rw_group_md_offset 112 - -/* Register rw_group_md_s, scope dma, type rw */ -#define reg_dma_rw_group_md_s___md_s___lsb 0 -#define reg_dma_rw_group_md_s___md_s___width 16 -#define reg_dma_rw_group_md_s_offset 116 - -/* Register rw_group_up, scope dma, type rw */ -#define reg_dma_rw_group_up_offset 120 - -/* Register rw_group_down, scope dma, type rw */ -#define reg_dma_rw_group_down_offset 124 - -/* Register rw_cmd, scope dma, type rw */ -#define reg_dma_rw_cmd___cont_data___lsb 0 -#define reg_dma_rw_cmd___cont_data___width 1 -#define reg_dma_rw_cmd___cont_data___bit 0 -#define reg_dma_rw_cmd_offset 128 - -/* Register rw_cfg, scope dma, type rw */ -#define reg_dma_rw_cfg___en___lsb 0 -#define reg_dma_rw_cfg___en___width 1 -#define reg_dma_rw_cfg___en___bit 0 -#define reg_dma_rw_cfg___stop___lsb 1 -#define reg_dma_rw_cfg___stop___width 1 -#define reg_dma_rw_cfg___stop___bit 1 -#define reg_dma_rw_cfg_offset 132 - -/* Register rw_stat, scope dma, type rw */ -#define reg_dma_rw_stat___mode___lsb 0 -#define reg_dma_rw_stat___mode___width 5 -#define reg_dma_rw_stat___list_state___lsb 5 -#define reg_dma_rw_stat___list_state___width 3 -#define reg_dma_rw_stat___stream_cmd_src___lsb 8 -#define reg_dma_rw_stat___stream_cmd_src___width 8 -#define reg_dma_rw_stat___buf___lsb 24 -#define reg_dma_rw_stat___buf___width 8 -#define reg_dma_rw_stat_offset 136 - -/* Register rw_intr_mask, scope dma, type rw */ -#define reg_dma_rw_intr_mask___group___lsb 0 -#define reg_dma_rw_intr_mask___group___width 1 -#define reg_dma_rw_intr_mask___group___bit 0 -#define reg_dma_rw_intr_mask___ctxt___lsb 1 -#define reg_dma_rw_intr_mask___ctxt___width 1 -#define reg_dma_rw_intr_mask___ctxt___bit 1 -#define reg_dma_rw_intr_mask___data___lsb 2 -#define reg_dma_rw_intr_mask___data___width 1 -#define reg_dma_rw_intr_mask___data___bit 2 -#define reg_dma_rw_intr_mask___in_eop___lsb 3 -#define reg_dma_rw_intr_mask___in_eop___width 1 -#define reg_dma_rw_intr_mask___in_eop___bit 3 -#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 -#define reg_dma_rw_intr_mask___stream_cmd___width 1 -#define reg_dma_rw_intr_mask___stream_cmd___bit 4 -#define reg_dma_rw_intr_mask_offset 140 - -/* Register rw_ack_intr, scope dma, type rw */ -#define reg_dma_rw_ack_intr___group___lsb 0 -#define reg_dma_rw_ack_intr___group___width 1 -#define reg_dma_rw_ack_intr___group___bit 0 -#define reg_dma_rw_ack_intr___ctxt___lsb 1 -#define reg_dma_rw_ack_intr___ctxt___width 1 -#define reg_dma_rw_ack_intr___ctxt___bit 1 -#define reg_dma_rw_ack_intr___data___lsb 2 -#define reg_dma_rw_ack_intr___data___width 1 -#define reg_dma_rw_ack_intr___data___bit 2 -#define reg_dma_rw_ack_intr___in_eop___lsb 3 -#define reg_dma_rw_ack_intr___in_eop___width 1 -#define reg_dma_rw_ack_intr___in_eop___bit 3 -#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 -#define reg_dma_rw_ack_intr___stream_cmd___width 1 -#define reg_dma_rw_ack_intr___stream_cmd___bit 4 -#define reg_dma_rw_ack_intr_offset 144 - -/* Register r_intr, scope dma, type r */ -#define reg_dma_r_intr___group___lsb 0 -#define reg_dma_r_intr___group___width 1 -#define reg_dma_r_intr___group___bit 0 -#define reg_dma_r_intr___ctxt___lsb 1 -#define reg_dma_r_intr___ctxt___width 1 -#define reg_dma_r_intr___ctxt___bit 1 -#define reg_dma_r_intr___data___lsb 2 -#define reg_dma_r_intr___data___width 1 -#define reg_dma_r_intr___data___bit 2 -#define reg_dma_r_intr___in_eop___lsb 3 -#define reg_dma_r_intr___in_eop___width 1 -#define reg_dma_r_intr___in_eop___bit 3 -#define reg_dma_r_intr___stream_cmd___lsb 4 -#define reg_dma_r_intr___stream_cmd___width 1 -#define reg_dma_r_intr___stream_cmd___bit 4 -#define reg_dma_r_intr_offset 148 - -/* Register r_masked_intr, scope dma, type r */ -#define reg_dma_r_masked_intr___group___lsb 0 -#define reg_dma_r_masked_intr___group___width 1 -#define reg_dma_r_masked_intr___group___bit 0 -#define reg_dma_r_masked_intr___ctxt___lsb 1 -#define reg_dma_r_masked_intr___ctxt___width 1 -#define reg_dma_r_masked_intr___ctxt___bit 1 -#define reg_dma_r_masked_intr___data___lsb 2 -#define reg_dma_r_masked_intr___data___width 1 -#define reg_dma_r_masked_intr___data___bit 2 -#define reg_dma_r_masked_intr___in_eop___lsb 3 -#define reg_dma_r_masked_intr___in_eop___width 1 -#define reg_dma_r_masked_intr___in_eop___bit 3 -#define reg_dma_r_masked_intr___stream_cmd___lsb 4 -#define reg_dma_r_masked_intr___stream_cmd___width 1 -#define reg_dma_r_masked_intr___stream_cmd___bit 4 -#define reg_dma_r_masked_intr_offset 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -#define reg_dma_rw_stream_cmd___cmd___lsb 0 -#define reg_dma_rw_stream_cmd___cmd___width 10 -#define reg_dma_rw_stream_cmd___n___lsb 16 -#define reg_dma_rw_stream_cmd___n___width 8 -#define reg_dma_rw_stream_cmd___busy___lsb 31 -#define reg_dma_rw_stream_cmd___busy___width 1 -#define reg_dma_rw_stream_cmd___busy___bit 31 -#define reg_dma_rw_stream_cmd_offset 156 - - -/* Constants */ -#define regk_dma_ack_pkt 0x00000100 -#define regk_dma_anytime 0x00000001 -#define regk_dma_array 0x00000008 -#define regk_dma_burst 0x00000020 -#define regk_dma_client 0x00000002 -#define regk_dma_copy_next 0x00000010 -#define regk_dma_copy_up 0x00000020 -#define regk_dma_data_at_eol 0x00000001 -#define regk_dma_dis_c 0x00000010 -#define regk_dma_dis_g 0x00000020 -#define regk_dma_idle 0x00000001 -#define regk_dma_intern 0x00000004 -#define regk_dma_load_c 0x00000200 -#define regk_dma_load_c_n 0x00000280 -#define regk_dma_load_c_next 0x00000240 -#define regk_dma_load_d 0x00000140 -#define regk_dma_load_g 0x00000300 -#define regk_dma_load_g_down 0x000003c0 -#define regk_dma_load_g_next 0x00000340 -#define regk_dma_load_g_up 0x00000380 -#define regk_dma_next_en 0x00000010 -#define regk_dma_next_pkt 0x00000010 -#define regk_dma_no 0x00000000 -#define regk_dma_only_at_wait 0x00000000 -#define regk_dma_restore 0x00000020 -#define regk_dma_rst 0x00000001 -#define regk_dma_running 0x00000004 -#define regk_dma_rw_cfg_default 0x00000000 -#define regk_dma_rw_cmd_default 0x00000000 -#define regk_dma_rw_intr_mask_default 0x00000000 -#define regk_dma_rw_stat_default 0x00000101 -#define regk_dma_rw_stream_cmd_default 0x00000000 -#define regk_dma_save_down 0x00000020 -#define regk_dma_save_up 0x00000020 -#define regk_dma_set_reg 0x00000050 -#define regk_dma_set_w_size1 0x00000190 -#define regk_dma_set_w_size2 0x000001a0 -#define regk_dma_set_w_size4 0x000001c0 -#define regk_dma_stopped 0x00000002 -#define regk_dma_store_c 0x00000002 -#define regk_dma_store_descr 0x00000000 -#define regk_dma_store_g 0x00000004 -#define regk_dma_store_md 0x00000001 -#define regk_dma_sw 0x00000008 -#define regk_dma_update_down 0x00000020 -#define regk_dma_yes 0x00000001 -#endif /* __dma_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h deleted file mode 100644 index c9f49864831b..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h +++ /dev/null @@ -1,498 +0,0 @@ -#ifndef __eth_defs_asm_h -#define __eth_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/eth/rtl/eth_regs.r - * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp - * last modfied: Mon Apr 11 16:07:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r - * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ma0_lo, scope eth, type rw */ -#define reg_eth_rw_ma0_lo___addr___lsb 0 -#define reg_eth_rw_ma0_lo___addr___width 32 -#define reg_eth_rw_ma0_lo_offset 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -#define reg_eth_rw_ma0_hi___addr___lsb 0 -#define reg_eth_rw_ma0_hi___addr___width 16 -#define reg_eth_rw_ma0_hi_offset 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -#define reg_eth_rw_ma1_lo___addr___lsb 0 -#define reg_eth_rw_ma1_lo___addr___width 32 -#define reg_eth_rw_ma1_lo_offset 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -#define reg_eth_rw_ma1_hi___addr___lsb 0 -#define reg_eth_rw_ma1_hi___addr___width 16 -#define reg_eth_rw_ma1_hi_offset 12 - -/* Register rw_ga_lo, scope eth, type rw */ -#define reg_eth_rw_ga_lo___table___lsb 0 -#define reg_eth_rw_ga_lo___table___width 32 -#define reg_eth_rw_ga_lo_offset 16 - -/* Register rw_ga_hi, scope eth, type rw */ -#define reg_eth_rw_ga_hi___table___lsb 0 -#define reg_eth_rw_ga_hi___table___width 32 -#define reg_eth_rw_ga_hi_offset 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -#define reg_eth_rw_gen_ctrl___en___lsb 0 -#define reg_eth_rw_gen_ctrl___en___width 1 -#define reg_eth_rw_gen_ctrl___en___bit 0 -#define reg_eth_rw_gen_ctrl___phy___lsb 1 -#define reg_eth_rw_gen_ctrl___phy___width 2 -#define reg_eth_rw_gen_ctrl___protocol___lsb 3 -#define reg_eth_rw_gen_ctrl___protocol___width 1 -#define reg_eth_rw_gen_ctrl___protocol___bit 3 -#define reg_eth_rw_gen_ctrl___loopback___lsb 4 -#define reg_eth_rw_gen_ctrl___loopback___width 1 -#define reg_eth_rw_gen_ctrl___loopback___bit 4 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 -#define reg_eth_rw_gen_ctrl_offset 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -#define reg_eth_rw_rec_ctrl___ma0___lsb 0 -#define reg_eth_rw_rec_ctrl___ma0___width 1 -#define reg_eth_rw_rec_ctrl___ma0___bit 0 -#define reg_eth_rw_rec_ctrl___ma1___lsb 1 -#define reg_eth_rw_rec_ctrl___ma1___width 1 -#define reg_eth_rw_rec_ctrl___ma1___bit 1 -#define reg_eth_rw_rec_ctrl___individual___lsb 2 -#define reg_eth_rw_rec_ctrl___individual___width 1 -#define reg_eth_rw_rec_ctrl___individual___bit 2 -#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 -#define reg_eth_rw_rec_ctrl___broadcast___width 1 -#define reg_eth_rw_rec_ctrl___broadcast___bit 3 -#define reg_eth_rw_rec_ctrl___undersize___lsb 4 -#define reg_eth_rw_rec_ctrl___undersize___width 1 -#define reg_eth_rw_rec_ctrl___undersize___bit 4 -#define reg_eth_rw_rec_ctrl___oversize___lsb 5 -#define reg_eth_rw_rec_ctrl___oversize___width 1 -#define reg_eth_rw_rec_ctrl___oversize___bit 5 -#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 -#define reg_eth_rw_rec_ctrl___bad_crc___width 1 -#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 -#define reg_eth_rw_rec_ctrl___duplex___lsb 7 -#define reg_eth_rw_rec_ctrl___duplex___width 1 -#define reg_eth_rw_rec_ctrl___duplex___bit 7 -#define reg_eth_rw_rec_ctrl___max_size___lsb 8 -#define reg_eth_rw_rec_ctrl___max_size___width 1 -#define reg_eth_rw_rec_ctrl___max_size___bit 8 -#define reg_eth_rw_rec_ctrl_offset 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -#define reg_eth_rw_tr_ctrl___crc___lsb 0 -#define reg_eth_rw_tr_ctrl___crc___width 1 -#define reg_eth_rw_tr_ctrl___crc___bit 0 -#define reg_eth_rw_tr_ctrl___pad___lsb 1 -#define reg_eth_rw_tr_ctrl___pad___width 1 -#define reg_eth_rw_tr_ctrl___pad___bit 1 -#define reg_eth_rw_tr_ctrl___retry___lsb 2 -#define reg_eth_rw_tr_ctrl___retry___width 1 -#define reg_eth_rw_tr_ctrl___retry___bit 2 -#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 -#define reg_eth_rw_tr_ctrl___ignore_col___width 1 -#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 -#define reg_eth_rw_tr_ctrl___cancel___lsb 4 -#define reg_eth_rw_tr_ctrl___cancel___width 1 -#define reg_eth_rw_tr_ctrl___cancel___bit 4 -#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 -#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 -#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 -#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 -#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 -#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 -#define reg_eth_rw_tr_ctrl_offset 32 - -/* Register rw_clr_err, scope eth, type rw */ -#define reg_eth_rw_clr_err___clr___lsb 0 -#define reg_eth_rw_clr_err___clr___width 1 -#define reg_eth_rw_clr_err___clr___bit 0 -#define reg_eth_rw_clr_err_offset 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 -#define reg_eth_rw_mgm_ctrl___mdio___width 1 -#define reg_eth_rw_mgm_ctrl___mdio___bit 0 -#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 -#define reg_eth_rw_mgm_ctrl___mdoe___width 1 -#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 -#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 -#define reg_eth_rw_mgm_ctrl___mdc___width 1 -#define reg_eth_rw_mgm_ctrl___mdc___bit 2 -#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 -#define reg_eth_rw_mgm_ctrl___phyclk___width 1 -#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 -#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 -#define reg_eth_rw_mgm_ctrl___txdata___width 4 -#define reg_eth_rw_mgm_ctrl___txen___lsb 8 -#define reg_eth_rw_mgm_ctrl___txen___width 1 -#define reg_eth_rw_mgm_ctrl___txen___bit 8 -#define reg_eth_rw_mgm_ctrl_offset 40 - -/* Register r_stat, scope eth, type r */ -#define reg_eth_r_stat___mdio___lsb 0 -#define reg_eth_r_stat___mdio___width 1 -#define reg_eth_r_stat___mdio___bit 0 -#define reg_eth_r_stat___exc_col___lsb 1 -#define reg_eth_r_stat___exc_col___width 1 -#define reg_eth_r_stat___exc_col___bit 1 -#define reg_eth_r_stat___urun___lsb 2 -#define reg_eth_r_stat___urun___width 1 -#define reg_eth_r_stat___urun___bit 2 -#define reg_eth_r_stat___phyclk___lsb 3 -#define reg_eth_r_stat___phyclk___width 1 -#define reg_eth_r_stat___phyclk___bit 3 -#define reg_eth_r_stat___txdata___lsb 4 -#define reg_eth_r_stat___txdata___width 4 -#define reg_eth_r_stat___txen___lsb 8 -#define reg_eth_r_stat___txen___width 1 -#define reg_eth_r_stat___txen___bit 8 -#define reg_eth_r_stat___col___lsb 9 -#define reg_eth_r_stat___col___width 1 -#define reg_eth_r_stat___col___bit 9 -#define reg_eth_r_stat___crs___lsb 10 -#define reg_eth_r_stat___crs___width 1 -#define reg_eth_r_stat___crs___bit 10 -#define reg_eth_r_stat___txclk___lsb 11 -#define reg_eth_r_stat___txclk___width 1 -#define reg_eth_r_stat___txclk___bit 11 -#define reg_eth_r_stat___rxdata___lsb 12 -#define reg_eth_r_stat___rxdata___width 4 -#define reg_eth_r_stat___rxer___lsb 16 -#define reg_eth_r_stat___rxer___width 1 -#define reg_eth_r_stat___rxer___bit 16 -#define reg_eth_r_stat___rxdv___lsb 17 -#define reg_eth_r_stat___rxdv___width 1 -#define reg_eth_r_stat___rxdv___bit 17 -#define reg_eth_r_stat___rxclk___lsb 18 -#define reg_eth_r_stat___rxclk___width 1 -#define reg_eth_r_stat___rxclk___bit 18 -#define reg_eth_r_stat_offset 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -#define reg_eth_rs_rec_cnt___crc_err___lsb 0 -#define reg_eth_rs_rec_cnt___crc_err___width 8 -#define reg_eth_rs_rec_cnt___align_err___lsb 8 -#define reg_eth_rs_rec_cnt___align_err___width 8 -#define reg_eth_rs_rec_cnt___oversize___lsb 16 -#define reg_eth_rs_rec_cnt___oversize___width 8 -#define reg_eth_rs_rec_cnt___congestion___lsb 24 -#define reg_eth_rs_rec_cnt___congestion___width 8 -#define reg_eth_rs_rec_cnt_offset 48 - -/* Register r_rec_cnt, scope eth, type r */ -#define reg_eth_r_rec_cnt___crc_err___lsb 0 -#define reg_eth_r_rec_cnt___crc_err___width 8 -#define reg_eth_r_rec_cnt___align_err___lsb 8 -#define reg_eth_r_rec_cnt___align_err___width 8 -#define reg_eth_r_rec_cnt___oversize___lsb 16 -#define reg_eth_r_rec_cnt___oversize___width 8 -#define reg_eth_r_rec_cnt___congestion___lsb 24 -#define reg_eth_r_rec_cnt___congestion___width 8 -#define reg_eth_r_rec_cnt_offset 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -#define reg_eth_rs_tr_cnt___single_col___lsb 0 -#define reg_eth_rs_tr_cnt___single_col___width 8 -#define reg_eth_rs_tr_cnt___mult_col___lsb 8 -#define reg_eth_rs_tr_cnt___mult_col___width 8 -#define reg_eth_rs_tr_cnt___late_col___lsb 16 -#define reg_eth_rs_tr_cnt___late_col___width 8 -#define reg_eth_rs_tr_cnt___deferred___lsb 24 -#define reg_eth_rs_tr_cnt___deferred___width 8 -#define reg_eth_rs_tr_cnt_offset 56 - -/* Register r_tr_cnt, scope eth, type r */ -#define reg_eth_r_tr_cnt___single_col___lsb 0 -#define reg_eth_r_tr_cnt___single_col___width 8 -#define reg_eth_r_tr_cnt___mult_col___lsb 8 -#define reg_eth_r_tr_cnt___mult_col___width 8 -#define reg_eth_r_tr_cnt___late_col___lsb 16 -#define reg_eth_r_tr_cnt___late_col___width 8 -#define reg_eth_r_tr_cnt___deferred___lsb 24 -#define reg_eth_r_tr_cnt___deferred___width 8 -#define reg_eth_r_tr_cnt_offset 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_rs_phy_cnt___carrier_loss___width 8 -#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 -#define reg_eth_rs_phy_cnt___sqe_err___width 8 -#define reg_eth_rs_phy_cnt_offset 64 - -/* Register r_phy_cnt, scope eth, type r */ -#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_r_phy_cnt___carrier_loss___width 8 -#define reg_eth_r_phy_cnt___sqe_err___lsb 8 -#define reg_eth_r_phy_cnt___sqe_err___width 8 -#define reg_eth_r_phy_cnt_offset 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 -#define reg_eth_rw_test_ctrl___snmp_inc___width 1 -#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 -#define reg_eth_rw_test_ctrl___snmp___lsb 1 -#define reg_eth_rw_test_ctrl___snmp___width 1 -#define reg_eth_rw_test_ctrl___snmp___bit 1 -#define reg_eth_rw_test_ctrl___backoff___lsb 2 -#define reg_eth_rw_test_ctrl___backoff___width 1 -#define reg_eth_rw_test_ctrl___backoff___bit 2 -#define reg_eth_rw_test_ctrl_offset 72 - -/* Register rw_intr_mask, scope eth, type rw */ -#define reg_eth_rw_intr_mask___crc___lsb 0 -#define reg_eth_rw_intr_mask___crc___width 1 -#define reg_eth_rw_intr_mask___crc___bit 0 -#define reg_eth_rw_intr_mask___align___lsb 1 -#define reg_eth_rw_intr_mask___align___width 1 -#define reg_eth_rw_intr_mask___align___bit 1 -#define reg_eth_rw_intr_mask___oversize___lsb 2 -#define reg_eth_rw_intr_mask___oversize___width 1 -#define reg_eth_rw_intr_mask___oversize___bit 2 -#define reg_eth_rw_intr_mask___congestion___lsb 3 -#define reg_eth_rw_intr_mask___congestion___width 1 -#define reg_eth_rw_intr_mask___congestion___bit 3 -#define reg_eth_rw_intr_mask___single_col___lsb 4 -#define reg_eth_rw_intr_mask___single_col___width 1 -#define reg_eth_rw_intr_mask___single_col___bit 4 -#define reg_eth_rw_intr_mask___mult_col___lsb 5 -#define reg_eth_rw_intr_mask___mult_col___width 1 -#define reg_eth_rw_intr_mask___mult_col___bit 5 -#define reg_eth_rw_intr_mask___late_col___lsb 6 -#define reg_eth_rw_intr_mask___late_col___width 1 -#define reg_eth_rw_intr_mask___late_col___bit 6 -#define reg_eth_rw_intr_mask___deferred___lsb 7 -#define reg_eth_rw_intr_mask___deferred___width 1 -#define reg_eth_rw_intr_mask___deferred___bit 7 -#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 -#define reg_eth_rw_intr_mask___carrier_loss___width 1 -#define reg_eth_rw_intr_mask___carrier_loss___bit 8 -#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 -#define reg_eth_rw_intr_mask___sqe_test_err___width 1 -#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 -#define reg_eth_rw_intr_mask___orun___lsb 10 -#define reg_eth_rw_intr_mask___orun___width 1 -#define reg_eth_rw_intr_mask___orun___bit 10 -#define reg_eth_rw_intr_mask___urun___lsb 11 -#define reg_eth_rw_intr_mask___urun___width 1 -#define reg_eth_rw_intr_mask___urun___bit 11 -#define reg_eth_rw_intr_mask___excessive_col___lsb 12 -#define reg_eth_rw_intr_mask___excessive_col___width 1 -#define reg_eth_rw_intr_mask___excessive_col___bit 12 -#define reg_eth_rw_intr_mask___mdio___lsb 13 -#define reg_eth_rw_intr_mask___mdio___width 1 -#define reg_eth_rw_intr_mask___mdio___bit 13 -#define reg_eth_rw_intr_mask_offset 76 - -/* Register rw_ack_intr, scope eth, type rw */ -#define reg_eth_rw_ack_intr___crc___lsb 0 -#define reg_eth_rw_ack_intr___crc___width 1 -#define reg_eth_rw_ack_intr___crc___bit 0 -#define reg_eth_rw_ack_intr___align___lsb 1 -#define reg_eth_rw_ack_intr___align___width 1 -#define reg_eth_rw_ack_intr___align___bit 1 -#define reg_eth_rw_ack_intr___oversize___lsb 2 -#define reg_eth_rw_ack_intr___oversize___width 1 -#define reg_eth_rw_ack_intr___oversize___bit 2 -#define reg_eth_rw_ack_intr___congestion___lsb 3 -#define reg_eth_rw_ack_intr___congestion___width 1 -#define reg_eth_rw_ack_intr___congestion___bit 3 -#define reg_eth_rw_ack_intr___single_col___lsb 4 -#define reg_eth_rw_ack_intr___single_col___width 1 -#define reg_eth_rw_ack_intr___single_col___bit 4 -#define reg_eth_rw_ack_intr___mult_col___lsb 5 -#define reg_eth_rw_ack_intr___mult_col___width 1 -#define reg_eth_rw_ack_intr___mult_col___bit 5 -#define reg_eth_rw_ack_intr___late_col___lsb 6 -#define reg_eth_rw_ack_intr___late_col___width 1 -#define reg_eth_rw_ack_intr___late_col___bit 6 -#define reg_eth_rw_ack_intr___deferred___lsb 7 -#define reg_eth_rw_ack_intr___deferred___width 1 -#define reg_eth_rw_ack_intr___deferred___bit 7 -#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 -#define reg_eth_rw_ack_intr___carrier_loss___width 1 -#define reg_eth_rw_ack_intr___carrier_loss___bit 8 -#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 -#define reg_eth_rw_ack_intr___sqe_test_err___width 1 -#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 -#define reg_eth_rw_ack_intr___orun___lsb 10 -#define reg_eth_rw_ack_intr___orun___width 1 -#define reg_eth_rw_ack_intr___orun___bit 10 -#define reg_eth_rw_ack_intr___urun___lsb 11 -#define reg_eth_rw_ack_intr___urun___width 1 -#define reg_eth_rw_ack_intr___urun___bit 11 -#define reg_eth_rw_ack_intr___excessive_col___lsb 12 -#define reg_eth_rw_ack_intr___excessive_col___width 1 -#define reg_eth_rw_ack_intr___excessive_col___bit 12 -#define reg_eth_rw_ack_intr___mdio___lsb 13 -#define reg_eth_rw_ack_intr___mdio___width 1 -#define reg_eth_rw_ack_intr___mdio___bit 13 -#define reg_eth_rw_ack_intr_offset 80 - -/* Register r_intr, scope eth, type r */ -#define reg_eth_r_intr___crc___lsb 0 -#define reg_eth_r_intr___crc___width 1 -#define reg_eth_r_intr___crc___bit 0 -#define reg_eth_r_intr___align___lsb 1 -#define reg_eth_r_intr___align___width 1 -#define reg_eth_r_intr___align___bit 1 -#define reg_eth_r_intr___oversize___lsb 2 -#define reg_eth_r_intr___oversize___width 1 -#define reg_eth_r_intr___oversize___bit 2 -#define reg_eth_r_intr___congestion___lsb 3 -#define reg_eth_r_intr___congestion___width 1 -#define reg_eth_r_intr___congestion___bit 3 -#define reg_eth_r_intr___single_col___lsb 4 -#define reg_eth_r_intr___single_col___width 1 -#define reg_eth_r_intr___single_col___bit 4 -#define reg_eth_r_intr___mult_col___lsb 5 -#define reg_eth_r_intr___mult_col___width 1 -#define reg_eth_r_intr___mult_col___bit 5 -#define reg_eth_r_intr___late_col___lsb 6 -#define reg_eth_r_intr___late_col___width 1 -#define reg_eth_r_intr___late_col___bit 6 -#define reg_eth_r_intr___deferred___lsb 7 -#define reg_eth_r_intr___deferred___width 1 -#define reg_eth_r_intr___deferred___bit 7 -#define reg_eth_r_intr___carrier_loss___lsb 8 -#define reg_eth_r_intr___carrier_loss___width 1 -#define reg_eth_r_intr___carrier_loss___bit 8 -#define reg_eth_r_intr___sqe_test_err___lsb 9 -#define reg_eth_r_intr___sqe_test_err___width 1 -#define reg_eth_r_intr___sqe_test_err___bit 9 -#define reg_eth_r_intr___orun___lsb 10 -#define reg_eth_r_intr___orun___width 1 -#define reg_eth_r_intr___orun___bit 10 -#define reg_eth_r_intr___urun___lsb 11 -#define reg_eth_r_intr___urun___width 1 -#define reg_eth_r_intr___urun___bit 11 -#define reg_eth_r_intr___excessive_col___lsb 12 -#define reg_eth_r_intr___excessive_col___width 1 -#define reg_eth_r_intr___excessive_col___bit 12 -#define reg_eth_r_intr___mdio___lsb 13 -#define reg_eth_r_intr___mdio___width 1 -#define reg_eth_r_intr___mdio___bit 13 -#define reg_eth_r_intr_offset 84 - -/* Register r_masked_intr, scope eth, type r */ -#define reg_eth_r_masked_intr___crc___lsb 0 -#define reg_eth_r_masked_intr___crc___width 1 -#define reg_eth_r_masked_intr___crc___bit 0 -#define reg_eth_r_masked_intr___align___lsb 1 -#define reg_eth_r_masked_intr___align___width 1 -#define reg_eth_r_masked_intr___align___bit 1 -#define reg_eth_r_masked_intr___oversize___lsb 2 -#define reg_eth_r_masked_intr___oversize___width 1 -#define reg_eth_r_masked_intr___oversize___bit 2 -#define reg_eth_r_masked_intr___congestion___lsb 3 -#define reg_eth_r_masked_intr___congestion___width 1 -#define reg_eth_r_masked_intr___congestion___bit 3 -#define reg_eth_r_masked_intr___single_col___lsb 4 -#define reg_eth_r_masked_intr___single_col___width 1 -#define reg_eth_r_masked_intr___single_col___bit 4 -#define reg_eth_r_masked_intr___mult_col___lsb 5 -#define reg_eth_r_masked_intr___mult_col___width 1 -#define reg_eth_r_masked_intr___mult_col___bit 5 -#define reg_eth_r_masked_intr___late_col___lsb 6 -#define reg_eth_r_masked_intr___late_col___width 1 -#define reg_eth_r_masked_intr___late_col___bit 6 -#define reg_eth_r_masked_intr___deferred___lsb 7 -#define reg_eth_r_masked_intr___deferred___width 1 -#define reg_eth_r_masked_intr___deferred___bit 7 -#define reg_eth_r_masked_intr___carrier_loss___lsb 8 -#define reg_eth_r_masked_intr___carrier_loss___width 1 -#define reg_eth_r_masked_intr___carrier_loss___bit 8 -#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 -#define reg_eth_r_masked_intr___sqe_test_err___width 1 -#define reg_eth_r_masked_intr___sqe_test_err___bit 9 -#define reg_eth_r_masked_intr___orun___lsb 10 -#define reg_eth_r_masked_intr___orun___width 1 -#define reg_eth_r_masked_intr___orun___bit 10 -#define reg_eth_r_masked_intr___urun___lsb 11 -#define reg_eth_r_masked_intr___urun___width 1 -#define reg_eth_r_masked_intr___urun___bit 11 -#define reg_eth_r_masked_intr___excessive_col___lsb 12 -#define reg_eth_r_masked_intr___excessive_col___width 1 -#define reg_eth_r_masked_intr___excessive_col___bit 12 -#define reg_eth_r_masked_intr___mdio___lsb 13 -#define reg_eth_r_masked_intr___mdio___width 1 -#define reg_eth_r_masked_intr___mdio___bit 13 -#define reg_eth_r_masked_intr_offset 88 - - -/* Constants */ -#define regk_eth_discard 0x00000000 -#define regk_eth_ether 0x00000000 -#define regk_eth_full 0x00000001 -#define regk_eth_half 0x00000000 -#define regk_eth_hsh 0x00000001 -#define regk_eth_mii 0x00000001 -#define regk_eth_mii_clk 0x00000000 -#define regk_eth_mii_rec 0x00000002 -#define regk_eth_no 0x00000000 -#define regk_eth_rec 0x00000001 -#define regk_eth_rw_ga_hi_default 0x00000000 -#define regk_eth_rw_ga_lo_default 0x00000000 -#define regk_eth_rw_gen_ctrl_default 0x00000000 -#define regk_eth_rw_intr_mask_default 0x00000000 -#define regk_eth_rw_ma0_hi_default 0x00000000 -#define regk_eth_rw_ma0_lo_default 0x00000000 -#define regk_eth_rw_ma1_hi_default 0x00000000 -#define regk_eth_rw_ma1_lo_default 0x00000000 -#define regk_eth_rw_mgm_ctrl_default 0x00000000 -#define regk_eth_rw_test_ctrl_default 0x00000000 -#define regk_eth_size1518 0x00000000 -#define regk_eth_size1522 0x00000001 -#define regk_eth_yes 0x00000001 -#endif /* __eth_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 35356bc08629..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h deleted file mode 100644 index c8315905c571..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h deleted file mode 100644 index 6df2a433b02d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h +++ /dev/null @@ -1,355 +0,0 @@ -#ifndef __intr_vect_defs_asm_h -#define __intr_vect_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mask, scope intr_vect, type rw */ -#define reg_intr_vect_rw_mask___memarb___lsb 0 -#define reg_intr_vect_rw_mask___memarb___width 1 -#define reg_intr_vect_rw_mask___memarb___bit 0 -#define reg_intr_vect_rw_mask___gen_io___lsb 1 -#define reg_intr_vect_rw_mask___gen_io___width 1 -#define reg_intr_vect_rw_mask___gen_io___bit 1 -#define reg_intr_vect_rw_mask___iop0___lsb 2 -#define reg_intr_vect_rw_mask___iop0___width 1 -#define reg_intr_vect_rw_mask___iop0___bit 2 -#define reg_intr_vect_rw_mask___iop1___lsb 3 -#define reg_intr_vect_rw_mask___iop1___width 1 -#define reg_intr_vect_rw_mask___iop1___bit 3 -#define reg_intr_vect_rw_mask___iop2___lsb 4 -#define reg_intr_vect_rw_mask___iop2___width 1 -#define reg_intr_vect_rw_mask___iop2___bit 4 -#define reg_intr_vect_rw_mask___iop3___lsb 5 -#define reg_intr_vect_rw_mask___iop3___width 1 -#define reg_intr_vect_rw_mask___iop3___bit 5 -#define reg_intr_vect_rw_mask___dma0___lsb 6 -#define reg_intr_vect_rw_mask___dma0___width 1 -#define reg_intr_vect_rw_mask___dma0___bit 6 -#define reg_intr_vect_rw_mask___dma1___lsb 7 -#define reg_intr_vect_rw_mask___dma1___width 1 -#define reg_intr_vect_rw_mask___dma1___bit 7 -#define reg_intr_vect_rw_mask___dma2___lsb 8 -#define reg_intr_vect_rw_mask___dma2___width 1 -#define reg_intr_vect_rw_mask___dma2___bit 8 -#define reg_intr_vect_rw_mask___dma3___lsb 9 -#define reg_intr_vect_rw_mask___dma3___width 1 -#define reg_intr_vect_rw_mask___dma3___bit 9 -#define reg_intr_vect_rw_mask___dma4___lsb 10 -#define reg_intr_vect_rw_mask___dma4___width 1 -#define reg_intr_vect_rw_mask___dma4___bit 10 -#define reg_intr_vect_rw_mask___dma5___lsb 11 -#define reg_intr_vect_rw_mask___dma5___width 1 -#define reg_intr_vect_rw_mask___dma5___bit 11 -#define reg_intr_vect_rw_mask___dma6___lsb 12 -#define reg_intr_vect_rw_mask___dma6___width 1 -#define reg_intr_vect_rw_mask___dma6___bit 12 -#define reg_intr_vect_rw_mask___dma7___lsb 13 -#define reg_intr_vect_rw_mask___dma7___width 1 -#define reg_intr_vect_rw_mask___dma7___bit 13 -#define reg_intr_vect_rw_mask___dma8___lsb 14 -#define reg_intr_vect_rw_mask___dma8___width 1 -#define reg_intr_vect_rw_mask___dma8___bit 14 -#define reg_intr_vect_rw_mask___dma9___lsb 15 -#define reg_intr_vect_rw_mask___dma9___width 1 -#define reg_intr_vect_rw_mask___dma9___bit 15 -#define reg_intr_vect_rw_mask___ata___lsb 16 -#define reg_intr_vect_rw_mask___ata___width 1 -#define reg_intr_vect_rw_mask___ata___bit 16 -#define reg_intr_vect_rw_mask___sser0___lsb 17 -#define reg_intr_vect_rw_mask___sser0___width 1 -#define reg_intr_vect_rw_mask___sser0___bit 17 -#define reg_intr_vect_rw_mask___sser1___lsb 18 -#define reg_intr_vect_rw_mask___sser1___width 1 -#define reg_intr_vect_rw_mask___sser1___bit 18 -#define reg_intr_vect_rw_mask___ser0___lsb 19 -#define reg_intr_vect_rw_mask___ser0___width 1 -#define reg_intr_vect_rw_mask___ser0___bit 19 -#define reg_intr_vect_rw_mask___ser1___lsb 20 -#define reg_intr_vect_rw_mask___ser1___width 1 -#define reg_intr_vect_rw_mask___ser1___bit 20 -#define reg_intr_vect_rw_mask___ser2___lsb 21 -#define reg_intr_vect_rw_mask___ser2___width 1 -#define reg_intr_vect_rw_mask___ser2___bit 21 -#define reg_intr_vect_rw_mask___ser3___lsb 22 -#define reg_intr_vect_rw_mask___ser3___width 1 -#define reg_intr_vect_rw_mask___ser3___bit 22 -#define reg_intr_vect_rw_mask___p21___lsb 23 -#define reg_intr_vect_rw_mask___p21___width 1 -#define reg_intr_vect_rw_mask___p21___bit 23 -#define reg_intr_vect_rw_mask___eth0___lsb 24 -#define reg_intr_vect_rw_mask___eth0___width 1 -#define reg_intr_vect_rw_mask___eth0___bit 24 -#define reg_intr_vect_rw_mask___eth1___lsb 25 -#define reg_intr_vect_rw_mask___eth1___width 1 -#define reg_intr_vect_rw_mask___eth1___bit 25 -#define reg_intr_vect_rw_mask___timer___lsb 26 -#define reg_intr_vect_rw_mask___timer___width 1 -#define reg_intr_vect_rw_mask___timer___bit 26 -#define reg_intr_vect_rw_mask___bif_arb___lsb 27 -#define reg_intr_vect_rw_mask___bif_arb___width 1 -#define reg_intr_vect_rw_mask___bif_arb___bit 27 -#define reg_intr_vect_rw_mask___bif_dma___lsb 28 -#define reg_intr_vect_rw_mask___bif_dma___width 1 -#define reg_intr_vect_rw_mask___bif_dma___bit 28 -#define reg_intr_vect_rw_mask___ext___lsb 29 -#define reg_intr_vect_rw_mask___ext___width 1 -#define reg_intr_vect_rw_mask___ext___bit 29 -#define reg_intr_vect_rw_mask_offset 0 - -/* Register r_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_vect___memarb___lsb 0 -#define reg_intr_vect_r_vect___memarb___width 1 -#define reg_intr_vect_r_vect___memarb___bit 0 -#define reg_intr_vect_r_vect___gen_io___lsb 1 -#define reg_intr_vect_r_vect___gen_io___width 1 -#define reg_intr_vect_r_vect___gen_io___bit 1 -#define reg_intr_vect_r_vect___iop0___lsb 2 -#define reg_intr_vect_r_vect___iop0___width 1 -#define reg_intr_vect_r_vect___iop0___bit 2 -#define reg_intr_vect_r_vect___iop1___lsb 3 -#define reg_intr_vect_r_vect___iop1___width 1 -#define reg_intr_vect_r_vect___iop1___bit 3 -#define reg_intr_vect_r_vect___iop2___lsb 4 -#define reg_intr_vect_r_vect___iop2___width 1 -#define reg_intr_vect_r_vect___iop2___bit 4 -#define reg_intr_vect_r_vect___iop3___lsb 5 -#define reg_intr_vect_r_vect___iop3___width 1 -#define reg_intr_vect_r_vect___iop3___bit 5 -#define reg_intr_vect_r_vect___dma0___lsb 6 -#define reg_intr_vect_r_vect___dma0___width 1 -#define reg_intr_vect_r_vect___dma0___bit 6 -#define reg_intr_vect_r_vect___dma1___lsb 7 -#define reg_intr_vect_r_vect___dma1___width 1 -#define reg_intr_vect_r_vect___dma1___bit 7 -#define reg_intr_vect_r_vect___dma2___lsb 8 -#define reg_intr_vect_r_vect___dma2___width 1 -#define reg_intr_vect_r_vect___dma2___bit 8 -#define reg_intr_vect_r_vect___dma3___lsb 9 -#define reg_intr_vect_r_vect___dma3___width 1 -#define reg_intr_vect_r_vect___dma3___bit 9 -#define reg_intr_vect_r_vect___dma4___lsb 10 -#define reg_intr_vect_r_vect___dma4___width 1 -#define reg_intr_vect_r_vect___dma4___bit 10 -#define reg_intr_vect_r_vect___dma5___lsb 11 -#define reg_intr_vect_r_vect___dma5___width 1 -#define reg_intr_vect_r_vect___dma5___bit 11 -#define reg_intr_vect_r_vect___dma6___lsb 12 -#define reg_intr_vect_r_vect___dma6___width 1 -#define reg_intr_vect_r_vect___dma6___bit 12 -#define reg_intr_vect_r_vect___dma7___lsb 13 -#define reg_intr_vect_r_vect___dma7___width 1 -#define reg_intr_vect_r_vect___dma7___bit 13 -#define reg_intr_vect_r_vect___dma8___lsb 14 -#define reg_intr_vect_r_vect___dma8___width 1 -#define reg_intr_vect_r_vect___dma8___bit 14 -#define reg_intr_vect_r_vect___dma9___lsb 15 -#define reg_intr_vect_r_vect___dma9___width 1 -#define reg_intr_vect_r_vect___dma9___bit 15 -#define reg_intr_vect_r_vect___ata___lsb 16 -#define reg_intr_vect_r_vect___ata___width 1 -#define reg_intr_vect_r_vect___ata___bit 16 -#define reg_intr_vect_r_vect___sser0___lsb 17 -#define reg_intr_vect_r_vect___sser0___width 1 -#define reg_intr_vect_r_vect___sser0___bit 17 -#define reg_intr_vect_r_vect___sser1___lsb 18 -#define reg_intr_vect_r_vect___sser1___width 1 -#define reg_intr_vect_r_vect___sser1___bit 18 -#define reg_intr_vect_r_vect___ser0___lsb 19 -#define reg_intr_vect_r_vect___ser0___width 1 -#define reg_intr_vect_r_vect___ser0___bit 19 -#define reg_intr_vect_r_vect___ser1___lsb 20 -#define reg_intr_vect_r_vect___ser1___width 1 -#define reg_intr_vect_r_vect___ser1___bit 20 -#define reg_intr_vect_r_vect___ser2___lsb 21 -#define reg_intr_vect_r_vect___ser2___width 1 -#define reg_intr_vect_r_vect___ser2___bit 21 -#define reg_intr_vect_r_vect___ser3___lsb 22 -#define reg_intr_vect_r_vect___ser3___width 1 -#define reg_intr_vect_r_vect___ser3___bit 22 -#define reg_intr_vect_r_vect___p21___lsb 23 -#define reg_intr_vect_r_vect___p21___width 1 -#define reg_intr_vect_r_vect___p21___bit 23 -#define reg_intr_vect_r_vect___eth0___lsb 24 -#define reg_intr_vect_r_vect___eth0___width 1 -#define reg_intr_vect_r_vect___eth0___bit 24 -#define reg_intr_vect_r_vect___eth1___lsb 25 -#define reg_intr_vect_r_vect___eth1___width 1 -#define reg_intr_vect_r_vect___eth1___bit 25 -#define reg_intr_vect_r_vect___timer___lsb 26 -#define reg_intr_vect_r_vect___timer___width 1 -#define reg_intr_vect_r_vect___timer___bit 26 -#define reg_intr_vect_r_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_vect___bif_arb___width 1 -#define reg_intr_vect_r_vect___bif_arb___bit 27 -#define reg_intr_vect_r_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_vect___bif_dma___width 1 -#define reg_intr_vect_r_vect___bif_dma___bit 28 -#define reg_intr_vect_r_vect___ext___lsb 29 -#define reg_intr_vect_r_vect___ext___width 1 -#define reg_intr_vect_r_vect___ext___bit 29 -#define reg_intr_vect_r_vect_offset 4 - -/* Register r_masked_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_masked_vect___memarb___lsb 0 -#define reg_intr_vect_r_masked_vect___memarb___width 1 -#define reg_intr_vect_r_masked_vect___memarb___bit 0 -#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 -#define reg_intr_vect_r_masked_vect___gen_io___width 1 -#define reg_intr_vect_r_masked_vect___gen_io___bit 1 -#define reg_intr_vect_r_masked_vect___iop0___lsb 2 -#define reg_intr_vect_r_masked_vect___iop0___width 1 -#define reg_intr_vect_r_masked_vect___iop0___bit 2 -#define reg_intr_vect_r_masked_vect___iop1___lsb 3 -#define reg_intr_vect_r_masked_vect___iop1___width 1 -#define reg_intr_vect_r_masked_vect___iop1___bit 3 -#define reg_intr_vect_r_masked_vect___iop2___lsb 4 -#define reg_intr_vect_r_masked_vect___iop2___width 1 -#define reg_intr_vect_r_masked_vect___iop2___bit 4 -#define reg_intr_vect_r_masked_vect___iop3___lsb 5 -#define reg_intr_vect_r_masked_vect___iop3___width 1 -#define reg_intr_vect_r_masked_vect___iop3___bit 5 -#define reg_intr_vect_r_masked_vect___dma0___lsb 6 -#define reg_intr_vect_r_masked_vect___dma0___width 1 -#define reg_intr_vect_r_masked_vect___dma0___bit 6 -#define reg_intr_vect_r_masked_vect___dma1___lsb 7 -#define reg_intr_vect_r_masked_vect___dma1___width 1 -#define reg_intr_vect_r_masked_vect___dma1___bit 7 -#define reg_intr_vect_r_masked_vect___dma2___lsb 8 -#define reg_intr_vect_r_masked_vect___dma2___width 1 -#define reg_intr_vect_r_masked_vect___dma2___bit 8 -#define reg_intr_vect_r_masked_vect___dma3___lsb 9 -#define reg_intr_vect_r_masked_vect___dma3___width 1 -#define reg_intr_vect_r_masked_vect___dma3___bit 9 -#define reg_intr_vect_r_masked_vect___dma4___lsb 10 -#define reg_intr_vect_r_masked_vect___dma4___width 1 -#define reg_intr_vect_r_masked_vect___dma4___bit 10 -#define reg_intr_vect_r_masked_vect___dma5___lsb 11 -#define reg_intr_vect_r_masked_vect___dma5___width 1 -#define reg_intr_vect_r_masked_vect___dma5___bit 11 -#define reg_intr_vect_r_masked_vect___dma6___lsb 12 -#define reg_intr_vect_r_masked_vect___dma6___width 1 -#define reg_intr_vect_r_masked_vect___dma6___bit 12 -#define reg_intr_vect_r_masked_vect___dma7___lsb 13 -#define reg_intr_vect_r_masked_vect___dma7___width 1 -#define reg_intr_vect_r_masked_vect___dma7___bit 13 -#define reg_intr_vect_r_masked_vect___dma8___lsb 14 -#define reg_intr_vect_r_masked_vect___dma8___width 1 -#define reg_intr_vect_r_masked_vect___dma8___bit 14 -#define reg_intr_vect_r_masked_vect___dma9___lsb 15 -#define reg_intr_vect_r_masked_vect___dma9___width 1 -#define reg_intr_vect_r_masked_vect___dma9___bit 15 -#define reg_intr_vect_r_masked_vect___ata___lsb 16 -#define reg_intr_vect_r_masked_vect___ata___width 1 -#define reg_intr_vect_r_masked_vect___ata___bit 16 -#define reg_intr_vect_r_masked_vect___sser0___lsb 17 -#define reg_intr_vect_r_masked_vect___sser0___width 1 -#define reg_intr_vect_r_masked_vect___sser0___bit 17 -#define reg_intr_vect_r_masked_vect___sser1___lsb 18 -#define reg_intr_vect_r_masked_vect___sser1___width 1 -#define reg_intr_vect_r_masked_vect___sser1___bit 18 -#define reg_intr_vect_r_masked_vect___ser0___lsb 19 -#define reg_intr_vect_r_masked_vect___ser0___width 1 -#define reg_intr_vect_r_masked_vect___ser0___bit 19 -#define reg_intr_vect_r_masked_vect___ser1___lsb 20 -#define reg_intr_vect_r_masked_vect___ser1___width 1 -#define reg_intr_vect_r_masked_vect___ser1___bit 20 -#define reg_intr_vect_r_masked_vect___ser2___lsb 21 -#define reg_intr_vect_r_masked_vect___ser2___width 1 -#define reg_intr_vect_r_masked_vect___ser2___bit 21 -#define reg_intr_vect_r_masked_vect___ser3___lsb 22 -#define reg_intr_vect_r_masked_vect___ser3___width 1 -#define reg_intr_vect_r_masked_vect___ser3___bit 22 -#define reg_intr_vect_r_masked_vect___p21___lsb 23 -#define reg_intr_vect_r_masked_vect___p21___width 1 -#define reg_intr_vect_r_masked_vect___p21___bit 23 -#define reg_intr_vect_r_masked_vect___eth0___lsb 24 -#define reg_intr_vect_r_masked_vect___eth0___width 1 -#define reg_intr_vect_r_masked_vect___eth0___bit 24 -#define reg_intr_vect_r_masked_vect___eth1___lsb 25 -#define reg_intr_vect_r_masked_vect___eth1___width 1 -#define reg_intr_vect_r_masked_vect___eth1___bit 25 -#define reg_intr_vect_r_masked_vect___timer___lsb 26 -#define reg_intr_vect_r_masked_vect___timer___width 1 -#define reg_intr_vect_r_masked_vect___timer___bit 26 -#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_masked_vect___bif_arb___width 1 -#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 -#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_masked_vect___bif_dma___width 1 -#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 -#define reg_intr_vect_r_masked_vect___ext___lsb 29 -#define reg_intr_vect_r_masked_vect___ext___width 1 -#define reg_intr_vect_r_masked_vect___ext___bit 29 -#define reg_intr_vect_r_masked_vect_offset 8 - -/* Register r_nmi, scope intr_vect, type r */ -#define reg_intr_vect_r_nmi___ext___lsb 0 -#define reg_intr_vect_r_nmi___ext___width 1 -#define reg_intr_vect_r_nmi___ext___bit 0 -#define reg_intr_vect_r_nmi___watchdog___lsb 1 -#define reg_intr_vect_r_nmi___watchdog___width 1 -#define reg_intr_vect_r_nmi___watchdog___bit 1 -#define reg_intr_vect_r_nmi_offset 12 - -/* Register r_guru, scope intr_vect, type r */ -#define reg_intr_vect_r_guru___jtag___lsb 0 -#define reg_intr_vect_r_guru___jtag___width 1 -#define reg_intr_vect_r_guru___jtag___bit 0 -#define reg_intr_vect_r_guru_offset 16 - - -/* Constants */ -#define regk_intr_vect_off 0x00000000 -#define regk_intr_vect_on 0x00000001 -#define regk_intr_vect_rw_mask_default 0x00000000 -#endif /* __intr_vect_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h deleted file mode 100644 index 0c8084054840..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef __irq_nmi_defs_asm_h -#define __irq_nmi_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cmd, scope irq_nmi, type rw */ -#define reg_irq_nmi_rw_cmd___delay___lsb 0 -#define reg_irq_nmi_rw_cmd___delay___width 16 -#define reg_irq_nmi_rw_cmd___op___lsb 16 -#define reg_irq_nmi_rw_cmd___op___width 2 -#define reg_irq_nmi_rw_cmd_offset 0 - - -/* Constants */ -#define regk_irq_nmi_ack_irq 0x00000002 -#define regk_irq_nmi_ack_nmi 0x00000003 -#define regk_irq_nmi_irq 0x00000000 -#define regk_irq_nmi_nmi 0x00000001 -#endif /* __irq_nmi_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h deleted file mode 100644 index 45400eb8d389..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h +++ /dev/null @@ -1,579 +0,0 @@ -#ifndef __marb_defs_asm_h -#define __marb_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -#define reg_marb_rw_int_slots___owner___lsb 0 -#define reg_marb_rw_int_slots___owner___width 4 -#define reg_marb_rw_int_slots_offset 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -#define reg_marb_rw_ext_slots___owner___lsb 0 -#define reg_marb_rw_ext_slots___owner___width 4 -#define reg_marb_rw_ext_slots_offset 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -#define reg_marb_rw_regs_slots___owner___lsb 0 -#define reg_marb_rw_regs_slots___owner___width 4 -#define reg_marb_rw_regs_slots_offset 512 - -/* Register rw_intr_mask, scope marb, type rw */ -#define reg_marb_rw_intr_mask___bp0___lsb 0 -#define reg_marb_rw_intr_mask___bp0___width 1 -#define reg_marb_rw_intr_mask___bp0___bit 0 -#define reg_marb_rw_intr_mask___bp1___lsb 1 -#define reg_marb_rw_intr_mask___bp1___width 1 -#define reg_marb_rw_intr_mask___bp1___bit 1 -#define reg_marb_rw_intr_mask___bp2___lsb 2 -#define reg_marb_rw_intr_mask___bp2___width 1 -#define reg_marb_rw_intr_mask___bp2___bit 2 -#define reg_marb_rw_intr_mask___bp3___lsb 3 -#define reg_marb_rw_intr_mask___bp3___width 1 -#define reg_marb_rw_intr_mask___bp3___bit 3 -#define reg_marb_rw_intr_mask_offset 528 - -/* Register rw_ack_intr, scope marb, type rw */ -#define reg_marb_rw_ack_intr___bp0___lsb 0 -#define reg_marb_rw_ack_intr___bp0___width 1 -#define reg_marb_rw_ack_intr___bp0___bit 0 -#define reg_marb_rw_ack_intr___bp1___lsb 1 -#define reg_marb_rw_ack_intr___bp1___width 1 -#define reg_marb_rw_ack_intr___bp1___bit 1 -#define reg_marb_rw_ack_intr___bp2___lsb 2 -#define reg_marb_rw_ack_intr___bp2___width 1 -#define reg_marb_rw_ack_intr___bp2___bit 2 -#define reg_marb_rw_ack_intr___bp3___lsb 3 -#define reg_marb_rw_ack_intr___bp3___width 1 -#define reg_marb_rw_ack_intr___bp3___bit 3 -#define reg_marb_rw_ack_intr_offset 532 - -/* Register r_intr, scope marb, type r */ -#define reg_marb_r_intr___bp0___lsb 0 -#define reg_marb_r_intr___bp0___width 1 -#define reg_marb_r_intr___bp0___bit 0 -#define reg_marb_r_intr___bp1___lsb 1 -#define reg_marb_r_intr___bp1___width 1 -#define reg_marb_r_intr___bp1___bit 1 -#define reg_marb_r_intr___bp2___lsb 2 -#define reg_marb_r_intr___bp2___width 1 -#define reg_marb_r_intr___bp2___bit 2 -#define reg_marb_r_intr___bp3___lsb 3 -#define reg_marb_r_intr___bp3___width 1 -#define reg_marb_r_intr___bp3___bit 3 -#define reg_marb_r_intr_offset 536 - -/* Register r_masked_intr, scope marb, type r */ -#define reg_marb_r_masked_intr___bp0___lsb 0 -#define reg_marb_r_masked_intr___bp0___width 1 -#define reg_marb_r_masked_intr___bp0___bit 0 -#define reg_marb_r_masked_intr___bp1___lsb 1 -#define reg_marb_r_masked_intr___bp1___width 1 -#define reg_marb_r_masked_intr___bp1___bit 1 -#define reg_marb_r_masked_intr___bp2___lsb 2 -#define reg_marb_r_masked_intr___bp2___width 1 -#define reg_marb_r_masked_intr___bp2___bit 2 -#define reg_marb_r_masked_intr___bp3___lsb 3 -#define reg_marb_r_masked_intr___bp3___width 1 -#define reg_marb_r_masked_intr___bp3___bit 3 -#define reg_marb_r_masked_intr_offset 540 - -/* Register rw_stop_mask, scope marb, type rw */ -#define reg_marb_rw_stop_mask___dma0___lsb 0 -#define reg_marb_rw_stop_mask___dma0___width 1 -#define reg_marb_rw_stop_mask___dma0___bit 0 -#define reg_marb_rw_stop_mask___dma1___lsb 1 -#define reg_marb_rw_stop_mask___dma1___width 1 -#define reg_marb_rw_stop_mask___dma1___bit 1 -#define reg_marb_rw_stop_mask___dma2___lsb 2 -#define reg_marb_rw_stop_mask___dma2___width 1 -#define reg_marb_rw_stop_mask___dma2___bit 2 -#define reg_marb_rw_stop_mask___dma3___lsb 3 -#define reg_marb_rw_stop_mask___dma3___width 1 -#define reg_marb_rw_stop_mask___dma3___bit 3 -#define reg_marb_rw_stop_mask___dma4___lsb 4 -#define reg_marb_rw_stop_mask___dma4___width 1 -#define reg_marb_rw_stop_mask___dma4___bit 4 -#define reg_marb_rw_stop_mask___dma5___lsb 5 -#define reg_marb_rw_stop_mask___dma5___width 1 -#define reg_marb_rw_stop_mask___dma5___bit 5 -#define reg_marb_rw_stop_mask___dma6___lsb 6 -#define reg_marb_rw_stop_mask___dma6___width 1 -#define reg_marb_rw_stop_mask___dma6___bit 6 -#define reg_marb_rw_stop_mask___dma7___lsb 7 -#define reg_marb_rw_stop_mask___dma7___width 1 -#define reg_marb_rw_stop_mask___dma7___bit 7 -#define reg_marb_rw_stop_mask___dma8___lsb 8 -#define reg_marb_rw_stop_mask___dma8___width 1 -#define reg_marb_rw_stop_mask___dma8___bit 8 -#define reg_marb_rw_stop_mask___dma9___lsb 9 -#define reg_marb_rw_stop_mask___dma9___width 1 -#define reg_marb_rw_stop_mask___dma9___bit 9 -#define reg_marb_rw_stop_mask___cpui___lsb 10 -#define reg_marb_rw_stop_mask___cpui___width 1 -#define reg_marb_rw_stop_mask___cpui___bit 10 -#define reg_marb_rw_stop_mask___cpud___lsb 11 -#define reg_marb_rw_stop_mask___cpud___width 1 -#define reg_marb_rw_stop_mask___cpud___bit 11 -#define reg_marb_rw_stop_mask___iop___lsb 12 -#define reg_marb_rw_stop_mask___iop___width 1 -#define reg_marb_rw_stop_mask___iop___bit 12 -#define reg_marb_rw_stop_mask___slave___lsb 13 -#define reg_marb_rw_stop_mask___slave___width 1 -#define reg_marb_rw_stop_mask___slave___bit 13 -#define reg_marb_rw_stop_mask_offset 544 - -/* Register r_stopped, scope marb, type r */ -#define reg_marb_r_stopped___dma0___lsb 0 -#define reg_marb_r_stopped___dma0___width 1 -#define reg_marb_r_stopped___dma0___bit 0 -#define reg_marb_r_stopped___dma1___lsb 1 -#define reg_marb_r_stopped___dma1___width 1 -#define reg_marb_r_stopped___dma1___bit 1 -#define reg_marb_r_stopped___dma2___lsb 2 -#define reg_marb_r_stopped___dma2___width 1 -#define reg_marb_r_stopped___dma2___bit 2 -#define reg_marb_r_stopped___dma3___lsb 3 -#define reg_marb_r_stopped___dma3___width 1 -#define reg_marb_r_stopped___dma3___bit 3 -#define reg_marb_r_stopped___dma4___lsb 4 -#define reg_marb_r_stopped___dma4___width 1 -#define reg_marb_r_stopped___dma4___bit 4 -#define reg_marb_r_stopped___dma5___lsb 5 -#define reg_marb_r_stopped___dma5___width 1 -#define reg_marb_r_stopped___dma5___bit 5 -#define reg_marb_r_stopped___dma6___lsb 6 -#define reg_marb_r_stopped___dma6___width 1 -#define reg_marb_r_stopped___dma6___bit 6 -#define reg_marb_r_stopped___dma7___lsb 7 -#define reg_marb_r_stopped___dma7___width 1 -#define reg_marb_r_stopped___dma7___bit 7 -#define reg_marb_r_stopped___dma8___lsb 8 -#define reg_marb_r_stopped___dma8___width 1 -#define reg_marb_r_stopped___dma8___bit 8 -#define reg_marb_r_stopped___dma9___lsb 9 -#define reg_marb_r_stopped___dma9___width 1 -#define reg_marb_r_stopped___dma9___bit 9 -#define reg_marb_r_stopped___cpui___lsb 10 -#define reg_marb_r_stopped___cpui___width 1 -#define reg_marb_r_stopped___cpui___bit 10 -#define reg_marb_r_stopped___cpud___lsb 11 -#define reg_marb_r_stopped___cpud___width 1 -#define reg_marb_r_stopped___cpud___bit 11 -#define reg_marb_r_stopped___iop___lsb 12 -#define reg_marb_r_stopped___iop___width 1 -#define reg_marb_r_stopped___iop___bit 12 -#define reg_marb_r_stopped___slave___lsb 13 -#define reg_marb_r_stopped___slave___width 1 -#define reg_marb_r_stopped___slave___bit 13 -#define reg_marb_r_stopped_offset 548 - -/* Register rw_no_snoop, scope marb, type rw */ -#define reg_marb_rw_no_snoop___dma0___lsb 0 -#define reg_marb_rw_no_snoop___dma0___width 1 -#define reg_marb_rw_no_snoop___dma0___bit 0 -#define reg_marb_rw_no_snoop___dma1___lsb 1 -#define reg_marb_rw_no_snoop___dma1___width 1 -#define reg_marb_rw_no_snoop___dma1___bit 1 -#define reg_marb_rw_no_snoop___dma2___lsb 2 -#define reg_marb_rw_no_snoop___dma2___width 1 -#define reg_marb_rw_no_snoop___dma2___bit 2 -#define reg_marb_rw_no_snoop___dma3___lsb 3 -#define reg_marb_rw_no_snoop___dma3___width 1 -#define reg_marb_rw_no_snoop___dma3___bit 3 -#define reg_marb_rw_no_snoop___dma4___lsb 4 -#define reg_marb_rw_no_snoop___dma4___width 1 -#define reg_marb_rw_no_snoop___dma4___bit 4 -#define reg_marb_rw_no_snoop___dma5___lsb 5 -#define reg_marb_rw_no_snoop___dma5___width 1 -#define reg_marb_rw_no_snoop___dma5___bit 5 -#define reg_marb_rw_no_snoop___dma6___lsb 6 -#define reg_marb_rw_no_snoop___dma6___width 1 -#define reg_marb_rw_no_snoop___dma6___bit 6 -#define reg_marb_rw_no_snoop___dma7___lsb 7 -#define reg_marb_rw_no_snoop___dma7___width 1 -#define reg_marb_rw_no_snoop___dma7___bit 7 -#define reg_marb_rw_no_snoop___dma8___lsb 8 -#define reg_marb_rw_no_snoop___dma8___width 1 -#define reg_marb_rw_no_snoop___dma8___bit 8 -#define reg_marb_rw_no_snoop___dma9___lsb 9 -#define reg_marb_rw_no_snoop___dma9___width 1 -#define reg_marb_rw_no_snoop___dma9___bit 9 -#define reg_marb_rw_no_snoop___cpui___lsb 10 -#define reg_marb_rw_no_snoop___cpui___width 1 -#define reg_marb_rw_no_snoop___cpui___bit 10 -#define reg_marb_rw_no_snoop___cpud___lsb 11 -#define reg_marb_rw_no_snoop___cpud___width 1 -#define reg_marb_rw_no_snoop___cpud___bit 11 -#define reg_marb_rw_no_snoop___iop___lsb 12 -#define reg_marb_rw_no_snoop___iop___width 1 -#define reg_marb_rw_no_snoop___iop___bit 12 -#define reg_marb_rw_no_snoop___slave___lsb 13 -#define reg_marb_rw_no_snoop___slave___width 1 -#define reg_marb_rw_no_snoop___slave___bit 13 -#define reg_marb_rw_no_snoop_offset 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 -#define reg_marb_rw_no_snoop_rq___cpui___width 1 -#define reg_marb_rw_no_snoop_rq___cpui___bit 10 -#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 -#define reg_marb_rw_no_snoop_rq___cpud___width 1 -#define reg_marb_rw_no_snoop_rq___cpud___bit 11 -#define reg_marb_rw_no_snoop_rq_offset 836 - - -/* Constants */ -#define regk_marb_cpud 0x0000000b -#define regk_marb_cpui 0x0000000a -#define regk_marb_dma0 0x00000000 -#define regk_marb_dma1 0x00000001 -#define regk_marb_dma2 0x00000002 -#define regk_marb_dma3 0x00000003 -#define regk_marb_dma4 0x00000004 -#define regk_marb_dma5 0x00000005 -#define regk_marb_dma6 0x00000006 -#define regk_marb_dma7 0x00000007 -#define regk_marb_dma8 0x00000008 -#define regk_marb_dma9 0x00000009 -#define regk_marb_iop 0x0000000c -#define regk_marb_no 0x00000000 -#define regk_marb_r_stopped_default 0x00000000 -#define regk_marb_rw_ext_slots_default 0x00000000 -#define regk_marb_rw_ext_slots_size 0x00000040 -#define regk_marb_rw_int_slots_default 0x00000000 -#define regk_marb_rw_int_slots_size 0x00000040 -#define regk_marb_rw_intr_mask_default 0x00000000 -#define regk_marb_rw_no_snoop_default 0x00000000 -#define regk_marb_rw_no_snoop_rq_default 0x00000000 -#define regk_marb_rw_regs_slots_default 0x00000000 -#define regk_marb_rw_regs_slots_size 0x00000004 -#define regk_marb_rw_stop_mask_default 0x00000000 -#define regk_marb_slave 0x0000000d -#define regk_marb_yes 0x00000001 -#endif /* __marb_defs_asm_h */ -#ifndef __marb_bp_defs_asm_h -#define __marb_bp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_first_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_first_addr_offset 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_last_addr_offset 4 - -/* Register rw_op, scope marb_bp, type rw */ -#define reg_marb_bp_rw_op___rd___lsb 0 -#define reg_marb_bp_rw_op___rd___width 1 -#define reg_marb_bp_rw_op___rd___bit 0 -#define reg_marb_bp_rw_op___wr___lsb 1 -#define reg_marb_bp_rw_op___wr___width 1 -#define reg_marb_bp_rw_op___wr___bit 1 -#define reg_marb_bp_rw_op___rd_excl___lsb 2 -#define reg_marb_bp_rw_op___rd_excl___width 1 -#define reg_marb_bp_rw_op___rd_excl___bit 2 -#define reg_marb_bp_rw_op___pri_wr___lsb 3 -#define reg_marb_bp_rw_op___pri_wr___width 1 -#define reg_marb_bp_rw_op___pri_wr___bit 3 -#define reg_marb_bp_rw_op___us_rd___lsb 4 -#define reg_marb_bp_rw_op___us_rd___width 1 -#define reg_marb_bp_rw_op___us_rd___bit 4 -#define reg_marb_bp_rw_op___us_wr___lsb 5 -#define reg_marb_bp_rw_op___us_wr___width 1 -#define reg_marb_bp_rw_op___us_wr___bit 5 -#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 -#define reg_marb_bp_rw_op___us_rd_excl___width 1 -#define reg_marb_bp_rw_op___us_rd_excl___bit 6 -#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 -#define reg_marb_bp_rw_op___us_pri_wr___width 1 -#define reg_marb_bp_rw_op___us_pri_wr___bit 7 -#define reg_marb_bp_rw_op_offset 8 - -/* Register rw_clients, scope marb_bp, type rw */ -#define reg_marb_bp_rw_clients___dma0___lsb 0 -#define reg_marb_bp_rw_clients___dma0___width 1 -#define reg_marb_bp_rw_clients___dma0___bit 0 -#define reg_marb_bp_rw_clients___dma1___lsb 1 -#define reg_marb_bp_rw_clients___dma1___width 1 -#define reg_marb_bp_rw_clients___dma1___bit 1 -#define reg_marb_bp_rw_clients___dma2___lsb 2 -#define reg_marb_bp_rw_clients___dma2___width 1 -#define reg_marb_bp_rw_clients___dma2___bit 2 -#define reg_marb_bp_rw_clients___dma3___lsb 3 -#define reg_marb_bp_rw_clients___dma3___width 1 -#define reg_marb_bp_rw_clients___dma3___bit 3 -#define reg_marb_bp_rw_clients___dma4___lsb 4 -#define reg_marb_bp_rw_clients___dma4___width 1 -#define reg_marb_bp_rw_clients___dma4___bit 4 -#define reg_marb_bp_rw_clients___dma5___lsb 5 -#define reg_marb_bp_rw_clients___dma5___width 1 -#define reg_marb_bp_rw_clients___dma5___bit 5 -#define reg_marb_bp_rw_clients___dma6___lsb 6 -#define reg_marb_bp_rw_clients___dma6___width 1 -#define reg_marb_bp_rw_clients___dma6___bit 6 -#define reg_marb_bp_rw_clients___dma7___lsb 7 -#define reg_marb_bp_rw_clients___dma7___width 1 -#define reg_marb_bp_rw_clients___dma7___bit 7 -#define reg_marb_bp_rw_clients___dma8___lsb 8 -#define reg_marb_bp_rw_clients___dma8___width 1 -#define reg_marb_bp_rw_clients___dma8___bit 8 -#define reg_marb_bp_rw_clients___dma9___lsb 9 -#define reg_marb_bp_rw_clients___dma9___width 1 -#define reg_marb_bp_rw_clients___dma9___bit 9 -#define reg_marb_bp_rw_clients___cpui___lsb 10 -#define reg_marb_bp_rw_clients___cpui___width 1 -#define reg_marb_bp_rw_clients___cpui___bit 10 -#define reg_marb_bp_rw_clients___cpud___lsb 11 -#define reg_marb_bp_rw_clients___cpud___width 1 -#define reg_marb_bp_rw_clients___cpud___bit 11 -#define reg_marb_bp_rw_clients___iop___lsb 12 -#define reg_marb_bp_rw_clients___iop___width 1 -#define reg_marb_bp_rw_clients___iop___bit 12 -#define reg_marb_bp_rw_clients___slave___lsb 13 -#define reg_marb_bp_rw_clients___slave___width 1 -#define reg_marb_bp_rw_clients___slave___bit 13 -#define reg_marb_bp_rw_clients_offset 12 - -/* Register rw_options, scope marb_bp, type rw */ -#define reg_marb_bp_rw_options___wrap___lsb 0 -#define reg_marb_bp_rw_options___wrap___width 1 -#define reg_marb_bp_rw_options___wrap___bit 0 -#define reg_marb_bp_rw_options_offset 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_addr_offset 20 - -/* Register r_brk_op, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_op___rd___lsb 0 -#define reg_marb_bp_r_brk_op___rd___width 1 -#define reg_marb_bp_r_brk_op___rd___bit 0 -#define reg_marb_bp_r_brk_op___wr___lsb 1 -#define reg_marb_bp_r_brk_op___wr___width 1 -#define reg_marb_bp_r_brk_op___wr___bit 1 -#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 -#define reg_marb_bp_r_brk_op___rd_excl___width 1 -#define reg_marb_bp_r_brk_op___rd_excl___bit 2 -#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 -#define reg_marb_bp_r_brk_op___pri_wr___width 1 -#define reg_marb_bp_r_brk_op___pri_wr___bit 3 -#define reg_marb_bp_r_brk_op___us_rd___lsb 4 -#define reg_marb_bp_r_brk_op___us_rd___width 1 -#define reg_marb_bp_r_brk_op___us_rd___bit 4 -#define reg_marb_bp_r_brk_op___us_wr___lsb 5 -#define reg_marb_bp_r_brk_op___us_wr___width 1 -#define reg_marb_bp_r_brk_op___us_wr___bit 5 -#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 -#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 -#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 -#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 -#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 -#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 -#define reg_marb_bp_r_brk_op_offset 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_clients___dma0___lsb 0 -#define reg_marb_bp_r_brk_clients___dma0___width 1 -#define reg_marb_bp_r_brk_clients___dma0___bit 0 -#define reg_marb_bp_r_brk_clients___dma1___lsb 1 -#define reg_marb_bp_r_brk_clients___dma1___width 1 -#define reg_marb_bp_r_brk_clients___dma1___bit 1 -#define reg_marb_bp_r_brk_clients___dma2___lsb 2 -#define reg_marb_bp_r_brk_clients___dma2___width 1 -#define reg_marb_bp_r_brk_clients___dma2___bit 2 -#define reg_marb_bp_r_brk_clients___dma3___lsb 3 -#define reg_marb_bp_r_brk_clients___dma3___width 1 -#define reg_marb_bp_r_brk_clients___dma3___bit 3 -#define reg_marb_bp_r_brk_clients___dma4___lsb 4 -#define reg_marb_bp_r_brk_clients___dma4___width 1 -#define reg_marb_bp_r_brk_clients___dma4___bit 4 -#define reg_marb_bp_r_brk_clients___dma5___lsb 5 -#define reg_marb_bp_r_brk_clients___dma5___width 1 -#define reg_marb_bp_r_brk_clients___dma5___bit 5 -#define reg_marb_bp_r_brk_clients___dma6___lsb 6 -#define reg_marb_bp_r_brk_clients___dma6___width 1 -#define reg_marb_bp_r_brk_clients___dma6___bit 6 -#define reg_marb_bp_r_brk_clients___dma7___lsb 7 -#define reg_marb_bp_r_brk_clients___dma7___width 1 -#define reg_marb_bp_r_brk_clients___dma7___bit 7 -#define reg_marb_bp_r_brk_clients___dma8___lsb 8 -#define reg_marb_bp_r_brk_clients___dma8___width 1 -#define reg_marb_bp_r_brk_clients___dma8___bit 8 -#define reg_marb_bp_r_brk_clients___dma9___lsb 9 -#define reg_marb_bp_r_brk_clients___dma9___width 1 -#define reg_marb_bp_r_brk_clients___dma9___bit 9 -#define reg_marb_bp_r_brk_clients___cpui___lsb 10 -#define reg_marb_bp_r_brk_clients___cpui___width 1 -#define reg_marb_bp_r_brk_clients___cpui___bit 10 -#define reg_marb_bp_r_brk_clients___cpud___lsb 11 -#define reg_marb_bp_r_brk_clients___cpud___width 1 -#define reg_marb_bp_r_brk_clients___cpud___bit 11 -#define reg_marb_bp_r_brk_clients___iop___lsb 12 -#define reg_marb_bp_r_brk_clients___iop___width 1 -#define reg_marb_bp_r_brk_clients___iop___bit 12 -#define reg_marb_bp_r_brk_clients___slave___lsb 13 -#define reg_marb_bp_r_brk_clients___slave___width 1 -#define reg_marb_bp_r_brk_clients___slave___bit 13 -#define reg_marb_bp_r_brk_clients_offset 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 -#define reg_marb_bp_r_brk_first_client___dma0___width 1 -#define reg_marb_bp_r_brk_first_client___dma0___bit 0 -#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 -#define reg_marb_bp_r_brk_first_client___dma1___width 1 -#define reg_marb_bp_r_brk_first_client___dma1___bit 1 -#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 -#define reg_marb_bp_r_brk_first_client___dma2___width 1 -#define reg_marb_bp_r_brk_first_client___dma2___bit 2 -#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 -#define reg_marb_bp_r_brk_first_client___dma3___width 1 -#define reg_marb_bp_r_brk_first_client___dma3___bit 3 -#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 -#define reg_marb_bp_r_brk_first_client___dma4___width 1 -#define reg_marb_bp_r_brk_first_client___dma4___bit 4 -#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 -#define reg_marb_bp_r_brk_first_client___dma5___width 1 -#define reg_marb_bp_r_brk_first_client___dma5___bit 5 -#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 -#define reg_marb_bp_r_brk_first_client___dma6___width 1 -#define reg_marb_bp_r_brk_first_client___dma6___bit 6 -#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 -#define reg_marb_bp_r_brk_first_client___dma7___width 1 -#define reg_marb_bp_r_brk_first_client___dma7___bit 7 -#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 -#define reg_marb_bp_r_brk_first_client___dma8___width 1 -#define reg_marb_bp_r_brk_first_client___dma8___bit 8 -#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 -#define reg_marb_bp_r_brk_first_client___dma9___width 1 -#define reg_marb_bp_r_brk_first_client___dma9___bit 9 -#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 -#define reg_marb_bp_r_brk_first_client___cpui___width 1 -#define reg_marb_bp_r_brk_first_client___cpui___bit 10 -#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 -#define reg_marb_bp_r_brk_first_client___cpud___width 1 -#define reg_marb_bp_r_brk_first_client___cpud___bit 11 -#define reg_marb_bp_r_brk_first_client___iop___lsb 12 -#define reg_marb_bp_r_brk_first_client___iop___width 1 -#define reg_marb_bp_r_brk_first_client___iop___bit 12 -#define reg_marb_bp_r_brk_first_client___slave___lsb 13 -#define reg_marb_bp_r_brk_first_client___slave___width 1 -#define reg_marb_bp_r_brk_first_client___slave___bit 13 -#define reg_marb_bp_r_brk_first_client_offset 32 - -/* Register r_brk_size, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_size_offset 36 - -/* Register rw_ack, scope marb_bp, type rw */ -#define reg_marb_bp_rw_ack_offset 40 - - -/* Constants */ -#define regk_marb_bp_no 0x00000000 -#define regk_marb_bp_rw_op_default 0x00000000 -#define regk_marb_bp_rw_options_default 0x00000000 -#define regk_marb_bp_yes 0x00000001 -#endif /* __marb_bp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h deleted file mode 100644 index 505b7a16d878..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h +++ /dev/null @@ -1,212 +0,0 @@ -#ifndef __mmu_defs_asm_h -#define __mmu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/mmu/doc/mmu_regs.r - * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp - * last modfied: Mon Apr 11 17:03:20 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r - * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mm_cfg, scope mmu, type rw */ -#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 -#define reg_mmu_rw_mm_cfg___seg_0___width 1 -#define reg_mmu_rw_mm_cfg___seg_0___bit 0 -#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 -#define reg_mmu_rw_mm_cfg___seg_1___width 1 -#define reg_mmu_rw_mm_cfg___seg_1___bit 1 -#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 -#define reg_mmu_rw_mm_cfg___seg_2___width 1 -#define reg_mmu_rw_mm_cfg___seg_2___bit 2 -#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 -#define reg_mmu_rw_mm_cfg___seg_3___width 1 -#define reg_mmu_rw_mm_cfg___seg_3___bit 3 -#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 -#define reg_mmu_rw_mm_cfg___seg_4___width 1 -#define reg_mmu_rw_mm_cfg___seg_4___bit 4 -#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 -#define reg_mmu_rw_mm_cfg___seg_5___width 1 -#define reg_mmu_rw_mm_cfg___seg_5___bit 5 -#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 -#define reg_mmu_rw_mm_cfg___seg_6___width 1 -#define reg_mmu_rw_mm_cfg___seg_6___bit 6 -#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 -#define reg_mmu_rw_mm_cfg___seg_7___width 1 -#define reg_mmu_rw_mm_cfg___seg_7___bit 7 -#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 -#define reg_mmu_rw_mm_cfg___seg_8___width 1 -#define reg_mmu_rw_mm_cfg___seg_8___bit 8 -#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 -#define reg_mmu_rw_mm_cfg___seg_9___width 1 -#define reg_mmu_rw_mm_cfg___seg_9___bit 9 -#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 -#define reg_mmu_rw_mm_cfg___seg_a___width 1 -#define reg_mmu_rw_mm_cfg___seg_a___bit 10 -#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 -#define reg_mmu_rw_mm_cfg___seg_b___width 1 -#define reg_mmu_rw_mm_cfg___seg_b___bit 11 -#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 -#define reg_mmu_rw_mm_cfg___seg_c___width 1 -#define reg_mmu_rw_mm_cfg___seg_c___bit 12 -#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 -#define reg_mmu_rw_mm_cfg___seg_d___width 1 -#define reg_mmu_rw_mm_cfg___seg_d___bit 13 -#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 -#define reg_mmu_rw_mm_cfg___seg_e___width 1 -#define reg_mmu_rw_mm_cfg___seg_e___bit 14 -#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 -#define reg_mmu_rw_mm_cfg___seg_f___width 1 -#define reg_mmu_rw_mm_cfg___seg_f___bit 15 -#define reg_mmu_rw_mm_cfg___inv___lsb 16 -#define reg_mmu_rw_mm_cfg___inv___width 1 -#define reg_mmu_rw_mm_cfg___inv___bit 16 -#define reg_mmu_rw_mm_cfg___ex___lsb 17 -#define reg_mmu_rw_mm_cfg___ex___width 1 -#define reg_mmu_rw_mm_cfg___ex___bit 17 -#define reg_mmu_rw_mm_cfg___acc___lsb 18 -#define reg_mmu_rw_mm_cfg___acc___width 1 -#define reg_mmu_rw_mm_cfg___acc___bit 18 -#define reg_mmu_rw_mm_cfg___we___lsb 19 -#define reg_mmu_rw_mm_cfg___we___width 1 -#define reg_mmu_rw_mm_cfg___we___bit 19 -#define reg_mmu_rw_mm_cfg_offset 0 - -/* Register rw_mm_kbase_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 -#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 -#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 -#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 -#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 -#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 -#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 -#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 -#define reg_mmu_rw_mm_kbase_lo_offset 4 - -/* Register rw_mm_kbase_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 -#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 -#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 -#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 -#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 -#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 -#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 -#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 -#define reg_mmu_rw_mm_kbase_hi_offset 8 - -/* Register r_mm_cause, scope mmu, type r */ -#define reg_mmu_r_mm_cause___pid___lsb 0 -#define reg_mmu_r_mm_cause___pid___width 8 -#define reg_mmu_r_mm_cause___op___lsb 8 -#define reg_mmu_r_mm_cause___op___width 2 -#define reg_mmu_r_mm_cause___vpn___lsb 13 -#define reg_mmu_r_mm_cause___vpn___width 19 -#define reg_mmu_r_mm_cause_offset 12 - -/* Register rw_mm_tlb_sel, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 -#define reg_mmu_rw_mm_tlb_sel___idx___width 4 -#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 -#define reg_mmu_rw_mm_tlb_sel___set___width 2 -#define reg_mmu_rw_mm_tlb_sel_offset 16 - -/* Register rw_mm_tlb_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 -#define reg_mmu_rw_mm_tlb_lo___x___width 1 -#define reg_mmu_rw_mm_tlb_lo___x___bit 0 -#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 -#define reg_mmu_rw_mm_tlb_lo___w___width 1 -#define reg_mmu_rw_mm_tlb_lo___w___bit 1 -#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 -#define reg_mmu_rw_mm_tlb_lo___k___width 1 -#define reg_mmu_rw_mm_tlb_lo___k___bit 2 -#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 -#define reg_mmu_rw_mm_tlb_lo___v___width 1 -#define reg_mmu_rw_mm_tlb_lo___v___bit 3 -#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 -#define reg_mmu_rw_mm_tlb_lo___g___width 1 -#define reg_mmu_rw_mm_tlb_lo___g___bit 4 -#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 -#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 -#define reg_mmu_rw_mm_tlb_lo_offset 20 - -/* Register rw_mm_tlb_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 -#define reg_mmu_rw_mm_tlb_hi___pid___width 8 -#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 -#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 -#define reg_mmu_rw_mm_tlb_hi_offset 24 - - -/* Constants */ -#define regk_mmu_execute 0x00000000 -#define regk_mmu_flush 0x00000003 -#define regk_mmu_linear 0x00000001 -#define regk_mmu_no 0x00000000 -#define regk_mmu_off 0x00000000 -#define regk_mmu_on 0x00000001 -#define regk_mmu_page 0x00000000 -#define regk_mmu_read 0x00000001 -#define regk_mmu_write 0x00000002 -#define regk_mmu_yes 0x00000001 -#endif /* __mmu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h deleted file mode 100644 index 339500bf3bc0..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h +++ /dev/null @@ -1,7 +0,0 @@ -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define R_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 13c725e4c774..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,632 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 76959b70cd2c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h deleted file mode 100644 index 10246f49fb28..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __rt_trace_defs_asm_h -#define __rt_trace_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope rt_trace, type rw */ -#define reg_rt_trace_rw_cfg___en___lsb 0 -#define reg_rt_trace_rw_cfg___en___width 1 -#define reg_rt_trace_rw_cfg___en___bit 0 -#define reg_rt_trace_rw_cfg___mode___lsb 1 -#define reg_rt_trace_rw_cfg___mode___width 1 -#define reg_rt_trace_rw_cfg___mode___bit 1 -#define reg_rt_trace_rw_cfg___owner___lsb 2 -#define reg_rt_trace_rw_cfg___owner___width 1 -#define reg_rt_trace_rw_cfg___owner___bit 2 -#define reg_rt_trace_rw_cfg___wp___lsb 3 -#define reg_rt_trace_rw_cfg___wp___width 1 -#define reg_rt_trace_rw_cfg___wp___bit 3 -#define reg_rt_trace_rw_cfg___stall___lsb 4 -#define reg_rt_trace_rw_cfg___stall___width 1 -#define reg_rt_trace_rw_cfg___stall___bit 4 -#define reg_rt_trace_rw_cfg___wp_start___lsb 8 -#define reg_rt_trace_rw_cfg___wp_start___width 7 -#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 -#define reg_rt_trace_rw_cfg___wp_stop___width 7 -#define reg_rt_trace_rw_cfg_offset 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 -#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 -#define reg_rt_trace_rw_tap_ctrl_offset 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -#define reg_rt_trace_r_tap_stat___dav___lsb 0 -#define reg_rt_trace_r_tap_stat___dav___width 1 -#define reg_rt_trace_r_tap_stat___dav___bit 0 -#define reg_rt_trace_r_tap_stat___empty___lsb 1 -#define reg_rt_trace_r_tap_stat___empty___width 1 -#define reg_rt_trace_r_tap_stat___empty___bit 1 -#define reg_rt_trace_r_tap_stat_offset 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_data_offset 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_hdata___op___lsb 0 -#define reg_rt_trace_rw_tap_hdata___op___width 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 -#define reg_rt_trace_rw_tap_hdata_offset 16 - -/* Register r_redir, scope rt_trace, type r */ -#define reg_rt_trace_r_redir_offset 20 - - -/* Constants */ -#define regk_rt_trace_brk 0x0000000c -#define regk_rt_trace_dbg 0x00000003 -#define regk_rt_trace_dbgdi 0x00000004 -#define regk_rt_trace_dbgdo 0x00000005 -#define regk_rt_trace_gmode 0x00000000 -#define regk_rt_trace_no 0x00000000 -#define regk_rt_trace_nop 0x00000000 -#define regk_rt_trace_normal 0x00000000 -#define regk_rt_trace_rdmem 0x00000007 -#define regk_rt_trace_rdmemb 0x00000009 -#define regk_rt_trace_rdpreg 0x00000002 -#define regk_rt_trace_rdreg 0x00000001 -#define regk_rt_trace_rdsreg 0x00000003 -#define regk_rt_trace_redir 0x00000006 -#define regk_rt_trace_ret 0x0000000b -#define regk_rt_trace_rw_cfg_default 0x00000000 -#define regk_rt_trace_trcfg 0x00000001 -#define regk_rt_trace_wp 0x00000001 -#define regk_rt_trace_wp0 0x00000001 -#define regk_rt_trace_wp1 0x00000002 -#define regk_rt_trace_wp2 0x00000004 -#define regk_rt_trace_wp3 0x00000008 -#define regk_rt_trace_wp4 0x00000010 -#define regk_rt_trace_wp5 0x00000020 -#define regk_rt_trace_wp6 0x00000040 -#define regk_rt_trace_wrmem 0x00000008 -#define regk_rt_trace_wrmemb 0x0000000a -#define regk_rt_trace_wrpreg 0x00000005 -#define regk_rt_trace_wrreg 0x00000004 -#define regk_rt_trace_wrsreg 0x00000006 -#define regk_rt_trace_yes 0x00000001 -#endif /* __rt_trace_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h deleted file mode 100644 index 4a2808bdf390..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h +++ /dev/null @@ -1,359 +0,0 @@ -#ifndef __ser_defs_asm_h -#define __ser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tr_ctrl, scope ser, type rw */ -#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 -#define reg_ser_rw_tr_ctrl___base_freq___width 3 -#define reg_ser_rw_tr_ctrl___en___lsb 3 -#define reg_ser_rw_tr_ctrl___en___width 1 -#define reg_ser_rw_tr_ctrl___en___bit 3 -#define reg_ser_rw_tr_ctrl___par___lsb 4 -#define reg_ser_rw_tr_ctrl___par___width 2 -#define reg_ser_rw_tr_ctrl___par_en___lsb 6 -#define reg_ser_rw_tr_ctrl___par_en___width 1 -#define reg_ser_rw_tr_ctrl___par_en___bit 6 -#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 -#define reg_ser_rw_tr_ctrl___data_bits___width 1 -#define reg_ser_rw_tr_ctrl___data_bits___bit 7 -#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 -#define reg_ser_rw_tr_ctrl___stop_bits___width 1 -#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 -#define reg_ser_rw_tr_ctrl___stop___lsb 9 -#define reg_ser_rw_tr_ctrl___stop___width 1 -#define reg_ser_rw_tr_ctrl___stop___bit 9 -#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 -#define reg_ser_rw_tr_ctrl___rts_delay___width 3 -#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 -#define reg_ser_rw_tr_ctrl___rts_setup___width 1 -#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 -#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 -#define reg_ser_rw_tr_ctrl___auto_rts___width 1 -#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 -#define reg_ser_rw_tr_ctrl___txd___lsb 15 -#define reg_ser_rw_tr_ctrl___txd___width 1 -#define reg_ser_rw_tr_ctrl___txd___bit 15 -#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 -#define reg_ser_rw_tr_ctrl___auto_cts___width 1 -#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 -#define reg_ser_rw_tr_ctrl_offset 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -#define reg_ser_rw_tr_dma_en___en___lsb 0 -#define reg_ser_rw_tr_dma_en___en___width 1 -#define reg_ser_rw_tr_dma_en___en___bit 0 -#define reg_ser_rw_tr_dma_en_offset 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 -#define reg_ser_rw_rec_ctrl___base_freq___width 3 -#define reg_ser_rw_rec_ctrl___en___lsb 3 -#define reg_ser_rw_rec_ctrl___en___width 1 -#define reg_ser_rw_rec_ctrl___en___bit 3 -#define reg_ser_rw_rec_ctrl___par___lsb 4 -#define reg_ser_rw_rec_ctrl___par___width 2 -#define reg_ser_rw_rec_ctrl___par_en___lsb 6 -#define reg_ser_rw_rec_ctrl___par_en___width 1 -#define reg_ser_rw_rec_ctrl___par_en___bit 6 -#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 -#define reg_ser_rw_rec_ctrl___data_bits___width 1 -#define reg_ser_rw_rec_ctrl___data_bits___bit 7 -#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 -#define reg_ser_rw_rec_ctrl___dma_mode___width 1 -#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 -#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 -#define reg_ser_rw_rec_ctrl___dma_err___width 1 -#define reg_ser_rw_rec_ctrl___dma_err___bit 9 -#define reg_ser_rw_rec_ctrl___sampling___lsb 10 -#define reg_ser_rw_rec_ctrl___sampling___width 1 -#define reg_ser_rw_rec_ctrl___sampling___bit 10 -#define reg_ser_rw_rec_ctrl___timeout___lsb 11 -#define reg_ser_rw_rec_ctrl___timeout___width 3 -#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 -#define reg_ser_rw_rec_ctrl___auto_eop___width 1 -#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 -#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 -#define reg_ser_rw_rec_ctrl___half_duplex___width 1 -#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 -#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 -#define reg_ser_rw_rec_ctrl___rts_n___width 1 -#define reg_ser_rw_rec_ctrl___rts_n___bit 16 -#define reg_ser_rw_rec_ctrl___loopback___lsb 17 -#define reg_ser_rw_rec_ctrl___loopback___width 1 -#define reg_ser_rw_rec_ctrl___loopback___bit 17 -#define reg_ser_rw_rec_ctrl_offset 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -#define reg_ser_rw_tr_baud_div___div___lsb 0 -#define reg_ser_rw_tr_baud_div___div___width 16 -#define reg_ser_rw_tr_baud_div_offset 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -#define reg_ser_rw_rec_baud_div___div___lsb 0 -#define reg_ser_rw_rec_baud_div___div___width 16 -#define reg_ser_rw_rec_baud_div_offset 16 - -/* Register rw_xoff, scope ser, type rw */ -#define reg_ser_rw_xoff___chr___lsb 0 -#define reg_ser_rw_xoff___chr___width 8 -#define reg_ser_rw_xoff___automatic___lsb 8 -#define reg_ser_rw_xoff___automatic___width 1 -#define reg_ser_rw_xoff___automatic___bit 8 -#define reg_ser_rw_xoff_offset 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -#define reg_ser_rw_xoff_clr___clr___lsb 0 -#define reg_ser_rw_xoff_clr___clr___width 1 -#define reg_ser_rw_xoff_clr___clr___bit 0 -#define reg_ser_rw_xoff_clr_offset 24 - -/* Register rw_dout, scope ser, type rw */ -#define reg_ser_rw_dout___data___lsb 0 -#define reg_ser_rw_dout___data___width 8 -#define reg_ser_rw_dout_offset 28 - -/* Register rs_stat_din, scope ser, type rs */ -#define reg_ser_rs_stat_din___data___lsb 0 -#define reg_ser_rs_stat_din___data___width 8 -#define reg_ser_rs_stat_din___dav___lsb 16 -#define reg_ser_rs_stat_din___dav___width 1 -#define reg_ser_rs_stat_din___dav___bit 16 -#define reg_ser_rs_stat_din___framing_err___lsb 17 -#define reg_ser_rs_stat_din___framing_err___width 1 -#define reg_ser_rs_stat_din___framing_err___bit 17 -#define reg_ser_rs_stat_din___par_err___lsb 18 -#define reg_ser_rs_stat_din___par_err___width 1 -#define reg_ser_rs_stat_din___par_err___bit 18 -#define reg_ser_rs_stat_din___orun___lsb 19 -#define reg_ser_rs_stat_din___orun___width 1 -#define reg_ser_rs_stat_din___orun___bit 19 -#define reg_ser_rs_stat_din___rec_err___lsb 20 -#define reg_ser_rs_stat_din___rec_err___width 1 -#define reg_ser_rs_stat_din___rec_err___bit 20 -#define reg_ser_rs_stat_din___rxd___lsb 21 -#define reg_ser_rs_stat_din___rxd___width 1 -#define reg_ser_rs_stat_din___rxd___bit 21 -#define reg_ser_rs_stat_din___tr_idle___lsb 22 -#define reg_ser_rs_stat_din___tr_idle___width 1 -#define reg_ser_rs_stat_din___tr_idle___bit 22 -#define reg_ser_rs_stat_din___tr_empty___lsb 23 -#define reg_ser_rs_stat_din___tr_empty___width 1 -#define reg_ser_rs_stat_din___tr_empty___bit 23 -#define reg_ser_rs_stat_din___tr_rdy___lsb 24 -#define reg_ser_rs_stat_din___tr_rdy___width 1 -#define reg_ser_rs_stat_din___tr_rdy___bit 24 -#define reg_ser_rs_stat_din___cts_n___lsb 25 -#define reg_ser_rs_stat_din___cts_n___width 1 -#define reg_ser_rs_stat_din___cts_n___bit 25 -#define reg_ser_rs_stat_din___xoff_detect___lsb 26 -#define reg_ser_rs_stat_din___xoff_detect___width 1 -#define reg_ser_rs_stat_din___xoff_detect___bit 26 -#define reg_ser_rs_stat_din___rts_n___lsb 27 -#define reg_ser_rs_stat_din___rts_n___width 1 -#define reg_ser_rs_stat_din___rts_n___bit 27 -#define reg_ser_rs_stat_din___txd___lsb 28 -#define reg_ser_rs_stat_din___txd___width 1 -#define reg_ser_rs_stat_din___txd___bit 28 -#define reg_ser_rs_stat_din_offset 32 - -/* Register r_stat_din, scope ser, type r */ -#define reg_ser_r_stat_din___data___lsb 0 -#define reg_ser_r_stat_din___data___width 8 -#define reg_ser_r_stat_din___dav___lsb 16 -#define reg_ser_r_stat_din___dav___width 1 -#define reg_ser_r_stat_din___dav___bit 16 -#define reg_ser_r_stat_din___framing_err___lsb 17 -#define reg_ser_r_stat_din___framing_err___width 1 -#define reg_ser_r_stat_din___framing_err___bit 17 -#define reg_ser_r_stat_din___par_err___lsb 18 -#define reg_ser_r_stat_din___par_err___width 1 -#define reg_ser_r_stat_din___par_err___bit 18 -#define reg_ser_r_stat_din___orun___lsb 19 -#define reg_ser_r_stat_din___orun___width 1 -#define reg_ser_r_stat_din___orun___bit 19 -#define reg_ser_r_stat_din___rec_err___lsb 20 -#define reg_ser_r_stat_din___rec_err___width 1 -#define reg_ser_r_stat_din___rec_err___bit 20 -#define reg_ser_r_stat_din___rxd___lsb 21 -#define reg_ser_r_stat_din___rxd___width 1 -#define reg_ser_r_stat_din___rxd___bit 21 -#define reg_ser_r_stat_din___tr_idle___lsb 22 -#define reg_ser_r_stat_din___tr_idle___width 1 -#define reg_ser_r_stat_din___tr_idle___bit 22 -#define reg_ser_r_stat_din___tr_empty___lsb 23 -#define reg_ser_r_stat_din___tr_empty___width 1 -#define reg_ser_r_stat_din___tr_empty___bit 23 -#define reg_ser_r_stat_din___tr_rdy___lsb 24 -#define reg_ser_r_stat_din___tr_rdy___width 1 -#define reg_ser_r_stat_din___tr_rdy___bit 24 -#define reg_ser_r_stat_din___cts_n___lsb 25 -#define reg_ser_r_stat_din___cts_n___width 1 -#define reg_ser_r_stat_din___cts_n___bit 25 -#define reg_ser_r_stat_din___xoff_detect___lsb 26 -#define reg_ser_r_stat_din___xoff_detect___width 1 -#define reg_ser_r_stat_din___xoff_detect___bit 26 -#define reg_ser_r_stat_din___rts_n___lsb 27 -#define reg_ser_r_stat_din___rts_n___width 1 -#define reg_ser_r_stat_din___rts_n___bit 27 -#define reg_ser_r_stat_din___txd___lsb 28 -#define reg_ser_r_stat_din___txd___width 1 -#define reg_ser_r_stat_din___txd___bit 28 -#define reg_ser_r_stat_din_offset 36 - -/* Register rw_rec_eop, scope ser, type rw */ -#define reg_ser_rw_rec_eop___set___lsb 0 -#define reg_ser_rw_rec_eop___set___width 1 -#define reg_ser_rw_rec_eop___set___bit 0 -#define reg_ser_rw_rec_eop_offset 40 - -/* Register rw_intr_mask, scope ser, type rw */ -#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 -#define reg_ser_rw_intr_mask___tr_rdy___width 1 -#define reg_ser_rw_intr_mask___tr_rdy___bit 0 -#define reg_ser_rw_intr_mask___tr_empty___lsb 1 -#define reg_ser_rw_intr_mask___tr_empty___width 1 -#define reg_ser_rw_intr_mask___tr_empty___bit 1 -#define reg_ser_rw_intr_mask___tr_idle___lsb 2 -#define reg_ser_rw_intr_mask___tr_idle___width 1 -#define reg_ser_rw_intr_mask___tr_idle___bit 2 -#define reg_ser_rw_intr_mask___dav___lsb 3 -#define reg_ser_rw_intr_mask___dav___width 1 -#define reg_ser_rw_intr_mask___dav___bit 3 -#define reg_ser_rw_intr_mask_offset 44 - -/* Register rw_ack_intr, scope ser, type rw */ -#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 -#define reg_ser_rw_ack_intr___tr_rdy___width 1 -#define reg_ser_rw_ack_intr___tr_rdy___bit 0 -#define reg_ser_rw_ack_intr___tr_empty___lsb 1 -#define reg_ser_rw_ack_intr___tr_empty___width 1 -#define reg_ser_rw_ack_intr___tr_empty___bit 1 -#define reg_ser_rw_ack_intr___tr_idle___lsb 2 -#define reg_ser_rw_ack_intr___tr_idle___width 1 -#define reg_ser_rw_ack_intr___tr_idle___bit 2 -#define reg_ser_rw_ack_intr___dav___lsb 3 -#define reg_ser_rw_ack_intr___dav___width 1 -#define reg_ser_rw_ack_intr___dav___bit 3 -#define reg_ser_rw_ack_intr_offset 48 - -/* Register r_intr, scope ser, type r */ -#define reg_ser_r_intr___tr_rdy___lsb 0 -#define reg_ser_r_intr___tr_rdy___width 1 -#define reg_ser_r_intr___tr_rdy___bit 0 -#define reg_ser_r_intr___tr_empty___lsb 1 -#define reg_ser_r_intr___tr_empty___width 1 -#define reg_ser_r_intr___tr_empty___bit 1 -#define reg_ser_r_intr___tr_idle___lsb 2 -#define reg_ser_r_intr___tr_idle___width 1 -#define reg_ser_r_intr___tr_idle___bit 2 -#define reg_ser_r_intr___dav___lsb 3 -#define reg_ser_r_intr___dav___width 1 -#define reg_ser_r_intr___dav___bit 3 -#define reg_ser_r_intr_offset 52 - -/* Register r_masked_intr, scope ser, type r */ -#define reg_ser_r_masked_intr___tr_rdy___lsb 0 -#define reg_ser_r_masked_intr___tr_rdy___width 1 -#define reg_ser_r_masked_intr___tr_rdy___bit 0 -#define reg_ser_r_masked_intr___tr_empty___lsb 1 -#define reg_ser_r_masked_intr___tr_empty___width 1 -#define reg_ser_r_masked_intr___tr_empty___bit 1 -#define reg_ser_r_masked_intr___tr_idle___lsb 2 -#define reg_ser_r_masked_intr___tr_idle___width 1 -#define reg_ser_r_masked_intr___tr_idle___bit 2 -#define reg_ser_r_masked_intr___dav___lsb 3 -#define reg_ser_r_masked_intr___dav___width 1 -#define reg_ser_r_masked_intr___dav___bit 3 -#define reg_ser_r_masked_intr_offset 56 - - -/* Constants */ -#define regk_ser_active 0x00000000 -#define regk_ser_bits1 0x00000000 -#define regk_ser_bits2 0x00000001 -#define regk_ser_bits7 0x00000001 -#define regk_ser_bits8 0x00000000 -#define regk_ser_del0_5 0x00000000 -#define regk_ser_del1 0x00000001 -#define regk_ser_del1_5 0x00000002 -#define regk_ser_del2 0x00000003 -#define regk_ser_del2_5 0x00000004 -#define regk_ser_del3 0x00000005 -#define regk_ser_del3_5 0x00000006 -#define regk_ser_del4 0x00000007 -#define regk_ser_even 0x00000000 -#define regk_ser_ext 0x00000001 -#define regk_ser_f100 0x00000007 -#define regk_ser_f29_493 0x00000004 -#define regk_ser_f32 0x00000005 -#define regk_ser_f32_768 0x00000006 -#define regk_ser_ignore 0x00000001 -#define regk_ser_inactive 0x00000001 -#define regk_ser_majority 0x00000001 -#define regk_ser_mark 0x00000002 -#define regk_ser_middle 0x00000000 -#define regk_ser_no 0x00000000 -#define regk_ser_odd 0x00000001 -#define regk_ser_off 0x00000000 -#define regk_ser_rw_intr_mask_default 0x00000000 -#define regk_ser_rw_rec_baud_div_default 0x00000000 -#define regk_ser_rw_rec_ctrl_default 0x00010000 -#define regk_ser_rw_tr_baud_div_default 0x00000000 -#define regk_ser_rw_tr_ctrl_default 0x00008000 -#define regk_ser_rw_tr_dma_en_default 0x00000000 -#define regk_ser_rw_xoff_default 0x00000000 -#define regk_ser_space 0x00000003 -#define regk_ser_stop 0x00000000 -#define regk_ser_yes 0x00000001 -#endif /* __ser_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h deleted file mode 100644 index 27d4d91b3abd..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h +++ /dev/null @@ -1,462 +0,0 @@ -#ifndef __sser_defs_asm_h -#define __sser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope sser, type rw */ -#define reg_sser_rw_cfg___clk_div___lsb 0 -#define reg_sser_rw_cfg___clk_div___width 16 -#define reg_sser_rw_cfg___base_freq___lsb 16 -#define reg_sser_rw_cfg___base_freq___width 3 -#define reg_sser_rw_cfg___gate_clk___lsb 19 -#define reg_sser_rw_cfg___gate_clk___width 1 -#define reg_sser_rw_cfg___gate_clk___bit 19 -#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 -#define reg_sser_rw_cfg___clkgate_ctrl___width 1 -#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 -#define reg_sser_rw_cfg___clkgate_in___lsb 21 -#define reg_sser_rw_cfg___clkgate_in___width 1 -#define reg_sser_rw_cfg___clkgate_in___bit 21 -#define reg_sser_rw_cfg___clk_dir___lsb 22 -#define reg_sser_rw_cfg___clk_dir___width 1 -#define reg_sser_rw_cfg___clk_dir___bit 22 -#define reg_sser_rw_cfg___clk_od_mode___lsb 23 -#define reg_sser_rw_cfg___clk_od_mode___width 1 -#define reg_sser_rw_cfg___clk_od_mode___bit 23 -#define reg_sser_rw_cfg___out_clk_pol___lsb 24 -#define reg_sser_rw_cfg___out_clk_pol___width 1 -#define reg_sser_rw_cfg___out_clk_pol___bit 24 -#define reg_sser_rw_cfg___out_clk_src___lsb 25 -#define reg_sser_rw_cfg___out_clk_src___width 2 -#define reg_sser_rw_cfg___clk_in_sel___lsb 27 -#define reg_sser_rw_cfg___clk_in_sel___width 1 -#define reg_sser_rw_cfg___clk_in_sel___bit 27 -#define reg_sser_rw_cfg___hold_pol___lsb 28 -#define reg_sser_rw_cfg___hold_pol___width 1 -#define reg_sser_rw_cfg___hold_pol___bit 28 -#define reg_sser_rw_cfg___prepare___lsb 29 -#define reg_sser_rw_cfg___prepare___width 1 -#define reg_sser_rw_cfg___prepare___bit 29 -#define reg_sser_rw_cfg___en___lsb 30 -#define reg_sser_rw_cfg___en___width 1 -#define reg_sser_rw_cfg___en___bit 30 -#define reg_sser_rw_cfg_offset 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -#define reg_sser_rw_frm_cfg___wordrate___lsb 0 -#define reg_sser_rw_frm_cfg___wordrate___width 10 -#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 -#define reg_sser_rw_frm_cfg___rec_delay___width 3 -#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 -#define reg_sser_rw_frm_cfg___tr_delay___width 3 -#define reg_sser_rw_frm_cfg___early_wend___lsb 16 -#define reg_sser_rw_frm_cfg___early_wend___width 1 -#define reg_sser_rw_frm_cfg___early_wend___bit 16 -#define reg_sser_rw_frm_cfg___level___lsb 17 -#define reg_sser_rw_frm_cfg___level___width 2 -#define reg_sser_rw_frm_cfg___type___lsb 19 -#define reg_sser_rw_frm_cfg___type___width 1 -#define reg_sser_rw_frm_cfg___type___bit 19 -#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 -#define reg_sser_rw_frm_cfg___clk_pol___width 1 -#define reg_sser_rw_frm_cfg___clk_pol___bit 20 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 -#define reg_sser_rw_frm_cfg___clk_src___lsb 22 -#define reg_sser_rw_frm_cfg___clk_src___width 1 -#define reg_sser_rw_frm_cfg___clk_src___bit 22 -#define reg_sser_rw_frm_cfg___out_off___lsb 23 -#define reg_sser_rw_frm_cfg___out_off___width 1 -#define reg_sser_rw_frm_cfg___out_off___bit 23 -#define reg_sser_rw_frm_cfg___out_on___lsb 24 -#define reg_sser_rw_frm_cfg___out_on___width 1 -#define reg_sser_rw_frm_cfg___out_on___bit 24 -#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 -#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 -#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 -#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 -#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 -#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 -#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 -#define reg_sser_rw_frm_cfg___status_pin_use___width 2 -#define reg_sser_rw_frm_cfg_offset 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -#define reg_sser_rw_tr_cfg___tr_en___lsb 0 -#define reg_sser_rw_tr_cfg___tr_en___width 1 -#define reg_sser_rw_tr_cfg___tr_en___bit 0 -#define reg_sser_rw_tr_cfg___stop___lsb 1 -#define reg_sser_rw_tr_cfg___stop___width 1 -#define reg_sser_rw_tr_cfg___stop___bit 1 -#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 -#define reg_sser_rw_tr_cfg___urun_stop___width 1 -#define reg_sser_rw_tr_cfg___urun_stop___bit 2 -#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 -#define reg_sser_rw_tr_cfg___eop_stop___width 1 -#define reg_sser_rw_tr_cfg___eop_stop___bit 3 -#define reg_sser_rw_tr_cfg___sample_size___lsb 4 -#define reg_sser_rw_tr_cfg___sample_size___width 6 -#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 -#define reg_sser_rw_tr_cfg___sh_dir___width 1 -#define reg_sser_rw_tr_cfg___sh_dir___bit 10 -#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 -#define reg_sser_rw_tr_cfg___clk_pol___width 1 -#define reg_sser_rw_tr_cfg___clk_pol___bit 11 -#define reg_sser_rw_tr_cfg___clk_src___lsb 12 -#define reg_sser_rw_tr_cfg___clk_src___width 1 -#define reg_sser_rw_tr_cfg___clk_src___bit 12 -#define reg_sser_rw_tr_cfg___use_dma___lsb 13 -#define reg_sser_rw_tr_cfg___use_dma___width 1 -#define reg_sser_rw_tr_cfg___use_dma___bit 13 -#define reg_sser_rw_tr_cfg___mode___lsb 14 -#define reg_sser_rw_tr_cfg___mode___width 2 -#define reg_sser_rw_tr_cfg___frm_src___lsb 16 -#define reg_sser_rw_tr_cfg___frm_src___width 1 -#define reg_sser_rw_tr_cfg___frm_src___bit 16 -#define reg_sser_rw_tr_cfg___use60958___lsb 17 -#define reg_sser_rw_tr_cfg___use60958___width 1 -#define reg_sser_rw_tr_cfg___use60958___bit 17 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 -#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 -#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 -#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 -#define reg_sser_rw_tr_cfg___use_md___lsb 21 -#define reg_sser_rw_tr_cfg___use_md___width 1 -#define reg_sser_rw_tr_cfg___use_md___bit 21 -#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 -#define reg_sser_rw_tr_cfg___dual_i2s___width 1 -#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 -#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 -#define reg_sser_rw_tr_cfg___data_pin_use___width 2 -#define reg_sser_rw_tr_cfg___od_mode___lsb 25 -#define reg_sser_rw_tr_cfg___od_mode___width 1 -#define reg_sser_rw_tr_cfg___od_mode___bit 25 -#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 -#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 -#define reg_sser_rw_tr_cfg_offset 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -#define reg_sser_rw_rec_cfg___rec_en___lsb 0 -#define reg_sser_rw_rec_cfg___rec_en___width 1 -#define reg_sser_rw_rec_cfg___rec_en___bit 0 -#define reg_sser_rw_rec_cfg___force_eop___lsb 1 -#define reg_sser_rw_rec_cfg___force_eop___width 1 -#define reg_sser_rw_rec_cfg___force_eop___bit 1 -#define reg_sser_rw_rec_cfg___stop___lsb 2 -#define reg_sser_rw_rec_cfg___stop___width 1 -#define reg_sser_rw_rec_cfg___stop___bit 2 -#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 -#define reg_sser_rw_rec_cfg___orun_stop___width 1 -#define reg_sser_rw_rec_cfg___orun_stop___bit 3 -#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 -#define reg_sser_rw_rec_cfg___eop_stop___width 1 -#define reg_sser_rw_rec_cfg___eop_stop___bit 4 -#define reg_sser_rw_rec_cfg___sample_size___lsb 5 -#define reg_sser_rw_rec_cfg___sample_size___width 6 -#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 -#define reg_sser_rw_rec_cfg___sh_dir___width 1 -#define reg_sser_rw_rec_cfg___sh_dir___bit 11 -#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 -#define reg_sser_rw_rec_cfg___clk_pol___width 1 -#define reg_sser_rw_rec_cfg___clk_pol___bit 12 -#define reg_sser_rw_rec_cfg___clk_src___lsb 13 -#define reg_sser_rw_rec_cfg___clk_src___width 1 -#define reg_sser_rw_rec_cfg___clk_src___bit 13 -#define reg_sser_rw_rec_cfg___use_dma___lsb 14 -#define reg_sser_rw_rec_cfg___use_dma___width 1 -#define reg_sser_rw_rec_cfg___use_dma___bit 14 -#define reg_sser_rw_rec_cfg___mode___lsb 15 -#define reg_sser_rw_rec_cfg___mode___width 2 -#define reg_sser_rw_rec_cfg___frm_src___lsb 17 -#define reg_sser_rw_rec_cfg___frm_src___width 2 -#define reg_sser_rw_rec_cfg___use60958___lsb 19 -#define reg_sser_rw_rec_cfg___use60958___width 1 -#define reg_sser_rw_rec_cfg___use60958___bit 19 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 -#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 -#define reg_sser_rw_rec_cfg___slave2_en___width 1 -#define reg_sser_rw_rec_cfg___slave2_en___bit 25 -#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 -#define reg_sser_rw_rec_cfg___slave3_en___width 1 -#define reg_sser_rw_rec_cfg___slave3_en___bit 26 -#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 -#define reg_sser_rw_rec_cfg___fifo_thr___width 2 -#define reg_sser_rw_rec_cfg_offset 12 - -/* Register rw_tr_data, scope sser, type rw */ -#define reg_sser_rw_tr_data___data___lsb 0 -#define reg_sser_rw_tr_data___data___width 16 -#define reg_sser_rw_tr_data___md___lsb 16 -#define reg_sser_rw_tr_data___md___width 1 -#define reg_sser_rw_tr_data___md___bit 16 -#define reg_sser_rw_tr_data_offset 16 - -/* Register r_rec_data, scope sser, type r */ -#define reg_sser_r_rec_data___data___lsb 0 -#define reg_sser_r_rec_data___data___width 16 -#define reg_sser_r_rec_data___md___lsb 16 -#define reg_sser_r_rec_data___md___width 1 -#define reg_sser_r_rec_data___md___bit 16 -#define reg_sser_r_rec_data___ext_clk___lsb 17 -#define reg_sser_r_rec_data___ext_clk___width 1 -#define reg_sser_r_rec_data___ext_clk___bit 17 -#define reg_sser_r_rec_data___status_in___lsb 18 -#define reg_sser_r_rec_data___status_in___width 1 -#define reg_sser_r_rec_data___status_in___bit 18 -#define reg_sser_r_rec_data___frame_in___lsb 19 -#define reg_sser_r_rec_data___frame_in___width 1 -#define reg_sser_r_rec_data___frame_in___bit 19 -#define reg_sser_r_rec_data___din___lsb 20 -#define reg_sser_r_rec_data___din___width 1 -#define reg_sser_r_rec_data___din___bit 20 -#define reg_sser_r_rec_data___data_in___lsb 21 -#define reg_sser_r_rec_data___data_in___width 1 -#define reg_sser_r_rec_data___data_in___bit 21 -#define reg_sser_r_rec_data___clk_in___lsb 22 -#define reg_sser_r_rec_data___clk_in___width 1 -#define reg_sser_r_rec_data___clk_in___bit 22 -#define reg_sser_r_rec_data_offset 20 - -/* Register rw_extra, scope sser, type rw */ -#define reg_sser_rw_extra___clkoff_cycles___lsb 0 -#define reg_sser_rw_extra___clkoff_cycles___width 20 -#define reg_sser_rw_extra___clkoff_en___lsb 20 -#define reg_sser_rw_extra___clkoff_en___width 1 -#define reg_sser_rw_extra___clkoff_en___bit 20 -#define reg_sser_rw_extra___clkon_en___lsb 21 -#define reg_sser_rw_extra___clkon_en___width 1 -#define reg_sser_rw_extra___clkon_en___bit 21 -#define reg_sser_rw_extra___dout_delay___lsb 22 -#define reg_sser_rw_extra___dout_delay___width 5 -#define reg_sser_rw_extra_offset 24 - -/* Register rw_intr_mask, scope sser, type rw */ -#define reg_sser_rw_intr_mask___trdy___lsb 0 -#define reg_sser_rw_intr_mask___trdy___width 1 -#define reg_sser_rw_intr_mask___trdy___bit 0 -#define reg_sser_rw_intr_mask___rdav___lsb 1 -#define reg_sser_rw_intr_mask___rdav___width 1 -#define reg_sser_rw_intr_mask___rdav___bit 1 -#define reg_sser_rw_intr_mask___tidle___lsb 2 -#define reg_sser_rw_intr_mask___tidle___width 1 -#define reg_sser_rw_intr_mask___tidle___bit 2 -#define reg_sser_rw_intr_mask___rstop___lsb 3 -#define reg_sser_rw_intr_mask___rstop___width 1 -#define reg_sser_rw_intr_mask___rstop___bit 3 -#define reg_sser_rw_intr_mask___urun___lsb 4 -#define reg_sser_rw_intr_mask___urun___width 1 -#define reg_sser_rw_intr_mask___urun___bit 4 -#define reg_sser_rw_intr_mask___orun___lsb 5 -#define reg_sser_rw_intr_mask___orun___width 1 -#define reg_sser_rw_intr_mask___orun___bit 5 -#define reg_sser_rw_intr_mask___md_rec___lsb 6 -#define reg_sser_rw_intr_mask___md_rec___width 1 -#define reg_sser_rw_intr_mask___md_rec___bit 6 -#define reg_sser_rw_intr_mask___md_sent___lsb 7 -#define reg_sser_rw_intr_mask___md_sent___width 1 -#define reg_sser_rw_intr_mask___md_sent___bit 7 -#define reg_sser_rw_intr_mask___r958err___lsb 8 -#define reg_sser_rw_intr_mask___r958err___width 1 -#define reg_sser_rw_intr_mask___r958err___bit 8 -#define reg_sser_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope sser, type rw */ -#define reg_sser_rw_ack_intr___trdy___lsb 0 -#define reg_sser_rw_ack_intr___trdy___width 1 -#define reg_sser_rw_ack_intr___trdy___bit 0 -#define reg_sser_rw_ack_intr___rdav___lsb 1 -#define reg_sser_rw_ack_intr___rdav___width 1 -#define reg_sser_rw_ack_intr___rdav___bit 1 -#define reg_sser_rw_ack_intr___tidle___lsb 2 -#define reg_sser_rw_ack_intr___tidle___width 1 -#define reg_sser_rw_ack_intr___tidle___bit 2 -#define reg_sser_rw_ack_intr___rstop___lsb 3 -#define reg_sser_rw_ack_intr___rstop___width 1 -#define reg_sser_rw_ack_intr___rstop___bit 3 -#define reg_sser_rw_ack_intr___urun___lsb 4 -#define reg_sser_rw_ack_intr___urun___width 1 -#define reg_sser_rw_ack_intr___urun___bit 4 -#define reg_sser_rw_ack_intr___orun___lsb 5 -#define reg_sser_rw_ack_intr___orun___width 1 -#define reg_sser_rw_ack_intr___orun___bit 5 -#define reg_sser_rw_ack_intr___md_rec___lsb 6 -#define reg_sser_rw_ack_intr___md_rec___width 1 -#define reg_sser_rw_ack_intr___md_rec___bit 6 -#define reg_sser_rw_ack_intr___md_sent___lsb 7 -#define reg_sser_rw_ack_intr___md_sent___width 1 -#define reg_sser_rw_ack_intr___md_sent___bit 7 -#define reg_sser_rw_ack_intr___r958err___lsb 8 -#define reg_sser_rw_ack_intr___r958err___width 1 -#define reg_sser_rw_ack_intr___r958err___bit 8 -#define reg_sser_rw_ack_intr_offset 32 - -/* Register r_intr, scope sser, type r */ -#define reg_sser_r_intr___trdy___lsb 0 -#define reg_sser_r_intr___trdy___width 1 -#define reg_sser_r_intr___trdy___bit 0 -#define reg_sser_r_intr___rdav___lsb 1 -#define reg_sser_r_intr___rdav___width 1 -#define reg_sser_r_intr___rdav___bit 1 -#define reg_sser_r_intr___tidle___lsb 2 -#define reg_sser_r_intr___tidle___width 1 -#define reg_sser_r_intr___tidle___bit 2 -#define reg_sser_r_intr___rstop___lsb 3 -#define reg_sser_r_intr___rstop___width 1 -#define reg_sser_r_intr___rstop___bit 3 -#define reg_sser_r_intr___urun___lsb 4 -#define reg_sser_r_intr___urun___width 1 -#define reg_sser_r_intr___urun___bit 4 -#define reg_sser_r_intr___orun___lsb 5 -#define reg_sser_r_intr___orun___width 1 -#define reg_sser_r_intr___orun___bit 5 -#define reg_sser_r_intr___md_rec___lsb 6 -#define reg_sser_r_intr___md_rec___width 1 -#define reg_sser_r_intr___md_rec___bit 6 -#define reg_sser_r_intr___md_sent___lsb 7 -#define reg_sser_r_intr___md_sent___width 1 -#define reg_sser_r_intr___md_sent___bit 7 -#define reg_sser_r_intr___r958err___lsb 8 -#define reg_sser_r_intr___r958err___width 1 -#define reg_sser_r_intr___r958err___bit 8 -#define reg_sser_r_intr_offset 36 - -/* Register r_masked_intr, scope sser, type r */ -#define reg_sser_r_masked_intr___trdy___lsb 0 -#define reg_sser_r_masked_intr___trdy___width 1 -#define reg_sser_r_masked_intr___trdy___bit 0 -#define reg_sser_r_masked_intr___rdav___lsb 1 -#define reg_sser_r_masked_intr___rdav___width 1 -#define reg_sser_r_masked_intr___rdav___bit 1 -#define reg_sser_r_masked_intr___tidle___lsb 2 -#define reg_sser_r_masked_intr___tidle___width 1 -#define reg_sser_r_masked_intr___tidle___bit 2 -#define reg_sser_r_masked_intr___rstop___lsb 3 -#define reg_sser_r_masked_intr___rstop___width 1 -#define reg_sser_r_masked_intr___rstop___bit 3 -#define reg_sser_r_masked_intr___urun___lsb 4 -#define reg_sser_r_masked_intr___urun___width 1 -#define reg_sser_r_masked_intr___urun___bit 4 -#define reg_sser_r_masked_intr___orun___lsb 5 -#define reg_sser_r_masked_intr___orun___width 1 -#define reg_sser_r_masked_intr___orun___bit 5 -#define reg_sser_r_masked_intr___md_rec___lsb 6 -#define reg_sser_r_masked_intr___md_rec___width 1 -#define reg_sser_r_masked_intr___md_rec___bit 6 -#define reg_sser_r_masked_intr___md_sent___lsb 7 -#define reg_sser_r_masked_intr___md_sent___width 1 -#define reg_sser_r_masked_intr___md_sent___bit 7 -#define reg_sser_r_masked_intr___r958err___lsb 8 -#define reg_sser_r_masked_intr___r958err___width 1 -#define reg_sser_r_masked_intr___r958err___bit 8 -#define reg_sser_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_sser_both 0x00000002 -#define regk_sser_bulk 0x00000001 -#define regk_sser_clk100 0x00000000 -#define regk_sser_clk_in 0x00000000 -#define regk_sser_const0 0x00000003 -#define regk_sser_dout 0x00000002 -#define regk_sser_edge 0x00000000 -#define regk_sser_ext 0x00000001 -#define regk_sser_ext_clk 0x00000001 -#define regk_sser_f100 0x00000000 -#define regk_sser_f29_493 0x00000004 -#define regk_sser_f32 0x00000005 -#define regk_sser_f32_768 0x00000006 -#define regk_sser_frm 0x00000003 -#define regk_sser_gio0 0x00000000 -#define regk_sser_gio1 0x00000001 -#define regk_sser_hispeed 0x00000001 -#define regk_sser_hold 0x00000002 -#define regk_sser_in 0x00000000 -#define regk_sser_inf 0x00000003 -#define regk_sser_intern 0x00000000 -#define regk_sser_intern_clk 0x00000001 -#define regk_sser_intern_tb 0x00000000 -#define regk_sser_iso 0x00000000 -#define regk_sser_level 0x00000001 -#define regk_sser_lospeed 0x00000000 -#define regk_sser_lsbfirst 0x00000000 -#define regk_sser_msbfirst 0x00000001 -#define regk_sser_neg 0x00000001 -#define regk_sser_neg_lo 0x00000000 -#define regk_sser_no 0x00000000 -#define regk_sser_no_clk 0x00000007 -#define regk_sser_nojitter 0x00000002 -#define regk_sser_out 0x00000001 -#define regk_sser_pos 0x00000000 -#define regk_sser_pos_hi 0x00000001 -#define regk_sser_rec 0x00000000 -#define regk_sser_rw_cfg_default 0x00000000 -#define regk_sser_rw_extra_default 0x00000000 -#define regk_sser_rw_frm_cfg_default 0x00000000 -#define regk_sser_rw_intr_mask_default 0x00000000 -#define regk_sser_rw_rec_cfg_default 0x00000000 -#define regk_sser_rw_tr_cfg_default 0x01800000 -#define regk_sser_rw_tr_data_default 0x00000000 -#define regk_sser_thr16 0x00000001 -#define regk_sser_thr32 0x00000002 -#define regk_sser_thr8 0x00000000 -#define regk_sser_tr 0x00000001 -#define regk_sser_ts_out 0x00000003 -#define regk_sser_tx_bulk 0x00000002 -#define regk_sser_wiresave 0x00000002 -#define regk_sser_yes 0x00000001 -#endif /* __sser_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h deleted file mode 100644 index 55083e6aec93..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef __strcop_defs_asm_h -#define __strcop_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strcop, type rw */ -#define reg_strcop_rw_cfg___td3___lsb 0 -#define reg_strcop_rw_cfg___td3___width 1 -#define reg_strcop_rw_cfg___td3___bit 0 -#define reg_strcop_rw_cfg___td2___lsb 1 -#define reg_strcop_rw_cfg___td2___width 1 -#define reg_strcop_rw_cfg___td2___bit 1 -#define reg_strcop_rw_cfg___td1___lsb 2 -#define reg_strcop_rw_cfg___td1___width 1 -#define reg_strcop_rw_cfg___td1___bit 2 -#define reg_strcop_rw_cfg___ipend___lsb 3 -#define reg_strcop_rw_cfg___ipend___width 1 -#define reg_strcop_rw_cfg___ipend___bit 3 -#define reg_strcop_rw_cfg___ignore_sync___lsb 4 -#define reg_strcop_rw_cfg___ignore_sync___width 1 -#define reg_strcop_rw_cfg___ignore_sync___bit 4 -#define reg_strcop_rw_cfg___en___lsb 5 -#define reg_strcop_rw_cfg___en___width 1 -#define reg_strcop_rw_cfg___en___bit 5 -#define reg_strcop_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strcop_big 0x00000001 -#define regk_strcop_d 0x00000001 -#define regk_strcop_e 0x00000000 -#define regk_strcop_little 0x00000000 -#define regk_strcop_rw_cfg_default 0x00000002 -#endif /* __strcop_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h deleted file mode 100644 index 69b299920f71..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h +++ /dev/null @@ -1,100 +0,0 @@ -#ifndef __strmux_defs_asm_h -#define __strmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strmux, type rw */ -#define reg_strmux_rw_cfg___dma0___lsb 0 -#define reg_strmux_rw_cfg___dma0___width 3 -#define reg_strmux_rw_cfg___dma1___lsb 3 -#define reg_strmux_rw_cfg___dma1___width 3 -#define reg_strmux_rw_cfg___dma2___lsb 6 -#define reg_strmux_rw_cfg___dma2___width 3 -#define reg_strmux_rw_cfg___dma3___lsb 9 -#define reg_strmux_rw_cfg___dma3___width 3 -#define reg_strmux_rw_cfg___dma4___lsb 12 -#define reg_strmux_rw_cfg___dma4___width 3 -#define reg_strmux_rw_cfg___dma5___lsb 15 -#define reg_strmux_rw_cfg___dma5___width 3 -#define reg_strmux_rw_cfg___dma6___lsb 18 -#define reg_strmux_rw_cfg___dma6___width 3 -#define reg_strmux_rw_cfg___dma7___lsb 21 -#define reg_strmux_rw_cfg___dma7___width 3 -#define reg_strmux_rw_cfg___dma8___lsb 24 -#define reg_strmux_rw_cfg___dma8___width 3 -#define reg_strmux_rw_cfg___dma9___lsb 27 -#define reg_strmux_rw_cfg___dma9___width 3 -#define reg_strmux_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strmux_ata 0x00000003 -#define regk_strmux_eth0 0x00000001 -#define regk_strmux_eth1 0x00000004 -#define regk_strmux_ext0 0x00000001 -#define regk_strmux_ext1 0x00000001 -#define regk_strmux_ext2 0x00000001 -#define regk_strmux_ext3 0x00000001 -#define regk_strmux_iop0 0x00000002 -#define regk_strmux_iop1 0x00000001 -#define regk_strmux_off 0x00000000 -#define regk_strmux_p21 0x00000004 -#define regk_strmux_rw_cfg_default 0x00000000 -#define regk_strmux_ser0 0x00000002 -#define regk_strmux_ser1 0x00000002 -#define regk_strmux_ser2 0x00000004 -#define regk_strmux_ser3 0x00000003 -#define regk_strmux_sser0 0x00000003 -#define regk_strmux_sser1 0x00000003 -#define regk_strmux_strcop 0x00000002 -#endif /* __strmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 43146021fc16..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,229 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h deleted file mode 100644 index 43b6643ff0d3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/ata_defs.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef __ata_defs_h -#define __ata_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ata */ - -/* Register rw_ctrl0, scope ata, type rw */ -typedef struct { - unsigned int pio_hold : 6; - unsigned int pio_strb : 6; - unsigned int pio_setup : 6; - unsigned int dma_hold : 6; - unsigned int dma_strb : 6; - unsigned int rst : 1; - unsigned int en : 1; -} reg_ata_rw_ctrl0; -#define REG_RD_ADDR_ata_rw_ctrl0 12 -#define REG_WR_ADDR_ata_rw_ctrl0 12 - -/* Register rw_ctrl1, scope ata, type rw */ -typedef struct { - unsigned int udma_tcyc : 4; - unsigned int udma_tdvs : 4; - unsigned int dummy1 : 24; -} reg_ata_rw_ctrl1; -#define REG_RD_ADDR_ata_rw_ctrl1 16 -#define REG_WR_ADDR_ata_rw_ctrl1 16 - -/* Register rw_ctrl2, scope ata, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 3; - unsigned int dma_size : 1; - unsigned int multi : 1; - unsigned int hsh : 2; - unsigned int trf_mode : 1; - unsigned int rw : 1; - unsigned int addr : 3; - unsigned int cs0 : 1; - unsigned int cs1 : 1; - unsigned int sel : 2; -} reg_ata_rw_ctrl2; -#define REG_RD_ADDR_ata_rw_ctrl2 0 -#define REG_WR_ADDR_ata_rw_ctrl2 0 - -/* Register rs_stat_data, scope ata, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_rs_stat_data; -#define REG_RD_ADDR_ata_rs_stat_data 4 - -/* Register r_stat_data, scope ata, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_r_stat_data; -#define REG_RD_ADDR_ata_r_stat_data 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -typedef struct { - unsigned int cnt : 17; - unsigned int dummy1 : 15; -} reg_ata_rw_trf_cnt; -#define REG_RD_ADDR_ata_rw_trf_cnt 20 -#define REG_WR_ADDR_ata_rw_trf_cnt 20 - -/* Register r_stat_misc, scope ata, type r */ -typedef struct { - unsigned int crc : 16; - unsigned int dummy1 : 16; -} reg_ata_r_stat_misc; -#define REG_RD_ADDR_ata_r_stat_misc 24 - -/* Register rw_intr_mask, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_intr_mask; -#define REG_RD_ADDR_ata_rw_intr_mask 28 -#define REG_WR_ADDR_ata_rw_intr_mask 28 - -/* Register rw_ack_intr, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_ack_intr; -#define REG_RD_ADDR_ata_rw_ack_intr 32 -#define REG_WR_ADDR_ata_rw_ack_intr 32 - -/* Register r_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_intr; -#define REG_RD_ADDR_ata_r_intr 36 - -/* Register r_masked_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_masked_intr; -#define REG_RD_ADDR_ata_r_masked_intr 40 - - -/* Constants */ -enum { - regk_ata_active = 0x00000001, - regk_ata_byte = 0x00000001, - regk_ata_data = 0x00000001, - regk_ata_dma = 0x00000001, - regk_ata_inactive = 0x00000000, - regk_ata_no = 0x00000000, - regk_ata_nodata = 0x00000000, - regk_ata_pio = 0x00000000, - regk_ata_rd = 0x00000001, - regk_ata_reg = 0x00000000, - regk_ata_rw_ctrl0_default = 0x00000000, - regk_ata_rw_ctrl2_default = 0x00000000, - regk_ata_rw_intr_mask_default = 0x00000000, - regk_ata_udma = 0x00000002, - regk_ata_word = 0x00000000, - regk_ata_wr = 0x00000000, - regk_ata_yes = 0x00000001 -}; -#endif /* __ata_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h deleted file mode 100644 index a56608b50359..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h +++ /dev/null @@ -1,284 +0,0 @@ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h deleted file mode 100644 index b931c1aab679..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,473 +0,0 @@ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h deleted file mode 100644 index d18fc3c9f569..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h deleted file mode 100644 index 45457a4e3817..000000000000 --- a/include/asm-cris/arch-v32/hwregs/config_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/include/asm-cris/arch-v32/hwregs/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h deleted file mode 100644 index 3ce322b5c731..000000000000 --- a/include/asm-cris/arch-v32/hwregs/dma.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * DMA C definitions and help macros - * - */ - -#ifndef dma_h -#define dma_h - -/* registers */ /* Really needed, since both are listed in sw.list? */ -#include "dma_defs.h" - - -/* descriptors */ - -// ------------------------------------------------------------ dma_descr_group -typedef struct dma_descr_group { - struct dma_descr_group *next; - unsigned eol : 1; - unsigned tol : 1; - unsigned bol : 1; - unsigned : 1; - unsigned intr : 1; - unsigned : 2; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md : 16; - struct dma_descr_group *up; - union { - struct dma_descr_context *context; - struct dma_descr_group *group; - } down; -} dma_descr_group; - -// ---------------------------------------------------------- dma_descr_context -typedef struct dma_descr_context { - struct dma_descr_context *next; - unsigned eol : 1; - unsigned : 3; - unsigned intr : 1; - unsigned : 1; - unsigned store_mode : 1; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md0 : 16; - unsigned md1; - unsigned md2; - unsigned md3; - unsigned md4; - struct dma_descr_data *saved_data; - char *saved_data_buf; -} dma_descr_context; - -// ------------------------------------------------------------- dma_descr_data -typedef struct dma_descr_data { - struct dma_descr_data *next; - char *buf; - unsigned eol : 1; - unsigned : 2; - unsigned out_eop : 1; - unsigned intr : 1; - unsigned wait : 1; - unsigned : 2; - unsigned : 3; - unsigned in_eop : 1; - unsigned : 4; - unsigned md : 16; - char *after; -} dma_descr_data; - -// --------------------------------------------------------------------- macros - -// enable DMA channel -#define DMA_ENABLE( inst ) \ - do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ - e.en = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, e); } while( 0 ) - -// reset DMA channel -#define DMA_RESET( inst ) \ - do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ - r.en = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, r); } while( 0 ) - -// stop DMA channel -#define DMA_STOP( inst ) \ - do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ - s.stop = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, s); } while( 0 ) - -// continue DMA channel operation -#define DMA_CONTINUE( inst ) \ - do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ - c.stop = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, c); } while( 0 ) - -// give stream command -#define DMA_WR_CMD( inst, cmd_par ) \ - do { reg_dma_rw_stream_cmd __x = {0}; \ - do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ - __x.cmd = (cmd_par); \ - REG_WR(dma, inst, rw_stream_cmd, __x); \ - } while (0) - -// load: g,c,d:burst -#define DMA_START_GROUP( inst, group_descr ) \ - do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_g ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// load: c,d:burst -#define DMA_START_CONTEXT( inst, ctx_descr ) \ - do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// if the DMA is at the end of the data list, the last data descr is reloaded -#define DMA_CONTINUE_DATA( inst ) \ -do { reg_dma_rw_cmd c = {0}; \ - c.cont_data = regk_dma_yes;\ - REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h deleted file mode 100644 index 48ac8cef7ebe..000000000000 --- a/include/asm-cris/arch-v32/hwregs/dma_defs.h +++ /dev/null @@ -1,436 +0,0 @@ -#ifndef __dma_defs_h -#define __dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope dma */ - -/* Register rw_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data; -#define REG_RD_ADDR_dma_rw_data 0 -#define REG_WR_ADDR_dma_rw_data 0 - -/* Register rw_data_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_next; -#define REG_RD_ADDR_dma_rw_data_next 4 -#define REG_WR_ADDR_dma_rw_data_next 4 - -/* Register rw_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_buf; -#define REG_RD_ADDR_dma_rw_data_buf 8 -#define REG_WR_ADDR_dma_rw_data_buf 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 2; - unsigned int out_eop : 1; - unsigned int intr : 1; - unsigned int wait : 1; - unsigned int dummy2 : 26; -} reg_dma_rw_data_ctrl; -#define REG_RD_ADDR_dma_rw_data_ctrl 12 -#define REG_WR_ADDR_dma_rw_data_ctrl 12 - -/* Register rw_data_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 3; - unsigned int in_eop : 1; - unsigned int dummy2 : 28; -} reg_dma_rw_data_stat; -#define REG_RD_ADDR_dma_rw_data_stat 16 -#define REG_WR_ADDR_dma_rw_data_stat 16 - -/* Register rw_data_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md; -#define REG_RD_ADDR_dma_rw_data_md 20 -#define REG_WR_ADDR_dma_rw_data_md 20 - -/* Register rw_data_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md_s; -#define REG_RD_ADDR_dma_rw_data_md_s 24 -#define REG_WR_ADDR_dma_rw_data_md_s 24 - -/* Register rw_data_after, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_after; -#define REG_RD_ADDR_dma_rw_data_after 28 -#define REG_WR_ADDR_dma_rw_data_after 28 - -/* Register rw_ctxt, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt; -#define REG_RD_ADDR_dma_rw_ctxt 32 -#define REG_WR_ADDR_dma_rw_ctxt 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_next; -#define REG_RD_ADDR_dma_rw_ctxt_next 36 -#define REG_WR_ADDR_dma_rw_ctxt_next 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 3; - unsigned int intr : 1; - unsigned int dummy2 : 1; - unsigned int store_mode : 1; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_ctxt_ctrl; -#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 -#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_ctxt_stat; -#define REG_RD_ADDR_dma_rw_ctxt_stat 44 -#define REG_WR_ADDR_dma_rw_ctxt_stat 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -typedef struct { - unsigned int md0 : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0; -#define REG_RD_ADDR_dma_rw_ctxt_md0 48 -#define REG_WR_ADDR_dma_rw_ctxt_md0 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -typedef struct { - unsigned int md0_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0_s; -#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 -#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1; -#define REG_RD_ADDR_dma_rw_ctxt_md1 56 -#define REG_WR_ADDR_dma_rw_ctxt_md1 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1_s; -#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 -#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2; -#define REG_RD_ADDR_dma_rw_ctxt_md2 64 -#define REG_WR_ADDR_dma_rw_ctxt_md2 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2_s; -#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 -#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3; -#define REG_RD_ADDR_dma_rw_ctxt_md3 72 -#define REG_WR_ADDR_dma_rw_ctxt_md3 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3_s; -#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 -#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4; -#define REG_RD_ADDR_dma_rw_ctxt_md4 80 -#define REG_WR_ADDR_dma_rw_ctxt_md4 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4_s; -#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 -#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 - -/* Register rw_saved_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data; -#define REG_RD_ADDR_dma_rw_saved_data 88 -#define REG_WR_ADDR_dma_rw_saved_data 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data_buf; -#define REG_RD_ADDR_dma_rw_saved_data_buf 92 -#define REG_WR_ADDR_dma_rw_saved_data_buf 92 - -/* Register rw_group, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group; -#define REG_RD_ADDR_dma_rw_group 96 -#define REG_WR_ADDR_dma_rw_group 96 - -/* Register rw_group_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_next; -#define REG_RD_ADDR_dma_rw_group_next 100 -#define REG_WR_ADDR_dma_rw_group_next 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int tol : 1; - unsigned int bol : 1; - unsigned int dummy1 : 1; - unsigned int intr : 1; - unsigned int dummy2 : 2; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_group_ctrl; -#define REG_RD_ADDR_dma_rw_group_ctrl 104 -#define REG_WR_ADDR_dma_rw_group_ctrl 104 - -/* Register rw_group_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_group_stat; -#define REG_RD_ADDR_dma_rw_group_stat 108 -#define REG_WR_ADDR_dma_rw_group_stat 108 - -/* Register rw_group_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md; -#define REG_RD_ADDR_dma_rw_group_md 112 -#define REG_WR_ADDR_dma_rw_group_md 112 - -/* Register rw_group_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md_s; -#define REG_RD_ADDR_dma_rw_group_md_s 116 -#define REG_WR_ADDR_dma_rw_group_md_s 116 - -/* Register rw_group_up, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_up; -#define REG_RD_ADDR_dma_rw_group_up 120 -#define REG_WR_ADDR_dma_rw_group_up 120 - -/* Register rw_group_down, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_down; -#define REG_RD_ADDR_dma_rw_group_down 124 -#define REG_WR_ADDR_dma_rw_group_down 124 - -/* Register rw_cmd, scope dma, type rw */ -typedef struct { - unsigned int cont_data : 1; - unsigned int dummy1 : 31; -} reg_dma_rw_cmd; -#define REG_RD_ADDR_dma_rw_cmd 128 -#define REG_WR_ADDR_dma_rw_cmd 128 - -/* Register rw_cfg, scope dma, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int stop : 1; - unsigned int dummy1 : 30; -} reg_dma_rw_cfg; -#define REG_RD_ADDR_dma_rw_cfg 132 -#define REG_WR_ADDR_dma_rw_cfg 132 - -/* Register rw_stat, scope dma, type rw */ -typedef struct { - unsigned int mode : 5; - unsigned int list_state : 3; - unsigned int stream_cmd_src : 8; - unsigned int dummy1 : 8; - unsigned int buf : 8; -} reg_dma_rw_stat; -#define REG_RD_ADDR_dma_rw_stat 136 -#define REG_WR_ADDR_dma_rw_stat 136 - -/* Register rw_intr_mask, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_intr_mask; -#define REG_RD_ADDR_dma_rw_intr_mask 140 -#define REG_WR_ADDR_dma_rw_intr_mask 140 - -/* Register rw_ack_intr, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_ack_intr; -#define REG_RD_ADDR_dma_rw_ack_intr 144 -#define REG_WR_ADDR_dma_rw_ack_intr 144 - -/* Register r_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_intr; -#define REG_RD_ADDR_dma_r_intr 148 - -/* Register r_masked_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_masked_intr; -#define REG_RD_ADDR_dma_r_masked_intr 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 7; - unsigned int busy : 1; -} reg_dma_rw_stream_cmd; -#define REG_RD_ADDR_dma_rw_stream_cmd 156 -#define REG_WR_ADDR_dma_rw_stream_cmd 156 - - -/* Constants */ -enum { - regk_dma_ack_pkt = 0x00000100, - regk_dma_anytime = 0x00000001, - regk_dma_array = 0x00000008, - regk_dma_burst = 0x00000020, - regk_dma_client = 0x00000002, - regk_dma_copy_next = 0x00000010, - regk_dma_copy_up = 0x00000020, - regk_dma_data_at_eol = 0x00000001, - regk_dma_dis_c = 0x00000010, - regk_dma_dis_g = 0x00000020, - regk_dma_idle = 0x00000001, - regk_dma_intern = 0x00000004, - regk_dma_load_c = 0x00000200, - regk_dma_load_c_n = 0x00000280, - regk_dma_load_c_next = 0x00000240, - regk_dma_load_d = 0x00000140, - regk_dma_load_g = 0x00000300, - regk_dma_load_g_down = 0x000003c0, - regk_dma_load_g_next = 0x00000340, - regk_dma_load_g_up = 0x00000380, - regk_dma_next_en = 0x00000010, - regk_dma_next_pkt = 0x00000010, - regk_dma_no = 0x00000000, - regk_dma_only_at_wait = 0x00000000, - regk_dma_restore = 0x00000020, - regk_dma_rst = 0x00000001, - regk_dma_running = 0x00000004, - regk_dma_rw_cfg_default = 0x00000000, - regk_dma_rw_cmd_default = 0x00000000, - regk_dma_rw_intr_mask_default = 0x00000000, - regk_dma_rw_stat_default = 0x00000101, - regk_dma_rw_stream_cmd_default = 0x00000000, - regk_dma_save_down = 0x00000020, - regk_dma_save_up = 0x00000020, - regk_dma_set_reg = 0x00000050, - regk_dma_set_w_size1 = 0x00000190, - regk_dma_set_w_size2 = 0x000001a0, - regk_dma_set_w_size4 = 0x000001c0, - regk_dma_stopped = 0x00000002, - regk_dma_store_c = 0x00000002, - regk_dma_store_descr = 0x00000000, - regk_dma_store_g = 0x00000004, - regk_dma_store_md = 0x00000001, - regk_dma_sw = 0x00000008, - regk_dma_update_down = 0x00000020, - regk_dma_yes = 0x00000001 -}; -#endif /* __dma_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h deleted file mode 100644 index 90fe8a28894f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ /dev/null @@ -1,378 +0,0 @@ -#ifndef __eth_defs_h -#define __eth_defs_h - -/* - * This file is autogenerated from - * file: eth.r - * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp - * last modfied: Mon Jan 9 06:06:41 2006 - * - * by /n/asic/design/tools/rdesc/rdes2c eth.r - * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope eth */ - -/* Register rw_ma0_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma0_lo; -#define REG_RD_ADDR_eth_rw_ma0_lo 0 -#define REG_WR_ADDR_eth_rw_ma0_lo 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma0_hi; -#define REG_RD_ADDR_eth_rw_ma0_hi 4 -#define REG_WR_ADDR_eth_rw_ma0_hi 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma1_lo; -#define REG_RD_ADDR_eth_rw_ma1_lo 8 -#define REG_WR_ADDR_eth_rw_ma1_lo 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma1_hi; -#define REG_RD_ADDR_eth_rw_ma1_hi 12 -#define REG_WR_ADDR_eth_rw_ma1_hi 12 - -/* Register rw_ga_lo, scope eth, type rw */ -typedef struct { - unsigned int tbl : 32; -} reg_eth_rw_ga_lo; -#define REG_RD_ADDR_eth_rw_ga_lo 16 -#define REG_WR_ADDR_eth_rw_ga_lo 16 - -/* Register rw_ga_hi, scope eth, type rw */ -typedef struct { - unsigned int tbl : 32; -} reg_eth_rw_ga_hi; -#define REG_RD_ADDR_eth_rw_ga_hi 20 -#define REG_WR_ADDR_eth_rw_ga_hi 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int phy : 2; - unsigned int protocol : 1; - unsigned int loopback : 1; - unsigned int flow_ctrl : 1; - unsigned int gtxclk_out : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 24; -} reg_eth_rw_gen_ctrl; -#define REG_RD_ADDR_eth_rw_gen_ctrl 24 -#define REG_WR_ADDR_eth_rw_gen_ctrl 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -typedef struct { - unsigned int ma0 : 1; - unsigned int ma1 : 1; - unsigned int individual : 1; - unsigned int broadcast : 1; - unsigned int undersize : 1; - unsigned int oversize : 1; - unsigned int bad_crc : 1; - unsigned int duplex : 1; - unsigned int max_size : 16; - unsigned int dummy1 : 8; -} reg_eth_rw_rec_ctrl; -#define REG_RD_ADDR_eth_rw_rec_ctrl 28 -#define REG_WR_ADDR_eth_rw_rec_ctrl 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int pad : 1; - unsigned int retry : 1; - unsigned int ignore_col : 1; - unsigned int cancel : 1; - unsigned int hsh_delay : 1; - unsigned int ignore_crs : 1; - unsigned int carrier_ext : 1; - unsigned int dummy1 : 24; -} reg_eth_rw_tr_ctrl; -#define REG_RD_ADDR_eth_rw_tr_ctrl 32 -#define REG_WR_ADDR_eth_rw_tr_ctrl 32 - -/* Register rw_clr_err, scope eth, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_eth_rw_clr_err; -#define REG_RD_ADDR_eth_rw_clr_err 36 -#define REG_WR_ADDR_eth_rw_clr_err 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -typedef struct { - unsigned int mdio : 1; - unsigned int mdoe : 1; - unsigned int mdc : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_mgm_ctrl; -#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 -#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 - -/* Register r_stat, scope eth, type r */ -typedef struct { - unsigned int mdio : 1; - unsigned int exc_col : 1; - unsigned int urun : 1; - unsigned int clk_125 : 1; - unsigned int dummy1 : 28; -} reg_eth_r_stat; -#define REG_RD_ADDR_eth_r_stat 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_rs_rec_cnt; -#define REG_RD_ADDR_eth_rs_rec_cnt 48 - -/* Register r_rec_cnt, scope eth, type r */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_r_rec_cnt; -#define REG_RD_ADDR_eth_r_rec_cnt 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_rs_tr_cnt; -#define REG_RD_ADDR_eth_rs_tr_cnt 56 - -/* Register r_tr_cnt, scope eth, type r */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_r_tr_cnt; -#define REG_RD_ADDR_eth_r_tr_cnt 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_rs_phy_cnt; -#define REG_RD_ADDR_eth_rs_phy_cnt 64 - -/* Register r_phy_cnt, scope eth, type r */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_r_phy_cnt; -#define REG_RD_ADDR_eth_r_phy_cnt 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -typedef struct { - unsigned int snmp_inc : 1; - unsigned int snmp : 1; - unsigned int backoff : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_test_ctrl; -#define REG_RD_ADDR_eth_rw_test_ctrl 72 -#define REG_WR_ADDR_eth_rw_test_ctrl 72 - -/* Register rw_intr_mask, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_intr_mask; -#define REG_RD_ADDR_eth_rw_intr_mask 76 -#define REG_WR_ADDR_eth_rw_intr_mask 76 - -/* Register rw_ack_intr, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_ack_intr; -#define REG_RD_ADDR_eth_rw_ack_intr 80 -#define REG_WR_ADDR_eth_rw_ack_intr 80 - -/* Register r_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_intr; -#define REG_RD_ADDR_eth_r_intr 84 - -/* Register r_masked_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_masked_intr; -#define REG_RD_ADDR_eth_r_masked_intr 88 - - -/* Constants */ -enum { - regk_eth_discard = 0x00000000, - regk_eth_ether = 0x00000000, - regk_eth_full = 0x00000001, - regk_eth_gmii = 0x00000003, - regk_eth_gtxclk = 0x00000001, - regk_eth_half = 0x00000000, - regk_eth_hsh = 0x00000001, - regk_eth_mii = 0x00000001, - regk_eth_mii_arec = 0x00000002, - regk_eth_mii_clk = 0x00000000, - regk_eth_no = 0x00000000, - regk_eth_phyrst = 0x00000000, - regk_eth_rec = 0x00000001, - regk_eth_rw_ga_hi_default = 0x00000000, - regk_eth_rw_ga_lo_default = 0x00000000, - regk_eth_rw_gen_ctrl_default = 0x00000000, - regk_eth_rw_intr_mask_default = 0x00000000, - regk_eth_rw_ma0_hi_default = 0x00000000, - regk_eth_rw_ma0_lo_default = 0x00000000, - regk_eth_rw_ma1_hi_default = 0x00000000, - regk_eth_rw_ma1_lo_default = 0x00000000, - regk_eth_rw_mgm_ctrl_default = 0x00000000, - regk_eth_rw_test_ctrl_default = 0x00000000, - regk_eth_size1518 = 0x000005ee, - regk_eth_size1522 = 0x000005f2, - regk_eth_yes = 0x00000001 -}; -#endif /* __eth_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h deleted file mode 100644 index c47b5ca48ece..000000000000 --- a/include/asm-cris/arch-v32/hwregs/extmem_defs.h +++ /dev/null @@ -1,369 +0,0 @@ -#ifndef __extmem_defs_h -#define __extmem_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ext_mem/mod/extmem_regs.r - * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp - * last modfied: Tue Mar 30 22:26:21 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r - * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope extmem */ - -/* Register rw_cse0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse0_cfg; -#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 -#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 - -/* Register rw_cse1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse1_cfg; -#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 -#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 - -/* Register rw_csr0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr0_cfg; -#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 -#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 - -/* Register rw_csr1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr1_cfg; -#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 -#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 - -/* Register rw_csp0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp0_cfg; -#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 -#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 - -/* Register rw_csp1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp1_cfg; -#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 -#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 - -/* Register rw_csp2_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp2_cfg; -#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 -#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 - -/* Register rw_csp3_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp3_cfg; -#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 -#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 - -/* Register rw_csp4_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp4_cfg; -#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 -#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 - -/* Register rw_csp5_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp5_cfg; -#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 -#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 - -/* Register rw_csp6_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp6_cfg; -#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 -#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 - -/* Register rw_css_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_css_cfg; -#define REG_RD_ADDR_extmem_rw_css_cfg 44 -#define REG_WR_ADDR_extmem_rw_css_cfg 44 - -/* Register rw_status_handle, scope extmem, type rw */ -typedef struct { - unsigned int h : 32; -} reg_extmem_rw_status_handle; -#define REG_RD_ADDR_extmem_rw_status_handle 48 -#define REG_WR_ADDR_extmem_rw_status_handle 48 - -/* Register rw_wait_pin, scope extmem, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 15; - unsigned int start : 1; -} reg_extmem_rw_wait_pin; -#define REG_RD_ADDR_extmem_rw_wait_pin 52 -#define REG_WR_ADDR_extmem_rw_wait_pin 52 - -/* Register rw_gated_csp, scope extmem, type rw */ -typedef struct { - unsigned int dummy1 : 31; - unsigned int en : 1; -} reg_extmem_rw_gated_csp; -#define REG_RD_ADDR_extmem_rw_gated_csp 56 -#define REG_WR_ADDR_extmem_rw_gated_csp 56 - - -/* Constants */ -enum { - regk_extmem_b16 = 0x00000001, - regk_extmem_b32 = 0x00000000, - regk_extmem_bwe = 0x00000000, - regk_extmem_cwe = 0x00000001, - regk_extmem_no = 0x00000000, - regk_extmem_rw_cse0_cfg_default = 0x000006cf, - regk_extmem_rw_cse1_cfg_default = 0x000006cf, - regk_extmem_rw_csp0_cfg_default = 0x000006cf, - regk_extmem_rw_csp1_cfg_default = 0x000006cf, - regk_extmem_rw_csp2_cfg_default = 0x000006cf, - regk_extmem_rw_csp3_cfg_default = 0x000006cf, - regk_extmem_rw_csp4_cfg_default = 0x000006cf, - regk_extmem_rw_csp5_cfg_default = 0x000006cf, - regk_extmem_rw_csp6_cfg_default = 0x000006cf, - regk_extmem_rw_csr0_cfg_default = 0x000006cf, - regk_extmem_rw_csr1_cfg_default = 0x000006cf, - regk_extmem_rw_css_cfg_default = 0x000006cf, - regk_extmem_s128KB = 0x00000000, - regk_extmem_s16MB = 0x00000005, - regk_extmem_s1MB = 0x00000001, - regk_extmem_s2MB = 0x00000002, - regk_extmem_s32MB = 0x00000006, - regk_extmem_s4MB = 0x00000003, - regk_extmem_s64MB = 0x00000007, - regk_extmem_s8MB = 0x00000004, - regk_extmem_yes = 0x00000001 -}; -#endif /* __extmem_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h deleted file mode 100644 index 3e9a0b25366f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/gio_defs.h +++ /dev/null @@ -1,295 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h deleted file mode 100644 index 5c1b28fb205d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/intr_vect.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile deleted file mode 100644 index a90056a095e3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/Makefile +++ /dev/null @@ -1,146 +0,0 @@ -# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The offical place for these files is probably at: -RELEASE ?= r1_alfa5 -IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -IOPROCDIR = /n/asic/design/io/io_proc/rtl - -IOPROCINCL_FILES = -IOPROCINCL_FILES2= -IOPROCINCL_FILES += iop_crc_par_defs.h -IOPROCINCL_FILES += iop_dmc_in_defs.h -IOPROCINCL_FILES += iop_dmc_out_defs.h -IOPROCINCL_FILES += iop_fifo_in_defs.h -IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h -IOPROCINCL_FILES += iop_fifo_out_defs.h -IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h -IOPROCINCL_FILES += iop_mpu_defs.h -IOPROCINCL_FILES2+= iop_mpu_macros.h -IOPROCINCL_FILES2+= iop_reg_space.h -IOPROCINCL_FILES += iop_sap_in_defs.h -IOPROCINCL_FILES += iop_sap_out_defs.h -IOPROCINCL_FILES += iop_scrc_in_defs.h -IOPROCINCL_FILES += iop_scrc_out_defs.h -IOPROCINCL_FILES += iop_spu_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_sw_cfg_defs.h -IOPROCINCL_FILES += iop_sw_cpu_defs.h -IOPROCINCL_FILES += iop_sw_mpu_defs.h -IOPROCINCL_FILES += iop_sw_spu_defs.h -# -IOPROCINCL_FILES += iop_timer_grp_defs.h -IOPROCINCL_FILES += iop_trigger_grp_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_version_defs.h - -IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) -IOPROCASMINCL_FILES+= iop_reg_space_asm.h - - -IOPROCREGDESC = -IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r -#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r -IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r - - -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) - echo "INCL: $(IOPROCINCL_FILES)" - echo "INCL2: $(IOPROCINCL_FILES2)" - echo "ASMINCL: $(IOPROCASMINCL_FILES)" - -# From the official location... -iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -## copy - Copy files from official location -copy: - @echo "## Copying and fixing iop files ##" - @for HFILE in $(IOPROCINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(IOPROCINCL_FILES2); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @echo "## Copying and fixing iop asm files ##" - @for HFILE in $(IOPROCASMINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ - done - -# I/O processor files: -## iop - Generate I/O processor include files -iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) -iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r - $(RDES2C) $< -iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) $< -%_defs.h: $(IOPROCDIR)/%.r - $(RDES2C) $< -%_defs_asm.h: $(IOPROCDIR)/%.r - $(RDES2C) -asm $< -iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) -asm $< - -## doc - Generate .axw files from register description. -doc: $(IOPROCREGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming of .r files. -%.axw: axw - @for RDES in $(IOPROCREGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(IOPROCINCL_FILES) *.axw - -.PHONY: cleandoc -## cleandoc - Remove .axw files. -cleandoc: - rm -rf *.axw - diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h deleted file mode 100644 index a4b58000c164..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef __iop_crc_par_defs_asm_h -#define __iop_crc_par_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_cfg___mode___lsb 0 -#define reg_iop_crc_par_rw_cfg___mode___width 1 -#define reg_iop_crc_par_rw_cfg___mode___bit 0 -#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 -#define reg_iop_crc_par_rw_cfg___crc_out___width 1 -#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 -#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 -#define reg_iop_crc_par_rw_cfg___rev_out___width 1 -#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 -#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 -#define reg_iop_crc_par_rw_cfg___inv_out___width 1 -#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 -#define reg_iop_crc_par_rw_cfg___trig___lsb 4 -#define reg_iop_crc_par_rw_cfg___trig___width 2 -#define reg_iop_crc_par_rw_cfg___poly___lsb 6 -#define reg_iop_crc_par_rw_cfg___poly___width 3 -#define reg_iop_crc_par_rw_cfg_offset 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_init_crc_offset 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_correct_crc_offset 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_ctrl___en___lsb 0 -#define reg_iop_crc_par_rw_ctrl___en___width 1 -#define reg_iop_crc_par_rw_ctrl___en___bit 0 -#define reg_iop_crc_par_rw_ctrl_offset 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 -#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 -#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 -#define reg_iop_crc_par_rw_set_last_offset 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_offset 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_offset 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_offset 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_offset 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_last_offset 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_last_offset 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_last_offset 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_last_offset 48 - -/* Register r_stat, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_stat___err___lsb 0 -#define reg_iop_crc_par_r_stat___err___width 1 -#define reg_iop_crc_par_r_stat___err___bit 0 -#define reg_iop_crc_par_r_stat___busy___lsb 1 -#define reg_iop_crc_par_r_stat___busy___width 1 -#define reg_iop_crc_par_r_stat___busy___bit 1 -#define reg_iop_crc_par_r_stat_offset 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_sh_reg_offset 56 - -/* Register r_crc, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_crc_offset 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 -#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 - - -/* Constants */ -#define regk_iop_crc_par_calc 0x00000001 -#define regk_iop_crc_par_ccitt 0x00000002 -#define regk_iop_crc_par_check 0x00000000 -#define regk_iop_crc_par_crc16 0x00000001 -#define regk_iop_crc_par_crc32 0x00000000 -#define regk_iop_crc_par_crc5 0x00000003 -#define regk_iop_crc_par_crc5_11 0x00000004 -#define regk_iop_crc_par_dif_in 0x00000002 -#define regk_iop_crc_par_hi 0x00000000 -#define regk_iop_crc_par_neg 0x00000002 -#define regk_iop_crc_par_no 0x00000000 -#define regk_iop_crc_par_pos 0x00000001 -#define regk_iop_crc_par_pos_neg 0x00000003 -#define regk_iop_crc_par_rw_cfg_default 0x00000000 -#define regk_iop_crc_par_rw_ctrl_default 0x00000000 -#define regk_iop_crc_par_yes 0x00000001 -#endif /* __iop_crc_par_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h deleted file mode 100644 index e7d539feccb1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef __iop_dmc_in_defs_asm_h -#define __iop_dmc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 -#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 -#define reg_iop_dmc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 -#define reg_iop_dmc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_in_r_stat___dif_en___width 1 -#define reg_iop_dmc_in_r_stat___dif_en___bit 0 -#define reg_iop_dmc_in_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_in_rw_stream_cmd_offset 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 -#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 -#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 -#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 -#define reg_iop_dmc_in_r_stream_stat___sth___width 7 -#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 -#define reg_iop_dmc_in_r_stream_stat___full___width 1 -#define reg_iop_dmc_in_r_stream_stat___full___bit 16 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 -#define reg_iop_dmc_in_r_stream_stat_offset 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_data_descr___stat___width 8 -#define reg_iop_dmc_in_r_data_descr___md___lsb 16 -#define reg_iop_dmc_in_r_data_descr___md___width 16 -#define reg_iop_dmc_in_r_data_descr_offset 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_r_ctxt_descr_offset 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_group_descr___stat___width 8 -#define reg_iop_dmc_in_r_group_descr___md___lsb 16 -#define reg_iop_dmc_in_r_group_descr___md___width 16 -#define reg_iop_dmc_in_r_group_descr_offset 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_data_descr___md___width 16 -#define reg_iop_dmc_in_rw_data_descr_offset 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_group_descr___md___width 16 -#define reg_iop_dmc_in_rw_group_descr_offset 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 -#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 -#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 -#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 -#define reg_iop_dmc_in_rw_intr_mask___full___width 1 -#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 -#define reg_iop_dmc_in_rw_intr_mask_offset 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 -#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 -#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 -#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 -#define reg_iop_dmc_in_rw_ack_intr___full___width 1 -#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 -#define reg_iop_dmc_in_rw_ack_intr_offset 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_intr___data_md___width 1 -#define reg_iop_dmc_in_r_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_intr___group_md___width 1 -#define reg_iop_dmc_in_r_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_intr___sth___width 1 -#define reg_iop_dmc_in_r_intr___sth___bit 4 -#define reg_iop_dmc_in_r_intr___full___lsb 5 -#define reg_iop_dmc_in_r_intr___full___width 1 -#define reg_iop_dmc_in_r_intr___full___bit 5 -#define reg_iop_dmc_in_r_intr_offset 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_masked_intr___sth___width 1 -#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 -#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 -#define reg_iop_dmc_in_r_masked_intr___full___width 1 -#define reg_iop_dmc_in_r_masked_intr___full___bit 5 -#define reg_iop_dmc_in_r_masked_intr_offset 100 - - -/* Constants */ -#define regk_iop_dmc_in_ack_pkt 0x00000100 -#define regk_iop_dmc_in_array 0x00000008 -#define regk_iop_dmc_in_burst 0x00000020 -#define regk_iop_dmc_in_copy_next 0x00000010 -#define regk_iop_dmc_in_copy_up 0x00000020 -#define regk_iop_dmc_in_dis_c 0x00000010 -#define regk_iop_dmc_in_dis_g 0x00000020 -#define regk_iop_dmc_in_lim1 0x00000000 -#define regk_iop_dmc_in_lim16 0x00000004 -#define regk_iop_dmc_in_lim2 0x00000001 -#define regk_iop_dmc_in_lim32 0x00000005 -#define regk_iop_dmc_in_lim4 0x00000002 -#define regk_iop_dmc_in_lim64 0x00000006 -#define regk_iop_dmc_in_lim8 0x00000003 -#define regk_iop_dmc_in_load_c 0x00000200 -#define regk_iop_dmc_in_load_c_n 0x00000280 -#define regk_iop_dmc_in_load_c_next 0x00000240 -#define regk_iop_dmc_in_load_d 0x00000140 -#define regk_iop_dmc_in_load_g 0x00000300 -#define regk_iop_dmc_in_load_g_down 0x000003c0 -#define regk_iop_dmc_in_load_g_next 0x00000340 -#define regk_iop_dmc_in_load_g_up 0x00000380 -#define regk_iop_dmc_in_next_en 0x00000010 -#define regk_iop_dmc_in_next_pkt 0x00000010 -#define regk_iop_dmc_in_no 0x00000000 -#define regk_iop_dmc_in_restore 0x00000020 -#define regk_iop_dmc_in_rw_cfg_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 -#define regk_iop_dmc_in_save_down 0x00000020 -#define regk_iop_dmc_in_save_up 0x00000020 -#define regk_iop_dmc_in_set_reg 0x00000050 -#define regk_iop_dmc_in_set_w_size1 0x00000190 -#define regk_iop_dmc_in_set_w_size2 0x000001a0 -#define regk_iop_dmc_in_set_w_size4 0x000001c0 -#define regk_iop_dmc_in_store_c 0x00000002 -#define regk_iop_dmc_in_store_descr 0x00000000 -#define regk_iop_dmc_in_store_g 0x00000004 -#define regk_iop_dmc_in_store_md 0x00000001 -#define regk_iop_dmc_in_update_down 0x00000020 -#define regk_iop_dmc_in_yes 0x00000001 -#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h deleted file mode 100644 index 9fe1a8054371..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h +++ /dev/null @@ -1,349 +0,0 @@ -#ifndef __iop_dmc_out_defs_asm_h -#define __iop_dmc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 -#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 -#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 -#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 -#define reg_iop_dmc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_out_r_stat___dif_en___width 1 -#define reg_iop_dmc_out_r_stat___dif_en___bit 0 -#define reg_iop_dmc_out_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_out_rw_stream_cmd_offset 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -#define reg_iop_dmc_out_rs_stream_data_offset 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_data_offset 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 -#define reg_iop_dmc_out_r_stream_stat___dth___width 7 -#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 -#define reg_iop_dmc_out_r_stream_stat___dv___width 1 -#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 -#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 -#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 -#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 -#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 -#define reg_iop_dmc_out_r_stream_stat___last___width 1 -#define reg_iop_dmc_out_r_stream_stat___last___bit 18 -#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 -#define reg_iop_dmc_out_r_stream_stat___size___width 3 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 -#define reg_iop_dmc_out_r_stream_stat_offset 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_data_descr___stat___width 8 -#define reg_iop_dmc_out_r_data_descr___md___lsb 16 -#define reg_iop_dmc_out_r_data_descr___md___width 16 -#define reg_iop_dmc_out_r_data_descr_offset 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_r_ctxt_descr_offset 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_group_descr___stat___width 8 -#define reg_iop_dmc_out_r_group_descr___md___lsb 16 -#define reg_iop_dmc_out_r_group_descr___md___width 16 -#define reg_iop_dmc_out_r_group_descr_offset 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_data_descr___md___width 16 -#define reg_iop_dmc_out_rw_data_descr_offset 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_group_descr___md___width 16 -#define reg_iop_dmc_out_rw_group_descr_offset 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 -#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 -#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 -#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 -#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 -#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 -#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_intr_mask_offset 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 -#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 -#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 -#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 -#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 -#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 -#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_ack_intr_offset 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_intr___data_md___width 1 -#define reg_iop_dmc_out_r_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_intr___group_md___width 1 -#define reg_iop_dmc_out_r_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_intr___dth___width 1 -#define reg_iop_dmc_out_r_intr___dth___bit 4 -#define reg_iop_dmc_out_r_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_intr___dv___width 1 -#define reg_iop_dmc_out_r_intr___dv___bit 5 -#define reg_iop_dmc_out_r_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_intr___last_data___width 1 -#define reg_iop_dmc_out_r_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_intr_offset 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_masked_intr___dth___width 1 -#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 -#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_masked_intr___dv___width 1 -#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 -#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 -#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_masked_intr_offset 96 - - -/* Constants */ -#define regk_iop_dmc_out_ack_pkt 0x00000100 -#define regk_iop_dmc_out_array 0x00000008 -#define regk_iop_dmc_out_burst 0x00000020 -#define regk_iop_dmc_out_copy_next 0x00000010 -#define regk_iop_dmc_out_copy_up 0x00000020 -#define regk_iop_dmc_out_dis_c 0x00000010 -#define regk_iop_dmc_out_dis_g 0x00000020 -#define regk_iop_dmc_out_lim1 0x00000000 -#define regk_iop_dmc_out_lim16 0x00000004 -#define regk_iop_dmc_out_lim2 0x00000001 -#define regk_iop_dmc_out_lim32 0x00000005 -#define regk_iop_dmc_out_lim4 0x00000002 -#define regk_iop_dmc_out_lim64 0x00000006 -#define regk_iop_dmc_out_lim8 0x00000003 -#define regk_iop_dmc_out_load_c 0x00000200 -#define regk_iop_dmc_out_load_c_n 0x00000280 -#define regk_iop_dmc_out_load_c_next 0x00000240 -#define regk_iop_dmc_out_load_d 0x00000140 -#define regk_iop_dmc_out_load_g 0x00000300 -#define regk_iop_dmc_out_load_g_down 0x000003c0 -#define regk_iop_dmc_out_load_g_next 0x00000340 -#define regk_iop_dmc_out_load_g_up 0x00000380 -#define regk_iop_dmc_out_next_en 0x00000010 -#define regk_iop_dmc_out_next_pkt 0x00000010 -#define regk_iop_dmc_out_no 0x00000000 -#define regk_iop_dmc_out_restore 0x00000020 -#define regk_iop_dmc_out_rw_cfg_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_out_save_down 0x00000020 -#define regk_iop_dmc_out_save_up 0x00000020 -#define regk_iop_dmc_out_set_reg 0x00000050 -#define regk_iop_dmc_out_set_w_size1 0x00000190 -#define regk_iop_dmc_out_set_w_size2 0x000001a0 -#define regk_iop_dmc_out_set_w_size4 0x000001c0 -#define regk_iop_dmc_out_store_c 0x00000002 -#define regk_iop_dmc_out_store_descr 0x00000000 -#define regk_iop_dmc_out_store_g 0x00000004 -#define regk_iop_dmc_out_store_md 0x00000001 -#define regk_iop_dmc_out_update_down 0x00000020 -#define regk_iop_dmc_out_yes 0x00000001 -#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h deleted file mode 100644 index 974dee082f9f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h +++ /dev/null @@ -1,234 +0,0 @@ -#ifndef __iop_fifo_in_defs_asm_h -#define __iop_fifo_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 -#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_in_rw_cfg___trig___width 2 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_in_rw_cfg___mode___width 2 -#define reg_iop_fifo_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_r_stat___last___lsb 4 -#define reg_iop_fifo_in_r_stat___last___width 8 -#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_r_stat_offset 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd1byte___data___width 8 -#define reg_iop_fifo_in_rs_rd1byte_offset 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd1byte___data___width 8 -#define reg_iop_fifo_in_r_rd1byte_offset 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd2byte___data___width 16 -#define reg_iop_fifo_in_rs_rd2byte_offset 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd2byte___data___width 16 -#define reg_iop_fifo_in_r_rd2byte_offset 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd3byte___data___width 24 -#define reg_iop_fifo_in_rs_rd3byte_offset 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd3byte___data___width 24 -#define reg_iop_fifo_in_r_rd3byte_offset 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd4byte___data___width 32 -#define reg_iop_fifo_in_rs_rd4byte_offset 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd4byte___data___width 32 -#define reg_iop_fifo_in_r_rd4byte_offset 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_set_last_offset 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_rw_intr_mask_offset 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_rw_ack_intr_offset 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_intr___urun___width 1 -#define reg_iop_fifo_in_r_intr___urun___bit 0 -#define reg_iop_fifo_in_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_intr___last_data___width 1 -#define reg_iop_fifo_in_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_intr___dav___width 1 -#define reg_iop_fifo_in_r_intr___dav___bit 2 -#define reg_iop_fifo_in_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_intr___avail___width 1 -#define reg_iop_fifo_in_r_intr___avail___bit 3 -#define reg_iop_fifo_in_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_intr___orun___width 1 -#define reg_iop_fifo_in_r_intr___orun___bit 4 -#define reg_iop_fifo_in_r_intr_offset 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_r_masked_intr_offset 64 - - -/* Constants */ -#define regk_iop_fifo_in_dif_in 0x00000002 -#define regk_iop_fifo_in_hi 0x00000000 -#define regk_iop_fifo_in_neg 0x00000002 -#define regk_iop_fifo_in_no 0x00000000 -#define regk_iop_fifo_in_order16 0x00000001 -#define regk_iop_fifo_in_order24 0x00000002 -#define regk_iop_fifo_in_order32 0x00000003 -#define regk_iop_fifo_in_order8 0x00000000 -#define regk_iop_fifo_in_pos 0x00000001 -#define regk_iop_fifo_in_pos_neg 0x00000003 -#define regk_iop_fifo_in_rw_cfg_default 0x00000024 -#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_rw_set_last_default 0x00000000 -#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 -#define regk_iop_fifo_in_size16 0x00000002 -#define regk_iop_fifo_in_size24 0x00000001 -#define regk_iop_fifo_in_size32 0x00000000 -#define regk_iop_fifo_in_size8 0x00000003 -#define regk_iop_fifo_in_yes 0x00000001 -#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h deleted file mode 100644 index e00fab0c9335..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __iop_fifo_in_extra_defs_asm_h -#define __iop_fifo_in_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_in_extra_r_stat___last___width 8 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_extra_r_stat_offset 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_intr_offset 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 - - -/* Constants */ -#define regk_iop_fifo_in_extra_fifo_in 0x00000002 -#define regk_iop_fifo_in_extra_no 0x00000000 -#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_extra_yes 0x00000001 -#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h deleted file mode 100644 index 9ec5f4a826df..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h +++ /dev/null @@ -1,254 +0,0 @@ -#ifndef __iop_fifo_out_defs_asm_h -#define __iop_fifo_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 -#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_out_rw_cfg___trig___width 2 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_out_rw_cfg___mode___width 2 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 -#define reg_iop_fifo_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_r_stat___last___lsb 4 -#define reg_iop_fifo_out_r_stat___last___width 8 -#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_r_stat_offset 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_offset 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_offset 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_offset 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_offset 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_set_last_offset 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -#define reg_iop_fifo_out_rs_rd_data_offset 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_rd_data_offset 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_rw_intr_mask_offset 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_rw_ack_intr_offset 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_intr___urun___width 1 -#define reg_iop_fifo_out_r_intr___urun___bit 0 -#define reg_iop_fifo_out_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_intr___last_data___width 1 -#define reg_iop_fifo_out_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_intr___dav___width 1 -#define reg_iop_fifo_out_r_intr___dav___bit 2 -#define reg_iop_fifo_out_r_intr___free___lsb 3 -#define reg_iop_fifo_out_r_intr___free___width 1 -#define reg_iop_fifo_out_r_intr___free___bit 3 -#define reg_iop_fifo_out_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_intr___orun___width 1 -#define reg_iop_fifo_out_r_intr___orun___bit 4 -#define reg_iop_fifo_out_r_intr_offset 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_r_masked_intr_offset 72 - - -/* Constants */ -#define regk_iop_fifo_out_hi 0x00000000 -#define regk_iop_fifo_out_neg 0x00000002 -#define regk_iop_fifo_out_no 0x00000000 -#define regk_iop_fifo_out_order16 0x00000001 -#define regk_iop_fifo_out_order24 0x00000002 -#define regk_iop_fifo_out_order32 0x00000003 -#define regk_iop_fifo_out_order8 0x00000000 -#define regk_iop_fifo_out_pos 0x00000001 -#define regk_iop_fifo_out_pos_neg 0x00000003 -#define regk_iop_fifo_out_rw_cfg_default 0x00000024 -#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_rw_set_last_default 0x00000000 -#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 -#define regk_iop_fifo_out_size16 0x00000002 -#define regk_iop_fifo_out_size24 0x00000001 -#define regk_iop_fifo_out_size32 0x00000000 -#define regk_iop_fifo_out_size8 0x00000003 -#define regk_iop_fifo_out_yes 0x00000001 -#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h deleted file mode 100644 index 0f84a50cf77c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h +++ /dev/null @@ -1,158 +0,0 @@ -#ifndef __iop_fifo_out_extra_defs_asm_h -#define __iop_fifo_out_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_rd_data_offset 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_out_extra_r_stat___last___width 8 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_extra_r_stat_offset 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_intr_offset 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 - - -/* Constants */ -#define regk_iop_fifo_out_extra_no 0x00000000 -#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_extra_yes 0x00000001 -#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h deleted file mode 100644 index 80490c82cc29..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h +++ /dev/null @@ -1,177 +0,0 @@ -#ifndef __iop_mpu_defs_asm_h -#define __iop_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_r_offset 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_ctrl___en___lsb 0 -#define reg_iop_mpu_rw_ctrl___en___width 1 -#define reg_iop_mpu_rw_ctrl___en___bit 0 -#define reg_iop_mpu_rw_ctrl_offset 128 - -/* Register r_pc, scope iop_mpu, type r */ -#define reg_iop_mpu_r_pc___addr___lsb 0 -#define reg_iop_mpu_r_pc___addr___width 12 -#define reg_iop_mpu_r_pc_offset 132 - -/* Register r_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 -#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 -#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 -#define reg_iop_mpu_r_stat___intr_busy___lsb 1 -#define reg_iop_mpu_r_stat___intr_busy___width 1 -#define reg_iop_mpu_r_stat___intr_busy___bit 1 -#define reg_iop_mpu_r_stat___intr_vect___lsb 2 -#define reg_iop_mpu_r_stat___intr_vect___width 16 -#define reg_iop_mpu_r_stat_offset 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_instr_offset 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_immediate_offset 144 - -/* Register r_trace, scope iop_mpu, type r */ -#define reg_iop_mpu_r_trace___intr_vect___lsb 0 -#define reg_iop_mpu_r_trace___intr_vect___width 16 -#define reg_iop_mpu_r_trace___pc___lsb 16 -#define reg_iop_mpu_r_trace___pc___width 12 -#define reg_iop_mpu_r_trace___en___lsb 28 -#define reg_iop_mpu_r_trace___en___width 1 -#define reg_iop_mpu_r_trace___en___bit 28 -#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 -#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 -#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 -#define reg_iop_mpu_r_trace___intr_busy___lsb 30 -#define reg_iop_mpu_r_trace___intr_busy___width 1 -#define reg_iop_mpu_r_trace___intr_busy___bit 30 -#define reg_iop_mpu_r_trace_offset 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_wr_stat___r0___lsb 0 -#define reg_iop_mpu_r_wr_stat___r0___width 1 -#define reg_iop_mpu_r_wr_stat___r0___bit 0 -#define reg_iop_mpu_r_wr_stat___r1___lsb 1 -#define reg_iop_mpu_r_wr_stat___r1___width 1 -#define reg_iop_mpu_r_wr_stat___r1___bit 1 -#define reg_iop_mpu_r_wr_stat___r2___lsb 2 -#define reg_iop_mpu_r_wr_stat___r2___width 1 -#define reg_iop_mpu_r_wr_stat___r2___bit 2 -#define reg_iop_mpu_r_wr_stat___r3___lsb 3 -#define reg_iop_mpu_r_wr_stat___r3___width 1 -#define reg_iop_mpu_r_wr_stat___r3___bit 3 -#define reg_iop_mpu_r_wr_stat___r4___lsb 4 -#define reg_iop_mpu_r_wr_stat___r4___width 1 -#define reg_iop_mpu_r_wr_stat___r4___bit 4 -#define reg_iop_mpu_r_wr_stat___r5___lsb 5 -#define reg_iop_mpu_r_wr_stat___r5___width 1 -#define reg_iop_mpu_r_wr_stat___r5___bit 5 -#define reg_iop_mpu_r_wr_stat___r6___lsb 6 -#define reg_iop_mpu_r_wr_stat___r6___width 1 -#define reg_iop_mpu_r_wr_stat___r6___bit 6 -#define reg_iop_mpu_r_wr_stat___r7___lsb 7 -#define reg_iop_mpu_r_wr_stat___r7___width 1 -#define reg_iop_mpu_r_wr_stat___r7___bit 7 -#define reg_iop_mpu_r_wr_stat___r8___lsb 8 -#define reg_iop_mpu_r_wr_stat___r8___width 1 -#define reg_iop_mpu_r_wr_stat___r8___bit 8 -#define reg_iop_mpu_r_wr_stat___r9___lsb 9 -#define reg_iop_mpu_r_wr_stat___r9___width 1 -#define reg_iop_mpu_r_wr_stat___r9___bit 9 -#define reg_iop_mpu_r_wr_stat___r10___lsb 10 -#define reg_iop_mpu_r_wr_stat___r10___width 1 -#define reg_iop_mpu_r_wr_stat___r10___bit 10 -#define reg_iop_mpu_r_wr_stat___r11___lsb 11 -#define reg_iop_mpu_r_wr_stat___r11___width 1 -#define reg_iop_mpu_r_wr_stat___r11___bit 11 -#define reg_iop_mpu_r_wr_stat___r12___lsb 12 -#define reg_iop_mpu_r_wr_stat___r12___width 1 -#define reg_iop_mpu_r_wr_stat___r12___bit 12 -#define reg_iop_mpu_r_wr_stat___r13___lsb 13 -#define reg_iop_mpu_r_wr_stat___r13___width 1 -#define reg_iop_mpu_r_wr_stat___r13___bit 13 -#define reg_iop_mpu_r_wr_stat___r14___lsb 14 -#define reg_iop_mpu_r_wr_stat___r14___width 1 -#define reg_iop_mpu_r_wr_stat___r14___bit 14 -#define reg_iop_mpu_r_wr_stat___r15___lsb 15 -#define reg_iop_mpu_r_wr_stat___r15___width 1 -#define reg_iop_mpu_r_wr_stat___r15___bit 15 -#define reg_iop_mpu_r_wr_stat_offset 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_thread___addr___lsb 0 -#define reg_iop_mpu_rw_thread___addr___width 12 -#define reg_iop_mpu_rw_thread_offset 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_intr___addr___lsb 0 -#define reg_iop_mpu_rw_intr___addr___width 12 -#define reg_iop_mpu_rw_intr_offset 196 - - -/* Constants */ -#define regk_iop_mpu_no 0x00000000 -#define regk_iop_mpu_r_pc_default 0x00000000 -#define regk_iop_mpu_rw_ctrl_default 0x00000000 -#define regk_iop_mpu_rw_intr_size 0x00000010 -#define regk_iop_mpu_rw_r_size 0x00000010 -#define regk_iop_mpu_rw_thread_default 0x00000000 -#define regk_iop_mpu_rw_thread_size 0x00000004 -#define regk_iop_mpu_yes 0x00000001 -#endif /* __iop_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index a20b8857b4d0..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in0_extra 64 -#define iop_fifo_in1_extra 128 -#define iop_fifo_out0_extra 192 -#define iop_fifo_out1_extra 256 -#define iop_trigger_grp0 320 -#define iop_trigger_grp1 384 -#define iop_trigger_grp2 448 -#define iop_trigger_grp3 512 -#define iop_trigger_grp4 576 -#define iop_trigger_grp5 640 -#define iop_trigger_grp6 704 -#define iop_trigger_grp7 768 -#define iop_crc_par0 896 -#define iop_crc_par1 1024 -#define iop_dmc_in0 1152 -#define iop_dmc_in1 1280 -#define iop_dmc_out0 1408 -#define iop_dmc_out1 1536 -#define iop_fifo_in0 1664 -#define iop_fifo_in1 1792 -#define iop_fifo_out0 1920 -#define iop_fifo_out1 2048 -#define iop_scrc_in0 2176 -#define iop_scrc_in1 2304 -#define iop_scrc_out0 2432 -#define iop_scrc_out1 2560 -#define iop_timer_grp0 2688 -#define iop_timer_grp1 2816 -#define iop_timer_grp2 2944 -#define iop_timer_grp3 3072 -#define iop_sap_in 3328 -#define iop_sap_out 3584 -#define iop_spu0 3840 -#define iop_spu1 4096 -#define iop_sw_cfg 4352 -#define iop_sw_cpu 4608 -#define iop_sw_mpu 4864 -#define iop_sw_spu0 5120 -#define iop_sw_spu1 5376 -#define iop_mpu 5632 diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index a4a10ff300b3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,182 +0,0 @@ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus0_sync_offset 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus1_sync_offset 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 1 -#define reg_iop_sap_in_rw_gio___delay___bit 7 -#define reg_iop_sap_in_rw_gio___logic___lsb 8 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 8 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio1 0x00000000 -#define regk_iop_sap_in_gio13 0x00000005 -#define regk_iop_sap_in_gio18 0x00000003 -#define regk_iop_sap_in_gio19 0x00000004 -#define regk_iop_sap_in_gio21 0x00000006 -#define regk_iop_sap_in_gio23 0x00000005 -#define regk_iop_sap_in_gio29 0x00000007 -#define regk_iop_sap_in_gio5 0x00000004 -#define regk_iop_sap_in_gio6 0x00000001 -#define regk_iop_sap_in_gio7 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 -#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 -#define regk_iop_sap_in_rw_gio_default 0x00000002 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 -#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 -#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 -#define regk_iop_sap_in_tmr_clk200 0x00000000 -#define regk_iop_sap_in_two_clk200 0x00000002 -#define regk_iop_sap_in_yes 0x00000001 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 0ec727f92a25..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus0_offset 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus1_offset 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic___width 1 -#define reg_iop_sap_out_rw_gio___out_logic___bit 10 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio_offset 28 - - -/* Constants */ -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000002 -#define regk_iop_sap_out_clk2 0x00000002 -#define regk_iop_sap_out_clk200 0x00000001 -#define regk_iop_sap_out_clk3 0x00000003 -#define regk_iop_sap_out_ext 0x00000003 -#define regk_iop_sap_out_gated 0x00000004 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio13 0x00000002 -#define regk_iop_sap_out_gio13_clk 0x0000000c -#define regk_iop_sap_out_gio15 0x00000001 -#define regk_iop_sap_out_gio18 0x00000003 -#define regk_iop_sap_out_gio18_clk 0x0000000d -#define regk_iop_sap_out_gio1_clk 0x00000008 -#define regk_iop_sap_out_gio21_clk 0x0000000e -#define regk_iop_sap_out_gio23 0x00000002 -#define regk_iop_sap_out_gio29_clk 0x0000000f -#define regk_iop_sap_out_gio31 0x00000003 -#define regk_iop_sap_out_gio5 0x00000001 -#define regk_iop_sap_out_gio5_clk 0x00000009 -#define regk_iop_sap_out_gio6_clk 0x0000000a -#define regk_iop_sap_out_gio7 0x00000000 -#define regk_iop_sap_out_gio7_clk 0x0000000b -#define regk_iop_sap_out_gio_in13 0x00000001 -#define regk_iop_sap_out_gio_in21 0x00000002 -#define regk_iop_sap_out_gio_in29 0x00000003 -#define regk_iop_sap_out_gio_in5 0x00000000 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_rw_bus0_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu0_gio0 0x00000002 -#define regk_iop_sap_out_spu0_gio1 0x00000003 -#define regk_iop_sap_out_spu0_gio12 0x00000004 -#define regk_iop_sap_out_spu0_gio13 0x00000004 -#define regk_iop_sap_out_spu0_gio14 0x00000004 -#define regk_iop_sap_out_spu0_gio15 0x00000004 -#define regk_iop_sap_out_spu0_gio2 0x00000002 -#define regk_iop_sap_out_spu0_gio3 0x00000003 -#define regk_iop_sap_out_spu0_gio4 0x00000002 -#define regk_iop_sap_out_spu0_gio5 0x00000003 -#define regk_iop_sap_out_spu0_gio6 0x00000002 -#define regk_iop_sap_out_spu0_gio7 0x00000003 -#define regk_iop_sap_out_spu1_gio0 0x00000005 -#define regk_iop_sap_out_spu1_gio1 0x00000006 -#define regk_iop_sap_out_spu1_gio12 0x00000007 -#define regk_iop_sap_out_spu1_gio13 0x00000007 -#define regk_iop_sap_out_spu1_gio14 0x00000007 -#define regk_iop_sap_out_spu1_gio15 0x00000007 -#define regk_iop_sap_out_spu1_gio2 0x00000005 -#define regk_iop_sap_out_spu1_gio3 0x00000006 -#define regk_iop_sap_out_spu1_gio4 0x00000005 -#define regk_iop_sap_out_spu1_gio5 0x00000006 -#define regk_iop_sap_out_spu1_gio6 0x00000005 -#define regk_iop_sap_out_spu1_gio7 0x00000006 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 -#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 -#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 -#define regk_iop_sap_out_tmr 0x00000005 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h deleted file mode 100644 index 2cf5721597fc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef __iop_scrc_in_defs_asm_h -#define __iop_scrc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_in_rw_cfg___trig___width 2 -#define reg_iop_scrc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_scrc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_stat___err___lsb 0 -#define reg_iop_scrc_in_r_stat___err___width 1 -#define reg_iop_scrc_in_r_stat___err___bit 0 -#define reg_iop_scrc_in_r_stat_offset 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_init_crc_offset 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -#define reg_iop_scrc_in_rs_computed_crc_offset 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_computed_crc_offset 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_crc_offset 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_correct_crc_offset 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 -#define reg_iop_scrc_in_rw_wr1bit___data___width 2 -#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 -#define reg_iop_scrc_in_rw_wr1bit___last___width 2 -#define reg_iop_scrc_in_rw_wr1bit_offset 32 - - -/* Constants */ -#define regk_iop_scrc_in_dif_in 0x00000002 -#define regk_iop_scrc_in_hi 0x00000000 -#define regk_iop_scrc_in_neg 0x00000002 -#define regk_iop_scrc_in_no 0x00000000 -#define regk_iop_scrc_in_pos 0x00000001 -#define regk_iop_scrc_in_pos_neg 0x00000003 -#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rw_cfg_default 0x00000000 -#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_in_set0 0x00000000 -#define regk_iop_scrc_in_set1 0x00000001 -#define regk_iop_scrc_in_yes 0x00000001 -#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h deleted file mode 100644 index 640a25725f20..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifndef __iop_scrc_out_defs_asm_h -#define __iop_scrc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_out_rw_cfg___trig___width 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 -#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 -#define reg_iop_scrc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 -#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 -#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 -#define reg_iop_scrc_out_rw_ctrl_offset 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_init_crc_offset 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_crc_offset 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_data___val___lsb 0 -#define reg_iop_scrc_out_rw_data___val___width 1 -#define reg_iop_scrc_out_rw_data___val___bit 0 -#define reg_iop_scrc_out_rw_data_offset 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -#define reg_iop_scrc_out_r_computed_crc_offset 20 - - -/* Constants */ -#define regk_iop_scrc_out_crc 0x00000001 -#define regk_iop_scrc_out_data 0x00000000 -#define regk_iop_scrc_out_dif 0x00000001 -#define regk_iop_scrc_out_hi 0x00000000 -#define regk_iop_scrc_out_neg 0x00000002 -#define regk_iop_scrc_out_no 0x00000000 -#define regk_iop_scrc_out_pos 0x00000001 -#define regk_iop_scrc_out_pos_neg 0x00000003 -#define regk_iop_scrc_out_reg 0x00000000 -#define regk_iop_scrc_out_rw_cfg_default 0x00000000 -#define regk_iop_scrc_out_rw_crc_default 0x00000000 -#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_out_rw_data_default 0x00000000 -#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_out_yes 0x00000001 -#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h deleted file mode 100644 index bb402c1aa761..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h +++ /dev/null @@ -1,573 +0,0 @@ -#ifndef __iop_spu_defs_asm_h -#define __iop_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -#define reg_iop_spu_rw_r_offset 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_seq_pc___addr___lsb 0 -#define reg_iop_spu_rw_seq_pc___addr___width 12 -#define reg_iop_spu_rw_seq_pc_offset 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 -#define reg_iop_spu_rw_fsm_pc___addr___width 12 -#define reg_iop_spu_rw_fsm_pc_offset 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -#define reg_iop_spu_rw_ctrl___fsm___lsb 0 -#define reg_iop_spu_rw_ctrl___fsm___width 1 -#define reg_iop_spu_rw_ctrl___fsm___bit 0 -#define reg_iop_spu_rw_ctrl___en___lsb 1 -#define reg_iop_spu_rw_ctrl___en___width 1 -#define reg_iop_spu_rw_ctrl___en___bit 1 -#define reg_iop_spu_rw_ctrl_offset 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 -#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 -#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_offset 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus0_out_offset 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus1_out_offset 92 - -/* Register r_gio_in, scope iop_spu, type r */ -#define reg_iop_spu_r_gio_in_offset 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus0_in_offset 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus1_in_offset 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_set_offset 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_clr_offset 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -#define reg_iop_spu_rs_wr_stat___r0___lsb 0 -#define reg_iop_spu_rs_wr_stat___r0___width 1 -#define reg_iop_spu_rs_wr_stat___r0___bit 0 -#define reg_iop_spu_rs_wr_stat___r1___lsb 1 -#define reg_iop_spu_rs_wr_stat___r1___width 1 -#define reg_iop_spu_rs_wr_stat___r1___bit 1 -#define reg_iop_spu_rs_wr_stat___r2___lsb 2 -#define reg_iop_spu_rs_wr_stat___r2___width 1 -#define reg_iop_spu_rs_wr_stat___r2___bit 2 -#define reg_iop_spu_rs_wr_stat___r3___lsb 3 -#define reg_iop_spu_rs_wr_stat___r3___width 1 -#define reg_iop_spu_rs_wr_stat___r3___bit 3 -#define reg_iop_spu_rs_wr_stat___r4___lsb 4 -#define reg_iop_spu_rs_wr_stat___r4___width 1 -#define reg_iop_spu_rs_wr_stat___r4___bit 4 -#define reg_iop_spu_rs_wr_stat___r5___lsb 5 -#define reg_iop_spu_rs_wr_stat___r5___width 1 -#define reg_iop_spu_rs_wr_stat___r5___bit 5 -#define reg_iop_spu_rs_wr_stat___r6___lsb 6 -#define reg_iop_spu_rs_wr_stat___r6___width 1 -#define reg_iop_spu_rs_wr_stat___r6___bit 6 -#define reg_iop_spu_rs_wr_stat___r7___lsb 7 -#define reg_iop_spu_rs_wr_stat___r7___width 1 -#define reg_iop_spu_rs_wr_stat___r7___bit 7 -#define reg_iop_spu_rs_wr_stat___r8___lsb 8 -#define reg_iop_spu_rs_wr_stat___r8___width 1 -#define reg_iop_spu_rs_wr_stat___r8___bit 8 -#define reg_iop_spu_rs_wr_stat___r9___lsb 9 -#define reg_iop_spu_rs_wr_stat___r9___width 1 -#define reg_iop_spu_rs_wr_stat___r9___bit 9 -#define reg_iop_spu_rs_wr_stat___r10___lsb 10 -#define reg_iop_spu_rs_wr_stat___r10___width 1 -#define reg_iop_spu_rs_wr_stat___r10___bit 10 -#define reg_iop_spu_rs_wr_stat___r11___lsb 11 -#define reg_iop_spu_rs_wr_stat___r11___width 1 -#define reg_iop_spu_rs_wr_stat___r11___bit 11 -#define reg_iop_spu_rs_wr_stat___r12___lsb 12 -#define reg_iop_spu_rs_wr_stat___r12___width 1 -#define reg_iop_spu_rs_wr_stat___r12___bit 12 -#define reg_iop_spu_rs_wr_stat___r13___lsb 13 -#define reg_iop_spu_rs_wr_stat___r13___width 1 -#define reg_iop_spu_rs_wr_stat___r13___bit 13 -#define reg_iop_spu_rs_wr_stat___r14___lsb 14 -#define reg_iop_spu_rs_wr_stat___r14___width 1 -#define reg_iop_spu_rs_wr_stat___r14___bit 14 -#define reg_iop_spu_rs_wr_stat___r15___lsb 15 -#define reg_iop_spu_rs_wr_stat___r15___width 1 -#define reg_iop_spu_rs_wr_stat___r15___bit 15 -#define reg_iop_spu_rs_wr_stat_offset 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_wr_stat___r0___lsb 0 -#define reg_iop_spu_r_wr_stat___r0___width 1 -#define reg_iop_spu_r_wr_stat___r0___bit 0 -#define reg_iop_spu_r_wr_stat___r1___lsb 1 -#define reg_iop_spu_r_wr_stat___r1___width 1 -#define reg_iop_spu_r_wr_stat___r1___bit 1 -#define reg_iop_spu_r_wr_stat___r2___lsb 2 -#define reg_iop_spu_r_wr_stat___r2___width 1 -#define reg_iop_spu_r_wr_stat___r2___bit 2 -#define reg_iop_spu_r_wr_stat___r3___lsb 3 -#define reg_iop_spu_r_wr_stat___r3___width 1 -#define reg_iop_spu_r_wr_stat___r3___bit 3 -#define reg_iop_spu_r_wr_stat___r4___lsb 4 -#define reg_iop_spu_r_wr_stat___r4___width 1 -#define reg_iop_spu_r_wr_stat___r4___bit 4 -#define reg_iop_spu_r_wr_stat___r5___lsb 5 -#define reg_iop_spu_r_wr_stat___r5___width 1 -#define reg_iop_spu_r_wr_stat___r5___bit 5 -#define reg_iop_spu_r_wr_stat___r6___lsb 6 -#define reg_iop_spu_r_wr_stat___r6___width 1 -#define reg_iop_spu_r_wr_stat___r6___bit 6 -#define reg_iop_spu_r_wr_stat___r7___lsb 7 -#define reg_iop_spu_r_wr_stat___r7___width 1 -#define reg_iop_spu_r_wr_stat___r7___bit 7 -#define reg_iop_spu_r_wr_stat___r8___lsb 8 -#define reg_iop_spu_r_wr_stat___r8___width 1 -#define reg_iop_spu_r_wr_stat___r8___bit 8 -#define reg_iop_spu_r_wr_stat___r9___lsb 9 -#define reg_iop_spu_r_wr_stat___r9___width 1 -#define reg_iop_spu_r_wr_stat___r9___bit 9 -#define reg_iop_spu_r_wr_stat___r10___lsb 10 -#define reg_iop_spu_r_wr_stat___r10___width 1 -#define reg_iop_spu_r_wr_stat___r10___bit 10 -#define reg_iop_spu_r_wr_stat___r11___lsb 11 -#define reg_iop_spu_r_wr_stat___r11___width 1 -#define reg_iop_spu_r_wr_stat___r11___bit 11 -#define reg_iop_spu_r_wr_stat___r12___lsb 12 -#define reg_iop_spu_r_wr_stat___r12___width 1 -#define reg_iop_spu_r_wr_stat___r12___bit 12 -#define reg_iop_spu_r_wr_stat___r13___lsb 13 -#define reg_iop_spu_r_wr_stat___r13___width 1 -#define reg_iop_spu_r_wr_stat___r13___bit 13 -#define reg_iop_spu_r_wr_stat___r14___lsb 14 -#define reg_iop_spu_r_wr_stat___r14___width 1 -#define reg_iop_spu_r_wr_stat___r14___bit 14 -#define reg_iop_spu_r_wr_stat___r15___lsb 15 -#define reg_iop_spu_r_wr_stat___r15___width 1 -#define reg_iop_spu_r_wr_stat___r15___bit 15 -#define reg_iop_spu_r_wr_stat_offset 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 - -/* Register r_stat_in, scope iop_spu, type r */ -#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 -#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 -#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 -#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 -#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 -#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 -#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 -#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 -#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 -#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 -#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 -#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 -#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 -#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 -#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 -#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 -#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 -#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 -#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 -#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 -#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 -#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 -#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 -#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 -#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 -#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 -#define reg_iop_spu_r_stat_in___sync_clk12___width 1 -#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 -#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 -#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 -#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 -#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 -#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 -#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 -#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 -#define reg_iop_spu_r_stat_in___mc_busy___width 1 -#define reg_iop_spu_r_stat_in___mc_busy___bit 30 -#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 -#define reg_iop_spu_r_stat_in___mc_owned___width 1 -#define reg_iop_spu_r_stat_in___mc_owned___bit 31 -#define reg_iop_spu_r_stat_in_offset 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -#define reg_iop_spu_r_trigger_in_offset 132 - -/* Register r_special_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_special_stat___c_flag___lsb 0 -#define reg_iop_spu_r_special_stat___c_flag___width 1 -#define reg_iop_spu_r_special_stat___c_flag___bit 0 -#define reg_iop_spu_r_special_stat___v_flag___lsb 1 -#define reg_iop_spu_r_special_stat___v_flag___width 1 -#define reg_iop_spu_r_special_stat___v_flag___bit 1 -#define reg_iop_spu_r_special_stat___z_flag___lsb 2 -#define reg_iop_spu_r_special_stat___z_flag___width 1 -#define reg_iop_spu_r_special_stat___z_flag___bit 2 -#define reg_iop_spu_r_special_stat___n_flag___lsb 3 -#define reg_iop_spu_r_special_stat___n_flag___width 1 -#define reg_iop_spu_r_special_stat___n_flag___bit 3 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 -#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 -#define reg_iop_spu_r_special_stat___fsm_in0___width 1 -#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 -#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 -#define reg_iop_spu_r_special_stat___fsm_in1___width 1 -#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 -#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 -#define reg_iop_spu_r_special_stat___fsm_in2___width 1 -#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 -#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 -#define reg_iop_spu_r_special_stat___fsm_in3___width 1 -#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 -#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 -#define reg_iop_spu_r_special_stat___fsm_in4___width 1 -#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 -#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 -#define reg_iop_spu_r_special_stat___fsm_in5___width 1 -#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 -#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 -#define reg_iop_spu_r_special_stat___fsm_in6___width 1 -#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 -#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 -#define reg_iop_spu_r_special_stat___fsm_in7___width 1 -#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 -#define reg_iop_spu_r_special_stat___event0___lsb 16 -#define reg_iop_spu_r_special_stat___event0___width 1 -#define reg_iop_spu_r_special_stat___event0___bit 16 -#define reg_iop_spu_r_special_stat___event1___lsb 17 -#define reg_iop_spu_r_special_stat___event1___width 1 -#define reg_iop_spu_r_special_stat___event1___bit 17 -#define reg_iop_spu_r_special_stat___event2___lsb 18 -#define reg_iop_spu_r_special_stat___event2___width 1 -#define reg_iop_spu_r_special_stat___event2___bit 18 -#define reg_iop_spu_r_special_stat___event3___lsb 19 -#define reg_iop_spu_r_special_stat___event3___width 1 -#define reg_iop_spu_r_special_stat___event3___bit 19 -#define reg_iop_spu_r_special_stat_offset 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -#define reg_iop_spu_rw_reg_access___addr___lsb 0 -#define reg_iop_spu_rw_reg_access___addr___width 13 -#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 -#define reg_iop_spu_rw_reg_access___imm_hi___width 16 -#define reg_iop_spu_rw_reg_access_offset 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_cfg___addr___lsb 0 -#define reg_iop_spu_rw_event_cfg___addr___width 12 -#define reg_iop_spu_rw_event_cfg___src___lsb 12 -#define reg_iop_spu_rw_event_cfg___src___width 2 -#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 -#define reg_iop_spu_rw_event_cfg___eq_en___width 1 -#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 -#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 -#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 -#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 -#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 -#define reg_iop_spu_rw_event_cfg___gt_en___width 1 -#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 -#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 -#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 -#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 -#define reg_iop_spu_rw_event_cfg_offset 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_mask_offset 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_val_offset 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_ret___addr___lsb 0 -#define reg_iop_spu_rw_event_ret___addr___width 12 -#define reg_iop_spu_rw_event_ret_offset 192 - -/* Register r_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_trace___fsm___lsb 0 -#define reg_iop_spu_r_trace___fsm___width 1 -#define reg_iop_spu_r_trace___fsm___bit 0 -#define reg_iop_spu_r_trace___en___lsb 1 -#define reg_iop_spu_r_trace___en___width 1 -#define reg_iop_spu_r_trace___en___bit 1 -#define reg_iop_spu_r_trace___c_flag___lsb 2 -#define reg_iop_spu_r_trace___c_flag___width 1 -#define reg_iop_spu_r_trace___c_flag___bit 2 -#define reg_iop_spu_r_trace___v_flag___lsb 3 -#define reg_iop_spu_r_trace___v_flag___width 1 -#define reg_iop_spu_r_trace___v_flag___bit 3 -#define reg_iop_spu_r_trace___z_flag___lsb 4 -#define reg_iop_spu_r_trace___z_flag___width 1 -#define reg_iop_spu_r_trace___z_flag___bit 4 -#define reg_iop_spu_r_trace___n_flag___lsb 5 -#define reg_iop_spu_r_trace___n_flag___width 1 -#define reg_iop_spu_r_trace___n_flag___bit 5 -#define reg_iop_spu_r_trace___seq_addr___lsb 6 -#define reg_iop_spu_r_trace___seq_addr___width 12 -#define reg_iop_spu_r_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_trace___fsm_addr___width 12 -#define reg_iop_spu_r_trace_offset 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 -#define reg_iop_spu_r_fsm_trace___fsm___width 1 -#define reg_iop_spu_r_fsm_trace___fsm___bit 0 -#define reg_iop_spu_r_fsm_trace___en___lsb 1 -#define reg_iop_spu_r_fsm_trace___en___width 1 -#define reg_iop_spu_r_fsm_trace___en___bit 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 -#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 -#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 -#define reg_iop_spu_r_fsm_trace___inp0___width 1 -#define reg_iop_spu_r_fsm_trace___inp0___bit 3 -#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 -#define reg_iop_spu_r_fsm_trace___inp1___width 1 -#define reg_iop_spu_r_fsm_trace___inp1___bit 4 -#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 -#define reg_iop_spu_r_fsm_trace___inp2___width 1 -#define reg_iop_spu_r_fsm_trace___inp2___bit 5 -#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 -#define reg_iop_spu_r_fsm_trace___inp3___width 1 -#define reg_iop_spu_r_fsm_trace___inp3___bit 6 -#define reg_iop_spu_r_fsm_trace___event0___lsb 7 -#define reg_iop_spu_r_fsm_trace___event0___width 1 -#define reg_iop_spu_r_fsm_trace___event0___bit 7 -#define reg_iop_spu_r_fsm_trace___event1___lsb 8 -#define reg_iop_spu_r_fsm_trace___event1___width 1 -#define reg_iop_spu_r_fsm_trace___event1___bit 8 -#define reg_iop_spu_r_fsm_trace___event2___lsb 9 -#define reg_iop_spu_r_fsm_trace___event2___width 1 -#define reg_iop_spu_r_fsm_trace___event2___bit 9 -#define reg_iop_spu_r_fsm_trace___event3___lsb 10 -#define reg_iop_spu_r_fsm_trace___event3___width 1 -#define reg_iop_spu_r_fsm_trace___event3___bit 10 -#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 -#define reg_iop_spu_r_fsm_trace___gio_out___width 8 -#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 -#define reg_iop_spu_r_fsm_trace_offset 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -#define reg_iop_spu_rw_brp___addr___lsb 0 -#define reg_iop_spu_rw_brp___addr___width 12 -#define reg_iop_spu_rw_brp___fsm___lsb 12 -#define reg_iop_spu_rw_brp___fsm___width 1 -#define reg_iop_spu_rw_brp___fsm___bit 12 -#define reg_iop_spu_rw_brp___en___lsb 13 -#define reg_iop_spu_rw_brp___en___width 1 -#define reg_iop_spu_rw_brp___en___bit 13 -#define reg_iop_spu_rw_brp_offset 204 - - -/* Constants */ -#define regk_iop_spu_attn_hi 0x00000005 -#define regk_iop_spu_attn_lo 0x00000005 -#define regk_iop_spu_attn_r0 0x00000000 -#define regk_iop_spu_attn_r1 0x00000001 -#define regk_iop_spu_attn_r10 0x00000002 -#define regk_iop_spu_attn_r11 0x00000003 -#define regk_iop_spu_attn_r12 0x00000004 -#define regk_iop_spu_attn_r13 0x00000005 -#define regk_iop_spu_attn_r14 0x00000006 -#define regk_iop_spu_attn_r15 0x00000007 -#define regk_iop_spu_attn_r2 0x00000002 -#define regk_iop_spu_attn_r3 0x00000003 -#define regk_iop_spu_attn_r4 0x00000004 -#define regk_iop_spu_attn_r5 0x00000005 -#define regk_iop_spu_attn_r6 0x00000006 -#define regk_iop_spu_attn_r7 0x00000007 -#define regk_iop_spu_attn_r8 0x00000000 -#define regk_iop_spu_attn_r9 0x00000001 -#define regk_iop_spu_c 0x00000000 -#define regk_iop_spu_flag 0x00000002 -#define regk_iop_spu_gio_in 0x00000000 -#define regk_iop_spu_gio_out 0x00000005 -#define regk_iop_spu_gio_out0 0x00000008 -#define regk_iop_spu_gio_out1 0x00000009 -#define regk_iop_spu_gio_out2 0x0000000a -#define regk_iop_spu_gio_out3 0x0000000b -#define regk_iop_spu_gio_out4 0x0000000c -#define regk_iop_spu_gio_out5 0x0000000d -#define regk_iop_spu_gio_out6 0x0000000e -#define regk_iop_spu_gio_out7 0x0000000f -#define regk_iop_spu_n 0x00000003 -#define regk_iop_spu_no 0x00000000 -#define regk_iop_spu_r0 0x00000008 -#define regk_iop_spu_r1 0x00000009 -#define regk_iop_spu_r10 0x0000000a -#define regk_iop_spu_r11 0x0000000b -#define regk_iop_spu_r12 0x0000000c -#define regk_iop_spu_r13 0x0000000d -#define regk_iop_spu_r14 0x0000000e -#define regk_iop_spu_r15 0x0000000f -#define regk_iop_spu_r2 0x0000000a -#define regk_iop_spu_r3 0x0000000b -#define regk_iop_spu_r4 0x0000000c -#define regk_iop_spu_r5 0x0000000d -#define regk_iop_spu_r6 0x0000000e -#define regk_iop_spu_r7 0x0000000f -#define regk_iop_spu_r8 0x00000008 -#define regk_iop_spu_r9 0x00000009 -#define regk_iop_spu_reg_hi 0x00000002 -#define regk_iop_spu_reg_lo 0x00000002 -#define regk_iop_spu_rw_brp_default 0x00000000 -#define regk_iop_spu_rw_brp_size 0x00000004 -#define regk_iop_spu_rw_ctrl_default 0x00000000 -#define regk_iop_spu_rw_event_cfg_size 0x00000004 -#define regk_iop_spu_rw_event_mask_size 0x00000004 -#define regk_iop_spu_rw_event_val_size 0x00000004 -#define regk_iop_spu_rw_gio_out_default 0x00000000 -#define regk_iop_spu_rw_r_size 0x00000010 -#define regk_iop_spu_rw_reg_access_default 0x00000000 -#define regk_iop_spu_stat_in 0x00000002 -#define regk_iop_spu_statin_hi 0x00000004 -#define regk_iop_spu_statin_lo 0x00000004 -#define regk_iop_spu_trig 0x00000003 -#define regk_iop_spu_trigger 0x00000006 -#define regk_iop_spu_v 0x00000001 -#define regk_iop_spu_wsts_gioout_spec 0x00000001 -#define regk_iop_spu_xor 0x00000003 -#define regk_iop_spu_xor_bus0_r2_0 0x00000000 -#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 -#define regk_iop_spu_xor_bus1_r3_0 0x00000001 -#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 -#define regk_iop_spu_yes 0x00000001 -#define regk_iop_spu_z 0x00000002 -#endif /* __iop_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3be60f9b024c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,1052 +0,0 @@ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus0 0x00000000 -#define regk_iop_sw_cfg_bus0_rot16 0x00000004 -#define regk_iop_sw_cfg_bus0_rot24 0x00000006 -#define regk_iop_sw_cfg_bus0_rot8 0x00000002 -#define regk_iop_sw_cfg_bus1 0x00000001 -#define regk_iop_sw_cfg_bus1_rot16 0x00000005 -#define regk_iop_sw_cfg_bus1_rot24 0x00000007 -#define regk_iop_sw_cfg_bus1_rot8 0x00000003 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_dmc0 0x00000000 -#define regk_iop_sw_cfg_dmc1 0x00000001 -#define regk_iop_sw_cfg_gated_clk0 0x00000010 -#define regk_iop_sw_cfg_gated_clk1 0x00000011 -#define regk_iop_sw_cfg_gated_clk2 0x00000012 -#define regk_iop_sw_cfg_gated_clk3 0x00000013 -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in0 0x00000000 -#define regk_iop_sw_cfg_gio_in1 0x00000001 -#define regk_iop_sw_cfg_gio_in10 0x00000002 -#define regk_iop_sw_cfg_gio_in11 0x00000003 -#define regk_iop_sw_cfg_gio_in14 0x00000004 -#define regk_iop_sw_cfg_gio_in15 0x00000005 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in28 0x00000006 -#define regk_iop_sw_cfg_gio_in29 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 -#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_par0 0x00000000 -#define regk_iop_sw_cfg_par1 0x00000001 -#define regk_iop_sw_cfg_pdp_out0 0x00000002 -#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 -#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_pdp_out1 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 -#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out0 0x00000008 -#define regk_iop_sw_cfg_sdp_out1 0x00000009 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu0 0x00000002 -#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu0_g0 0x0000000e -#define regk_iop_sw_cfg_spu0_g1 0x0000000e -#define regk_iop_sw_cfg_spu0_g2 0x0000000e -#define regk_iop_sw_cfg_spu0_g3 0x0000000e -#define regk_iop_sw_cfg_spu0_g4 0x0000000e -#define regk_iop_sw_cfg_spu0_g5 0x0000000e -#define regk_iop_sw_cfg_spu0_g6 0x0000000e -#define regk_iop_sw_cfg_spu0_g7 0x0000000e -#define regk_iop_sw_cfg_spu0_gio0 0x00000000 -#define regk_iop_sw_cfg_spu0_gio1 0x00000001 -#define regk_iop_sw_cfg_spu0_gio2 0x00000000 -#define regk_iop_sw_cfg_spu0_gio5 0x00000005 -#define regk_iop_sw_cfg_spu0_gio6 0x00000006 -#define regk_iop_sw_cfg_spu0_gio7 0x00000007 -#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e -#define regk_iop_sw_cfg_spu1 0x00000003 -#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu1_g0 0x0000000f -#define regk_iop_sw_cfg_spu1_g1 0x0000000f -#define regk_iop_sw_cfg_spu1_g2 0x0000000f -#define regk_iop_sw_cfg_spu1_g3 0x0000000f -#define regk_iop_sw_cfg_spu1_g4 0x0000000f -#define regk_iop_sw_cfg_spu1_g5 0x0000000f -#define regk_iop_sw_cfg_spu1_g6 0x0000000f -#define regk_iop_sw_cfg_spu1_g7 0x0000000f -#define regk_iop_sw_cfg_spu1_gio0 0x00000002 -#define regk_iop_sw_cfg_spu1_gio1 0x00000003 -#define regk_iop_sw_cfg_spu1_gio2 0x00000002 -#define regk_iop_sw_cfg_spu1_gio5 0x00000005 -#define regk_iop_sw_cfg_spu1_gio6 0x00000006 -#define regk_iop_sw_cfg_spu1_gio7 0x00000007 -#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 -#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 -#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 -#define regk_iop_sw_cfg_timer_grp2 0x00000000 -#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 -#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 -#define regk_iop_sw_cfg_timer_grp3 0x00000000 -#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 -#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000000 -#define regk_iop_sw_cfg_trig2_1 0x00000000 -#define regk_iop_sw_cfg_trig2_2 0x00000000 -#define regk_iop_sw_cfg_trig2_3 0x00000000 -#define regk_iop_sw_cfg_trig3_0 0x00000000 -#define regk_iop_sw_cfg_trig3_1 0x00000000 -#define regk_iop_sw_cfg_trig3_2 0x00000000 -#define regk_iop_sw_cfg_trig3_3 0x00000000 -#define regk_iop_sw_cfg_trig4_0 0x00000001 -#define regk_iop_sw_cfg_trig4_1 0x00000001 -#define regk_iop_sw_cfg_trig4_2 0x00000001 -#define regk_iop_sw_cfg_trig4_3 0x00000001 -#define regk_iop_sw_cfg_trig5_0 0x00000001 -#define regk_iop_sw_cfg_trig5_1 0x00000001 -#define regk_iop_sw_cfg_trig5_2 0x00000001 -#define regk_iop_sw_cfg_trig5_3 0x00000001 -#define regk_iop_sw_cfg_trig6_0 0x00000001 -#define regk_iop_sw_cfg_trig6_1 0x00000001 -#define regk_iop_sw_cfg_trig6_2 0x00000001 -#define regk_iop_sw_cfg_trig6_3 0x00000001 -#define regk_iop_sw_cfg_trig7_0 0x00000001 -#define regk_iop_sw_cfg_trig7_1 0x00000001 -#define regk_iop_sw_cfg_trig7_2 0x00000001 -#define regk_iop_sw_cfg_trig7_3 0x00000001 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index db347bcba025..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,1758 +0,0 @@ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_cpu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr2_offset 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr2_offset 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 -#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_intr3_offset 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_masked_intr3_offset 144 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ee7dc0435b59..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1776 +0,0 @@ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_mpu_r_mc_stat_offset 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus0_in_offset 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus1_in_offset 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp0_offset 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp1_offset 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp2_offset 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp3_offset 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu0 0x00000002 -#define regk_iop_sw_mpu_spu1 0x00000003 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 0929f144cfa1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,691 +0,0 @@ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_spu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 -#define reg_iop_sw_spu_r_hw_intr_offset 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 -#define reg_iop_sw_spu_r_mpu_intr_offset 164 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h deleted file mode 100644 index 7129a9a4bedc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h +++ /dev/null @@ -1,237 +0,0 @@ -#ifndef __iop_timer_grp_defs_asm_h -#define __iop_timer_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 -#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 -#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 -#define reg_iop_timer_grp_rw_cfg___trig___width 2 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 -#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 -#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 -#define reg_iop_timer_grp_rw_cfg_offset 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 -#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 -#define reg_iop_timer_grp_rw_half_period_offset 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period_len_offset 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 -#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 -#define reg_iop_timer_grp_rw_tmr_len___val___width 16 -#define reg_iop_timer_grp_rw_tmr_len_offset 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 -#define reg_iop_timer_grp_rw_cmd___rst___width 4 -#define reg_iop_timer_grp_rw_cmd___en___lsb 4 -#define reg_iop_timer_grp_rw_cmd___en___width 4 -#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 -#define reg_iop_timer_grp_rw_cmd___dis___width 4 -#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 -#define reg_iop_timer_grp_rw_cmd___strb___width 4 -#define reg_iop_timer_grp_rw_cmd_offset 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_r_tmr_cnt_offset 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 -#define reg_iop_timer_grp_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 -#define reg_iop_timer_grp_rw_ack_intr_offset 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_intr_offset 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_iop_timer_grp_clk200 0x00000000 -#define regk_iop_timer_grp_clk_gen 0x00000002 -#define regk_iop_timer_grp_complete 0x00000002 -#define regk_iop_timer_grp_div_clk200 0x00000001 -#define regk_iop_timer_grp_div_clk_gen 0x00000003 -#define regk_iop_timer_grp_ext 0x00000001 -#define regk_iop_timer_grp_hi 0x00000000 -#define regk_iop_timer_grp_long_period 0x00000001 -#define regk_iop_timer_grp_neg 0x00000002 -#define regk_iop_timer_grp_no 0x00000000 -#define regk_iop_timer_grp_once 0x00000003 -#define regk_iop_timer_grp_pause 0x00000001 -#define regk_iop_timer_grp_pos 0x00000001 -#define regk_iop_timer_grp_pos_neg 0x00000003 -#define regk_iop_timer_grp_pulse 0x00000000 -#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rw_cfg_default 0x00000002 -#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 -#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 -#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 -#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 -#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 -#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 -#define regk_iop_timer_grp_short_period 0x00000000 -#define regk_iop_timer_grp_stop 0x00000000 -#define regk_iop_timer_grp_tmr 0x00000004 -#define regk_iop_timer_grp_toggle 0x00000001 -#define regk_iop_timer_grp_yes 0x00000001 -#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h deleted file mode 100644 index 1005d9db80dc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h +++ /dev/null @@ -1,157 +0,0 @@ -#ifndef __iop_trigger_grp_defs_asm_h -#define __iop_trigger_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 -#define reg_iop_trigger_grp_rw_cfg___action___width 2 -#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 -#define reg_iop_trigger_grp_rw_cfg___once___width 1 -#define reg_iop_trigger_grp_rw_cfg___once___bit 2 -#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 -#define reg_iop_trigger_grp_rw_cfg___trig___width 3 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 -#define reg_iop_trigger_grp_rw_cfg_offset 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 -#define reg_iop_trigger_grp_rw_cmd___dis___width 4 -#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 -#define reg_iop_trigger_grp_rw_cmd___en___width 4 -#define reg_iop_trigger_grp_rw_cmd_offset 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 -#define reg_iop_trigger_grp_rw_intr_mask_offset 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 -#define reg_iop_trigger_grp_rw_ack_intr_offset 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_intr_offset 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_masked_intr_offset 32 - - -/* Constants */ -#define regk_iop_trigger_grp_fall 0x00000002 -#define regk_iop_trigger_grp_fall_lo 0x00000006 -#define regk_iop_trigger_grp_no 0x00000000 -#define regk_iop_trigger_grp_off 0x00000000 -#define regk_iop_trigger_grp_pulse 0x00000000 -#define regk_iop_trigger_grp_rise 0x00000001 -#define regk_iop_trigger_grp_rise_fall 0x00000003 -#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 -#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 -#define regk_iop_trigger_grp_rise_hi 0x00000005 -#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 -#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 -#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_trigger_grp_toggle 0x00000003 -#define regk_iop_trigger_grp_yes 0x00000001 -#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index e13feb20a7e3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v1_0 0x00000001 -#endif /* __iop_version_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h deleted file mode 100644 index 90e4785b6474..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h +++ /dev/null @@ -1,232 +0,0 @@ -#ifndef __iop_crc_par_defs_h -#define __iop_crc_par_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_crc_par */ - -/* Register rw_cfg, scope iop_crc_par, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int crc_out : 1; - unsigned int rev_out : 1; - unsigned int inv_out : 1; - unsigned int trig : 2; - unsigned int poly : 3; - unsigned int dummy1 : 23; -} reg_iop_crc_par_rw_cfg; -#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 -#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_init_crc; -#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 -#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_correct_crc; -#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 -#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_ctrl; -#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 -#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int tr_dif : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_set_last; -#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 -#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 - -/* Register r_stat, scope iop_crc_par, type r */ -typedef struct { - unsigned int err : 1; - unsigned int busy : 1; - unsigned int dummy1 : 30; -} reg_iop_crc_par_r_stat; -#define REG_RD_ADDR_iop_crc_par_r_stat 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_sh_reg; -#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 - -/* Register r_crc, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_crc; -#define REG_RD_ADDR_iop_crc_par_r_crc 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_crc_par_rw_strb_rec_dif_in; -#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 -#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 - - -/* Constants */ -enum { - regk_iop_crc_par_calc = 0x00000001, - regk_iop_crc_par_ccitt = 0x00000002, - regk_iop_crc_par_check = 0x00000000, - regk_iop_crc_par_crc16 = 0x00000001, - regk_iop_crc_par_crc32 = 0x00000000, - regk_iop_crc_par_crc5 = 0x00000003, - regk_iop_crc_par_crc5_11 = 0x00000004, - regk_iop_crc_par_dif_in = 0x00000002, - regk_iop_crc_par_hi = 0x00000000, - regk_iop_crc_par_neg = 0x00000002, - regk_iop_crc_par_no = 0x00000000, - regk_iop_crc_par_pos = 0x00000001, - regk_iop_crc_par_pos_neg = 0x00000003, - regk_iop_crc_par_rw_cfg_default = 0x00000000, - regk_iop_crc_par_rw_ctrl_default = 0x00000000, - regk_iop_crc_par_yes = 0x00000001 -}; -#endif /* __iop_crc_par_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h deleted file mode 100644 index 76aec6e37f3e..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h +++ /dev/null @@ -1,325 +0,0 @@ -#ifndef __iop_dmc_in_defs_h -#define __iop_dmc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_in */ - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int sth_intr : 3; - unsigned int last_dis_dif : 1; - unsigned int dummy1 : 28; -} reg_iop_dmc_in_rw_cfg; -#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int stream_clr : 1; - unsigned int dummy1 : 29; -} reg_iop_dmc_in_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_in_r_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_in_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int eop : 1; - unsigned int wait : 1; - unsigned int keep_md : 1; - unsigned int size : 3; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_stream_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int sth : 7; - unsigned int dummy1 : 9; - unsigned int full : 1; - unsigned int last_pkt : 1; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int dummy2 : 9; -} reg_iop_dmc_in_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_data_descr; -#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_in_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_group_descr; -#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 -#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_in_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 -#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 -#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 -#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_intr; -#define REG_RD_ADDR_iop_dmc_in_r_intr 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 - - -/* Constants */ -enum { - regk_iop_dmc_in_ack_pkt = 0x00000100, - regk_iop_dmc_in_array = 0x00000008, - regk_iop_dmc_in_burst = 0x00000020, - regk_iop_dmc_in_copy_next = 0x00000010, - regk_iop_dmc_in_copy_up = 0x00000020, - regk_iop_dmc_in_dis_c = 0x00000010, - regk_iop_dmc_in_dis_g = 0x00000020, - regk_iop_dmc_in_lim1 = 0x00000000, - regk_iop_dmc_in_lim16 = 0x00000004, - regk_iop_dmc_in_lim2 = 0x00000001, - regk_iop_dmc_in_lim32 = 0x00000005, - regk_iop_dmc_in_lim4 = 0x00000002, - regk_iop_dmc_in_lim64 = 0x00000006, - regk_iop_dmc_in_lim8 = 0x00000003, - regk_iop_dmc_in_load_c = 0x00000200, - regk_iop_dmc_in_load_c_n = 0x00000280, - regk_iop_dmc_in_load_c_next = 0x00000240, - regk_iop_dmc_in_load_d = 0x00000140, - regk_iop_dmc_in_load_g = 0x00000300, - regk_iop_dmc_in_load_g_down = 0x000003c0, - regk_iop_dmc_in_load_g_next = 0x00000340, - regk_iop_dmc_in_load_g_up = 0x00000380, - regk_iop_dmc_in_next_en = 0x00000010, - regk_iop_dmc_in_next_pkt = 0x00000010, - regk_iop_dmc_in_no = 0x00000000, - regk_iop_dmc_in_restore = 0x00000020, - regk_iop_dmc_in_rw_cfg_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_in_rw_data_descr_default = 0x00000000, - regk_iop_dmc_in_rw_group_descr_default = 0x00000000, - regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, - regk_iop_dmc_in_save_down = 0x00000020, - regk_iop_dmc_in_save_up = 0x00000020, - regk_iop_dmc_in_set_reg = 0x00000050, - regk_iop_dmc_in_set_w_size1 = 0x00000190, - regk_iop_dmc_in_set_w_size2 = 0x000001a0, - regk_iop_dmc_in_set_w_size4 = 0x000001c0, - regk_iop_dmc_in_store_c = 0x00000002, - regk_iop_dmc_in_store_descr = 0x00000000, - regk_iop_dmc_in_store_g = 0x00000004, - regk_iop_dmc_in_store_md = 0x00000001, - regk_iop_dmc_in_update_down = 0x00000020, - regk_iop_dmc_in_yes = 0x00000001 -}; -#endif /* __iop_dmc_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h deleted file mode 100644 index 938a0d4c4604..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef __iop_dmc_out_defs_h -#define __iop_dmc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_out */ - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int trf_lim : 16; - unsigned int last_at_trf_lim : 1; - unsigned int dth_intr : 3; - unsigned int dummy1 : 12; -} reg_iop_dmc_out_rw_cfg; -#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int dummy1 : 30; -} reg_iop_dmc_out_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_out_r_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_out_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -typedef unsigned int reg_iop_dmc_out_rs_stream_data; -#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_stream_data; -#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dth : 7; - unsigned int dummy1 : 9; - unsigned int dv : 1; - unsigned int all_avail : 1; - unsigned int last : 1; - unsigned int size : 3; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int cmd_rq : 1; - unsigned int dummy2 : 4; -} reg_iop_dmc_out_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_data_descr; -#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_out_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_group_descr; -#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 -#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_out_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 -#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 -#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 -#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_intr; -#define REG_RD_ADDR_iop_dmc_out_r_intr 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 - - -/* Constants */ -enum { - regk_iop_dmc_out_ack_pkt = 0x00000100, - regk_iop_dmc_out_array = 0x00000008, - regk_iop_dmc_out_burst = 0x00000020, - regk_iop_dmc_out_copy_next = 0x00000010, - regk_iop_dmc_out_copy_up = 0x00000020, - regk_iop_dmc_out_dis_c = 0x00000010, - regk_iop_dmc_out_dis_g = 0x00000020, - regk_iop_dmc_out_lim1 = 0x00000000, - regk_iop_dmc_out_lim16 = 0x00000004, - regk_iop_dmc_out_lim2 = 0x00000001, - regk_iop_dmc_out_lim32 = 0x00000005, - regk_iop_dmc_out_lim4 = 0x00000002, - regk_iop_dmc_out_lim64 = 0x00000006, - regk_iop_dmc_out_lim8 = 0x00000003, - regk_iop_dmc_out_load_c = 0x00000200, - regk_iop_dmc_out_load_c_n = 0x00000280, - regk_iop_dmc_out_load_c_next = 0x00000240, - regk_iop_dmc_out_load_d = 0x00000140, - regk_iop_dmc_out_load_g = 0x00000300, - regk_iop_dmc_out_load_g_down = 0x000003c0, - regk_iop_dmc_out_load_g_next = 0x00000340, - regk_iop_dmc_out_load_g_up = 0x00000380, - regk_iop_dmc_out_next_en = 0x00000010, - regk_iop_dmc_out_next_pkt = 0x00000010, - regk_iop_dmc_out_no = 0x00000000, - regk_iop_dmc_out_restore = 0x00000020, - regk_iop_dmc_out_rw_cfg_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_out_rw_data_descr_default = 0x00000000, - regk_iop_dmc_out_rw_group_descr_default = 0x00000000, - regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_out_save_down = 0x00000020, - regk_iop_dmc_out_save_up = 0x00000020, - regk_iop_dmc_out_set_reg = 0x00000050, - regk_iop_dmc_out_set_w_size1 = 0x00000190, - regk_iop_dmc_out_set_w_size2 = 0x000001a0, - regk_iop_dmc_out_set_w_size4 = 0x000001c0, - regk_iop_dmc_out_store_c = 0x00000002, - regk_iop_dmc_out_store_descr = 0x00000000, - regk_iop_dmc_out_store_g = 0x00000004, - regk_iop_dmc_out_store_md = 0x00000001, - regk_iop_dmc_out_update_down = 0x00000020, - regk_iop_dmc_out_yes = 0x00000001 -}; -#endif /* __iop_dmc_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h deleted file mode 100644 index e0c982b263fa..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h +++ /dev/null @@ -1,255 +0,0 @@ -#ifndef __iop_fifo_in_defs_h -#define __iop_fifo_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in */ - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int avail_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int dummy1 : 22; -} reg_iop_fifo_in_rw_cfg; -#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_r_stat; -#define REG_RD_ADDR_iop_fifo_in_r_stat 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_rs_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_r_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_rs_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_r_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_rs_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_r_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_rs_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_r_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -typedef unsigned int reg_iop_fifo_in_rw_set_last; -#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 -#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 -#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 -#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_intr; -#define REG_RD_ADDR_iop_fifo_in_r_intr 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 - - -/* Constants */ -enum { - regk_iop_fifo_in_dif_in = 0x00000002, - regk_iop_fifo_in_hi = 0x00000000, - regk_iop_fifo_in_neg = 0x00000002, - regk_iop_fifo_in_no = 0x00000000, - regk_iop_fifo_in_order16 = 0x00000001, - regk_iop_fifo_in_order24 = 0x00000002, - regk_iop_fifo_in_order32 = 0x00000003, - regk_iop_fifo_in_order8 = 0x00000000, - regk_iop_fifo_in_pos = 0x00000001, - regk_iop_fifo_in_pos_neg = 0x00000003, - regk_iop_fifo_in_rw_cfg_default = 0x00000024, - regk_iop_fifo_in_rw_ctrl_default = 0x00000000, - regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_rw_set_last_default = 0x00000000, - regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, - regk_iop_fifo_in_size16 = 0x00000002, - regk_iop_fifo_in_size24 = 0x00000001, - regk_iop_fifo_in_size32 = 0x00000000, - regk_iop_fifo_in_size8 = 0x00000003, - regk_iop_fifo_in_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h deleted file mode 100644 index 798ac95870e9..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __iop_fifo_in_extra_defs_h -#define __iop_fifo_in_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in_extra */ - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_extra_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 - - -/* Constants */ -enum { - regk_iop_fifo_in_extra_fifo_in = 0x00000002, - regk_iop_fifo_in_extra_no = 0x00000000, - regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h deleted file mode 100644 index 833e10f02526..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h +++ /dev/null @@ -1,278 +0,0 @@ -#ifndef __iop_fifo_out_defs_h -#define __iop_fifo_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out */ - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int free_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int delay_out_last : 1; - unsigned int last_dis_dif_out : 1; - unsigned int dummy1 : 20; -} reg_iop_fifo_out_rw_cfg; -#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_out_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_r_stat; -#define REG_RD_ADDR_iop_fifo_out_r_stat 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_set_last; -#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -typedef unsigned int reg_iop_fifo_out_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -typedef unsigned int reg_iop_fifo_out_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 -#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 -#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 -#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_intr; -#define REG_RD_ADDR_iop_fifo_out_r_intr 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 - - -/* Constants */ -enum { - regk_iop_fifo_out_hi = 0x00000000, - regk_iop_fifo_out_neg = 0x00000002, - regk_iop_fifo_out_no = 0x00000000, - regk_iop_fifo_out_order16 = 0x00000001, - regk_iop_fifo_out_order24 = 0x00000002, - regk_iop_fifo_out_order32 = 0x00000003, - regk_iop_fifo_out_order8 = 0x00000000, - regk_iop_fifo_out_pos = 0x00000001, - regk_iop_fifo_out_pos_neg = 0x00000003, - regk_iop_fifo_out_rw_cfg_default = 0x00000024, - regk_iop_fifo_out_rw_ctrl_default = 0x00000000, - regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_rw_set_last_default = 0x00000000, - regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, - regk_iop_fifo_out_size16 = 0x00000002, - regk_iop_fifo_out_size24 = 0x00000001, - regk_iop_fifo_out_size32 = 0x00000000, - regk_iop_fifo_out_size8 = 0x00000003, - regk_iop_fifo_out_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h deleted file mode 100644 index 4a840aae84ee..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __iop_fifo_out_extra_defs_h -#define __iop_fifo_out_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out_extra */ - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 - - -/* Constants */ -enum { - regk_iop_fifo_out_extra_no = 0x00000000, - regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h deleted file mode 100644 index c2b0ba1be60f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h +++ /dev/null @@ -1,190 +0,0 @@ -#ifndef __iop_mpu_defs_h -#define __iop_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_mpu */ - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_r; -#define REG_RD_ADDR_iop_mpu_rw_r 0 -#define REG_WR_ADDR_iop_mpu_rw_r 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_mpu_rw_ctrl; -#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 -#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 - -/* Register r_pc, scope iop_mpu, type r */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_r_pc; -#define REG_RD_ADDR_iop_mpu_r_pc 132 - -/* Register r_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int intr_vect : 16; - unsigned int dummy1 : 14; -} reg_iop_mpu_r_stat; -#define REG_RD_ADDR_iop_mpu_r_stat 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_instr; -#define REG_RD_ADDR_iop_mpu_rw_instr 140 -#define REG_WR_ADDR_iop_mpu_rw_instr 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_immediate; -#define REG_RD_ADDR_iop_mpu_rw_immediate 144 -#define REG_WR_ADDR_iop_mpu_rw_immediate 144 - -/* Register r_trace, scope iop_mpu, type r */ -typedef struct { - unsigned int intr_vect : 16; - unsigned int pc : 12; - unsigned int en : 1; - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int dummy1 : 1; -} reg_iop_mpu_r_trace; -#define REG_RD_ADDR_iop_mpu_r_trace 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_mpu_r_wr_stat; -#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_thread; -#define REG_RD_ADDR_iop_mpu_rw_thread 156 -#define REG_WR_ADDR_iop_mpu_rw_thread 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_intr; -#define REG_RD_ADDR_iop_mpu_rw_intr 196 -#define REG_WR_ADDR_iop_mpu_rw_intr 196 - - -/* Constants */ -enum { - regk_iop_mpu_no = 0x00000000, - regk_iop_mpu_r_pc_default = 0x00000000, - regk_iop_mpu_rw_ctrl_default = 0x00000000, - regk_iop_mpu_rw_intr_size = 0x00000010, - regk_iop_mpu_rw_r_size = 0x00000010, - regk_iop_mpu_rw_thread_default = 0x00000000, - regk_iop_mpu_rw_thread_size = 0x00000004, - regk_iop_mpu_yes = 0x00000001 -}; -#endif /* __iop_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h deleted file mode 100644 index 2ec897ced166..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h +++ /dev/null @@ -1,764 +0,0 @@ -/* ************************************************************************* */ -/* This file is autogenerated by IOPASM Version 1.2 */ -/* DO NOT EDIT THIS FILE - All changes will be lost! */ -/* ************************************************************************* */ - - - -#ifndef __IOP_MPU_MACROS_H__ -#define __IOP_MPU_MACROS_H__ - - -/* ************************************************************************* */ -/* REGISTER DEFINITIONS */ -/* ************************************************************************* */ -#define MPU_R0 (0x0) -#define MPU_R1 (0x1) -#define MPU_R2 (0x2) -#define MPU_R3 (0x3) -#define MPU_R4 (0x4) -#define MPU_R5 (0x5) -#define MPU_R6 (0x6) -#define MPU_R7 (0x7) -#define MPU_R8 (0x8) -#define MPU_R9 (0x9) -#define MPU_R10 (0xa) -#define MPU_R11 (0xb) -#define MPU_R12 (0xc) -#define MPU_R13 (0xd) -#define MPU_R14 (0xe) -#define MPU_R15 (0xf) -#define MPU_PC (0x2) -#define MPU_WSTS (0x3) -#define MPU_JADDR (0x4) -#define MPU_IRP (0x5) -#define MPU_SRP (0x6) -#define MPU_T0 (0x8) -#define MPU_T1 (0x9) -#define MPU_T2 (0xa) -#define MPU_T3 (0xb) -#define MPU_I0 (0x10) -#define MPU_I1 (0x11) -#define MPU_I2 (0x12) -#define MPU_I3 (0x13) -#define MPU_I4 (0x14) -#define MPU_I5 (0x15) -#define MPU_I6 (0x16) -#define MPU_I7 (0x17) -#define MPU_I8 (0x18) -#define MPU_I9 (0x19) -#define MPU_I10 (0x1a) -#define MPU_I11 (0x1b) -#define MPU_I12 (0x1c) -#define MPU_I13 (0x1d) -#define MPU_I14 (0x1e) -#define MPU_I15 (0x1f) -#define MPU_P2 (0x2) -#define MPU_P3 (0x3) -#define MPU_P5 (0x5) -#define MPU_P6 (0x6) -#define MPU_P8 (0x8) -#define MPU_P9 (0x9) -#define MPU_P10 (0xa) -#define MPU_P11 (0xb) -#define MPU_P16 (0x10) -#define MPU_P17 (0x12) -#define MPU_P18 (0x12) -#define MPU_P19 (0x13) -#define MPU_P20 (0x14) -#define MPU_P21 (0x15) -#define MPU_P22 (0x16) -#define MPU_P23 (0x17) -#define MPU_P24 (0x18) -#define MPU_P25 (0x19) -#define MPU_P26 (0x1a) -#define MPU_P27 (0x1b) -#define MPU_P28 (0x1c) -#define MPU_P29 (0x1d) -#define MPU_P30 (0x1e) -#define MPU_P31 (0x1f) -#define MPU_P1 (0x1) -#define MPU_REGA (0x1) - - - -/* ************************************************************************* */ -/* ADDRESS MACROS */ -/* ************************************************************************* */ -#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) -#define MK_BYTE_ADDR(ADDR) (ADDR) - - - -/* ************************************************************************* */ -/* INSTRUCTION MACROS */ -/* ************************************************************************* */ -#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_DI() (0x40000001) - -#define MPU_EI() (0x40000003) - -#define MPU_HALT() (0x40000002) - -#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JNT() (0x61000000) - -#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_NOP() (0x40000000) - -#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_RET() (0x63003000) - -#define MPU_RETI() (0x63602800) - -#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - - -#endif /* end of __IOP_MPU_MACROS_H__ */ -/* End of iop_mpu_macros.h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 756550f5d6cb..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in0_extra (regi_iop + 64) -#define regi_iop_fifo_in1_extra (regi_iop + 128) -#define regi_iop_fifo_out0_extra (regi_iop + 192) -#define regi_iop_fifo_out1_extra (regi_iop + 256) -#define regi_iop_trigger_grp0 (regi_iop + 320) -#define regi_iop_trigger_grp1 (regi_iop + 384) -#define regi_iop_trigger_grp2 (regi_iop + 448) -#define regi_iop_trigger_grp3 (regi_iop + 512) -#define regi_iop_trigger_grp4 (regi_iop + 576) -#define regi_iop_trigger_grp5 (regi_iop + 640) -#define regi_iop_trigger_grp6 (regi_iop + 704) -#define regi_iop_trigger_grp7 (regi_iop + 768) -#define regi_iop_crc_par0 (regi_iop + 896) -#define regi_iop_crc_par1 (regi_iop + 1024) -#define regi_iop_dmc_in0 (regi_iop + 1152) -#define regi_iop_dmc_in1 (regi_iop + 1280) -#define regi_iop_dmc_out0 (regi_iop + 1408) -#define regi_iop_dmc_out1 (regi_iop + 1536) -#define regi_iop_fifo_in0 (regi_iop + 1664) -#define regi_iop_fifo_in1 (regi_iop + 1792) -#define regi_iop_fifo_out0 (regi_iop + 1920) -#define regi_iop_fifo_out1 (regi_iop + 2048) -#define regi_iop_scrc_in0 (regi_iop + 2176) -#define regi_iop_scrc_in1 (regi_iop + 2304) -#define regi_iop_scrc_out0 (regi_iop + 2432) -#define regi_iop_scrc_out1 (regi_iop + 2560) -#define regi_iop_timer_grp0 (regi_iop + 2688) -#define regi_iop_timer_grp1 (regi_iop + 2816) -#define regi_iop_timer_grp2 (regi_iop + 2944) -#define regi_iop_timer_grp3 (regi_iop + 3072) -#define regi_iop_sap_in (regi_iop + 3328) -#define regi_iop_sap_out (regi_iop + 3584) -#define regi_iop_spu0 (regi_iop + 3840) -#define regi_iop_spu1 (regi_iop + 4096) -#define regi_iop_sw_cfg (regi_iop + 4352) -#define regi_iop_sw_cpu (regi_iop + 4608) -#define regi_iop_sw_mpu (regi_iop + 4864) -#define regi_iop_sw_spu0 (regi_iop + 5120) -#define regi_iop_sw_spu1 (regi_iop + 5376) -#define regi_iop_mpu (regi_iop + 5632) diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 5548ac10074f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,179 +0,0 @@ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus0_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus1_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 -#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 1; - unsigned int logic : 2; - unsigned int dummy1 : 22; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 8 -#define REG_WR_ADDR_iop_sap_in_rw_gio 8 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio1 = 0x00000000, - regk_iop_sap_in_gio13 = 0x00000005, - regk_iop_sap_in_gio18 = 0x00000003, - regk_iop_sap_in_gio19 = 0x00000004, - regk_iop_sap_in_gio21 = 0x00000006, - regk_iop_sap_in_gio23 = 0x00000005, - regk_iop_sap_in_gio29 = 0x00000007, - regk_iop_sap_in_gio5 = 0x00000004, - regk_iop_sap_in_gio6 = 0x00000001, - regk_iop_sap_in_gio7 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, - regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, - regk_iop_sap_in_rw_gio_default = 0x00000002, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, - regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, - regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, - regk_iop_sap_in_tmr_clk200 = 0x00000000, - regk_iop_sap_in_two_clk200 = 0x00000002, - regk_iop_sap_in_yes = 0x00000001 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 273936996183..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,306 +0,0 @@ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int clk2_src : 2; - unsigned int clk2_gate_src : 2; - unsigned int clk2_force_src : 3; - unsigned int clk3_src : 2; - unsigned int clk3_gate_src : 2; - unsigned int clk3_force_src : 3; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus0; -#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus1; -#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 4; - unsigned int out_gated_clk : 2; - unsigned int out_clk_inv : 1; - unsigned int out_logic : 1; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 3; - unsigned int oe_gated_clk : 2; - unsigned int oe_clk_inv : 1; - unsigned int oe_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 28 -#define REG_WR_ADDR_iop_sap_out_rw_gio 28 - - -/* Constants */ -enum { - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000002, - regk_iop_sap_out_clk2 = 0x00000002, - regk_iop_sap_out_clk200 = 0x00000001, - regk_iop_sap_out_clk3 = 0x00000003, - regk_iop_sap_out_ext = 0x00000003, - regk_iop_sap_out_gated = 0x00000004, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio13 = 0x00000002, - regk_iop_sap_out_gio13_clk = 0x0000000c, - regk_iop_sap_out_gio15 = 0x00000001, - regk_iop_sap_out_gio18 = 0x00000003, - regk_iop_sap_out_gio18_clk = 0x0000000d, - regk_iop_sap_out_gio1_clk = 0x00000008, - regk_iop_sap_out_gio21_clk = 0x0000000e, - regk_iop_sap_out_gio23 = 0x00000002, - regk_iop_sap_out_gio29_clk = 0x0000000f, - regk_iop_sap_out_gio31 = 0x00000003, - regk_iop_sap_out_gio5 = 0x00000001, - regk_iop_sap_out_gio5_clk = 0x00000009, - regk_iop_sap_out_gio6_clk = 0x0000000a, - regk_iop_sap_out_gio7 = 0x00000000, - regk_iop_sap_out_gio7_clk = 0x0000000b, - regk_iop_sap_out_gio_in13 = 0x00000001, - regk_iop_sap_out_gio_in21 = 0x00000002, - regk_iop_sap_out_gio_in29 = 0x00000003, - regk_iop_sap_out_gio_in5 = 0x00000000, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_rw_bus0_default = 0x00000000, - regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_default = 0x00000000, - regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu0_gio0 = 0x00000002, - regk_iop_sap_out_spu0_gio1 = 0x00000003, - regk_iop_sap_out_spu0_gio12 = 0x00000004, - regk_iop_sap_out_spu0_gio13 = 0x00000004, - regk_iop_sap_out_spu0_gio14 = 0x00000004, - regk_iop_sap_out_spu0_gio15 = 0x00000004, - regk_iop_sap_out_spu0_gio2 = 0x00000002, - regk_iop_sap_out_spu0_gio3 = 0x00000003, - regk_iop_sap_out_spu0_gio4 = 0x00000002, - regk_iop_sap_out_spu0_gio5 = 0x00000003, - regk_iop_sap_out_spu0_gio6 = 0x00000002, - regk_iop_sap_out_spu0_gio7 = 0x00000003, - regk_iop_sap_out_spu1_gio0 = 0x00000005, - regk_iop_sap_out_spu1_gio1 = 0x00000006, - regk_iop_sap_out_spu1_gio12 = 0x00000007, - regk_iop_sap_out_spu1_gio13 = 0x00000007, - regk_iop_sap_out_spu1_gio14 = 0x00000007, - regk_iop_sap_out_spu1_gio15 = 0x00000007, - regk_iop_sap_out_spu1_gio2 = 0x00000005, - regk_iop_sap_out_spu1_gio3 = 0x00000006, - regk_iop_sap_out_spu1_gio4 = 0x00000005, - regk_iop_sap_out_spu1_gio5 = 0x00000006, - regk_iop_sap_out_spu1_gio6 = 0x00000005, - regk_iop_sap_out_spu1_gio7 = 0x00000006, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, - regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, - regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, - regk_iop_sap_out_tmr = 0x00000005, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h deleted file mode 100644 index 4f0a9a81e737..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h +++ /dev/null @@ -1,160 +0,0 @@ -#ifndef __iop_scrc_in_defs_h -#define __iop_scrc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_in */ - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int dummy1 : 30; -} reg_iop_scrc_in_rw_cfg; -#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -typedef struct { - unsigned int err : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_r_stat; -#define REG_RD_ADDR_iop_scrc_in_r_stat 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 -#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -typedef unsigned int reg_iop_scrc_in_rs_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -typedef unsigned int reg_iop_scrc_in_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 -#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_correct_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 -#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int data : 2; - unsigned int last : 2; - unsigned int dummy1 : 28; -} reg_iop_scrc_in_rw_wr1bit; -#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 -#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 - - -/* Constants */ -enum { - regk_iop_scrc_in_dif_in = 0x00000002, - regk_iop_scrc_in_hi = 0x00000000, - regk_iop_scrc_in_neg = 0x00000002, - regk_iop_scrc_in_no = 0x00000000, - regk_iop_scrc_in_pos = 0x00000001, - regk_iop_scrc_in_pos_neg = 0x00000003, - regk_iop_scrc_in_r_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rw_cfg_default = 0x00000000, - regk_iop_scrc_in_rw_ctrl_default = 0x00000000, - regk_iop_scrc_in_rw_init_crc_default = 0x00000000, - regk_iop_scrc_in_set0 = 0x00000000, - regk_iop_scrc_in_set1 = 0x00000001, - regk_iop_scrc_in_yes = 0x00000001 -}; -#endif /* __iop_scrc_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h deleted file mode 100644 index fd1d6ea1d484..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef __iop_scrc_out_defs_h -#define __iop_scrc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_out */ - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int inv_crc : 1; - unsigned int dummy1 : 29; -} reg_iop_scrc_out_rw_cfg; -#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int strb_src : 1; - unsigned int out_src : 1; - unsigned int dummy1 : 30; -} reg_iop_scrc_out_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 -#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 -#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int val : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_out_rw_data; -#define REG_RD_ADDR_iop_scrc_out_rw_data 16 -#define REG_WR_ADDR_iop_scrc_out_rw_data 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -typedef unsigned int reg_iop_scrc_out_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 - - -/* Constants */ -enum { - regk_iop_scrc_out_crc = 0x00000001, - regk_iop_scrc_out_data = 0x00000000, - regk_iop_scrc_out_dif = 0x00000001, - regk_iop_scrc_out_hi = 0x00000000, - regk_iop_scrc_out_neg = 0x00000002, - regk_iop_scrc_out_no = 0x00000000, - regk_iop_scrc_out_pos = 0x00000001, - regk_iop_scrc_out_pos_neg = 0x00000003, - regk_iop_scrc_out_reg = 0x00000000, - regk_iop_scrc_out_rw_cfg_default = 0x00000000, - regk_iop_scrc_out_rw_crc_default = 0x00000000, - regk_iop_scrc_out_rw_ctrl_default = 0x00000000, - regk_iop_scrc_out_rw_data_default = 0x00000000, - regk_iop_scrc_out_rw_init_crc_default = 0x00000000, - regk_iop_scrc_out_yes = 0x00000001 -}; -#endif /* __iop_scrc_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h deleted file mode 100644 index 0fda26e2f06f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h +++ /dev/null @@ -1,453 +0,0 @@ -#ifndef __iop_spu_defs_h -#define __iop_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_spu */ - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_r; -#define REG_RD_ADDR_iop_spu_rw_r 0 -#define REG_WR_ADDR_iop_spu_rw_r 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_seq_pc; -#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 -#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_fsm_pc; -#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 -#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_iop_spu_rw_ctrl; -#define REG_RD_ADDR_iop_spu_rw_ctrl 72 -#define REG_WR_ADDR_iop_spu_rw_ctrl 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -typedef struct { - unsigned int val0 : 5; - unsigned int src0 : 3; - unsigned int val1 : 5; - unsigned int src1 : 3; - unsigned int val2 : 5; - unsigned int src2 : 3; - unsigned int val3 : 5; - unsigned int src3 : 3; -} reg_iop_spu_rw_fsm_inputs3_0; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -typedef struct { - unsigned int val4 : 5; - unsigned int src4 : 3; - unsigned int val5 : 5; - unsigned int src5 : 3; - unsigned int val6 : 5; - unsigned int src6 : 3; - unsigned int val7 : 5; - unsigned int src7 : 3; -} reg_iop_spu_rw_fsm_inputs7_4; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out; -#define REG_RD_ADDR_iop_spu_rw_gio_out 84 -#define REG_WR_ADDR_iop_spu_rw_gio_out 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus0_out; -#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 -#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus1_out; -#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 -#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 - -/* Register r_gio_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_gio_in; -#define REG_RD_ADDR_iop_spu_r_gio_in 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus0_in; -#define REG_RD_ADDR_iop_spu_r_bus0_in 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus1_in; -#define REG_RD_ADDR_iop_spu_r_bus1_in 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_set; -#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 -#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_clr; -#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 -#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_rs_wr_stat; -#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_r_wr_stat; -#define REG_RD_ADDR_iop_spu_r_wr_stat 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; -#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 - -/* Register r_stat_in, scope iop_spu, type r */ -typedef struct { - unsigned int timer_grp_lo : 4; - unsigned int fifo_out_last : 1; - unsigned int fifo_out_rdy : 1; - unsigned int fifo_out_all : 1; - unsigned int fifo_in_rdy : 1; - unsigned int dmc_out_all : 1; - unsigned int dmc_out_dth : 1; - unsigned int dmc_out_eop : 1; - unsigned int dmc_out_dv : 1; - unsigned int dmc_out_last : 1; - unsigned int dmc_out_cmd_rq : 1; - unsigned int dmc_out_cmd_rdy : 1; - unsigned int pcrc_correct : 1; - unsigned int timer_grp_hi : 4; - unsigned int dmc_in_sth : 1; - unsigned int dmc_in_full : 1; - unsigned int dmc_in_cmd_rdy : 1; - unsigned int spu_gio_out : 4; - unsigned int sync_clk12 : 1; - unsigned int scrc_out_data : 1; - unsigned int scrc_in_err : 1; - unsigned int mc_busy : 1; - unsigned int mc_owned : 1; -} reg_iop_spu_r_stat_in; -#define REG_RD_ADDR_iop_spu_r_stat_in 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_trigger_in; -#define REG_RD_ADDR_iop_spu_r_trigger_in 132 - -/* Register r_special_stat, scope iop_spu, type r */ -typedef struct { - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int xor_bus0_r2_0 : 1; - unsigned int xor_bus1_r3_0 : 1; - unsigned int xor_bus0m_r2_0 : 1; - unsigned int xor_bus1m_r3_0 : 1; - unsigned int fsm_in0 : 1; - unsigned int fsm_in1 : 1; - unsigned int fsm_in2 : 1; - unsigned int fsm_in3 : 1; - unsigned int fsm_in4 : 1; - unsigned int fsm_in5 : 1; - unsigned int fsm_in6 : 1; - unsigned int fsm_in7 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int dummy1 : 12; -} reg_iop_spu_r_special_stat; -#define REG_RD_ADDR_iop_spu_r_special_stat 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 13; - unsigned int dummy1 : 3; - unsigned int imm_hi : 16; -} reg_iop_spu_rw_reg_access; -#define REG_RD_ADDR_iop_spu_rw_reg_access 140 -#define REG_WR_ADDR_iop_spu_rw_reg_access 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int src : 2; - unsigned int eq_en : 1; - unsigned int eq_inv : 1; - unsigned int gt_en : 1; - unsigned int gt_inv : 1; - unsigned int dummy1 : 14; -} reg_iop_spu_rw_event_cfg; -#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 -#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_mask; -#define REG_RD_ADDR_iop_spu_rw_event_mask 160 -#define REG_WR_ADDR_iop_spu_rw_event_mask 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_val; -#define REG_RD_ADDR_iop_spu_rw_event_val 176 -#define REG_WR_ADDR_iop_spu_rw_event_val 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_event_ret; -#define REG_RD_ADDR_iop_spu_rw_event_ret 192 -#define REG_WR_ADDR_iop_spu_rw_event_ret 192 - -/* Register r_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int seq_addr : 12; - unsigned int dummy1 : 2; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_trace; -#define REG_RD_ADDR_iop_spu_r_trace 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int tmr_done : 1; - unsigned int inp0 : 1; - unsigned int inp1 : 1; - unsigned int inp2 : 1; - unsigned int inp3 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int gio_out : 8; - unsigned int dummy1 : 1; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_fsm_trace; -#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 18; -} reg_iop_spu_rw_brp; -#define REG_RD_ADDR_iop_spu_rw_brp 204 -#define REG_WR_ADDR_iop_spu_rw_brp 204 - - -/* Constants */ -enum { - regk_iop_spu_attn_hi = 0x00000005, - regk_iop_spu_attn_lo = 0x00000005, - regk_iop_spu_attn_r0 = 0x00000000, - regk_iop_spu_attn_r1 = 0x00000001, - regk_iop_spu_attn_r10 = 0x00000002, - regk_iop_spu_attn_r11 = 0x00000003, - regk_iop_spu_attn_r12 = 0x00000004, - regk_iop_spu_attn_r13 = 0x00000005, - regk_iop_spu_attn_r14 = 0x00000006, - regk_iop_spu_attn_r15 = 0x00000007, - regk_iop_spu_attn_r2 = 0x00000002, - regk_iop_spu_attn_r3 = 0x00000003, - regk_iop_spu_attn_r4 = 0x00000004, - regk_iop_spu_attn_r5 = 0x00000005, - regk_iop_spu_attn_r6 = 0x00000006, - regk_iop_spu_attn_r7 = 0x00000007, - regk_iop_spu_attn_r8 = 0x00000000, - regk_iop_spu_attn_r9 = 0x00000001, - regk_iop_spu_c = 0x00000000, - regk_iop_spu_flag = 0x00000002, - regk_iop_spu_gio_in = 0x00000000, - regk_iop_spu_gio_out = 0x00000005, - regk_iop_spu_gio_out0 = 0x00000008, - regk_iop_spu_gio_out1 = 0x00000009, - regk_iop_spu_gio_out2 = 0x0000000a, - regk_iop_spu_gio_out3 = 0x0000000b, - regk_iop_spu_gio_out4 = 0x0000000c, - regk_iop_spu_gio_out5 = 0x0000000d, - regk_iop_spu_gio_out6 = 0x0000000e, - regk_iop_spu_gio_out7 = 0x0000000f, - regk_iop_spu_n = 0x00000003, - regk_iop_spu_no = 0x00000000, - regk_iop_spu_r0 = 0x00000008, - regk_iop_spu_r1 = 0x00000009, - regk_iop_spu_r10 = 0x0000000a, - regk_iop_spu_r11 = 0x0000000b, - regk_iop_spu_r12 = 0x0000000c, - regk_iop_spu_r13 = 0x0000000d, - regk_iop_spu_r14 = 0x0000000e, - regk_iop_spu_r15 = 0x0000000f, - regk_iop_spu_r2 = 0x0000000a, - regk_iop_spu_r3 = 0x0000000b, - regk_iop_spu_r4 = 0x0000000c, - regk_iop_spu_r5 = 0x0000000d, - regk_iop_spu_r6 = 0x0000000e, - regk_iop_spu_r7 = 0x0000000f, - regk_iop_spu_r8 = 0x00000008, - regk_iop_spu_r9 = 0x00000009, - regk_iop_spu_reg_hi = 0x00000002, - regk_iop_spu_reg_lo = 0x00000002, - regk_iop_spu_rw_brp_default = 0x00000000, - regk_iop_spu_rw_brp_size = 0x00000004, - regk_iop_spu_rw_ctrl_default = 0x00000000, - regk_iop_spu_rw_event_cfg_size = 0x00000004, - regk_iop_spu_rw_event_mask_size = 0x00000004, - regk_iop_spu_rw_event_val_size = 0x00000004, - regk_iop_spu_rw_gio_out_default = 0x00000000, - regk_iop_spu_rw_r_size = 0x00000010, - regk_iop_spu_rw_reg_access_default = 0x00000000, - regk_iop_spu_stat_in = 0x00000002, - regk_iop_spu_statin_hi = 0x00000004, - regk_iop_spu_statin_lo = 0x00000004, - regk_iop_spu_trig = 0x00000003, - regk_iop_spu_trigger = 0x00000006, - regk_iop_spu_v = 0x00000001, - regk_iop_spu_wsts_gioout_spec = 0x00000001, - regk_iop_spu_xor = 0x00000003, - regk_iop_spu_xor_bus0_r2_0 = 0x00000000, - regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, - regk_iop_spu_xor_bus1_r3_0 = 0x00000001, - regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, - regk_iop_spu_yes = 0x00000001, - regk_iop_spu_z = 0x00000002 -}; -#endif /* __iop_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index d7b6d75884d2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,1042 +0,0 @@ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus0_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus0_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus1_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus1_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_byte0 : 2; - unsigned int bus0_byte1 : 2; - unsigned int bus0_byte2 : 2; - unsigned int bus0_byte3 : 2; - unsigned int bus1_byte0 : 2; - unsigned int bus1_byte1 : 2; - unsigned int bus1_byte2 : 2; - unsigned int bus1_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_lo : 3; - unsigned int bus0_hi : 3; - unsigned int bus0_lo_oe : 3; - unsigned int bus0_hi_oe : 3; - unsigned int bus1_lo : 3; - unsigned int bus1_hi : 3; - unsigned int bus1_lo_oe : 3; - unsigned int bus1_hi_oe : 3; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 4; - unsigned int gio0_oe : 2; - unsigned int gio1 : 4; - unsigned int gio1_oe : 2; - unsigned int gio2 : 4; - unsigned int gio2_oe : 2; - unsigned int gio3 : 4; - unsigned int gio3_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 4; - unsigned int gio4_oe : 2; - unsigned int gio5 : 4; - unsigned int gio5_oe : 2; - unsigned int gio6 : 4; - unsigned int gio6_oe : 2; - unsigned int gio7 : 4; - unsigned int gio7_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 4; - unsigned int gio8_oe : 2; - unsigned int gio9 : 4; - unsigned int gio9_oe : 2; - unsigned int gio10 : 4; - unsigned int gio10_oe : 2; - unsigned int gio11 : 4; - unsigned int gio11_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 4; - unsigned int gio12_oe : 2; - unsigned int gio13 : 4; - unsigned int gio13_oe : 2; - unsigned int gio14 : 4; - unsigned int gio14_oe : 2; - unsigned int gio15 : 4; - unsigned int gio15_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 4; - unsigned int gio16_oe : 2; - unsigned int gio17 : 4; - unsigned int gio17_oe : 2; - unsigned int gio18 : 4; - unsigned int gio18_oe : 2; - unsigned int gio19 : 4; - unsigned int gio19_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 4; - unsigned int gio20_oe : 2; - unsigned int gio21 : 4; - unsigned int gio21_oe : 2; - unsigned int gio22 : 4; - unsigned int gio22_oe : 2; - unsigned int gio23 : 4; - unsigned int gio23_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 4; - unsigned int gio24_oe : 2; - unsigned int gio25 : 4; - unsigned int gio25_oe : 2; - unsigned int gio26 : 4; - unsigned int gio26_oe : 2; - unsigned int gio27 : 4; - unsigned int gio27_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 4; - unsigned int gio28_oe : 2; - unsigned int gio29 : 4; - unsigned int gio29_oe : 2; - unsigned int gio30 : 4; - unsigned int gio30_oe : 2; - unsigned int gio31 : 4; - unsigned int gio31_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc0_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc1_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out0_strb : 3; - unsigned int sdp_out1_strb : 3; - unsigned int sdp_in0_data : 3; - unsigned int sdp_in0_last : 2; - unsigned int sdp_in0_strb : 3; - unsigned int sdp_in1_data : 3; - unsigned int sdp_in1_last : 2; - unsigned int sdp_in1_strb : 3; - unsigned int dummy1 : 10; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus0 = 0x00000000, - regk_iop_sw_cfg_bus0_rot16 = 0x00000004, - regk_iop_sw_cfg_bus0_rot24 = 0x00000006, - regk_iop_sw_cfg_bus0_rot8 = 0x00000002, - regk_iop_sw_cfg_bus1 = 0x00000001, - regk_iop_sw_cfg_bus1_rot16 = 0x00000005, - regk_iop_sw_cfg_bus1_rot24 = 0x00000007, - regk_iop_sw_cfg_bus1_rot8 = 0x00000003, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_dmc0 = 0x00000000, - regk_iop_sw_cfg_dmc1 = 0x00000001, - regk_iop_sw_cfg_gated_clk0 = 0x00000010, - regk_iop_sw_cfg_gated_clk1 = 0x00000011, - regk_iop_sw_cfg_gated_clk2 = 0x00000012, - regk_iop_sw_cfg_gated_clk3 = 0x00000013, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in0 = 0x00000000, - regk_iop_sw_cfg_gio_in1 = 0x00000001, - regk_iop_sw_cfg_gio_in10 = 0x00000002, - regk_iop_sw_cfg_gio_in11 = 0x00000003, - regk_iop_sw_cfg_gio_in14 = 0x00000004, - regk_iop_sw_cfg_gio_in15 = 0x00000005, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in28 = 0x00000006, - regk_iop_sw_cfg_gio_in29 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, - regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_par0 = 0x00000000, - regk_iop_sw_cfg_par1 = 0x00000001, - regk_iop_sw_cfg_pdp_out0 = 0x00000002, - regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, - regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_pdp_out1 = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, - regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out0 = 0x00000008, - regk_iop_sw_cfg_sdp_out1 = 0x00000009, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu0 = 0x00000002, - regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu0_g0 = 0x0000000e, - regk_iop_sw_cfg_spu0_g1 = 0x0000000e, - regk_iop_sw_cfg_spu0_g2 = 0x0000000e, - regk_iop_sw_cfg_spu0_g3 = 0x0000000e, - regk_iop_sw_cfg_spu0_g4 = 0x0000000e, - regk_iop_sw_cfg_spu0_g5 = 0x0000000e, - regk_iop_sw_cfg_spu0_g6 = 0x0000000e, - regk_iop_sw_cfg_spu0_g7 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio0 = 0x00000000, - regk_iop_sw_cfg_spu0_gio1 = 0x00000001, - regk_iop_sw_cfg_spu0_gio2 = 0x00000000, - regk_iop_sw_cfg_spu0_gio5 = 0x00000005, - regk_iop_sw_cfg_spu0_gio6 = 0x00000006, - regk_iop_sw_cfg_spu0_gio7 = 0x00000007, - regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, - regk_iop_sw_cfg_spu1 = 0x00000003, - regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu1_g0 = 0x0000000f, - regk_iop_sw_cfg_spu1_g1 = 0x0000000f, - regk_iop_sw_cfg_spu1_g2 = 0x0000000f, - regk_iop_sw_cfg_spu1_g3 = 0x0000000f, - regk_iop_sw_cfg_spu1_g4 = 0x0000000f, - regk_iop_sw_cfg_spu1_g5 = 0x0000000f, - regk_iop_sw_cfg_spu1_g6 = 0x0000000f, - regk_iop_sw_cfg_spu1_g7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gio0 = 0x00000002, - regk_iop_sw_cfg_spu1_gio1 = 0x00000003, - regk_iop_sw_cfg_spu1_gio2 = 0x00000002, - regk_iop_sw_cfg_spu1_gio5 = 0x00000005, - regk_iop_sw_cfg_spu1_gio6 = 0x00000006, - regk_iop_sw_cfg_spu1_gio7 = 0x00000007, - regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, - regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, - regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, - regk_iop_sw_cfg_timer_grp2 = 0x00000000, - regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, - regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, - regk_iop_sw_cfg_timer_grp3 = 0x00000000, - regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, - regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000000, - regk_iop_sw_cfg_trig2_1 = 0x00000000, - regk_iop_sw_cfg_trig2_2 = 0x00000000, - regk_iop_sw_cfg_trig2_3 = 0x00000000, - regk_iop_sw_cfg_trig3_0 = 0x00000000, - regk_iop_sw_cfg_trig3_1 = 0x00000000, - regk_iop_sw_cfg_trig3_2 = 0x00000000, - regk_iop_sw_cfg_trig3_3 = 0x00000000, - regk_iop_sw_cfg_trig4_0 = 0x00000001, - regk_iop_sw_cfg_trig4_1 = 0x00000001, - regk_iop_sw_cfg_trig4_2 = 0x00000001, - regk_iop_sw_cfg_trig4_3 = 0x00000001, - regk_iop_sw_cfg_trig5_0 = 0x00000001, - regk_iop_sw_cfg_trig5_1 = 0x00000001, - regk_iop_sw_cfg_trig5_2 = 0x00000001, - regk_iop_sw_cfg_trig5_3 = 0x00000001, - regk_iop_sw_cfg_trig6_0 = 0x00000001, - regk_iop_sw_cfg_trig6_1 = 0x00000001, - regk_iop_sw_cfg_trig6_2 = 0x00000001, - regk_iop_sw_cfg_trig6_3 = 0x00000001, - regk_iop_sw_cfg_trig7_0 = 0x00000001, - regk_iop_sw_cfg_trig7_1 = 0x00000001, - regk_iop_sw_cfg_trig7_2 = 0x00000001, - regk_iop_sw_cfg_trig7_3 = 0x00000001 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index 5fed844b19e2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,853 +0,0 @@ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr2_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr2; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_rw_intr3_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr3; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_masked_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index da718f2a8cad..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,893 +0,0 @@ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu0 = 0x00000002, - regk_iop_sw_mpu_spu1 = 0x00000003, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index b59dde4bd0d1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,552 +0,0 @@ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out1 : 1; - unsigned int dmc_in1 : 1; - unsigned int dummy1 : 8; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int other_spu_intr0 : 1; - unsigned int other_spu_intr1 : 1; - unsigned int other_spu_intr2 : 1; - unsigned int other_spu_intr3 : 1; - unsigned int other_spu_intr4 : 1; - unsigned int other_spu_intr5 : 1; - unsigned int other_spu_intr6 : 1; - unsigned int other_spu_intr7 : 1; - unsigned int other_spu_intr8 : 1; - unsigned int other_spu_intr9 : 1; - unsigned int other_spu_intr10 : 1; - unsigned int other_spu_intr11 : 1; - unsigned int other_spu_intr12 : 1; - unsigned int other_spu_intr13 : 1; - unsigned int other_spu_intr14 : 1; - unsigned int other_spu_intr15 : 1; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h deleted file mode 100644 index c994114f3b51..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __iop_timer_grp_defs_h -#define __iop_timer_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_timer_grp */ - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 1; - unsigned int trig : 2; - unsigned int clk_gen_div : 8; - unsigned int clk_div : 8; - unsigned int dummy1 : 13; -} reg_iop_timer_grp_rw_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int quota_lo : 15; - unsigned int quota_hi : 15; - unsigned int quota_hi_sel : 1; - unsigned int dummy1 : 1; -} reg_iop_timer_grp_rw_half_period; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -typedef unsigned int reg_iop_timer_grp_rw_half_period_len; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 3; - unsigned int strb : 2; - unsigned int run_mode : 2; - unsigned int out_mode : 1; - unsigned int active_on_tmr : 2; - unsigned int inv : 1; - unsigned int en_by_tmr : 2; - unsigned int dis_by_tmr : 2; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int rst_at_en_strb : 1; - unsigned int dummy1 : 14; -} reg_iop_timer_grp_rw_tmr_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_tmr_len; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int rst : 4; - unsigned int en : 4; - unsigned int dis : 4; - unsigned int strb : 4; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_cmd; -#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 -#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rs_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_r_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 -#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 -#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_intr; -#define REG_RD_ADDR_iop_timer_grp_r_intr 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_masked_intr; -#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 - - -/* Constants */ -enum { - regk_iop_timer_grp_clk200 = 0x00000000, - regk_iop_timer_grp_clk_gen = 0x00000002, - regk_iop_timer_grp_complete = 0x00000002, - regk_iop_timer_grp_div_clk200 = 0x00000001, - regk_iop_timer_grp_div_clk_gen = 0x00000003, - regk_iop_timer_grp_ext = 0x00000001, - regk_iop_timer_grp_hi = 0x00000000, - regk_iop_timer_grp_long_period = 0x00000001, - regk_iop_timer_grp_neg = 0x00000002, - regk_iop_timer_grp_no = 0x00000000, - regk_iop_timer_grp_once = 0x00000003, - regk_iop_timer_grp_pause = 0x00000001, - regk_iop_timer_grp_pos = 0x00000001, - regk_iop_timer_grp_pos_neg = 0x00000003, - regk_iop_timer_grp_pulse = 0x00000000, - regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rw_cfg_default = 0x00000002, - regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, - regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, - regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, - regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, - regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, - regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, - regk_iop_timer_grp_short_period = 0x00000000, - regk_iop_timer_grp_stop = 0x00000000, - regk_iop_timer_grp_tmr = 0x00000004, - regk_iop_timer_grp_toggle = 0x00000001, - regk_iop_timer_grp_yes = 0x00000001 -}; -#endif /* __iop_timer_grp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h deleted file mode 100644 index 36e44282399d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h +++ /dev/null @@ -1,170 +0,0 @@ -#ifndef __iop_trigger_grp_defs_h -#define __iop_trigger_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_trigger_grp */ - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int action : 2; - unsigned int once : 1; - unsigned int trig : 3; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cfg; -#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int dis : 4; - unsigned int en : 4; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cmd; -#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 -#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 -#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 -#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_masked_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 - - -/* Constants */ -enum { - regk_iop_trigger_grp_fall = 0x00000002, - regk_iop_trigger_grp_fall_lo = 0x00000006, - regk_iop_trigger_grp_no = 0x00000000, - regk_iop_trigger_grp_off = 0x00000000, - regk_iop_trigger_grp_pulse = 0x00000000, - regk_iop_trigger_grp_rise = 0x00000001, - regk_iop_trigger_grp_rise_fall = 0x00000003, - regk_iop_trigger_grp_rise_fall_hi = 0x00000007, - regk_iop_trigger_grp_rise_fall_lo = 0x00000004, - regk_iop_trigger_grp_rise_hi = 0x00000005, - regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, - regk_iop_trigger_grp_rw_cfg_size = 0x00000004, - regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, - regk_iop_trigger_grp_toggle = 0x00000003, - regk_iop_trigger_grp_yes = 0x00000001 -}; -#endif /* __iop_trigger_grp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h deleted file mode 100644 index b8d6a910c71c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v1_0 = 0x00000001 -}; -#endif /* __iop_version_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h deleted file mode 100644 index 7b167e3c0572..000000000000 --- a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __irq_nmi_defs_h -#define __irq_nmi_defs_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope irq_nmi */ - -/* Register rw_cmd, scope irq_nmi, type rw */ -typedef struct { - unsigned int delay : 16; - unsigned int op : 2; - unsigned int dummy1 : 14; -} reg_irq_nmi_rw_cmd; -#define REG_RD_ADDR_irq_nmi_rw_cmd 0 -#define REG_WR_ADDR_irq_nmi_rw_cmd 0 - - -/* Constants */ -enum { - regk_irq_nmi_ack_irq = 0x00000002, - regk_irq_nmi_ack_nmi = 0x00000003, - regk_irq_nmi_irq = 0x00000000, - regk_irq_nmi_nmi = 0x00000001 -}; -#endif /* __irq_nmi_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h deleted file mode 100644 index a11fdd3cd907..000000000000 --- a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,205 +0,0 @@ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h deleted file mode 100644 index 71e8af0bb3a4..000000000000 --- a/include/asm-cris/arch-v32/hwregs/marb_defs.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h deleted file mode 100644 index 9d91c2de1b07..000000000000 --- a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h +++ /dev/null @@ -1,357 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h deleted file mode 100644 index 236f91efe7e8..000000000000 --- a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Read/write register macros used by *_defs.h - */ - -#ifndef reg_rdwr_h -#define reg_rdwr_h - -#ifndef REG_READ -#define REG_READ(type, addr) (*((volatile type *) (addr))) -#endif - -#ifndef REG_WRITE -#define REG_WRITE(type, addr, val) \ - do { *((volatile type *) (addr)) = (val); } while(0) -#endif - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h deleted file mode 100644 index d9f0e924fb23..000000000000 --- a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h +++ /dev/null @@ -1,173 +0,0 @@ -#ifndef __rt_trace_defs_h -#define __rt_trace_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope rt_trace */ - -/* Register rw_cfg, scope rt_trace, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int mode : 1; - unsigned int owner : 1; - unsigned int wp : 1; - unsigned int stall : 1; - unsigned int dummy1 : 3; - unsigned int wp_start : 7; - unsigned int dummy2 : 1; - unsigned int wp_stop : 7; - unsigned int dummy3 : 9; -} reg_rt_trace_rw_cfg; -#define REG_RD_ADDR_rt_trace_rw_cfg 0 -#define REG_WR_ADDR_rt_trace_rw_cfg 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -typedef struct { - unsigned int ack_data : 1; - unsigned int ack_guru : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_rw_tap_ctrl; -#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 -#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -typedef struct { - unsigned int dav : 1; - unsigned int empty : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_r_tap_stat; -#define REG_RD_ADDR_rt_trace_r_tap_stat 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -typedef unsigned int reg_rt_trace_rw_tap_data; -#define REG_RD_ADDR_rt_trace_rw_tap_data 12 -#define REG_WR_ADDR_rt_trace_rw_tap_data 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -typedef struct { - unsigned int op : 4; - unsigned int sub_op : 4; - unsigned int dummy1 : 24; -} reg_rt_trace_rw_tap_hdata; -#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 -#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 - -/* Register r_redir, scope rt_trace, type r */ -typedef unsigned int reg_rt_trace_r_redir; -#define REG_RD_ADDR_rt_trace_r_redir 20 - - -/* Constants */ -enum { - regk_rt_trace_brk = 0x0000000c, - regk_rt_trace_dbg = 0x00000003, - regk_rt_trace_dbgdi = 0x00000004, - regk_rt_trace_dbgdo = 0x00000005, - regk_rt_trace_gmode = 0x00000000, - regk_rt_trace_no = 0x00000000, - regk_rt_trace_nop = 0x00000000, - regk_rt_trace_normal = 0x00000000, - regk_rt_trace_rdmem = 0x00000007, - regk_rt_trace_rdmemb = 0x00000009, - regk_rt_trace_rdpreg = 0x00000002, - regk_rt_trace_rdreg = 0x00000001, - regk_rt_trace_rdsreg = 0x00000003, - regk_rt_trace_redir = 0x00000006, - regk_rt_trace_ret = 0x0000000b, - regk_rt_trace_rw_cfg_default = 0x00000000, - regk_rt_trace_trcfg = 0x00000001, - regk_rt_trace_wp = 0x00000001, - regk_rt_trace_wp0 = 0x00000001, - regk_rt_trace_wp1 = 0x00000002, - regk_rt_trace_wp2 = 0x00000004, - regk_rt_trace_wp3 = 0x00000008, - regk_rt_trace_wp4 = 0x00000010, - regk_rt_trace_wp5 = 0x00000020, - regk_rt_trace_wp6 = 0x00000040, - regk_rt_trace_wrmem = 0x00000008, - regk_rt_trace_wrmemb = 0x0000000a, - regk_rt_trace_wrpreg = 0x00000005, - regk_rt_trace_wrreg = 0x00000004, - regk_rt_trace_wrsreg = 0x00000006, - regk_rt_trace_yes = 0x00000001 -}; -#endif /* __rt_trace_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h deleted file mode 100644 index 01c2fab97d43..000000000000 --- a/include/asm-cris/arch-v32/hwregs/ser_defs.h +++ /dev/null @@ -1,308 +0,0 @@ -#ifndef __ser_defs_h -#define __ser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ser */ - -/* Register rw_tr_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int stop_bits : 1; - unsigned int stop : 1; - unsigned int rts_delay : 3; - unsigned int rts_setup : 1; - unsigned int auto_rts : 1; - unsigned int txd : 1; - unsigned int auto_cts : 1; - unsigned int dummy1 : 15; -} reg_ser_rw_tr_ctrl; -#define REG_RD_ADDR_ser_rw_tr_ctrl 0 -#define REG_WR_ADDR_ser_rw_tr_ctrl 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_tr_dma_en; -#define REG_RD_ADDR_ser_rw_tr_dma_en 4 -#define REG_WR_ADDR_ser_rw_tr_dma_en 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int dma_mode : 1; - unsigned int dma_err : 1; - unsigned int sampling : 1; - unsigned int timeout : 3; - unsigned int auto_eop : 1; - unsigned int half_duplex : 1; - unsigned int rts_n : 1; - unsigned int loopback : 1; - unsigned int dummy1 : 14; -} reg_ser_rw_rec_ctrl; -#define REG_RD_ADDR_ser_rw_rec_ctrl 8 -#define REG_WR_ADDR_ser_rw_rec_ctrl 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_tr_baud_div; -#define REG_RD_ADDR_ser_rw_tr_baud_div 12 -#define REG_WR_ADDR_ser_rw_tr_baud_div 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_rec_baud_div; -#define REG_RD_ADDR_ser_rw_rec_baud_div 16 -#define REG_WR_ADDR_ser_rw_rec_baud_div 16 - -/* Register rw_xoff, scope ser, type rw */ -typedef struct { - unsigned int chr : 8; - unsigned int automatic : 1; - unsigned int dummy1 : 23; -} reg_ser_rw_xoff; -#define REG_RD_ADDR_ser_rw_xoff 20 -#define REG_WR_ADDR_ser_rw_xoff 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_xoff_clr; -#define REG_RD_ADDR_ser_rw_xoff_clr 24 -#define REG_WR_ADDR_ser_rw_xoff_clr 24 - -/* Register rw_dout, scope ser, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_ser_rw_dout; -#define REG_RD_ADDR_ser_rw_dout 28 -#define REG_WR_ADDR_ser_rw_dout 28 - -/* Register rs_stat_din, scope ser, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_rs_stat_din; -#define REG_RD_ADDR_ser_rs_stat_din 32 - -/* Register r_stat_din, scope ser, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_r_stat_din; -#define REG_RD_ADDR_ser_r_stat_din 36 - -/* Register rw_rec_eop, scope ser, type rw */ -typedef struct { - unsigned int set : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_rec_eop; -#define REG_RD_ADDR_ser_rw_rec_eop 40 -#define REG_WR_ADDR_ser_rw_rec_eop 40 - -/* Register rw_intr_mask, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_intr_mask; -#define REG_RD_ADDR_ser_rw_intr_mask 44 -#define REG_WR_ADDR_ser_rw_intr_mask 44 - -/* Register rw_ack_intr, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_ack_intr; -#define REG_RD_ADDR_ser_rw_ack_intr 48 -#define REG_WR_ADDR_ser_rw_ack_intr 48 - -/* Register r_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_intr; -#define REG_RD_ADDR_ser_r_intr 52 - -/* Register r_masked_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_masked_intr; -#define REG_RD_ADDR_ser_r_masked_intr 56 - - -/* Constants */ -enum { - regk_ser_active = 0x00000000, - regk_ser_bits1 = 0x00000000, - regk_ser_bits2 = 0x00000001, - regk_ser_bits7 = 0x00000001, - regk_ser_bits8 = 0x00000000, - regk_ser_del0_5 = 0x00000000, - regk_ser_del1 = 0x00000001, - regk_ser_del1_5 = 0x00000002, - regk_ser_del2 = 0x00000003, - regk_ser_del2_5 = 0x00000004, - regk_ser_del3 = 0x00000005, - regk_ser_del3_5 = 0x00000006, - regk_ser_del4 = 0x00000007, - regk_ser_even = 0x00000000, - regk_ser_ext = 0x00000001, - regk_ser_f100 = 0x00000007, - regk_ser_f29_493 = 0x00000004, - regk_ser_f32 = 0x00000005, - regk_ser_f32_768 = 0x00000006, - regk_ser_ignore = 0x00000001, - regk_ser_inactive = 0x00000001, - regk_ser_majority = 0x00000001, - regk_ser_mark = 0x00000002, - regk_ser_middle = 0x00000000, - regk_ser_no = 0x00000000, - regk_ser_odd = 0x00000001, - regk_ser_off = 0x00000000, - regk_ser_rw_intr_mask_default = 0x00000000, - regk_ser_rw_rec_baud_div_default = 0x00000000, - regk_ser_rw_rec_ctrl_default = 0x00010000, - regk_ser_rw_tr_baud_div_default = 0x00000000, - regk_ser_rw_tr_ctrl_default = 0x00008000, - regk_ser_rw_tr_dma_en_default = 0x00000000, - regk_ser_rw_xoff_default = 0x00000000, - regk_ser_space = 0x00000003, - regk_ser_stop = 0x00000000, - regk_ser_yes = 0x00000001 -}; -#endif /* __ser_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h deleted file mode 100644 index 8d1dab218b91..000000000000 --- a/include/asm-cris/arch-v32/hwregs/sser_defs.h +++ /dev/null @@ -1,331 +0,0 @@ -#ifndef __sser_defs_h -#define __sser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope sser */ - -/* Register rw_cfg, scope sser, type rw */ -typedef struct { - unsigned int clk_div : 16; - unsigned int base_freq : 3; - unsigned int gate_clk : 1; - unsigned int clkgate_ctrl : 1; - unsigned int clkgate_in : 1; - unsigned int clk_dir : 1; - unsigned int clk_od_mode : 1; - unsigned int out_clk_pol : 1; - unsigned int out_clk_src : 2; - unsigned int clk_in_sel : 1; - unsigned int hold_pol : 1; - unsigned int prepare : 1; - unsigned int en : 1; - unsigned int dummy1 : 1; -} reg_sser_rw_cfg; -#define REG_RD_ADDR_sser_rw_cfg 0 -#define REG_WR_ADDR_sser_rw_cfg 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -typedef struct { - unsigned int wordrate : 10; - unsigned int rec_delay : 3; - unsigned int tr_delay : 3; - unsigned int early_wend : 1; - unsigned int level : 2; - unsigned int type : 1; - unsigned int clk_pol : 1; - unsigned int fr_in_rxclk : 1; - unsigned int clk_src : 1; - unsigned int out_off : 1; - unsigned int out_on : 1; - unsigned int frame_pin_dir : 1; - unsigned int frame_pin_use : 2; - unsigned int status_pin_dir : 1; - unsigned int status_pin_use : 2; - unsigned int dummy1 : 1; -} reg_sser_rw_frm_cfg; -#define REG_RD_ADDR_sser_rw_frm_cfg 4 -#define REG_WR_ADDR_sser_rw_frm_cfg 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -typedef struct { - unsigned int tr_en : 1; - unsigned int stop : 1; - unsigned int urun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 1; - unsigned int use60958 : 1; - unsigned int iec60958_ckdiv : 2; - unsigned int rate_ctrl : 1; - unsigned int use_md : 1; - unsigned int dual_i2s : 1; - unsigned int data_pin_use : 2; - unsigned int od_mode : 1; - unsigned int bulk_wspace : 2; - unsigned int dummy1 : 4; -} reg_sser_rw_tr_cfg; -#define REG_RD_ADDR_sser_rw_tr_cfg 8 -#define REG_WR_ADDR_sser_rw_tr_cfg 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -typedef struct { - unsigned int rec_en : 1; - unsigned int force_eop : 1; - unsigned int stop : 1; - unsigned int orun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 2; - unsigned int use60958 : 1; - unsigned int iec60958_ui_len : 5; - unsigned int slave2_en : 1; - unsigned int slave3_en : 1; - unsigned int fifo_thr : 2; - unsigned int dummy1 : 3; -} reg_sser_rw_rec_cfg; -#define REG_RD_ADDR_sser_rw_rec_cfg 12 -#define REG_WR_ADDR_sser_rw_rec_cfg 12 - -/* Register rw_tr_data, scope sser, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int dummy1 : 15; -} reg_sser_rw_tr_data; -#define REG_RD_ADDR_sser_rw_tr_data 16 -#define REG_WR_ADDR_sser_rw_tr_data 16 - -/* Register r_rec_data, scope sser, type r */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int ext_clk : 1; - unsigned int status_in : 1; - unsigned int frame_in : 1; - unsigned int din : 1; - unsigned int data_in : 1; - unsigned int clk_in : 1; - unsigned int dummy1 : 9; -} reg_sser_r_rec_data; -#define REG_RD_ADDR_sser_r_rec_data 20 - -/* Register rw_extra, scope sser, type rw */ -typedef struct { - unsigned int clkoff_cycles : 20; - unsigned int clkoff_en : 1; - unsigned int clkon_en : 1; - unsigned int dout_delay : 5; - unsigned int dummy1 : 5; -} reg_sser_rw_extra; -#define REG_RD_ADDR_sser_rw_extra 24 -#define REG_WR_ADDR_sser_rw_extra 24 - -/* Register rw_intr_mask, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_intr_mask; -#define REG_RD_ADDR_sser_rw_intr_mask 28 -#define REG_WR_ADDR_sser_rw_intr_mask 28 - -/* Register rw_ack_intr, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_ack_intr; -#define REG_RD_ADDR_sser_rw_ack_intr 32 -#define REG_WR_ADDR_sser_rw_ack_intr 32 - -/* Register r_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_intr; -#define REG_RD_ADDR_sser_r_intr 36 - -/* Register r_masked_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_masked_intr; -#define REG_RD_ADDR_sser_r_masked_intr 40 - - -/* Constants */ -enum { - regk_sser_both = 0x00000002, - regk_sser_bulk = 0x00000001, - regk_sser_clk100 = 0x00000000, - regk_sser_clk_in = 0x00000000, - regk_sser_const0 = 0x00000003, - regk_sser_dout = 0x00000002, - regk_sser_edge = 0x00000000, - regk_sser_ext = 0x00000001, - regk_sser_ext_clk = 0x00000001, - regk_sser_f100 = 0x00000000, - regk_sser_f29_493 = 0x00000004, - regk_sser_f32 = 0x00000005, - regk_sser_f32_768 = 0x00000006, - regk_sser_frm = 0x00000003, - regk_sser_gio0 = 0x00000000, - regk_sser_gio1 = 0x00000001, - regk_sser_hispeed = 0x00000001, - regk_sser_hold = 0x00000002, - regk_sser_in = 0x00000000, - regk_sser_inf = 0x00000003, - regk_sser_intern = 0x00000000, - regk_sser_intern_clk = 0x00000001, - regk_sser_intern_tb = 0x00000000, - regk_sser_iso = 0x00000000, - regk_sser_level = 0x00000001, - regk_sser_lospeed = 0x00000000, - regk_sser_lsbfirst = 0x00000000, - regk_sser_msbfirst = 0x00000001, - regk_sser_neg = 0x00000001, - regk_sser_neg_lo = 0x00000000, - regk_sser_no = 0x00000000, - regk_sser_no_clk = 0x00000007, - regk_sser_nojitter = 0x00000002, - regk_sser_out = 0x00000001, - regk_sser_pos = 0x00000000, - regk_sser_pos_hi = 0x00000001, - regk_sser_rec = 0x00000000, - regk_sser_rw_cfg_default = 0x00000000, - regk_sser_rw_extra_default = 0x00000000, - regk_sser_rw_frm_cfg_default = 0x00000000, - regk_sser_rw_intr_mask_default = 0x00000000, - regk_sser_rw_rec_cfg_default = 0x00000000, - regk_sser_rw_tr_cfg_default = 0x01800000, - regk_sser_rw_tr_data_default = 0x00000000, - regk_sser_thr16 = 0x00000001, - regk_sser_thr32 = 0x00000002, - regk_sser_thr8 = 0x00000000, - regk_sser_tr = 0x00000001, - regk_sser_ts_out = 0x00000003, - regk_sser_tx_bulk = 0x00000002, - regk_sser_wiresave = 0x00000002, - regk_sser_yes = 0x00000001 -}; -#endif /* __sser_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h deleted file mode 100644 index 35131ba466f3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strcop.h +++ /dev/null @@ -1,57 +0,0 @@ -// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ - -// Streamcop meta-data configuration structs - -struct strcop_meta_out { - unsigned char csumsel : 3; - unsigned char ciphsel : 3; - unsigned char ciphconf : 2; - unsigned char hashsel : 3; - unsigned char hashconf : 1; - unsigned char hashmode : 1; - unsigned char decrypt : 1; - unsigned char dlkey : 1; - unsigned char cbcmode : 1; -}; - -struct strcop_meta_in { - unsigned char dmasel : 3; - unsigned char sync : 1; - unsigned char res1 : 5; - unsigned char res2; -}; - -// Source definitions - -enum { - src_none = 0, - src_dma = 1, - src_des = 2, - src_sha1 = 3, - src_csum = 4, - src_aes = 5, - src_md5 = 6, - src_res = 7 -}; - -// Cipher definitions - -enum { - ciph_des = 0, - ciph_3des = 1, - ciph_aes = 2 -}; - -// Hash definitions - -enum { - hash_sha1 = 0, - hash_md5 = 1 -}; - -enum { - hash_noiv = 0, - hash_iv = 1 -}; - - diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h deleted file mode 100644 index bd145a49b2c4..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strcop_defs.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __strcop_defs_h -#define __strcop_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strcop */ - -/* Register rw_cfg, scope strcop, type rw */ -typedef struct { - unsigned int td3 : 1; - unsigned int td2 : 1; - unsigned int td1 : 1; - unsigned int ipend : 1; - unsigned int ignore_sync : 1; - unsigned int en : 1; - unsigned int dummy1 : 26; -} reg_strcop_rw_cfg; -#define REG_RD_ADDR_strcop_rw_cfg 0 -#define REG_WR_ADDR_strcop_rw_cfg 0 - - -/* Constants */ -enum { - regk_strcop_big = 0x00000001, - regk_strcop_d = 0x00000001, - regk_strcop_e = 0x00000000, - regk_strcop_little = 0x00000000, - regk_strcop_rw_cfg_default = 0x00000002 -}; -#endif /* __strcop_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h deleted file mode 100644 index 67474855c499..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strmux_defs.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h deleted file mode 100644 index ffe49625ae36..000000000000 --- a/include/asm-cris/arch-v32/hwregs/supp_reg.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef __SUPP_REG_H__ -#define __SUPP_REG_H__ - -/* Macros for reading and writing support/special registers. */ - -#ifndef STRINGIFYFY -#define STRINGIFYFY(i) #i -#endif - -#ifndef STRINGIFY -#define STRINGIFY(i) STRINGIFYFY(i) -#endif - -#define SPEC_REG_BZ "BZ" -#define SPEC_REG_VR "VR" -#define SPEC_REG_PID "PID" -#define SPEC_REG_SRS "SRS" -#define SPEC_REG_WZ "WZ" -#define SPEC_REG_EXS "EXS" -#define SPEC_REG_EDA "EDA" -#define SPEC_REG_MOF "MOF" -#define SPEC_REG_DZ "DZ" -#define SPEC_REG_EBP "EBP" -#define SPEC_REG_ERP "ERP" -#define SPEC_REG_SRP "SRP" -#define SPEC_REG_NRP "NRP" -#define SPEC_REG_CCS "CCS" -#define SPEC_REG_USP "USP" -#define SPEC_REG_SPC "SPC" - -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define RW_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 -#define RW_MM_TLB_PGD 7 - -#define BANK_GC 0 -#define BANK_IM 1 -#define BANK_DM 2 -#define BANK_BP 3 - -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_R0 8 -#define RW_GC_R1 9 - -#define SPEC_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $" r : : "r" (v)); - -#define SPEC_REG_RD(r,v) \ -__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); - -#define NOP() \ - __asm__ __volatile__ ("nop"); - -#define SUPP_BANK_SEL(b) \ - SPEC_REG_WR(SPEC_REG_SRS,b); \ - NOP(); \ - NOP(); \ - NOP(); - -#define SUPP_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - : : "r" (v)); - -#define SUPP_REG_RD(r,v) \ -__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); - -#endif /* __SUPP_REG_H__ */ diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h deleted file mode 100644 index c0ada33bf90f..000000000000 --- a/include/asm-cris/arch-v32/intmem.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_INTMEM_H -#define _ASM_CRIS_INTMEM_H - -void* crisv32_intmem_alloc(unsigned size, unsigned align); -void crisv32_intmem_free(void* addr); -void* crisv32_intmem_phys_to_virt(unsigned long addr); -unsigned long crisv32_intmem_virt_to_phys(void *addr); - -#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h deleted file mode 100644 index 6b38912f29ba..000000000000 --- a/include/asm-cris/arch-v32/io.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_IO_H -#define _ASM_ARCH_CRIS_IO_H - -#include -#include -#include -#include - -enum crisv32_io_dir -{ - crisv32_io_dir_in = 0, - crisv32_io_dir_out = 1 -}; - -struct crisv32_ioport -{ - volatile unsigned long *oe; - volatile unsigned long *data; - volatile unsigned long *data_in; - unsigned int pin_count; - spinlock_t lock; -}; - -struct crisv32_iopin -{ - struct crisv32_ioport* port; - int bit; -}; - -extern struct crisv32_ioport crisv32_ioports[]; - -extern struct crisv32_iopin crisv32_led1_green; -extern struct crisv32_iopin crisv32_led1_red; -extern struct crisv32_iopin crisv32_led2_green; -extern struct crisv32_iopin crisv32_led2_red; -extern struct crisv32_iopin crisv32_led3_green; -extern struct crisv32_iopin crisv32_led3_red; - -extern struct crisv32_iopin crisv32_led_net0_green; -extern struct crisv32_iopin crisv32_led_net0_red; -extern struct crisv32_iopin crisv32_led_net1_green; -extern struct crisv32_iopin crisv32_led_net1_red; - -static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) -{ - long flags; - spin_lock_irqsave(&iopin->port->lock, flags); - - if (val) - *iopin->port->data |= iopin->bit; - else - *iopin->port->data &= ~iopin->bit; - - spin_unlock_irqrestore(&iopin->port->lock, flags); -} - -static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, - enum crisv32_io_dir dir) -{ - long flags; - spin_lock_irqsave(&iopin->port->lock, flags); - - if (dir == crisv32_io_dir_in) - *iopin->port->oe &= ~iopin->bit; - else - *iopin->port->oe |= iopin->bit; - - spin_unlock_irqrestore(&iopin->port->lock, flags); -} - -static inline int crisv32_io_rd(struct crisv32_iopin* iopin) -{ - return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); -} - -int crisv32_io_get(struct crisv32_iopin* iopin, - unsigned int port, unsigned int pin); -int crisv32_io_get_name(struct crisv32_iopin* iopin, - const char *name); - -#define CRIS_LED_OFF 0x00 -#define CRIS_LED_GREEN 0x01 -#define CRIS_LED_RED 0x02 -#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) - -#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) -#define CRIS_LED_NETWORK_GRP0_SET(x) \ - do { \ - CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#else -#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} -#endif - -#define CRIS_LED_NETWORK_GRP0_SET_G(x) \ - crisv32_io_set(&crisv32_led_net0_green, !(x)); - -#define CRIS_LED_NETWORK_GRP0_SET_R(x) \ - crisv32_io_set(&crisv32_led_net0_red, !(x)); - -#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) -#define CRIS_LED_NETWORK_GRP1_SET(x) \ - do { \ - CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#else -#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} -#endif - -#define CRIS_LED_NETWORK_GRP1_SET_G(x) \ - crisv32_io_set(&crisv32_led_net1_green, !(x)); - -#define CRIS_LED_NETWORK_GRP1_SET_R(x) \ - crisv32_io_set(&crisv32_led_net1_red, !(x)); - -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ - } while (0) - -#define CRIS_LED_ACTIVE_SET_G(x) \ - crisv32_io_set(&crisv32_led2_green, !(x)); -#define CRIS_LED_ACTIVE_SET_R(x) \ - crisv32_io_set(&crisv32_led2_red, !(x)); -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - crisv32_io_set(&crisv32_led3_green, !(x)); \ - crisv32_io_set(&crisv32_led3_red, !(x)); \ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - crisv32_io_set(&crisv32_led3_green, !(x)); - -#endif diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h deleted file mode 100644 index 9e4c9fbdfddf..000000000000 --- a/include/asm-cris/arch-v32/irq.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include - -/* Number of non-cpu interrupts. */ -#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ -#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ -#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ -#if NR_REAL_IRQS > 32 -#define MACH_IRQS 64 -#else -#define MACH_IRQS 32 -#endif - -#ifndef __ASSEMBLY__ -/* Global IRQ vector. */ -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ - -void mask_irq(int irq); -void unmask_irq(int irq); - -void set_exception_vector(int n, irqvectptr addr); - -/* Save registers so that they match pt_regs. */ -#define SAVE_ALL \ - "subq 12,$sp\n\t" \ - "move $erp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $ccs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $spc,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $mof,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $acr,[$sp]\n\t" \ - "subq 14*4,$sp\n\t" \ - "movem $r13,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $r10,[$sp]\n" - -#define STR2(x) #x -#define STR(x) STR2(x) - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) - -/* - * The reason for setting the S-bit when debugging the kernel is that we want - * hardware breakpoints to remain active while we are in an exception handler. - * Note that we cannot simply copy S1, since we may come here from user-space, - * or any context where the S-bit wasn't set. - */ -#ifdef CONFIG_ETRAX_KGDB -#define KGDB_FIXUP \ - "move $ccs, $r10\n\t" \ - "or.d (1<<9), $r10\n\t" \ - "move $r10, $ccs\n\t" -#else -#define KGDB_FIXUP "" -#endif - -/* - * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock - * and jump to ret_from_intr which is found in entry.S. - * - * The reason for blocking the IRQ is to allow an sti() before the handler, - * which will acknowledge the interrupt, is run. The actual blocking is made - * by crisv32_do_IRQ. - */ -#define BUILD_IRQ(nr) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp, $r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 1, $r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); -/* - * This is subtle. The timer interrupt is crucial and it should not be disabled - * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it - * would have been BLOCK'ed, and then softirq's are run before we return here to - * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run - * and the watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the - * multiple_irq handler is run and it prioritizes the timer interrupt. However - * if we had BLOCK'edit here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt is - * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not - * be an sti() before the timer irq handler is run to acknowledge the interrupt. - */ -#define BUILD_TIMER_IRQ(nr, mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp,$r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 0,$r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_ARCH_IRQ_H */ diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h deleted file mode 100644 index 65e9d6ff0520..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/arbiter.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x7fe, - arbiter_cpu = 0x1800, - arbiter_all_clients = 0x7fff -}; - -enum { - arbiter_bar_all_clients = 0x1ff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h deleted file mode 100644 index 9e8eb13b601d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/dma.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ - -enum dma_owner { - dma_eth, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_ser4, - dma_iop, - dma_sser, - dma_strp, - dma_h264, - dma_jpeg -}; - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned bandwidth, enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h deleted file mode 100644 index 02855adf63e8..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __clkgen_defs_asm_h -#define __clkgen_defs_asm_h - -/* - * This file is autogenerated from - * file: clkgen.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope clkgen, type r */ -#define reg_clkgen_r_bootsel___boot_mode___lsb 0 -#define reg_clkgen_r_bootsel___boot_mode___width 5 -#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 -#define reg_clkgen_r_bootsel___intern_main_clk___width 1 -#define reg_clkgen_r_bootsel___intern_main_clk___bit 5 -#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 -#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 -#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 -#define reg_clkgen_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope clkgen, type rw */ -#define reg_clkgen_rw_clk_ctrl___pll___lsb 0 -#define reg_clkgen_rw_clk_ctrl___pll___width 1 -#define reg_clkgen_rw_clk_ctrl___pll___bit 0 -#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 -#define reg_clkgen_rw_clk_ctrl___cpu___width 1 -#define reg_clkgen_rw_clk_ctrl___cpu___bit 1 -#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 -#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 -#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 -#define reg_clkgen_rw_clk_ctrl___vin___lsb 3 -#define reg_clkgen_rw_clk_ctrl___vin___width 1 -#define reg_clkgen_rw_clk_ctrl___vin___bit 3 -#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 -#define reg_clkgen_rw_clk_ctrl___sclr___width 1 -#define reg_clkgen_rw_clk_ctrl___sclr___bit 4 -#define reg_clkgen_rw_clk_ctrl___h264___lsb 5 -#define reg_clkgen_rw_clk_ctrl___h264___width 1 -#define reg_clkgen_rw_clk_ctrl___h264___bit 5 -#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 -#define reg_clkgen_rw_clk_ctrl___ddr2___width 1 -#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 -#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 -#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 -#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 -#define reg_clkgen_rw_clk_ctrl___eth___lsb 8 -#define reg_clkgen_rw_clk_ctrl___eth___width 1 -#define reg_clkgen_rw_clk_ctrl___eth___bit 8 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 -#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 -#define reg_clkgen_rw_clk_ctrl___jpeg___width 1 -#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 -#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 -#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 -#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 -#define reg_clkgen_rw_clk_ctrl_offset 4 - - -/* Constants */ -#define regk_clkgen_eth1000_rx 0x0000000c -#define regk_clkgen_eth1000_tx 0x0000000e -#define regk_clkgen_eth100_rx 0x0000001d -#define regk_clkgen_eth100_rx_half 0x0000001c -#define regk_clkgen_eth100_tx 0x0000001f -#define regk_clkgen_eth100_tx_half 0x0000001e -#define regk_clkgen_nand_3_2 0x00000000 -#define regk_clkgen_nand_3_2_0x30 0x00000002 -#define regk_clkgen_nand_3_2_0x30_pll 0x00000012 -#define regk_clkgen_nand_3_2_pll 0x00000010 -#define regk_clkgen_nand_3_3 0x00000001 -#define regk_clkgen_nand_3_3_0x30 0x00000003 -#define regk_clkgen_nand_3_3_0x30_pll 0x00000013 -#define regk_clkgen_nand_3_3_pll 0x00000011 -#define regk_clkgen_nand_4_2 0x00000004 -#define regk_clkgen_nand_4_2_0x30 0x00000006 -#define regk_clkgen_nand_4_2_0x30_pll 0x00000016 -#define regk_clkgen_nand_4_2_pll 0x00000014 -#define regk_clkgen_nand_4_3 0x00000005 -#define regk_clkgen_nand_4_3_0x30 0x00000007 -#define regk_clkgen_nand_4_3_0x30_pll 0x00000017 -#define regk_clkgen_nand_4_3_pll 0x00000015 -#define regk_clkgen_nand_5_2 0x00000008 -#define regk_clkgen_nand_5_2_0x30 0x0000000a -#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a -#define regk_clkgen_nand_5_2_pll 0x00000018 -#define regk_clkgen_nand_5_3 0x00000009 -#define regk_clkgen_nand_5_3_0x30 0x0000000b -#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b -#define regk_clkgen_nand_5_3_pll 0x00000019 -#define regk_clkgen_no 0x00000000 -#define regk_clkgen_rw_clk_ctrl_default 0x00000002 -#define regk_clkgen_ser 0x0000000d -#define regk_clkgen_ser_pll 0x0000000f -#define regk_clkgen_yes 0x00000001 -#endif /* __clkgen_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h deleted file mode 100644 index b12be03edacb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h +++ /dev/null @@ -1,266 +0,0 @@ -#ifndef __ddr2_defs_asm_h -#define __ddr2_defs_asm_h - -/* - * This file is autogenerated from - * file: ddr2.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope ddr2, type rw */ -#define reg_ddr2_rw_cfg___col_width___lsb 0 -#define reg_ddr2_rw_cfg___col_width___width 4 -#define reg_ddr2_rw_cfg___nr_banks___lsb 4 -#define reg_ddr2_rw_cfg___nr_banks___width 1 -#define reg_ddr2_rw_cfg___nr_banks___bit 4 -#define reg_ddr2_rw_cfg___bw___lsb 5 -#define reg_ddr2_rw_cfg___bw___width 1 -#define reg_ddr2_rw_cfg___bw___bit 5 -#define reg_ddr2_rw_cfg___nr_ref___lsb 6 -#define reg_ddr2_rw_cfg___nr_ref___width 4 -#define reg_ddr2_rw_cfg___ref_interval___lsb 10 -#define reg_ddr2_rw_cfg___ref_interval___width 11 -#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 -#define reg_ddr2_rw_cfg___odt_ctrl___width 2 -#define reg_ddr2_rw_cfg___odt_mem___lsb 23 -#define reg_ddr2_rw_cfg___odt_mem___width 1 -#define reg_ddr2_rw_cfg___odt_mem___bit 23 -#define reg_ddr2_rw_cfg___imp_strength___lsb 24 -#define reg_ddr2_rw_cfg___imp_strength___width 1 -#define reg_ddr2_rw_cfg___imp_strength___bit 24 -#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 -#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 -#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 -#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 -#define reg_ddr2_rw_cfg___imp_cal_override___width 1 -#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 -#define reg_ddr2_rw_cfg___dll_override___lsb 27 -#define reg_ddr2_rw_cfg___dll_override___width 1 -#define reg_ddr2_rw_cfg___dll_override___bit 27 -#define reg_ddr2_rw_cfg_offset 0 - -/* Register rw_timing, scope ddr2, type rw */ -#define reg_ddr2_rw_timing___wr___lsb 0 -#define reg_ddr2_rw_timing___wr___width 3 -#define reg_ddr2_rw_timing___rcd___lsb 3 -#define reg_ddr2_rw_timing___rcd___width 3 -#define reg_ddr2_rw_timing___rp___lsb 6 -#define reg_ddr2_rw_timing___rp___width 3 -#define reg_ddr2_rw_timing___ras___lsb 9 -#define reg_ddr2_rw_timing___ras___width 4 -#define reg_ddr2_rw_timing___rfc___lsb 13 -#define reg_ddr2_rw_timing___rfc___width 7 -#define reg_ddr2_rw_timing___rc___lsb 20 -#define reg_ddr2_rw_timing___rc___width 5 -#define reg_ddr2_rw_timing___rtp___lsb 25 -#define reg_ddr2_rw_timing___rtp___width 2 -#define reg_ddr2_rw_timing___rtw___lsb 27 -#define reg_ddr2_rw_timing___rtw___width 3 -#define reg_ddr2_rw_timing___wtr___lsb 30 -#define reg_ddr2_rw_timing___wtr___width 2 -#define reg_ddr2_rw_timing_offset 4 - -/* Register rw_latency, scope ddr2, type rw */ -#define reg_ddr2_rw_latency___cas___lsb 0 -#define reg_ddr2_rw_latency___cas___width 3 -#define reg_ddr2_rw_latency___additive___lsb 3 -#define reg_ddr2_rw_latency___additive___width 3 -#define reg_ddr2_rw_latency_offset 8 - -/* Register rw_phy_cfg, scope ddr2, type rw */ -#define reg_ddr2_rw_phy_cfg___en___lsb 0 -#define reg_ddr2_rw_phy_cfg___en___width 1 -#define reg_ddr2_rw_phy_cfg___en___bit 0 -#define reg_ddr2_rw_phy_cfg_offset 12 - -/* Register rw_phy_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 -#define reg_ddr2_rw_phy_ctrl___rst___width 1 -#define reg_ddr2_rw_phy_ctrl___rst___bit 0 -#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 -#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 -#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 -#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 -#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 -#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 -#define reg_ddr2_rw_phy_ctrl_offset 16 - -/* Register rw_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 -#define reg_ddr2_rw_ctrl___mrs_data___width 16 -#define reg_ddr2_rw_ctrl___cmd___lsb 16 -#define reg_ddr2_rw_ctrl___cmd___width 8 -#define reg_ddr2_rw_ctrl_offset 20 - -/* Register rw_pwr_down, scope ddr2, type rw */ -#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 -#define reg_ddr2_rw_pwr_down___self_ref___width 2 -#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 -#define reg_ddr2_rw_pwr_down___phy_en___width 1 -#define reg_ddr2_rw_pwr_down___phy_en___bit 2 -#define reg_ddr2_rw_pwr_down_offset 24 - -/* Register r_stat, scope ddr2, type r */ -#define reg_ddr2_r_stat___dll_lock___lsb 0 -#define reg_ddr2_r_stat___dll_lock___width 1 -#define reg_ddr2_r_stat___dll_lock___bit 0 -#define reg_ddr2_r_stat___dll_delay_code___lsb 1 -#define reg_ddr2_r_stat___dll_delay_code___width 7 -#define reg_ddr2_r_stat___imp_cal_done___lsb 8 -#define reg_ddr2_r_stat___imp_cal_done___width 1 -#define reg_ddr2_r_stat___imp_cal_done___bit 8 -#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 -#define reg_ddr2_r_stat___imp_cal_fault___width 1 -#define reg_ddr2_r_stat___imp_cal_fault___bit 9 -#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 -#define reg_ddr2_r_stat___cal_imp_pu___width 4 -#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 -#define reg_ddr2_r_stat___cal_imp_pd___width 4 -#define reg_ddr2_r_stat_offset 28 - -/* Register rw_imp_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 -#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 -#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 -#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 -#define reg_ddr2_rw_imp_ctrl_offset 32 - -#define STRIDE_ddr2_rw_dll_ctrl 4 -/* Register rw_dll_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 -#define reg_ddr2_rw_dll_ctrl___mode___width 1 -#define reg_ddr2_rw_dll_ctrl___mode___bit 0 -#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 -#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 -#define reg_ddr2_rw_dll_ctrl_offset 36 - -#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 -/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 - - -/* Constants */ -#define regk_ddr2_al0 0x00000000 -#define regk_ddr2_al1 0x00000008 -#define regk_ddr2_al2 0x00000010 -#define regk_ddr2_al3 0x00000018 -#define regk_ddr2_al4 0x00000020 -#define regk_ddr2_auto 0x00000003 -#define regk_ddr2_bank4 0x00000000 -#define regk_ddr2_bank8 0x00000001 -#define regk_ddr2_bl4 0x00000002 -#define regk_ddr2_bl8 0x00000003 -#define regk_ddr2_bt_il 0x00000008 -#define regk_ddr2_bt_seq 0x00000000 -#define regk_ddr2_bw16 0x00000001 -#define regk_ddr2_bw32 0x00000000 -#define regk_ddr2_cas2 0x00000020 -#define regk_ddr2_cas3 0x00000030 -#define regk_ddr2_cas4 0x00000040 -#define regk_ddr2_cas5 0x00000050 -#define regk_ddr2_deselect 0x000000c0 -#define regk_ddr2_dic_weak 0x00000002 -#define regk_ddr2_direct 0x00000001 -#define regk_ddr2_dis 0x00000000 -#define regk_ddr2_dll_dis 0x00000001 -#define regk_ddr2_dll_en 0x00000000 -#define regk_ddr2_dll_rst 0x00000100 -#define regk_ddr2_emrs 0x00000081 -#define regk_ddr2_emrs2 0x00000082 -#define regk_ddr2_emrs3 0x00000083 -#define regk_ddr2_full 0x00000001 -#define regk_ddr2_hi_ref_rate 0x00000080 -#define regk_ddr2_mrs 0x00000080 -#define regk_ddr2_no 0x00000000 -#define regk_ddr2_nop 0x000000b8 -#define regk_ddr2_ocd_adj 0x00000200 -#define regk_ddr2_ocd_default 0x00000380 -#define regk_ddr2_ocd_drive0 0x00000100 -#define regk_ddr2_ocd_drive1 0x00000080 -#define regk_ddr2_ocd_exit 0x00000000 -#define regk_ddr2_odt_dis 0x00000000 -#define regk_ddr2_offs 0x00000000 -#define regk_ddr2_pre 0x00000090 -#define regk_ddr2_pre_all 0x00000400 -#define regk_ddr2_pwr_down_fast 0x00000000 -#define regk_ddr2_pwr_down_slow 0x00001000 -#define regk_ddr2_ref 0x00000088 -#define regk_ddr2_rtt150 0x00000040 -#define regk_ddr2_rtt50 0x00000044 -#define regk_ddr2_rtt75 0x00000004 -#define regk_ddr2_rw_cfg_default 0x00186000 -#define regk_ddr2_rw_dll_ctrl_default 0x00000000 -#define regk_ddr2_rw_dll_ctrl_size 0x00000004 -#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 -#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 -#define regk_ddr2_rw_latency_default 0x00000000 -#define regk_ddr2_rw_phy_cfg_default 0x00000000 -#define regk_ddr2_rw_pwr_down_default 0x00000000 -#define regk_ddr2_rw_timing_default 0x00000000 -#define regk_ddr2_s1Gb 0x0000001a -#define regk_ddr2_s256Mb 0x0000000f -#define regk_ddr2_s2Gb 0x00000027 -#define regk_ddr2_s4Gb 0x00000042 -#define regk_ddr2_s512Mb 0x00000015 -#define regk_ddr2_temp0_85 0x00000618 -#define regk_ddr2_temp85_95 0x0000030c -#define regk_ddr2_term150 0x00000002 -#define regk_ddr2_term50 0x00000003 -#define regk_ddr2_term75 0x00000001 -#define regk_ddr2_test 0x00000080 -#define regk_ddr2_weak 0x00000000 -#define regk_ddr2_wr2 0x00000200 -#define regk_ddr2_wr3 0x00000400 -#define regk_ddr2_yes 0x00000001 -#endif /* __ddr2_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index df6714fda179..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,849 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: gio.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 32 -#define reg_gio_r_pa_din_offset 0 - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 32 -#define reg_gio_rw_pa_dout_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 32 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_pa_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte0_dout___data___lsb 0 -#define reg_gio_rw_pa_byte0_dout___data___width 8 -#define reg_gio_rw_pa_byte0_dout_offset 12 - -/* Register rw_pa_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte0_oe___oe___width 8 -#define reg_gio_rw_pa_byte0_oe_offset 16 - -/* Register rw_pa_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte1_dout___data___lsb 0 -#define reg_gio_rw_pa_byte1_dout___data___width 8 -#define reg_gio_rw_pa_byte1_dout_offset 20 - -/* Register rw_pa_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte1_oe___oe___width 8 -#define reg_gio_rw_pa_byte1_oe_offset 24 - -/* Register rw_pa_byte2_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte2_dout___data___lsb 0 -#define reg_gio_rw_pa_byte2_dout___data___width 8 -#define reg_gio_rw_pa_byte2_dout_offset 28 - -/* Register rw_pa_byte2_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte2_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte2_oe___oe___width 8 -#define reg_gio_rw_pa_byte2_oe_offset 32 - -/* Register rw_pa_byte3_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte3_dout___data___lsb 0 -#define reg_gio_rw_pa_byte3_dout___data___width 8 -#define reg_gio_rw_pa_byte3_dout_offset 36 - -/* Register rw_pa_byte3_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte3_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte3_oe___oe___width 8 -#define reg_gio_rw_pa_byte3_oe_offset 40 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 32 -#define reg_gio_r_pb_din_offset 44 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 32 -#define reg_gio_rw_pb_dout_offset 48 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 32 -#define reg_gio_rw_pb_oe_offset 52 - -/* Register rw_pb_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte0_dout___data___lsb 0 -#define reg_gio_rw_pb_byte0_dout___data___width 8 -#define reg_gio_rw_pb_byte0_dout_offset 56 - -/* Register rw_pb_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte0_oe___oe___width 8 -#define reg_gio_rw_pb_byte0_oe_offset 60 - -/* Register rw_pb_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte1_dout___data___lsb 0 -#define reg_gio_rw_pb_byte1_dout___data___width 8 -#define reg_gio_rw_pb_byte1_dout_offset 64 - -/* Register rw_pb_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte1_oe___oe___width 8 -#define reg_gio_rw_pb_byte1_oe_offset 68 - -/* Register rw_pb_byte2_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte2_dout___data___lsb 0 -#define reg_gio_rw_pb_byte2_dout___data___width 8 -#define reg_gio_rw_pb_byte2_dout_offset 72 - -/* Register rw_pb_byte2_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte2_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte2_oe___oe___width 8 -#define reg_gio_rw_pb_byte2_oe_offset 76 - -/* Register rw_pb_byte3_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte3_dout___data___lsb 0 -#define reg_gio_rw_pb_byte3_dout___data___width 8 -#define reg_gio_rw_pb_byte3_dout_offset 80 - -/* Register rw_pb_byte3_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte3_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte3_oe___oe___width 8 -#define reg_gio_rw_pb_byte3_oe_offset 84 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 16 -#define reg_gio_r_pc_din_offset 88 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 16 -#define reg_gio_rw_pc_dout_offset 92 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 16 -#define reg_gio_rw_pc_oe_offset 96 - -/* Register rw_pc_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pc_byte0_dout___data___lsb 0 -#define reg_gio_rw_pc_byte0_dout___data___width 8 -#define reg_gio_rw_pc_byte0_dout_offset 100 - -/* Register rw_pc_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pc_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pc_byte0_oe___oe___width 8 -#define reg_gio_rw_pc_byte0_oe_offset 104 - -/* Register rw_pc_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pc_byte1_dout___data___lsb 0 -#define reg_gio_rw_pc_byte1_dout___data___width 8 -#define reg_gio_rw_pc_byte1_dout_offset 108 - -/* Register rw_pc_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pc_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pc_byte1_oe___oe___width 8 -#define reg_gio_rw_pc_byte1_oe_offset 112 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 32 -#define reg_gio_r_pd_din_offset 116 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___intr0___lsb 0 -#define reg_gio_rw_intr_cfg___intr0___width 3 -#define reg_gio_rw_intr_cfg___intr1___lsb 3 -#define reg_gio_rw_intr_cfg___intr1___width 3 -#define reg_gio_rw_intr_cfg___intr2___lsb 6 -#define reg_gio_rw_intr_cfg___intr2___width 3 -#define reg_gio_rw_intr_cfg___intr3___lsb 9 -#define reg_gio_rw_intr_cfg___intr3___width 3 -#define reg_gio_rw_intr_cfg___intr4___lsb 12 -#define reg_gio_rw_intr_cfg___intr4___width 3 -#define reg_gio_rw_intr_cfg___intr5___lsb 15 -#define reg_gio_rw_intr_cfg___intr5___width 3 -#define reg_gio_rw_intr_cfg___intr6___lsb 18 -#define reg_gio_rw_intr_cfg___intr6___width 3 -#define reg_gio_rw_intr_cfg___intr7___lsb 21 -#define reg_gio_rw_intr_cfg___intr7___width 3 -#define reg_gio_rw_intr_cfg_offset 120 - -/* Register rw_intr_pins, scope gio, type rw */ -#define reg_gio_rw_intr_pins___intr0___lsb 0 -#define reg_gio_rw_intr_pins___intr0___width 4 -#define reg_gio_rw_intr_pins___intr1___lsb 4 -#define reg_gio_rw_intr_pins___intr1___width 4 -#define reg_gio_rw_intr_pins___intr2___lsb 8 -#define reg_gio_rw_intr_pins___intr2___width 4 -#define reg_gio_rw_intr_pins___intr3___lsb 12 -#define reg_gio_rw_intr_pins___intr3___width 4 -#define reg_gio_rw_intr_pins___intr4___lsb 16 -#define reg_gio_rw_intr_pins___intr4___width 4 -#define reg_gio_rw_intr_pins___intr5___lsb 20 -#define reg_gio_rw_intr_pins___intr5___width 4 -#define reg_gio_rw_intr_pins___intr6___lsb 24 -#define reg_gio_rw_intr_pins___intr6___width 4 -#define reg_gio_rw_intr_pins___intr7___lsb 28 -#define reg_gio_rw_intr_pins___intr7___width 4 -#define reg_gio_rw_intr_pins_offset 124 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___intr0___lsb 0 -#define reg_gio_rw_intr_mask___intr0___width 1 -#define reg_gio_rw_intr_mask___intr0___bit 0 -#define reg_gio_rw_intr_mask___intr1___lsb 1 -#define reg_gio_rw_intr_mask___intr1___width 1 -#define reg_gio_rw_intr_mask___intr1___bit 1 -#define reg_gio_rw_intr_mask___intr2___lsb 2 -#define reg_gio_rw_intr_mask___intr2___width 1 -#define reg_gio_rw_intr_mask___intr2___bit 2 -#define reg_gio_rw_intr_mask___intr3___lsb 3 -#define reg_gio_rw_intr_mask___intr3___width 1 -#define reg_gio_rw_intr_mask___intr3___bit 3 -#define reg_gio_rw_intr_mask___intr4___lsb 4 -#define reg_gio_rw_intr_mask___intr4___width 1 -#define reg_gio_rw_intr_mask___intr4___bit 4 -#define reg_gio_rw_intr_mask___intr5___lsb 5 -#define reg_gio_rw_intr_mask___intr5___width 1 -#define reg_gio_rw_intr_mask___intr5___bit 5 -#define reg_gio_rw_intr_mask___intr6___lsb 6 -#define reg_gio_rw_intr_mask___intr6___width 1 -#define reg_gio_rw_intr_mask___intr6___bit 6 -#define reg_gio_rw_intr_mask___intr7___lsb 7 -#define reg_gio_rw_intr_mask___intr7___width 1 -#define reg_gio_rw_intr_mask___intr7___bit 7 -#define reg_gio_rw_intr_mask___i2c0_done___lsb 8 -#define reg_gio_rw_intr_mask___i2c0_done___width 1 -#define reg_gio_rw_intr_mask___i2c0_done___bit 8 -#define reg_gio_rw_intr_mask___i2c1_done___lsb 9 -#define reg_gio_rw_intr_mask___i2c1_done___width 1 -#define reg_gio_rw_intr_mask___i2c1_done___bit 9 -#define reg_gio_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___intr0___lsb 0 -#define reg_gio_rw_ack_intr___intr0___width 1 -#define reg_gio_rw_ack_intr___intr0___bit 0 -#define reg_gio_rw_ack_intr___intr1___lsb 1 -#define reg_gio_rw_ack_intr___intr1___width 1 -#define reg_gio_rw_ack_intr___intr1___bit 1 -#define reg_gio_rw_ack_intr___intr2___lsb 2 -#define reg_gio_rw_ack_intr___intr2___width 1 -#define reg_gio_rw_ack_intr___intr2___bit 2 -#define reg_gio_rw_ack_intr___intr3___lsb 3 -#define reg_gio_rw_ack_intr___intr3___width 1 -#define reg_gio_rw_ack_intr___intr3___bit 3 -#define reg_gio_rw_ack_intr___intr4___lsb 4 -#define reg_gio_rw_ack_intr___intr4___width 1 -#define reg_gio_rw_ack_intr___intr4___bit 4 -#define reg_gio_rw_ack_intr___intr5___lsb 5 -#define reg_gio_rw_ack_intr___intr5___width 1 -#define reg_gio_rw_ack_intr___intr5___bit 5 -#define reg_gio_rw_ack_intr___intr6___lsb 6 -#define reg_gio_rw_ack_intr___intr6___width 1 -#define reg_gio_rw_ack_intr___intr6___bit 6 -#define reg_gio_rw_ack_intr___intr7___lsb 7 -#define reg_gio_rw_ack_intr___intr7___width 1 -#define reg_gio_rw_ack_intr___intr7___bit 7 -#define reg_gio_rw_ack_intr___i2c0_done___lsb 8 -#define reg_gio_rw_ack_intr___i2c0_done___width 1 -#define reg_gio_rw_ack_intr___i2c0_done___bit 8 -#define reg_gio_rw_ack_intr___i2c1_done___lsb 9 -#define reg_gio_rw_ack_intr___i2c1_done___width 1 -#define reg_gio_rw_ack_intr___i2c1_done___bit 9 -#define reg_gio_rw_ack_intr_offset 132 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___intr0___lsb 0 -#define reg_gio_r_intr___intr0___width 1 -#define reg_gio_r_intr___intr0___bit 0 -#define reg_gio_r_intr___intr1___lsb 1 -#define reg_gio_r_intr___intr1___width 1 -#define reg_gio_r_intr___intr1___bit 1 -#define reg_gio_r_intr___intr2___lsb 2 -#define reg_gio_r_intr___intr2___width 1 -#define reg_gio_r_intr___intr2___bit 2 -#define reg_gio_r_intr___intr3___lsb 3 -#define reg_gio_r_intr___intr3___width 1 -#define reg_gio_r_intr___intr3___bit 3 -#define reg_gio_r_intr___intr4___lsb 4 -#define reg_gio_r_intr___intr4___width 1 -#define reg_gio_r_intr___intr4___bit 4 -#define reg_gio_r_intr___intr5___lsb 5 -#define reg_gio_r_intr___intr5___width 1 -#define reg_gio_r_intr___intr5___bit 5 -#define reg_gio_r_intr___intr6___lsb 6 -#define reg_gio_r_intr___intr6___width 1 -#define reg_gio_r_intr___intr6___bit 6 -#define reg_gio_r_intr___intr7___lsb 7 -#define reg_gio_r_intr___intr7___width 1 -#define reg_gio_r_intr___intr7___bit 7 -#define reg_gio_r_intr___i2c0_done___lsb 8 -#define reg_gio_r_intr___i2c0_done___width 1 -#define reg_gio_r_intr___i2c0_done___bit 8 -#define reg_gio_r_intr___i2c1_done___lsb 9 -#define reg_gio_r_intr___i2c1_done___width 1 -#define reg_gio_r_intr___i2c1_done___bit 9 -#define reg_gio_r_intr_offset 136 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___intr0___lsb 0 -#define reg_gio_r_masked_intr___intr0___width 1 -#define reg_gio_r_masked_intr___intr0___bit 0 -#define reg_gio_r_masked_intr___intr1___lsb 1 -#define reg_gio_r_masked_intr___intr1___width 1 -#define reg_gio_r_masked_intr___intr1___bit 1 -#define reg_gio_r_masked_intr___intr2___lsb 2 -#define reg_gio_r_masked_intr___intr2___width 1 -#define reg_gio_r_masked_intr___intr2___bit 2 -#define reg_gio_r_masked_intr___intr3___lsb 3 -#define reg_gio_r_masked_intr___intr3___width 1 -#define reg_gio_r_masked_intr___intr3___bit 3 -#define reg_gio_r_masked_intr___intr4___lsb 4 -#define reg_gio_r_masked_intr___intr4___width 1 -#define reg_gio_r_masked_intr___intr4___bit 4 -#define reg_gio_r_masked_intr___intr5___lsb 5 -#define reg_gio_r_masked_intr___intr5___width 1 -#define reg_gio_r_masked_intr___intr5___bit 5 -#define reg_gio_r_masked_intr___intr6___lsb 6 -#define reg_gio_r_masked_intr___intr6___width 1 -#define reg_gio_r_masked_intr___intr6___bit 6 -#define reg_gio_r_masked_intr___intr7___lsb 7 -#define reg_gio_r_masked_intr___intr7___width 1 -#define reg_gio_r_masked_intr___intr7___bit 7 -#define reg_gio_r_masked_intr___i2c0_done___lsb 8 -#define reg_gio_r_masked_intr___i2c0_done___width 1 -#define reg_gio_r_masked_intr___i2c0_done___bit 8 -#define reg_gio_r_masked_intr___i2c1_done___lsb 9 -#define reg_gio_r_masked_intr___i2c1_done___width 1 -#define reg_gio_r_masked_intr___i2c1_done___bit 9 -#define reg_gio_r_masked_intr_offset 140 - -/* Register rw_i2c0_start, scope gio, type rw */ -#define reg_gio_rw_i2c0_start___run___lsb 0 -#define reg_gio_rw_i2c0_start___run___width 1 -#define reg_gio_rw_i2c0_start___run___bit 0 -#define reg_gio_rw_i2c0_start_offset 144 - -/* Register rw_i2c0_cfg, scope gio, type rw */ -#define reg_gio_rw_i2c0_cfg___en___lsb 0 -#define reg_gio_rw_i2c0_cfg___en___width 1 -#define reg_gio_rw_i2c0_cfg___en___bit 0 -#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 -#define reg_gio_rw_i2c0_cfg___bit_order___width 1 -#define reg_gio_rw_i2c0_cfg___bit_order___bit 1 -#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 -#define reg_gio_rw_i2c0_cfg___scl_io___width 1 -#define reg_gio_rw_i2c0_cfg___scl_io___bit 2 -#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 -#define reg_gio_rw_i2c0_cfg___scl_inv___width 1 -#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 -#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 -#define reg_gio_rw_i2c0_cfg___sda_io___width 1 -#define reg_gio_rw_i2c0_cfg___sda_io___bit 4 -#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 -#define reg_gio_rw_i2c0_cfg___sda_idle___width 1 -#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 -#define reg_gio_rw_i2c0_cfg_offset 148 - -/* Register rw_i2c0_ctrl, scope gio, type rw */ -#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 -#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 -#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 -#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 -#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 -#define reg_gio_rw_i2c0_ctrl___extra_start___width 3 -#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 -#define reg_gio_rw_i2c0_ctrl___early_end___width 1 -#define reg_gio_rw_i2c0_ctrl___early_end___bit 15 -#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 -#define reg_gio_rw_i2c0_ctrl___start_stop___width 1 -#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 -#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 -#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 -#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 -#define reg_gio_rw_i2c0_ctrl___start_bit___width 1 -#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 -#define reg_gio_rw_i2c0_ctrl___freq___lsb 25 -#define reg_gio_rw_i2c0_ctrl___freq___width 2 -#define reg_gio_rw_i2c0_ctrl_offset 152 - -/* Register rw_i2c0_data, scope gio, type rw */ -#define reg_gio_rw_i2c0_data___data0___lsb 0 -#define reg_gio_rw_i2c0_data___data0___width 8 -#define reg_gio_rw_i2c0_data___data1___lsb 8 -#define reg_gio_rw_i2c0_data___data1___width 8 -#define reg_gio_rw_i2c0_data___data2___lsb 16 -#define reg_gio_rw_i2c0_data___data2___width 8 -#define reg_gio_rw_i2c0_data___data3___lsb 24 -#define reg_gio_rw_i2c0_data___data3___width 8 -#define reg_gio_rw_i2c0_data_offset 156 - -/* Register rw_i2c0_data2, scope gio, type rw */ -#define reg_gio_rw_i2c0_data2___data4___lsb 0 -#define reg_gio_rw_i2c0_data2___data4___width 8 -#define reg_gio_rw_i2c0_data2___data5___lsb 8 -#define reg_gio_rw_i2c0_data2___data5___width 8 -#define reg_gio_rw_i2c0_data2___start_val___lsb 16 -#define reg_gio_rw_i2c0_data2___start_val___width 6 -#define reg_gio_rw_i2c0_data2___ack_val___lsb 22 -#define reg_gio_rw_i2c0_data2___ack_val___width 6 -#define reg_gio_rw_i2c0_data2_offset 160 - -/* Register rw_i2c1_start, scope gio, type rw */ -#define reg_gio_rw_i2c1_start___run___lsb 0 -#define reg_gio_rw_i2c1_start___run___width 1 -#define reg_gio_rw_i2c1_start___run___bit 0 -#define reg_gio_rw_i2c1_start_offset 164 - -/* Register rw_i2c1_cfg, scope gio, type rw */ -#define reg_gio_rw_i2c1_cfg___en___lsb 0 -#define reg_gio_rw_i2c1_cfg___en___width 1 -#define reg_gio_rw_i2c1_cfg___en___bit 0 -#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 -#define reg_gio_rw_i2c1_cfg___bit_order___width 1 -#define reg_gio_rw_i2c1_cfg___bit_order___bit 1 -#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 -#define reg_gio_rw_i2c1_cfg___scl_io___width 1 -#define reg_gio_rw_i2c1_cfg___scl_io___bit 2 -#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 -#define reg_gio_rw_i2c1_cfg___scl_inv___width 1 -#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 -#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 -#define reg_gio_rw_i2c1_cfg___sda0_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 -#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 -#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 -#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 -#define reg_gio_rw_i2c1_cfg___sda1_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 -#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 -#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 -#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 -#define reg_gio_rw_i2c1_cfg___sda2_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 -#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 -#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 -#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 -#define reg_gio_rw_i2c1_cfg___sda3_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 -#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 -#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 -#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 -#define reg_gio_rw_i2c1_cfg___sda_sel___width 2 -#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 -#define reg_gio_rw_i2c1_cfg___sen_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 -#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 -#define reg_gio_rw_i2c1_cfg___sen_inv___width 1 -#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 -#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 -#define reg_gio_rw_i2c1_cfg___sen_sel___width 2 -#define reg_gio_rw_i2c1_cfg_offset 168 - -/* Register rw_i2c1_ctrl, scope gio, type rw */ -#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 -#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 -#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 -#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 -#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 -#define reg_gio_rw_i2c1_ctrl___extra_start___width 3 -#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 -#define reg_gio_rw_i2c1_ctrl___early_end___width 1 -#define reg_gio_rw_i2c1_ctrl___early_end___bit 15 -#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 -#define reg_gio_rw_i2c1_ctrl___start_stop___width 1 -#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 -#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 -#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 -#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 -#define reg_gio_rw_i2c1_ctrl___start_bit___width 1 -#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 -#define reg_gio_rw_i2c1_ctrl___freq___lsb 25 -#define reg_gio_rw_i2c1_ctrl___freq___width 2 -#define reg_gio_rw_i2c1_ctrl_offset 172 - -/* Register rw_i2c1_data, scope gio, type rw */ -#define reg_gio_rw_i2c1_data___data0___lsb 0 -#define reg_gio_rw_i2c1_data___data0___width 8 -#define reg_gio_rw_i2c1_data___data1___lsb 8 -#define reg_gio_rw_i2c1_data___data1___width 8 -#define reg_gio_rw_i2c1_data___data2___lsb 16 -#define reg_gio_rw_i2c1_data___data2___width 8 -#define reg_gio_rw_i2c1_data___data3___lsb 24 -#define reg_gio_rw_i2c1_data___data3___width 8 -#define reg_gio_rw_i2c1_data_offset 176 - -/* Register rw_i2c1_data2, scope gio, type rw */ -#define reg_gio_rw_i2c1_data2___data4___lsb 0 -#define reg_gio_rw_i2c1_data2___data4___width 8 -#define reg_gio_rw_i2c1_data2___data5___lsb 8 -#define reg_gio_rw_i2c1_data2___data5___width 8 -#define reg_gio_rw_i2c1_data2___start_val___lsb 16 -#define reg_gio_rw_i2c1_data2___start_val___width 6 -#define reg_gio_rw_i2c1_data2___ack_val___lsb 22 -#define reg_gio_rw_i2c1_data2___ack_val___width 6 -#define reg_gio_rw_i2c1_data2_offset 180 - -/* Register r_ppwm_stat, scope gio, type r */ -#define reg_gio_r_ppwm_stat___freq___lsb 0 -#define reg_gio_r_ppwm_stat___freq___width 2 -#define reg_gio_r_ppwm_stat_offset 184 - -/* Register rw_ppwm_data, scope gio, type rw */ -#define reg_gio_rw_ppwm_data___data___lsb 0 -#define reg_gio_rw_ppwm_data___data___width 8 -#define reg_gio_rw_ppwm_data_offset 188 - -/* Register rw_pwm0_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm0_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm0_ctrl___mode___width 2 -#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm0_ctrl_offset 192 - -/* Register rw_pwm0_var, scope gio, type rw */ -#define reg_gio_rw_pwm0_var___lo___lsb 0 -#define reg_gio_rw_pwm0_var___lo___width 13 -#define reg_gio_rw_pwm0_var___hi___lsb 13 -#define reg_gio_rw_pwm0_var___hi___width 13 -#define reg_gio_rw_pwm0_var_offset 196 - -/* Register rw_pwm0_data, scope gio, type rw */ -#define reg_gio_rw_pwm0_data___data___lsb 0 -#define reg_gio_rw_pwm0_data___data___width 8 -#define reg_gio_rw_pwm0_data_offset 200 - -/* Register rw_pwm1_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm1_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm1_ctrl___mode___width 2 -#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm1_ctrl_offset 204 - -/* Register rw_pwm1_var, scope gio, type rw */ -#define reg_gio_rw_pwm1_var___lo___lsb 0 -#define reg_gio_rw_pwm1_var___lo___width 13 -#define reg_gio_rw_pwm1_var___hi___lsb 13 -#define reg_gio_rw_pwm1_var___hi___width 13 -#define reg_gio_rw_pwm1_var_offset 208 - -/* Register rw_pwm1_data, scope gio, type rw */ -#define reg_gio_rw_pwm1_data___data___lsb 0 -#define reg_gio_rw_pwm1_data___data___width 8 -#define reg_gio_rw_pwm1_data_offset 212 - -/* Register rw_pwm2_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm2_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm2_ctrl___mode___width 2 -#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm2_ctrl_offset 216 - -/* Register rw_pwm2_var, scope gio, type rw */ -#define reg_gio_rw_pwm2_var___lo___lsb 0 -#define reg_gio_rw_pwm2_var___lo___width 13 -#define reg_gio_rw_pwm2_var___hi___lsb 13 -#define reg_gio_rw_pwm2_var___hi___width 13 -#define reg_gio_rw_pwm2_var_offset 220 - -/* Register rw_pwm2_data, scope gio, type rw */ -#define reg_gio_rw_pwm2_data___data___lsb 0 -#define reg_gio_rw_pwm2_data___data___width 8 -#define reg_gio_rw_pwm2_data_offset 224 - -/* Register rw_pwm_in_cfg, scope gio, type rw */ -#define reg_gio_rw_pwm_in_cfg___pin___lsb 0 -#define reg_gio_rw_pwm_in_cfg___pin___width 3 -#define reg_gio_rw_pwm_in_cfg_offset 228 - -/* Register r_pwm_in_lo, scope gio, type r */ -#define reg_gio_r_pwm_in_lo___data___lsb 0 -#define reg_gio_r_pwm_in_lo___data___width 32 -#define reg_gio_r_pwm_in_lo_offset 232 - -/* Register r_pwm_in_hi, scope gio, type r */ -#define reg_gio_r_pwm_in_hi___data___lsb 0 -#define reg_gio_r_pwm_in_hi___data___width 32 -#define reg_gio_r_pwm_in_hi_offset 236 - -/* Register r_pwm_in_cnt, scope gio, type r */ -#define reg_gio_r_pwm_in_cnt___data___lsb 0 -#define reg_gio_r_pwm_in_cnt___data___width 32 -#define reg_gio_r_pwm_in_cnt_offset 240 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_f100k 0x00000000 -#define regk_gio_f1562 0x00000000 -#define regk_gio_f195 0x00000003 -#define regk_gio_f1m 0x00000002 -#define regk_gio_f390 0x00000002 -#define regk_gio_f400k 0x00000001 -#define regk_gio_f5m 0x00000003 -#define regk_gio_f781 0x00000001 -#define regk_gio_hi 0x00000001 -#define regk_gio_in 0x00000000 -#define regk_gio_intr_pa0 0x00000000 -#define regk_gio_intr_pa1 0x00000000 -#define regk_gio_intr_pa10 0x00000001 -#define regk_gio_intr_pa11 0x00000001 -#define regk_gio_intr_pa12 0x00000001 -#define regk_gio_intr_pa13 0x00000001 -#define regk_gio_intr_pa14 0x00000001 -#define regk_gio_intr_pa15 0x00000001 -#define regk_gio_intr_pa16 0x00000002 -#define regk_gio_intr_pa17 0x00000002 -#define regk_gio_intr_pa18 0x00000002 -#define regk_gio_intr_pa19 0x00000002 -#define regk_gio_intr_pa2 0x00000000 -#define regk_gio_intr_pa20 0x00000002 -#define regk_gio_intr_pa21 0x00000002 -#define regk_gio_intr_pa22 0x00000002 -#define regk_gio_intr_pa23 0x00000002 -#define regk_gio_intr_pa24 0x00000003 -#define regk_gio_intr_pa25 0x00000003 -#define regk_gio_intr_pa26 0x00000003 -#define regk_gio_intr_pa27 0x00000003 -#define regk_gio_intr_pa28 0x00000003 -#define regk_gio_intr_pa29 0x00000003 -#define regk_gio_intr_pa3 0x00000000 -#define regk_gio_intr_pa30 0x00000003 -#define regk_gio_intr_pa31 0x00000003 -#define regk_gio_intr_pa4 0x00000000 -#define regk_gio_intr_pa5 0x00000000 -#define regk_gio_intr_pa6 0x00000000 -#define regk_gio_intr_pa7 0x00000000 -#define regk_gio_intr_pa8 0x00000001 -#define regk_gio_intr_pa9 0x00000001 -#define regk_gio_intr_pb0 0x00000004 -#define regk_gio_intr_pb1 0x00000004 -#define regk_gio_intr_pb10 0x00000005 -#define regk_gio_intr_pb11 0x00000005 -#define regk_gio_intr_pb12 0x00000005 -#define regk_gio_intr_pb13 0x00000005 -#define regk_gio_intr_pb14 0x00000005 -#define regk_gio_intr_pb15 0x00000005 -#define regk_gio_intr_pb16 0x00000006 -#define regk_gio_intr_pb17 0x00000006 -#define regk_gio_intr_pb18 0x00000006 -#define regk_gio_intr_pb19 0x00000006 -#define regk_gio_intr_pb2 0x00000004 -#define regk_gio_intr_pb20 0x00000006 -#define regk_gio_intr_pb21 0x00000006 -#define regk_gio_intr_pb22 0x00000006 -#define regk_gio_intr_pb23 0x00000006 -#define regk_gio_intr_pb24 0x00000007 -#define regk_gio_intr_pb25 0x00000007 -#define regk_gio_intr_pb26 0x00000007 -#define regk_gio_intr_pb27 0x00000007 -#define regk_gio_intr_pb28 0x00000007 -#define regk_gio_intr_pb29 0x00000007 -#define regk_gio_intr_pb3 0x00000004 -#define regk_gio_intr_pb30 0x00000007 -#define regk_gio_intr_pb31 0x00000007 -#define regk_gio_intr_pb4 0x00000004 -#define regk_gio_intr_pb5 0x00000004 -#define regk_gio_intr_pb6 0x00000004 -#define regk_gio_intr_pb7 0x00000004 -#define regk_gio_intr_pb8 0x00000005 -#define regk_gio_intr_pb9 0x00000005 -#define regk_gio_intr_pc0 0x00000008 -#define regk_gio_intr_pc1 0x00000008 -#define regk_gio_intr_pc10 0x00000009 -#define regk_gio_intr_pc11 0x00000009 -#define regk_gio_intr_pc12 0x00000009 -#define regk_gio_intr_pc13 0x00000009 -#define regk_gio_intr_pc14 0x00000009 -#define regk_gio_intr_pc15 0x00000009 -#define regk_gio_intr_pc2 0x00000008 -#define regk_gio_intr_pc3 0x00000008 -#define regk_gio_intr_pc4 0x00000008 -#define regk_gio_intr_pc5 0x00000008 -#define regk_gio_intr_pc6 0x00000008 -#define regk_gio_intr_pc7 0x00000008 -#define regk_gio_intr_pc8 0x00000009 -#define regk_gio_intr_pc9 0x00000009 -#define regk_gio_intr_pd0 0x0000000c -#define regk_gio_intr_pd1 0x0000000c -#define regk_gio_intr_pd10 0x0000000d -#define regk_gio_intr_pd11 0x0000000d -#define regk_gio_intr_pd12 0x0000000d -#define regk_gio_intr_pd13 0x0000000d -#define regk_gio_intr_pd14 0x0000000d -#define regk_gio_intr_pd15 0x0000000d -#define regk_gio_intr_pd16 0x0000000e -#define regk_gio_intr_pd17 0x0000000e -#define regk_gio_intr_pd18 0x0000000e -#define regk_gio_intr_pd19 0x0000000e -#define regk_gio_intr_pd2 0x0000000c -#define regk_gio_intr_pd20 0x0000000e -#define regk_gio_intr_pd21 0x0000000e -#define regk_gio_intr_pd22 0x0000000e -#define regk_gio_intr_pd23 0x0000000e -#define regk_gio_intr_pd24 0x0000000f -#define regk_gio_intr_pd25 0x0000000f -#define regk_gio_intr_pd26 0x0000000f -#define regk_gio_intr_pd27 0x0000000f -#define regk_gio_intr_pd28 0x0000000f -#define regk_gio_intr_pd29 0x0000000f -#define regk_gio_intr_pd3 0x0000000c -#define regk_gio_intr_pd30 0x0000000f -#define regk_gio_intr_pd31 0x0000000f -#define regk_gio_intr_pd4 0x0000000c -#define regk_gio_intr_pd5 0x0000000c -#define regk_gio_intr_pd6 0x0000000c -#define regk_gio_intr_pd7 0x0000000c -#define regk_gio_intr_pd8 0x0000000d -#define regk_gio_intr_pd9 0x0000000d -#define regk_gio_lo 0x00000002 -#define regk_gio_lsb 0x00000000 -#define regk_gio_msb 0x00000001 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_no_switch 0x0000003f -#define regk_gio_none 0x00000007 -#define regk_gio_off 0x00000000 -#define regk_gio_opendrain 0x00000000 -#define regk_gio_out 0x00000001 -#define regk_gio_posedge 0x00000005 -#define regk_gio_pwm_hfp 0x00000002 -#define regk_gio_pwm_pa0 0x00000001 -#define regk_gio_pwm_pa19 0x00000004 -#define regk_gio_pwm_pa6 0x00000002 -#define regk_gio_pwm_pa7 0x00000003 -#define regk_gio_pwm_pb26 0x00000005 -#define regk_gio_pwm_pd23 0x00000006 -#define regk_gio_pwm_pd31 0x00000007 -#define regk_gio_pwm_std 0x00000001 -#define regk_gio_pwm_var 0x00000003 -#define regk_gio_rw_i2c0_cfg_default 0x00000020 -#define regk_gio_rw_i2c0_ctrl_default 0x00010000 -#define regk_gio_rw_i2c0_start_default 0x00000000 -#define regk_gio_rw_i2c1_cfg_default 0x00000aa0 -#define regk_gio_rw_i2c1_ctrl_default 0x00010000 -#define regk_gio_rw_i2c1_start_default 0x00000000 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_ppwm_data_default 0x00000000 -#define regk_gio_rw_pwm0_ctrl_default 0x00000000 -#define regk_gio_rw_pwm1_ctrl_default 0x00000000 -#define regk_gio_rw_pwm2_ctrl_default 0x00000000 -#define regk_gio_rw_pwm_in_cfg_default 0x00000000 -#define regk_gio_sda0 0x00000000 -#define regk_gio_sda1 0x00000001 -#define regk_gio_sda2 0x00000002 -#define regk_gio_sda3 0x00000003 -#define regk_gio_sen 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index c3dc9c666c46..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,572 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: pinmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___eth___lsb 0 -#define reg_pinmux_rw_hwprot___eth___width 1 -#define reg_pinmux_rw_hwprot___eth___bit 0 -#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 -#define reg_pinmux_rw_hwprot___eth_mdio___width 1 -#define reg_pinmux_rw_hwprot___eth_mdio___bit 1 -#define reg_pinmux_rw_hwprot___geth___lsb 2 -#define reg_pinmux_rw_hwprot___geth___width 1 -#define reg_pinmux_rw_hwprot___geth___bit 2 -#define reg_pinmux_rw_hwprot___tg___lsb 3 -#define reg_pinmux_rw_hwprot___tg___width 1 -#define reg_pinmux_rw_hwprot___tg___bit 3 -#define reg_pinmux_rw_hwprot___tg_clk___lsb 4 -#define reg_pinmux_rw_hwprot___tg_clk___width 1 -#define reg_pinmux_rw_hwprot___tg_clk___bit 4 -#define reg_pinmux_rw_hwprot___vout___lsb 5 -#define reg_pinmux_rw_hwprot___vout___width 1 -#define reg_pinmux_rw_hwprot___vout___bit 5 -#define reg_pinmux_rw_hwprot___vout_sync___lsb 6 -#define reg_pinmux_rw_hwprot___vout_sync___width 1 -#define reg_pinmux_rw_hwprot___vout_sync___bit 6 -#define reg_pinmux_rw_hwprot___ser1___lsb 7 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 7 -#define reg_pinmux_rw_hwprot___ser2___lsb 8 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 8 -#define reg_pinmux_rw_hwprot___ser3___lsb 9 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 9 -#define reg_pinmux_rw_hwprot___ser4___lsb 10 -#define reg_pinmux_rw_hwprot___ser4___width 1 -#define reg_pinmux_rw_hwprot___ser4___bit 10 -#define reg_pinmux_rw_hwprot___sser___lsb 11 -#define reg_pinmux_rw_hwprot___sser___width 1 -#define reg_pinmux_rw_hwprot___sser___bit 11 -#define reg_pinmux_rw_hwprot___pwm0___lsb 12 -#define reg_pinmux_rw_hwprot___pwm0___width 1 -#define reg_pinmux_rw_hwprot___pwm0___bit 12 -#define reg_pinmux_rw_hwprot___pwm1___lsb 13 -#define reg_pinmux_rw_hwprot___pwm1___width 1 -#define reg_pinmux_rw_hwprot___pwm1___bit 13 -#define reg_pinmux_rw_hwprot___pwm2___lsb 14 -#define reg_pinmux_rw_hwprot___pwm2___width 1 -#define reg_pinmux_rw_hwprot___pwm2___bit 14 -#define reg_pinmux_rw_hwprot___timer0___lsb 15 -#define reg_pinmux_rw_hwprot___timer0___width 1 -#define reg_pinmux_rw_hwprot___timer0___bit 15 -#define reg_pinmux_rw_hwprot___timer1___lsb 16 -#define reg_pinmux_rw_hwprot___timer1___width 1 -#define reg_pinmux_rw_hwprot___timer1___bit 16 -#define reg_pinmux_rw_hwprot___pio___lsb 17 -#define reg_pinmux_rw_hwprot___pio___width 1 -#define reg_pinmux_rw_hwprot___pio___bit 17 -#define reg_pinmux_rw_hwprot___i2c0___lsb 18 -#define reg_pinmux_rw_hwprot___i2c0___width 1 -#define reg_pinmux_rw_hwprot___i2c0___bit 18 -#define reg_pinmux_rw_hwprot___i2c1___lsb 19 -#define reg_pinmux_rw_hwprot___i2c1___width 1 -#define reg_pinmux_rw_hwprot___i2c1___bit 19 -#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 -#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 -#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 -#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 -#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 -#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 -#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 -#define reg_pinmux_rw_hwprot___i2c1_sen___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 -#define reg_pinmux_rw_hwprot_offset 0 - -/* Register rw_gio_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pa___pa0___lsb 0 -#define reg_pinmux_rw_gio_pa___pa0___width 1 -#define reg_pinmux_rw_gio_pa___pa0___bit 0 -#define reg_pinmux_rw_gio_pa___pa1___lsb 1 -#define reg_pinmux_rw_gio_pa___pa1___width 1 -#define reg_pinmux_rw_gio_pa___pa1___bit 1 -#define reg_pinmux_rw_gio_pa___pa2___lsb 2 -#define reg_pinmux_rw_gio_pa___pa2___width 1 -#define reg_pinmux_rw_gio_pa___pa2___bit 2 -#define reg_pinmux_rw_gio_pa___pa3___lsb 3 -#define reg_pinmux_rw_gio_pa___pa3___width 1 -#define reg_pinmux_rw_gio_pa___pa3___bit 3 -#define reg_pinmux_rw_gio_pa___pa4___lsb 4 -#define reg_pinmux_rw_gio_pa___pa4___width 1 -#define reg_pinmux_rw_gio_pa___pa4___bit 4 -#define reg_pinmux_rw_gio_pa___pa5___lsb 5 -#define reg_pinmux_rw_gio_pa___pa5___width 1 -#define reg_pinmux_rw_gio_pa___pa5___bit 5 -#define reg_pinmux_rw_gio_pa___pa6___lsb 6 -#define reg_pinmux_rw_gio_pa___pa6___width 1 -#define reg_pinmux_rw_gio_pa___pa6___bit 6 -#define reg_pinmux_rw_gio_pa___pa7___lsb 7 -#define reg_pinmux_rw_gio_pa___pa7___width 1 -#define reg_pinmux_rw_gio_pa___pa7___bit 7 -#define reg_pinmux_rw_gio_pa___pa8___lsb 8 -#define reg_pinmux_rw_gio_pa___pa8___width 1 -#define reg_pinmux_rw_gio_pa___pa8___bit 8 -#define reg_pinmux_rw_gio_pa___pa9___lsb 9 -#define reg_pinmux_rw_gio_pa___pa9___width 1 -#define reg_pinmux_rw_gio_pa___pa9___bit 9 -#define reg_pinmux_rw_gio_pa___pa10___lsb 10 -#define reg_pinmux_rw_gio_pa___pa10___width 1 -#define reg_pinmux_rw_gio_pa___pa10___bit 10 -#define reg_pinmux_rw_gio_pa___pa11___lsb 11 -#define reg_pinmux_rw_gio_pa___pa11___width 1 -#define reg_pinmux_rw_gio_pa___pa11___bit 11 -#define reg_pinmux_rw_gio_pa___pa12___lsb 12 -#define reg_pinmux_rw_gio_pa___pa12___width 1 -#define reg_pinmux_rw_gio_pa___pa12___bit 12 -#define reg_pinmux_rw_gio_pa___pa13___lsb 13 -#define reg_pinmux_rw_gio_pa___pa13___width 1 -#define reg_pinmux_rw_gio_pa___pa13___bit 13 -#define reg_pinmux_rw_gio_pa___pa14___lsb 14 -#define reg_pinmux_rw_gio_pa___pa14___width 1 -#define reg_pinmux_rw_gio_pa___pa14___bit 14 -#define reg_pinmux_rw_gio_pa___pa15___lsb 15 -#define reg_pinmux_rw_gio_pa___pa15___width 1 -#define reg_pinmux_rw_gio_pa___pa15___bit 15 -#define reg_pinmux_rw_gio_pa___pa16___lsb 16 -#define reg_pinmux_rw_gio_pa___pa16___width 1 -#define reg_pinmux_rw_gio_pa___pa16___bit 16 -#define reg_pinmux_rw_gio_pa___pa17___lsb 17 -#define reg_pinmux_rw_gio_pa___pa17___width 1 -#define reg_pinmux_rw_gio_pa___pa17___bit 17 -#define reg_pinmux_rw_gio_pa___pa18___lsb 18 -#define reg_pinmux_rw_gio_pa___pa18___width 1 -#define reg_pinmux_rw_gio_pa___pa18___bit 18 -#define reg_pinmux_rw_gio_pa___pa19___lsb 19 -#define reg_pinmux_rw_gio_pa___pa19___width 1 -#define reg_pinmux_rw_gio_pa___pa19___bit 19 -#define reg_pinmux_rw_gio_pa___pa20___lsb 20 -#define reg_pinmux_rw_gio_pa___pa20___width 1 -#define reg_pinmux_rw_gio_pa___pa20___bit 20 -#define reg_pinmux_rw_gio_pa___pa21___lsb 21 -#define reg_pinmux_rw_gio_pa___pa21___width 1 -#define reg_pinmux_rw_gio_pa___pa21___bit 21 -#define reg_pinmux_rw_gio_pa___pa22___lsb 22 -#define reg_pinmux_rw_gio_pa___pa22___width 1 -#define reg_pinmux_rw_gio_pa___pa22___bit 22 -#define reg_pinmux_rw_gio_pa___pa23___lsb 23 -#define reg_pinmux_rw_gio_pa___pa23___width 1 -#define reg_pinmux_rw_gio_pa___pa23___bit 23 -#define reg_pinmux_rw_gio_pa___pa24___lsb 24 -#define reg_pinmux_rw_gio_pa___pa24___width 1 -#define reg_pinmux_rw_gio_pa___pa24___bit 24 -#define reg_pinmux_rw_gio_pa___pa25___lsb 25 -#define reg_pinmux_rw_gio_pa___pa25___width 1 -#define reg_pinmux_rw_gio_pa___pa25___bit 25 -#define reg_pinmux_rw_gio_pa___pa26___lsb 26 -#define reg_pinmux_rw_gio_pa___pa26___width 1 -#define reg_pinmux_rw_gio_pa___pa26___bit 26 -#define reg_pinmux_rw_gio_pa___pa27___lsb 27 -#define reg_pinmux_rw_gio_pa___pa27___width 1 -#define reg_pinmux_rw_gio_pa___pa27___bit 27 -#define reg_pinmux_rw_gio_pa___pa28___lsb 28 -#define reg_pinmux_rw_gio_pa___pa28___width 1 -#define reg_pinmux_rw_gio_pa___pa28___bit 28 -#define reg_pinmux_rw_gio_pa___pa29___lsb 29 -#define reg_pinmux_rw_gio_pa___pa29___width 1 -#define reg_pinmux_rw_gio_pa___pa29___bit 29 -#define reg_pinmux_rw_gio_pa___pa30___lsb 30 -#define reg_pinmux_rw_gio_pa___pa30___width 1 -#define reg_pinmux_rw_gio_pa___pa30___bit 30 -#define reg_pinmux_rw_gio_pa___pa31___lsb 31 -#define reg_pinmux_rw_gio_pa___pa31___width 1 -#define reg_pinmux_rw_gio_pa___pa31___bit 31 -#define reg_pinmux_rw_gio_pa_offset 4 - -/* Register rw_gio_pb, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pb___pb0___lsb 0 -#define reg_pinmux_rw_gio_pb___pb0___width 1 -#define reg_pinmux_rw_gio_pb___pb0___bit 0 -#define reg_pinmux_rw_gio_pb___pb1___lsb 1 -#define reg_pinmux_rw_gio_pb___pb1___width 1 -#define reg_pinmux_rw_gio_pb___pb1___bit 1 -#define reg_pinmux_rw_gio_pb___pb2___lsb 2 -#define reg_pinmux_rw_gio_pb___pb2___width 1 -#define reg_pinmux_rw_gio_pb___pb2___bit 2 -#define reg_pinmux_rw_gio_pb___pb3___lsb 3 -#define reg_pinmux_rw_gio_pb___pb3___width 1 -#define reg_pinmux_rw_gio_pb___pb3___bit 3 -#define reg_pinmux_rw_gio_pb___pb4___lsb 4 -#define reg_pinmux_rw_gio_pb___pb4___width 1 -#define reg_pinmux_rw_gio_pb___pb4___bit 4 -#define reg_pinmux_rw_gio_pb___pb5___lsb 5 -#define reg_pinmux_rw_gio_pb___pb5___width 1 -#define reg_pinmux_rw_gio_pb___pb5___bit 5 -#define reg_pinmux_rw_gio_pb___pb6___lsb 6 -#define reg_pinmux_rw_gio_pb___pb6___width 1 -#define reg_pinmux_rw_gio_pb___pb6___bit 6 -#define reg_pinmux_rw_gio_pb___pb7___lsb 7 -#define reg_pinmux_rw_gio_pb___pb7___width 1 -#define reg_pinmux_rw_gio_pb___pb7___bit 7 -#define reg_pinmux_rw_gio_pb___pb8___lsb 8 -#define reg_pinmux_rw_gio_pb___pb8___width 1 -#define reg_pinmux_rw_gio_pb___pb8___bit 8 -#define reg_pinmux_rw_gio_pb___pb9___lsb 9 -#define reg_pinmux_rw_gio_pb___pb9___width 1 -#define reg_pinmux_rw_gio_pb___pb9___bit 9 -#define reg_pinmux_rw_gio_pb___pb10___lsb 10 -#define reg_pinmux_rw_gio_pb___pb10___width 1 -#define reg_pinmux_rw_gio_pb___pb10___bit 10 -#define reg_pinmux_rw_gio_pb___pb11___lsb 11 -#define reg_pinmux_rw_gio_pb___pb11___width 1 -#define reg_pinmux_rw_gio_pb___pb11___bit 11 -#define reg_pinmux_rw_gio_pb___pb12___lsb 12 -#define reg_pinmux_rw_gio_pb___pb12___width 1 -#define reg_pinmux_rw_gio_pb___pb12___bit 12 -#define reg_pinmux_rw_gio_pb___pb13___lsb 13 -#define reg_pinmux_rw_gio_pb___pb13___width 1 -#define reg_pinmux_rw_gio_pb___pb13___bit 13 -#define reg_pinmux_rw_gio_pb___pb14___lsb 14 -#define reg_pinmux_rw_gio_pb___pb14___width 1 -#define reg_pinmux_rw_gio_pb___pb14___bit 14 -#define reg_pinmux_rw_gio_pb___pb15___lsb 15 -#define reg_pinmux_rw_gio_pb___pb15___width 1 -#define reg_pinmux_rw_gio_pb___pb15___bit 15 -#define reg_pinmux_rw_gio_pb___pb16___lsb 16 -#define reg_pinmux_rw_gio_pb___pb16___width 1 -#define reg_pinmux_rw_gio_pb___pb16___bit 16 -#define reg_pinmux_rw_gio_pb___pb17___lsb 17 -#define reg_pinmux_rw_gio_pb___pb17___width 1 -#define reg_pinmux_rw_gio_pb___pb17___bit 17 -#define reg_pinmux_rw_gio_pb___pb18___lsb 18 -#define reg_pinmux_rw_gio_pb___pb18___width 1 -#define reg_pinmux_rw_gio_pb___pb18___bit 18 -#define reg_pinmux_rw_gio_pb___pb19___lsb 19 -#define reg_pinmux_rw_gio_pb___pb19___width 1 -#define reg_pinmux_rw_gio_pb___pb19___bit 19 -#define reg_pinmux_rw_gio_pb___pb20___lsb 20 -#define reg_pinmux_rw_gio_pb___pb20___width 1 -#define reg_pinmux_rw_gio_pb___pb20___bit 20 -#define reg_pinmux_rw_gio_pb___pb21___lsb 21 -#define reg_pinmux_rw_gio_pb___pb21___width 1 -#define reg_pinmux_rw_gio_pb___pb21___bit 21 -#define reg_pinmux_rw_gio_pb___pb22___lsb 22 -#define reg_pinmux_rw_gio_pb___pb22___width 1 -#define reg_pinmux_rw_gio_pb___pb22___bit 22 -#define reg_pinmux_rw_gio_pb___pb23___lsb 23 -#define reg_pinmux_rw_gio_pb___pb23___width 1 -#define reg_pinmux_rw_gio_pb___pb23___bit 23 -#define reg_pinmux_rw_gio_pb___pb24___lsb 24 -#define reg_pinmux_rw_gio_pb___pb24___width 1 -#define reg_pinmux_rw_gio_pb___pb24___bit 24 -#define reg_pinmux_rw_gio_pb___pb25___lsb 25 -#define reg_pinmux_rw_gio_pb___pb25___width 1 -#define reg_pinmux_rw_gio_pb___pb25___bit 25 -#define reg_pinmux_rw_gio_pb___pb26___lsb 26 -#define reg_pinmux_rw_gio_pb___pb26___width 1 -#define reg_pinmux_rw_gio_pb___pb26___bit 26 -#define reg_pinmux_rw_gio_pb___pb27___lsb 27 -#define reg_pinmux_rw_gio_pb___pb27___width 1 -#define reg_pinmux_rw_gio_pb___pb27___bit 27 -#define reg_pinmux_rw_gio_pb___pb28___lsb 28 -#define reg_pinmux_rw_gio_pb___pb28___width 1 -#define reg_pinmux_rw_gio_pb___pb28___bit 28 -#define reg_pinmux_rw_gio_pb___pb29___lsb 29 -#define reg_pinmux_rw_gio_pb___pb29___width 1 -#define reg_pinmux_rw_gio_pb___pb29___bit 29 -#define reg_pinmux_rw_gio_pb___pb30___lsb 30 -#define reg_pinmux_rw_gio_pb___pb30___width 1 -#define reg_pinmux_rw_gio_pb___pb30___bit 30 -#define reg_pinmux_rw_gio_pb___pb31___lsb 31 -#define reg_pinmux_rw_gio_pb___pb31___width 1 -#define reg_pinmux_rw_gio_pb___pb31___bit 31 -#define reg_pinmux_rw_gio_pb_offset 8 - -/* Register rw_gio_pc, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pc___pc0___lsb 0 -#define reg_pinmux_rw_gio_pc___pc0___width 1 -#define reg_pinmux_rw_gio_pc___pc0___bit 0 -#define reg_pinmux_rw_gio_pc___pc1___lsb 1 -#define reg_pinmux_rw_gio_pc___pc1___width 1 -#define reg_pinmux_rw_gio_pc___pc1___bit 1 -#define reg_pinmux_rw_gio_pc___pc2___lsb 2 -#define reg_pinmux_rw_gio_pc___pc2___width 1 -#define reg_pinmux_rw_gio_pc___pc2___bit 2 -#define reg_pinmux_rw_gio_pc___pc3___lsb 3 -#define reg_pinmux_rw_gio_pc___pc3___width 1 -#define reg_pinmux_rw_gio_pc___pc3___bit 3 -#define reg_pinmux_rw_gio_pc___pc4___lsb 4 -#define reg_pinmux_rw_gio_pc___pc4___width 1 -#define reg_pinmux_rw_gio_pc___pc4___bit 4 -#define reg_pinmux_rw_gio_pc___pc5___lsb 5 -#define reg_pinmux_rw_gio_pc___pc5___width 1 -#define reg_pinmux_rw_gio_pc___pc5___bit 5 -#define reg_pinmux_rw_gio_pc___pc6___lsb 6 -#define reg_pinmux_rw_gio_pc___pc6___width 1 -#define reg_pinmux_rw_gio_pc___pc6___bit 6 -#define reg_pinmux_rw_gio_pc___pc7___lsb 7 -#define reg_pinmux_rw_gio_pc___pc7___width 1 -#define reg_pinmux_rw_gio_pc___pc7___bit 7 -#define reg_pinmux_rw_gio_pc___pc8___lsb 8 -#define reg_pinmux_rw_gio_pc___pc8___width 1 -#define reg_pinmux_rw_gio_pc___pc8___bit 8 -#define reg_pinmux_rw_gio_pc___pc9___lsb 9 -#define reg_pinmux_rw_gio_pc___pc9___width 1 -#define reg_pinmux_rw_gio_pc___pc9___bit 9 -#define reg_pinmux_rw_gio_pc___pc10___lsb 10 -#define reg_pinmux_rw_gio_pc___pc10___width 1 -#define reg_pinmux_rw_gio_pc___pc10___bit 10 -#define reg_pinmux_rw_gio_pc___pc11___lsb 11 -#define reg_pinmux_rw_gio_pc___pc11___width 1 -#define reg_pinmux_rw_gio_pc___pc11___bit 11 -#define reg_pinmux_rw_gio_pc___pc12___lsb 12 -#define reg_pinmux_rw_gio_pc___pc12___width 1 -#define reg_pinmux_rw_gio_pc___pc12___bit 12 -#define reg_pinmux_rw_gio_pc___pc13___lsb 13 -#define reg_pinmux_rw_gio_pc___pc13___width 1 -#define reg_pinmux_rw_gio_pc___pc13___bit 13 -#define reg_pinmux_rw_gio_pc___pc14___lsb 14 -#define reg_pinmux_rw_gio_pc___pc14___width 1 -#define reg_pinmux_rw_gio_pc___pc14___bit 14 -#define reg_pinmux_rw_gio_pc___pc15___lsb 15 -#define reg_pinmux_rw_gio_pc___pc15___width 1 -#define reg_pinmux_rw_gio_pc___pc15___bit 15 -#define reg_pinmux_rw_gio_pc_offset 12 - -/* Register rw_iop_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pa___pa0___lsb 0 -#define reg_pinmux_rw_iop_pa___pa0___width 1 -#define reg_pinmux_rw_iop_pa___pa0___bit 0 -#define reg_pinmux_rw_iop_pa___pa1___lsb 1 -#define reg_pinmux_rw_iop_pa___pa1___width 1 -#define reg_pinmux_rw_iop_pa___pa1___bit 1 -#define reg_pinmux_rw_iop_pa___pa2___lsb 2 -#define reg_pinmux_rw_iop_pa___pa2___width 1 -#define reg_pinmux_rw_iop_pa___pa2___bit 2 -#define reg_pinmux_rw_iop_pa___pa3___lsb 3 -#define reg_pinmux_rw_iop_pa___pa3___width 1 -#define reg_pinmux_rw_iop_pa___pa3___bit 3 -#define reg_pinmux_rw_iop_pa___pa4___lsb 4 -#define reg_pinmux_rw_iop_pa___pa4___width 1 -#define reg_pinmux_rw_iop_pa___pa4___bit 4 -#define reg_pinmux_rw_iop_pa___pa5___lsb 5 -#define reg_pinmux_rw_iop_pa___pa5___width 1 -#define reg_pinmux_rw_iop_pa___pa5___bit 5 -#define reg_pinmux_rw_iop_pa___pa6___lsb 6 -#define reg_pinmux_rw_iop_pa___pa6___width 1 -#define reg_pinmux_rw_iop_pa___pa6___bit 6 -#define reg_pinmux_rw_iop_pa___pa7___lsb 7 -#define reg_pinmux_rw_iop_pa___pa7___width 1 -#define reg_pinmux_rw_iop_pa___pa7___bit 7 -#define reg_pinmux_rw_iop_pa___pa8___lsb 8 -#define reg_pinmux_rw_iop_pa___pa8___width 1 -#define reg_pinmux_rw_iop_pa___pa8___bit 8 -#define reg_pinmux_rw_iop_pa___pa9___lsb 9 -#define reg_pinmux_rw_iop_pa___pa9___width 1 -#define reg_pinmux_rw_iop_pa___pa9___bit 9 -#define reg_pinmux_rw_iop_pa___pa10___lsb 10 -#define reg_pinmux_rw_iop_pa___pa10___width 1 -#define reg_pinmux_rw_iop_pa___pa10___bit 10 -#define reg_pinmux_rw_iop_pa___pa11___lsb 11 -#define reg_pinmux_rw_iop_pa___pa11___width 1 -#define reg_pinmux_rw_iop_pa___pa11___bit 11 -#define reg_pinmux_rw_iop_pa___pa12___lsb 12 -#define reg_pinmux_rw_iop_pa___pa12___width 1 -#define reg_pinmux_rw_iop_pa___pa12___bit 12 -#define reg_pinmux_rw_iop_pa___pa13___lsb 13 -#define reg_pinmux_rw_iop_pa___pa13___width 1 -#define reg_pinmux_rw_iop_pa___pa13___bit 13 -#define reg_pinmux_rw_iop_pa___pa14___lsb 14 -#define reg_pinmux_rw_iop_pa___pa14___width 1 -#define reg_pinmux_rw_iop_pa___pa14___bit 14 -#define reg_pinmux_rw_iop_pa___pa15___lsb 15 -#define reg_pinmux_rw_iop_pa___pa15___width 1 -#define reg_pinmux_rw_iop_pa___pa15___bit 15 -#define reg_pinmux_rw_iop_pa___pa16___lsb 16 -#define reg_pinmux_rw_iop_pa___pa16___width 1 -#define reg_pinmux_rw_iop_pa___pa16___bit 16 -#define reg_pinmux_rw_iop_pa___pa17___lsb 17 -#define reg_pinmux_rw_iop_pa___pa17___width 1 -#define reg_pinmux_rw_iop_pa___pa17___bit 17 -#define reg_pinmux_rw_iop_pa___pa18___lsb 18 -#define reg_pinmux_rw_iop_pa___pa18___width 1 -#define reg_pinmux_rw_iop_pa___pa18___bit 18 -#define reg_pinmux_rw_iop_pa___pa19___lsb 19 -#define reg_pinmux_rw_iop_pa___pa19___width 1 -#define reg_pinmux_rw_iop_pa___pa19___bit 19 -#define reg_pinmux_rw_iop_pa___pa20___lsb 20 -#define reg_pinmux_rw_iop_pa___pa20___width 1 -#define reg_pinmux_rw_iop_pa___pa20___bit 20 -#define reg_pinmux_rw_iop_pa___pa21___lsb 21 -#define reg_pinmux_rw_iop_pa___pa21___width 1 -#define reg_pinmux_rw_iop_pa___pa21___bit 21 -#define reg_pinmux_rw_iop_pa___pa22___lsb 22 -#define reg_pinmux_rw_iop_pa___pa22___width 1 -#define reg_pinmux_rw_iop_pa___pa22___bit 22 -#define reg_pinmux_rw_iop_pa___pa23___lsb 23 -#define reg_pinmux_rw_iop_pa___pa23___width 1 -#define reg_pinmux_rw_iop_pa___pa23___bit 23 -#define reg_pinmux_rw_iop_pa___pa24___lsb 24 -#define reg_pinmux_rw_iop_pa___pa24___width 1 -#define reg_pinmux_rw_iop_pa___pa24___bit 24 -#define reg_pinmux_rw_iop_pa___pa25___lsb 25 -#define reg_pinmux_rw_iop_pa___pa25___width 1 -#define reg_pinmux_rw_iop_pa___pa25___bit 25 -#define reg_pinmux_rw_iop_pa___pa26___lsb 26 -#define reg_pinmux_rw_iop_pa___pa26___width 1 -#define reg_pinmux_rw_iop_pa___pa26___bit 26 -#define reg_pinmux_rw_iop_pa___pa27___lsb 27 -#define reg_pinmux_rw_iop_pa___pa27___width 1 -#define reg_pinmux_rw_iop_pa___pa27___bit 27 -#define reg_pinmux_rw_iop_pa___pa28___lsb 28 -#define reg_pinmux_rw_iop_pa___pa28___width 1 -#define reg_pinmux_rw_iop_pa___pa28___bit 28 -#define reg_pinmux_rw_iop_pa___pa29___lsb 29 -#define reg_pinmux_rw_iop_pa___pa29___width 1 -#define reg_pinmux_rw_iop_pa___pa29___bit 29 -#define reg_pinmux_rw_iop_pa___pa30___lsb 30 -#define reg_pinmux_rw_iop_pa___pa30___width 1 -#define reg_pinmux_rw_iop_pa___pa30___bit 30 -#define reg_pinmux_rw_iop_pa___pa31___lsb 31 -#define reg_pinmux_rw_iop_pa___pa31___width 1 -#define reg_pinmux_rw_iop_pa___pa31___bit 31 -#define reg_pinmux_rw_iop_pa_offset 16 - -/* Register rw_iop_pb, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pb___pb0___lsb 0 -#define reg_pinmux_rw_iop_pb___pb0___width 1 -#define reg_pinmux_rw_iop_pb___pb0___bit 0 -#define reg_pinmux_rw_iop_pb___pb1___lsb 1 -#define reg_pinmux_rw_iop_pb___pb1___width 1 -#define reg_pinmux_rw_iop_pb___pb1___bit 1 -#define reg_pinmux_rw_iop_pb___pb2___lsb 2 -#define reg_pinmux_rw_iop_pb___pb2___width 1 -#define reg_pinmux_rw_iop_pb___pb2___bit 2 -#define reg_pinmux_rw_iop_pb___pb3___lsb 3 -#define reg_pinmux_rw_iop_pb___pb3___width 1 -#define reg_pinmux_rw_iop_pb___pb3___bit 3 -#define reg_pinmux_rw_iop_pb___pb4___lsb 4 -#define reg_pinmux_rw_iop_pb___pb4___width 1 -#define reg_pinmux_rw_iop_pb___pb4___bit 4 -#define reg_pinmux_rw_iop_pb___pb5___lsb 5 -#define reg_pinmux_rw_iop_pb___pb5___width 1 -#define reg_pinmux_rw_iop_pb___pb5___bit 5 -#define reg_pinmux_rw_iop_pb___pb6___lsb 6 -#define reg_pinmux_rw_iop_pb___pb6___width 1 -#define reg_pinmux_rw_iop_pb___pb6___bit 6 -#define reg_pinmux_rw_iop_pb___pb7___lsb 7 -#define reg_pinmux_rw_iop_pb___pb7___width 1 -#define reg_pinmux_rw_iop_pb___pb7___bit 7 -#define reg_pinmux_rw_iop_pb_offset 20 - -/* Register rw_iop_pio, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pio___d0___lsb 0 -#define reg_pinmux_rw_iop_pio___d0___width 1 -#define reg_pinmux_rw_iop_pio___d0___bit 0 -#define reg_pinmux_rw_iop_pio___d1___lsb 1 -#define reg_pinmux_rw_iop_pio___d1___width 1 -#define reg_pinmux_rw_iop_pio___d1___bit 1 -#define reg_pinmux_rw_iop_pio___d2___lsb 2 -#define reg_pinmux_rw_iop_pio___d2___width 1 -#define reg_pinmux_rw_iop_pio___d2___bit 2 -#define reg_pinmux_rw_iop_pio___d3___lsb 3 -#define reg_pinmux_rw_iop_pio___d3___width 1 -#define reg_pinmux_rw_iop_pio___d3___bit 3 -#define reg_pinmux_rw_iop_pio___d4___lsb 4 -#define reg_pinmux_rw_iop_pio___d4___width 1 -#define reg_pinmux_rw_iop_pio___d4___bit 4 -#define reg_pinmux_rw_iop_pio___d5___lsb 5 -#define reg_pinmux_rw_iop_pio___d5___width 1 -#define reg_pinmux_rw_iop_pio___d5___bit 5 -#define reg_pinmux_rw_iop_pio___d6___lsb 6 -#define reg_pinmux_rw_iop_pio___d6___width 1 -#define reg_pinmux_rw_iop_pio___d6___bit 6 -#define reg_pinmux_rw_iop_pio___d7___lsb 7 -#define reg_pinmux_rw_iop_pio___d7___width 1 -#define reg_pinmux_rw_iop_pio___d7___bit 7 -#define reg_pinmux_rw_iop_pio___rd_n___lsb 8 -#define reg_pinmux_rw_iop_pio___rd_n___width 1 -#define reg_pinmux_rw_iop_pio___rd_n___bit 8 -#define reg_pinmux_rw_iop_pio___wr_n___lsb 9 -#define reg_pinmux_rw_iop_pio___wr_n___width 1 -#define reg_pinmux_rw_iop_pio___wr_n___bit 9 -#define reg_pinmux_rw_iop_pio___a0___lsb 10 -#define reg_pinmux_rw_iop_pio___a0___width 1 -#define reg_pinmux_rw_iop_pio___a0___bit 10 -#define reg_pinmux_rw_iop_pio___a1___lsb 11 -#define reg_pinmux_rw_iop_pio___a1___width 1 -#define reg_pinmux_rw_iop_pio___a1___bit 11 -#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 -#define reg_pinmux_rw_iop_pio___ce0_n___width 1 -#define reg_pinmux_rw_iop_pio___ce0_n___bit 12 -#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 -#define reg_pinmux_rw_iop_pio___ce1_n___width 1 -#define reg_pinmux_rw_iop_pio___ce1_n___bit 13 -#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 -#define reg_pinmux_rw_iop_pio___ce2_n___width 1 -#define reg_pinmux_rw_iop_pio___ce2_n___bit 14 -#define reg_pinmux_rw_iop_pio___rdy___lsb 15 -#define reg_pinmux_rw_iop_pio___rdy___width 1 -#define reg_pinmux_rw_iop_pio___rdy___bit 15 -#define reg_pinmux_rw_iop_pio_offset 24 - -/* Register rw_iop_usb, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_usb___usb0___lsb 0 -#define reg_pinmux_rw_iop_usb___usb0___width 1 -#define reg_pinmux_rw_iop_usb___usb0___bit 0 -#define reg_pinmux_rw_iop_usb_offset 28 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_gio_pa_default 0x00000000 -#define regk_pinmux_rw_gio_pb_default 0x00000000 -#define regk_pinmux_rw_gio_pc_default 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_iop_pa_default 0x00000000 -#define regk_pinmux_rw_iop_pb_default 0x00000000 -#define regk_pinmux_rw_iop_pio_default 0x00000000 -#define regk_pinmux_rw_iop_usb_default 0x00000001 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h deleted file mode 100644 index 3907ef4921c8..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h +++ /dev/null @@ -1,337 +0,0 @@ -#ifndef __pio_defs_asm_h -#define __pio_defs_asm_h - -/* - * This file is autogenerated from - * file: pio.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope pio, type rw */ -#define reg_pio_rw_data_offset 64 - -/* Register rw_io_access0, scope pio, type rw */ -#define reg_pio_rw_io_access0___data___lsb 0 -#define reg_pio_rw_io_access0___data___width 8 -#define reg_pio_rw_io_access0_offset 0 - -/* Register rw_io_access1, scope pio, type rw */ -#define reg_pio_rw_io_access1___data___lsb 0 -#define reg_pio_rw_io_access1___data___width 8 -#define reg_pio_rw_io_access1_offset 4 - -/* Register rw_io_access2, scope pio, type rw */ -#define reg_pio_rw_io_access2___data___lsb 0 -#define reg_pio_rw_io_access2___data___width 8 -#define reg_pio_rw_io_access2_offset 8 - -/* Register rw_io_access3, scope pio, type rw */ -#define reg_pio_rw_io_access3___data___lsb 0 -#define reg_pio_rw_io_access3___data___width 8 -#define reg_pio_rw_io_access3_offset 12 - -/* Register rw_io_access4, scope pio, type rw */ -#define reg_pio_rw_io_access4___data___lsb 0 -#define reg_pio_rw_io_access4___data___width 8 -#define reg_pio_rw_io_access4_offset 16 - -/* Register rw_io_access5, scope pio, type rw */ -#define reg_pio_rw_io_access5___data___lsb 0 -#define reg_pio_rw_io_access5___data___width 8 -#define reg_pio_rw_io_access5_offset 20 - -/* Register rw_io_access6, scope pio, type rw */ -#define reg_pio_rw_io_access6___data___lsb 0 -#define reg_pio_rw_io_access6___data___width 8 -#define reg_pio_rw_io_access6_offset 24 - -/* Register rw_io_access7, scope pio, type rw */ -#define reg_pio_rw_io_access7___data___lsb 0 -#define reg_pio_rw_io_access7___data___width 8 -#define reg_pio_rw_io_access7_offset 28 - -/* Register rw_io_access8, scope pio, type rw */ -#define reg_pio_rw_io_access8___data___lsb 0 -#define reg_pio_rw_io_access8___data___width 8 -#define reg_pio_rw_io_access8_offset 32 - -/* Register rw_io_access9, scope pio, type rw */ -#define reg_pio_rw_io_access9___data___lsb 0 -#define reg_pio_rw_io_access9___data___width 8 -#define reg_pio_rw_io_access9_offset 36 - -/* Register rw_io_access10, scope pio, type rw */ -#define reg_pio_rw_io_access10___data___lsb 0 -#define reg_pio_rw_io_access10___data___width 8 -#define reg_pio_rw_io_access10_offset 40 - -/* Register rw_io_access11, scope pio, type rw */ -#define reg_pio_rw_io_access11___data___lsb 0 -#define reg_pio_rw_io_access11___data___width 8 -#define reg_pio_rw_io_access11_offset 44 - -/* Register rw_io_access12, scope pio, type rw */ -#define reg_pio_rw_io_access12___data___lsb 0 -#define reg_pio_rw_io_access12___data___width 8 -#define reg_pio_rw_io_access12_offset 48 - -/* Register rw_io_access13, scope pio, type rw */ -#define reg_pio_rw_io_access13___data___lsb 0 -#define reg_pio_rw_io_access13___data___width 8 -#define reg_pio_rw_io_access13_offset 52 - -/* Register rw_io_access14, scope pio, type rw */ -#define reg_pio_rw_io_access14___data___lsb 0 -#define reg_pio_rw_io_access14___data___width 8 -#define reg_pio_rw_io_access14_offset 56 - -/* Register rw_io_access15, scope pio, type rw */ -#define reg_pio_rw_io_access15___data___lsb 0 -#define reg_pio_rw_io_access15___data___width 8 -#define reg_pio_rw_io_access15_offset 60 - -/* Register rw_ce0_cfg, scope pio, type rw */ -#define reg_pio_rw_ce0_cfg___lw___lsb 0 -#define reg_pio_rw_ce0_cfg___lw___width 6 -#define reg_pio_rw_ce0_cfg___ew___lsb 6 -#define reg_pio_rw_ce0_cfg___ew___width 3 -#define reg_pio_rw_ce0_cfg___zw___lsb 9 -#define reg_pio_rw_ce0_cfg___zw___width 3 -#define reg_pio_rw_ce0_cfg___aw___lsb 12 -#define reg_pio_rw_ce0_cfg___aw___width 2 -#define reg_pio_rw_ce0_cfg___mode___lsb 14 -#define reg_pio_rw_ce0_cfg___mode___width 2 -#define reg_pio_rw_ce0_cfg_offset 68 - -/* Register rw_ce1_cfg, scope pio, type rw */ -#define reg_pio_rw_ce1_cfg___lw___lsb 0 -#define reg_pio_rw_ce1_cfg___lw___width 6 -#define reg_pio_rw_ce1_cfg___ew___lsb 6 -#define reg_pio_rw_ce1_cfg___ew___width 3 -#define reg_pio_rw_ce1_cfg___zw___lsb 9 -#define reg_pio_rw_ce1_cfg___zw___width 3 -#define reg_pio_rw_ce1_cfg___aw___lsb 12 -#define reg_pio_rw_ce1_cfg___aw___width 2 -#define reg_pio_rw_ce1_cfg___mode___lsb 14 -#define reg_pio_rw_ce1_cfg___mode___width 2 -#define reg_pio_rw_ce1_cfg_offset 72 - -/* Register rw_ce2_cfg, scope pio, type rw */ -#define reg_pio_rw_ce2_cfg___lw___lsb 0 -#define reg_pio_rw_ce2_cfg___lw___width 6 -#define reg_pio_rw_ce2_cfg___ew___lsb 6 -#define reg_pio_rw_ce2_cfg___ew___width 3 -#define reg_pio_rw_ce2_cfg___zw___lsb 9 -#define reg_pio_rw_ce2_cfg___zw___width 3 -#define reg_pio_rw_ce2_cfg___aw___lsb 12 -#define reg_pio_rw_ce2_cfg___aw___width 2 -#define reg_pio_rw_ce2_cfg___mode___lsb 14 -#define reg_pio_rw_ce2_cfg___mode___width 2 -#define reg_pio_rw_ce2_cfg_offset 76 - -/* Register rw_dout, scope pio, type rw */ -#define reg_pio_rw_dout___data___lsb 0 -#define reg_pio_rw_dout___data___width 8 -#define reg_pio_rw_dout___rd_n___lsb 8 -#define reg_pio_rw_dout___rd_n___width 1 -#define reg_pio_rw_dout___rd_n___bit 8 -#define reg_pio_rw_dout___wr_n___lsb 9 -#define reg_pio_rw_dout___wr_n___width 1 -#define reg_pio_rw_dout___wr_n___bit 9 -#define reg_pio_rw_dout___a0___lsb 10 -#define reg_pio_rw_dout___a0___width 1 -#define reg_pio_rw_dout___a0___bit 10 -#define reg_pio_rw_dout___a1___lsb 11 -#define reg_pio_rw_dout___a1___width 1 -#define reg_pio_rw_dout___a1___bit 11 -#define reg_pio_rw_dout___ce0_n___lsb 12 -#define reg_pio_rw_dout___ce0_n___width 1 -#define reg_pio_rw_dout___ce0_n___bit 12 -#define reg_pio_rw_dout___ce1_n___lsb 13 -#define reg_pio_rw_dout___ce1_n___width 1 -#define reg_pio_rw_dout___ce1_n___bit 13 -#define reg_pio_rw_dout___ce2_n___lsb 14 -#define reg_pio_rw_dout___ce2_n___width 1 -#define reg_pio_rw_dout___ce2_n___bit 14 -#define reg_pio_rw_dout___rdy___lsb 15 -#define reg_pio_rw_dout___rdy___width 1 -#define reg_pio_rw_dout___rdy___bit 15 -#define reg_pio_rw_dout_offset 80 - -/* Register rw_oe, scope pio, type rw */ -#define reg_pio_rw_oe___data___lsb 0 -#define reg_pio_rw_oe___data___width 8 -#define reg_pio_rw_oe___rd_n___lsb 8 -#define reg_pio_rw_oe___rd_n___width 1 -#define reg_pio_rw_oe___rd_n___bit 8 -#define reg_pio_rw_oe___wr_n___lsb 9 -#define reg_pio_rw_oe___wr_n___width 1 -#define reg_pio_rw_oe___wr_n___bit 9 -#define reg_pio_rw_oe___a0___lsb 10 -#define reg_pio_rw_oe___a0___width 1 -#define reg_pio_rw_oe___a0___bit 10 -#define reg_pio_rw_oe___a1___lsb 11 -#define reg_pio_rw_oe___a1___width 1 -#define reg_pio_rw_oe___a1___bit 11 -#define reg_pio_rw_oe___ce0_n___lsb 12 -#define reg_pio_rw_oe___ce0_n___width 1 -#define reg_pio_rw_oe___ce0_n___bit 12 -#define reg_pio_rw_oe___ce1_n___lsb 13 -#define reg_pio_rw_oe___ce1_n___width 1 -#define reg_pio_rw_oe___ce1_n___bit 13 -#define reg_pio_rw_oe___ce2_n___lsb 14 -#define reg_pio_rw_oe___ce2_n___width 1 -#define reg_pio_rw_oe___ce2_n___bit 14 -#define reg_pio_rw_oe___rdy___lsb 15 -#define reg_pio_rw_oe___rdy___width 1 -#define reg_pio_rw_oe___rdy___bit 15 -#define reg_pio_rw_oe_offset 84 - -/* Register rw_man_ctrl, scope pio, type rw */ -#define reg_pio_rw_man_ctrl___data___lsb 0 -#define reg_pio_rw_man_ctrl___data___width 8 -#define reg_pio_rw_man_ctrl___rd_n___lsb 8 -#define reg_pio_rw_man_ctrl___rd_n___width 1 -#define reg_pio_rw_man_ctrl___rd_n___bit 8 -#define reg_pio_rw_man_ctrl___wr_n___lsb 9 -#define reg_pio_rw_man_ctrl___wr_n___width 1 -#define reg_pio_rw_man_ctrl___wr_n___bit 9 -#define reg_pio_rw_man_ctrl___a0___lsb 10 -#define reg_pio_rw_man_ctrl___a0___width 1 -#define reg_pio_rw_man_ctrl___a0___bit 10 -#define reg_pio_rw_man_ctrl___a1___lsb 11 -#define reg_pio_rw_man_ctrl___a1___width 1 -#define reg_pio_rw_man_ctrl___a1___bit 11 -#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 -#define reg_pio_rw_man_ctrl___ce0_n___width 1 -#define reg_pio_rw_man_ctrl___ce0_n___bit 12 -#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 -#define reg_pio_rw_man_ctrl___ce1_n___width 1 -#define reg_pio_rw_man_ctrl___ce1_n___bit 13 -#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 -#define reg_pio_rw_man_ctrl___ce2_n___width 1 -#define reg_pio_rw_man_ctrl___ce2_n___bit 14 -#define reg_pio_rw_man_ctrl___rdy___lsb 15 -#define reg_pio_rw_man_ctrl___rdy___width 1 -#define reg_pio_rw_man_ctrl___rdy___bit 15 -#define reg_pio_rw_man_ctrl_offset 88 - -/* Register r_din, scope pio, type r */ -#define reg_pio_r_din___data___lsb 0 -#define reg_pio_r_din___data___width 8 -#define reg_pio_r_din___rd_n___lsb 8 -#define reg_pio_r_din___rd_n___width 1 -#define reg_pio_r_din___rd_n___bit 8 -#define reg_pio_r_din___wr_n___lsb 9 -#define reg_pio_r_din___wr_n___width 1 -#define reg_pio_r_din___wr_n___bit 9 -#define reg_pio_r_din___a0___lsb 10 -#define reg_pio_r_din___a0___width 1 -#define reg_pio_r_din___a0___bit 10 -#define reg_pio_r_din___a1___lsb 11 -#define reg_pio_r_din___a1___width 1 -#define reg_pio_r_din___a1___bit 11 -#define reg_pio_r_din___ce0_n___lsb 12 -#define reg_pio_r_din___ce0_n___width 1 -#define reg_pio_r_din___ce0_n___bit 12 -#define reg_pio_r_din___ce1_n___lsb 13 -#define reg_pio_r_din___ce1_n___width 1 -#define reg_pio_r_din___ce1_n___bit 13 -#define reg_pio_r_din___ce2_n___lsb 14 -#define reg_pio_r_din___ce2_n___width 1 -#define reg_pio_r_din___ce2_n___bit 14 -#define reg_pio_r_din___rdy___lsb 15 -#define reg_pio_r_din___rdy___width 1 -#define reg_pio_r_din___rdy___bit 15 -#define reg_pio_r_din_offset 92 - -/* Register r_stat, scope pio, type r */ -#define reg_pio_r_stat___busy___lsb 0 -#define reg_pio_r_stat___busy___width 1 -#define reg_pio_r_stat___busy___bit 0 -#define reg_pio_r_stat_offset 96 - -/* Register rw_intr_mask, scope pio, type rw */ -#define reg_pio_rw_intr_mask___rdy___lsb 0 -#define reg_pio_rw_intr_mask___rdy___width 1 -#define reg_pio_rw_intr_mask___rdy___bit 0 -#define reg_pio_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope pio, type rw */ -#define reg_pio_rw_ack_intr___rdy___lsb 0 -#define reg_pio_rw_ack_intr___rdy___width 1 -#define reg_pio_rw_ack_intr___rdy___bit 0 -#define reg_pio_rw_ack_intr_offset 104 - -/* Register r_intr, scope pio, type r */ -#define reg_pio_r_intr___rdy___lsb 0 -#define reg_pio_r_intr___rdy___width 1 -#define reg_pio_r_intr___rdy___bit 0 -#define reg_pio_r_intr_offset 108 - -/* Register r_masked_intr, scope pio, type r */ -#define reg_pio_r_masked_intr___rdy___lsb 0 -#define reg_pio_r_masked_intr___rdy___width 1 -#define reg_pio_r_masked_intr___rdy___bit 0 -#define reg_pio_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_pio_a2 0x00000003 -#define regk_pio_no 0x00000000 -#define regk_pio_normal 0x00000000 -#define regk_pio_rd 0x00000001 -#define regk_pio_rw_ce0_cfg_default 0x00000000 -#define regk_pio_rw_ce1_cfg_default 0x00000000 -#define regk_pio_rw_ce2_cfg_default 0x00000000 -#define regk_pio_rw_intr_mask_default 0x00000000 -#define regk_pio_rw_man_ctrl_default 0x00000000 -#define regk_pio_rw_oe_default 0x00000000 -#define regk_pio_wr 0x00000002 -#define regk_pio_wr_ce2 0x00000003 -#define regk_pio_yes 0x00000001 -#define regk_pio_yes_all 0x000000ff -#endif /* __pio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 89439e9610e2..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef __reg_map_asm_h -#define __reg_map_asm_h - -/* - * This file is autogenerated from - * file: reg.rmap - * - * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_ccd 0xb0000000 -#define regi_ccd_top 0xb0000000 -#define regi_ccd_dp 0xb0000400 -#define regi_ccd_stat 0xb0000800 -#define regi_ccd_tg 0xb0001000 -#define regi_cfg 0xb0002000 -#define regi_clkgen 0xb0004000 -#define regi_ddr2_ctrl 0xb0006000 -#define regi_dma0 0xb0008000 -#define regi_dma1 0xb000a000 -#define regi_dma11 0xb000c000 -#define regi_dma2 0xb000e000 -#define regi_dma3 0xb0010000 -#define regi_dma4 0xb0012000 -#define regi_dma5 0xb0014000 -#define regi_dma6 0xb0016000 -#define regi_dma7 0xb0018000 -#define regi_dma9 0xb001a000 -#define regi_eth 0xb001c000 -#define regi_gio 0xb0020000 -#define regi_h264 0xb0022000 -#define regi_hist 0xb0026000 -#define regi_iop 0xb0028000 -#define regi_iop_version 0xb0028000 -#define regi_iop_fifo_in_extra 0xb0028040 -#define regi_iop_fifo_out_extra 0xb0028080 -#define regi_iop_trigger_grp0 0xb00280c0 -#define regi_iop_trigger_grp1 0xb0028100 -#define regi_iop_trigger_grp2 0xb0028140 -#define regi_iop_trigger_grp3 0xb0028180 -#define regi_iop_trigger_grp4 0xb00281c0 -#define regi_iop_trigger_grp5 0xb0028200 -#define regi_iop_trigger_grp6 0xb0028240 -#define regi_iop_trigger_grp7 0xb0028280 -#define regi_iop_crc_par 0xb0028300 -#define regi_iop_dmc_in 0xb0028380 -#define regi_iop_dmc_out 0xb0028400 -#define regi_iop_fifo_in 0xb0028480 -#define regi_iop_fifo_out 0xb0028500 -#define regi_iop_scrc_in 0xb0028580 -#define regi_iop_scrc_out 0xb0028600 -#define regi_iop_timer_grp0 0xb0028680 -#define regi_iop_timer_grp1 0xb0028700 -#define regi_iop_sap_in 0xb0028800 -#define regi_iop_sap_out 0xb0028900 -#define regi_iop_spu 0xb0028a00 -#define regi_iop_sw_cfg 0xb0028b00 -#define regi_iop_sw_cpu 0xb0028c00 -#define regi_iop_sw_mpu 0xb0028d00 -#define regi_iop_sw_spu 0xb0028e00 -#define regi_iop_mpu 0xb0029000 -#define regi_irq 0xb002a000 -#define regi_jpeg 0xb002c000 -#define regi_l2cache 0xb0030000 -#define regi_marb_bar 0xb0032000 -#define regi_marb_bar_bp0 0xb0032140 -#define regi_marb_bar_bp1 0xb0032180 -#define regi_marb_bar_bp2 0xb00321c0 -#define regi_marb_bar_bp3 0xb0032200 -#define regi_marb_foo 0xb0034000 -#define regi_marb_foo_bp0 0xb0034280 -#define regi_marb_foo_bp1 0xb00342c0 -#define regi_marb_foo_bp2 0xb0034300 -#define regi_marb_foo_bp3 0xb0034340 -#define regi_pinmux 0xb0038000 -#define regi_pio 0xb0036000 -#define regi_sclr 0xb003a000 -#define regi_sclr_fifo 0xb003c000 -#define regi_ser0 0xb003e000 -#define regi_ser1 0xb0040000 -#define regi_ser2 0xb0042000 -#define regi_ser3 0xb0044000 -#define regi_ser4 0xb0046000 -#define regi_sser 0xb0048000 -#define regi_strcop 0xb004a000 -#define regi_strdma0 0xb004e000 -#define regi_strdma1 0xb0050000 -#define regi_strdma2 0xb0052000 -#define regi_strdma3 0xb0054000 -#define regi_strdma5 0xb0056000 -#define regi_strmux 0xb004c000 -#define regi_timer0 0xb0058000 -#define regi_timer1 0xb005a000 -#define regi_trace 0xb005c000 -#define regi_vin 0xb005e000 -#define regi_vout 0xb0060000 -#endif /* __reg_map_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index b129e826fc34..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: timer.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_f90 0x00000003 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_vclk 0x00000002 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h deleted file mode 100644 index c1e9ba93b3a3..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h +++ /dev/null @@ -1,159 +0,0 @@ -#ifndef __clkgen_defs_h -#define __clkgen_defs_h - -/* - * This file is autogenerated from - * file: clkgen.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope clkgen */ - -/* Register r_bootsel, scope clkgen, type r */ -typedef struct { - unsigned int boot_mode : 5; - unsigned int intern_main_clk : 1; - unsigned int extern_usb2_clk : 1; - unsigned int dummy1 : 25; -} reg_clkgen_r_bootsel; -#define REG_RD_ADDR_clkgen_r_bootsel 0 - -/* Register rw_clk_ctrl, scope clkgen, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop_usb : 1; - unsigned int vin : 1; - unsigned int sclr : 1; - unsigned int h264 : 1; - unsigned int ddr2 : 1; - unsigned int vout_hist : 1; - unsigned int eth : 1; - unsigned int ccd_tg_200 : 1; - unsigned int dma0_1_eth : 1; - unsigned int ccd_tg_100 : 1; - unsigned int jpeg : 1; - unsigned int sser_ser_dma6_7 : 1; - unsigned int strdma0_2_video : 1; - unsigned int dma2_3_strcop : 1; - unsigned int dma4_5_iop : 1; - unsigned int dma9_11 : 1; - unsigned int memarb_bar_ddr : 1; - unsigned int sclr_h264 : 1; - unsigned int dummy1 : 12; -} reg_clkgen_rw_clk_ctrl; -#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 -#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 - - -/* Constants */ -enum { - regk_clkgen_eth1000_rx = 0x0000000c, - regk_clkgen_eth1000_tx = 0x0000000e, - regk_clkgen_eth100_rx = 0x0000001d, - regk_clkgen_eth100_rx_half = 0x0000001c, - regk_clkgen_eth100_tx = 0x0000001f, - regk_clkgen_eth100_tx_half = 0x0000001e, - regk_clkgen_nand_3_2 = 0x00000000, - regk_clkgen_nand_3_2_0x30 = 0x00000002, - regk_clkgen_nand_3_2_0x30_pll = 0x00000012, - regk_clkgen_nand_3_2_pll = 0x00000010, - regk_clkgen_nand_3_3 = 0x00000001, - regk_clkgen_nand_3_3_0x30 = 0x00000003, - regk_clkgen_nand_3_3_0x30_pll = 0x00000013, - regk_clkgen_nand_3_3_pll = 0x00000011, - regk_clkgen_nand_4_2 = 0x00000004, - regk_clkgen_nand_4_2_0x30 = 0x00000006, - regk_clkgen_nand_4_2_0x30_pll = 0x00000016, - regk_clkgen_nand_4_2_pll = 0x00000014, - regk_clkgen_nand_4_3 = 0x00000005, - regk_clkgen_nand_4_3_0x30 = 0x00000007, - regk_clkgen_nand_4_3_0x30_pll = 0x00000017, - regk_clkgen_nand_4_3_pll = 0x00000015, - regk_clkgen_nand_5_2 = 0x00000008, - regk_clkgen_nand_5_2_0x30 = 0x0000000a, - regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, - regk_clkgen_nand_5_2_pll = 0x00000018, - regk_clkgen_nand_5_3 = 0x00000009, - regk_clkgen_nand_5_3_0x30 = 0x0000000b, - regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, - regk_clkgen_nand_5_3_pll = 0x00000019, - regk_clkgen_no = 0x00000000, - regk_clkgen_rw_clk_ctrl_default = 0x00000002, - regk_clkgen_ser = 0x0000000d, - regk_clkgen_ser_pll = 0x0000000f, - regk_clkgen_yes = 0x00000001 -}; -#endif /* __clkgen_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h deleted file mode 100644 index 0f30e8bf946d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h +++ /dev/null @@ -1,281 +0,0 @@ -#ifndef __ddr2_defs_h -#define __ddr2_defs_h - -/* - * This file is autogenerated from - * file: ddr2.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ddr2 */ - -/* Register rw_cfg, scope ddr2, type rw */ -typedef struct { - unsigned int col_width : 4; - unsigned int nr_banks : 1; - unsigned int bw : 1; - unsigned int nr_ref : 4; - unsigned int ref_interval : 11; - unsigned int odt_ctrl : 2; - unsigned int odt_mem : 1; - unsigned int imp_strength : 1; - unsigned int auto_imp_cal : 1; - unsigned int imp_cal_override : 1; - unsigned int dll_override : 1; - unsigned int dummy1 : 4; -} reg_ddr2_rw_cfg; -#define REG_RD_ADDR_ddr2_rw_cfg 0 -#define REG_WR_ADDR_ddr2_rw_cfg 0 - -/* Register rw_timing, scope ddr2, type rw */ -typedef struct { - unsigned int wr : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int ras : 4; - unsigned int rfc : 7; - unsigned int rc : 5; - unsigned int rtp : 2; - unsigned int rtw : 3; - unsigned int wtr : 2; -} reg_ddr2_rw_timing; -#define REG_RD_ADDR_ddr2_rw_timing 4 -#define REG_WR_ADDR_ddr2_rw_timing 4 - -/* Register rw_latency, scope ddr2, type rw */ -typedef struct { - unsigned int cas : 3; - unsigned int additive : 3; - unsigned int dummy1 : 26; -} reg_ddr2_rw_latency; -#define REG_RD_ADDR_ddr2_rw_latency 8 -#define REG_WR_ADDR_ddr2_rw_latency 8 - -/* Register rw_phy_cfg, scope ddr2, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ddr2_rw_phy_cfg; -#define REG_RD_ADDR_ddr2_rw_phy_cfg 12 -#define REG_WR_ADDR_ddr2_rw_phy_cfg 12 - -/* Register rw_phy_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int rst : 1; - unsigned int cal_rst : 1; - unsigned int cal_start : 1; - unsigned int dummy1 : 29; -} reg_ddr2_rw_phy_ctrl; -#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 -#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 - -/* Register rw_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int mrs_data : 16; - unsigned int cmd : 8; - unsigned int dummy1 : 8; -} reg_ddr2_rw_ctrl; -#define REG_RD_ADDR_ddr2_rw_ctrl 20 -#define REG_WR_ADDR_ddr2_rw_ctrl 20 - -/* Register rw_pwr_down, scope ddr2, type rw */ -typedef struct { - unsigned int self_ref : 2; - unsigned int phy_en : 1; - unsigned int dummy1 : 29; -} reg_ddr2_rw_pwr_down; -#define REG_RD_ADDR_ddr2_rw_pwr_down 24 -#define REG_WR_ADDR_ddr2_rw_pwr_down 24 - -/* Register r_stat, scope ddr2, type r */ -typedef struct { - unsigned int dll_lock : 1; - unsigned int dll_delay_code : 7; - unsigned int imp_cal_done : 1; - unsigned int imp_cal_fault : 1; - unsigned int cal_imp_pu : 4; - unsigned int cal_imp_pd : 4; - unsigned int dummy1 : 14; -} reg_ddr2_r_stat; -#define REG_RD_ADDR_ddr2_r_stat 28 - -/* Register rw_imp_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int imp_pu : 4; - unsigned int imp_pd : 4; - unsigned int dummy1 : 24; -} reg_ddr2_rw_imp_ctrl; -#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 -#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 - -#define STRIDE_ddr2_rw_dll_ctrl 4 -/* Register rw_dll_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int clk_delay : 7; - unsigned int dummy1 : 24; -} reg_ddr2_rw_dll_ctrl; -#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 -#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 - -#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 -/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int dqs90_delay : 7; - unsigned int dqs180_delay : 7; - unsigned int dqs270_delay : 7; - unsigned int dqs360_delay : 7; - unsigned int dummy1 : 4; -} reg_ddr2_rw_dqs_dll_ctrl; -#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 -#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 - - -/* Constants */ -enum { - regk_ddr2_al0 = 0x00000000, - regk_ddr2_al1 = 0x00000008, - regk_ddr2_al2 = 0x00000010, - regk_ddr2_al3 = 0x00000018, - regk_ddr2_al4 = 0x00000020, - regk_ddr2_auto = 0x00000003, - regk_ddr2_bank4 = 0x00000000, - regk_ddr2_bank8 = 0x00000001, - regk_ddr2_bl4 = 0x00000002, - regk_ddr2_bl8 = 0x00000003, - regk_ddr2_bt_il = 0x00000008, - regk_ddr2_bt_seq = 0x00000000, - regk_ddr2_bw16 = 0x00000001, - regk_ddr2_bw32 = 0x00000000, - regk_ddr2_cas2 = 0x00000020, - regk_ddr2_cas3 = 0x00000030, - regk_ddr2_cas4 = 0x00000040, - regk_ddr2_cas5 = 0x00000050, - regk_ddr2_deselect = 0x000000c0, - regk_ddr2_dic_weak = 0x00000002, - regk_ddr2_direct = 0x00000001, - regk_ddr2_dis = 0x00000000, - regk_ddr2_dll_dis = 0x00000001, - regk_ddr2_dll_en = 0x00000000, - regk_ddr2_dll_rst = 0x00000100, - regk_ddr2_emrs = 0x00000081, - regk_ddr2_emrs2 = 0x00000082, - regk_ddr2_emrs3 = 0x00000083, - regk_ddr2_full = 0x00000001, - regk_ddr2_hi_ref_rate = 0x00000080, - regk_ddr2_mrs = 0x00000080, - regk_ddr2_no = 0x00000000, - regk_ddr2_nop = 0x000000b8, - regk_ddr2_ocd_adj = 0x00000200, - regk_ddr2_ocd_default = 0x00000380, - regk_ddr2_ocd_drive0 = 0x00000100, - regk_ddr2_ocd_drive1 = 0x00000080, - regk_ddr2_ocd_exit = 0x00000000, - regk_ddr2_odt_dis = 0x00000000, - regk_ddr2_offs = 0x00000000, - regk_ddr2_pre = 0x00000090, - regk_ddr2_pre_all = 0x00000400, - regk_ddr2_pwr_down_fast = 0x00000000, - regk_ddr2_pwr_down_slow = 0x00001000, - regk_ddr2_ref = 0x00000088, - regk_ddr2_rtt150 = 0x00000040, - regk_ddr2_rtt50 = 0x00000044, - regk_ddr2_rtt75 = 0x00000004, - regk_ddr2_rw_cfg_default = 0x00186000, - regk_ddr2_rw_dll_ctrl_default = 0x00000000, - regk_ddr2_rw_dll_ctrl_size = 0x00000004, - regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, - regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, - regk_ddr2_rw_latency_default = 0x00000000, - regk_ddr2_rw_phy_cfg_default = 0x00000000, - regk_ddr2_rw_pwr_down_default = 0x00000000, - regk_ddr2_rw_timing_default = 0x00000000, - regk_ddr2_s1Gb = 0x0000001a, - regk_ddr2_s256Mb = 0x0000000f, - regk_ddr2_s2Gb = 0x00000027, - regk_ddr2_s4Gb = 0x00000042, - regk_ddr2_s512Mb = 0x00000015, - regk_ddr2_temp0_85 = 0x00000618, - regk_ddr2_temp85_95 = 0x0000030c, - regk_ddr2_term150 = 0x00000002, - regk_ddr2_term50 = 0x00000003, - regk_ddr2_term75 = 0x00000001, - regk_ddr2_test = 0x00000080, - regk_ddr2_weak = 0x00000000, - regk_ddr2_wr2 = 0x00000200, - regk_ddr2_wr3 = 0x00000400, - regk_ddr2_yes = 0x00000001 -}; -#endif /* __ddr2_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h deleted file mode 100644 index 5d88e0db23ae..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h +++ /dev/null @@ -1,837 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: gio.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 0 - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 32; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 4 -#define REG_WR_ADDR_gio_rw_pa_dout 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 32; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_pa_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte0_dout; -#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 -#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 - -/* Register rw_pa_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte0_oe; -#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 -#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 - -/* Register rw_pa_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte1_dout; -#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 -#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 - -/* Register rw_pa_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte1_oe; -#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 -#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 - -/* Register rw_pa_byte2_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte2_dout; -#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 -#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 - -/* Register rw_pa_byte2_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte2_oe; -#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 -#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 - -/* Register rw_pa_byte3_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte3_dout; -#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 -#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 - -/* Register rw_pa_byte3_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte3_oe; -#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 -#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 44 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 32; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 48 -#define REG_WR_ADDR_gio_rw_pb_dout 48 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 32; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 52 -#define REG_WR_ADDR_gio_rw_pb_oe 52 - -/* Register rw_pb_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte0_dout; -#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 -#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 - -/* Register rw_pb_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte0_oe; -#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 -#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 - -/* Register rw_pb_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte1_dout; -#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 -#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 - -/* Register rw_pb_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte1_oe; -#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 -#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 - -/* Register rw_pb_byte2_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte2_dout; -#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 -#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 - -/* Register rw_pb_byte2_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte2_oe; -#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 -#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 - -/* Register rw_pb_byte3_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte3_dout; -#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 -#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 - -/* Register rw_pb_byte3_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte3_oe; -#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 -#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 88 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 92 -#define REG_WR_ADDR_gio_rw_pc_dout 92 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 16; - unsigned int dummy1 : 16; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 96 -#define REG_WR_ADDR_gio_rw_pc_oe 96 - -/* Register rw_pc_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte0_dout; -#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 -#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 - -/* Register rw_pc_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte0_oe; -#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 -#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 - -/* Register rw_pc_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte1_dout; -#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 -#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 - -/* Register rw_pc_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte1_oe; -#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 -#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 116 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 3; - unsigned int intr1 : 3; - unsigned int intr2 : 3; - unsigned int intr3 : 3; - unsigned int intr4 : 3; - unsigned int intr5 : 3; - unsigned int intr6 : 3; - unsigned int intr7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 120 -#define REG_WR_ADDR_gio_rw_intr_cfg 120 - -/* Register rw_intr_pins, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 4; - unsigned int intr1 : 4; - unsigned int intr2 : 4; - unsigned int intr3 : 4; - unsigned int intr4 : 4; - unsigned int intr5 : 4; - unsigned int intr6 : 4; - unsigned int intr7 : 4; -} reg_gio_rw_intr_pins; -#define REG_RD_ADDR_gio_rw_intr_pins 124 -#define REG_WR_ADDR_gio_rw_intr_pins 124 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 128 -#define REG_WR_ADDR_gio_rw_intr_mask 128 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 132 -#define REG_WR_ADDR_gio_rw_ack_intr 132 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 136 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 140 - -/* Register rw_i2c0_start, scope gio, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_gio_rw_i2c0_start; -#define REG_RD_ADDR_gio_rw_i2c0_start 144 -#define REG_WR_ADDR_gio_rw_i2c0_start 144 - -/* Register rw_i2c0_cfg, scope gio, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int bit_order : 1; - unsigned int scl_io : 1; - unsigned int scl_inv : 1; - unsigned int sda_io : 1; - unsigned int sda_idle : 1; - unsigned int dummy1 : 26; -} reg_gio_rw_i2c0_cfg; -#define REG_RD_ADDR_gio_rw_i2c0_cfg 148 -#define REG_WR_ADDR_gio_rw_i2c0_cfg 148 - -/* Register rw_i2c0_ctrl, scope gio, type rw */ -typedef struct { - unsigned int trf_bits : 6; - unsigned int switch_dir : 6; - unsigned int extra_start : 3; - unsigned int early_end : 1; - unsigned int start_stop : 1; - unsigned int ack_dir0 : 1; - unsigned int ack_dir1 : 1; - unsigned int ack_dir2 : 1; - unsigned int ack_dir3 : 1; - unsigned int ack_dir4 : 1; - unsigned int ack_dir5 : 1; - unsigned int ack_bit : 1; - unsigned int start_bit : 1; - unsigned int freq : 2; - unsigned int dummy1 : 5; -} reg_gio_rw_i2c0_ctrl; -#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 -#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 - -/* Register rw_i2c0_data, scope gio, type rw */ -typedef struct { - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int data2 : 8; - unsigned int data3 : 8; -} reg_gio_rw_i2c0_data; -#define REG_RD_ADDR_gio_rw_i2c0_data 156 -#define REG_WR_ADDR_gio_rw_i2c0_data 156 - -/* Register rw_i2c0_data2, scope gio, type rw */ -typedef struct { - unsigned int data4 : 8; - unsigned int data5 : 8; - unsigned int start_val : 6; - unsigned int ack_val : 6; - unsigned int dummy1 : 4; -} reg_gio_rw_i2c0_data2; -#define REG_RD_ADDR_gio_rw_i2c0_data2 160 -#define REG_WR_ADDR_gio_rw_i2c0_data2 160 - -/* Register rw_i2c1_start, scope gio, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_gio_rw_i2c1_start; -#define REG_RD_ADDR_gio_rw_i2c1_start 164 -#define REG_WR_ADDR_gio_rw_i2c1_start 164 - -/* Register rw_i2c1_cfg, scope gio, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int bit_order : 1; - unsigned int scl_io : 1; - unsigned int scl_inv : 1; - unsigned int sda0_io : 1; - unsigned int sda0_idle : 1; - unsigned int sda1_io : 1; - unsigned int sda1_idle : 1; - unsigned int sda2_io : 1; - unsigned int sda2_idle : 1; - unsigned int sda3_io : 1; - unsigned int sda3_idle : 1; - unsigned int sda_sel : 2; - unsigned int sen_idle : 1; - unsigned int sen_inv : 1; - unsigned int sen_sel : 2; - unsigned int dummy1 : 14; -} reg_gio_rw_i2c1_cfg; -#define REG_RD_ADDR_gio_rw_i2c1_cfg 168 -#define REG_WR_ADDR_gio_rw_i2c1_cfg 168 - -/* Register rw_i2c1_ctrl, scope gio, type rw */ -typedef struct { - unsigned int trf_bits : 6; - unsigned int switch_dir : 6; - unsigned int extra_start : 3; - unsigned int early_end : 1; - unsigned int start_stop : 1; - unsigned int ack_dir0 : 1; - unsigned int ack_dir1 : 1; - unsigned int ack_dir2 : 1; - unsigned int ack_dir3 : 1; - unsigned int ack_dir4 : 1; - unsigned int ack_dir5 : 1; - unsigned int ack_bit : 1; - unsigned int start_bit : 1; - unsigned int freq : 2; - unsigned int dummy1 : 5; -} reg_gio_rw_i2c1_ctrl; -#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 -#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 - -/* Register rw_i2c1_data, scope gio, type rw */ -typedef struct { - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int data2 : 8; - unsigned int data3 : 8; -} reg_gio_rw_i2c1_data; -#define REG_RD_ADDR_gio_rw_i2c1_data 176 -#define REG_WR_ADDR_gio_rw_i2c1_data 176 - -/* Register rw_i2c1_data2, scope gio, type rw */ -typedef struct { - unsigned int data4 : 8; - unsigned int data5 : 8; - unsigned int start_val : 6; - unsigned int ack_val : 6; - unsigned int dummy1 : 4; -} reg_gio_rw_i2c1_data2; -#define REG_RD_ADDR_gio_rw_i2c1_data2 180 -#define REG_WR_ADDR_gio_rw_i2c1_data2 180 - -/* Register r_ppwm_stat, scope gio, type r */ -typedef struct { - unsigned int freq : 2; - unsigned int dummy1 : 30; -} reg_gio_r_ppwm_stat; -#define REG_RD_ADDR_gio_r_ppwm_stat 184 - -/* Register rw_ppwm_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_ppwm_data; -#define REG_RD_ADDR_gio_rw_ppwm_data 188 -#define REG_WR_ADDR_gio_rw_ppwm_data 188 - -/* Register rw_pwm0_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm0_ctrl; -#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 -#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 - -/* Register rw_pwm0_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm0_var; -#define REG_RD_ADDR_gio_rw_pwm0_var 196 -#define REG_WR_ADDR_gio_rw_pwm0_var 196 - -/* Register rw_pwm0_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm0_data; -#define REG_RD_ADDR_gio_rw_pwm0_data 200 -#define REG_WR_ADDR_gio_rw_pwm0_data 200 - -/* Register rw_pwm1_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm1_ctrl; -#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 -#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 - -/* Register rw_pwm1_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm1_var; -#define REG_RD_ADDR_gio_rw_pwm1_var 208 -#define REG_WR_ADDR_gio_rw_pwm1_var 208 - -/* Register rw_pwm1_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm1_data; -#define REG_RD_ADDR_gio_rw_pwm1_data 212 -#define REG_WR_ADDR_gio_rw_pwm1_data 212 - -/* Register rw_pwm2_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm2_ctrl; -#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 -#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 - -/* Register rw_pwm2_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm2_var; -#define REG_RD_ADDR_gio_rw_pwm2_var 220 -#define REG_WR_ADDR_gio_rw_pwm2_var 220 - -/* Register rw_pwm2_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm2_data; -#define REG_RD_ADDR_gio_rw_pwm2_data 224 -#define REG_WR_ADDR_gio_rw_pwm2_data 224 - -/* Register rw_pwm_in_cfg, scope gio, type rw */ -typedef struct { - unsigned int pin : 3; - unsigned int dummy1 : 29; -} reg_gio_rw_pwm_in_cfg; -#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 -#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 - -/* Register r_pwm_in_lo, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_lo; -#define REG_RD_ADDR_gio_r_pwm_in_lo 232 - -/* Register r_pwm_in_hi, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_hi; -#define REG_RD_ADDR_gio_r_pwm_in_hi 236 - -/* Register r_pwm_in_cnt, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_cnt; -#define REG_RD_ADDR_gio_r_pwm_in_cnt 240 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_f100k = 0x00000000, - regk_gio_f1562 = 0x00000000, - regk_gio_f195 = 0x00000003, - regk_gio_f1m = 0x00000002, - regk_gio_f390 = 0x00000002, - regk_gio_f400k = 0x00000001, - regk_gio_f5m = 0x00000003, - regk_gio_f781 = 0x00000001, - regk_gio_hi = 0x00000001, - regk_gio_in = 0x00000000, - regk_gio_intr_pa0 = 0x00000000, - regk_gio_intr_pa1 = 0x00000000, - regk_gio_intr_pa10 = 0x00000001, - regk_gio_intr_pa11 = 0x00000001, - regk_gio_intr_pa12 = 0x00000001, - regk_gio_intr_pa13 = 0x00000001, - regk_gio_intr_pa14 = 0x00000001, - regk_gio_intr_pa15 = 0x00000001, - regk_gio_intr_pa16 = 0x00000002, - regk_gio_intr_pa17 = 0x00000002, - regk_gio_intr_pa18 = 0x00000002, - regk_gio_intr_pa19 = 0x00000002, - regk_gio_intr_pa2 = 0x00000000, - regk_gio_intr_pa20 = 0x00000002, - regk_gio_intr_pa21 = 0x00000002, - regk_gio_intr_pa22 = 0x00000002, - regk_gio_intr_pa23 = 0x00000002, - regk_gio_intr_pa24 = 0x00000003, - regk_gio_intr_pa25 = 0x00000003, - regk_gio_intr_pa26 = 0x00000003, - regk_gio_intr_pa27 = 0x00000003, - regk_gio_intr_pa28 = 0x00000003, - regk_gio_intr_pa29 = 0x00000003, - regk_gio_intr_pa3 = 0x00000000, - regk_gio_intr_pa30 = 0x00000003, - regk_gio_intr_pa31 = 0x00000003, - regk_gio_intr_pa4 = 0x00000000, - regk_gio_intr_pa5 = 0x00000000, - regk_gio_intr_pa6 = 0x00000000, - regk_gio_intr_pa7 = 0x00000000, - regk_gio_intr_pa8 = 0x00000001, - regk_gio_intr_pa9 = 0x00000001, - regk_gio_intr_pb0 = 0x00000004, - regk_gio_intr_pb1 = 0x00000004, - regk_gio_intr_pb10 = 0x00000005, - regk_gio_intr_pb11 = 0x00000005, - regk_gio_intr_pb12 = 0x00000005, - regk_gio_intr_pb13 = 0x00000005, - regk_gio_intr_pb14 = 0x00000005, - regk_gio_intr_pb15 = 0x00000005, - regk_gio_intr_pb16 = 0x00000006, - regk_gio_intr_pb17 = 0x00000006, - regk_gio_intr_pb18 = 0x00000006, - regk_gio_intr_pb19 = 0x00000006, - regk_gio_intr_pb2 = 0x00000004, - regk_gio_intr_pb20 = 0x00000006, - regk_gio_intr_pb21 = 0x00000006, - regk_gio_intr_pb22 = 0x00000006, - regk_gio_intr_pb23 = 0x00000006, - regk_gio_intr_pb24 = 0x00000007, - regk_gio_intr_pb25 = 0x00000007, - regk_gio_intr_pb26 = 0x00000007, - regk_gio_intr_pb27 = 0x00000007, - regk_gio_intr_pb28 = 0x00000007, - regk_gio_intr_pb29 = 0x00000007, - regk_gio_intr_pb3 = 0x00000004, - regk_gio_intr_pb30 = 0x00000007, - regk_gio_intr_pb31 = 0x00000007, - regk_gio_intr_pb4 = 0x00000004, - regk_gio_intr_pb5 = 0x00000004, - regk_gio_intr_pb6 = 0x00000004, - regk_gio_intr_pb7 = 0x00000004, - regk_gio_intr_pb8 = 0x00000005, - regk_gio_intr_pb9 = 0x00000005, - regk_gio_intr_pc0 = 0x00000008, - regk_gio_intr_pc1 = 0x00000008, - regk_gio_intr_pc10 = 0x00000009, - regk_gio_intr_pc11 = 0x00000009, - regk_gio_intr_pc12 = 0x00000009, - regk_gio_intr_pc13 = 0x00000009, - regk_gio_intr_pc14 = 0x00000009, - regk_gio_intr_pc15 = 0x00000009, - regk_gio_intr_pc2 = 0x00000008, - regk_gio_intr_pc3 = 0x00000008, - regk_gio_intr_pc4 = 0x00000008, - regk_gio_intr_pc5 = 0x00000008, - regk_gio_intr_pc6 = 0x00000008, - regk_gio_intr_pc7 = 0x00000008, - regk_gio_intr_pc8 = 0x00000009, - regk_gio_intr_pc9 = 0x00000009, - regk_gio_intr_pd0 = 0x0000000c, - regk_gio_intr_pd1 = 0x0000000c, - regk_gio_intr_pd10 = 0x0000000d, - regk_gio_intr_pd11 = 0x0000000d, - regk_gio_intr_pd12 = 0x0000000d, - regk_gio_intr_pd13 = 0x0000000d, - regk_gio_intr_pd14 = 0x0000000d, - regk_gio_intr_pd15 = 0x0000000d, - regk_gio_intr_pd16 = 0x0000000e, - regk_gio_intr_pd17 = 0x0000000e, - regk_gio_intr_pd18 = 0x0000000e, - regk_gio_intr_pd19 = 0x0000000e, - regk_gio_intr_pd2 = 0x0000000c, - regk_gio_intr_pd20 = 0x0000000e, - regk_gio_intr_pd21 = 0x0000000e, - regk_gio_intr_pd22 = 0x0000000e, - regk_gio_intr_pd23 = 0x0000000e, - regk_gio_intr_pd24 = 0x0000000f, - regk_gio_intr_pd25 = 0x0000000f, - regk_gio_intr_pd26 = 0x0000000f, - regk_gio_intr_pd27 = 0x0000000f, - regk_gio_intr_pd28 = 0x0000000f, - regk_gio_intr_pd29 = 0x0000000f, - regk_gio_intr_pd3 = 0x0000000c, - regk_gio_intr_pd30 = 0x0000000f, - regk_gio_intr_pd31 = 0x0000000f, - regk_gio_intr_pd4 = 0x0000000c, - regk_gio_intr_pd5 = 0x0000000c, - regk_gio_intr_pd6 = 0x0000000c, - regk_gio_intr_pd7 = 0x0000000c, - regk_gio_intr_pd8 = 0x0000000d, - regk_gio_intr_pd9 = 0x0000000d, - regk_gio_lo = 0x00000002, - regk_gio_lsb = 0x00000000, - regk_gio_msb = 0x00000001, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_no_switch = 0x0000003f, - regk_gio_none = 0x00000007, - regk_gio_off = 0x00000000, - regk_gio_opendrain = 0x00000000, - regk_gio_out = 0x00000001, - regk_gio_posedge = 0x00000005, - regk_gio_pwm_hfp = 0x00000002, - regk_gio_pwm_pa0 = 0x00000001, - regk_gio_pwm_pa19 = 0x00000004, - regk_gio_pwm_pa6 = 0x00000002, - regk_gio_pwm_pa7 = 0x00000003, - regk_gio_pwm_pb26 = 0x00000005, - regk_gio_pwm_pd23 = 0x00000006, - regk_gio_pwm_pd31 = 0x00000007, - regk_gio_pwm_std = 0x00000001, - regk_gio_pwm_var = 0x00000003, - regk_gio_rw_i2c0_cfg_default = 0x00000020, - regk_gio_rw_i2c0_ctrl_default = 0x00010000, - regk_gio_rw_i2c0_start_default = 0x00000000, - regk_gio_rw_i2c1_cfg_default = 0x00000aa0, - regk_gio_rw_i2c1_ctrl_default = 0x00010000, - regk_gio_rw_i2c1_start_default = 0x00000000, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_ppwm_data_default = 0x00000000, - regk_gio_rw_pwm0_ctrl_default = 0x00000000, - regk_gio_rw_pwm1_ctrl_default = 0x00000000, - regk_gio_rw_pwm2_ctrl_default = 0x00000000, - regk_gio_rw_pwm_in_cfg_default = 0x00000000, - regk_gio_sda0 = 0x00000000, - regk_gio_sda1 = 0x00000001, - regk_gio_sda2 = 0x00000002, - regk_gio_sda3 = 0x00000003, - regk_gio_sen = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h deleted file mode 100644 index bea699aa480e..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr - from intr_vect.r */ - -#ifndef _INTR_VECT_R -#define _INTR_VECT_R -#define TIMER0_INTR_VECT 0x31 -#define TIMER1_INTR_VECT 0x32 -#define DMA0_INTR_VECT 0x33 -#define DMA1_INTR_VECT 0x34 -#define DMA2_INTR_VECT 0x35 -#define DMA3_INTR_VECT 0x36 -#define DMA4_INTR_VECT 0x37 -#define DMA5_INTR_VECT 0x38 -#define DMA6_INTR_VECT 0x39 -#define DMA7_INTR_VECT 0x3a -#define DMA9_INTR_VECT 0x3b -#define DMA11_INTR_VECT 0x3c -#define GIO_INTR_VECT 0x3d -#define IOP0_INTR_VECT 0x3e -#define IOP1_INTR_VECT 0x3f -#define SER0_INTR_VECT 0x40 -#define SER1_INTR_VECT 0x41 -#define SER2_INTR_VECT 0x42 -#define SER3_INTR_VECT 0x43 -#define SER4_INTR_VECT 0x44 -#define SSER_INTR_VECT 0x45 -#define STRDMA0_INTR_VECT 0x46 -#define STRDMA1_INTR_VECT 0x47 -#define STRDMA2_INTR_VECT 0x48 -#define STRDMA3_INTR_VECT 0x49 -#define STRDMA5_INTR_VECT 0x4a -#define VIN_INTR_VECT 0x4b -#define VOUT_INTR_VECT 0x4c -#define JPEG_INTR_VECT 0x4d -#define H264_INTR_VECT 0x4e -#define HISTO_INTR_VECT 0x4f -#define CCD_INTR_VECT 0x50 -#define ETH_INTR_VECT 0x51 -#define MEMARB_BAR_INTR_VECT 0x52 -#define MEMARB_FOO_INTR_VECT 0x53 -#define PIO_INTR_VECT 0x54 -#define SCLR_INTR_VECT 0x55 -#define SCLR_FIFO_INTR_VECT 0x56 -#define IPI_INTR_VECT 0x57 -#define NBR_INTR_VECT 0x58 -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h deleted file mode 100644 index b820f6347c74..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,341 +0,0 @@ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: intr_vect.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - - -#define STRIDE_intr_vect_rw_mask 4 -/* Register rw_mask0, scope intr_vect, type rw */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_rw_mask0; -#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 -#define REG_RD_ADDR_intr_vect_rw_mask0 0 -#define REG_WR_ADDR_intr_vect_rw_mask0 0 - -#define STRIDE_intr_vect_r_vect 4 -/* Register r_vect0, scope intr_vect, type r */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_r_vect0; -#define reg_intr_vect_r_vect reg_intr_vect_r_vect0 -#define REG_RD_ADDR_intr_vect_r_vect 8 -#define REG_RD_ADDR_intr_vect_r_vect0 8 - -#define STRIDE_intr_vect_r_masked_vect 4 -/* Register r_masked_vect0, scope intr_vect, type r */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_r_masked_vect0; -#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 -#define REG_RD_ADDR_intr_vect_r_masked_vect0 16 -#define REG_RD_ADDR_intr_vect_r_masked_vect 16 - -#define STRIDE_intr_vect_rw_xmask 4 -/* Register rw_xmask0, scope intr_vect, type rw */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_rw_xmask0; -#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 -#define REG_RD_ADDR_intr_vect_rw_xmask0 24 -#define REG_WR_ADDR_intr_vect_rw_xmask0 24 -#define REG_RD_ADDR_intr_vect_rw_xmask 24 -#define REG_WR_ADDR_intr_vect_rw_xmask 24 - -/* Register rw_mask1, scope intr_vect, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_rw_mask1; -#define REG_RD_ADDR_intr_vect_rw_mask1 4 -#define REG_WR_ADDR_intr_vect_rw_mask1 4 - -/* Register r_vect1, scope intr_vect, type r */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_r_vect1; -#define REG_RD_ADDR_intr_vect_r_vect1 12 - -/* Register r_masked_vect1, scope intr_vect, type r */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_r_masked_vect1; -#define REG_RD_ADDR_intr_vect_r_masked_vect1 20 - -/* Register rw_xmask1, scope intr_vect, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_rw_xmask1; -#define REG_RD_ADDR_intr_vect_rw_xmask1 28 -#define REG_WR_ADDR_intr_vect_rw_xmask1 28 - -/* Register rw_xmask_ctrl, scope intr_vect, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_rw_xmask_ctrl; -#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 -#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int watchdog0 : 1; - unsigned int watchdog1 : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 64 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 68 - - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 72 -#define REG_WR_ADDR_intr_vect_rw_ipi 72 - -/* Constants */ -enum { - regk_intr_vect_no = 0x00000000, - regk_intr_vect_rw_mask0_default = 0x00000000, - regk_intr_vect_rw_mask1_default = 0x00000000, - regk_intr_vect_rw_xmask0_default = 0x00000000, - regk_intr_vect_rw_xmask1_default = 0x00000000, - regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, - regk_intr_vect_yes = 0x00000001 -}; -#endif /* __intr_vect_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index d75a74e90458..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in_extra 64 -#define iop_fifo_out_extra 128 -#define iop_trigger_grp0 192 -#define iop_trigger_grp1 256 -#define iop_trigger_grp2 320 -#define iop_trigger_grp3 384 -#define iop_trigger_grp4 448 -#define iop_trigger_grp5 512 -#define iop_trigger_grp6 576 -#define iop_trigger_grp7 640 -#define iop_crc_par 768 -#define iop_dmc_in 896 -#define iop_dmc_out 1024 -#define iop_fifo_in 1152 -#define iop_fifo_out 1280 -#define iop_scrc_in 1408 -#define iop_scrc_out 1536 -#define iop_timer_grp0 1664 -#define iop_timer_grp1 1792 -#define iop_sap_in 2048 -#define iop_sap_out 2304 -#define iop_spu 2560 -#define iop_sw_cfg 2816 -#define iop_sw_cpu 3072 -#define iop_sw_mpu 3328 -#define iop_sw_spu 3584 -#define iop_mpu 4096 diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index 7f90b5a0460d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 -#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 -#define reg_iop_sap_in_rw_bus_byte___delay___width 2 -#define reg_iop_sap_in_rw_bus_byte_offset 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 2 -#define reg_iop_sap_in_rw_gio___logic___lsb 9 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio0 0x00000000 -#define regk_iop_sap_in_gio12 0x00000003 -#define regk_iop_sap_in_gio16 0x00000004 -#define regk_iop_sap_in_gio20 0x00000005 -#define regk_iop_sap_in_gio24 0x00000006 -#define regk_iop_sap_in_gio28 0x00000007 -#define regk_iop_sap_in_gio4 0x00000001 -#define regk_iop_sap_in_gio8 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_one 0x00000001 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 -#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 -#define regk_iop_sap_in_rw_gio_default 0x00000000 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 -#define regk_iop_sap_in_tmr_clk200 0x00000001 -#define regk_iop_sap_in_two 0x00000002 -#define regk_iop_sap_in_two_clk200 0x00000000 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 399bd656406b..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 -#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 -#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 -#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 -#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 -#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 -#define reg_iop_sap_out_rw_bus_offset 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 -#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 -#define reg_iop_sap_out_rw_gio___out_delay___width 1 -#define reg_iop_sap_out_rw_gio___out_delay___bit 7 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 -#define reg_iop_sap_out_rw_gio___out_logic___width 2 -#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 -#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_delay___width 1 -#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 -#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 -#define reg_iop_sap_out_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_out_always 0x00000001 -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000004 -#define regk_iop_sap_out_clk200 0x00000000 -#define regk_iop_sap_out_ext 0x00000002 -#define regk_iop_sap_out_gated 0x00000003 -#define regk_iop_sap_out_gio0 0x00000000 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio16 0x00000002 -#define regk_iop_sap_out_gio17 0x00000002 -#define regk_iop_sap_out_gio24 0x00000003 -#define regk_iop_sap_out_gio25 0x00000003 -#define regk_iop_sap_out_gio8 0x00000001 -#define regk_iop_sap_out_gio9 0x00000001 -#define regk_iop_sap_out_gio_out10 0x00000005 -#define regk_iop_sap_out_gio_out18 0x00000006 -#define regk_iop_sap_out_gio_out2 0x00000004 -#define regk_iop_sap_out_gio_out26 0x00000007 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_one 0x00000001 -#define regk_iop_sap_out_rw_bus_default 0x00000000 -#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu_gio6 0x00000002 -#define regk_iop_sap_out_spu_gio7 0x00000003 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 -#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 -#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 -#define regk_iop_sap_out_tmr200 0x00000001 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3b3949b51a66..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,739 +0,0 @@ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 -#define reg_iop_sw_cfg_rw_spu_owner_offset 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus_mask_offset 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 -#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus 0x00000000 -#define regk_iop_sw_cfg_bus_rot16 0x00000002 -#define regk_iop_sw_cfg_bus_rot24 0x00000003 -#define regk_iop_sw_cfg_bus_rot8 0x00000001 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_gated_clk0 0x0000000e -#define regk_iop_sw_cfg_gated_clk1 0x0000000f -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_pdp_out 0x00000001 -#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 -#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out 0x00000004 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 -#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 -#define regk_iop_sw_cfg_spu_g0 0x00000007 -#define regk_iop_sw_cfg_spu_g1 0x00000007 -#define regk_iop_sw_cfg_spu_g2 0x00000007 -#define regk_iop_sw_cfg_spu_g3 0x00000007 -#define regk_iop_sw_cfg_spu_g4 0x00000007 -#define regk_iop_sw_cfg_spu_g5 0x00000007 -#define regk_iop_sw_cfg_spu_g6 0x00000007 -#define regk_iop_sw_cfg_spu_g7 0x00000007 -#define regk_iop_sw_cfg_spu_gio0 0x00000000 -#define regk_iop_sw_cfg_spu_gio1 0x00000001 -#define regk_iop_sw_cfg_spu_gio5 0x00000005 -#define regk_iop_sw_cfg_spu_gio6 0x00000006 -#define regk_iop_sw_cfg_spu_gio7 0x00000007 -#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu_gioout10 0x00000007 -#define regk_iop_sw_cfg_spu_gioout11 0x00000007 -#define regk_iop_sw_cfg_spu_gioout12 0x00000007 -#define regk_iop_sw_cfg_spu_gioout13 0x00000007 -#define regk_iop_sw_cfg_spu_gioout14 0x00000007 -#define regk_iop_sw_cfg_spu_gioout15 0x00000007 -#define regk_iop_sw_cfg_spu_gioout16 0x00000007 -#define regk_iop_sw_cfg_spu_gioout17 0x00000007 -#define regk_iop_sw_cfg_spu_gioout18 0x00000007 -#define regk_iop_sw_cfg_spu_gioout19 0x00000007 -#define regk_iop_sw_cfg_spu_gioout2 0x00000001 -#define regk_iop_sw_cfg_spu_gioout20 0x00000007 -#define regk_iop_sw_cfg_spu_gioout21 0x00000007 -#define regk_iop_sw_cfg_spu_gioout22 0x00000007 -#define regk_iop_sw_cfg_spu_gioout23 0x00000007 -#define regk_iop_sw_cfg_spu_gioout24 0x00000007 -#define regk_iop_sw_cfg_spu_gioout25 0x00000007 -#define regk_iop_sw_cfg_spu_gioout26 0x00000007 -#define regk_iop_sw_cfg_spu_gioout27 0x00000007 -#define regk_iop_sw_cfg_spu_gioout28 0x00000007 -#define regk_iop_sw_cfg_spu_gioout29 0x00000007 -#define regk_iop_sw_cfg_spu_gioout3 0x00000001 -#define regk_iop_sw_cfg_spu_gioout30 0x00000007 -#define regk_iop_sw_cfg_spu_gioout31 0x00000007 -#define regk_iop_sw_cfg_spu_gioout4 0x00000002 -#define regk_iop_sw_cfg_spu_gioout5 0x00000002 -#define regk_iop_sw_cfg_spu_gioout6 0x00000003 -#define regk_iop_sw_cfg_spu_gioout7 0x00000003 -#define regk_iop_sw_cfg_spu_gioout8 0x00000007 -#define regk_iop_sw_cfg_spu_gioout9 0x00000007 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000001 -#define regk_iop_sw_cfg_trig2_1 0x00000001 -#define regk_iop_sw_cfg_trig2_2 0x00000001 -#define regk_iop_sw_cfg_trig2_3 0x00000001 -#define regk_iop_sw_cfg_trig3_0 0x00000001 -#define regk_iop_sw_cfg_trig3_1 0x00000001 -#define regk_iop_sw_cfg_trig3_2 0x00000001 -#define regk_iop_sw_cfg_trig3_3 0x00000001 -#define regk_iop_sw_cfg_trig4_0 0x00000002 -#define regk_iop_sw_cfg_trig4_1 0x00000002 -#define regk_iop_sw_cfg_trig4_2 0x00000002 -#define regk_iop_sw_cfg_trig4_3 0x00000002 -#define regk_iop_sw_cfg_trig5_0 0x00000002 -#define regk_iop_sw_cfg_trig5_1 0x00000002 -#define regk_iop_sw_cfg_trig5_2 0x00000002 -#define regk_iop_sw_cfg_trig5_3 0x00000002 -#define regk_iop_sw_cfg_trig6_0 0x00000003 -#define regk_iop_sw_cfg_trig6_1 0x00000003 -#define regk_iop_sw_cfg_trig6_2 0x00000003 -#define regk_iop_sw_cfg_trig6_3 0x00000003 -#define regk_iop_sw_cfg_trig7_0 0x00000003 -#define regk_iop_sw_cfg_trig7_1 0x00000003 -#define regk_iop_sw_cfg_trig7_2 0x00000003 -#define regk_iop_sw_cfg_trig7_3 0x00000003 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index 3f4fe1b31815..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,950 +0,0 @@ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mpu_trace_offset 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 104 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ffcc83b22d21..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1086 +0,0 @@ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0_offset 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1_offset 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2_offset 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3_offset 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu 0x00000002 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 67a745338087..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,523 +0,0 @@ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_trace_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_spu_r_mc_stat_offset 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus_in_offset 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 -#define reg_iop_sw_spu_r_hw_intr_offset 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr_offset 132 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index 4ad671202af0..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v2_0 0x00000002 -#endif /* __iop_version_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h deleted file mode 100644 index af3196c60a46..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in_extra (regi_iop + 64) -#define regi_iop_fifo_out_extra (regi_iop + 128) -#define regi_iop_trigger_grp0 (regi_iop + 192) -#define regi_iop_trigger_grp1 (regi_iop + 256) -#define regi_iop_trigger_grp2 (regi_iop + 320) -#define regi_iop_trigger_grp3 (regi_iop + 384) -#define regi_iop_trigger_grp4 (regi_iop + 448) -#define regi_iop_trigger_grp5 (regi_iop + 512) -#define regi_iop_trigger_grp6 (regi_iop + 576) -#define regi_iop_trigger_grp7 (regi_iop + 640) -#define regi_iop_crc_par (regi_iop + 768) -#define regi_iop_dmc_in (regi_iop + 896) -#define regi_iop_dmc_out (regi_iop + 1024) -#define regi_iop_fifo_in (regi_iop + 1152) -#define regi_iop_fifo_out (regi_iop + 1280) -#define regi_iop_scrc_in (regi_iop + 1408) -#define regi_iop_scrc_out (regi_iop + 1536) -#define regi_iop_timer_grp0 (regi_iop + 1664) -#define regi_iop_timer_grp1 (regi_iop + 1792) -#define regi_iop_sap_in (regi_iop + 2048) -#define regi_iop_sap_out (regi_iop + 2304) -#define regi_iop_spu (regi_iop + 2560) -#define regi_iop_sw_cfg (regi_iop + 2816) -#define regi_iop_sw_cpu (regi_iop + 3072) -#define regi_iop_sw_mpu (regi_iop + 3328) -#define regi_iop_sw_spu (regi_iop + 3584) -#define regi_iop_mpu (regi_iop + 4096) diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 51dde016c03a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,141 +0,0 @@ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int dummy1 : 23; -} reg_iop_sap_in_rw_bus_byte; -#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int logic : 2; - unsigned int dummy1 : 21; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 16 -#define REG_WR_ADDR_iop_sap_in_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio0 = 0x00000000, - regk_iop_sap_in_gio12 = 0x00000003, - regk_iop_sap_in_gio16 = 0x00000004, - regk_iop_sap_in_gio20 = 0x00000005, - regk_iop_sap_in_gio24 = 0x00000006, - regk_iop_sap_in_gio28 = 0x00000007, - regk_iop_sap_in_gio4 = 0x00000001, - regk_iop_sap_in_gio8 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_one = 0x00000001, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus_byte_default = 0x00000000, - regk_iop_sap_in_rw_bus_byte_size = 0x00000004, - regk_iop_sap_in_rw_gio_default = 0x00000000, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, - regk_iop_sap_in_tmr_clk200 = 0x00000001, - regk_iop_sap_in_two = 0x00000002, - regk_iop_sap_in_two_clk200 = 0x00000000 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 5af88baa2ac1..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,231 +0,0 @@ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int dummy1 : 18; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_bus; -#define REG_RD_ADDR_iop_sap_out_rw_bus 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte0_logic : 2; - unsigned int byte0_logic_src : 2; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte1_logic : 2; - unsigned int byte1_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte2_logic : 2; - unsigned int byte2_logic_src : 2; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int byte3_logic : 2; - unsigned int byte3_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 2; - unsigned int out_gated_clk : 1; - unsigned int out_clk_inv : 1; - unsigned int out_delay : 1; - unsigned int out_logic : 2; - unsigned int out_logic_src : 2; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 2; - unsigned int oe_gated_clk : 1; - unsigned int oe_clk_inv : 1; - unsigned int oe_delay : 1; - unsigned int oe_logic : 2; - unsigned int oe_logic_src : 2; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 16 -#define REG_WR_ADDR_iop_sap_out_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_out_always = 0x00000001, - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000004, - regk_iop_sap_out_clk200 = 0x00000000, - regk_iop_sap_out_ext = 0x00000002, - regk_iop_sap_out_gated = 0x00000003, - regk_iop_sap_out_gio0 = 0x00000000, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio16 = 0x00000002, - regk_iop_sap_out_gio17 = 0x00000002, - regk_iop_sap_out_gio24 = 0x00000003, - regk_iop_sap_out_gio25 = 0x00000003, - regk_iop_sap_out_gio8 = 0x00000001, - regk_iop_sap_out_gio9 = 0x00000001, - regk_iop_sap_out_gio_out10 = 0x00000005, - regk_iop_sap_out_gio_out18 = 0x00000006, - regk_iop_sap_out_gio_out2 = 0x00000004, - regk_iop_sap_out_gio_out26 = 0x00000007, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_one = 0x00000001, - regk_iop_sap_out_rw_bus_default = 0x00000000, - regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu_gio6 = 0x00000002, - regk_iop_sap_out_spu_gio7 = 0x00000003, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, - regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, - regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, - regk_iop_sap_out_tmr200 = 0x00000001, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index 98ac95275a1c..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,725 +0,0 @@ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 1; - unsigned int dummy1 : 31; -} reg_iop_sw_cfg_rw_spu_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_byte0 : 2; - unsigned int bus_byte1 : 2; - unsigned int bus_byte2 : 2; - unsigned int bus_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_lo : 2; - unsigned int bus_hi : 2; - unsigned int bus_lo_oe : 2; - unsigned int bus_hi_oe : 2; - unsigned int dummy1 : 24; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 3; - unsigned int gio0_oe : 1; - unsigned int gio1 : 3; - unsigned int gio1_oe : 1; - unsigned int gio2 : 3; - unsigned int gio2_oe : 1; - unsigned int gio3 : 3; - unsigned int gio3_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 3; - unsigned int gio4_oe : 1; - unsigned int gio5 : 3; - unsigned int gio5_oe : 1; - unsigned int gio6 : 3; - unsigned int gio6_oe : 1; - unsigned int gio7 : 3; - unsigned int gio7_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 3; - unsigned int gio8_oe : 1; - unsigned int gio9 : 3; - unsigned int gio9_oe : 1; - unsigned int gio10 : 3; - unsigned int gio10_oe : 1; - unsigned int gio11 : 3; - unsigned int gio11_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 3; - unsigned int gio12_oe : 1; - unsigned int gio13 : 3; - unsigned int gio13_oe : 1; - unsigned int gio14 : 3; - unsigned int gio14_oe : 1; - unsigned int gio15 : 3; - unsigned int gio15_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 3; - unsigned int gio16_oe : 1; - unsigned int gio17 : 3; - unsigned int gio17_oe : 1; - unsigned int gio18 : 3; - unsigned int gio18_oe : 1; - unsigned int gio19 : 3; - unsigned int gio19_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 3; - unsigned int gio20_oe : 1; - unsigned int gio21 : 3; - unsigned int gio21_oe : 1; - unsigned int gio22 : 3; - unsigned int gio22_oe : 1; - unsigned int gio23 : 3; - unsigned int gio23_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 3; - unsigned int gio24_oe : 1; - unsigned int gio25 : 3; - unsigned int gio25_oe : 1; - unsigned int gio26 : 3; - unsigned int gio26_oe : 1; - unsigned int gio27 : 3; - unsigned int gio27_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 3; - unsigned int gio28_oe : 1; - unsigned int gio29 : 3; - unsigned int gio29_oe : 1; - unsigned int gio30 : 3; - unsigned int gio30_oe : 1; - unsigned int gio31 : 3; - unsigned int gio31_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 1; - unsigned int bus1_in : 1; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int out_strb : 4; - unsigned int in_src : 2; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int dummy1 : 17; -} reg_iop_sw_cfg_rw_pdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out_strb : 3; - unsigned int sdp_in_data : 3; - unsigned int sdp_in_last : 2; - unsigned int sdp_in_strb : 3; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus = 0x00000000, - regk_iop_sw_cfg_bus_rot16 = 0x00000002, - regk_iop_sw_cfg_bus_rot24 = 0x00000003, - regk_iop_sw_cfg_bus_rot8 = 0x00000001, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_gated_clk0 = 0x0000000e, - regk_iop_sw_cfg_gated_clk1 = 0x0000000f, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_pdp_out = 0x00000001, - regk_iop_sw_cfg_pdp_out_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out_lo = 0x00000000, - regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out = 0x00000004, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, - regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, - regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, - regk_iop_sw_cfg_spu_g0 = 0x00000007, - regk_iop_sw_cfg_spu_g1 = 0x00000007, - regk_iop_sw_cfg_spu_g2 = 0x00000007, - regk_iop_sw_cfg_spu_g3 = 0x00000007, - regk_iop_sw_cfg_spu_g4 = 0x00000007, - regk_iop_sw_cfg_spu_g5 = 0x00000007, - regk_iop_sw_cfg_spu_g6 = 0x00000007, - regk_iop_sw_cfg_spu_g7 = 0x00000007, - regk_iop_sw_cfg_spu_gio0 = 0x00000000, - regk_iop_sw_cfg_spu_gio1 = 0x00000001, - regk_iop_sw_cfg_spu_gio5 = 0x00000005, - regk_iop_sw_cfg_spu_gio6 = 0x00000006, - regk_iop_sw_cfg_spu_gio7 = 0x00000007, - regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu_gioout10 = 0x00000007, - regk_iop_sw_cfg_spu_gioout11 = 0x00000007, - regk_iop_sw_cfg_spu_gioout12 = 0x00000007, - regk_iop_sw_cfg_spu_gioout13 = 0x00000007, - regk_iop_sw_cfg_spu_gioout14 = 0x00000007, - regk_iop_sw_cfg_spu_gioout15 = 0x00000007, - regk_iop_sw_cfg_spu_gioout16 = 0x00000007, - regk_iop_sw_cfg_spu_gioout17 = 0x00000007, - regk_iop_sw_cfg_spu_gioout18 = 0x00000007, - regk_iop_sw_cfg_spu_gioout19 = 0x00000007, - regk_iop_sw_cfg_spu_gioout2 = 0x00000001, - regk_iop_sw_cfg_spu_gioout20 = 0x00000007, - regk_iop_sw_cfg_spu_gioout21 = 0x00000007, - regk_iop_sw_cfg_spu_gioout22 = 0x00000007, - regk_iop_sw_cfg_spu_gioout23 = 0x00000007, - regk_iop_sw_cfg_spu_gioout24 = 0x00000007, - regk_iop_sw_cfg_spu_gioout25 = 0x00000007, - regk_iop_sw_cfg_spu_gioout26 = 0x00000007, - regk_iop_sw_cfg_spu_gioout27 = 0x00000007, - regk_iop_sw_cfg_spu_gioout28 = 0x00000007, - regk_iop_sw_cfg_spu_gioout29 = 0x00000007, - regk_iop_sw_cfg_spu_gioout3 = 0x00000001, - regk_iop_sw_cfg_spu_gioout30 = 0x00000007, - regk_iop_sw_cfg_spu_gioout31 = 0x00000007, - regk_iop_sw_cfg_spu_gioout4 = 0x00000002, - regk_iop_sw_cfg_spu_gioout5 = 0x00000002, - regk_iop_sw_cfg_spu_gioout6 = 0x00000003, - regk_iop_sw_cfg_spu_gioout7 = 0x00000003, - regk_iop_sw_cfg_spu_gioout8 = 0x00000007, - regk_iop_sw_cfg_spu_gioout9 = 0x00000007, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000001, - regk_iop_sw_cfg_trig2_1 = 0x00000001, - regk_iop_sw_cfg_trig2_2 = 0x00000001, - regk_iop_sw_cfg_trig2_3 = 0x00000001, - regk_iop_sw_cfg_trig3_0 = 0x00000001, - regk_iop_sw_cfg_trig3_1 = 0x00000001, - regk_iop_sw_cfg_trig3_2 = 0x00000001, - regk_iop_sw_cfg_trig3_3 = 0x00000001, - regk_iop_sw_cfg_trig4_0 = 0x00000002, - regk_iop_sw_cfg_trig4_1 = 0x00000002, - regk_iop_sw_cfg_trig4_2 = 0x00000002, - regk_iop_sw_cfg_trig4_3 = 0x00000002, - regk_iop_sw_cfg_trig5_0 = 0x00000002, - regk_iop_sw_cfg_trig5_1 = 0x00000002, - regk_iop_sw_cfg_trig5_2 = 0x00000002, - regk_iop_sw_cfg_trig5_3 = 0x00000002, - regk_iop_sw_cfg_trig6_0 = 0x00000003, - regk_iop_sw_cfg_trig6_1 = 0x00000003, - regk_iop_sw_cfg_trig6_2 = 0x00000003, - regk_iop_sw_cfg_trig6_3 = 0x00000003, - regk_iop_sw_cfg_trig7_0 = 0x00000003, - regk_iop_sw_cfg_trig7_1 = 0x00000003, - regk_iop_sw_cfg_trig7_2 = 0x00000003, - regk_iop_sw_cfg_trig7_3 = 0x00000003 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index a16f556370eb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,522 +0,0 @@ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index a2e4e1a33e57..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,648 +0,0 @@ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr1 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr2 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr3 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr5 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr6 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr7 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr9 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr10 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr11 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr13 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr14 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr15 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu = 0x00000002, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index c8560b865a1a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,441 +0,0 @@ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out : 1; - unsigned int fifo_out_extra : 1; - unsigned int fifo_in : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_out : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h deleted file mode 100644 index 20de425e652b..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v2_0 = 0x00000002 -}; -#endif /* __iop_version_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h deleted file mode 100644 index 243ac3c882cb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __l2cache_defs_h -#define __l2cache_defs_h - -/* - * This file is autogenerated from - * file: l2cache.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope l2cache */ - -/* Register rw_cfg, scope l2cache, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_l2cache_rw_cfg; -#define REG_RD_ADDR_l2cache_rw_cfg 0 -#define REG_WR_ADDR_l2cache_rw_cfg 0 - -/* Register rw_ctrl, scope l2cache, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int cbase : 9; - unsigned int dummy2 : 4; - unsigned int csize : 10; - unsigned int dummy3 : 2; -} reg_l2cache_rw_ctrl; -#define REG_RD_ADDR_l2cache_rw_ctrl 4 -#define REG_WR_ADDR_l2cache_rw_ctrl 4 - -/* Register rw_idxop, scope l2cache, type rw */ -typedef struct { - unsigned int idx : 10; - unsigned int dummy1 : 14; - unsigned int way : 3; - unsigned int dummy2 : 2; - unsigned int cmd : 3; -} reg_l2cache_rw_idxop; -#define REG_RD_ADDR_l2cache_rw_idxop 8 -#define REG_WR_ADDR_l2cache_rw_idxop 8 - -/* Register rw_addrop_addr, scope l2cache, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_l2cache_rw_addrop_addr; -#define REG_RD_ADDR_l2cache_rw_addrop_addr 12 -#define REG_WR_ADDR_l2cache_rw_addrop_addr 12 - -/* Register rw_addrop_ctrl, scope l2cache, type rw */ -typedef struct { - unsigned int size : 16; - unsigned int dummy1 : 13; - unsigned int cmd : 3; -} reg_l2cache_rw_addrop_ctrl; -#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 -#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 - - -/* Constants */ -enum { - regk_l2cache_flush = 0x00000001, - regk_l2cache_no = 0x00000000, - regk_l2cache_rw_addrop_addr_default = 0x00000000, - regk_l2cache_rw_addrop_ctrl_default = 0x00000000, - regk_l2cache_rw_cfg_default = 0x00000000, - regk_l2cache_rw_ctrl_default = 0x00000000, - regk_l2cache_rw_idxop_default = 0x00000000, - regk_l2cache_yes = 0x00000001 -}; -#endif /* __l2cache_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h deleted file mode 100644 index c0e7628cbf7d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h +++ /dev/null @@ -1,482 +0,0 @@ -#ifndef __marb_bar_defs_h -#define __marb_bar_defs_h - -/* - * This file is autogenerated from - * file: marb_bar.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bar */ - -#define STRIDE_marb_bar_rw_ddr2_slots 4 -/* Register rw_ddr2_slots, scope marb_bar, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_ddr2_slots; -#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 -#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 - -/* Register rw_h264_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_h264_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 -#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 - -/* Register rw_h264_wr_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_h264_wr_burst; -#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 -#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 - -/* Register rw_ccd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_ccd_burst; -#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 -#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 - -/* Register rw_vin_wr_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vin_wr_burst; -#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 -#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 - -/* Register rw_vin_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vin_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 -#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 - -/* Register rw_sclr_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_sclr_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 -#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 - -/* Register rw_vout_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vout_burst; -#define REG_RD_ADDR_marb_bar_rw_vout_burst 280 -#define REG_WR_ADDR_marb_bar_rw_vout_burst 280 - -/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_sclr_fifo_burst; -#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 -#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 - -/* Register rw_l2cache_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_l2cache_burst; -#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 -#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 - -/* Register rw_intr_mask, scope marb_bar, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_intr_mask; -#define REG_RD_ADDR_marb_bar_rw_intr_mask 292 -#define REG_WR_ADDR_marb_bar_rw_intr_mask 292 - -/* Register rw_ack_intr, scope marb_bar, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_ack_intr; -#define REG_RD_ADDR_marb_bar_rw_ack_intr 296 -#define REG_WR_ADDR_marb_bar_rw_ack_intr 296 - -/* Register r_intr, scope marb_bar, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_r_intr; -#define REG_RD_ADDR_marb_bar_r_intr 300 - -/* Register r_masked_intr, scope marb_bar, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_r_masked_intr; -#define REG_RD_ADDR_marb_bar_r_masked_intr 304 - -/* Register rw_stop_mask, scope marb_bar, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_rw_stop_mask; -#define REG_RD_ADDR_marb_bar_rw_stop_mask 308 -#define REG_WR_ADDR_marb_bar_rw_stop_mask 308 - -/* Register r_stopped, scope marb_bar, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_r_stopped; -#define REG_RD_ADDR_marb_bar_r_stopped 312 - -/* Register rw_no_snoop, scope marb_bar, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_rw_no_snoop; -#define REG_RD_ADDR_marb_bar_rw_no_snoop 576 -#define REG_WR_ADDR_marb_bar_rw_no_snoop 576 - - -/* Constants */ -enum { - regk_marb_bar_ccd = 0x00000002, - regk_marb_bar_h264_rd = 0x00000000, - regk_marb_bar_h264_wr = 0x00000001, - regk_marb_bar_l2cache = 0x00000008, - regk_marb_bar_no = 0x00000000, - regk_marb_bar_r_stopped_default = 0x00000000, - regk_marb_bar_rw_ccd_burst_default = 0x00000000, - regk_marb_bar_rw_ddr2_slots_default = 0x00000000, - regk_marb_bar_rw_ddr2_slots_size = 0x00000040, - regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, - regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, - regk_marb_bar_rw_intr_mask_default = 0x00000000, - regk_marb_bar_rw_l2cache_burst_default = 0x00000000, - regk_marb_bar_rw_no_snoop_default = 0x00000000, - regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, - regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, - regk_marb_bar_rw_stop_mask_default = 0x00000000, - regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, - regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, - regk_marb_bar_rw_vout_burst_default = 0x00000000, - regk_marb_bar_sclr_fifo = 0x00000007, - regk_marb_bar_sclr_rd = 0x00000005, - regk_marb_bar_vin_rd = 0x00000004, - regk_marb_bar_vin_wr = 0x00000003, - regk_marb_bar_vout = 0x00000006, - regk_marb_bar_yes = 0x00000001 -}; -#endif /* __marb_bar_defs_h */ -#ifndef __marb_bar_bp_defs_h -#define __marb_bar_bp_defs_h - -/* - * This file is autogenerated from - * file: marb_bar.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bar_bp */ - -/* Register rw_first_addr, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bar_bp_rw_op; -#define REG_RD_ADDR_marb_bar_bp_rw_op 8 -#define REG_WR_ADDR_marb_bar_bp_rw_op 8 - -/* Register rw_clients, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_rw_clients; -#define REG_RD_ADDR_marb_bar_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bar_bp_rw_clients 12 - -/* Register rw_options, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bar_bp_rw_options; -#define REG_RD_ADDR_marb_bar_bp_rw_options 16 -#define REG_WR_ADDR_marb_bar_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bar_bp, type r */ -typedef unsigned int reg_marb_bar_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bar_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bar_bp_r_brk_op; -#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bar_bp, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bar_bp, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bar_bp, type r */ -typedef unsigned int reg_marb_bar_bp_r_brk_size; -#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_ack; -#define REG_RD_ADDR_marb_bar_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bar_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bar_bp_no = 0x00000000, - regk_marb_bar_bp_rw_op_default = 0x00000000, - regk_marb_bar_bp_rw_options_default = 0x00000000, - regk_marb_bar_bp_yes = 0x00000001 -}; -#endif /* __marb_bar_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h deleted file mode 100644 index 2baa833f109a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h +++ /dev/null @@ -1,626 +0,0 @@ -#ifndef __marb_foo_defs_h -#define __marb_foo_defs_h - -/* - * This file is autogenerated from - * file: marb_foo.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_foo */ - -#define STRIDE_marb_foo_rw_intm_slots 4 -/* Register rw_intm_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_intm_slots; -#define REG_RD_ADDR_marb_foo_rw_intm_slots 0 -#define REG_WR_ADDR_marb_foo_rw_intm_slots 0 - -#define STRIDE_marb_foo_rw_l2_slots 4 -/* Register rw_l2_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_l2_slots; -#define REG_RD_ADDR_marb_foo_rw_l2_slots 256 -#define REG_WR_ADDR_marb_foo_rw_l2_slots 256 - -#define STRIDE_marb_foo_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_regs_slots; -#define REG_RD_ADDR_marb_foo_rw_regs_slots 512 -#define REG_WR_ADDR_marb_foo_rw_regs_slots 512 - -/* Register rw_sclr_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_sclr_burst; -#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 -#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 - -/* Register rw_dma0_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma0_burst; -#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 -#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 - -/* Register rw_dma1_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma1_burst; -#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 -#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 - -/* Register rw_dma2_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma2_burst; -#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 -#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 - -/* Register rw_dma3_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma3_burst; -#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 -#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 - -/* Register rw_dma4_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma4_burst; -#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 -#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 - -/* Register rw_dma5_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma5_burst; -#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 -#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 - -/* Register rw_dma6_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma6_burst; -#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 -#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 - -/* Register rw_dma7_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma7_burst; -#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 -#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 - -/* Register rw_dma9_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma9_burst; -#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 -#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 - -/* Register rw_dma11_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma11_burst; -#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 -#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 - -/* Register rw_cpui_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_cpui_burst; -#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 -#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 - -/* Register rw_cpud_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_cpud_burst; -#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 -#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 - -/* Register rw_iop_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_iop_burst; -#define REG_RD_ADDR_marb_foo_rw_iop_burst 580 -#define REG_WR_ADDR_marb_foo_rw_iop_burst 580 - -/* Register rw_ccdstat_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_ccdstat_burst; -#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 -#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 - -/* Register rw_intr_mask, scope marb_foo, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_intr_mask; -#define REG_RD_ADDR_marb_foo_rw_intr_mask 588 -#define REG_WR_ADDR_marb_foo_rw_intr_mask 588 - -/* Register rw_ack_intr, scope marb_foo, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_ack_intr; -#define REG_RD_ADDR_marb_foo_rw_ack_intr 592 -#define REG_WR_ADDR_marb_foo_rw_ack_intr 592 - -/* Register r_intr, scope marb_foo, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_r_intr; -#define REG_RD_ADDR_marb_foo_r_intr 596 - -/* Register r_masked_intr, scope marb_foo, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_r_masked_intr; -#define REG_RD_ADDR_marb_foo_r_masked_intr 600 - -/* Register rw_stop_mask, scope marb_foo, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_rw_stop_mask; -#define REG_RD_ADDR_marb_foo_rw_stop_mask 604 -#define REG_WR_ADDR_marb_foo_rw_stop_mask 604 - -/* Register r_stopped, scope marb_foo, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_r_stopped; -#define REG_RD_ADDR_marb_foo_r_stopped 608 - -/* Register rw_no_snoop, scope marb_foo, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_rw_no_snoop; -#define REG_RD_ADDR_marb_foo_rw_no_snoop 896 -#define REG_WR_ADDR_marb_foo_rw_no_snoop 896 - -/* Register rw_no_snoop_rq, scope marb_foo, type rw */ -typedef struct { - unsigned int dummy1 : 11; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 19; -} reg_marb_foo_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 -#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 - - -/* Constants */ -enum { - regk_marb_foo_ccdstat = 0x0000000e, - regk_marb_foo_cpud = 0x0000000c, - regk_marb_foo_cpui = 0x0000000b, - regk_marb_foo_dma0 = 0x00000001, - regk_marb_foo_dma1 = 0x00000002, - regk_marb_foo_dma11 = 0x0000000a, - regk_marb_foo_dma2 = 0x00000003, - regk_marb_foo_dma3 = 0x00000004, - regk_marb_foo_dma4 = 0x00000005, - regk_marb_foo_dma5 = 0x00000006, - regk_marb_foo_dma6 = 0x00000007, - regk_marb_foo_dma7 = 0x00000008, - regk_marb_foo_dma9 = 0x00000009, - regk_marb_foo_iop = 0x0000000d, - regk_marb_foo_no = 0x00000000, - regk_marb_foo_r_stopped_default = 0x00000000, - regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, - regk_marb_foo_rw_cpud_burst_default = 0x00000000, - regk_marb_foo_rw_cpui_burst_default = 0x00000000, - regk_marb_foo_rw_dma0_burst_default = 0x00000000, - regk_marb_foo_rw_dma11_burst_default = 0x00000000, - regk_marb_foo_rw_dma1_burst_default = 0x00000000, - regk_marb_foo_rw_dma2_burst_default = 0x00000000, - regk_marb_foo_rw_dma3_burst_default = 0x00000000, - regk_marb_foo_rw_dma4_burst_default = 0x00000000, - regk_marb_foo_rw_dma5_burst_default = 0x00000000, - regk_marb_foo_rw_dma6_burst_default = 0x00000000, - regk_marb_foo_rw_dma7_burst_default = 0x00000000, - regk_marb_foo_rw_dma9_burst_default = 0x00000000, - regk_marb_foo_rw_intm_slots_default = 0x00000000, - regk_marb_foo_rw_intm_slots_size = 0x00000040, - regk_marb_foo_rw_intr_mask_default = 0x00000000, - regk_marb_foo_rw_iop_burst_default = 0x00000000, - regk_marb_foo_rw_l2_slots_default = 0x00000000, - regk_marb_foo_rw_l2_slots_size = 0x00000040, - regk_marb_foo_rw_no_snoop_default = 0x00000000, - regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, - regk_marb_foo_rw_regs_slots_default = 0x00000000, - regk_marb_foo_rw_regs_slots_size = 0x00000004, - regk_marb_foo_rw_sclr_burst_default = 0x00000000, - regk_marb_foo_rw_stop_mask_default = 0x00000000, - regk_marb_foo_sclr = 0x00000000, - regk_marb_foo_yes = 0x00000001 -}; -#endif /* __marb_foo_defs_h */ -#ifndef __marb_foo_bp_defs_h -#define __marb_foo_bp_defs_h - -/* - * This file is autogenerated from - * file: marb_foo.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_foo_bp */ - -/* Register rw_first_addr, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_first_addr; -#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_last_addr; -#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_foo_bp_rw_op; -#define REG_RD_ADDR_marb_foo_bp_rw_op 8 -#define REG_WR_ADDR_marb_foo_bp_rw_op 8 - -/* Register rw_clients, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_rw_clients; -#define REG_RD_ADDR_marb_foo_bp_rw_clients 12 -#define REG_WR_ADDR_marb_foo_bp_rw_clients 12 - -/* Register rw_options, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_foo_bp_rw_options; -#define REG_RD_ADDR_marb_foo_bp_rw_options 16 -#define REG_WR_ADDR_marb_foo_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_foo_bp, type r */ -typedef unsigned int reg_marb_foo_bp_r_brk_addr; -#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_foo_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_foo_bp_r_brk_op; -#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_foo_bp, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_r_brk_clients; -#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_foo_bp, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_foo_bp, type r */ -typedef unsigned int reg_marb_foo_bp_r_brk_size; -#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_ack; -#define REG_RD_ADDR_marb_foo_bp_rw_ack 40 -#define REG_WR_ADDR_marb_foo_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_foo_bp_no = 0x00000000, - regk_marb_foo_bp_rw_op_default = 0x00000000, - regk_marb_foo_bp_rw_options_default = 0x00000000, - regk_marb_foo_bp_yes = 0x00000001 -}; -#endif /* __marb_foo_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h deleted file mode 100644 index 4b96cd2cba8a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h +++ /dev/null @@ -1,312 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: pinmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int eth_mdio : 1; - unsigned int geth : 1; - unsigned int tg : 1; - unsigned int tg_clk : 1; - unsigned int vout : 1; - unsigned int vout_sync : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int pwm0 : 1; - unsigned int pwm1 : 1; - unsigned int pwm2 : 1; - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int pio : 1; - unsigned int i2c0 : 1; - unsigned int i2c1 : 1; - unsigned int i2c1_sda1 : 1; - unsigned int i2c1_sda2 : 1; - unsigned int i2c1_sda3 : 1; - unsigned int i2c1_sen : 1; - unsigned int dummy1 : 8; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 0 -#define REG_WR_ADDR_pinmux_rw_hwprot 0 - -/* Register rw_gio_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int pa8 : 1; - unsigned int pa9 : 1; - unsigned int pa10 : 1; - unsigned int pa11 : 1; - unsigned int pa12 : 1; - unsigned int pa13 : 1; - unsigned int pa14 : 1; - unsigned int pa15 : 1; - unsigned int pa16 : 1; - unsigned int pa17 : 1; - unsigned int pa18 : 1; - unsigned int pa19 : 1; - unsigned int pa20 : 1; - unsigned int pa21 : 1; - unsigned int pa22 : 1; - unsigned int pa23 : 1; - unsigned int pa24 : 1; - unsigned int pa25 : 1; - unsigned int pa26 : 1; - unsigned int pa27 : 1; - unsigned int pa28 : 1; - unsigned int pa29 : 1; - unsigned int pa30 : 1; - unsigned int pa31 : 1; -} reg_pinmux_rw_gio_pa; -#define REG_RD_ADDR_pinmux_rw_gio_pa 4 -#define REG_WR_ADDR_pinmux_rw_gio_pa 4 - -/* Register rw_gio_pb, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int pb18 : 1; - unsigned int pb19 : 1; - unsigned int pb20 : 1; - unsigned int pb21 : 1; - unsigned int pb22 : 1; - unsigned int pb23 : 1; - unsigned int pb24 : 1; - unsigned int pb25 : 1; - unsigned int pb26 : 1; - unsigned int pb27 : 1; - unsigned int pb28 : 1; - unsigned int pb29 : 1; - unsigned int pb30 : 1; - unsigned int pb31 : 1; -} reg_pinmux_rw_gio_pb; -#define REG_RD_ADDR_pinmux_rw_gio_pb 8 -#define REG_WR_ADDR_pinmux_rw_gio_pb 8 - -/* Register rw_gio_pc, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_gio_pc; -#define REG_RD_ADDR_pinmux_rw_gio_pc 12 -#define REG_WR_ADDR_pinmux_rw_gio_pc 12 - -/* Register rw_iop_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int pa8 : 1; - unsigned int pa9 : 1; - unsigned int pa10 : 1; - unsigned int pa11 : 1; - unsigned int pa12 : 1; - unsigned int pa13 : 1; - unsigned int pa14 : 1; - unsigned int pa15 : 1; - unsigned int pa16 : 1; - unsigned int pa17 : 1; - unsigned int pa18 : 1; - unsigned int pa19 : 1; - unsigned int pa20 : 1; - unsigned int pa21 : 1; - unsigned int pa22 : 1; - unsigned int pa23 : 1; - unsigned int pa24 : 1; - unsigned int pa25 : 1; - unsigned int pa26 : 1; - unsigned int pa27 : 1; - unsigned int pa28 : 1; - unsigned int pa29 : 1; - unsigned int pa30 : 1; - unsigned int pa31 : 1; -} reg_pinmux_rw_iop_pa; -#define REG_RD_ADDR_pinmux_rw_iop_pa 16 -#define REG_WR_ADDR_pinmux_rw_iop_pa 16 - -/* Register rw_iop_pb, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int dummy1 : 24; -} reg_pinmux_rw_iop_pb; -#define REG_RD_ADDR_pinmux_rw_iop_pb 20 -#define REG_WR_ADDR_pinmux_rw_iop_pb 20 - -/* Register rw_iop_pio, scope pinmux, type rw */ -typedef struct { - unsigned int d0 : 1; - unsigned int d1 : 1; - unsigned int d2 : 1; - unsigned int d3 : 1; - unsigned int d4 : 1; - unsigned int d5 : 1; - unsigned int d6 : 1; - unsigned int d7 : 1; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_iop_pio; -#define REG_RD_ADDR_pinmux_rw_iop_pio 24 -#define REG_WR_ADDR_pinmux_rw_iop_pio 24 - -/* Register rw_iop_usb, scope pinmux, type rw */ -typedef struct { - unsigned int usb0 : 1; - unsigned int dummy1 : 31; -} reg_pinmux_rw_iop_usb; -#define REG_RD_ADDR_pinmux_rw_iop_usb 28 -#define REG_WR_ADDR_pinmux_rw_iop_usb 28 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_gio_pa_default = 0x00000000, - regk_pinmux_rw_gio_pb_default = 0x00000000, - regk_pinmux_rw_gio_pc_default = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_iop_pa_default = 0x00000000, - regk_pinmux_rw_iop_pb_default = 0x00000000, - regk_pinmux_rw_iop_pio_default = 0x00000000, - regk_pinmux_rw_iop_usb_default = 0x00000001, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h deleted file mode 100644 index 2d8e4b4cc602..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h +++ /dev/null @@ -1,371 +0,0 @@ -#ifndef __pio_defs_h -#define __pio_defs_h - -/* - * This file is autogenerated from - * file: pio.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pio */ - -/* Register rw_data, scope pio, type rw */ -typedef unsigned int reg_pio_rw_data; -#define REG_RD_ADDR_pio_rw_data 64 -#define REG_WR_ADDR_pio_rw_data 64 - -/* Register rw_io_access0, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access0; -#define REG_RD_ADDR_pio_rw_io_access0 0 -#define REG_WR_ADDR_pio_rw_io_access0 0 - -/* Register rw_io_access1, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access1; -#define REG_RD_ADDR_pio_rw_io_access1 4 -#define REG_WR_ADDR_pio_rw_io_access1 4 - -/* Register rw_io_access2, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access2; -#define REG_RD_ADDR_pio_rw_io_access2 8 -#define REG_WR_ADDR_pio_rw_io_access2 8 - -/* Register rw_io_access3, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access3; -#define REG_RD_ADDR_pio_rw_io_access3 12 -#define REG_WR_ADDR_pio_rw_io_access3 12 - -/* Register rw_io_access4, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access4; -#define REG_RD_ADDR_pio_rw_io_access4 16 -#define REG_WR_ADDR_pio_rw_io_access4 16 - -/* Register rw_io_access5, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access5; -#define REG_RD_ADDR_pio_rw_io_access5 20 -#define REG_WR_ADDR_pio_rw_io_access5 20 - -/* Register rw_io_access6, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access6; -#define REG_RD_ADDR_pio_rw_io_access6 24 -#define REG_WR_ADDR_pio_rw_io_access6 24 - -/* Register rw_io_access7, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access7; -#define REG_RD_ADDR_pio_rw_io_access7 28 -#define REG_WR_ADDR_pio_rw_io_access7 28 - -/* Register rw_io_access8, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access8; -#define REG_RD_ADDR_pio_rw_io_access8 32 -#define REG_WR_ADDR_pio_rw_io_access8 32 - -/* Register rw_io_access9, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access9; -#define REG_RD_ADDR_pio_rw_io_access9 36 -#define REG_WR_ADDR_pio_rw_io_access9 36 - -/* Register rw_io_access10, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access10; -#define REG_RD_ADDR_pio_rw_io_access10 40 -#define REG_WR_ADDR_pio_rw_io_access10 40 - -/* Register rw_io_access11, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access11; -#define REG_RD_ADDR_pio_rw_io_access11 44 -#define REG_WR_ADDR_pio_rw_io_access11 44 - -/* Register rw_io_access12, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access12; -#define REG_RD_ADDR_pio_rw_io_access12 48 -#define REG_WR_ADDR_pio_rw_io_access12 48 - -/* Register rw_io_access13, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access13; -#define REG_RD_ADDR_pio_rw_io_access13 52 -#define REG_WR_ADDR_pio_rw_io_access13 52 - -/* Register rw_io_access14, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access14; -#define REG_RD_ADDR_pio_rw_io_access14 56 -#define REG_WR_ADDR_pio_rw_io_access14 56 - -/* Register rw_io_access15, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access15; -#define REG_RD_ADDR_pio_rw_io_access15 60 -#define REG_WR_ADDR_pio_rw_io_access15 60 - -/* Register rw_ce0_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce0_cfg; -#define REG_RD_ADDR_pio_rw_ce0_cfg 68 -#define REG_WR_ADDR_pio_rw_ce0_cfg 68 - -/* Register rw_ce1_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce1_cfg; -#define REG_RD_ADDR_pio_rw_ce1_cfg 72 -#define REG_WR_ADDR_pio_rw_ce1_cfg 72 - -/* Register rw_ce2_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce2_cfg; -#define REG_RD_ADDR_pio_rw_ce2_cfg 76 -#define REG_WR_ADDR_pio_rw_ce2_cfg 76 - -/* Register rw_dout, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_dout; -#define REG_RD_ADDR_pio_rw_dout 80 -#define REG_WR_ADDR_pio_rw_dout 80 - -/* Register rw_oe, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_oe; -#define REG_RD_ADDR_pio_rw_oe 84 -#define REG_WR_ADDR_pio_rw_oe 84 - -/* Register rw_man_ctrl, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_man_ctrl; -#define REG_RD_ADDR_pio_rw_man_ctrl 88 -#define REG_WR_ADDR_pio_rw_man_ctrl 88 - -/* Register r_din, scope pio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_r_din; -#define REG_RD_ADDR_pio_r_din 92 - -/* Register r_stat, scope pio, type r */ -typedef struct { - unsigned int busy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_stat; -#define REG_RD_ADDR_pio_r_stat 96 - -/* Register rw_intr_mask, scope pio, type rw */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_rw_intr_mask; -#define REG_RD_ADDR_pio_rw_intr_mask 100 -#define REG_WR_ADDR_pio_rw_intr_mask 100 - -/* Register rw_ack_intr, scope pio, type rw */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_rw_ack_intr; -#define REG_RD_ADDR_pio_rw_ack_intr 104 -#define REG_WR_ADDR_pio_rw_ack_intr 104 - -/* Register r_intr, scope pio, type r */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_intr; -#define REG_RD_ADDR_pio_r_intr 108 - -/* Register r_masked_intr, scope pio, type r */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_masked_intr; -#define REG_RD_ADDR_pio_r_masked_intr 112 - - -/* Constants */ -enum { - regk_pio_a2 = 0x00000003, - regk_pio_no = 0x00000000, - regk_pio_normal = 0x00000000, - regk_pio_rd = 0x00000001, - regk_pio_rw_ce0_cfg_default = 0x00000000, - regk_pio_rw_ce1_cfg_default = 0x00000000, - regk_pio_rw_ce2_cfg_default = 0x00000000, - regk_pio_rw_intr_mask_default = 0x00000000, - regk_pio_rw_man_ctrl_default = 0x00000000, - regk_pio_rw_oe_default = 0x00000000, - regk_pio_wr = 0x00000002, - regk_pio_wr_ce2 = 0x00000003, - regk_pio_yes = 0x00000001, - regk_pio_yes_all = 0x000000ff -}; -#endif /* __pio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h deleted file mode 100644 index 36e59d6e96b6..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: reg.rmap - * - * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ccd = 0xb0000000, - regi_ccd_top = 0xb0000000, - regi_ccd_dp = 0xb0000400, - regi_ccd_stat = 0xb0000800, - regi_ccd_tg = 0xb0001000, - regi_cfg = 0xb0002000, - regi_clkgen = 0xb0004000, - regi_ddr2_ctrl = 0xb0006000, - regi_dma0 = 0xb0008000, - regi_dma1 = 0xb000a000, - regi_dma11 = 0xb000c000, - regi_dma2 = 0xb000e000, - regi_dma3 = 0xb0010000, - regi_dma4 = 0xb0012000, - regi_dma5 = 0xb0014000, - regi_dma6 = 0xb0016000, - regi_dma7 = 0xb0018000, - regi_dma9 = 0xb001a000, - regi_eth = 0xb001c000, - regi_gio = 0xb0020000, - regi_h264 = 0xb0022000, - regi_hist = 0xb0026000, - regi_iop = 0xb0028000, - regi_iop_version = 0xb0028000, - regi_iop_fifo_in_extra = 0xb0028040, - regi_iop_fifo_out_extra = 0xb0028080, - regi_iop_trigger_grp0 = 0xb00280c0, - regi_iop_trigger_grp1 = 0xb0028100, - regi_iop_trigger_grp2 = 0xb0028140, - regi_iop_trigger_grp3 = 0xb0028180, - regi_iop_trigger_grp4 = 0xb00281c0, - regi_iop_trigger_grp5 = 0xb0028200, - regi_iop_trigger_grp6 = 0xb0028240, - regi_iop_trigger_grp7 = 0xb0028280, - regi_iop_crc_par = 0xb0028300, - regi_iop_dmc_in = 0xb0028380, - regi_iop_dmc_out = 0xb0028400, - regi_iop_fifo_in = 0xb0028480, - regi_iop_fifo_out = 0xb0028500, - regi_iop_scrc_in = 0xb0028580, - regi_iop_scrc_out = 0xb0028600, - regi_iop_timer_grp0 = 0xb0028680, - regi_iop_timer_grp1 = 0xb0028700, - regi_iop_sap_in = 0xb0028800, - regi_iop_sap_out = 0xb0028900, - regi_iop_spu = 0xb0028a00, - regi_iop_sw_cfg = 0xb0028b00, - regi_iop_sw_cpu = 0xb0028c00, - regi_iop_sw_mpu = 0xb0028d00, - regi_iop_sw_spu = 0xb0028e00, - regi_iop_mpu = 0xb0029000, - regi_irq = 0xb002a000, - regi_irq2 = 0xb006a000, - regi_jpeg = 0xb002c000, - regi_l2cache = 0xb0030000, - regi_marb_bar = 0xb0032000, - regi_marb_bar_bp0 = 0xb0032140, - regi_marb_bar_bp1 = 0xb0032180, - regi_marb_bar_bp2 = 0xb00321c0, - regi_marb_bar_bp3 = 0xb0032200, - regi_marb_foo = 0xb0034000, - regi_marb_foo_bp0 = 0xb0034280, - regi_marb_foo_bp1 = 0xb00342c0, - regi_marb_foo_bp2 = 0xb0034300, - regi_marb_foo_bp3 = 0xb0034340, - regi_pinmux = 0xb0038000, - regi_pio = 0xb0036000, - regi_sclr = 0xb003a000, - regi_sclr_fifo = 0xb003c000, - regi_ser0 = 0xb003e000, - regi_ser1 = 0xb0040000, - regi_ser2 = 0xb0042000, - regi_ser3 = 0xb0044000, - regi_ser4 = 0xb0046000, - regi_sser = 0xb0048000, - regi_strcop = 0xb004a000, - regi_strdma0 = 0xb004e000, - regi_strdma1 = 0xb0050000, - regi_strdma2 = 0xb0052000, - regi_strdma3 = 0xb0054000, - regi_strdma5 = 0xb0056000, - regi_strmux = 0xb004c000, - regi_timer0 = 0xb0058000, - regi_timer1 = 0xb005a000, - regi_timer2 = 0xb006e000, - regi_trace = 0xb005c000, - regi_vin = 0xb005e000, - regi_vout = 0xb0060000 -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h deleted file mode 100644 index 14f718a4ecc3..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: strmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 2; - unsigned int dma1 : 2; - unsigned int dma2 : 2; - unsigned int dma3 : 2; - unsigned int dma4 : 2; - unsigned int dma5 : 2; - unsigned int dma6 : 2; - unsigned int dma7 : 2; - unsigned int dummy1 : 2; - unsigned int dma9 : 2; - unsigned int dummy2 : 2; - unsigned int dma11 : 2; - unsigned int dummy3 : 8; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_eth = 0x00000001, - regk_strmux_h264 = 0x00000001, - regk_strmux_iop = 0x00000001, - regk_strmux_jpeg = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000002, - regk_strmux_ser3 = 0x00000002, - regk_strmux_ser4 = 0x00000002, - regk_strmux_sser = 0x00000001, - regk_strmux_strcop = 0x00000001 -}; -#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h deleted file mode 100644 index 2c33e097d60a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h +++ /dev/null @@ -1,265 +0,0 @@ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: timer.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_f90 = 0x00000003, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_vclk = 0x00000002, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h deleted file mode 100644 index 7e15c9eb4e49..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/memmap.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00018000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h deleted file mode 100644 index db42a7254584..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/pinmux.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_A 0 -#define PORT_B 1 -#define PORT_C 2 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_eth, - pinmux_geth, - pinmux_tg_ccd, - pinmux_tg_cmos, - pinmux_vout, - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_ser4, - pinmux_sser, - pinmux_pio, - pinmux_pwm0, - pinmux_pwm1, - pinmux_pwm2, - pinmux_i2c0, - pinmux_i2c1, - pinmux_i2c1_3wire, - pinmux_i2c1_sda1, - pinmux_i2c1_sda2, - pinmux_i2c1_sda3, -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc deleted file mode 100644 index 2f23e5e16f4a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/startup.inc +++ /dev/null @@ -1,60 +0,0 @@ -#include -#include -#include -#include -#include - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d 0xFFFFFFFF, $r0 - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 - move.d $r0, [$r1] - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 - move.d $r0, [$r1] - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 - move.d $r0, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ - REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 - move.d $r1, [$r0] - .endm diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h deleted file mode 100644 index a2e0ec8faa7d..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/arbiter.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index 0a409c92837e..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,319 +0,0 @@ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h deleted file mode 100644 index a9908dfc2937..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index be4c63936d90..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 30cf5a936b64..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,632 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 87517aebd2cb..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index e1197194d5c1..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,229 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h deleted file mode 100644 index 44362a62b47c..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h +++ /dev/null @@ -1,284 +0,0 @@ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h deleted file mode 100644 index 3cb51a09dba7..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,473 +0,0 @@ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h deleted file mode 100644 index 0c434585a3f9..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h deleted file mode 100644 index abc5f20705f7..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h deleted file mode 100644 index 26aa3efcf91b..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h +++ /dev/null @@ -1,295 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h deleted file mode 100644 index bacc2a895c21..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define GIO_INTR_VECT GEN_IO_INTR_VECT -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define TIMER0_INTR_VECT TIMER_INTR_VECT -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f -#define NBR_INTR_VECT 0x50 -#endif diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h deleted file mode 100644 index aa65128ae1aa..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - -#define STRIDE_intr_vect_rw_mask 0 -/* Register rw_mask, scope intr_vect, type rw */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer0 : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_rw_mask; -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 - -#define STRIDE_intr_vect_r_vect 0 -/* Register r_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_vect; -#define REG_RD_ADDR_intr_vect_r_vect 4 - -#define STRIDE_intr_vect_r_masked_vect 0 -/* Register r_masked_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_masked_vect; -#define REG_RD_ADDR_intr_vect_r_masked_vect 8 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int ext : 1; - unsigned int watchdog : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 12 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 16 - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 20 -#define REG_WR_ADDR_intr_vect_rw_ipi 20 - -/* Constants */ -enum { - regk_intr_vect_off = 0x00000000, - regk_intr_vect_on = 0x00000001, - regk_intr_vect_rw_mask_default = 0x00000000 -}; -#endif /* __intr_vect_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h deleted file mode 100644 index dcaaec4620ba..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,205 +0,0 @@ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h deleted file mode 100644 index 254da0854986..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h deleted file mode 100644 index 751eab5f191c..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h +++ /dev/null @@ -1,357 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h deleted file mode 100644 index 4146973a58b3..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ata = 0xb0032000, - regi_bif_core = 0xb0014000, - regi_bif_dma = 0xb0016000, - regi_bif_slave = 0xb0018000, - regi_config = 0xb003c000, - regi_dma0 = 0xb0000000, - regi_dma1 = 0xb0002000, - regi_dma2 = 0xb0004000, - regi_dma3 = 0xb0006000, - regi_dma4 = 0xb0008000, - regi_dma5 = 0xb000a000, - regi_dma6 = 0xb000c000, - regi_dma7 = 0xb000e000, - regi_dma8 = 0xb0010000, - regi_dma9 = 0xb0012000, - regi_eth0 = 0xb0034000, - regi_eth1 = 0xb0036000, - regi_gio = 0xb001a000, - regi_iop = 0xb0020000, - regi_iop_version = 0xb0020000, - regi_iop_fifo_in0_extra = 0xb0020040, - regi_iop_fifo_in1_extra = 0xb0020080, - regi_iop_fifo_out0_extra = 0xb00200c0, - regi_iop_fifo_out1_extra = 0xb0020100, - regi_iop_trigger_grp0 = 0xb0020140, - regi_iop_trigger_grp1 = 0xb0020180, - regi_iop_trigger_grp2 = 0xb00201c0, - regi_iop_trigger_grp3 = 0xb0020200, - regi_iop_trigger_grp4 = 0xb0020240, - regi_iop_trigger_grp5 = 0xb0020280, - regi_iop_trigger_grp6 = 0xb00202c0, - regi_iop_trigger_grp7 = 0xb0020300, - regi_iop_crc_par0 = 0xb0020380, - regi_iop_crc_par1 = 0xb0020400, - regi_iop_dmc_in0 = 0xb0020480, - regi_iop_dmc_in1 = 0xb0020500, - regi_iop_dmc_out0 = 0xb0020580, - regi_iop_dmc_out1 = 0xb0020600, - regi_iop_fifo_in0 = 0xb0020680, - regi_iop_fifo_in1 = 0xb0020700, - regi_iop_fifo_out0 = 0xb0020780, - regi_iop_fifo_out1 = 0xb0020800, - regi_iop_scrc_in0 = 0xb0020880, - regi_iop_scrc_in1 = 0xb0020900, - regi_iop_scrc_out0 = 0xb0020980, - regi_iop_scrc_out1 = 0xb0020a00, - regi_iop_timer_grp0 = 0xb0020a80, - regi_iop_timer_grp1 = 0xb0020b00, - regi_iop_timer_grp2 = 0xb0020b80, - regi_iop_timer_grp3 = 0xb0020c00, - regi_iop_sap_in = 0xb0020d00, - regi_iop_sap_out = 0xb0020e00, - regi_iop_spu0 = 0xb0020f00, - regi_iop_spu1 = 0xb0021000, - regi_iop_sw_cfg = 0xb0021100, - regi_iop_sw_cpu = 0xb0021200, - regi_iop_sw_mpu = 0xb0021300, - regi_iop_sw_spu0 = 0xb0021400, - regi_iop_sw_spu1 = 0xb0021500, - regi_iop_mpu = 0xb0021600, - regi_irq = 0xb001c000, - regi_irq2 = 0xb005c000, - regi_marb = 0xb003e000, - regi_marb_bp0 = 0xb003e240, - regi_marb_bp1 = 0xb003e280, - regi_marb_bp2 = 0xb003e2c0, - regi_marb_bp3 = 0xb003e300, - regi_pinmux = 0xb0038000, - regi_ser0 = 0xb0026000, - regi_ser1 = 0xb0028000, - regi_ser2 = 0xb002a000, - regi_ser3 = 0xb002c000, - regi_sser0 = 0xb0022000, - regi_sser1 = 0xb0024000, - regi_strcop = 0xb0030000, - regi_strmux = 0xb003a000, - regi_timer = 0xb001e000, - regi_timer0 = 0xb001e000, - regi_timer2 = 0xb005e000, - regi_trace = 0xb0040000, -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h deleted file mode 100644 index cbfaa867829e..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h deleted file mode 100644 index 76bcc591921d..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h +++ /dev/null @@ -1,266 +0,0 @@ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h deleted file mode 100644 index c2b3036779df..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/pinmux.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc deleted file mode 100644 index 4a10ccbd6cc1..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/startup.inc +++ /dev/null @@ -1,77 +0,0 @@ -#include -#include -#include -#include - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 - move.d $r0, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - ;; Set up waitstates etc - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 - move.d $r1, [$r0] -#ifdef CONFIG_ETRAX_VCS_SIM - ;; Set up minimal flash waitstates - move.d 0, $r10 - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 - move.d $r10, [$r11] -#endif - .endm diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h deleted file mode 100644 index d29df5644d3e..000000000000 --- a/include/asm-cris/arch-v32/memmap.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00020000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h deleted file mode 100644 index 6bcdc3fdf7dc..000000000000 --- a/include/asm-cris/arch-v32/mmu.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_MMU_H -#define _ASM_CRIS_ARCH_MMU_H - -/* MMU context type. */ -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* Kernel memory segments. */ -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* - * CRISv32 PTE bits: - * - * Bit: 31-13 12-5 4 3 2 1 0 - * +-----+------+--------+-------+--------+-------+---------+ - * | pfn | zero | global | valid | kernel | write | execute | - * +-----+------+--------+-------+--------+-------+---------+ - */ - -/* - * Defines for accessing the bits. Also define some synonyms for use with - * the software-based defined bits below. - */ -#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ -#define _PAGE_WE (1 << 1) /* Write bit. */ -#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ -#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ -#define _PAGE_VALID (1 << 3) /* Page is valid. */ -#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ -#define _PAGE_GLOBAL (1 << 4) /* Global page. */ - -/* - * The hardware doesn't care about these bits, but the kernel uses them in - * software. - */ -#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ -#define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */ -#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ -#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ -#define _PAGE_READ (1 << 8) /* Read enabled. */ -#define _PAGE_WRITE (1 << 9) /* Write enabled. */ - -/* Define some higher level generic page attributes. */ -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED | _PAGE_EXECUTE) - -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) - -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE) - -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* CRISv32 can do page protection for execute. - * Write permissions imply read permissions. - * Note that the numbers are in Execute-Write-Read order! - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY_EXEC -#define __P101 PAGE_READONLY_EXEC -#define __P110 PAGE_COPY_EXEC -#define __P111 PAGE_COPY_EXEC - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY_EXEC -#define __S101 PAGE_READONLY_EXEC -#define __S110 PAGE_SHARED_EXEC -#define __S111 PAGE_SHARED_EXEC - -#define PTE_FILE_MAX_BITS 25 - -#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h deleted file mode 100644 index 4442c4bd52f4..000000000000 --- a/include/asm-cris/arch-v32/offset.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ -#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ -#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ -#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ -#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ -#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ - -#define TASK_pid 151 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h deleted file mode 100644 index 20f1b4806bfe..000000000000 --- a/include/asm-cris/arch-v32/page.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PAGE_H -#define _ASM_CRIS_ARCH_PAGE_H - - -#ifdef __KERNEL__ - -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ - -/* - * Macros to convert between physical and virtual addresses. By stripping a - * selected bit it's possible to convert between KSEG_x and 0x40000000 where the - * DRAM really resides. DRAM is virtually at 0xc. - */ -#ifndef CONFIG_ETRAX_VCS_SIM -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) -#else -#define __pa(x) ((unsigned long)(x) & 0x3fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000)) -#endif - -#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ - VM_MAYREAD | VM_MAYWRITE) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h deleted file mode 100644 index 08cb7ff7e4e7..000000000000 --- a/include/asm-cris/arch-v32/pgtable.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PGTABLE_H -#define _ASM_CRIS_ARCH_PGTABLE_H - -/* Define the kernels virtual memory area. */ -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) - -#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h deleted file mode 100644 index bb09bce42e7a..000000000000 --- a/include/asm-cris/arch-v32/pinmux.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode -{ - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function -{ - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h deleted file mode 100644 index f80b47790ca6..000000000000 --- a/include/asm-cris/arch-v32/processor.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PROCESSOR_H -#define _ASM_CRIS_ARCH_PROCESSOR_H - - -/* Return current instruction pointer. */ -#define current_text_addr() \ - ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) - -/* - * Since CRIS doesn't do hardware task-switching this hasn't really anything to - * do with the proccessor itself, it's just here for legacy reasons. This is - * used when task-switching using _resume defined in entry.S. The offsets here - * are hardcoded into _resume, so if this struct is changed, entry.S needs to be - * changed as well. - */ -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer. */ - unsigned long usp; /* User stack pointer. */ - unsigned long ccs; /* Saved flags register. */ -}; - -/* - * User-space process size. This is hardcoded into a few places, so don't - * changed it unless everything's clear! - */ -#ifndef CONFIG_ETRAX_VCS_SIM -#define TASK_SIZE (0xB0000000UL) -#else -#define TASK_SIZE (0xA0000000UL) -#endif - -/* CCS I=1, enable interrupts. */ -#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) } - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)task_pt_regs(tsk); \ - if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->erp; \ - eip; \ -}) - -/* - * Give the thread a program location, set user-mode and switch user - * stackpointer. - */ -#define start_thread(regs, ip, usp) \ -do { \ - set_fs(USER_DS); \ - regs->erp = ip; \ - regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ - wrusp(usp); \ -} while(0) - -/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ -#define arch_fixup(regs) {}; - -#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h deleted file mode 100644 index 41f4e8662bc2..000000000000 --- a/include/asm-cris/arch-v32/ptrace.h +++ /dev/null @@ -1,118 +0,0 @@ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Register numbers in the ptrace system call interface */ - -#define PT_ORIG_R10 0 -#define PT_R0 1 -#define PT_R1 2 -#define PT_R2 3 -#define PT_R3 4 -#define PT_R4 5 -#define PT_R5 6 -#define PT_R6 7 -#define PT_R7 8 -#define PT_R8 9 -#define PT_R9 10 -#define PT_R10 11 -#define PT_R11 12 -#define PT_R12 13 -#define PT_R13 14 -#define PT_ACR 15 -#define PT_SRS 16 -#define PT_MOF 17 -#define PT_SPC 18 -#define PT_CCS 19 -#define PT_SRP 20 -#define PT_ERP 21 /* This is actually the debugged process' PC */ -#define PT_EXS 22 -#define PT_EDA 23 -#define PT_USP 24 /* special case - USP is not in the pt_regs */ -#define PT_PPC 25 /* special case - pseudo PC */ -#define PT_BP 26 /* Base number for BP registers. */ -#define PT_BP_CTRL 26 /* BP control register. */ -#define PT_MAX 40 - -/* Condition code bit numbers. */ -#define C_CCS_BITNR 0 -#define V_CCS_BITNR 1 -#define Z_CCS_BITNR 2 -#define N_CCS_BITNR 3 -#define X_CCS_BITNR 4 -#define I_CCS_BITNR 5 -#define U_CCS_BITNR 6 -#define P_CCS_BITNR 7 -#define R_CCS_BITNR 8 -#define S_CCS_BITNR 9 -#define M_CCS_BITNR 30 -#define Q_CCS_BITNR 31 -#define CCS_SHIFT 10 /* Shift count for each level in CCS */ - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL. */ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long acr; - unsigned long srs; - unsigned long mof; - unsigned long spc; - unsigned long ccs; - unsigned long srp; - unsigned long erp; /* This is actually the debugged process' PC */ - /* For debugging purposes; saved only when needed. */ - unsigned long exs; - unsigned long eda; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) -#define instruction_pointer(regs) ((regs)->erp) -extern void show_regs(struct pt_regs *); -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h deleted file mode 100644 index 0d5709b983a1..000000000000 --- a/include/asm-cris/arch-v32/spinlock.h +++ /dev/null @@ -1,129 +0,0 @@ -#ifndef __ASM_ARCH_SPINLOCK_H -#define __ASM_ARCH_SPINLOCK_H - -#include - -#define RW_LOCK_BIAS 0x01000000 - -extern void cris_spin_unlock(void *l, int val); -extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void *l); - -static inline int __raw_spin_is_locked(raw_spinlock_t *x) -{ - return *(volatile signed char *)(&(x)->slock) <= 0; -} - -static inline void __raw_spin_unlock(raw_spinlock_t *lock) -{ - __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->slock) \ - : "r" (1) \ - : "memory"); -} - -static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) -{ - while (__raw_spin_is_locked(lock)) - cpu_relax(); -} - -static inline int __raw_spin_trylock(raw_spinlock_t *lock) -{ - return cris_spin_trylock((void *)&lock->slock); -} - -static inline void __raw_spin_lock(raw_spinlock_t *lock) -{ - cris_spin_lock((void *)&lock->slock); -} - -static inline void -__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) -{ - __raw_spin_lock(lock); -} - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - * - */ - -static inline int __raw_read_can_lock(raw_rwlock_t *x) -{ - return (int)(x)->lock > 0; -} - -static inline int __raw_write_can_lock(raw_rwlock_t *x) -{ - return (x)->lock == RW_LOCK_BIAS; -} - -static inline void __raw_read_lock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - while (rw->lock == 0); - rw->lock--; - __raw_spin_unlock(&rw->slock); -} - -static inline void __raw_write_lock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - while (rw->lock != RW_LOCK_BIAS); - rw->lock == 0; - __raw_spin_unlock(&rw->slock); -} - -static inline void __raw_read_unlock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - rw->lock++; - __raw_spin_unlock(&rw->slock); -} - -static inline void __raw_write_unlock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - while (rw->lock != RW_LOCK_BIAS); - rw->lock == RW_LOCK_BIAS; - __raw_spin_unlock(&rw->slock); -} - -static inline int __raw_read_trylock(raw_rwlock_t *rw) -{ - int ret = 0; - __raw_spin_lock(&rw->slock); - if (rw->lock != 0) { - rw->lock--; - ret = 1; - } - __raw_spin_unlock(&rw->slock); - return ret; -} - -static inline int __raw_write_trylock(raw_rwlock_t *rw) -{ - int ret = 0; - __raw_spin_lock(&rw->slock); - if (rw->lock == RW_LOCK_BIAS) { - rw->lock == 0; - ret = 1; - } - __raw_spin_unlock(&rw->slock); - return 1; -} - - -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() - -#endif /* __ASM_ARCH_SPINLOCK_H */ diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h deleted file mode 100644 index 6ca90f1f110a..000000000000 --- a/include/asm-cris/arch-v32/system.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_SYSTEM_H -#define _ASM_CRIS_ARCH_SYSTEM_H - - -/* Read the CPU version register. */ -static inline unsigned long rdvr(void) -{ - unsigned char vr; - - __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "crisv32" - -/* Read the user-mode stack pointer. */ -static inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); - return usp; -} - -/* Read the current stack pointer. */ -static inline unsigned long rdsp(void) -{ - unsigned long sp; - - __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); - return sp; -} - -/* Write the user-mode stack pointer. */ -#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) - -#define nop() __asm__ __volatile__ ("nop"); - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr)))) - -#define tas(ptr) (xchg((ptr),1)) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* Used for interrupt control. */ -#define local_save_flags(x) \ - __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); - -#define local_irq_restore(x) \ - __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); - -#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); -#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - \ - local_save_flags(flags);\ - !(flags & (1 << I_CCS_BITNR)); \ -}) - -/* Used for spinlocks, etc. */ -#define local_irq_save(x) \ - __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); - -#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h deleted file mode 100644 index d6936956a3c6..000000000000 --- a/include/asm-cris/arch-v32/thread_info.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H -#define _ASM_CRIS_ARCH_THREAD_INFO_H - -/* Return a thread_info struct. */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - - __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h deleted file mode 100644 index 2591d3c5ed9d..000000000000 --- a/include/asm-cris/arch-v32/timex.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -#include -#include -#include - -/* - * The clock runs at 100MHz, we divide it by 1000000. If you change anything - * here you must check time.c as well. - */ - -#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ - -/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - -/* Convert the value in step of 10 ns to 1us without overflow: */ -#define GET_JIFFIES_USEC() \ - ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) - -extern unsigned long get_ns_in_jiffie(void); - -static inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie() / 1000; -} - -#endif - diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h deleted file mode 100644 index 4effb1253660..000000000000 --- a/include/asm-cris/arch-v32/tlb.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* - * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used - * to store the "process" it belongs to (=> fast mm context switch). The - * last page_id is never used so we can make TLB entries that never matches. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 256 -#define INVALID_PAGEID 255 -#define NO_CONTEXT -1 - -#endif /* _CRIS_ARCH_TLB_H */ diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h deleted file mode 100644 index 6b207f1b6622..000000000000 --- a/include/asm-cris/arch-v32/uaccess.h +++ /dev/null @@ -1,748 +0,0 @@ -/* - * Authors: Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *at* the faulting - * instruction for CRISv32. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" %1,[%2]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " nop\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) do { \ - int dummy_for_put_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d %M2,[%1+]\n" \ - "4: move.d %H2,[%1]\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ - : "r" (x), "1" (addr), "g" (-EFAULT), \ - "0" (err)); \ - } while (0) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" [%2],%1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) do { \ - int dummy_for_get_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d [%2+],%M1\n" \ - "4: move.d [%2],%H1\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x), \ - "=b" (dummy_for_get_user_asm_64_) \ - : "2" (addr), "g" (-EFAULT), "0" (err));\ - } while (0) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -static inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3; - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - "5: move.b [%2+],$acr\n" - "1: beq 2f\n" - " move.b $acr,[%1+]\n" - - " subq 1,%0\n" - "2: bne 1b\n" - " move.b [%2+],$acr\n" - - " sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - " nop\n" - - /* The address for a fault at the first move is trivial. - The address for a fault at the second move is that of - the preceding branch insn, since the move insn is in - its delay-slot. That address is also a branch - target. Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 5b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "acr"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address for the insn, or for the preceding branch when in a delay-slot. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=b" (to), "=b" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "acr", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - "2: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "3: addq 1,%2\n" \ - " jump 1b\n" \ - " clear.b [%0+]\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "3: addq 2,%2\n" \ - " jump 1b\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "3: addq 4,%2\n" \ - " jump 1b\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - "10: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - COPY \ - "10: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - COPY \ - "12: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "2: move.b $acr,[%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "2: move.w $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 2,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "2: move.d $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "4: move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "4: move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "6: move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "6: move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "8: move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "10: move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "8: move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "10: move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "12: move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=b" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.b [%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n", \ - "3: jump 1b\n" \ - " addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n" \ - "3: clear.b [%0+]\n", \ - "4: addq 2,%1\n" \ - "5: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - CLEAR \ - "2: clear.d [%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%1\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - CLEAR \ - "4: clear.d [%0+]\n", \ - FIXUP \ - "5: addq 4,%1\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - CLEAR \ - "6: clear.d [%0+]\n", \ - FIXUP \ - "7: addq 4,%1\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - CLEAR \ - "8: clear.d [%0+]\n", \ - FIXUP \ - "9: addq 4,%1\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - CLEAR \ - "10: clear.d [%0+]\n", \ - FIXUP \ - "11: addq 4,%1\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - CLEAR \ - "12: clear.d [%0+]\n", \ - FIXUP \ - "13: addq 4,%1\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -static inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$acr\n" - " cmpq 0,$acr\n" - "0:\n" - " ble 1f\n" - " subq 1,$acr\n" - - "4: test.b [%0+]\n" - " bne 0b\n" - " cmpq 0,$acr\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $acr,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: jump 2b\n" - " clear.d %0\n" - - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 4b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "acr"); - - return res; -} - -#endif diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h deleted file mode 100644 index 0051114c63c7..000000000000 --- a/include/asm-cris/arch-v32/unistd.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)\ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __f __asm__ ("srp") = (long) arg6; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h deleted file mode 100644 index 03fa1f3c3c00..000000000000 --- a/include/asm-cris/arch-v32/user.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_USER_H -#define _ASM_CRIS_ARCH_USER_H - -/* User-mode register used for core dumps. */ - -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* R14, Stack pointer. */ - unsigned long acr; /* R15, Address calculation register. */ - unsigned long bz; /* P0, Constant zero (8-bits). */ - unsigned long vr; /* P1, Version register (8-bits). */ - unsigned long pid; /* P2, Process ID (8-bits). */ - unsigned long srs; /* P3, Support register select (8-bits). */ - unsigned long wz; /* P4, Constant zero (16-bits). */ - unsigned long exs; /* P5, Exception status. */ - unsigned long eda; /* P6, Exception data address. */ - unsigned long mof; /* P7, Multiply overflow regiter. */ - unsigned long dz; /* P8, Constant zero (32-bits). */ - unsigned long ebp; /* P9, Exception base pointer. */ - unsigned long erp; /* P10, Exception return pointer. */ - unsigned long srp; /* P11, Subroutine return pointer. */ - unsigned long nrp; /* P12, NMI return pointer. */ - unsigned long ccs; /* P13, Condition code stack. */ - unsigned long usp; /* P14, User mode stack pointer. */ - unsigned long spc; /* P15, Single step PC. */ -}; - -#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h deleted file mode 100644 index 5fc87768774a..000000000000 --- a/include/asm-cris/atomic.h +++ /dev/null @@ -1,164 +0,0 @@ -/* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */ - -#ifndef __ASM_CRIS_ATOMIC__ -#define __ASM_CRIS_ATOMIC__ - -#include - -#include -#include - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -/* These should be written in asm but we do it in C for now. */ - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - v->counter += i; - cris_atomic_restore(v, flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - v->counter -= i; - cris_atomic_restore(v, flags); -} - -static inline int atomic_add_return(int i, volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = (v->counter += i); - cris_atomic_restore(v, flags); - return retval; -} - -#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) - -static inline int atomic_sub_return(int i, volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = (v->counter -= i); - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_sub_and_test(int i, volatile atomic_t *v) -{ - int retval; - unsigned long flags; - cris_atomic_save(v, flags); - retval = (v->counter -= i) == 0; - cris_atomic_restore(v, flags); - return retval; -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - (v->counter)++; - cris_atomic_restore(v, flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - (v->counter)--; - cris_atomic_restore(v, flags); -} - -static inline int atomic_inc_return(volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = ++(v->counter); - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_dec_return(volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = --(v->counter); - cris_atomic_restore(v, flags); - return retval; -} -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - int retval; - unsigned long flags; - cris_atomic_save(v, flags); - retval = --(v->counter) == 0; - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_inc_and_test(volatile atomic_t *v) -{ - int retval; - unsigned long flags; - cris_atomic_save(v, flags); - retval = ++(v->counter) == 0; - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_cmpxchg(atomic_t *v, int old, int new) -{ - int ret; - unsigned long flags; - - cris_atomic_save(v, flags); - ret = v->counter; - if (likely(ret == old)) - v->counter = new; - cris_atomic_restore(v, flags); - return ret; -} - -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - -static inline int atomic_add_unless(atomic_t *v, int a, int u) -{ - int ret; - unsigned long flags; - - cris_atomic_save(v, flags); - ret = v->counter; - if (ret != u) - v->counter += a; - cris_atomic_restore(v, flags); - return ret != u; -} -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#include -#endif diff --git a/include/asm-cris/auxvec.h b/include/asm-cris/auxvec.h deleted file mode 100644 index cb30b01bf19f..000000000000 --- a/include/asm-cris/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASMCRIS_AUXVEC_H -#define __ASMCRIS_AUXVEC_H - -#endif diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h deleted file mode 100644 index 015ca5445ddd..000000000000 --- a/include/asm-cris/axisflashmap.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __ASM_AXISFLASHMAP_H -#define __ASM_AXISFLASHMAP_H - -/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC - * as start, it ends with 0xFFFFFFFF */ -#define FLASH_BOOT_MAGIC 0xbeefcace -#define BOOTPARAM_OFFSET 0xc000 -/* apps/bootblocktool is used to read and write the parameters, - * and it has nothing to do with the partition table. - */ - -#define PARTITION_TABLE_OFFSET 10 -#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ - -/* The partitiontable_head is located at offset +10: */ -struct partitiontable_head { - __u16 magic; /* PARTITION_TABLE_MAGIC */ - __u16 size; /* Length of ptable block (entries + end marker) */ - __u32 checksum; /* simple longword sum, over entries + end marker */ -}; - -/* And followed by partition table entries */ -struct partitiontable_entry { - __u32 offset; /* relative to the sector the ptable is in */ - __u32 size; /* in bytes */ - __u32 checksum; /* simple longword sum */ - __u16 type; /* see type codes below */ - __u16 flags; /* bit 0: ro/rw = 1/0 */ - __u32 future0; /* 16 bytes reserved for future use */ - __u32 future1; - __u32 future2; - __u32 future3; -}; -/* ended by an end marker: */ -#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF -#define PARTITIONTABLE_END_MARKER_SIZE 4 - -#define PARTITIONTABLE_END_PAD 10 - -/* Complete structure for whole partition table */ -/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting - * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. - */ -struct partitiontable { - __u8 skip[PARTITION_TABLE_OFFSET]; - struct partitiontable_head head; - struct partitiontable_entry entries[]; -}; - -#define PARTITION_TYPE_PARAM 0x0001 -#define PARTITION_TYPE_KERNEL 0x0002 -#define PARTITION_TYPE_JFFS 0x0003 -#define PARTITION_TYPE_JFFS2 0x0000 - -#define PARTITION_FLAGS_READONLY_MASK 0x0001 -#define PARTITION_FLAGS_READONLY 0x0001 - -/* The master mtd for the entire flash. */ -extern struct mtd_info *axisflash_mtd; - -#endif diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h deleted file mode 100644 index 75ea6e096483..000000000000 --- a/include/asm-cris/bitops.h +++ /dev/null @@ -1,166 +0,0 @@ -/* asm/bitops.h for Linux/CRIS - * - * TODO: asm versions if speed is needed - * - * All bit operations return 0 if the bit was cleared before the - * operation and != 0 if it was not. - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - */ - -#ifndef _CRIS_BITOPS_H -#define _CRIS_BITOPS_H - -/* Currently this is unsuitable for consumption outside the kernel. */ -#ifdef __KERNEL__ - -#ifndef _LINUX_BITOPS_H -#error only can be included directly -#endif - -#include -#include -#include -#include - -/* - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ - -#define set_bit(nr, addr) (void)test_and_set_bit(nr, addr) - -/* - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ - -#define clear_bit(nr, addr) (void)test_and_clear_bit(nr, addr) - -/* - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ - -#define change_bit(nr, addr) (void)test_and_change_bit(nr, addr) - -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ - -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned int mask, retval; - unsigned long flags; - unsigned int *adr = (unsigned int *)addr; - - adr += nr >> 5; - mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); - retval = (mask & *adr) != 0; - *adr |= mask; - cris_atomic_restore(addr, flags); - return retval; -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ - -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned int mask, retval; - unsigned long flags; - unsigned int *adr = (unsigned int *)addr; - - adr += nr >> 5; - mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); - retval = (mask & *adr) != 0; - *adr &= ~mask; - cris_atomic_restore(addr, flags); - return retval; -} - -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ - -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) -{ - unsigned int mask, retval; - unsigned long flags; - unsigned int *adr = (unsigned int *)addr; - adr += nr >> 5; - mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); - retval = (mask & *adr) != 0; - *adr ^= mask; - cris_atomic_restore(addr, flags); - return retval; -} - -#include - -/* - * Since we define it "external", it collides with the built-in - * definition, which doesn't have the same semantics. We don't want to - * use -fno-builtin, so just hide the name ffs. - */ -#define ffs kernel_ffs - -#include -#include -#include -#include -#include - -#include - -#define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) -#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) - -#include -#include - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_BITOPS_H */ diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h deleted file mode 100644 index fee12d4ae683..000000000000 --- a/include/asm-cris/bug.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _CRIS_BUG_H -#define _CRIS_BUG_H -#include -#endif diff --git a/include/asm-cris/bugs.h b/include/asm-cris/bugs.h deleted file mode 100644 index c5907aac1007..000000000000 --- a/include/asm-cris/bugs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ - * - * include/asm-cris/bugs.h - * - * Copyright (C) 2001 Axis Communications AB - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -static void check_bugs(void) -{ -} - - - - diff --git a/include/asm-cris/byteorder.h b/include/asm-cris/byteorder.h deleted file mode 100644 index 0cd9db1cc888..000000000000 --- a/include/asm-cris/byteorder.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _CRIS_BYTEORDER_H -#define _CRIS_BYTEORDER_H - -#ifdef __GNUC__ - -#ifdef __KERNEL__ -#include - -/* defines are necessary because the other files detect the presence - * of a defined __arch_swab32, not an inline - */ -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) -#endif /* __KERNEL__ */ - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#include - -#endif - - diff --git a/include/asm-cris/cache.h b/include/asm-cris/cache.h deleted file mode 100644 index 46a3b26e205a..000000000000 --- a/include/asm-cris/cache.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include - -#endif /* _ASM_CACHE_H */ diff --git a/include/asm-cris/cacheflush.h b/include/asm-cris/cacheflush.h deleted file mode 100644 index cf60e3f69f8d..000000000000 --- a/include/asm-cris/cacheflush.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _CRIS_CACHEFLUSH_H -#define _CRIS_CACHEFLUSH_H - -/* Keep includes the same across arches. */ -#include - -/* The cache doesn't need to be flushed when TLB entries change because - * the cache is mapped to physical memory, not virtual memory - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -int change_page_attr(struct page *page, int numpages, pgprot_t prot); - -#endif /* _CRIS_CACHEFLUSH_H */ diff --git a/include/asm-cris/checksum.h b/include/asm-cris/checksum.h deleted file mode 100644 index c6c5be62c698..000000000000 --- a/include/asm-cris/checksum.h +++ /dev/null @@ -1,83 +0,0 @@ -/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ - -#ifndef _CRIS_CHECKSUM_H -#define _CRIS_CHECKSUM_H - -#include - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -__wsum csum_partial(const void *buff, int len, __wsum sum); - -/* - * the same as csum_partial, but copies from src while it - * checksums - * - * here even more important to align src and dst on a 32-bit (or even - * better 64-bit) boundary - */ - -__wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum); - -/* - * Fold a partial checksum into a word - */ - -static inline __sum16 csum_fold(__wsum csum) -{ - u32 sum = (__force u32)csum; - sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ - sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ - return (__force __sum16)~sum; -} - -extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, - int len, __wsum sum, - int *errptr); - -/* - * This is a version of ip_compute_csum() optimized for IP headers, - * which always checksum on 4 octet boundaries. - * - */ - -static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) -{ - return csum_fold(csum_partial(iph, ihl * 4, 0)); -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ - -static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, - unsigned short len, - unsigned short proto, - __wsum sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); -} - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ - -static inline __sum16 ip_compute_csum(const void *buff, int len) -{ - return csum_fold (csum_partial(buff, len, 0)); -} - -#endif diff --git a/include/asm-cris/cputime.h b/include/asm-cris/cputime.h deleted file mode 100644 index 4446a65656fa..000000000000 --- a/include/asm-cris/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __CRIS_CPUTIME_H -#define __CRIS_CPUTIME_H - -#include - -#endif /* __CRIS_CPUTIME_H */ diff --git a/include/asm-cris/current.h b/include/asm-cris/current.h deleted file mode 100644 index 5f5c0efd00be..000000000000 --- a/include/asm-cris/current.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _CRIS_CURRENT_H -#define _CRIS_CURRENT_H - -#include - -struct task_struct; - -static inline struct task_struct * get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() - -#endif /* !(_CRIS_CURRENT_H) */ diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h deleted file mode 100644 index 123e19aef49d..000000000000 --- a/include/asm-cris/delay.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _CRIS_DELAY_H -#define _CRIS_DELAY_H - -/* - * Copyright (C) 1998-2002 Axis Communications AB - * - * Delay routines, using a pre-computed "loops_per_second" value. - */ - -#include - -/* Use only for very small delays ( < 1 msec). */ - -extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ - -/* May be defined by arch/delay.h. */ -#ifndef udelay -static inline void udelay(unsigned long usecs) -{ - __delay(usecs * loops_per_usec); -} -#endif - -#endif /* defined(_CRIS_DELAY_H) */ - - - diff --git a/include/asm-cris/device.h b/include/asm-cris/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-cris/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include - diff --git a/include/asm-cris/div64.h b/include/asm-cris/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/include/asm-cris/div64.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h deleted file mode 100644 index da8ef8e8f842..000000000000 --- a/include/asm-cris/dma-mapping.h +++ /dev/null @@ -1,170 +0,0 @@ -/* DMA mapping. Nothing tricky here, just virt_to_phys */ - -#ifndef _ASM_CRIS_DMA_MAPPING_H -#define _ASM_CRIS_DMA_MAPPING_H - -#include -#include - -#include -#include -#include - -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) - -#ifdef CONFIG_PCI -#include - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); - -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); -#else -static inline void * -dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - gfp_t flag) -{ - BUG(); - return NULL; -} - -static inline void -dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) -{ - BUG(); -} -#endif -static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - return virt_to_phys(ptr); -} - -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - printk("Map sg\n"); - return nents; -} - -static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, unsigned long offset, - size_t size, enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - return page_to_phys(page) + offset; -} - -static inline void -dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - - -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ -} - -static inline int -dma_mapping_error(struct device *dev, dma_addr_t dma_addr) -{ - return 0; -} - -static inline int -dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if(mask < 0x00ffffff) - return 0; - - return 1; -} - -static inline int -dma_set_mask(struct device *dev, u64 mask) -{ - if(!dev->dma_mask || !dma_supported(dev, mask)) - return -EIO; - - *dev->dma_mask = mask; - - return 0; -} - -static inline int -dma_get_cache_alignment(void) -{ - return (1 << INTERNODE_CACHE_SHIFT); -} - -#define dma_is_consistent(d, h) (1) - -static inline void -dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction) -{ -} - - -#endif diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h deleted file mode 100644 index 6f188dc56138..000000000000 --- a/include/asm-cris/dma.h +++ /dev/null @@ -1,21 +0,0 @@ -/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ - -#ifndef _ASM_DMA_H -#define _ASM_DMA_H - -#include - -/* it's useless on the Etrax, but unfortunately needed by the new - bootmem allocator (but this should do it for this) */ - -#define MAX_DMA_ADDRESS PAGE_OFFSET - -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - -#endif /* _ASM_DMA_H */ diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h deleted file mode 100644 index f0d17fbc81ba..000000000000 --- a/include/asm-cris/elf.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef __ASMCRIS_ELF_H -#define __ASMCRIS_ELF_H - -/* - * ELF register definitions.. - */ - -#include - -#define R_CRIS_NONE 0 -#define R_CRIS_8 1 -#define R_CRIS_16 2 -#define R_CRIS_32 3 -#define R_CRIS_8_PCREL 4 -#define R_CRIS_16_PCREL 5 -#define R_CRIS_32_PCREL 6 -#define R_CRIS_GNU_VTINHERIT 7 -#define R_CRIS_GNU_VTENTRY 8 -#define R_CRIS_COPY 9 -#define R_CRIS_GLOB_DAT 10 -#define R_CRIS_JUMP_SLOT 11 -#define R_CRIS_RELATIVE 12 -#define R_CRIS_16_GOT 13 -#define R_CRIS_32_GOT 14 -#define R_CRIS_16_GOTPLT 15 -#define R_CRIS_32_GOTPLT 16 -#define R_CRIS_32_GOTREL 17 -#define R_CRIS_32_PLT_GOTREL 18 -#define R_CRIS_32_PLT_PCREL 19 - -typedef unsigned long elf_greg_t; - -/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is - thus exposed to user-space. */ -#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -/* A placeholder; CRIS does not have any fp regs. */ -typedef unsigned long elf_fpregset_t; - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_CRIS - -#include - -/* The master for these definitions is {binutils}/include/elf/cris.h: */ -/* User symbols in this file have a leading underscore. */ -#define EF_CRIS_UNDERSCORE 0x00000001 - -/* This is a mask for different incompatible machine variants. */ -#define EF_CRIS_VARIANT_MASK 0x0000000e - -/* Variant 0; may contain v0..10 object. */ -#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 - -/* Variant 1; contains v32 object. */ -#define EF_CRIS_VARIANT_V32 0x00000002 - -/* Variant 2; contains object compatible with v32 and v10. */ -#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 -/* End of excerpt from {binutils}/include/elf/cris.h. */ - -#define USE_ELF_CORE_DUMP - -#define ELF_EXEC_PAGESIZE 8192 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -/* This yields a mask that user programs can use to figure out what - instruction set this CPU supports. This could be done in user space, - but it's not easy, and we've already done it here. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. -*/ - -#define ELF_PLATFORM (NULL) - -#define SET_PERSONALITY(ex) set_personality(PER_LINUX) - -#endif diff --git a/include/asm-cris/emergency-restart.h b/include/asm-cris/emergency-restart.h deleted file mode 100644 index 108d8c48e42e..000000000000 --- a/include/asm-cris/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-cris/errno.h b/include/asm-cris/errno.h deleted file mode 100644 index 2bf5eb5fa773..000000000000 --- a/include/asm-cris/errno.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_ERRNO_H -#define _CRIS_ERRNO_H - -#include - -#endif diff --git a/include/asm-cris/eshlibld.h b/include/asm-cris/eshlibld.h deleted file mode 100644 index 10ce36cf79a9..000000000000 --- a/include/asm-cris/eshlibld.h +++ /dev/null @@ -1,113 +0,0 @@ -/*!************************************************************************** -*! -*! FILE NAME : eshlibld.h -*! -*! DESCRIPTION: Prototypes for exported shared library functions -*! -*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit -*! (EXPORTED) -*! -*!--------------------------------------------------------------------------- -*! -*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN -*! -*!**************************************************************************/ -/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ - -#ifndef _cris_relocate_h -#define _cris_relocate_h - -/* Please note that this file is also compiled into the xsim simulator. - Try to avoid breaking its double use (only works on a little-endian - 32-bit machine such as the i386 anyway). - - Use __KERNEL__ when you're about to use kernel functions, - (which you should not do here anyway, since this file is - used by glibc). - Use defined(__KERNEL__) || defined(__elinux__) when doing - things that only makes sense on an elinux system. - Use __CRIS__ when you're about to do (really) CRIS-specific code. -*/ - -/* We have dependencies all over the place for the host system - for xsim being a linux system, so let's not pretend anything - else with #ifdef:s here until fixed. */ -#include - -/* Maybe do sanity checking if file input. */ -#undef SANITYCHECK_RELOC - -/* Maybe output debug messages. */ -#undef RELOC_DEBUG - -/* Maybe we want to share core as well as disk space. - Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is - assumed that we want to share code when debugging (exposes more - trouble). */ -#ifndef SHARE_LIB_CORE -# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ - && !defined(CONFIG_SHARE_SHLIB_CORE) -# define SHARE_LIB_CORE 0 -# else -# define SHARE_LIB_CORE 1 -# endif /* __KERNEL__ etc */ -#endif /* SHARE_LIB_CORE */ - - -/* Main exported function; supposed to be called when the program a.out - has been read in. */ -extern int -perform_cris_aout_relocations(unsigned long text, unsigned long tlength, - unsigned long data, unsigned long dlength, - unsigned long baddr, unsigned long blength, - - /* These may be zero when there's "perfect" - position-independent code. */ - unsigned char *trel, unsigned long tsrel, - unsigned long dsrel, - - /* These will be zero at a first try, to see - if code is statically linked. Else a - second try, with the symbol table and - string table nonzero should be done. */ - unsigned char *symbols, unsigned long symlength, - unsigned char *strings, unsigned long stringlength, - - /* These will only be used when symbol table - information is present. */ - char **env, int envc, - int euid, int is_suid); - - -#ifdef RELOC_DEBUG -/* Task-specific debug stuff. */ -struct task_reloc_debug { - struct memdebug *alloclast; - unsigned long alloc_total; - unsigned long export_total; -}; -#endif /* RELOC_DEBUG */ - -#if SHARE_LIB_CORE - -/* When code (and some very specific data) is shared and not just - dynamically linked, we need to export hooks for exec beginning and - end. */ - -struct shlibdep; - -extern void -shlibmod_exit(struct shlibdep **deps); - -/* Returns 0 if failure, nonzero for ok. */ -extern int -shlibmod_fork(struct shlibdep **deps); - -#else /* ! SHARE_LIB_CORE */ -# define shlibmod_exit(x) -# define shlibmod_fork(x) 1 -#endif /* ! SHARE_LIB_CORE */ - -#endif _cris_relocate_h -/********************** END OF FILE eshlibld.h *****************************/ - diff --git a/include/asm-cris/ethernet.h b/include/asm-cris/ethernet.h deleted file mode 100644 index 4d58652c3a49..000000000000 --- a/include/asm-cris/ethernet.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * ioctl defines for ethernet driver - * - * Copyright (c) 2001 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef _CRIS_ETHERNET_H -#define _CRIS_ETHERNET_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ -#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ -#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ -#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 -#endif /* _CRIS_ETHERNET_H */ diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h deleted file mode 100644 index 38f1c8e1770c..000000000000 --- a/include/asm-cris/etraxgpio.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * The following devices are accessable using this driver using - * GPIO_MAJOR (120) and a couple of minor numbers. - * - * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/gpiog minor 3 - * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG - * g1-g7 and g25-g31 is both input and outputs but on different pins - * Also note that some bits change pins depending on what interfaces - * are enabled. - * - * For ETRAX FS (CONFIG_ETRAXFS): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction - * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction - * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction - * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * - * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction - * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction - * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/pwm0 minor 16, PWM channel 0 on PA30 - * /dev/pwm1 minor 17, PWM channel 1 on PA31 - * /dev/pwm2 minor 18, PWM channel 2 on PB26 - * - */ -#ifndef _ASM_ETRAXGPIO_H -#define _ASM_ETRAXGPIO_H - -/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ -#ifdef CONFIG_ETRAX_ARCH_V10 -#define ETRAXGPIO_IOCTYPE 43 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_G 3 -#define GPIO_MINOR_LAST 3 -#endif - -#ifdef CONFIG_ETRAXFS -#define ETRAXGPIO_IOCTYPE 43 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#define GPIO_MINOR_E 5 -#ifdef CONFIG_ETRAX_VIRTUAL_GPIO -#define GPIO_MINOR_V 6 -#define GPIO_MINOR_LAST 6 -#else -#define GPIO_MINOR_LAST 5 -#endif -#endif - -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -#define ETRAXGPIO_IOCTYPE 43 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#ifdef CONFIG_ETRAX_VIRTUAL_GPIO -#define GPIO_MINOR_V 6 -#define GPIO_MINOR_LAST 6 -#else -#define GPIO_MINOR_LAST 4 -#endif -#define GPIO_MINOR_PWM0 16 -#define GPIO_MINOR_PWM1 17 -#define GPIO_MINOR_PWM2 18 -#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 -#endif - -/* supported ioctl _IOC_NR's */ - -#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ -#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ -#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ - -/* the alarm is waited for by select() */ - -#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ -#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ -#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ - -/* LED ioctl */ -#define IO_LEDACTIVE_SET 0x7 /* set active led - * 0=off, 1=green, 2=red, 3=yellow */ - -/* GPIO direction ioctl's */ -#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ -#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, - returns mask with current inputs (obsolete) */ -#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, - returns mask with current outputs (obsolete)*/ - -/* LED ioctl extended */ -#define IO_LED_SETBIT 0xB -#define IO_LED_CLRBIT 0xC - -/* SHUTDOWN ioctl */ -#define IO_SHUTDOWN 0xD -#define IO_GET_PWR_BT 0xE - -/* Bit toggling in driver settings */ -/* bit set in low byte0 is CLK mask (0x00FF), - bit set in byte1 is DATA mask (0xFF00) - msb, data_mask[7:0] , clk_mask[7:0] - */ -#define IO_CFG_WRITE_MODE 0xF -#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ - ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) - -/* The following 4 ioctl's take a pointer as argument and handles - * 32 bit ports (port G) properly. - * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT - */ -#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ -#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ -#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, - * *arg updated with current input pins. - */ -#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, - * *arg updated with current output pins. - */ - -/* The following ioctl's are applicable to the PWM channels only */ - -#define IO_PWM_SET_MODE 0x20 - -enum io_pwm_mode { - PWM_OFF = 0, /* disabled, deallocated */ - PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ - PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ - PWM_VARFREQ = 3 /* individually configurable high/low periods */ -}; - -struct io_pwm_set_mode { - enum io_pwm_mode mode; -}; - -/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns - * from 10ns (value = 0) to 81920ns (value = 8191) - * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to - * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty - * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) - */ -#define IO_PWM_SET_PERIOD 0x21 - -struct io_pwm_set_period { - unsigned int lo; /* 0..8191 */ - unsigned int hi; /* 0..8191 */ -}; - -/* Only for modes PWM_STANDARD and PWM_FAST. - * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from - * 0 (value = 0) to 255/256 (value = 255). - * For PWM_FAST, set duty cycle of PWM output signal from - * 0% (value = 0) to 100% (value = 255). Output signal in this mode - * is a 10ns pulse surrounded by a high or low level depending on duty - * cycle (except for 0% and 100% which result in a constant output). - * Resulting output frequency varies from 50 MHz at 50% duty cycle, - * down to 390 kHz at min/max duty cycle. - */ -#define IO_PWM_SET_DUTY 0x22 - -struct io_pwm_set_duty { - int duty; /* 0..255 */ -}; - -#endif diff --git a/include/asm-cris/etraxi2c.h b/include/asm-cris/etraxi2c.h deleted file mode 100644 index e369a7620893..000000000000 --- a/include/asm-cris/etraxi2c.h +++ /dev/null @@ -1,36 +0,0 @@ -/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ - -#ifndef _LINUX_ETRAXI2C_H -#define _LINUX_ETRAXI2C_H - -/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ - -#define ETRAXI2C_IOCTYPE 44 - -/* supported ioctl _IOC_NR's */ - -/* in write operations, the argument contains both i2c - * slave, register and value. - */ - -#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) -#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) - -#define I2C_ARGSLAVE(arg) ((arg) >> 16) -#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) -#define I2C_ARGVALUE(arg) ((arg) & 0xff) - -#define I2C_WRITEREG 0x1 /* write to an i2c register */ -#define I2C_READREG 0x2 /* read from an i2c register */ - -/* -EXAMPLE usage: - - i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); - ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); - - i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); - val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); - -*/ -#endif diff --git a/include/asm-cris/fasttimer.h b/include/asm-cris/fasttimer.h deleted file mode 100644 index 8f8a8d6c9653..000000000000 --- a/include/asm-cris/fasttimer.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * linux/include/asm-cris/fasttimer.h - * - * Fast timers for ETRAX100LX - * Copyright (C) 2000-2007 Axis Communications AB - */ -#include /* struct timeval */ -#include - -#ifdef CONFIG_ETRAX_FAST_TIMER - -typedef void fast_timer_function_type(unsigned long); - -struct fasttime_t { - unsigned long tv_jiff; /* jiffies */ - unsigned long tv_usec; /* microseconds */ -}; - -struct fast_timer{ /* Close to timer_list */ - struct fast_timer *next; - struct fast_timer *prev; - struct fasttime_t tv_set; - struct fasttime_t tv_expires; - unsigned long delay_us; - fast_timer_function_type *function; - unsigned long data; - const char *name; -}; - -extern struct fast_timer *fast_timer_list; - -void start_one_shot_timer(struct fast_timer *t, - fast_timer_function_type *function, - unsigned long data, - unsigned long delay_us, - const char *name); - -int del_fast_timer(struct fast_timer * t); -/* return 1 if deleted */ - - -void schedule_usleep(unsigned long us); - - -int fast_timer_init(void); - -#endif diff --git a/include/asm-cris/fb.h b/include/asm-cris/fb.h deleted file mode 100644 index c7df38030992..000000000000 --- a/include/asm-cris/fb.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ -#include - -#define fb_pgprotect(...) do {} while (0) - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ diff --git a/include/asm-cris/fcntl.h b/include/asm-cris/fcntl.h deleted file mode 100644 index 46ab12db5739..000000000000 --- a/include/asm-cris/fcntl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/futex.h b/include/asm-cris/futex.h deleted file mode 100644 index 6a332a9f099c..000000000000 --- a/include/asm-cris/futex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H - -#include - -#endif diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h deleted file mode 100644 index 74178adeb1cd..000000000000 --- a/include/asm-cris/hardirq.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __ASM_HARDIRQ_H -#define __ASM_HARDIRQ_H - -#include -#include -#include - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - -void ack_bad_irq(unsigned int irq); - -#define HARDIRQ_BITS 8 - -/* - * The hardirq mask has to be large enough to have - * space for potentially all IRQ sources in the system - * nesting on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -#endif /* __ASM_HARDIRQ_H */ diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h deleted file mode 100644 index 298066020af2..000000000000 --- a/include/asm-cris/hw_irq.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -#endif - diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h deleted file mode 100644 index b87ce63f531f..000000000000 --- a/include/asm-cris/io.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef _ASM_CRIS_IO_H -#define _ASM_CRIS_IO_H - -#include /* for __va, __pa */ -#include -#include - -struct cris_io_operations -{ - u32 (*read_mem)(void *addr, int size); - void (*write_mem)(u32 val, int size, void *addr); - u32 (*read_io)(u32 port, void *addr, int size, int count); - void (*write_io)(u32 port, void *addr, int size, int count); -}; - -#ifdef CONFIG_PCI -extern struct cris_io_operations *cris_iops; -#else -#define cris_iops ((struct cris_io_operations*)NULL) -#endif - -/* - * Change virtual addresses to physical addresses and vv. - */ - -static inline unsigned long virt_to_phys(volatile void * address) -{ - return __pa(address); -} - -static inline void * phys_to_virt(unsigned long address) -{ - return __va(address); -} - -extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); -extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); - -static inline void __iomem * ioremap (unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, 0); -} - -extern void iounmap(volatile void * __iomem addr); - -extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); - -/* - * IO bus memory addresses are also 1:1 with the physical address - */ -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt - -/* - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the CRIS architecture, we just read/write the - * memory location directly. - */ -#ifdef CONFIG_PCI -#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) -#else -#define PCI_SPACE(x) 0 -#endif -static inline unsigned char readb(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 1); - else - return *(volatile unsigned char __force *) addr; -} -static inline unsigned short readw(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 2); - else - return *(volatile unsigned short __force *) addr; -} -static inline unsigned int readl(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 4); - else - return *(volatile unsigned int __force *) addr; -} -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -static inline void writeb(unsigned char b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 1, (void*)addr); - else - *(volatile unsigned char __force *) addr = b; -} -static inline void writew(unsigned short b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 2, (void*)addr); - else - *(volatile unsigned short __force *) addr = b; -} -static inline void writel(unsigned int b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 4, (void*)addr); - else - *(volatile unsigned int __force *) addr = b; -} -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define mmiowb() - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - - -/* I/O port access. Normally there is no I/O space on CRIS but when - * Cardbus/PCI is enabled the request is passed through the bridge. - */ - -#define IO_SPACE_LIMIT 0xffff -#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) -#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) -#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) -#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) -#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) -#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) -#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1) -#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1) -#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1) -#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count) -#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count) -#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count) - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#endif diff --git a/include/asm-cris/ioctl.h b/include/asm-cris/ioctl.h deleted file mode 100644 index b279fe06dfe5..000000000000 --- a/include/asm-cris/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/ioctls.h b/include/asm-cris/ioctls.h deleted file mode 100644 index 4f4e52531fa0..000000000000 --- a/include/asm-cris/ioctls.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef __ARCH_CRIS_IOCTLS_H__ -#define __ARCH_CRIS_IOCTLS_H__ - -/* verbatim copy of asm-i386/ioctls.h */ - -#include - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ -#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ -#define FIOQSIZE 0x5460 - -#define TIOCSERSETRS485 0x5461 /* enable rs-485 */ -#define TIOCSERWRRS485 0x5462 /* write rs-485 */ - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -#endif diff --git a/include/asm-cris/ipcbuf.h b/include/asm-cris/ipcbuf.h deleted file mode 100644 index 8b0c18b02844..000000000000 --- a/include/asm-cris/ipcbuf.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __CRIS_IPCBUF_H__ -#define __CRIS_IPCBUF_H__ - -/* - * The user_ipc_perm structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit mode_t and seq - * - 2 miscellaneous 32-bit values - */ - -struct ipc64_perm -{ - __kernel_key_t key; - __kernel_uid32_t uid; - __kernel_gid32_t gid; - __kernel_uid32_t cuid; - __kernel_gid32_t cgid; - __kernel_mode_t mode; - unsigned short __pad1; - unsigned short seq; - unsigned short __pad2; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* __CRIS_IPCBUF_H__ */ diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h deleted file mode 100644 index 998cce9f3200..000000000000 --- a/include/asm-cris/irq.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -#include - -static inline int irq_canonicalize(int irq) -{ - return irq; -} - -#endif /* _ASM_IRQ_H */ - - diff --git a/include/asm-cris/irq_regs.h b/include/asm-cris/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-cris/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/kdebug.h b/include/asm-cris/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-cris/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h deleted file mode 100644 index 492988cb9077..000000000000 --- a/include/asm-cris/kmap_types.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - -/* Dummy header just to define km_type. None of this - * is actually used on cris. - */ - -enum km_type { - KM_BOUNCE_READ, - KM_SKB_SUNRPC_DATA, - KM_SKB_DATA_SOFTIRQ, - KM_USER0, - KM_USER1, - KM_BIO_SRC_IRQ, - KM_BIO_DST_IRQ, - KM_PTE0, - KM_PTE1, - KM_IRQ0, - KM_IRQ1, - KM_SOFTIRQ0, - KM_SOFTIRQ1, - KM_TYPE_NR -}; - -#endif diff --git a/include/asm-cris/linkage.h b/include/asm-cris/linkage.h deleted file mode 100644 index 291c2d01c44f..000000000000 --- a/include/asm-cris/linkage.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -/* Nothing to see here... */ - -#endif diff --git a/include/asm-cris/local.h b/include/asm-cris/local.h deleted file mode 100644 index c11c530f74d0..000000000000 --- a/include/asm-cris/local.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/mman.h b/include/asm-cris/mman.h deleted file mode 100644 index 1c35e1b66b46..000000000000 --- a/include/asm-cris/mman.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __CRIS_MMAN_H__ -#define __CRIS_MMAN_H__ - -/* verbatim copy of asm-i386/ version */ - -#include - -#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -#define MAP_LOCKED 0x2000 /* pages are locked */ -#define MAP_NORESERVE 0x4000 /* don't check for reservations */ -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ - -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ - -#endif /* __CRIS_MMAN_H__ */ diff --git a/include/asm-cris/mmu.h b/include/asm-cris/mmu.h deleted file mode 100644 index c40a1bcad06c..000000000000 --- a/include/asm-cris/mmu.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * CRIS MMU constants and PTE layout - */ - -#ifndef _CRIS_MMU_H -#define _CRIS_MMU_H - -#include - -#endif diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h deleted file mode 100644 index 72ba08dcfd18..000000000000 --- a/include/asm-cris/mmu_context.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __CRIS_MMU_CONTEXT_H -#define __CRIS_MMU_CONTEXT_H - -#include - -extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); -extern void get_mmu_context(struct mm_struct *mm); -extern void destroy_context(struct mm_struct *mm); -extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk); - -#define deactivate_mm(tsk,mm) do { } while (0) - -#define activate_mm(prev,next) switch_mm((prev),(next),NULL) - -/* current active pgd - this is similar to other processors pgd - * registers like cr3 on the i386 - */ - -extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */ - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -#endif diff --git a/include/asm-cris/module.h b/include/asm-cris/module.h deleted file mode 100644 index 7ee72311bd78..000000000000 --- a/include/asm-cris/module.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_MODULE_H -#define _ASM_CRIS_MODULE_H -/* cris is simple */ -struct mod_arch_specific { }; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr -#endif /* _ASM_CRIS_MODULE_H */ diff --git a/include/asm-cris/msgbuf.h b/include/asm-cris/msgbuf.h deleted file mode 100644 index ada63df1d574..000000000000 --- a/include/asm-cris/msgbuf.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _CRIS_MSGBUF_H -#define _CRIS_MSGBUF_H - -/* verbatim copy of asm-i386 version */ - -/* - * The msqid64_ds structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _CRIS_MSGBUF_H */ diff --git a/include/asm-cris/mutex.h b/include/asm-cris/mutex.h deleted file mode 100644 index 458c1f7fbc18..000000000000 --- a/include/asm-cris/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h deleted file mode 100644 index d19272ba6b69..000000000000 --- a/include/asm-cris/page.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef _CRIS_PAGE_H -#define _CRIS_PAGE_H - -#include -#include - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 13 -#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) - -#define clear_user_page(page, vaddr, pg) clear_page(page) -#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) - -#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ - alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) -#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE - -/* - * These are used to make use of C type-checking.. - */ -#ifndef __ASSEMBLY__ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; -#endif - -#define pte_val(x) ((x).pte) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ -/* for that before indexing into the page table starting at mem_map */ -#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) -#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) - -/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so - * we can let the map start there. notice that we subtract PAGE_OFFSET because - * we start our mem_map there - in other ports they map mem_map physically and - * use __pa instead. in our system both the physical and virtual address of DRAM - * is too high to let mem_map start at 0, so we do it this way instead (similar - * to arm and m68k I think) - */ - -#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) -#define VALID_PAGE(page) (((page) - mem_map) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) - -/* convert a page (based on mem_map and forward) to a physical address - * do this by figuring out the virtual address and then use __pa - */ - -#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) - -#ifndef __ASSEMBLY__ - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#include -#include - -#endif /* _CRIS_PAGE_H */ - diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h deleted file mode 100644 index 0e47994e40be..000000000000 --- a/include/asm-cris/param.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _ASMCRIS_PARAM_H -#define _ASMCRIS_PARAM_H - -/* Currently we assume that HZ=100 is good for CRIS. */ -#ifdef __KERNEL__ -# define HZ CONFIG_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#endif - -#ifndef HZ -#define HZ 100 -#endif - -#define EXEC_PAGESIZE 8192 - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ - -#endif diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h deleted file mode 100644 index 730ce40fdd0f..000000000000 --- a/include/asm-cris/pci.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef __ASM_CRIS_PCI_H -#define __ASM_CRIS_PCI_H - - -#ifdef __KERNEL__ -#include /* for struct page */ - -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -#define pcibios_assign_all_busses(void) 1 - -extern unsigned long pci_mem_start; -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -#define PCIBIOS_MIN_CARDBUS_IO 0x4000 - -void pcibios_config_init(void); -struct pci_bus * pcibios_scan_root(int bus); -int pcibios_assign_resources(void); - -void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); -struct irq_routing_table *pcibios_get_irq_routing_table(void); -int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); - -/* Dynamic DMA mapping stuff. - * i386 has everything mapped statically. - */ - -#include -#include -#include -#include -#include - -struct pci_dev; - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#define HAVE_PCI_MMAP -extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine); - - -#endif /* __KERNEL__ */ - -/* implement the pci_ DMA API in terms of the generic device dma_ one */ -#include - -/* generic pci stuff */ -#include - -#endif /* __ASM_CRIS_PCI_H */ diff --git a/include/asm-cris/percpu.h b/include/asm-cris/percpu.h deleted file mode 100644 index 6db9b43cf80a..000000000000 --- a/include/asm-cris/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_PERCPU_H -#define _CRIS_PERCPU_H - -#include - -#endif /* _CRIS_PERCPU_H */ diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h deleted file mode 100644 index a1ba761d0573..000000000000 --- a/include/asm-cris/pgalloc.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef _CRIS_PGALLOC_H -#define _CRIS_PGALLOC_H - -#include -#include - -#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) -#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) -#define pmd_pgtable(pmd) pmd_page(pmd) - -/* - * Allocate and free page tables. - */ - -static inline pgd_t *pgd_alloc (struct mm_struct *mm) -{ - return (pgd_t *)get_zeroed_page(GFP_KERNEL); -} - -static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - free_page((unsigned long)pgd); -} - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); - return pte; -} - -static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - struct page *pte; - pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); - pgtable_page_ctor(pte); - return pte; -} - -static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_page((unsigned long)pte); -} - -static inline void pte_free(struct mm_struct *mm, pgtable_t pte) -{ - pgtable_page_dtor(pte); - __free_page(pte); -} - -#define __pte_free_tlb(tlb,pte) \ -do { \ - pgtable_page_dtor(pte); \ - tlb_remove_page((tlb), pte); \ -} while (0) - -#define check_pgt_cache() do { } while (0) - -#endif diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h deleted file mode 100644 index 829e7a7d9fb9..000000000000 --- a/include/asm-cris/pgtable.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * CRIS pgtable.h - macros and functions to manipulate page tables. - */ - -#ifndef _CRIS_PGTABLE_H -#define _CRIS_PGTABLE_H - -#include -#include - -#ifndef __ASSEMBLY__ -#include -#include -#endif -#include - -/* - * The Linux memory management assumes a three-level page table setup. On - * CRIS, we use that, but "fold" the mid level into the top-level page - * table. Since the MMU TLB is software loaded through an interrupt, it - * supports any page table structure, so we could have used a three-level - * setup, but for the amounts of memory we normally use, a two-level is - * probably more efficient. - * - * This file contains the functions and defines necessary to modify and use - * the CRIS page table tree. - */ -#ifndef __ASSEMBLY__ -extern void paging_init(void); -#endif - -/* Certain architectures need to do special things when pte's - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - -/* - * (pmds are folded into pgds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) -#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) - -/* PGDIR_SHIFT determines the size of the area a second-level page table can - * map. It is equal to the page size times the number of PTE's that fit in - * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. - */ - -#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * entries per page directory level: we use a two-level, so - * we don't really have any PMD directory physically. - * pointers are 4 bytes so we can use the page size and - * divide it by 4 (shift by 2). - */ -#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) -#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) - -/* calculate how many PGD entries a user-level program can use - * the first mappable virtual address is 0 - * (TASK_SIZE is the maximum virtual address space) - */ - -#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 - -/* zero page used for uninitialized stuff */ -#ifndef __ASSEMBLY__ -extern unsigned long empty_zero_page; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) -#endif - -/* number of bits that fit into a memory pointer */ -#define BITS_PER_PTR (8*sizeof(unsigned long)) - -/* to align the pointer to a pointer address */ -#define PTR_MASK (~(sizeof(void*)-1)) - -/* sizeof(void*)==1<>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) - -/* to set the page-dir */ -#define SET_PAGE_DIR(tsk,pgdir) - -#define pte_none(x) (!pte_val(x)) -#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) -#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) - -#define pmd_none(x) (!pmd_val(x)) -/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad - * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. - */ -#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) -#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) -#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) - -#ifndef __ASSEMBLY__ - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ - -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } -static inline int pte_special(pte_t pte) { return 0; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkold(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) |= _PAGE_WRITE; - if (pte_val(pte) & _PAGE_MODIFIED) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkdirty(pte_t pte) -{ - pte_val(pte) |= _PAGE_MODIFIED; - if (pte_val(pte) & _PAGE_WRITE) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - { - pte_val(pte) |= _PAGE_SILENT_READ; - if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == - (_PAGE_WRITE | _PAGE_MODIFIED)) - pte_val(pte) |= _PAGE_SILENT_WRITE; - } - return pte; -} -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ - -/* What actually goes as arguments to the various functions is less than - * obvious, but a rule of thumb is that struct page's goes as struct page *, - * really physical DRAM addresses are unsigned long's, and DRAM "virtual" - * addresses (the 0xc0xxxxxx's) goes as void *'s. - */ - -static inline pte_t __mk_pte(void * page, pgprot_t pgprot) -{ - pte_t pte; - /* the PTE needs a physical address */ - pte_val(pte) = __pa(page) | pgprot_val(pgprot); - return pte; -} - -#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) - -#define mk_pte_phys(physpage, pgprot) \ -({ \ - pte_t __pte; \ - \ - pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ - __pte; \ -}) - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } - - -/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval - * __pte_page(pte_val) refers to the "virtual" DRAM interval - * pte_pagenr refers to the page-number counted starting from the virtual DRAM start - */ - -static inline unsigned long __pte_page(pte_t pte) -{ - /* the PTE contains a physical address */ - return (unsigned long)__va(pte_val(pte) & PAGE_MASK); -} - -#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) - -/* permanent address of a page */ - -#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) -#define pte_page(pte) (mem_map+pte_pagenr(pte)) - -/* only the pte's themselves need to point to physical DRAM (see above) - * the pagetable links are purely handled within the kernel SW and thus - * don't need the __pa and __va transformations. - */ - -static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) -{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } - -#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) -#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) - -/* to find an entry in a page-table-directory. */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) - -/* to find an entry in a page-table-directory */ -static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address) -{ - return mm->pgd + pgd_index(address); -} - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) - -#define pte_unmap(pte) do { } while (0) -#define pte_unmap_nested(pte) do { } while (0) -#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) - - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ - -/* - * CRIS doesn't have any external MMU info: the kernel page - * tables contain all the necessary information. - * - * Actually I am not sure on what this could be used for. - */ -static inline void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ -} - -/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ -/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ - -#define __swp_type(x) (((x).val >> 5) & 0x7f) -#define __swp_offset(x) ((x).val >> 12) -#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -#define kern_addr_valid(addr) (1) - -#include - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -#define pte_to_pgoff(x) (pte_val(x) >> 6) -#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) - -typedef pte_t *pte_addr_t; - -#endif /* __ASSEMBLY__ */ -#endif /* _CRIS_PGTABLE_H */ diff --git a/include/asm-cris/poll.h b/include/asm-cris/poll.h deleted file mode 100644 index c98509d3149e..000000000000 --- a/include/asm-cris/poll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h deleted file mode 100644 index ce3fb25a460b..000000000000 --- a/include/asm-cris/posix_types.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ -/* I guess we should write these in assembler because they are used often. */ - -#ifndef __ARCH_CRIS_POSIX_TYPES_H -#define __ARCH_CRIS_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef __SIZE_TYPE__ __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#ifdef __KERNEL__ - -#undef __FD_SET -#define __FD_SET(fd,fdsetp) set_bit(fd, (void *)(fdsetp)) - -#undef __FD_CLR -#define __FD_CLR(fd,fdsetp) clear_bit(fd, (void *)(fdsetp)) - -#undef __FD_ISSET -#define __FD_ISSET(fd,fdsetp) test_bit(fd, (void *)(fdsetp)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) memset((void *)(fdsetp), 0, __FDSET_LONGS << 2) - -#endif /* __KERNEL__ */ - -#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h deleted file mode 100644 index cdc0c1dce6be..000000000000 --- a/include/asm-cris/processor.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * include/asm-cris/processor.h - * - * Copyright (C) 2000, 2001 Axis Communications AB - * - * Authors: Bjorn Wesen Initial version - * - */ - -#ifndef __ASM_CRIS_PROCESSOR_H -#define __ASM_CRIS_PROCESSOR_H - -#include -#include -#include -#include - -struct task_struct; - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) - -/* THREAD_SIZE is the size of the task_struct/kernel_stack combo. - * normally, the stack is found by doing something like p + THREAD_SIZE - * in CRIS, a page is 8192 bytes, which seems like a sane size - */ - -#define THREAD_SIZE PAGE_SIZE -#define KERNEL_STACK_SIZE PAGE_SIZE - -/* - * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. - * This macro allows us to find those regs for a task. - * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while - * we're in the kernel, won't affect this - only the first user->kernel transition - * registers are reached by this. - */ - -#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) - -/* - * Dito but for the currently running task - */ - -#define task_pt_regs(task) user_regs(task_thread_info(task)) -#define current_regs() task_pt_regs(current) - -static inline void prepare_to_copy(struct task_struct *tsk) -{ -} - -extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) - -extern unsigned long thread_saved_pc(struct task_struct *tsk); - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ - /* Nothing needs to be done. */ -} - -#define init_stack (init_thread_union.stack) - -#define cpu_relax() barrier() - -#endif /* __ASM_CRIS_PROCESSOR_H */ diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h deleted file mode 100644 index d910925e3174..000000000000 --- a/include/asm-cris/ptrace.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _CRIS_PTRACE_H -#define _CRIS_PTRACE_H - -#include - -#ifdef __KERNEL__ - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 - -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_PTRACE_H */ diff --git a/include/asm-cris/resource.h b/include/asm-cris/resource.h deleted file mode 100644 index b5d29448de4e..000000000000 --- a/include/asm-cris/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_RESOURCE_H -#define _CRIS_RESOURCE_H - -#include - -#endif diff --git a/include/asm-cris/rs485.h b/include/asm-cris/rs485.h deleted file mode 100644 index c331c51b0c2b..000000000000 --- a/include/asm-cris/rs485.h +++ /dev/null @@ -1,20 +0,0 @@ -/* RS-485 structures */ - -/* RS-485 support */ -/* Used with ioctl() TIOCSERSETRS485 */ -struct rs485_control { - unsigned short rts_on_send; - unsigned short rts_after_sent; - unsigned long delay_rts_before_send; - unsigned short enabled; -#ifdef __KERNEL__ - int disable_serial_loopback; -#endif -}; - -/* Used with ioctl() TIOCSERWRRS485 */ -struct rs485_write { - unsigned short outc_size; - unsigned char *outc; -}; - diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h deleted file mode 100644 index 17d3019529e1..000000000000 --- a/include/asm-cris/rtc.h +++ /dev/null @@ -1,107 +0,0 @@ - -#ifndef __RTC_H__ -#define __RTC_H__ - -#ifdef CONFIG_ETRAX_DS1302 - /* Dallas DS1302 clock/calendar register numbers. */ -# define RTC_SECONDS 0 -# define RTC_MINUTES 1 -# define RTC_HOURS 2 -# define RTC_DAY_OF_MONTH 3 -# define RTC_MONTH 4 -# define RTC_WEEKDAY 5 -# define RTC_YEAR 6 -# define RTC_CONTROL 7 - - /* Bits in CONTROL register. */ -# define RTC_CONTROL_WRITEPROTECT 0x80 -# define RTC_TRICKLECHARGER 8 - - /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ -# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ -# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ -# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ -# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ -# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ -# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ -# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ - -#elif defined(CONFIG_ETRAX_PCF8563) - /* I2C bus slave registers. */ -# define RTC_I2C_READ 0xa3 -# define RTC_I2C_WRITE 0xa2 - - /* Phillips PCF8563 registers. */ -# define RTC_CONTROL1 0x00 /* Control/Status register 1. */ -# define RTC_CONTROL2 0x01 /* Control/Status register 2. */ -# define RTC_CLOCKOUT_FREQ 0x0d /* CLKOUT frequency. */ -# define RTC_TIMER_CONTROL 0x0e /* Timer control. */ -# define RTC_TIMER_CNTDOWN 0x0f /* Timer countdown. */ - - /* BCD encoded clock registers. */ -# define RTC_SECONDS 0x02 -# define RTC_MINUTES 0x03 -# define RTC_HOURS 0x04 -# define RTC_DAY_OF_MONTH 0x05 -# define RTC_WEEKDAY 0x06 /* Not coded in BCD! */ -# define RTC_MONTH 0x07 -# define RTC_YEAR 0x08 -# define RTC_MINUTE_ALARM 0x09 -# define RTC_HOUR_ALARM 0x0a -# define RTC_DAY_ALARM 0x0b -# define RTC_WEEKDAY_ALARM 0x0c - -#endif - -#ifdef CONFIG_ETRAX_DS1302 -extern unsigned char ds1302_readreg(int reg); -extern void ds1302_writereg(int reg, unsigned char val); -extern int ds1302_init(void); -# define CMOS_READ(x) ds1302_readreg(x) -# define CMOS_WRITE(val,reg) ds1302_writereg(reg,val) -# define RTC_INIT() ds1302_init() -#elif defined(CONFIG_ETRAX_PCF8563) -extern unsigned char pcf8563_readreg(int reg); -extern void pcf8563_writereg(int reg, unsigned char val); -extern int pcf8563_init(void); -# define CMOS_READ(x) pcf8563_readreg(x) -# define CMOS_WRITE(val,reg) pcf8563_writereg(reg,val) -# define RTC_INIT() pcf8563_init() -#else - /* No RTC configured so we shouldn't try to access any. */ -# define CMOS_READ(x) 42 -# define CMOS_WRITE(x,y) -# define RTC_INIT() (-1) -#endif - -/* - * The struct used to pass data via the following ioctl. Similar to the - * struct tm in , but it needs to be here so that the kernel - * source is self contained, allowing cross-compiles, etc. etc. - */ -struct rtc_time { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; -}; - -/* ioctl() calls that are permitted to the /dev/rtc interface. */ -#define RTC_MAGIC 'p' -/* Read RTC time. */ -#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) -/* Set RTC time. */ -#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) -#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) -/* Voltage low detector */ -#define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int) -/* Clear voltage low information */ -#define RTC_VL_CLR _IO(RTC_MAGIC, 0x14) -#define RTC_MAX_IOCTL 0x14 - -#endif /* __RTC_H__ */ diff --git a/include/asm-cris/scatterlist.h b/include/asm-cris/scatterlist.h deleted file mode 100644 index faff53ad1f96..000000000000 --- a/include/asm-cris/scatterlist.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_CRIS_SCATTERLIST_H -#define __ASM_CRIS_SCATTERLIST_H - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - char * address; /* Location data is to be transferred to */ - unsigned int length; - - /* The following is i386 highmem junk - not used by us */ - unsigned long page_link; - unsigned int offset;/* for highmem, page offset */ - -}; - -#define sg_dma_address(sg) ((sg)->address) -#define sg_dma_len(sg) ((sg)->length) -/* i386 junk */ - -#define ISA_DMA_THRESHOLD (0x1fffffff) - -#endif /* !(__ASM_CRIS_SCATTERLIST_H) */ diff --git a/include/asm-cris/sections.h b/include/asm-cris/sections.h deleted file mode 100644 index 2c998ce8967b..000000000000 --- a/include/asm-cris/sections.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _CRIS_SECTIONS_H -#define _CRIS_SECTIONS_H - -/* nothing to see, move along */ -#include - -#endif diff --git a/include/asm-cris/segment.h b/include/asm-cris/segment.h deleted file mode 100644 index c067513beaaf..000000000000 --- a/include/asm-cris/segment.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#endif diff --git a/include/asm-cris/sembuf.h b/include/asm-cris/sembuf.h deleted file mode 100644 index 7fed9843796d..000000000000 --- a/include/asm-cris/sembuf.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _CRIS_SEMBUF_H -#define _CRIS_SEMBUF_H - -/* - * The semid64_ds structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _CRIS_SEMBUF_H */ diff --git a/include/asm-cris/setup.h b/include/asm-cris/setup.h deleted file mode 100644 index b90728652d1a..000000000000 --- a/include/asm-cris/setup.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_SETUP_H -#define _CRIS_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -#endif diff --git a/include/asm-cris/shmbuf.h b/include/asm-cris/shmbuf.h deleted file mode 100644 index 3239e3f000e8..000000000000 --- a/include/asm-cris/shmbuf.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _CRIS_SHMBUF_H -#define _CRIS_SHMBUF_H - -/* - * The shmid64_ds structure for CRIS architecture (same as for i386) - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _CRIS_SHMBUF_H */ diff --git a/include/asm-cris/shmparam.h b/include/asm-cris/shmparam.h deleted file mode 100644 index d29d12270687..000000000000 --- a/include/asm-cris/shmparam.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASM_CRIS_SHMPARAM_H -#define _ASM_CRIS_SHMPARAM_H - -/* same as asm-i386/ version.. */ - -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _ASM_CRIS_SHMPARAM_H */ diff --git a/include/asm-cris/sigcontext.h b/include/asm-cris/sigcontext.h deleted file mode 100644 index a1d634e120df..000000000000 --- a/include/asm-cris/sigcontext.h +++ /dev/null @@ -1,24 +0,0 @@ -/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef _ASM_CRIS_SIGCONTEXT_H -#define _ASM_CRIS_SIGCONTEXT_H - -#include - -/* This struct is saved by setup_frame in signal.c, to keep the current context while - a signal handler is executed. It's restored by sys_sigreturn. - - To keep things simple, we use pt_regs here even though normally you just specify - the list of regs to save. Then we can use copy_from_user on the entire regs instead - of a bunch of get_user's as well... - -*/ - -struct sigcontext { - struct pt_regs regs; /* needs to be first */ - unsigned long oldmask; - unsigned long usp; /* usp before stacking this gunk on it */ -}; - -#endif - diff --git a/include/asm-cris/siginfo.h b/include/asm-cris/siginfo.h deleted file mode 100644 index c1cd6d16928b..000000000000 --- a/include/asm-cris/siginfo.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_SIGINFO_H -#define _CRIS_SIGINFO_H - -#include - -#endif diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h deleted file mode 100644 index 349ae682b568..000000000000 --- a/include/asm-cris/signal.h +++ /dev/null @@ -1,163 +0,0 @@ -#ifndef _ASM_CRIS_SIGNAL_H -#define _ASM_CRIS_SIGNAL_H - -#include - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ - -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include - -#ifdef __KERNEL__ -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer)(void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ -#include - -/* here we could define asm-optimized sigaddset, sigdelset etc. operations. - * if we don't, generic ones are used from linux/signal.h - */ -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h deleted file mode 100644 index dba33aba3e95..000000000000 --- a/include/asm-cris/smp.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_SMP_H -#define __ASM_SMP_H - -#include - -extern cpumask_t phys_cpu_present_map; -extern cpumask_t cpu_possible_map; - -#define raw_smp_processor_id() (current_thread_info()->cpu) - -#endif diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h deleted file mode 100644 index 9df0ca82f5de..000000000000 --- a/include/asm-cris/socket.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -/* almost the same as asm-i386/socket.h */ - -#include - -/* For setsockoptions(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#endif /* _ASM_SOCKET_H */ - - diff --git a/include/asm-cris/sockios.h b/include/asm-cris/sockios.h deleted file mode 100644 index cfe7bfecf599..000000000000 --- a/include/asm-cris/sockios.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ARCH_CRIS_SOCKIOS__ -#define __ARCH_CRIS_SOCKIOS__ - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h deleted file mode 100644 index 2e8ba8afc7af..000000000000 --- a/include/asm-cris/spinlock.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-cris/stat.h b/include/asm-cris/stat.h deleted file mode 100644 index 9e558cc3c43b..000000000000 --- a/include/asm-cris/stat.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef _CRIS_STAT_H -#define _CRIS_STAT_H - -/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in - the kernel if necessary. */ - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -#define STAT_HAVE_NSEC 1 - -struct stat { - unsigned long st_dev; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned long st_rdev; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* future possible st_blocks high bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ - - unsigned long long st_ino; -}; - -#endif diff --git a/include/asm-cris/statfs.h b/include/asm-cris/statfs.h deleted file mode 100644 index fdaf921844bc..000000000000 --- a/include/asm-cris/statfs.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_STATFS_H -#define _CRIS_STATFS_H - -#include - -#endif diff --git a/include/asm-cris/string.h b/include/asm-cris/string.h deleted file mode 100644 index 691190e99a27..000000000000 --- a/include/asm-cris/string.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _ASM_CRIS_STRING_H -#define _ASM_CRIS_STRING_H - -/* the optimized memcpy is in arch/cris/lib/string.c */ - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *, const void *, size_t); - -/* New and improved. In arch/cris/lib/memset.c */ - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, size_t); - -#endif diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h deleted file mode 100644 index d87c24df2b38..000000000000 --- a/include/asm-cris/sync_serial.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * ioctl defines for synchronous serial port driver - * - * Copyright (c) 2001-2003 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef SYNC_SERIAL_H -#define SYNC_SERIAL_H - -#include - -#define SSP_SPEED _IOR('S', 0, unsigned int) -#define SSP_MODE _IOR('S', 1, unsigned int) -#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) -#define SSP_IPOLARITY _IOR('S', 3, unsigned int) -#define SSP_OPOLARITY _IOR('S', 4, unsigned int) -#define SSP_SPI _IOR('S', 5, unsigned int) -#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) - -/* Values for SSP_SPEED */ -#define SSP150 0 -#define SSP300 1 -#define SSP600 2 -#define SSP1200 3 -#define SSP2400 4 -#define SSP4800 5 -#define SSP9600 6 -#define SSP19200 7 -#define SSP28800 8 -#define SSP57600 9 -#define SSP115200 10 -#define SSP230400 11 -#define SSP460800 12 -#define SSP921600 13 -#define SSP3125000 14 -#define CODEC 15 - -#define FREQ_4MHz 0 -#define FREQ_2MHz 1 -#define FREQ_1MHz 2 -#define FREQ_512kHz 3 -#define FREQ_256kHz 4 -#define FREQ_128kHz 5 -#define FREQ_64kHz 6 -#define FREQ_32kHz 7 - -/* Used by application to set CODEC divider, word rate and frame rate */ -#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28)) - -/* Used by driver to extract speed */ -#define GET_SPEED(x) (x & 0xff) -#define GET_FREQ(x) ((x & 0xff00) >> 8) -#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) -#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) - -/* Values for SSP_MODE */ -#define MASTER_OUTPUT 0 -#define SLAVE_OUTPUT 1 -#define MASTER_INPUT 2 -#define SLAVE_INPUT 3 -#define MASTER_BIDIR 4 -#define SLAVE_BIDIR 5 - -/* Values for SSP_FRAME_SYNC */ -#define NORMAL_SYNC 1 -#define EARLY_SYNC 2 -#define SECOND_WORD_SYNC 0x40000 - -#define BIT_SYNC 4 -#define WORD_SYNC 8 -#define EXTENDED_SYNC 0x10 - -#define SYNC_OFF 0x20 -#define SYNC_ON 0x40 -#define WORD_SIZE_8 0x80 -#define WORD_SIZE_12 0x100 -#define WORD_SIZE_16 0x200 -#define WORD_SIZE_24 0x400 -#define WORD_SIZE_32 0x800 -#define BIT_ORDER_LSB 0x1000 -#define BIT_ORDER_MSB 0x2000 -#define FLOW_CONTROL_ENABLE 0x4000 -#define FLOW_CONTROL_DISABLE 0x8000 -#define CLOCK_GATED 0x10000 -#define CLOCK_NOT_GATED 0x20000 - -/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ -#define CLOCK_NORMAL 1 -#define CLOCK_INVERT 2 -#define CLOCK_INEGEDGE CLOCK_NORMAL -#define CLOCK_IPOSEDGE CLOCK_INVERT -#define FRAME_NORMAL 4 -#define FRAME_INVERT 8 -#define STATUS_NORMAL 0x10 -#define STATUS_INVERT 0x20 - -/* Values for SSP_SPI */ -#define SPI_MASTER 0 -#define SPI_SLAVE 1 - -/* Values for SSP_INBUFCHUNK */ -/* plain integer with the size of DMA chunks */ - -#endif diff --git a/include/asm-cris/system.h b/include/asm-cris/system.h deleted file mode 100644 index 5bcfe5a10907..000000000000 --- a/include/asm-cris/system.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef __ASM_CRIS_SYSTEM_H -#define __ASM_CRIS_SYSTEM_H - -#include - -/* the switch_to macro calls resume, an asm function in entry.S which does the actual - * task switching. - */ - -extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); -#define switch_to(prev,next,last) last = resume(prev,next, \ - (int)&((struct task_struct *)0)->thread) - -#define barrier() __asm__ __volatile__("": : :"memory") -#define mb() barrier() -#define rmb() mb() -#define wmb() mb() -#define read_barrier_depends() do { } while(0) -#define set_mb(var, value) do { var = value; mb(); } while (0) - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif - -#define iret() - -/* - * disable hlt during certain critical i/o operations - */ -#define HAVE_DISABLE_HLT -void disable_hlt(void); -void enable_hlt(void); - -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - /* since Etrax doesn't have any atomic xchg instructions, we need to disable - irq's (if enabled) and do it with move.d's */ - unsigned long flags,temp; - local_irq_save(flags); /* save flags, including irq enable bit and shut off irqs */ - switch (size) { - case 1: - *((unsigned char *)&temp) = x; - x = *(unsigned char *)ptr; - *(unsigned char *)ptr = *((unsigned char *)&temp); - break; - case 2: - *((unsigned short *)&temp) = x; - x = *(unsigned short *)ptr; - *(unsigned short *)ptr = *((unsigned short *)&temp); - break; - case 4: - temp = x; - x = *(unsigned long *)ptr; - *(unsigned long *)ptr = temp; - break; - } - local_irq_restore(flags); /* restore irq enable bit */ - return x; -} - -#include - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#ifndef CONFIG_SMP -#include -#endif - -#define arch_align_stack(x) (x) - -void default_idle(void); - -#endif diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h deleted file mode 100644 index 66e1a7492a0c..000000000000 --- a/include/asm-cris/termbits.h +++ /dev/null @@ -1,234 +0,0 @@ -/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef __ARCH_ETRAX100_TERMBITS_H__ -#define __ARCH_ETRAX100_TERMBITS_H__ - -#include - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -/* - * 3 2 1 - * 10 987 654 321 098 765 432 109 876 543 210 - * | | ||| CBAUD - * obaud - * - * ||CSIZE - * - * |CSTOP - * |CREAD - * |CPARENB - * - * |CPARODD - * |HUPCL - * |CLOCAL - * |CBAUDEX - * 10 987 654 321 098 765 432 109 876 543 210 - * | || || CIBAUD, IBSHIFT=16 - * ibaud - * |CMSPAR - * | CRTSCTS - * x x xxx xxx x x xx Free bits - */ - -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 - -/* Unsupported rates, but needed to avoid compile error. */ -#define B500000 0010005 -#define B576000 0010006 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 - -/* etrax supports these additional three baud rates */ -#define B921600 0010005 -#define B1843200 0010006 -#define B6250000 0010007 -/* ETRAX FS supports this as well */ -#define B12500000 0010010 -#define CIBAUD 002003600000 /* input baud rate (used in v32) */ -/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX - * shifted left IBSHIFT bits. - */ -#define IBSHIFT 16 -#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ -#define CRTSCTS 020000000000 /* flow control */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif diff --git a/include/asm-cris/termios.h b/include/asm-cris/termios.h deleted file mode 100644 index b0124e6c2e41..000000000000 --- a/include/asm-cris/termios.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef _CRIS_TERMIOS_H -#define _CRIS_TERMIOS_H - -#include -#include -#include - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - -#ifdef __KERNEL__ - -/* intr=^C quit=^\ erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp,&(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_TERMIOS_H */ diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h deleted file mode 100644 index cee97f14af3b..000000000000 --- a/include/asm-cris/thread_info.h +++ /dev/null @@ -1,106 +0,0 @@ -/* thread_info.h: CRIS low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - * - * CRIS port by Axis Communications - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR - -#ifndef __ASSEMBLY__ -#include -#include -#include -#include -#endif - - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, the assembly constants must also be changed - */ -#ifndef __ASSEMBLY__ -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ - __u32 cpu; /* current CPU */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - __u32 tls; /* TLS for this thread */ - - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ - struct restart_block restart_block; - __u8 supervisor_stack[0]; -}; - -#endif - -#define PREEMPT_ACTIVE 0x10000000 - -/* - * macros/functions for gaining access to the thread information structure - * - * preempt_count needs to be 1 initially, until the scheduler is functional. - */ -#ifndef __ASSEMBLY__ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) - -/* thread information allocation */ -#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) -#define free_thread_info(ti) free_pages((unsigned long) (ti), 1) - -#endif /* !__ASSEMBLY__ */ - -/* - * thread information flags - * - these are process state flags that various assembly files may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ -#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 17 -#define TIF_FREEZE 18 /* is freezing for suspend */ - -#define _TIF_SYSCALL_TRACE (1< - -/* - * We don't have a cycle-counter.. but we do not support SMP anyway where this is - * used so it does not matter. - */ - -typedef unsigned long long cycles_t; - -static inline cycles_t get_cycles(void) -{ - return 0; -} - -#endif diff --git a/include/asm-cris/tlb.h b/include/asm-cris/tlb.h deleted file mode 100644 index 7724246a2601..000000000000 --- a/include/asm-cris/tlb.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _CRIS_TLB_H -#define _CRIS_TLB_H - -#include - -#include - -/* - * cris doesn't need any special per-pte or - * per-vma handling.. - */ -#define tlb_start_vma(tlb, vma) do { } while (0) -#define tlb_end_vma(tlb, vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) - -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) -#include - -#endif diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h deleted file mode 100644 index 20697e7ef4f2..000000000000 --- a/include/asm-cris/tlbflush.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _CRIS_TLBFLUSH_H -#define _CRIS_TLBFLUSH_H - -#include -#include -#include -#include - -/* - * TLB flushing (implemented in arch/cris/mm/tlb.c): - * - * - flush_tlb() flushes the current mm struct TLBs - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(mm, start, end) flushes a range of pages - * - */ - -extern void __flush_tlb_all(void); -extern void __flush_tlb_mm(struct mm_struct *mm); -extern void __flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr); - -#ifdef CONFIG_SMP -extern void flush_tlb_all(void); -extern void flush_tlb_mm(struct mm_struct *mm); -extern void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr); -#else -#define flush_tlb_all __flush_tlb_all -#define flush_tlb_mm __flush_tlb_mm -#define flush_tlb_page __flush_tlb_page -#endif - -static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} - -static inline void flush_tlb(void) -{ - flush_tlb_mm(current->mm); -} - -#define flush_tlb_kernel_range(start, end) flush_tlb_all() - -#endif /* _CRIS_TLBFLUSH_H */ diff --git a/include/asm-cris/topology.h b/include/asm-cris/topology.h deleted file mode 100644 index 2ac613d32a89..000000000000 --- a/include/asm-cris/topology.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_CRIS_TOPOLOGY_H -#define _ASM_CRIS_TOPOLOGY_H - -#include - -#endif /* _ASM_CRIS_TOPOLOGY_H */ diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h deleted file mode 100644 index 5790262cbe8a..000000000000 --- a/include/asm-cris/types.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ETRAX_TYPES_H -#define _ETRAX_TYPES_H - -#include - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide, just like our other addresses. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/uaccess.h b/include/asm-cris/uaccess.h deleted file mode 100644 index ea11eaf0e922..000000000000 --- a/include/asm-cris/uaccess.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * Authors: Bjorn Wesen (bjornw@axis.com) - * Hans-Peter Nilsson (hp@axis.com) - */ - -/* Asm:s have been tweaked (within the domain of correctness) to give - satisfactory results for "gcc version 2.96 20000427 (experimental)". - - Check regularly... - - Register $r9 is chosen for temporaries, being a call-clobbered register - first in line to be used (notably for local blocks), not colliding with - parameter registers. */ - -#ifndef _CRIS_UACCESS_H -#define _CRIS_UACCESS_H - -#ifndef __ASSEMBLY__ -#include -#include -#include -#include - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -/* addr_limit is the maximum accessible address for the task. we misuse - * the KERNEL_DS and USER_DS values to both assign and compare the - * addr_limit values through the equally misnamed get/set_fs macros. - * (see above) - */ - -#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) -#define USER_DS MAKE_MM_SEG(TASK_SIZE) - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define segment_eq(a,b) ((a).seg == (b).seg) - -#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) -#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size))) -#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size))) -#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size)) - -#include - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -/* - * These are the main single-value transfer routines. They automatically - * use the right size if we just have the right pointer type. - * - * This gets kind of ugly. We want to return _two_ values in "get_user()" - * and yet we don't want to do any pointers, because that is too much - * of a performance impact. Thus we have a few rather ugly macros here, - * and hide all the ugliness from the user. - * - * The "__xxx" versions of the user access functions are versions that - * do not verify the address space, that must have been done previously - * with a separate "access_ok()" call (this is used when we do multiple - * accesses to the same area of user memory). - * - * As we use the same address space for kernel and user data on - * CRIS, we can just do these as direct assignments. (Of course, the - * exception handling means that it's no longer "just"...) - */ -#define get_user(x,ptr) \ - __get_user_check((x),(ptr),sizeof(*(ptr))) -#define put_user(x,ptr) \ - __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) - -#define __get_user(x,ptr) \ - __get_user_nocheck((x),(ptr),sizeof(*(ptr))) -#define __put_user(x,ptr) \ - __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) - -extern long __put_user_bad(void); - -#define __put_user_size(x,ptr,size,retval) \ -do { \ - retval = 0; \ - switch (size) { \ - case 1: __put_user_asm(x,ptr,retval,"move.b"); break; \ - case 2: __put_user_asm(x,ptr,retval,"move.w"); break; \ - case 4: __put_user_asm(x,ptr,retval,"move.d"); break; \ - case 8: __put_user_asm_64(x,ptr,retval); break; \ - default: __put_user_bad(); \ - } \ -} while (0) - -#define __get_user_size(x,ptr,size,retval) \ -do { \ - retval = 0; \ - switch (size) { \ - case 1: __get_user_asm(x,ptr,retval,"move.b"); break; \ - case 2: __get_user_asm(x,ptr,retval,"move.w"); break; \ - case 4: __get_user_asm(x,ptr,retval,"move.d"); break; \ - case 8: __get_user_asm_64(x,ptr,retval); break; \ - default: (x) = __get_user_bad(); \ - } \ -} while (0) - -#define __put_user_nocheck(x,ptr,size) \ -({ \ - long __pu_err; \ - __put_user_size((x),(ptr),(size),__pu_err); \ - __pu_err; \ -}) - -#define __put_user_check(x,ptr,size) \ -({ \ - long __pu_err = -EFAULT; \ - __typeof__(*(ptr)) *__pu_addr = (ptr); \ - if (access_ok(VERIFY_WRITE,__pu_addr,size)) \ - __put_user_size((x),__pu_addr,(size),__pu_err); \ - __pu_err; \ -}) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) - - - -#define __get_user_nocheck(x,ptr,size) \ -({ \ - long __gu_err, __gu_val; \ - __get_user_size(__gu_val,(ptr),(size),__gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -#define __get_user_check(x,ptr,size) \ -({ \ - long __gu_err = -EFAULT, __gu_val = 0; \ - const __typeof__(*(ptr)) *__gu_addr = (ptr); \ - if (access_ok(VERIFY_READ,__gu_addr,size)) \ - __get_user_size(__gu_val,__gu_addr,(size),__gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -extern long __get_user_bad(void); - -/* More complex functions. Most are inline, but some call functions that - live in lib/usercopy.c */ - -extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __copy_user_zeroing(void *to, const void __user *from, unsigned long n); -extern unsigned long __do_clear_user(void __user *to, unsigned long n); - -static inline unsigned long -__generic_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - return __copy_user(to,from,n); - return n; -} - -static inline unsigned long -__generic_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - if (access_ok(VERIFY_READ, from, n)) - return __copy_user_zeroing(to,from,n); - return n; -} - -static inline unsigned long -__generic_clear_user(void __user *to, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - return __do_clear_user(to,n); - return n; -} - -static inline long -__strncpy_from_user(char *dst, const char __user *src, long count) -{ - return __do_strncpy_from_user(dst, src, count); -} - -static inline long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - res = __do_strncpy_from_user(dst, src, count); - return res; -} - - -/* Note that these expand awfully if made into switch constructs, so - don't do that. */ - -static inline unsigned long -__constant_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - unsigned long ret = 0; - if (n == 0) - ; - else if (n == 1) - __asm_copy_from_user_1(to, from, ret); - else if (n == 2) - __asm_copy_from_user_2(to, from, ret); - else if (n == 3) - __asm_copy_from_user_3(to, from, ret); - else if (n == 4) - __asm_copy_from_user_4(to, from, ret); - else if (n == 5) - __asm_copy_from_user_5(to, from, ret); - else if (n == 6) - __asm_copy_from_user_6(to, from, ret); - else if (n == 7) - __asm_copy_from_user_7(to, from, ret); - else if (n == 8) - __asm_copy_from_user_8(to, from, ret); - else if (n == 9) - __asm_copy_from_user_9(to, from, ret); - else if (n == 10) - __asm_copy_from_user_10(to, from, ret); - else if (n == 11) - __asm_copy_from_user_11(to, from, ret); - else if (n == 12) - __asm_copy_from_user_12(to, from, ret); - else if (n == 13) - __asm_copy_from_user_13(to, from, ret); - else if (n == 14) - __asm_copy_from_user_14(to, from, ret); - else if (n == 15) - __asm_copy_from_user_15(to, from, ret); - else if (n == 16) - __asm_copy_from_user_16(to, from, ret); - else if (n == 20) - __asm_copy_from_user_20(to, from, ret); - else if (n == 24) - __asm_copy_from_user_24(to, from, ret); - else - ret = __generic_copy_from_user(to, from, n); - - return ret; -} - -/* Ditto, don't make a switch out of this. */ - -static inline unsigned long -__constant_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - unsigned long ret = 0; - if (n == 0) - ; - else if (n == 1) - __asm_copy_to_user_1(to, from, ret); - else if (n == 2) - __asm_copy_to_user_2(to, from, ret); - else if (n == 3) - __asm_copy_to_user_3(to, from, ret); - else if (n == 4) - __asm_copy_to_user_4(to, from, ret); - else if (n == 5) - __asm_copy_to_user_5(to, from, ret); - else if (n == 6) - __asm_copy_to_user_6(to, from, ret); - else if (n == 7) - __asm_copy_to_user_7(to, from, ret); - else if (n == 8) - __asm_copy_to_user_8(to, from, ret); - else if (n == 9) - __asm_copy_to_user_9(to, from, ret); - else if (n == 10) - __asm_copy_to_user_10(to, from, ret); - else if (n == 11) - __asm_copy_to_user_11(to, from, ret); - else if (n == 12) - __asm_copy_to_user_12(to, from, ret); - else if (n == 13) - __asm_copy_to_user_13(to, from, ret); - else if (n == 14) - __asm_copy_to_user_14(to, from, ret); - else if (n == 15) - __asm_copy_to_user_15(to, from, ret); - else if (n == 16) - __asm_copy_to_user_16(to, from, ret); - else if (n == 20) - __asm_copy_to_user_20(to, from, ret); - else if (n == 24) - __asm_copy_to_user_24(to, from, ret); - else - ret = __generic_copy_to_user(to, from, n); - - return ret; -} - -/* No switch, please. */ - -static inline unsigned long -__constant_clear_user(void __user *to, unsigned long n) -{ - unsigned long ret = 0; - if (n == 0) - ; - else if (n == 1) - __asm_clear_1(to, ret); - else if (n == 2) - __asm_clear_2(to, ret); - else if (n == 3) - __asm_clear_3(to, ret); - else if (n == 4) - __asm_clear_4(to, ret); - else if (n == 8) - __asm_clear_8(to, ret); - else if (n == 12) - __asm_clear_12(to, ret); - else if (n == 16) - __asm_clear_16(to, ret); - else if (n == 20) - __asm_clear_20(to, ret); - else if (n == 24) - __asm_clear_24(to, ret); - else - ret = __generic_clear_user(to, n); - - return ret; -} - - -#define clear_user(to, n) \ -(__builtin_constant_p(n) ? \ - __constant_clear_user(to, n) : \ - __generic_clear_user(to, n)) - -#define copy_from_user(to, from, n) \ -(__builtin_constant_p(n) ? \ - __constant_copy_from_user(to, from, n) : \ - __generic_copy_from_user(to, from, n)) - -#define copy_to_user(to, from, n) \ -(__builtin_constant_p(n) ? \ - __constant_copy_to_user(to, from, n) : \ - __generic_copy_to_user(to, from, n)) - -/* We let the __ versions of copy_from/to_user inline, because they're often - * used in fast paths and have only a small space overhead. - */ - -static inline unsigned long -__generic_copy_from_user_nocheck(void *to, const void __user *from, - unsigned long n) -{ - return __copy_user_zeroing(to,from,n); -} - -static inline unsigned long -__generic_copy_to_user_nocheck(void __user *to, const void *from, - unsigned long n) -{ - return __copy_user(to,from,n); -} - -static inline unsigned long -__generic_clear_user_nocheck(void __user *to, unsigned long n) -{ - return __do_clear_user(to,n); -} - -/* without checking */ - -#define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n)) -#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n)) -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user -#define __clear_user(to,n) __generic_clear_user_nocheck((to),(n)) - -#define strlen_user(str) strnlen_user((str), 0x7ffffffe) - -#endif /* __ASSEMBLY__ */ - -#endif /* _CRIS_UACCESS_H */ diff --git a/include/asm-cris/ucontext.h b/include/asm-cris/ucontext.h deleted file mode 100644 index eed6ad5eb3f2..000000000000 --- a/include/asm-cris/ucontext.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_CRIS_UCONTEXT_H -#define _ASM_CRIS_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* !_ASM_CRIS_UCONTEXT_H */ diff --git a/include/asm-cris/unaligned.h b/include/asm-cris/unaligned.h deleted file mode 100644 index 7b3f3fec567c..000000000000 --- a/include/asm-cris/unaligned.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_CRIS_UNALIGNED_H -#define _ASM_CRIS_UNALIGNED_H - -/* - * CRIS can do unaligned accesses itself. - */ -#include -#include - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_CRIS_UNALIGNED_H */ diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h deleted file mode 100644 index 76398ef87e9b..000000000000 --- a/include/asm-cris/unistd.h +++ /dev/null @@ -1,374 +0,0 @@ -#ifndef _ASM_CRIS_UNISTD_H_ -#define _ASM_CRIS_UNISTD_H_ - -/* - * This file contains the system call numbers, and stub macros for libc. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_chown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_lchown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_chown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_mincore 218 -#define __NR_madvise 219 -#define __NR_getdents64 220 -#define __NR_fcntl64 221 -/* 223 is unused */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 -#define __NR_set_thread_area 243 -#define __NR_get_thread_area 244 -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 -#define __NR_fadvise64 250 -/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_epoll_create 254 -#define __NR_epoll_ctl 255 -#define __NR_epoll_wait 256 -#define __NR_remap_file_pages 257 -#define __NR_set_tid_address 258 -#define __NR_timer_create 259 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) -#define __NR_statfs64 268 -#define __NR_fstatfs64 269 -#define __NR_tgkill 270 -#define __NR_utimes 271 -#define __NR_fadvise64_64 272 -#define __NR_vserver 273 -#define __NR_mbind 274 -#define __NR_get_mempolicy 275 -#define __NR_set_mempolicy 276 -#define __NR_mq_open 277 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_kexec_load 283 -#define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 -#define __NR_migrate_pages 294 -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 -#define __NR_set_robust_list 311 -#define __NR_get_robust_list 312 -#define __NR_splice 313 -#define __NR_sync_file_range 314 -#define __NR_tee 315 -#define __NR_vmsplice 316 -#define __NR_move_pages 317 -#define __NR_getcpu 318 -#define __NR_epoll_pwait 319 -#define __NR_utimensat 320 -#define __NR_signalfd 321 -#define __NR_timerfd_create 322 -#define __NR_eventfd 323 -#define __NR_fallocate 324 -#define __NR_timerfd_settime 325 -#define __NR_timerfd_gettime 326 - -#ifdef __KERNEL__ - -#define NR_syscalls 327 - -#include - -#define __ARCH_WANT_IPC_PARSE_VERSION -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_OLD_STAT -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SGETMASK -#define __ARCH_WANT_SYS_SIGNAL -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_WAITPID -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_RT_SIGACTION -#define __ARCH_WANT_SYS_RT_SIGSUSPEND - -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") - -#endif /* __KERNEL__ */ -#endif /* _ASM_CRIS_UNISTD_H_ */ diff --git a/include/asm-cris/user.h b/include/asm-cris/user.h deleted file mode 100644 index 73e60fcbcf38..000000000000 --- a/include/asm-cris/user.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef __ASM_CRIS_USER_H -#define __ASM_CRIS_USER_H - -#include -#include -#include -#include - -/* - * Core file format: The core file is written in such a way that gdb - * can understand it and provide useful information to the user (under - * linux we use the `trad-core' bfd). The file contents are as follows: - * - * upage: 1 page consisting of a user struct that tells gdb - * what is present in the file. Directly after this is a - * copy of the task_struct, which is currently not used by gdb, - * but it may come in handy at some point. All of the registers - * are stored as part of the upage. The upage should always be - * only one page long. - * data: The data segment follows next. We use current->end_text to - * current->brk to pick up all of the user variables, plus any memory - * that may have been sbrk'ed. No attempt is made to determine if a - * page is demand-zero or if a page is totally unused, we just cover - * the entire range. All of the addresses are rounded in such a way - * that an integral number of pages is written. - * stack: We need the stack information in order to get a meaningful - * backtrace. We need to write the data from usp to - * current->start_stack, so we round each of these in order to be able - * to write an integer number of pages. - */ - -struct user { - struct user_regs_struct regs; /* entire machine state */ - size_t u_tsize; /* text size (pages) */ - size_t u_dsize; /* data size (pages) */ - size_t u_ssize; /* stack size (pages) */ - unsigned long start_code; /* text starting address */ - unsigned long start_data; /* data starting address */ - unsigned long start_stack; /* stack starting address */ - long int signal; /* signal causing core dump */ - unsigned long u_ar0; /* help gdb find registers */ - unsigned long magic; /* identifies a core file */ - char u_comm[32]; /* user command name */ -}; - -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_DATA_START_ADDR (u.start_data) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif /* __ASM_CRIS_USER_H */ diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h index 4ec0a296bdec..7abdaa91ccd3 100644 --- a/include/asm-generic/atomic.h +++ b/include/asm-generic/atomic.h @@ -251,7 +251,7 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) #define atomic_long_cmpxchg(l, old, new) \ (atomic_cmpxchg((atomic_t *)(l), (old), (new))) #define atomic_long_xchg(v, new) \ - (atomic_xchg((atomic_t *)(l), (new))) + (atomic_xchg((atomic_t *)(v), (new))) #endif /* BITS_PER_LONG == 64 */ diff --git a/include/asm-generic/audit_write.h b/include/asm-generic/audit_write.h index f10d367fb2a5..c5f1c2c920e2 100644 --- a/include/asm-generic/audit_write.h +++ b/include/asm-generic/audit_write.h @@ -1,6 +1,8 @@ #include __NR_acct, +#ifdef __NR_swapon __NR_swapon, +#endif __NR_quotactl, __NR_truncate, #ifdef __NR_truncate64 diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h index 12c07c1866b2..4c794d73fb84 100644 --- a/include/asm-generic/bug.h +++ b/include/asm-generic/bug.h @@ -8,9 +8,17 @@ #ifdef CONFIG_GENERIC_BUG #ifndef __ASSEMBLY__ struct bug_entry { +#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS unsigned long bug_addr; +#else + signed int bug_addr_disp; +#endif #ifdef CONFIG_DEBUG_BUGVERBOSE +#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS const char *file; +#else + signed int file_disp; +#endif unsigned short line; #endif unsigned short flags; diff --git a/include/asm-generic/kdebug.h b/include/asm-generic/kdebug.h index 2b799c90b2d4..11e57b6a85fc 100644 --- a/include/asm-generic/kdebug.h +++ b/include/asm-generic/kdebug.h @@ -3,6 +3,7 @@ enum die_val { DIE_UNUSED, + DIE_OOPS=1 }; #endif /* _ASM_GENERIC_KDEBUG_H */ diff --git a/include/asm-generic/memory_model.h b/include/asm-generic/memory_model.h index ae060c62aff1..18546d8eb78e 100644 --- a/include/asm-generic/memory_model.h +++ b/include/asm-generic/memory_model.h @@ -34,7 +34,7 @@ #define __pfn_to_page(pfn) \ ({ unsigned long __pfn = (pfn); \ - unsigned long __nid = arch_pfn_to_nid(pfn); \ + unsigned long __nid = arch_pfn_to_nid(__pfn); \ NODE_DATA(__nid)->node_mem_map + arch_local_page_offset(__pfn, __nid);\ }) diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index ef87f889ef62..72ebe91005a8 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -129,6 +129,10 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres #define move_pte(pte, prot, old_addr, new_addr) (pte) #endif +#ifndef pgprot_writecombine +#define pgprot_writecombine pgprot_noncached +#endif + /* * When walking page tables, get the address of the next boundary, * or the end address of the range if that comes earlier. Although no @@ -289,6 +293,52 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm, #define arch_flush_lazy_cpu_mode() do {} while (0) #endif +#ifndef __HAVE_PFNMAP_TRACKING +/* + * Interface that can be used by architecture code to keep track of + * memory type of pfn mappings (remap_pfn_range, vm_insert_pfn) + * + * track_pfn_vma_new is called when a _new_ pfn mapping is being established + * for physical range indicated by pfn and size. + */ +static inline int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot, + unsigned long pfn, unsigned long size) +{ + return 0; +} + +/* + * Interface that can be used by architecture code to keep track of + * memory type of pfn mappings (remap_pfn_range, vm_insert_pfn) + * + * track_pfn_vma_copy is called when vma that is covering the pfnmap gets + * copied through copy_page_range(). + */ +static inline int track_pfn_vma_copy(struct vm_area_struct *vma) +{ + return 0; +} + +/* + * Interface that can be used by architecture code to keep track of + * memory type of pfn mappings (remap_pfn_range, vm_insert_pfn) + * + * untrack_pfn_vma is called while unmapping a pfnmap for a region. + * untrack can be called for a specific region indicated by pfn and size or + * can be for the entire vma (in which case size can be zero). + */ +static inline void untrack_pfn_vma(struct vm_area_struct *vma, + unsigned long pfn, unsigned long size) +{ +} +#else +extern int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot, + unsigned long pfn, unsigned long size); +extern int track_pfn_vma_copy(struct vm_area_struct *vma); +extern void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn, + unsigned long size); +#endif + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_GENERIC_PGTABLE_H */ diff --git a/include/asm-mn10300/uaccess.h b/include/asm-mn10300/uaccess.h index 46b9b647f3c3..8a3a4dd55763 100644 --- a/include/asm-mn10300/uaccess.h +++ b/include/asm-mn10300/uaccess.h @@ -266,7 +266,7 @@ extern int __get_user_unknown(void); " .section .fixup,\"ax\" \n" \ "4: \n" \ " mov %5,%0 \n" \ - " jmp 2b \n" \ + " jmp 3b \n" \ " .previous \n" \ " .section __ex_table,\"a\"\n" \ " .balign 4 \n" \ diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 59c796b46ee7..d5e8e5c89548 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -861,8 +861,6 @@ struct drm_device { struct timer_list vblank_disable_timer; u32 max_vblank_count; /**< size of vblank counter register */ - spinlock_t tasklet_lock; /**< For drm_locked_tasklet */ - void (*locked_tasklet_func)(struct drm_device *dev); /*@} */ cycles_t ctx_start; @@ -1149,16 +1147,14 @@ extern int drm_vblank_init(struct drm_device *dev, int num_crtcs); extern int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *filp); extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq); -extern void drm_locked_tasklet(struct drm_device *dev, - void(*func)(struct drm_device *)); extern u32 drm_vblank_count(struct drm_device *dev, int crtc); extern void drm_handle_vblank(struct drm_device *dev, int crtc); extern int drm_vblank_get(struct drm_device *dev, int crtc); extern void drm_vblank_put(struct drm_device *dev, int crtc); +extern void drm_vblank_cleanup(struct drm_device *dev); /* Modesetting support */ extern int drm_modeset_ctl(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*)); /* AGP/GART support (drm_agpsupport.h) */ extern struct drm_agp_head *drm_agp_init(struct drm_device *dev); diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index da04109741e8..5165f240aa68 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -395,27 +395,27 @@ {0, 0, 0} #define i915_PCI_IDS \ - {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ - {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ + {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0, 0, 0} diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index eb4b35031a55..152b34da927c 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -159,6 +159,7 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_SW_FINISH 0x20 #define DRM_I915_GEM_SET_TILING 0x21 #define DRM_I915_GEM_GET_TILING 0x22 +#define DRM_I915_GEM_GET_APERTURE 0x23 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -190,6 +191,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) +#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -600,4 +602,15 @@ struct drm_i915_gem_get_tiling { uint32_t swizzle_mode; }; +struct drm_i915_gem_get_aperture { + /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ + uint64_t aper_size; + + /** + * Available space in the aperture used by i915_gem_execbuffer, in + * bytes + */ + uint64_t aper_available_size; +}; + #endif /* _I915_DRM_H_ */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index fd6a452b0ceb..fba8051fb297 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -163,8 +163,6 @@ struct acpi_pci_driver { int acpi_pci_register_driver(struct acpi_pci_driver *driver); void acpi_pci_unregister_driver(struct acpi_pci_driver *driver); -#ifdef CONFIG_ACPI_EC - extern int ec_read(u8 addr, u8 *val); extern int ec_write(u8 addr, u8 val); extern int ec_transaction(u8 command, @@ -172,8 +170,6 @@ extern int ec_transaction(u8 command, u8 *rdata, unsigned rdata_len, int force_poll); -#endif /*CONFIG_ACPI_EC*/ - #if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE) typedef void (*wmi_notify_handler) (u32 value, void *context); @@ -194,6 +190,50 @@ extern bool wmi_has_guid(const char *guid); #endif /* CONFIG_ACPI_WMI */ +#define ACPI_VIDEO_OUTPUT_SWITCHING 0x0001 +#define ACPI_VIDEO_DEVICE_POSTING 0x0002 +#define ACPI_VIDEO_ROM_AVAILABLE 0x0004 +#define ACPI_VIDEO_BACKLIGHT 0x0008 +#define ACPI_VIDEO_BACKLIGHT_FORCE_VENDOR 0x0010 +#define ACPI_VIDEO_BACKLIGHT_FORCE_VIDEO 0x0020 +#define ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VENDOR 0x0040 +#define ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO 0x0080 +#define ACPI_VIDEO_BACKLIGHT_DMI_VENDOR 0x0100 +#define ACPI_VIDEO_BACKLIGHT_DMI_VIDEO 0x0200 +#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR 0x0400 +#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO 0x0800 + +#if defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE) + +extern long acpi_video_get_capabilities(acpi_handle graphics_dev_handle); +extern long acpi_is_video_device(struct acpi_device *device); +extern int acpi_video_backlight_support(void); +extern int acpi_video_display_switch_support(void); + +#else + +static inline long acpi_video_get_capabilities(acpi_handle graphics_dev_handle) +{ + return 0; +} + +static inline long acpi_is_video_device(struct acpi_device *device) +{ + return 0; +} + +static inline int acpi_video_backlight_support(void) +{ + return 0; +} + +static inline int acpi_video_display_switch_support(void) +{ + return 0; +} + +#endif /* defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE) */ + extern int acpi_blacklisted(void); #ifdef CONFIG_DMI extern void acpi_dmi_osi_linux(int enable, const struct dmi_system_id *d); diff --git a/include/linux/audit.h b/include/linux/audit.h index 6272a395d43c..8f0672d13eb1 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -391,6 +391,7 @@ extern int audit_classify_arch(int arch); #ifdef CONFIG_AUDITSYSCALL /* These are defined in auditsc.c */ /* Public API */ +extern void audit_finish_fork(struct task_struct *child); extern int audit_alloc(struct task_struct *task); extern void audit_free(struct task_struct *task); extern void audit_syscall_entry(int arch, @@ -434,7 +435,7 @@ static inline void audit_ptrace(struct task_struct *t) /* Private API (for audit.c only) */ extern unsigned int audit_serial(void); -extern void auditsc_get_stamp(struct audit_context *ctx, +extern int auditsc_get_stamp(struct audit_context *ctx, struct timespec *t, unsigned int *serial); extern int audit_set_loginuid(struct task_struct *task, uid_t loginuid); #define audit_get_loginuid(t) ((t)->loginuid) @@ -504,6 +505,7 @@ static inline int audit_mq_getsetattr(mqd_t mqdes, struct mq_attr *mqstat) extern int audit_n_rules; extern int audit_signals; #else +#define audit_finish_fork(t) #define audit_alloc(t) ({ 0; }) #define audit_free(t) do { ; } while (0) #define audit_syscall_entry(ta,a,b,c,d,e) do { ; } while (0) @@ -516,7 +518,7 @@ extern int audit_signals; #define audit_inode(n,d) do { ; } while (0) #define audit_inode_child(d,i,p) do { ; } while (0) #define audit_core_dumps(i) do { ; } while (0) -#define auditsc_get_stamp(c,t,s) do { BUG(); } while (0) +#define auditsc_get_stamp(c,t,s) (0) #define audit_get_loginuid(t) (-1) #define audit_get_sessionid(t) (-1) #define audit_log_task_context(b) do { ; } while (0) diff --git a/include/linux/bio.h b/include/linux/bio.h index 1c91a176b9ae..6a642098e5c3 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h @@ -236,12 +236,16 @@ static inline void *bio_data(struct bio *bio) #define __BVEC_END(bio) bio_iovec_idx((bio), (bio)->bi_vcnt - 1) #define __BVEC_START(bio) bio_iovec_idx((bio), (bio)->bi_idx) +/* Default implementation of BIOVEC_PHYS_MERGEABLE */ +#define __BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ + ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) + /* * allow arch override, for eg virtualized architectures (put in asm/io.h) */ #ifndef BIOVEC_PHYS_MERGEABLE #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ - ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) + __BIOVEC_PHYS_MERGEABLE(vec1, vec2) #endif #define __BIO_SEG_BOUNDARY(addr1, addr2, mask) \ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index a135256b272c..031a315c0509 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -662,6 +662,7 @@ extern unsigned long blk_max_low_pfn, blk_max_pfn; * default timeout for SG_IO if none specified */ #define BLK_DEFAULT_SG_TIMEOUT (60 * HZ) +#define BLK_MIN_SG_TIMEOUT (7 * HZ) #ifdef CONFIG_BOUNCE extern int init_emergency_isa_pool(void); @@ -786,6 +787,8 @@ static inline void blk_run_address_space(struct address_space *mapping) blk_run_backing_dev(mapping->backing_dev_info, NULL); } +extern void blkdev_dequeue_request(struct request *req); + /* * blk_end_request() and friends. * __blk_end_request() and end_request() must be called with @@ -820,11 +823,6 @@ extern void blk_update_request(struct request *rq, int error, extern unsigned int blk_rq_bytes(struct request *rq); extern unsigned int blk_rq_cur_bytes(struct request *rq); -static inline void blkdev_dequeue_request(struct request *req) -{ - elv_dequeue_request(req->q, req); -} - /* * Access functions for manipulating queue properties */ @@ -921,6 +919,8 @@ extern void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter); #define MAX_SEGMENT_SIZE 65536 +#define BLK_SEG_BOUNDARY_MASK 0xFFFFFFFFUL + #define blkdev_entry_to_request(entry) list_entry((entry), struct request, queuelist) static inline int queue_hardsect_size(struct request_queue *q) diff --git a/include/linux/c2port.h b/include/linux/c2port.h new file mode 100644 index 000000000000..7b5a2388ba67 --- /dev/null +++ b/include/linux/c2port.h @@ -0,0 +1,65 @@ +/* + * Silicon Labs C2 port Linux support + * + * Copyright (c) 2007 Rodolfo Giometti + * Copyright (c) 2007 Eurotech S.p.A. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation + */ + +#include + +#define C2PORT_NAME_LEN 32 + +/* + * C2 port basic structs + */ + +/* Main struct */ +struct c2port_ops; +struct c2port_device { + unsigned int access:1; + unsigned int flash_access:1; + + int id; + char name[C2PORT_NAME_LEN]; + struct c2port_ops *ops; + struct mutex mutex; /* prevent races during read/write */ + + struct device *dev; + + void *private_data; +}; + +/* Basic operations */ +struct c2port_ops { + /* Flash layout */ + unsigned short block_size; /* flash block size in bytes */ + unsigned short blocks_num; /* flash blocks number */ + + /* Enable or disable the access to C2 port */ + void (*access)(struct c2port_device *dev, int status); + + /* Set C2D data line as input/output */ + void (*c2d_dir)(struct c2port_device *dev, int dir); + + /* Read/write C2D data line */ + int (*c2d_get)(struct c2port_device *dev); + void (*c2d_set)(struct c2port_device *dev, int status); + + /* Write C2CK clock line */ + void (*c2ck_set)(struct c2port_device *dev, int status); +}; + +/* + * Exported functions + */ + +#define to_class_dev(obj) container_of((obj), struct class_device, kobj) +#define to_c2port_device(obj) container_of((obj), struct c2port_device, class) + +extern struct c2port_device *c2port_device_register(char *name, + struct c2port_ops *ops, void *devdata); +extern void c2port_device_unregister(struct c2port_device *dev); diff --git a/include/linux/can/core.h b/include/linux/can/core.h index e9ca210ffa5b..f50785ad4781 100644 --- a/include/linux/can/core.h +++ b/include/linux/can/core.h @@ -19,7 +19,7 @@ #include #include -#define CAN_VERSION "20071116" +#define CAN_VERSION "20081130" /* increment this number each time you change some user-space interface */ #define CAN_ABI_VERSION "8" diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h index 8b00f6643e93..1164963c3a85 100644 --- a/include/linux/cgroup.h +++ b/include/linux/cgroup.h @@ -25,7 +25,6 @@ struct cgroup; extern int cgroup_init_early(void); extern int cgroup_init(void); -extern void cgroup_init_smp(void); extern void cgroup_lock(void); extern bool cgroup_lock_live_group(struct cgroup *cgrp); extern void cgroup_unlock(void); @@ -348,8 +347,6 @@ struct cgroup_subsys { struct cgroupfs_root *root; struct list_head sibling; - - void *private; }; #define SUBSYS(_x) extern struct cgroup_subsys _x ## _subsys; @@ -410,7 +407,6 @@ void cgroup_mm_owner_callbacks(struct task_struct *old, static inline int cgroup_init_early(void) { return 0; } static inline int cgroup_init(void) { return 0; } -static inline void cgroup_init_smp(void) {} static inline void cgroup_fork(struct task_struct *p) {} static inline void cgroup_fork_callbacks(struct task_struct *p) {} static inline void cgroup_post_fork(struct task_struct *p) {} diff --git a/include/linux/cnt32_to_63.h b/include/linux/cnt32_to_63.h index 8c0f9505b48c..7605fdd1eb65 100644 --- a/include/linux/cnt32_to_63.h +++ b/include/linux/cnt32_to_63.h @@ -16,6 +16,7 @@ #include #include #include +#include /* this is used only to give gcc a clue about good code generation */ union cnt32_to_63 { @@ -53,11 +54,19 @@ union cnt32_to_63 { * needed increment. And any race in updating the value in memory is harmless * as the same value would simply be stored more than once. * - * The only restriction for the algorithm to work properly is that this - * code must be executed at least once per each half period of the 32-bit - * counter to properly update the state bit in memory. This is usually not a - * problem in practice, but if it is then a kernel timer could be scheduled - * to manage for this code to be executed often enough. + * The restrictions for the algorithm to work properly are: + * + * 1) this code must be called at least once per each half period of the + * 32-bit counter; + * + * 2) this code must not be preempted for a duration longer than the + * 32-bit counter half period minus the longest period between two + * calls to this code. + * + * Those requirements ensure proper update to the state bit in memory. + * This is usually not a problem in practice, but if it is then a kernel + * timer should be scheduled to manage for this code to be executed often + * enough. * * Note that the top bit (bit 63) in the returned value should be considered * as garbage. It is not cleared here because callers are likely to use a @@ -68,9 +77,10 @@ union cnt32_to_63 { */ #define cnt32_to_63(cnt_lo) \ ({ \ - static volatile u32 __m_cnt_hi; \ + static u32 __m_cnt_hi; \ union cnt32_to_63 __x; \ __x.hi = __m_cnt_hi; \ + smp_rmb(); \ __x.lo = (cnt_lo); \ if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \ __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \ diff --git a/include/linux/compat.h b/include/linux/compat.h index f061a1ea1b74..e88f3ecf38b4 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -252,12 +252,10 @@ extern int compat_ptrace_request(struct task_struct *child, compat_long_t request, compat_ulong_t addr, compat_ulong_t data); -#ifdef __ARCH_WANT_COMPAT_SYS_PTRACE extern long compat_arch_ptrace(struct task_struct *child, compat_long_t request, compat_ulong_t addr, compat_ulong_t data); asmlinkage long compat_sys_ptrace(compat_long_t request, compat_long_t pid, compat_long_t addr, compat_long_t data); -#endif /* __ARCH_WANT_COMPAT_SYS_PTRACE */ /* * epoll (fs/eventpoll.c) compat bits follow ... diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index d3219d73f8e6..21e1dd43e52a 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -5,6 +5,9 @@ * Cpumasks provide a bitmap suitable for representing the * set of CPU's in a system, one bit position per CPU number. * + * The new cpumask_ ops take a "struct cpumask *"; the old ones + * use cpumask_t. + * * See detailed comments in the file linux/bitmap.h describing the * data type on which these cpumasks are based. * @@ -31,7 +34,7 @@ * will span the entire range of NR_CPUS. * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * - * The available cpumask operations are: + * The obsolescent cpumask operations are: * * void cpu_set(cpu, mask) turn on bit 'cpu' in mask * void cpu_clear(cpu, mask) turn off bit 'cpu' in mask @@ -138,7 +141,7 @@ #include #include -typedef struct { DECLARE_BITMAP(bits, NR_CPUS); } cpumask_t; +typedef struct cpumask { DECLARE_BITMAP(bits, NR_CPUS); } cpumask_t; extern cpumask_t _unused_cpumask_arg_; #define cpu_set(cpu, dst) __cpu_set((cpu), &(dst)) @@ -527,4 +530,556 @@ extern cpumask_t cpu_active_map; #define for_each_online_cpu(cpu) for_each_cpu_mask_nr((cpu), cpu_online_map) #define for_each_present_cpu(cpu) for_each_cpu_mask_nr((cpu), cpu_present_map) +/* These are the new versions of the cpumask operators: passed by pointer. + * The older versions will be implemented in terms of these, then deleted. */ +#define cpumask_bits(maskp) ((maskp)->bits) + +#if NR_CPUS <= BITS_PER_LONG +#define CPU_BITS_ALL \ +{ \ + [BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD \ +} + +/* This produces more efficient code. */ +#define nr_cpumask_bits NR_CPUS + +#else /* NR_CPUS > BITS_PER_LONG */ + +#define CPU_BITS_ALL \ +{ \ + [0 ... BITS_TO_LONGS(NR_CPUS)-2] = ~0UL, \ + [BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD \ +} + +#define nr_cpumask_bits nr_cpu_ids +#endif /* NR_CPUS > BITS_PER_LONG */ + +/* verify cpu argument to cpumask_* operators */ +static inline unsigned int cpumask_check(unsigned int cpu) +{ +#ifdef CONFIG_DEBUG_PER_CPU_MAPS + WARN_ON_ONCE(cpu >= nr_cpumask_bits); +#endif /* CONFIG_DEBUG_PER_CPU_MAPS */ + return cpu; +} + +#if NR_CPUS == 1 +/* Uniprocessor. Assume all masks are "1". */ +static inline unsigned int cpumask_first(const struct cpumask *srcp) +{ + return 0; +} + +/* Valid inputs for n are -1 and 0. */ +static inline unsigned int cpumask_next(int n, const struct cpumask *srcp) +{ + return n+1; +} + +static inline unsigned int cpumask_next_zero(int n, const struct cpumask *srcp) +{ + return n+1; +} + +static inline unsigned int cpumask_next_and(int n, + const struct cpumask *srcp, + const struct cpumask *andp) +{ + return n+1; +} + +/* cpu must be a valid cpu, ie 0, so there's no other choice. */ +static inline unsigned int cpumask_any_but(const struct cpumask *mask, + unsigned int cpu) +{ + return 1; +} + +#define for_each_cpu(cpu, mask) \ + for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask) +#define for_each_cpu_and(cpu, mask, and) \ + for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)and) +#else +/** + * cpumask_first - get the first cpu in a cpumask + * @srcp: the cpumask pointer + * + * Returns >= nr_cpu_ids if no cpus set. + */ +static inline unsigned int cpumask_first(const struct cpumask *srcp) +{ + return find_first_bit(cpumask_bits(srcp), nr_cpumask_bits); +} + +/** + * cpumask_next - get the next cpu in a cpumask + * @n: the cpu prior to the place to search (ie. return will be > @n) + * @srcp: the cpumask pointer + * + * Returns >= nr_cpu_ids if no further cpus set. + */ +static inline unsigned int cpumask_next(int n, const struct cpumask *srcp) +{ + /* -1 is a legal arg here. */ + if (n != -1) + cpumask_check(n); + return find_next_bit(cpumask_bits(srcp), nr_cpumask_bits, n+1); +} + +/** + * cpumask_next_zero - get the next unset cpu in a cpumask + * @n: the cpu prior to the place to search (ie. return will be > @n) + * @srcp: the cpumask pointer + * + * Returns >= nr_cpu_ids if no further cpus unset. + */ +static inline unsigned int cpumask_next_zero(int n, const struct cpumask *srcp) +{ + /* -1 is a legal arg here. */ + if (n != -1) + cpumask_check(n); + return find_next_zero_bit(cpumask_bits(srcp), nr_cpumask_bits, n+1); +} + +int cpumask_next_and(int n, const struct cpumask *, const struct cpumask *); +int cpumask_any_but(const struct cpumask *mask, unsigned int cpu); + +/** + * for_each_cpu - iterate over every cpu in a mask + * @cpu: the (optionally unsigned) integer iterator + * @mask: the cpumask pointer + * + * After the loop, cpu is >= nr_cpu_ids. + */ +#define for_each_cpu(cpu, mask) \ + for ((cpu) = -1; \ + (cpu) = cpumask_next((cpu), (mask)), \ + (cpu) < nr_cpu_ids;) + +/** + * for_each_cpu_and - iterate over every cpu in both masks + * @cpu: the (optionally unsigned) integer iterator + * @mask: the first cpumask pointer + * @and: the second cpumask pointer + * + * This saves a temporary CPU mask in many places. It is equivalent to: + * struct cpumask tmp; + * cpumask_and(&tmp, &mask, &and); + * for_each_cpu(cpu, &tmp) + * ... + * + * After the loop, cpu is >= nr_cpu_ids. + */ +#define for_each_cpu_and(cpu, mask, and) \ + for ((cpu) = -1; \ + (cpu) = cpumask_next_and((cpu), (mask), (and)), \ + (cpu) < nr_cpu_ids;) +#endif /* SMP */ + +#define CPU_BITS_NONE \ +{ \ + [0 ... BITS_TO_LONGS(NR_CPUS)-1] = 0UL \ +} + +#define CPU_BITS_CPU0 \ +{ \ + [0] = 1UL \ +} + +/** + * cpumask_set_cpu - set a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @dstp: the cpumask pointer + */ +static inline void cpumask_set_cpu(unsigned int cpu, struct cpumask *dstp) +{ + set_bit(cpumask_check(cpu), cpumask_bits(dstp)); +} + +/** + * cpumask_clear_cpu - clear a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @dstp: the cpumask pointer + */ +static inline void cpumask_clear_cpu(int cpu, struct cpumask *dstp) +{ + clear_bit(cpumask_check(cpu), cpumask_bits(dstp)); +} + +/** + * cpumask_test_cpu - test for a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @cpumask: the cpumask pointer + * + * No static inline type checking - see Subtlety (1) above. + */ +#define cpumask_test_cpu(cpu, cpumask) \ + test_bit(cpumask_check(cpu), (cpumask)->bits) + +/** + * cpumask_test_and_set_cpu - atomically test and set a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @cpumask: the cpumask pointer + * + * test_and_set_bit wrapper for cpumasks. + */ +static inline int cpumask_test_and_set_cpu(int cpu, struct cpumask *cpumask) +{ + return test_and_set_bit(cpumask_check(cpu), cpumask_bits(cpumask)); +} + +/** + * cpumask_setall - set all cpus (< nr_cpu_ids) in a cpumask + * @dstp: the cpumask pointer + */ +static inline void cpumask_setall(struct cpumask *dstp) +{ + bitmap_fill(cpumask_bits(dstp), nr_cpumask_bits); +} + +/** + * cpumask_clear - clear all cpus (< nr_cpu_ids) in a cpumask + * @dstp: the cpumask pointer + */ +static inline void cpumask_clear(struct cpumask *dstp) +{ + bitmap_zero(cpumask_bits(dstp), nr_cpumask_bits); +} + +/** + * cpumask_and - *dstp = *src1p & *src2p + * @dstp: the cpumask result + * @src1p: the first input + * @src2p: the second input + */ +static inline void cpumask_and(struct cpumask *dstp, + const struct cpumask *src1p, + const struct cpumask *src2p) +{ + bitmap_and(cpumask_bits(dstp), cpumask_bits(src1p), + cpumask_bits(src2p), nr_cpumask_bits); +} + +/** + * cpumask_or - *dstp = *src1p | *src2p + * @dstp: the cpumask result + * @src1p: the first input + * @src2p: the second input + */ +static inline void cpumask_or(struct cpumask *dstp, const struct cpumask *src1p, + const struct cpumask *src2p) +{ + bitmap_or(cpumask_bits(dstp), cpumask_bits(src1p), + cpumask_bits(src2p), nr_cpumask_bits); +} + +/** + * cpumask_xor - *dstp = *src1p ^ *src2p + * @dstp: the cpumask result + * @src1p: the first input + * @src2p: the second input + */ +static inline void cpumask_xor(struct cpumask *dstp, + const struct cpumask *src1p, + const struct cpumask *src2p) +{ + bitmap_xor(cpumask_bits(dstp), cpumask_bits(src1p), + cpumask_bits(src2p), nr_cpumask_bits); +} + +/** + * cpumask_andnot - *dstp = *src1p & ~*src2p + * @dstp: the cpumask result + * @src1p: the first input + * @src2p: the second input + */ +static inline void cpumask_andnot(struct cpumask *dstp, + const struct cpumask *src1p, + const struct cpumask *src2p) +{ + bitmap_andnot(cpumask_bits(dstp), cpumask_bits(src1p), + cpumask_bits(src2p), nr_cpumask_bits); +} + +/** + * cpumask_complement - *dstp = ~*srcp + * @dstp: the cpumask result + * @srcp: the input to invert + */ +static inline void cpumask_complement(struct cpumask *dstp, + const struct cpumask *srcp) +{ + bitmap_complement(cpumask_bits(dstp), cpumask_bits(srcp), + nr_cpumask_bits); +} + +/** + * cpumask_equal - *src1p == *src2p + * @src1p: the first input + * @src2p: the second input + */ +static inline bool cpumask_equal(const struct cpumask *src1p, + const struct cpumask *src2p) +{ + return bitmap_equal(cpumask_bits(src1p), cpumask_bits(src2p), + nr_cpumask_bits); +} + +/** + * cpumask_intersects - (*src1p & *src2p) != 0 + * @src1p: the first input + * @src2p: the second input + */ +static inline bool cpumask_intersects(const struct cpumask *src1p, + const struct cpumask *src2p) +{ + return bitmap_intersects(cpumask_bits(src1p), cpumask_bits(src2p), + nr_cpumask_bits); +} + +/** + * cpumask_subset - (*src1p & ~*src2p) == 0 + * @src1p: the first input + * @src2p: the second input + */ +static inline int cpumask_subset(const struct cpumask *src1p, + const struct cpumask *src2p) +{ + return bitmap_subset(cpumask_bits(src1p), cpumask_bits(src2p), + nr_cpumask_bits); +} + +/** + * cpumask_empty - *srcp == 0 + * @srcp: the cpumask to that all cpus < nr_cpu_ids are clear. + */ +static inline bool cpumask_empty(const struct cpumask *srcp) +{ + return bitmap_empty(cpumask_bits(srcp), nr_cpumask_bits); +} + +/** + * cpumask_full - *srcp == 0xFFFFFFFF... + * @srcp: the cpumask to that all cpus < nr_cpu_ids are set. + */ +static inline bool cpumask_full(const struct cpumask *srcp) +{ + return bitmap_full(cpumask_bits(srcp), nr_cpumask_bits); +} + +/** + * cpumask_weight - Count of bits in *srcp + * @srcp: the cpumask to count bits (< nr_cpu_ids) in. + */ +static inline unsigned int cpumask_weight(const struct cpumask *srcp) +{ + return bitmap_weight(cpumask_bits(srcp), nr_cpumask_bits); +} + +/** + * cpumask_shift_right - *dstp = *srcp >> n + * @dstp: the cpumask result + * @srcp: the input to shift + * @n: the number of bits to shift by + */ +static inline void cpumask_shift_right(struct cpumask *dstp, + const struct cpumask *srcp, int n) +{ + bitmap_shift_right(cpumask_bits(dstp), cpumask_bits(srcp), n, + nr_cpumask_bits); +} + +/** + * cpumask_shift_left - *dstp = *srcp << n + * @dstp: the cpumask result + * @srcp: the input to shift + * @n: the number of bits to shift by + */ +static inline void cpumask_shift_left(struct cpumask *dstp, + const struct cpumask *srcp, int n) +{ + bitmap_shift_left(cpumask_bits(dstp), cpumask_bits(srcp), n, + nr_cpumask_bits); +} + +/** + * cpumask_copy - *dstp = *srcp + * @dstp: the result + * @srcp: the input cpumask + */ +static inline void cpumask_copy(struct cpumask *dstp, + const struct cpumask *srcp) +{ + bitmap_copy(cpumask_bits(dstp), cpumask_bits(srcp), nr_cpumask_bits); +} + +/** + * cpumask_any - pick a "random" cpu from *srcp + * @srcp: the input cpumask + * + * Returns >= nr_cpu_ids if no cpus set. + */ +#define cpumask_any(srcp) cpumask_first(srcp) + +/** + * cpumask_first_and - return the first cpu from *srcp1 & *srcp2 + * @src1p: the first input + * @src2p: the second input + * + * Returns >= nr_cpu_ids if no cpus set in both. See also cpumask_next_and(). + */ +#define cpumask_first_and(src1p, src2p) cpumask_next_and(-1, (src1p), (src2p)) + +/** + * cpumask_any_and - pick a "random" cpu from *mask1 & *mask2 + * @mask1: the first input cpumask + * @mask2: the second input cpumask + * + * Returns >= nr_cpu_ids if no cpus set. + */ +#define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) + +/** + * cpumask_of - the cpumask containing just a given cpu + * @cpu: the cpu (<= nr_cpu_ids) + */ +#define cpumask_of(cpu) (get_cpu_mask(cpu)) + +/** + * to_cpumask - convert an NR_CPUS bitmap to a struct cpumask * + * @bitmap: the bitmap + * + * There are a few places where cpumask_var_t isn't appropriate and + * static cpumasks must be used (eg. very early boot), yet we don't + * expose the definition of 'struct cpumask'. + * + * This does the conversion, and can be used as a constant initializer. + */ +#define to_cpumask(bitmap) \ + ((struct cpumask *)(1 ? (bitmap) \ + : (void *)sizeof(__check_is_bitmap(bitmap)))) + +static inline int __check_is_bitmap(const unsigned long *bitmap) +{ + return 1; +} + +/** + * cpumask_size - size to allocate for a 'struct cpumask' in bytes + * + * This will eventually be a runtime variable, depending on nr_cpu_ids. + */ +static inline size_t cpumask_size(void) +{ + /* FIXME: Once all cpumask assignments are eliminated, this + * can be nr_cpumask_bits */ + return BITS_TO_LONGS(NR_CPUS) * sizeof(long); +} + +/* + * cpumask_var_t: struct cpumask for stack usage. + * + * Oh, the wicked games we play! In order to make kernel coding a + * little more difficult, we typedef cpumask_var_t to an array or a + * pointer: doing &mask on an array is a noop, so it still works. + * + * ie. + * cpumask_var_t tmpmask; + * if (!alloc_cpumask_var(&tmpmask, GFP_KERNEL)) + * return -ENOMEM; + * + * ... use 'tmpmask' like a normal struct cpumask * ... + * + * free_cpumask_var(tmpmask); + */ +#ifdef CONFIG_CPUMASK_OFFSTACK +typedef struct cpumask *cpumask_var_t; + +bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags); +void alloc_bootmem_cpumask_var(cpumask_var_t *mask); +void free_cpumask_var(cpumask_var_t mask); +void free_bootmem_cpumask_var(cpumask_var_t mask); + +#else +typedef struct cpumask cpumask_var_t[1]; + +static inline bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) +{ + return true; +} + +static inline void alloc_bootmem_cpumask_var(cpumask_var_t *mask) +{ +} + +static inline void free_cpumask_var(cpumask_var_t mask) +{ +} + +static inline void free_bootmem_cpumask_var(cpumask_var_t mask) +{ +} +#endif /* CONFIG_CPUMASK_OFFSTACK */ + +/* The pointer versions of the maps, these will become the primary versions. */ +#define cpu_possible_mask ((const struct cpumask *)&cpu_possible_map) +#define cpu_online_mask ((const struct cpumask *)&cpu_online_map) +#define cpu_present_mask ((const struct cpumask *)&cpu_present_map) +#define cpu_active_mask ((const struct cpumask *)&cpu_active_map) + +/* It's common to want to use cpu_all_mask in struct member initializers, + * so it has to refer to an address rather than a pointer. */ +extern const DECLARE_BITMAP(cpu_all_bits, NR_CPUS); +#define cpu_all_mask to_cpumask(cpu_all_bits) + +/* First bits of cpu_bit_bitmap are in fact unset. */ +#define cpu_none_mask to_cpumask(cpu_bit_bitmap[0]) + +/* Wrappers for arch boot code to manipulate normally-constant masks */ +static inline void set_cpu_possible(unsigned int cpu, bool possible) +{ + if (possible) + cpumask_set_cpu(cpu, &cpu_possible_map); + else + cpumask_clear_cpu(cpu, &cpu_possible_map); +} + +static inline void set_cpu_present(unsigned int cpu, bool present) +{ + if (present) + cpumask_set_cpu(cpu, &cpu_present_map); + else + cpumask_clear_cpu(cpu, &cpu_present_map); +} + +static inline void set_cpu_online(unsigned int cpu, bool online) +{ + if (online) + cpumask_set_cpu(cpu, &cpu_online_map); + else + cpumask_clear_cpu(cpu, &cpu_online_map); +} + +static inline void set_cpu_active(unsigned int cpu, bool active) +{ + if (active) + cpumask_set_cpu(cpu, &cpu_active_map); + else + cpumask_clear_cpu(cpu, &cpu_active_map); +} + +static inline void init_cpu_present(const struct cpumask *src) +{ + cpumask_copy(&cpu_present_map, src); +} + +static inline void init_cpu_possible(const struct cpumask *src) +{ + cpumask_copy(&cpu_possible_map, src); +} + +static inline void init_cpu_online(const struct cpumask *src) +{ + cpumask_copy(&cpu_online_map, src); +} #endif /* __LINUX_CPUMASK_H */ diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h index 2691926fb506..8e540d32c9fe 100644 --- a/include/linux/cpuset.h +++ b/include/linux/cpuset.h @@ -74,8 +74,6 @@ static inline int cpuset_do_slab_mem_spread(void) return current->flags & PF_SPREAD_SLAB; } -extern void cpuset_track_online_nodes(void); - extern int current_cpuset_is_being_rebound(void); extern void rebuild_sched_domains(void); @@ -151,8 +149,6 @@ static inline int cpuset_do_slab_mem_spread(void) return 0; } -static inline void cpuset_track_online_nodes(void) {} - static inline int current_cpuset_is_being_rebound(void) { return 0; diff --git a/include/linux/dmi.h b/include/linux/dmi.h index e5084eb5943a..2bfda178f274 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -44,6 +44,7 @@ extern const struct dmi_device * dmi_find_device(int type, const char *name, extern void dmi_scan_machine(void); extern int dmi_get_year(int field); extern int dmi_name_in_vendors(const char *str); +extern int dmi_name_in_serial(const char *str); extern int dmi_available; extern int dmi_walk(void (*decode)(const struct dmi_header *)); @@ -56,6 +57,7 @@ static inline const struct dmi_device * dmi_find_device(int type, const char *na static inline void dmi_scan_machine(void) { return; } static inline int dmi_get_year(int year) { return 0; } static inline int dmi_name_in_vendors(const char *s) { return 0; } +static inline int dmi_name_in_serial(const char *s) { return 0; } #define dmi_available 0 static inline int dmi_walk(void (*decode)(const struct dmi_header *)) { return -1; } diff --git a/include/linux/freezer.h b/include/linux/freezer.h index 8f225339eee9..5a361f85cfec 100644 --- a/include/linux/freezer.h +++ b/include/linux/freezer.h @@ -44,11 +44,6 @@ static inline bool should_send_signal(struct task_struct *p) return !(p->flags & PF_FREEZER_NOSIG); } -/* - * Wake up a frozen process - */ -extern int __thaw_process(struct task_struct *p); - /* Takes and releases task alloc lock using task_lock() */ extern int thaw_process(struct task_struct *p); diff --git a/include/linux/fs.h b/include/linux/fs.h index 5b248d61430c..4a853ef6fd35 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -63,23 +63,24 @@ extern int dir_notify_enable; #define MAY_ACCESS 16 #define MAY_OPEN 32 -#define FMODE_READ ((__force fmode_t)1) -#define FMODE_WRITE ((__force fmode_t)2) - -/* Internal kernel extensions */ -#define FMODE_LSEEK ((__force fmode_t)4) -#define FMODE_PREAD ((__force fmode_t)8) -#define FMODE_PWRITE FMODE_PREAD /* These go hand in hand */ - -/* File is being opened for execution. Primary users of this flag are - distributed filesystems that can use it to achieve correct ETXTBUSY - behavior for cross-node execution/opening_for_writing of files */ -#define FMODE_EXEC ((__force fmode_t)16) - -#define FMODE_NDELAY ((__force fmode_t)32) -#define FMODE_EXCL ((__force fmode_t)64) +/* file is open for reading */ +#define FMODE_READ ((__force fmode_t)1) +/* file is open for writing */ +#define FMODE_WRITE ((__force fmode_t)2) +/* file is seekable */ +#define FMODE_LSEEK ((__force fmode_t)4) +/* file can be accessed using pread/pwrite */ +#define FMODE_PREAD ((__force fmode_t)8) +#define FMODE_PWRITE FMODE_PREAD /* These go hand in hand */ +/* File is opened for execution with sys_execve / sys_uselib */ +#define FMODE_EXEC ((__force fmode_t)16) +/* File is opened with O_NDELAY (only set for block devices) */ +#define FMODE_NDELAY ((__force fmode_t)32) +/* File is opened with O_EXCL (only set for block devices) */ +#define FMODE_EXCL ((__force fmode_t)64) +/* File is opened using open(.., 3, ..) and is writeable only for ioctls + (specialy hack for floppy.c) */ #define FMODE_WRITE_IOCTL ((__force fmode_t)128) -#define FMODE_NDELAY_NOW ((__force fmode_t)256) #define RW_MASK 1 #define RWA_MASK 2 @@ -489,13 +490,6 @@ struct address_space_operations { int (*readpages)(struct file *filp, struct address_space *mapping, struct list_head *pages, unsigned nr_pages); - /* - * ext3 requires that a successful prepare_write() call be followed - * by a commit_write() call - they must be balanced - */ - int (*prepare_write)(struct file *, struct page *, unsigned, unsigned); - int (*commit_write)(struct file *, struct page *, unsigned, unsigned); - int (*write_begin)(struct file *, struct address_space *mapping, loff_t pos, unsigned len, unsigned flags, struct page **pagep, void **fsdata); diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 4e625e0094c8..708bab58d8d0 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -49,7 +49,8 @@ struct gianfar_platform_data { u32 device_flags; /* board specific information */ u32 board_flags; - char bus_id[MII_BUS_ID_SIZE]; + int mdio_bus; /* Bus controlled by us */ + char bus_id[MII_BUS_ID_SIZE]; /* Bus PHY is on */ u32 phy_id; u8 mac_addr[6]; phy_interface_t interface; diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h index a3d46151be19..9c5bc6be2b09 100644 --- a/include/linux/ftrace.h +++ b/include/linux/ftrace.h @@ -6,9 +6,10 @@ #include #include #include +#include #include -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER extern int ftrace_enabled; extern int @@ -36,16 +37,14 @@ void clear_ftrace_function(void); extern void ftrace_stub(unsigned long a0, unsigned long a1); -#else /* !CONFIG_FTRACE */ +#else /* !CONFIG_FUNCTION_TRACER */ # define register_ftrace_function(ops) do { } while (0) # define unregister_ftrace_function(ops) do { } while (0) # define clear_ftrace_function(ops) do { } while (0) -static inline void ftrace_kill_atomic(void) { } -#endif /* CONFIG_FTRACE */ +static inline void ftrace_kill(void) { } +#endif /* CONFIG_FUNCTION_TRACER */ #ifdef CONFIG_DYNAMIC_FTRACE -# define FTRACE_HASHBITS 10 -# define FTRACE_HASHSIZE (1<_softexpires = ktime_add_safe(timer->_softexpires, time); } -static inline void hrtimer_add_expires_ns(struct hrtimer *timer, unsigned long ns) +static inline void hrtimer_add_expires_ns(struct hrtimer *timer, u64 ns) { timer->_expires = ktime_add_ns(timer->_expires, ns); timer->_softexpires = ktime_add_ns(timer->_softexpires, ns); diff --git a/include/linux/i7300_idle.h b/include/linux/i7300_idle.h new file mode 100644 index 000000000000..05a80c44513c --- /dev/null +++ b/include/linux/i7300_idle.h @@ -0,0 +1,83 @@ + +#ifndef I7300_IDLE_H +#define I7300_IDLE_H + +#include + +/* + * I/O AT controls (PCI bus 0 device 8 function 0) + * DIMM controls (PCI bus 0 device 16 function 1) + */ +#define IOAT_BUS 0 +#define IOAT_DEVFN PCI_DEVFN(8, 0) +#define MEMCTL_BUS 0 +#define MEMCTL_DEVFN PCI_DEVFN(16, 1) + +struct fbd_ioat { + unsigned int vendor; + unsigned int ioat_dev; +}; + +/* + * The i5000 chip-set has the same hooks as the i7300 + * but support is disabled by default because this driver + * has not been validated on that platform. + */ +#define SUPPORT_I5000 0 + +static const struct fbd_ioat fbd_ioat_list[] = { + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB}, +#if SUPPORT_I5000 + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT}, +#endif + {0, 0} +}; + +/* table of devices that work with this driver */ +static const struct pci_device_id pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FBD_CNB) }, +#if SUPPORT_I5000 + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5000_ERR) }, +#endif + { } /* Terminating entry */ +}; + +/* Check for known platforms with I/O-AT */ +static inline int i7300_idle_platform_probe(struct pci_dev **fbd_dev, + struct pci_dev **ioat_dev) +{ + int i; + struct pci_dev *memdev, *dmadev; + + memdev = pci_get_bus_and_slot(MEMCTL_BUS, MEMCTL_DEVFN); + if (!memdev) + return -ENODEV; + + for (i = 0; pci_tbl[i].vendor != 0; i++) { + if (memdev->vendor == pci_tbl[i].vendor && + memdev->device == pci_tbl[i].device) { + break; + } + } + if (pci_tbl[i].vendor == 0) + return -ENODEV; + + dmadev = pci_get_bus_and_slot(IOAT_BUS, IOAT_DEVFN); + if (!dmadev) + return -ENODEV; + + for (i = 0; fbd_ioat_list[i].vendor != 0; i++) { + if (dmadev->vendor == fbd_ioat_list[i].vendor && + dmadev->device == fbd_ioat_list[i].ioat_dev) { + if (fbd_dev) + *fbd_dev = memdev; + if (ioat_dev) + *ioat_dev = dmadev; + + return 0; + } + } + return -ENODEV; +} + +#endif diff --git a/include/linux/ide.h b/include/linux/ide.h index 54525be4b5f8..010fb26a1579 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1296,6 +1296,13 @@ extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *o #define ide_pci_register_driver(d) pci_register_driver(d) #endif +static inline int ide_pci_is_in_compatibility_mode(struct pci_dev *dev) +{ + if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) + return 1; + return 0; +} + void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *, int, hw_regs_t *, hw_regs_t **); void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *); @@ -1375,6 +1382,7 @@ enum { IDE_HFLAG_IO_32BIT = (1 << 24), /* unmask IRQs */ IDE_HFLAG_UNMASK_IRQS = (1 << 25), + IDE_HFLAG_BROKEN_ALTSTATUS = (1 << 26), /* serialize ports if DMA is possible (for sl82c105) */ IDE_HFLAG_SERIALIZE_DMA = (1 << 27), /* force host out of "simplex" mode */ diff --git a/include/linux/idr.h b/include/linux/idr.h index fa035f96f2a3..dd846df8cd32 100644 --- a/include/linux/idr.h +++ b/include/linux/idr.h @@ -52,13 +52,14 @@ struct idr_layer { unsigned long bitmap; /* A zero bit means "space here" */ struct idr_layer *ary[1< + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_IO_MAPPING_H +#define _LINUX_IO_MAPPING_H + +#include +#include +#include +#include + +/* + * The io_mapping mechanism provides an abstraction for mapping + * individual pages from an io device to the CPU in an efficient fashion. + * + * See Documentation/io_mapping.txt + */ + +/* this struct isn't actually defined anywhere */ +struct io_mapping; + +#ifdef CONFIG_HAVE_ATOMIC_IOMAP + +/* + * For small address space machines, mapping large objects + * into the kernel virtual space isn't practical. Where + * available, use fixmap support to dynamically map pages + * of the object at run time. + */ + +static inline struct io_mapping * +io_mapping_create_wc(unsigned long base, unsigned long size) +{ + return (struct io_mapping *) base; +} + +static inline void +io_mapping_free(struct io_mapping *mapping) +{ +} + +/* Atomic map/unmap */ +static inline void * +io_mapping_map_atomic_wc(struct io_mapping *mapping, unsigned long offset) +{ + offset += (unsigned long) mapping; + return iomap_atomic_prot_pfn(offset >> PAGE_SHIFT, KM_USER0, + __pgprot(__PAGE_KERNEL_WC)); +} + +static inline void +io_mapping_unmap_atomic(void *vaddr) +{ + iounmap_atomic(vaddr, KM_USER0); +} + +static inline void * +io_mapping_map_wc(struct io_mapping *mapping, unsigned long offset) +{ + offset += (unsigned long) mapping; + return ioremap_wc(offset, PAGE_SIZE); +} + +static inline void +io_mapping_unmap(void *vaddr) +{ + iounmap(vaddr); +} + +#else + +/* Create the io_mapping object*/ +static inline struct io_mapping * +io_mapping_create_wc(unsigned long base, unsigned long size) +{ + return (struct io_mapping *) ioremap_wc(base, size); +} + +static inline void +io_mapping_free(struct io_mapping *mapping) +{ + iounmap(mapping); +} + +/* Atomic map/unmap */ +static inline void * +io_mapping_map_atomic_wc(struct io_mapping *mapping, unsigned long offset) +{ + return ((char *) mapping) + offset; +} + +static inline void +io_mapping_unmap_atomic(void *vaddr) +{ +} + +/* Non-atomic map/unmap */ +static inline void * +io_mapping_map_wc(struct io_mapping *mapping, unsigned long offset) +{ + return ((char *) mapping) + offset; +} + +static inline void +io_mapping_unmap(void *vaddr) +{ +} + +#endif /* HAVE_ATOMIC_IOMAP */ + +#endif /* _LINUX_IO_MAPPING_H */ diff --git a/include/linux/irq.h b/include/linux/irq.h index d058c57be02d..3dddfa703ebd 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -63,7 +63,8 @@ typedef void (*irq_flow_handler_t)(unsigned int irq, #define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */ #define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */ #define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */ -#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */ +#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */ +#define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/ #ifdef CONFIG_IRQ_PER_CPU # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU) @@ -130,7 +131,7 @@ struct irq_chip { /** * struct irq_desc - interrupt descriptor - * + * @irq: interrupt number for this descriptor * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()] * @chip: low level interrupt hardware access * @msi_desc: MSI descriptor @@ -149,7 +150,6 @@ struct irq_chip { * @cpu: cpu index useful for balancing * @pending_mask: pending rebalanced interrupts * @dir: /proc/irq/ procfs entry - * @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP * @name: flow handler name for /proc/interrupts output */ struct irq_desc { @@ -210,7 +210,6 @@ extern int setup_irq(unsigned int irq, struct irqaction *new); #ifdef CONFIG_GENERIC_PENDING_IRQ -void set_pending_irq(unsigned int irq, cpumask_t mask); void move_native_irq(int irq); void move_masked_irq(int irq); @@ -228,10 +227,6 @@ static inline void move_masked_irq(int irq) { } -static inline void set_pending_irq(unsigned int irq, cpumask_t mask) -{ -} - #endif /* CONFIG_GENERIC_PENDING_IRQ */ #else /* CONFIG_SMP */ diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 396a350b87a6..dc7e0d0a6474 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -116,6 +116,8 @@ extern int _cond_resched(void); # define might_resched() do { } while (0) #endif +#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP + void __might_sleep(char *file, int line); /** * might_sleep - annotation for functions that can sleep * @@ -126,8 +128,6 @@ extern int _cond_resched(void); * be bitten later when the calling function happens to sleep when it is not * supposed to. */ -#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP - void __might_sleep(char *file, int line); # define might_sleep() \ do { __might_sleep(__FILE__, __LINE__); might_resched(); } while (0) #else @@ -318,32 +318,36 @@ static inline char *pack_hex_byte(char *buf, u8 byte) return buf; } -#define pr_emerg(fmt, arg...) \ - printk(KERN_EMERG fmt, ##arg) -#define pr_alert(fmt, arg...) \ - printk(KERN_ALERT fmt, ##arg) -#define pr_crit(fmt, arg...) \ - printk(KERN_CRIT fmt, ##arg) -#define pr_err(fmt, arg...) \ - printk(KERN_ERR fmt, ##arg) -#define pr_warning(fmt, arg...) \ - printk(KERN_WARNING fmt, ##arg) -#define pr_notice(fmt, arg...) \ - printk(KERN_NOTICE fmt, ##arg) -#define pr_info(fmt, arg...) \ - printk(KERN_INFO fmt, ##arg) +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif + +#define pr_emerg(fmt, ...) \ + printk(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__) +#define pr_alert(fmt, ...) \ + printk(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__) +#define pr_crit(fmt, ...) \ + printk(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__) +#define pr_err(fmt, ...) \ + printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#define pr_warning(fmt, ...) \ + printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) +#define pr_notice(fmt, ...) \ + printk(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__) +#define pr_info(fmt, ...) \ + printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__) /* If you are writing a driver, please use dev_dbg instead */ #if defined(CONFIG_DYNAMIC_PRINTK_DEBUG) #define pr_debug(fmt, ...) do { \ - dynamic_pr_debug(fmt, ##__VA_ARGS__); \ + dynamic_pr_debug(pr_fmt(fmt), ##__VA_ARGS__); \ } while (0) #elif defined(DEBUG) -#define pr_debug(fmt, arg...) \ - printk(KERN_DEBUG fmt, ##arg) +#define pr_debug(fmt, ...) \ + printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__) #else -#define pr_debug(fmt, arg...) \ - ({ if (0) printk(KERN_DEBUG fmt, ##arg); 0; }) +#define pr_debug(fmt, ...) \ + ({ if (0) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__); 0; }) #endif /* diff --git a/include/linux/kexec.h b/include/linux/kexec.h index 17f76fc05173..adc34f2c6eff 100644 --- a/include/linux/kexec.h +++ b/include/linux/kexec.h @@ -100,6 +100,10 @@ struct kimage { #define KEXEC_TYPE_DEFAULT 0 #define KEXEC_TYPE_CRASH 1 unsigned int preserve_context : 1; + +#ifdef ARCH_HAS_KIMAGE_ARCH + struct kimage_arch arch; +#endif }; diff --git a/include/linux/kvm.h b/include/linux/kvm.h index 797fcd781242..f18b86fa8655 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -489,6 +489,9 @@ struct kvm_assigned_pci_dev { __u32 busnr; __u32 devfn; __u32 flags; + union { + __u32 reserved[12]; + }; }; struct kvm_assigned_irq { @@ -496,6 +499,9 @@ struct kvm_assigned_irq { __u32 host_irq; __u32 guest_irq; __u32 flags; + union { + __u32 reserved[12]; + }; }; #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 3833c48fae3a..bb92be2153bc 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -37,6 +37,8 @@ #define KVM_REQ_UNHALT 6 #define KVM_REQ_MMU_SYNC 7 +#define KVM_USERSPACE_IRQ_SOURCE_ID 0 + struct kvm_vcpu; extern struct kmem_cache *kvm_vcpu_cache; @@ -306,15 +308,18 @@ struct kvm_assigned_dev_kernel { int host_irq; int guest_irq; int irq_requested; + int irq_source_id; struct pci_dev *dev; struct kvm *kvm; }; -void kvm_set_irq(struct kvm *kvm, int irq, int level); +void kvm_set_irq(struct kvm *kvm, int irq_source_id, int irq, int level); void kvm_notify_acked_irq(struct kvm *kvm, unsigned gsi); void kvm_register_irq_ack_notifier(struct kvm *kvm, struct kvm_irq_ack_notifier *kian); void kvm_unregister_irq_ack_notifier(struct kvm *kvm, struct kvm_irq_ack_notifier *kian); +int kvm_request_irq_source_id(struct kvm *kvm); +void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id); #ifdef CONFIG_DMAR int kvm_iommu_map_pages(struct kvm *kvm, gfn_t base_gfn, diff --git a/include/linux/libata.h b/include/linux/libata.h index 507f53ef8038..ed3f26eb5df1 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -372,6 +372,10 @@ enum { ATA_HORKAGE_IPM = (1 << 7), /* Link PM problems */ ATA_HORKAGE_IVB = (1 << 8), /* cbl det validity bit bugs */ ATA_HORKAGE_STUCK_ERR = (1 << 9), /* stuck ERR on next PACKET */ + ATA_HORKAGE_BRIDGE_OK = (1 << 10), /* no bridge limits */ + ATA_HORKAGE_ATAPI_MOD16_DMA = (1 << 11), /* use ATAPI DMA for commands + not multiple of 16 bytes */ + ATA_HORKAGE_FIRMWARE_WARN = (1 << 12), /* firwmare update warning */ /* DMA mask for user DMA control: User visible values; DO NOT renumber */ @@ -695,6 +699,7 @@ struct ata_port { unsigned int cbl; /* cable type; ATA_CBL_xxx */ struct ata_queued_cmd qcmd[ATA_MAX_QUEUE]; + unsigned long qc_allocated; unsigned int qc_active; int nr_active_links; /* #links with active qcs */ diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h index 331e5f1c2d8e..29aec6e10020 100644 --- a/include/linux/lockdep.h +++ b/include/linux/lockdep.h @@ -331,10 +331,11 @@ static inline void lockdep_on(void) # define lock_set_subclass(l, s, i) do { } while (0) # define lockdep_init() do { } while (0) # define lockdep_info() do { } while (0) -# define lockdep_init_map(lock, name, key, sub) do { (void)(key); } while (0) +# define lockdep_init_map(lock, name, key, sub) \ + do { (void)(name); (void)(key); } while (0) # define lockdep_set_class(lock, key) do { (void)(key); } while (0) # define lockdep_set_class_and_name(lock, key, name) \ - do { (void)(key); } while (0) + do { (void)(key); (void)(name); } while (0) #define lockdep_set_class_and_subclass(lock, key, sub) \ do { (void)(key); } while (0) #define lockdep_set_subclass(lock, sub) do { } while (0) diff --git a/include/linux/memory.h b/include/linux/memory.h index 2f5f8a5ef2a0..36c82c9e6ea7 100644 --- a/include/linux/memory.h +++ b/include/linux/memory.h @@ -91,7 +91,7 @@ extern int memory_notify(unsigned long val, void *v); #ifdef CONFIG_MEMORY_HOTPLUG #define hotplug_memory_notifier(fn, pri) { \ - static struct notifier_block fn##_mem_nb = \ + static __meminitdata struct notifier_block fn##_mem_nb =\ { .notifier_call = fn, .priority = pri }; \ register_memory_notifier(&fn##_mem_nb); \ } diff --git a/include/linux/mfd/wm8350/rtc.h b/include/linux/mfd/wm8350/rtc.h index dfda69e9f440..24add2bef6c9 100644 --- a/include/linux/mfd/wm8350/rtc.h +++ b/include/linux/mfd/wm8350/rtc.h @@ -261,6 +261,8 @@ struct wm8350_rtc { struct platform_device *pdev; + struct rtc_device *rtc; + int alarm_enabled; /* used over suspend/resume */ }; #endif diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index bd9977b89490..371086fd946f 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -179,6 +179,7 @@ struct mlx4_caps { int num_ports; int vl_cap[MLX4_MAX_PORTS + 1]; int ib_mtu_cap[MLX4_MAX_PORTS + 1]; + __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; u64 def_mac[MLX4_MAX_PORTS + 1]; int eth_mtu_cap[MLX4_MAX_PORTS + 1]; int gid_table_len[MLX4_MAX_PORTS + 1]; diff --git a/include/linux/mm.h b/include/linux/mm.h index ffee2f743418..d3ddd735e375 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -145,6 +145,23 @@ extern pgprot_t protection_map[16]; #define FAULT_FLAG_WRITE 0x01 /* Fault was a write access */ #define FAULT_FLAG_NONLINEAR 0x02 /* Fault was via a nonlinear mapping */ +/* + * This interface is used by x86 PAT code to identify a pfn mapping that is + * linear over entire vma. This is to optimize PAT code that deals with + * marking the physical region with a particular prot. This is not for generic + * mm use. Note also that this check will not work if the pfn mapping is + * linear for a vma starting at physical address 0. In which case PAT code + * falls back to slow path of reserving physical range page by page. + */ +static inline int is_linear_pfn_mapping(struct vm_area_struct *vma) +{ + return ((vma->vm_flags & VM_PFNMAP) && vma->vm_pgoff); +} + +static inline int is_pfn_mapping(struct vm_area_struct *vma) +{ + return (vma->vm_flags & VM_PFNMAP); +} /* * vm_fault is filled by the the pagefault handler and passed to the vma's @@ -781,6 +798,8 @@ int copy_page_range(struct mm_struct *dst, struct mm_struct *src, struct vm_area_struct *vma); void unmap_mapping_range(struct address_space *mapping, loff_t const holebegin, loff_t const holelen, int even_cows); +int follow_phys(struct vm_area_struct *vma, unsigned long address, + unsigned int flags, unsigned long *prot, resource_size_t *phys); int generic_access_phys(struct vm_area_struct *vma, unsigned long addr, void *buf, int len, int write); diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index ee6e822d5994..403aa505f27e 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -130,7 +130,7 @@ struct mmc_card { #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) #define mmc_card_name(c) ((c)->cid.prod_name) -#define mmc_card_id(c) ((c)->dev.bus_id) +#define mmc_card_id(c) (dev_name(&(c)->dev)) #define mmc_list_to_card(l) container_of(l, struct mmc_card, node) #define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev) diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index bde891f64591..f842f234e44f 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -176,7 +176,7 @@ static inline void *mmc_priv(struct mmc_host *host) #define mmc_dev(x) ((x)->parent) #define mmc_classdev(x) (&(x)->class_dev) -#define mmc_hostname(x) ((x)->class_dev.bus_id) +#define mmc_hostname(x) (dev_name(&(x)->class_dev)) extern int mmc_suspend_host(struct mmc_host *, pm_message_t); extern int mmc_resume_host(struct mmc_host *); diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h index 07bee4a0d457..451bdfc85830 100644 --- a/include/linux/mmc/sdio_func.h +++ b/include/linux/mmc/sdio_func.h @@ -63,7 +63,7 @@ struct sdio_func { #define sdio_func_set_present(f) ((f)->state |= SDIO_STATE_PRESENT) -#define sdio_func_id(f) ((f)->dev.bus_id) +#define sdio_func_id(f) (dev_name(&(f)->dev)) #define sdio_get_drvdata(f) dev_get_drvdata(&(f)->dev) #define sdio_set_drvdata(f,d) dev_set_drvdata(&(f)->dev, d) diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index eb71b45fdf5a..97b91d1abb43 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -135,6 +135,7 @@ struct usb_device_id { struct hid_device_id { __u16 bus; + __u16 pad1; __u32 vendor; __u32 product; kernel_ulong_t driver_data diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h index ba63858056c7..e0a9b207920d 100644 --- a/include/linux/msdos_fs.h +++ b/include/linux/msdos_fs.h @@ -46,11 +46,6 @@ #define DELETED_FLAG 0xe5 /* marks file as deleted when in name[0] */ #define IS_FREE(n) (!*(n) || *(n) == DELETED_FLAG) -/* valid file mode bits */ -#define MSDOS_VALID_MODE (S_IFREG | S_IFDIR | S_IRWXU | S_IRWXG | S_IRWXO) -/* Convert attribute bits and a mask to the UNIX mode. */ -#define MSDOS_MKMODE(a, m) (m & (a & ATTR_RO ? S_IRUGO|S_IXUGO : S_IRWXUGO)) - #define MSDOS_NAME 11 /* maximum name length */ #define MSDOS_LONGNAME 256 /* maximum name length */ #define MSDOS_SLOTS 21 /* max # of slots for short and long names */ @@ -167,282 +162,10 @@ struct msdos_dir_slot { }; #ifdef __KERNEL__ - -#include -#include -#include -#include -#include - -/* - * vfat shortname flags - */ -#define VFAT_SFN_DISPLAY_LOWER 0x0001 /* convert to lowercase for display */ -#define VFAT_SFN_DISPLAY_WIN95 0x0002 /* emulate win95 rule for display */ -#define VFAT_SFN_DISPLAY_WINNT 0x0004 /* emulate winnt rule for display */ -#define VFAT_SFN_CREATE_WIN95 0x0100 /* emulate win95 rule for create */ -#define VFAT_SFN_CREATE_WINNT 0x0200 /* emulate winnt rule for create */ - -struct fat_mount_options { - uid_t fs_uid; - gid_t fs_gid; - unsigned short fs_fmask; - unsigned short fs_dmask; - unsigned short codepage; /* Codepage for shortname conversions */ - char *iocharset; /* Charset used for filename input/display */ - unsigned short shortname; /* flags for shortname display/create rule */ - unsigned char name_check; /* r = relaxed, n = normal, s = strict */ - unsigned short allow_utime;/* permission for setting the [am]time */ - unsigned quiet:1, /* set = fake successful chmods and chowns */ - showexec:1, /* set = only set x bit for com/exe/bat */ - sys_immutable:1, /* set = system files are immutable */ - dotsOK:1, /* set = hidden and system files are named '.filename' */ - isvfat:1, /* 0=no vfat long filename support, 1=vfat support */ - utf8:1, /* Use of UTF-8 character set (Default) */ - unicode_xlate:1, /* create escape sequences for unhandled Unicode */ - numtail:1, /* Does first alias have a numeric '~1' type tail? */ - flush:1, /* write things quickly */ - nocase:1, /* Does this need case conversion? 0=need case conversion*/ - usefree:1, /* Use free_clusters for FAT32 */ - tz_utc:1; /* Filesystem timestamps are in UTC */ -}; - -#define FAT_HASH_BITS 8 -#define FAT_HASH_SIZE (1UL << FAT_HASH_BITS) -#define FAT_HASH_MASK (FAT_HASH_SIZE-1) - -/* - * MS-DOS file system in-core superblock data - */ -struct msdos_sb_info { - unsigned short sec_per_clus; /* sectors/cluster */ - unsigned short cluster_bits; /* log2(cluster_size) */ - unsigned int cluster_size; /* cluster size */ - unsigned char fats,fat_bits; /* number of FATs, FAT bits (12 or 16) */ - unsigned short fat_start; - unsigned long fat_length; /* FAT start & length (sec.) */ - unsigned long dir_start; - unsigned short dir_entries; /* root dir start & entries */ - unsigned long data_start; /* first data sector */ - unsigned long max_cluster; /* maximum cluster number */ - unsigned long root_cluster; /* first cluster of the root directory */ - unsigned long fsinfo_sector; /* sector number of FAT32 fsinfo */ - struct mutex fat_lock; - unsigned int prev_free; /* previously allocated cluster number */ - unsigned int free_clusters; /* -1 if undefined */ - unsigned int free_clus_valid; /* is free_clusters valid? */ - struct fat_mount_options options; - struct nls_table *nls_disk; /* Codepage used on disk */ - struct nls_table *nls_io; /* Charset used for input and display */ - const void *dir_ops; /* Opaque; default directory operations */ - int dir_per_block; /* dir entries per block */ - int dir_per_block_bits; /* log2(dir_per_block) */ - - int fatent_shift; - struct fatent_operations *fatent_ops; - - spinlock_t inode_hash_lock; - struct hlist_head inode_hashtable[FAT_HASH_SIZE]; -}; - -#define FAT_CACHE_VALID 0 /* special case for valid cache */ - -/* - * MS-DOS file system inode data in memory - */ -struct msdos_inode_info { - spinlock_t cache_lru_lock; - struct list_head cache_lru; - int nr_caches; - /* for avoiding the race between fat_free() and fat_get_cluster() */ - unsigned int cache_valid_id; - - loff_t mmu_private; - int i_start; /* first cluster or 0 */ - int i_logstart; /* logical first cluster */ - int i_attrs; /* unused attribute bits */ - loff_t i_pos; /* on-disk position of directory entry or 0 */ - struct hlist_node i_fat_hash; /* hash by i_location */ - struct inode vfs_inode; -}; - -struct fat_slot_info { - loff_t i_pos; /* on-disk position of directory entry */ - loff_t slot_off; /* offset for slot or de start */ - int nr_slots; /* number of slots + 1(de) in filename */ - struct msdos_dir_entry *de; - struct buffer_head *bh; -}; - -static inline struct msdos_sb_info *MSDOS_SB(struct super_block *sb) -{ - return sb->s_fs_info; -} - -static inline struct msdos_inode_info *MSDOS_I(struct inode *inode) -{ - return container_of(inode, struct msdos_inode_info, vfs_inode); -} - -/* Return the FAT attribute byte for this inode */ -static inline u8 fat_attr(struct inode *inode) -{ - return ((inode->i_mode & S_IWUGO) ? ATTR_NONE : ATTR_RO) | - (S_ISDIR(inode->i_mode) ? ATTR_DIR : ATTR_NONE) | - MSDOS_I(inode)->i_attrs; -} - -static inline unsigned char fat_checksum(const __u8 *name) -{ - unsigned char s = name[0]; - s = (s<<7) + (s>>1) + name[1]; s = (s<<7) + (s>>1) + name[2]; - s = (s<<7) + (s>>1) + name[3]; s = (s<<7) + (s>>1) + name[4]; - s = (s<<7) + (s>>1) + name[5]; s = (s<<7) + (s>>1) + name[6]; - s = (s<<7) + (s>>1) + name[7]; s = (s<<7) + (s>>1) + name[8]; - s = (s<<7) + (s>>1) + name[9]; s = (s<<7) + (s>>1) + name[10]; - return s; -} - -static inline sector_t fat_clus_to_blknr(struct msdos_sb_info *sbi, int clus) -{ - return ((sector_t)clus - FAT_START_ENT) * sbi->sec_per_clus - + sbi->data_start; -} - -static inline void fat16_towchar(wchar_t *dst, const __u8 *src, size_t len) -{ -#ifdef __BIG_ENDIAN - while (len--) { - *dst++ = src[0] | (src[1] << 8); - src += 2; - } -#else - memcpy(dst, src, len * 2); -#endif -} - -static inline void fatwchar_to16(__u8 *dst, const wchar_t *src, size_t len) -{ -#ifdef __BIG_ENDIAN - while (len--) { - dst[0] = *src & 0x00FF; - dst[1] = (*src & 0xFF00) >> 8; - dst += 2; - src++; - } -#else - memcpy(dst, src, len * 2); -#endif -} - /* media of boot sector */ static inline int fat_valid_media(u8 media) { return 0xf8 <= media || media == 0xf0; } - -/* fat/cache.c */ -extern void fat_cache_inval_inode(struct inode *inode); -extern int fat_get_cluster(struct inode *inode, int cluster, - int *fclus, int *dclus); -extern int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys, - unsigned long *mapped_blocks); - -/* fat/dir.c */ -extern const struct file_operations fat_dir_operations; -extern int fat_search_long(struct inode *inode, const unsigned char *name, - int name_len, struct fat_slot_info *sinfo); -extern int fat_dir_empty(struct inode *dir); -extern int fat_subdirs(struct inode *dir); -extern int fat_scan(struct inode *dir, const unsigned char *name, - struct fat_slot_info *sinfo); -extern int fat_get_dotdot_entry(struct inode *dir, struct buffer_head **bh, - struct msdos_dir_entry **de, loff_t *i_pos); -extern int fat_alloc_new_dir(struct inode *dir, struct timespec *ts); -extern int fat_add_entries(struct inode *dir, void *slots, int nr_slots, - struct fat_slot_info *sinfo); -extern int fat_remove_entries(struct inode *dir, struct fat_slot_info *sinfo); - -/* fat/fatent.c */ -struct fat_entry { - int entry; - union { - u8 *ent12_p[2]; - __le16 *ent16_p; - __le32 *ent32_p; - } u; - int nr_bhs; - struct buffer_head *bhs[2]; -}; - -static inline void fatent_init(struct fat_entry *fatent) -{ - fatent->nr_bhs = 0; - fatent->entry = 0; - fatent->u.ent32_p = NULL; - fatent->bhs[0] = fatent->bhs[1] = NULL; -} - -static inline void fatent_set_entry(struct fat_entry *fatent, int entry) -{ - fatent->entry = entry; - fatent->u.ent32_p = NULL; -} - -static inline void fatent_brelse(struct fat_entry *fatent) -{ - int i; - fatent->u.ent32_p = NULL; - for (i = 0; i < fatent->nr_bhs; i++) - brelse(fatent->bhs[i]); - fatent->nr_bhs = 0; - fatent->bhs[0] = fatent->bhs[1] = NULL; -} - -extern void fat_ent_access_init(struct super_block *sb); -extern int fat_ent_read(struct inode *inode, struct fat_entry *fatent, - int entry); -extern int fat_ent_write(struct inode *inode, struct fat_entry *fatent, - int new, int wait); -extern int fat_alloc_clusters(struct inode *inode, int *cluster, - int nr_cluster); -extern int fat_free_clusters(struct inode *inode, int cluster); -extern int fat_count_free_clusters(struct super_block *sb); - -/* fat/file.c */ -extern int fat_generic_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern const struct file_operations fat_file_operations; -extern const struct inode_operations fat_file_inode_operations; -extern int fat_setattr(struct dentry * dentry, struct iattr * attr); -extern void fat_truncate(struct inode *inode); -extern int fat_getattr(struct vfsmount *mnt, struct dentry *dentry, - struct kstat *stat); - -/* fat/inode.c */ -extern void fat_attach(struct inode *inode, loff_t i_pos); -extern void fat_detach(struct inode *inode); -extern struct inode *fat_iget(struct super_block *sb, loff_t i_pos); -extern struct inode *fat_build_inode(struct super_block *sb, - struct msdos_dir_entry *de, loff_t i_pos); -extern int fat_sync_inode(struct inode *inode); -extern int fat_fill_super(struct super_block *sb, void *data, int silent, - const struct inode_operations *fs_dir_inode_ops, int isvfat); - -extern int fat_flush_inodes(struct super_block *sb, struct inode *i1, - struct inode *i2); -/* fat/misc.c */ -extern void fat_fs_panic(struct super_block *s, const char *fmt, ...); -extern void fat_clusters_flush(struct super_block *sb); -extern int fat_chain_add(struct inode *inode, int new_dclus, int nr_cluster); -extern int date_dos2unix(unsigned short time, unsigned short date, int tz_utc); -extern void fat_date_unix2dos(int unix_date, __le16 *time, __le16 *date, - int tz_utc); -extern int fat_sync_bhs(struct buffer_head **bhs, int nr_bhs); - -int fat_cache_init(void); -void fat_cache_destroy(void); - -#endif /* __KERNEL__ */ - -#endif +#endif /* !__KERNEL__ */ +#endif /* !_LINUX_MSDOS_FS_H */ diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index ee5124ec319e..00e2b575021f 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -282,9 +282,25 @@ struct cfi_private { /* * Returns the command address according to the given geometry. */ -static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int type) +static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, + struct map_info *map, struct cfi_private *cfi) { - return (cmd_ofs * type) * interleave; + unsigned bankwidth = map_bankwidth(map); + unsigned interleave = cfi_interleave(cfi); + unsigned type = cfi->device_type; + uint32_t addr; + + addr = (cmd_ofs * type) * interleave; + + /* Modify the unlock address if we are in compatiblity mode. + * For 16bit devices on 8 bit busses + * and 32bit devices on 16 bit busses + * set the low bit of the alternating bit sequence of the address. + */ + if (((type * interleave) > bankwidth) && ((uint8_t)cmd_ofs == 0xaa)) + addr |= (type >> 1)*interleave; + + return addr; } /* @@ -430,7 +446,7 @@ static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t int type, map_word *prev_val) { map_word val; - uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type); + uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi); val = cfi_build_cmd(cmd, map, cfi); if (prev_val) diff --git a/include/linux/net.h b/include/linux/net.h index 6dc14a240042..4515efae4c39 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -40,7 +40,7 @@ #define SYS_GETSOCKOPT 15 /* sys_getsockopt(2) */ #define SYS_SENDMSG 16 /* sys_sendmsg(2) */ #define SYS_RECVMSG 17 /* sys_recvmsg(2) */ -#define SYS_PACCEPT 18 /* sys_paccept(2) */ +#define SYS_ACCEPT4 18 /* sys_accept4(2) */ typedef enum { SS_FREE = 0, /* not allocated */ @@ -100,7 +100,7 @@ enum sock_type { * remaining bits are used as flags. */ #define SOCK_TYPE_MASK 0xf -/* Flags for socket, socketpair, paccept */ +/* Flags for socket, socketpair, accept4 */ #define SOCK_CLOEXEC O_CLOEXEC #ifndef SOCK_NONBLOCK #define SOCK_NONBLOCK O_NONBLOCK @@ -223,8 +223,6 @@ extern int sock_map_fd(struct socket *sock, int flags); extern struct socket *sockfd_lookup(int fd, int *err); #define sockfd_put(sock) fput(sock->file) extern int net_ratelimit(void); -extern long do_accept(int fd, struct sockaddr __user *upeer_sockaddr, - int __user *upeer_addrlen, int flags); #define net_random() random32() #define net_srandom(seed) srandom32((__force u32)seed) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index c8bcb59adfdf..e26f54952892 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -319,6 +319,7 @@ enum { NAPI_STATE_SCHED, /* Poll is scheduled */ NAPI_STATE_DISABLE, /* Disable pending */ + NAPI_STATE_NPSVC, /* Netpoll - don't dequeue from poll_list */ }; extern void __napi_schedule(struct napi_struct *n); @@ -1497,6 +1498,12 @@ static inline void netif_rx_complete(struct net_device *dev, { unsigned long flags; + /* + * don't let napi dequeue from the cpu poll list + * just in case its running on a different cpu + */ + if (unlikely(test_bit(NAPI_STATE_NPSVC, &napi->state))) + return; local_irq_save(flags); __netif_rx_complete(dev, napi); local_irq_restore(flags); @@ -1537,7 +1544,6 @@ static inline void __netif_tx_unlock_bh(struct netdev_queue *txq) /** * netif_tx_lock - grab network device transmit lock * @dev: network device - * @cpu: cpu number of lock owner * * Get network device transmit lock */ diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h index c19595c89304..29fe9ea1d346 100644 --- a/include/linux/netfilter/nfnetlink_conntrack.h +++ b/include/linux/netfilter/nfnetlink_conntrack.h @@ -141,6 +141,7 @@ enum ctattr_protonat { #define CTA_PROTONAT_MAX (__CTA_PROTONAT_MAX - 1) enum ctattr_natseq { + CTA_NAT_SEQ_UNSPEC, CTA_NAT_SEQ_CORRECTION_POS, CTA_NAT_SEQ_OFFSET_BEFORE, CTA_NAT_SEQ_OFFSET_AFTER, diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index be41b609c88f..e52ce475d19f 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -251,7 +251,7 @@ struct xt_target_param { */ struct xt_tgchk_param { const char *table; - void *entryinfo; + const void *entryinfo; const struct xt_target *target; void *targinfo; unsigned int hook_mask; diff --git a/include/linux/page_cgroup.h b/include/linux/page_cgroup.h index f546ad6fc028..1e6d34bfa094 100644 --- a/include/linux/page_cgroup.h +++ b/include/linux/page_cgroup.h @@ -17,7 +17,7 @@ struct page_cgroup { struct list_head lru; /* per cgroup LRU list */ }; -void __init pgdat_page_cgroup_init(struct pglist_data *pgdat); +void __meminit pgdat_page_cgroup_init(struct pglist_data *pgdat); void __init page_cgroup_init(void); struct page_cgroup *lookup_page_cgroup(struct page *page); @@ -91,7 +91,7 @@ static inline void unlock_page_cgroup(struct page_cgroup *pc) #else /* CONFIG_CGROUP_MEM_RES_CTLR */ struct page_cgroup; -static inline void pgdat_page_cgroup_init(struct pglist_data *pgdat) +static inline void __meminit pgdat_page_cgroup_init(struct pglist_data *pgdat) { } diff --git a/include/linux/pci.h b/include/linux/pci.h index 9194adf82e20..03b0b8c3c81b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1142,7 +1142,7 @@ static inline void pci_mmcfg_late_init(void) { } #endif #ifdef CONFIG_HAS_IOMEM -static inline void * pci_ioremap_bar(struct pci_dev *pdev, int bar) +static inline void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) { /* * Make sure the BAR is actually a memory resource, not an IO resource diff --git a/include/linux/phonet.h b/include/linux/phonet.h index c9609f9aedac..4157faa857b6 100644 --- a/include/linux/phonet.h +++ b/include/linux/phonet.h @@ -72,6 +72,7 @@ struct phonetmsg { } pn_msg_u; }; #define PN_COMMON_MESSAGE 0xF0 +#define PN_COMMGR 0x10 #define PN_PREFIX 0xE0 /* resource for extended messages */ #define pn_submsg_id pn_msg_u.base.pn_submsg_id #define pn_e_submsg_id pn_msg_u.ext.pn_e_submsg_id diff --git a/include/linux/raid/md_k.h b/include/linux/raid/md_k.h index c200b9a34aff..8fc909ef6787 100644 --- a/include/linux/raid/md_k.h +++ b/include/linux/raid/md_k.h @@ -115,6 +115,9 @@ struct mdk_rdev_s * in superblock. */ struct work_struct del_work; /* used for delayed sysfs removal */ + + struct sysfs_dirent *sysfs_state; /* handle for 'state' + * sysfs entry */ }; struct mddev_s @@ -128,7 +131,6 @@ struct mddev_s #define MD_CHANGE_DEVS 0 /* Some device status has changed */ #define MD_CHANGE_CLEAN 1 /* transition to or from 'clean' */ #define MD_CHANGE_PENDING 2 /* superblock update in progress */ -#define MD_NOTIFY_ARRAY_STATE 3 /* atomic context wants to notify userspace */ int ro; @@ -239,6 +241,10 @@ struct mddev_s sector_t resync_max; /* resync should pause * when it gets here */ + struct sysfs_dirent *sysfs_state; /* handle for 'array_state' + * file in sysfs. + */ + spinlock_t write_lock; wait_queue_head_t sb_wait; /* for waiting on superblock updates */ atomic_t pending_writes; /* number of active superblock writes */ diff --git a/include/linux/ratelimit.h b/include/linux/ratelimit.h index 18a5b9ba9d40..00044b856453 100644 --- a/include/linux/ratelimit.h +++ b/include/linux/ratelimit.h @@ -17,11 +17,4 @@ struct ratelimit_state { struct ratelimit_state name = {interval, burst,} extern int __ratelimit(struct ratelimit_state *rs); - -static inline int ratelimit(void) -{ - static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, - DEFAULT_RATELIMIT_BURST); - return __ratelimit(&rs); -} #endif diff --git a/include/linux/resource.h b/include/linux/resource.h index aaa423a6f3d9..40fc7e626082 100644 --- a/include/linux/resource.h +++ b/include/linux/resource.h @@ -59,10 +59,10 @@ struct rlimit { #define _STK_LIM (8*1024*1024) /* - * GPG wants 32kB of mlocked memory, to make sure pass phrases + * GPG2 wants 64kB of mlocked memory, to make sure pass phrases * and other sensitive information are never written to disk. */ -#define MLOCK_LIMIT (8 * PAGE_SIZE) +#define MLOCK_LIMIT ((PAGE_SIZE > 64*1024) ? PAGE_SIZE : 64*1024) /* * Due to binary compatibility, the actual resource numbers diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h index 536b0ca46a03..e097c2e6b6dc 100644 --- a/include/linux/ring_buffer.h +++ b/include/linux/ring_buffer.h @@ -120,6 +120,9 @@ unsigned long ring_buffer_overruns(struct ring_buffer *buffer); u64 ring_buffer_time_stamp(int cpu); void ring_buffer_normalize_time_stamp(int cpu, u64 *ts); +void tracing_on(void); +void tracing_off(void); + enum ring_buffer_flags { RB_FL_OVERWRITE = 1 << 0, }; diff --git a/include/linux/sched.h b/include/linux/sched.h index 8478f334d732..55e30d114477 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -247,6 +247,7 @@ extern void init_idle(struct task_struct *idle, int cpu); extern void init_idle_bootup_task(struct task_struct *idle); extern int runqueue_is_locked(void); +extern void task_rq_unlock_wait(struct task_struct *p); extern cpumask_t nohz_cpu_mask; #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ) @@ -629,6 +630,10 @@ struct user_struct { atomic_t inotify_watches; /* How many inotify watches does this user have? */ atomic_t inotify_devs; /* How many inotify devs does this user have opened? */ #endif +#ifdef CONFIG_EPOLL + atomic_t epoll_devs; /* The number of epoll descriptors currently open */ + atomic_t epoll_watches; /* The number of file descriptors currently watched */ +#endif #ifdef CONFIG_POSIX_MQUEUE /* protected by mq_lock */ unsigned long mq_bytes; /* How many bytes can be allocated to mqueue? */ @@ -936,7 +941,6 @@ struct sched_class { void (*enqueue_task) (struct rq *rq, struct task_struct *p, int wakeup); void (*dequeue_task) (struct rq *rq, struct task_struct *p, int sleep); void (*yield_task) (struct rq *rq); - int (*select_task_rq)(struct task_struct *p, int sync); void (*check_preempt_curr) (struct rq *rq, struct task_struct *p, int sync); @@ -944,6 +948,8 @@ struct sched_class { void (*put_prev_task) (struct rq *rq, struct task_struct *p); #ifdef CONFIG_SMP + int (*select_task_rq)(struct task_struct *p, int sync); + unsigned long (*load_balance) (struct rq *this_rq, int this_cpu, struct rq *busiest, unsigned long max_load_move, struct sched_domain *sd, enum cpu_idle_type idle, @@ -955,16 +961,17 @@ struct sched_class { void (*pre_schedule) (struct rq *this_rq, struct task_struct *task); void (*post_schedule) (struct rq *this_rq); void (*task_wake_up) (struct rq *this_rq, struct task_struct *task); -#endif - void (*set_curr_task) (struct rq *rq); - void (*task_tick) (struct rq *rq, struct task_struct *p, int queued); - void (*task_new) (struct rq *rq, struct task_struct *p); void (*set_cpus_allowed)(struct task_struct *p, const cpumask_t *newmask); void (*rq_online)(struct rq *rq); void (*rq_offline)(struct rq *rq); +#endif + + void (*set_curr_task) (struct rq *rq); + void (*task_tick) (struct rq *rq, struct task_struct *p, int queued); + void (*task_new) (struct rq *rq, struct task_struct *p); void (*switched_from) (struct rq *this_rq, struct task_struct *task, int running); @@ -1347,6 +1354,8 @@ struct task_struct { */ unsigned long timer_slack_ns; unsigned long default_timer_slack_ns; + + struct list_head *scm_work_list; }; /* diff --git a/include/linux/security.h b/include/linux/security.h index f5c4a51eb42e..e3d4ecda2673 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -1585,6 +1585,7 @@ int security_syslog(int type); int security_settime(struct timespec *ts, struct timezone *tz); int security_vm_enough_memory(long pages); int security_vm_enough_memory_mm(struct mm_struct *mm, long pages); +int security_vm_enough_memory_kern(long pages); int security_bprm_alloc(struct linux_binprm *bprm); void security_bprm_free(struct linux_binprm *bprm); void security_bprm_apply_creds(struct linux_binprm *bprm, int unsafe); @@ -1817,14 +1818,23 @@ static inline int security_settime(struct timespec *ts, struct timezone *tz) static inline int security_vm_enough_memory(long pages) { + WARN_ON(current->mm == NULL); return cap_vm_enough_memory(current->mm, pages); } static inline int security_vm_enough_memory_mm(struct mm_struct *mm, long pages) { + WARN_ON(mm == NULL); return cap_vm_enough_memory(mm, pages); } +static inline int security_vm_enough_memory_kern(long pages) +{ + /* If current->mm is a kernel thread then we will pass NULL, + for this specific case that is fine */ + return cap_vm_enough_memory(current->mm, pages); +} + static inline int security_bprm_alloc(struct linux_binprm *bprm) { return 0; diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index e27f216361fc..4e4f1277f3bf 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -155,6 +155,9 @@ #define PORT_SC26XX 82 +/* SH-SCI */ +#define PORT_SCIFA 83 + #ifdef __KERNEL__ #include diff --git a/include/linux/slab.h b/include/linux/slab.h index ba965c84ae06..000da12b5cf0 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -23,6 +23,34 @@ #define SLAB_CACHE_DMA 0x00004000UL /* Use GFP_DMA memory */ #define SLAB_STORE_USER 0x00010000UL /* DEBUG: Store the last owner for bug hunting */ #define SLAB_PANIC 0x00040000UL /* Panic if kmem_cache_create() fails */ +/* + * SLAB_DESTROY_BY_RCU - **WARNING** READ THIS! + * + * This delays freeing the SLAB page by a grace period, it does _NOT_ + * delay object freeing. This means that if you do kmem_cache_free() + * that memory location is free to be reused at any time. Thus it may + * be possible to see another object there in the same RCU grace period. + * + * This feature only ensures the memory location backing the object + * stays valid, the trick to using this is relying on an independent + * object validation pass. Something like: + * + * rcu_read_lock() + * again: + * obj = lockless_lookup(key); + * if (obj) { + * if (!try_get_ref(obj)) // might fail for free objects + * goto again; + * + * if (obj->key != key) { // not the object we expected + * put_ref(obj); + * goto again; + * } + * } + * rcu_read_unlock(); + * + * See also the comment on struct slab_rcu in mm/slab.c. + */ #define SLAB_DESTROY_BY_RCU 0x00080000UL /* Defer freeing slabs to RCU */ #define SLAB_MEM_SPREAD 0x00100000UL /* Spread some memory over cpuset */ #define SLAB_TRACE 0x00200000UL /* Trace allocations and frees */ diff --git a/include/linux/smp.h b/include/linux/smp.h index 2e4d58b26c06..6e7ba16ff454 100644 --- a/include/linux/smp.h +++ b/include/linux/smp.h @@ -64,8 +64,17 @@ extern void smp_cpus_done(unsigned int max_cpus); * Call a function on all other processors */ int smp_call_function(void(*func)(void *info), void *info, int wait); +/* Deprecated: use smp_call_function_many() which uses a cpumask ptr. */ int smp_call_function_mask(cpumask_t mask, void(*func)(void *info), void *info, int wait); + +static inline void smp_call_function_many(const struct cpumask *mask, + void (*func)(void *info), void *info, + int wait) +{ + smp_call_function_mask(*mask, func, info, wait); +} + int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, int wait); void __smp_call_function_single(int cpuid, struct call_single_data *data); @@ -137,6 +146,8 @@ static inline void smp_send_reschedule(int cpu) { } }) #define smp_call_function_mask(mask, func, info, wait) \ (up_smp_call_function(func, info)) +#define smp_call_function_many(mask, func, info, wait) \ + (up_smp_call_function(func, info)) static inline void init_call_single_data(void) { } diff --git a/include/linux/spi/spi_bitbang.h b/include/linux/spi/spi_bitbang.h index b8db32cea1de..bf8de281b4ed 100644 --- a/include/linux/spi/spi_bitbang.h +++ b/include/linux/spi/spi_bitbang.h @@ -18,6 +18,9 @@ * duplex (MicroWire) controllers. Provide chipslect() and txrx_bufs(), * and custom setup()/cleanup() methods. */ + +#include + struct spi_bitbang { struct workqueue_struct *workqueue; struct work_struct work; diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index e530026eedf7..17d9b58f6379 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h @@ -427,12 +427,16 @@ static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr) { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST return pci_dma_mapping_error(dev->bus->host_pci, addr); +#endif + break; case SSB_BUSTYPE_SSB: return dma_mapping_error(dev->dev, addr); default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); return -ENOSYS; } @@ -441,12 +445,16 @@ static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p, { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST return pci_map_single(dev->bus->host_pci, p, size, dir); +#endif + break; case SSB_BUSTYPE_SSB: return dma_map_single(dev->dev, p, size, dir); default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); return 0; } @@ -455,14 +463,18 @@ static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_a { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir); return; +#endif + break; case SSB_BUSTYPE_SSB: dma_unmap_single(dev->dev, dma_addr, size, dir); return; default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); } static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev, @@ -472,15 +484,19 @@ static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev, { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr, size, dir); return; +#endif + break; case SSB_BUSTYPE_SSB: dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir); return; default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); } static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev, @@ -490,15 +506,19 @@ static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev, { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr, size, dir); return; +#endif + break; case SSB_BUSTYPE_SSB: dma_sync_single_for_device(dev->dev, dma_addr, size, dir); return; default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); } static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev, @@ -509,17 +529,21 @@ static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev, { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST /* Just sync everything. That's all the PCI API can do. */ pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr, offset + size, dir); return; +#endif + break; case SSB_BUSTYPE_SSB: dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset, size, dir); return; default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); } static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev, @@ -530,17 +554,21 @@ static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev, { switch (dev->bus->bustype) { case SSB_BUSTYPE_PCI: +#ifdef CONFIG_SSB_PCIHOST /* Just sync everything. That's all the PCI API can do. */ pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr, offset + size, dir); return; +#endif + break; case SSB_BUSTYPE_SSB: dma_sync_single_range_for_device(dev->dev, dma_addr, offset, size, dir); return; default: - __ssb_dma_not_implemented(dev); + break; } + __ssb_dma_not_implemented(dev); } diff --git a/include/linux/string.h b/include/linux/string.h index 810d80df0a1d..d18fc198aa2f 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -1,7 +1,7 @@ #ifndef _LINUX_STRING_H_ #define _LINUX_STRING_H_ -/* We don't want strings.h stuff being user by user stuff by accident */ +/* We don't want strings.h stuff being used by user stuff by accident */ #ifndef __KERNEL__ #include diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index d6ff145919ca..04fb47bfb920 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -410,8 +410,7 @@ asmlinkage long sys_getsockopt(int fd, int level, int optname, asmlinkage long sys_bind(int, struct sockaddr __user *, int); asmlinkage long sys_connect(int, struct sockaddr __user *, int); asmlinkage long sys_accept(int, struct sockaddr __user *, int __user *); -asmlinkage long sys_paccept(int, struct sockaddr __user *, int __user *, - const __user sigset_t *, size_t, int); +asmlinkage long sys_accept4(int, struct sockaddr __user *, int __user *, int); asmlinkage long sys_getsockname(int, struct sockaddr __user *, int __user *); asmlinkage long sys_getpeername(int, struct sockaddr __user *, int __user *); asmlinkage long sys_send(int, void __user *, size_t, unsigned); diff --git a/include/linux/telephony.h b/include/linux/telephony.h index 5b2b6261f193..f63afe330add 100644 --- a/include/linux/telephony.h +++ b/include/linux/telephony.h @@ -14,7 +14,7 @@ * Authors: Ed Okerson, * Greg Herlein, * - * Contributors: Alan Cox, + * Contributors: Alan Cox, * David W. Erhart, * * IN NO EVENT SHALL QUICKNET TECHNOLOGIES, INC. BE LIABLE TO ANY PARTY FOR diff --git a/include/linux/timer.h b/include/linux/timer.h index d4ba79248a27..daf9685b861c 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -186,4 +186,9 @@ unsigned long __round_jiffies_relative(unsigned long j, int cpu); unsigned long round_jiffies(unsigned long j); unsigned long round_jiffies_relative(unsigned long j); +unsigned long __round_jiffies_up(unsigned long j, int cpu); +unsigned long __round_jiffies_up_relative(unsigned long j, int cpu); +unsigned long round_jiffies_up(unsigned long j); +unsigned long round_jiffies_up_relative(unsigned long j); + #endif diff --git a/include/linux/topology.h b/include/linux/topology.h index 2158fc0d5a56..117f1b7405cf 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -99,7 +99,7 @@ void arch_update_cpu_topology(void); | SD_BALANCE_FORK \ | SD_BALANCE_EXEC \ | SD_WAKE_AFFINE \ - | SD_WAKE_IDLE \ + | SD_WAKE_BALANCE \ | SD_SHARE_CPUPOWER, \ .last_balance = jiffies, \ .balance_interval = 1, \ @@ -120,10 +120,10 @@ void arch_update_cpu_topology(void); .wake_idx = 1, \ .forkexec_idx = 1, \ .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_NEWIDLE \ | SD_BALANCE_FORK \ | SD_BALANCE_EXEC \ | SD_WAKE_AFFINE \ + | SD_WAKE_BALANCE \ | SD_SHARE_PKG_RESOURCES\ | BALANCE_FOR_MC_POWER, \ .last_balance = jiffies, \ @@ -146,10 +146,10 @@ void arch_update_cpu_topology(void); .wake_idx = 1, \ .forkexec_idx = 1, \ .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_NEWIDLE \ - | SD_BALANCE_FORK \ | SD_BALANCE_EXEC \ + | SD_BALANCE_FORK \ | SD_WAKE_AFFINE \ + | SD_WAKE_BALANCE \ | BALANCE_FOR_PKG_POWER,\ .last_balance = jiffies, \ .balance_interval = 1, \ diff --git a/include/linux/usb.h b/include/linux/usb.h index 8fa973bede5e..f72aa51f7bcd 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -108,6 +108,7 @@ enum usb_interface_condition { * (in probe()), bound to a driver, or unbinding (in disconnect()) * @is_active: flag set when the interface is bound and not suspended. * @sysfs_files_created: sysfs attributes exist + * @unregistering: flag set when the interface is being unregistered * @needs_remote_wakeup: flag set when the driver requires remote-wakeup * capability during autosuspend. * @needs_altsetting0: flag set when a set-interface request for altsetting 0 @@ -163,6 +164,7 @@ struct usb_interface { enum usb_interface_condition condition; /* state of binding */ unsigned is_active:1; /* the interface is not suspended */ unsigned sysfs_files_created:1; /* the sysfs attributes exist */ + unsigned unregistering:1; /* unregistration is in progress */ unsigned needs_remote_wakeup:1; /* driver requires remote wakeup */ unsigned needs_altsetting0:1; /* switch to altsetting 0 is pending */ unsigned needs_binding:1; /* needs delayed unbind/rebind */ diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 73a2f4eb1f7a..9b42baed3900 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -158,8 +158,12 @@ struct usb_ctrlrequest { * (rarely) accepted by SET_DESCRIPTOR. * * Note that all multi-byte values here are encoded in little endian - * byte order "on the wire". But when exposed through Linux-USB APIs, - * they've been converted to cpu byte order. + * byte order "on the wire". Within the kernel and when exposed + * through the Linux-USB APIs, they are not converted to cpu byte + * order; it is the responsibility of the client code to do this. + * The single exception is when device and configuration descriptors (but + * not other descriptors) are read from usbfs (i.e. /proc/bus/usb/BBB/DDD); + * in this case the fields are converted to host endianness by the kernel. */ /* diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index 89a5a1231ffb..b36291130f22 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -240,4 +240,12 @@ void cancel_rearming_delayed_work(struct delayed_work *work) cancel_delayed_work_sync(work); } +#ifndef CONFIG_SMP +static inline long work_on_cpu(unsigned int cpu, long (*fn)(void *), void *arg) +{ + return fn(arg); +} +#else +long work_on_cpu(unsigned int cpu, long (*fn)(void *), void *arg); +#endif /* CONFIG_SMP */ #endif diff --git a/include/net/af_unix.h b/include/net/af_unix.h index 7dd29b7e461d..1614d78c60ed 100644 --- a/include/net/af_unix.h +++ b/include/net/af_unix.h @@ -9,6 +9,7 @@ extern void unix_inflight(struct file *fp); extern void unix_notinflight(struct file *fp); extern void unix_gc(void); +extern void wait_for_unix_gc(void); #define UNIX_HASH_SIZE 256 @@ -54,6 +55,7 @@ struct unix_sock { atomic_long_t inflight; spinlock_t lock; unsigned int gc_candidate : 1; + unsigned int gc_maybe_cycle : 1; wait_queue_head_t peer_wait; }; #define unix_sk(__sk) ((struct unix_sock *)__sk) diff --git a/include/net/irda/irda_device.h b/include/net/irda/irda_device.h index 3025ae17ddbe..94c852d47d0f 100644 --- a/include/net/irda/irda_device.h +++ b/include/net/irda/irda_device.h @@ -135,9 +135,11 @@ struct dongle_reg { /* * Per-packet information we need to hide inside sk_buff - * (must not exceed 48 bytes, check with struct sk_buff) + * (must not exceed 48 bytes, check with struct sk_buff) + * The default_qdisc_pad field is a temporary hack. */ struct irda_skb_cb { + unsigned int default_qdisc_pad; magic_t magic; /* Be sure that we can trust the information */ __u32 next_speed; /* The Speed to be set *after* this frame */ __u16 mtt; /* Minimum turn around time */ diff --git a/include/net/mac80211.h b/include/net/mac80211.h index d861197f83c7..73d81bc6aa75 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -73,14 +73,6 @@ * not do so then mac80211 may add this under certain circumstances. */ -/** - * enum ieee80211_notification_type - Low level driver notification - * @IEEE80211_NOTIFY_RE_ASSOC: start the re-association sequence - */ -enum ieee80211_notification_types { - IEEE80211_NOTIFY_RE_ASSOC, -}; - /** * struct ieee80211_ht_bss_info - describing BSS's HT characteristics * @@ -1474,7 +1466,6 @@ void ieee80211_tx_status_irqsafe(struct ieee80211_hw *hw, * ieee80211_beacon_get - beacon generation function * @hw: pointer obtained from ieee80211_alloc_hw(). * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf. - * @control: will be filled with information needed to send this beacon. * * If the beacon frames are generated by the host system (i.e., not in * hardware/firmware), the low-level driver uses this function to receive @@ -1575,7 +1566,6 @@ __le16 ieee80211_generic_frame_duration(struct ieee80211_hw *hw, * ieee80211_get_buffered_bc - accessing buffered broadcast and multicast frames * @hw: pointer as obtained from ieee80211_alloc_hw(). * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf. - * @control: will be filled with information needed to send returned frame. * * Function for accessing buffered broadcast and multicast frames. If * hardware/firmware does not implement buffering of broadcast/multicast @@ -1623,9 +1613,8 @@ unsigned int ieee80211_hdrlen(__le16 fc); * * @keyconf: the parameter passed with the set key * @skb: the skb for which the key is needed - * @rc4key: a buffer to which the key will be written * @type: TBD - * @key: TBD + * @key: a buffer to which the key will be written */ void ieee80211_get_tkip_key(struct ieee80211_key_conf *keyconf, struct sk_buff *skb, @@ -1726,7 +1715,8 @@ void ieee80211_iterate_active_interfaces_atomic(struct ieee80211_hw *hw, * @hw: pointer as obtained from ieee80211_alloc_hw(). * @ra: receiver address of the BA session recipient * @tid: the TID to BA on. - * @return: success if addBA request was sent, failure otherwise + * + * Return: success if addBA request was sent, failure otherwise * * Although mac80211/low level driver/user space application can estimate * the need to start aggregation on a certain RA/TID, the session level @@ -1764,7 +1754,8 @@ void ieee80211_start_tx_ba_cb_irqsafe(struct ieee80211_hw *hw, const u8 *ra, * @ra: receiver address of the BA session recipient * @tid: the TID to stop BA. * @initiator: if indicates initiator DELBA frame will be sent. - * @return: error if no sta with matching da found, success otherwise + * + * Return: error if no sta with matching da found, success otherwise * * Although mac80211/low level driver/user space application can estimate * the need to stop aggregation on a certain RA/TID, the session level @@ -1798,18 +1789,6 @@ void ieee80211_stop_tx_ba_cb(struct ieee80211_hw *hw, u8 *ra, u8 tid); void ieee80211_stop_tx_ba_cb_irqsafe(struct ieee80211_hw *hw, const u8 *ra, u16 tid); -/** - * ieee80211_notify_mac - low level driver notification - * @hw: pointer as obtained from ieee80211_alloc_hw(). - * @notif_type: enum ieee80211_notification_types - * - * This function must be called by low level driver to inform mac80211 of - * low level driver status change or force mac80211 to re-assoc for low - * level driver internal error that require re-assoc. - */ -void ieee80211_notify_mac(struct ieee80211_hw *hw, - enum ieee80211_notification_types notif_type); - /** * ieee80211_find_sta - find a station * diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index 708009be88b6..700c53a3c6fa 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h @@ -214,6 +214,8 @@ struct pernet_operations { extern int register_pernet_subsys(struct pernet_operations *); extern void unregister_pernet_subsys(struct pernet_operations *); +extern int register_pernet_gen_subsys(int *id, struct pernet_operations *); +extern void unregister_pernet_gen_subsys(int id, struct pernet_operations *); extern int register_pernet_device(struct pernet_operations *); extern void unregister_pernet_device(struct pernet_operations *); extern int register_pernet_gen_device(int *id, struct pernet_operations *); diff --git a/include/net/phonet/phonet.h b/include/net/phonet/phonet.h index d4e72508e145..c6a245184460 100644 --- a/include/net/phonet/phonet.h +++ b/include/net/phonet/phonet.h @@ -27,7 +27,7 @@ * The lower layers may not require more space, ever. Make sure it's * enough. */ -#define MAX_PHONET_HEADER 8 +#define MAX_PHONET_HEADER (8 + MAX_HEADER) /* * Every Phonet* socket has this structure first in its diff --git a/include/net/request_sock.h b/include/net/request_sock.h index cac811e51f6d..c7190846e128 100644 --- a/include/net/request_sock.h +++ b/include/net/request_sock.h @@ -31,6 +31,7 @@ struct request_sock_ops { int family; int obj_size; struct kmem_cache *slab; + char *slab_name; int (*rtx_syn_ack)(struct sock *sk, struct request_sock *req); void (*send_ack)(struct sock *sk, struct sk_buff *skb, diff --git a/include/net/scm.h b/include/net/scm.h index 06df126103ca..33e9986beb86 100644 --- a/include/net/scm.h +++ b/include/net/scm.h @@ -14,8 +14,9 @@ struct scm_fp_list { - int count; - struct file *fp[SCM_MAX_FD]; + struct list_head list; + int count; + struct file *fp[SCM_MAX_FD]; }; struct scm_cookie diff --git a/include/net/sock.h b/include/net/sock.h index ada50c04d09f..2f47107f6d0f 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -815,7 +815,7 @@ static inline void sk_wmem_free_skb(struct sock *sk, struct sk_buff *skb) */ #define sock_lock_init_class_and_name(sk, sname, skey, name, key) \ do { \ - sk->sk_lock.owned = 0; \ + sk->sk_lock.owned = 0; \ init_waitqueue_head(&sk->sk_lock.wq); \ spin_lock_init(&(sk)->sk_lock.slock); \ debug_check_no_locks_freed((void *)&(sk)->sk_lock, \ @@ -936,7 +936,6 @@ extern void sock_init_data(struct socket *sock, struct sock *sk); /** * sk_filter_release: Release a socket filter - * @sk: socket * @fp: filter to remove * * Remove a filter from a socket and release its resources. diff --git a/include/net/timewait_sock.h b/include/net/timewait_sock.h index 1e1ee3253fd8..97c3b14da55d 100644 --- a/include/net/timewait_sock.h +++ b/include/net/timewait_sock.h @@ -16,6 +16,7 @@ struct timewait_sock_ops { struct kmem_cache *twsk_slab; + char *twsk_slab_name; unsigned int twsk_obj_size; int (*twsk_unique)(struct sock *sk, struct sock *sktw, void *twp); diff --git a/include/scsi/scsi_tcq.h b/include/scsi/scsi_tcq.h index cf4c219c0b5c..17231385cb37 100644 --- a/include/scsi/scsi_tcq.h +++ b/include/scsi/scsi_tcq.h @@ -140,8 +140,18 @@ static inline struct scsi_cmnd *scsi_find_tag(struct scsi_device *sdev, int tag) */ static inline int scsi_init_shared_tag_map(struct Scsi_Host *shost, int depth) { - shost->bqt = blk_init_tags(depth); - return shost->bqt ? 0 : -ENOMEM; + /* + * If the shared tag map isn't already initialized, do it now. + * This saves callers from having to check ->bqt when setting up + * devices on the shared host (for libata) + */ + if (!shost->bqt) { + shost->bqt = blk_init_tags(depth); + if (!shost->bqt) + return -ENOMEM; + } + + return 0; } /** diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h index 49d8913c4f86..6e04e6fe79c7 100644 --- a/include/scsi/scsi_transport_fc.h +++ b/include/scsi/scsi_transport_fc.h @@ -357,7 +357,7 @@ struct fc_rport { /* aka fc_starget_attrs */ /* bit field values for struct fc_rport "flags" field: */ #define FC_RPORT_DEVLOSS_PENDING 0x01 #define FC_RPORT_SCAN_PENDING 0x02 -#define FC_RPORT_FAST_FAIL_TIMEDOUT 0x03 +#define FC_RPORT_FAST_FAIL_TIMEDOUT 0x04 #define dev_to_rport(d) \ container_of(d, struct fc_rport, dev) diff --git a/include/sound/core.h b/include/sound/core.h index 35424a971b7a..1508c4ec1ba9 100644 --- a/include/sound/core.h +++ b/include/sound/core.h @@ -385,9 +385,13 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...) #else /* !CONFIG_SND_DEBUG */ -#define snd_printd(fmt, args...) /* nothing */ -#define snd_BUG() /* nothing */ -#define snd_BUG_ON(cond) ({/*(void)(cond);*/ 0;}) /* always false */ +#define snd_printd(fmt, args...) do { } while (0) +#define snd_BUG() do { } while (0) +static inline int __snd_bug_on(void) +{ + return 0; +} +#define snd_BUG_ON(cond) __snd_bug_on() /* always false */ #endif /* CONFIG_SND_DEBUG */ diff --git a/include/sound/soc.h b/include/sound/soc.h index a1e0357a84d7..5e0189876afd 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -28,7 +28,8 @@ */ #define SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert) \ ((unsigned long)&(struct soc_mixer_control) \ - {.reg = xreg, .shift = xshift, .max = xmax, .invert = xinvert}) + {.reg = xreg, .shift = xshift, .rshift = xshift, .max = xmax, \ + .invert = xinvert}) #define SOC_SINGLE_VALUE_EXT(xreg, xmax, xinvert) \ ((unsigned long)&(struct soc_mixer_control) \ {.reg = xreg, .max = xmax, .invert = xinvert}) diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index 6ad87f485992..0c864db1a466 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h @@ -38,7 +38,7 @@ struct atmel_lcdfb_info { spinlock_t lock; struct fb_info *info; void __iomem *mmio; - unsigned long irq_base; + int irq_base; struct work_struct task; unsigned int guard_time; diff --git a/include/video/radeon.h b/include/video/radeon.h index d5dcaf154ba4..1cd09cc5b169 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h @@ -525,9 +525,6 @@ #define CRTC_DISPLAY_DIS (1 << 10) #define CRTC_CRT_ON (1 << 15) -/* DSTCACHE_MODE bits constants */ -#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) -#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17) /* DSTCACHE_CTLSTAT bit constants */ #define RB2D_DC_FLUSH_2D (1 << 0) @@ -869,10 +866,15 @@ #define GMC_DST_16BPP_YVYU422 0x00000c00 #define GMC_DST_32BPP_AYUV444 0x00000e00 #define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 #define GMC_3D_FCN_EN_CLR 0x00000000 #define GMC_3D_FCN_EN_SET 0x08000000 @@ -883,9 +885,6 @@ #define GMC_WRITE_MASK_LEAVE 0x00000000 #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) -#define GMC_SRC_DATATYPE_MASK (3 << 12) -#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) -#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) #define GMC_SRC_DATATYPE_COLOR (3 << 12) #define ROP3_S 0x00cc0000 #define ROP3_SRCCOPY 0x00cc0000 @@ -894,7 +893,6 @@ #define DP_SRC_SOURCE_MASK (7 << 24) #define GMC_BRUSH_NONE (15 << 4) #define DP_SRC_SOURCE_MEMORY (2 << 24) -#define DP_SRC_SOURCE_HOST_DATA (3 << 24) #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 /* DP_MIX bit constants */ @@ -980,12 +978,6 @@ #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) -/* RBBM_GUICNTL constants */ -#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0) -#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0) -#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0) -#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0) - /* masks */ #define CONFIG_MEMSIZE_MASK 0x1f000000 diff --git a/include/xen/interface/event_channel.h b/include/xen/interface/event_channel.h index 919b5bdcb2bd..2090881c3650 100644 --- a/include/xen/interface/event_channel.h +++ b/include/xen/interface/event_channel.h @@ -9,6 +9,8 @@ #ifndef __XEN_PUBLIC_EVENT_CHANNEL_H__ #define __XEN_PUBLIC_EVENT_CHANNEL_H__ +#include + typedef uint32_t evtchn_port_t; DEFINE_GUEST_HANDLE(evtchn_port_t); diff --git a/init/Kconfig b/init/Kconfig index 44e9208f9c78..f763762d544a 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -354,7 +354,7 @@ config RT_GROUP_SCHED setting below. If enabled, it will also make it impossible to schedule realtime tasks for non-root users until you allocate realtime bandwidth for them. - See Documentation/sched-rt-group.txt for more information. + See Documentation/scheduler/sched-rt-group.txt for more information. choice depends on GROUP_SCHED @@ -401,16 +401,20 @@ config CGROUP_MEM_RES_CTLR depends on CGROUPS && RESOURCE_COUNTERS select MM_OWNER help - Provides a memory resource controller that manages both page cache and - RSS memory. + Provides a memory resource controller that manages both anonymous + memory and page cache. (See Documentation/controllers/memory.txt) Note that setting this option increases fixed memory overhead - associated with each page of memory in the system by 4/8 bytes - and also increases cache misses because struct page on many 64bit - systems will not fit into a single cache line anymore. + associated with each page of memory in the system. By this, + 20(40)bytes/PAGE_SIZE on 32(64)bit system will be occupied by memory + usage tracking struct at boot. Total amount of this is printed out + at boot. Only enable when you're ok with these trade offs and really - sure you need the memory resource controller. + sure you need the memory resource controller. Even when you enable + this, you can set "cgroup_disable=memory" at your boot option to + disable memory resource controller and you can avoid overheads. + (and lose benefits of memory resource contoller) This config option also selects MM_OWNER config option, which could in turn add some fork/exit overhead. @@ -767,8 +771,7 @@ config SLAB help The regular slab allocator that is established and known to work well in all environments. It organizes cache hot objects in - per cpu and per node queues. SLAB is the default choice for - a slab allocator. + per cpu and per node queues. config SLUB bool "SLUB (Unqueued Allocator)" @@ -777,7 +780,8 @@ config SLUB instead of managing queues of cached objects (SLAB approach). Per cpu caching is realized using slabs of objects instead of queues of objects. SLUB can use memory efficiently - and has enhanced diagnostics. + and has enhanced diagnostics. SLUB is the default choice for + a slab allocator. config SLOB depends on EMBEDDED diff --git a/init/do_mounts_md.c b/init/do_mounts_md.c index 4c87ee1fe5d3..d6da5cdd3c38 100644 --- a/init/do_mounts_md.c +++ b/init/do_mounts_md.c @@ -1,6 +1,5 @@ - -#include #include +#include #include "do_mounts.h" diff --git a/ipc/util.c b/ipc/util.c index 49b3ea615dc5..361fd1c96fcf 100644 --- a/ipc/util.c +++ b/ipc/util.c @@ -266,9 +266,17 @@ int ipc_addid(struct ipc_ids* ids, struct kern_ipc_perm* new, int size) if (ids->in_use >= size) return -ENOSPC; + spin_lock_init(&new->lock); + new->deleted = 0; + rcu_read_lock(); + spin_lock(&new->lock); + err = idr_get_new(&ids->ipcs_idr, new, &id); - if (err) + if (err) { + spin_unlock(&new->lock); + rcu_read_unlock(); return err; + } ids->in_use++; @@ -280,10 +288,6 @@ int ipc_addid(struct ipc_ids* ids, struct kern_ipc_perm* new, int size) ids->seq = 0; new->id = ipc_buildid(id, new->seq); - spin_lock_init(&new->lock); - new->deleted = 0; - rcu_read_lock(); - spin_lock(&new->lock); return id; } diff --git a/kernel/Makefile b/kernel/Makefile index 305f11dbef21..19fad003b19d 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -11,9 +11,7 @@ obj-y = sched.o fork.o exec_domain.o panic.o printk.o \ hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \ notifier.o ksysfs.o pm_qos_params.o sched_clock.o -CFLAGS_REMOVE_sched.o = -mno-spe - -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER # Do not trace debug files and internal ftrace files CFLAGS_REMOVE_lockdep.o = -pg CFLAGS_REMOVE_lockdep_proc.o = -pg @@ -21,7 +19,7 @@ CFLAGS_REMOVE_mutex-debug.o = -pg CFLAGS_REMOVE_rtmutex-debug.o = -pg CFLAGS_REMOVE_cgroup-debug.o = -pg CFLAGS_REMOVE_sched_clock.o = -pg -CFLAGS_REMOVE_sched.o = -mno-spe -pg +CFLAGS_REMOVE_sched.o = -pg endif obj-$(CONFIG_FREEZER) += freezer.o @@ -88,7 +86,7 @@ obj-$(CONFIG_MARKERS) += marker.o obj-$(CONFIG_TRACEPOINTS) += tracepoint.o obj-$(CONFIG_LATENCYTOP) += latencytop.o obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o -obj-$(CONFIG_FTRACE) += trace/ +obj-$(CONFIG_FUNCTION_TRACER) += trace/ obj-$(CONFIG_TRACING) += trace/ obj-$(CONFIG_SMP) += sched_cpupri.o diff --git a/kernel/audit.c b/kernel/audit.c index 4414e93d8750..ce6d8ea3131e 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -61,8 +61,11 @@ #include "audit.h" -/* No auditing will take place until audit_initialized != 0. +/* No auditing will take place until audit_initialized == AUDIT_INITIALIZED. * (Initialization happens after skb_init is called.) */ +#define AUDIT_DISABLED -1 +#define AUDIT_UNINITIALIZED 0 +#define AUDIT_INITIALIZED 1 static int audit_initialized; #define AUDIT_OFF 0 @@ -965,6 +968,9 @@ static int __init audit_init(void) { int i; + if (audit_initialized == AUDIT_DISABLED) + return 0; + printk(KERN_INFO "audit: initializing netlink socket (%s)\n", audit_default ? "enabled" : "disabled"); audit_sock = netlink_kernel_create(&init_net, NETLINK_AUDIT, 0, @@ -976,7 +982,7 @@ static int __init audit_init(void) skb_queue_head_init(&audit_skb_queue); skb_queue_head_init(&audit_skb_hold_queue); - audit_initialized = 1; + audit_initialized = AUDIT_INITIALIZED; audit_enabled = audit_default; audit_ever_enabled |= !!audit_default; @@ -999,13 +1005,21 @@ __initcall(audit_init); static int __init audit_enable(char *str) { audit_default = !!simple_strtol(str, NULL, 0); - printk(KERN_INFO "audit: %s%s\n", - audit_default ? "enabled" : "disabled", - audit_initialized ? "" : " (after initialization)"); - if (audit_initialized) { + if (!audit_default) + audit_initialized = AUDIT_DISABLED; + + printk(KERN_INFO "audit: %s", audit_default ? "enabled" : "disabled"); + + if (audit_initialized == AUDIT_INITIALIZED) { audit_enabled = audit_default; audit_ever_enabled |= !!audit_default; + } else if (audit_initialized == AUDIT_UNINITIALIZED) { + printk(" (after initialization)"); + } else { + printk(" (until reboot)"); } + printk("\n"); + return 1; } @@ -1107,9 +1121,7 @@ unsigned int audit_serial(void) static inline void audit_get_stamp(struct audit_context *ctx, struct timespec *t, unsigned int *serial) { - if (ctx) - auditsc_get_stamp(ctx, t, serial); - else { + if (!ctx || !auditsc_get_stamp(ctx, t, serial)) { *t = CURRENT_TIME; *serial = audit_serial(); } @@ -1146,7 +1158,7 @@ struct audit_buffer *audit_log_start(struct audit_context *ctx, gfp_t gfp_mask, int reserve; unsigned long timeout_start = jiffies; - if (!audit_initialized) + if (audit_initialized != AUDIT_INITIALIZED) return NULL; if (unlikely(audit_filter_type(type))) diff --git a/kernel/audit_tree.c b/kernel/audit_tree.c index 8ba0e0d934f2..8b509441f49a 100644 --- a/kernel/audit_tree.c +++ b/kernel/audit_tree.c @@ -24,6 +24,7 @@ struct audit_chunk { struct list_head trees; /* with root here */ int dead; int count; + atomic_long_t refs; struct rcu_head head; struct node { struct list_head list; @@ -56,7 +57,8 @@ static LIST_HEAD(prune_list); * tree is refcounted; one reference for "some rules on rules_list refer to * it", one for each chunk with pointer to it. * - * chunk is refcounted by embedded inotify_watch. + * chunk is refcounted by embedded inotify_watch + .refs (non-zero refcount + * of watch contributes 1 to .refs). * * node.index allows to get from node.list to containing chunk. * MSB of that sucker is stolen to mark taggings that we might have to @@ -121,6 +123,7 @@ static struct audit_chunk *alloc_chunk(int count) INIT_LIST_HEAD(&chunk->hash); INIT_LIST_HEAD(&chunk->trees); chunk->count = count; + atomic_long_set(&chunk->refs, 1); for (i = 0; i < count; i++) { INIT_LIST_HEAD(&chunk->owners[i].list); chunk->owners[i].index = i; @@ -129,9 +132,8 @@ static struct audit_chunk *alloc_chunk(int count) return chunk; } -static void __free_chunk(struct rcu_head *rcu) +static void free_chunk(struct audit_chunk *chunk) { - struct audit_chunk *chunk = container_of(rcu, struct audit_chunk, head); int i; for (i = 0; i < chunk->count; i++) { @@ -141,14 +143,16 @@ static void __free_chunk(struct rcu_head *rcu) kfree(chunk); } -static inline void free_chunk(struct audit_chunk *chunk) +void audit_put_chunk(struct audit_chunk *chunk) { - call_rcu(&chunk->head, __free_chunk); + if (atomic_long_dec_and_test(&chunk->refs)) + free_chunk(chunk); } -void audit_put_chunk(struct audit_chunk *chunk) +static void __put_chunk(struct rcu_head *rcu) { - put_inotify_watch(&chunk->watch); + struct audit_chunk *chunk = container_of(rcu, struct audit_chunk, head); + audit_put_chunk(chunk); } enum {HASH_SIZE = 128}; @@ -176,7 +180,7 @@ struct audit_chunk *audit_tree_lookup(const struct inode *inode) list_for_each_entry_rcu(p, list, hash) { if (p->watch.inode == inode) { - get_inotify_watch(&p->watch); + atomic_long_inc(&p->refs); return p; } } @@ -194,17 +198,49 @@ int audit_tree_match(struct audit_chunk *chunk, struct audit_tree *tree) /* tagging and untagging inodes with trees */ -static void untag_chunk(struct audit_chunk *chunk, struct node *p) +static struct audit_chunk *find_chunk(struct node *p) +{ + int index = p->index & ~(1U<<31); + p -= index; + return container_of(p, struct audit_chunk, owners[0]); +} + +static void untag_chunk(struct node *p) { + struct audit_chunk *chunk = find_chunk(p); struct audit_chunk *new; struct audit_tree *owner; int size = chunk->count - 1; int i, j; + if (!pin_inotify_watch(&chunk->watch)) { + /* + * Filesystem is shutting down; all watches are getting + * evicted, just take it off the node list for this + * tree and let the eviction logics take care of the + * rest. + */ + owner = p->owner; + if (owner->root == chunk) { + list_del_init(&owner->same_root); + owner->root = NULL; + } + list_del_init(&p->list); + p->owner = NULL; + put_tree(owner); + return; + } + + spin_unlock(&hash_lock); + + /* + * pin_inotify_watch() succeeded, so the watch won't go away + * from under us. + */ mutex_lock(&chunk->watch.inode->inotify_mutex); if (chunk->dead) { mutex_unlock(&chunk->watch.inode->inotify_mutex); - return; + goto out; } owner = p->owner; @@ -221,7 +257,7 @@ static void untag_chunk(struct audit_chunk *chunk, struct node *p) inotify_evict_watch(&chunk->watch); mutex_unlock(&chunk->watch.inode->inotify_mutex); put_inotify_watch(&chunk->watch); - return; + goto out; } new = alloc_chunk(size); @@ -263,7 +299,7 @@ static void untag_chunk(struct audit_chunk *chunk, struct node *p) inotify_evict_watch(&chunk->watch); mutex_unlock(&chunk->watch.inode->inotify_mutex); put_inotify_watch(&chunk->watch); - return; + goto out; Fallback: // do the best we can @@ -277,6 +313,9 @@ Fallback: put_tree(owner); spin_unlock(&hash_lock); mutex_unlock(&chunk->watch.inode->inotify_mutex); +out: + unpin_inotify_watch(&chunk->watch); + spin_lock(&hash_lock); } static int create_chunk(struct inode *inode, struct audit_tree *tree) @@ -387,13 +426,6 @@ static int tag_chunk(struct inode *inode, struct audit_tree *tree) return 0; } -static struct audit_chunk *find_chunk(struct node *p) -{ - int index = p->index & ~(1U<<31); - p -= index; - return container_of(p, struct audit_chunk, owners[0]); -} - static void kill_rules(struct audit_tree *tree) { struct audit_krule *rule, *next; @@ -431,17 +463,10 @@ static void prune_one(struct audit_tree *victim) spin_lock(&hash_lock); while (!list_empty(&victim->chunks)) { struct node *p; - struct audit_chunk *chunk; p = list_entry(victim->chunks.next, struct node, list); - chunk = find_chunk(p); - get_inotify_watch(&chunk->watch); - spin_unlock(&hash_lock); - - untag_chunk(chunk, p); - put_inotify_watch(&chunk->watch); - spin_lock(&hash_lock); + untag_chunk(p); } spin_unlock(&hash_lock); put_tree(victim); @@ -469,7 +494,6 @@ static void trim_marked(struct audit_tree *tree) while (!list_empty(&tree->chunks)) { struct node *node; - struct audit_chunk *chunk; node = list_entry(tree->chunks.next, struct node, list); @@ -477,14 +501,7 @@ static void trim_marked(struct audit_tree *tree) if (!(node->index & (1U<<31))) break; - chunk = find_chunk(node); - get_inotify_watch(&chunk->watch); - spin_unlock(&hash_lock); - - untag_chunk(chunk, node); - - put_inotify_watch(&chunk->watch); - spin_lock(&hash_lock); + untag_chunk(node); } if (!tree->root && !tree->goner) { tree->goner = 1; @@ -878,7 +895,7 @@ static void handle_event(struct inotify_watch *watch, u32 wd, u32 mask, static void destroy_watch(struct inotify_watch *watch) { struct audit_chunk *chunk = container_of(watch, struct audit_chunk, watch); - free_chunk(chunk); + call_rcu(&chunk->head, __put_chunk); } static const struct inotify_operations rtree_inotify_ops = { diff --git a/kernel/auditfilter.c b/kernel/auditfilter.c index b7d354e2b0ef..9fd85a4640a0 100644 --- a/kernel/auditfilter.c +++ b/kernel/auditfilter.c @@ -1094,8 +1094,8 @@ static void audit_inotify_unregister(struct list_head *in_list) list_for_each_entry_safe(p, n, in_list, ilist) { list_del(&p->ilist); inotify_rm_watch(audit_ih, &p->wdata); - /* the put matching the get in audit_do_del_rule() */ - put_inotify_watch(&p->wdata); + /* the unpin matching the pin in audit_do_del_rule() */ + unpin_inotify_watch(&p->wdata); } } @@ -1389,9 +1389,13 @@ static inline int audit_del_rule(struct audit_entry *entry, /* Put parent on the inotify un-registration * list. Grab a reference before releasing * audit_filter_mutex, to be released in - * audit_inotify_unregister(). */ - list_add(&parent->ilist, &inotify_list); - get_inotify_watch(&parent->wdata); + * audit_inotify_unregister(). + * If filesystem is going away, just leave + * the sucker alone, eviction will take + * care of it. + */ + if (pin_inotify_watch(&parent->wdata)) + list_add(&parent->ilist, &inotify_list); } } } diff --git a/kernel/auditsc.c b/kernel/auditsc.c index cf5bc2f5f9c3..2a3f0afc4d2a 100644 --- a/kernel/auditsc.c +++ b/kernel/auditsc.c @@ -1459,7 +1459,6 @@ void audit_free(struct task_struct *tsk) /** * audit_syscall_entry - fill in an audit record at syscall entry - * @tsk: task being audited * @arch: architecture type * @major: major syscall type (function) * @a1: additional syscall register 1 @@ -1548,9 +1547,25 @@ void audit_syscall_entry(int arch, int major, context->ppid = 0; } +void audit_finish_fork(struct task_struct *child) +{ + struct audit_context *ctx = current->audit_context; + struct audit_context *p = child->audit_context; + if (!p || !ctx || !ctx->auditable) + return; + p->arch = ctx->arch; + p->major = ctx->major; + memcpy(p->argv, ctx->argv, sizeof(ctx->argv)); + p->ctime = ctx->ctime; + p->dummy = ctx->dummy; + p->auditable = ctx->auditable; + p->in_syscall = ctx->in_syscall; + p->filterkey = kstrdup(ctx->filterkey, GFP_KERNEL); + p->ppid = current->pid; +} + /** * audit_syscall_exit - deallocate audit context after a system call - * @tsk: task being audited * @valid: success/failure flag * @return_code: syscall return value * @@ -1942,15 +1957,18 @@ EXPORT_SYMBOL_GPL(__audit_inode_child); * * Also sets the context as auditable. */ -void auditsc_get_stamp(struct audit_context *ctx, +int auditsc_get_stamp(struct audit_context *ctx, struct timespec *t, unsigned int *serial) { + if (!ctx->in_syscall) + return 0; if (!ctx->serial) ctx->serial = audit_serial(); t->tv_sec = ctx->ctime.tv_sec; t->tv_nsec = ctx->ctime.tv_nsec; *serial = ctx->serial; ctx->auditable = 1; + return 1; } /* global counter which is incremented every time something logs in */ diff --git a/kernel/cgroup.c b/kernel/cgroup.c index 35eebd5510c2..8185a0f09594 100644 --- a/kernel/cgroup.c +++ b/kernel/cgroup.c @@ -702,7 +702,7 @@ static int rebind_subsystems(struct cgroupfs_root *root, * any child cgroups exist. This is theoretically supportable * but involves complex error handling, so it's being left until * later */ - if (!list_empty(&cgrp->children)) + if (root->number_of_cgroups > 1) return -EBUSY; /* Process each subsystem */ @@ -2039,10 +2039,13 @@ int cgroupstats_build(struct cgroupstats *stats, struct dentry *dentry) struct cgroup *cgrp; struct cgroup_iter it; struct task_struct *tsk; + /* - * Validate dentry by checking the superblock operations + * Validate dentry by checking the superblock operations, + * and make sure it's a directory. */ - if (dentry->d_sb->s_op != &cgroup_ops) + if (dentry->d_sb->s_op != &cgroup_ops || + !S_ISDIR(dentry->d_inode->i_mode)) goto err; ret = 0; @@ -2472,10 +2475,7 @@ static int cgroup_rmdir(struct inode *unused_dir, struct dentry *dentry) mutex_unlock(&cgroup_mutex); return -EBUSY; } - - parent = cgrp->parent; - root = cgrp->root; - sb = root->sb; + mutex_unlock(&cgroup_mutex); /* * Call pre_destroy handlers of subsys. Notify subsystems @@ -2483,7 +2483,14 @@ static int cgroup_rmdir(struct inode *unused_dir, struct dentry *dentry) */ cgroup_call_pre_destroy(cgrp); - if (cgroup_has_css_refs(cgrp)) { + mutex_lock(&cgroup_mutex); + parent = cgrp->parent; + root = cgrp->root; + sb = root->sb; + + if (atomic_read(&cgrp->count) + || !list_empty(&cgrp->children) + || cgroup_has_css_refs(cgrp)) { mutex_unlock(&cgroup_mutex); return -EBUSY; } @@ -2497,7 +2504,6 @@ static int cgroup_rmdir(struct inode *unused_dir, struct dentry *dentry) list_del(&cgrp->sibling); spin_lock(&cgrp->dentry->d_lock); d = dget(cgrp->dentry); - cgrp->dentry = NULL; spin_unlock(&d->d_lock); cgroup_d_remove_dir(d); diff --git a/kernel/cgroup_freezer.c b/kernel/cgroup_freezer.c index e95056954498..fb249e2bcada 100644 --- a/kernel/cgroup_freezer.c +++ b/kernel/cgroup_freezer.c @@ -162,9 +162,13 @@ static int freezer_can_attach(struct cgroup_subsys *ss, struct task_struct *task) { struct freezer *freezer; - int retval; - /* Anything frozen can't move or be moved to/from */ + /* + * Anything frozen can't move or be moved to/from. + * + * Since orig_freezer->state == FROZEN means that @task has been + * frozen, so it's sufficient to check the latter condition. + */ if (is_task_frozen_enough(task)) return -EBUSY; @@ -173,25 +177,31 @@ static int freezer_can_attach(struct cgroup_subsys *ss, if (freezer->state == CGROUP_FROZEN) return -EBUSY; - retval = 0; - task_lock(task); - freezer = task_freezer(task); - if (freezer->state == CGROUP_FROZEN) - retval = -EBUSY; - task_unlock(task); - return retval; + return 0; } static void freezer_fork(struct cgroup_subsys *ss, struct task_struct *task) { struct freezer *freezer; - task_lock(task); + /* + * No lock is needed, since the task isn't on tasklist yet, + * so it can't be moved to another cgroup, which means the + * freezer won't be removed and will be valid during this + * function call. + */ freezer = task_freezer(task); - task_unlock(task); - BUG_ON(freezer->state == CGROUP_FROZEN); + /* + * The root cgroup is non-freezable, so we can skip the + * following check. + */ + if (!freezer->css.cgroup->parent) + return; + spin_lock_irq(&freezer->lock); + BUG_ON(freezer->state == CGROUP_FROZEN); + /* Locking avoids race with FREEZING -> THAWED transitions. */ if (freezer->state == CGROUP_FREEZING) freeze_task(task, true); @@ -276,25 +286,18 @@ static int try_to_freeze_cgroup(struct cgroup *cgroup, struct freezer *freezer) return num_cant_freeze_now ? -EBUSY : 0; } -static int unfreeze_cgroup(struct cgroup *cgroup, struct freezer *freezer) +static void unfreeze_cgroup(struct cgroup *cgroup, struct freezer *freezer) { struct cgroup_iter it; struct task_struct *task; cgroup_iter_start(cgroup, &it); while ((task = cgroup_iter_next(cgroup, &it))) { - int do_wake; - - task_lock(task); - do_wake = __thaw_process(task); - task_unlock(task); - if (do_wake) - wake_up_process(task); + thaw_process(task); } cgroup_iter_end(cgroup, &it); - freezer->state = CGROUP_THAWED; - return 0; + freezer->state = CGROUP_THAWED; } static int freezer_change_state(struct cgroup *cgroup, @@ -304,27 +307,22 @@ static int freezer_change_state(struct cgroup *cgroup, int retval = 0; freezer = cgroup_freezer(cgroup); + spin_lock_irq(&freezer->lock); + update_freezer_state(cgroup, freezer); if (goal_state == freezer->state) goto out; - switch (freezer->state) { + + switch (goal_state) { case CGROUP_THAWED: - retval = try_to_freeze_cgroup(cgroup, freezer); + unfreeze_cgroup(cgroup, freezer); break; - case CGROUP_FREEZING: - if (goal_state == CGROUP_FROZEN) { - /* Userspace is retrying after - * "/bin/echo FROZEN > freezer.state" returned -EBUSY */ - retval = try_to_freeze_cgroup(cgroup, freezer); - break; - } - /* state == FREEZING and goal_state == THAWED, so unfreeze */ case CGROUP_FROZEN: - retval = unfreeze_cgroup(cgroup, freezer); + retval = try_to_freeze_cgroup(cgroup, freezer); break; default: - break; + BUG(); } out: spin_unlock_irq(&freezer->lock); @@ -344,7 +342,7 @@ static int freezer_write(struct cgroup *cgroup, else if (strcmp(buffer, freezer_state_strs[CGROUP_FROZEN]) == 0) goal_state = CGROUP_FROZEN; else - return -EIO; + return -EINVAL; if (!cgroup_lock_live_group(cgroup)) return -ENODEV; @@ -363,6 +361,8 @@ static struct cftype files[] = { static int freezer_populate(struct cgroup_subsys *ss, struct cgroup *cgroup) { + if (!cgroup->parent) + return 0; return cgroup_add_files(cgroup, ss, files, ARRAY_SIZE(files)); } diff --git a/kernel/cpu.c b/kernel/cpu.c index 86d49045daed..8ea32e8d68b0 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -462,7 +462,7 @@ out: * It must be called by the arch code on the new cpu, before the new cpu * enables interrupts and before the "boot" cpu returns from __cpu_up(). */ -void notify_cpu_starting(unsigned int cpu) +void __cpuinit notify_cpu_starting(unsigned int cpu) { unsigned long val = CPU_STARTING; @@ -499,3 +499,6 @@ const unsigned long cpu_bit_bitmap[BITS_PER_LONG+1][BITS_TO_LONGS(NR_CPUS)] = { #endif }; EXPORT_SYMBOL_GPL(cpu_bit_bitmap); + +const DECLARE_BITMAP(cpu_all_bits, NR_CPUS) = CPU_BITS_ALL; +EXPORT_SYMBOL(cpu_all_bits); diff --git a/kernel/cpuset.c b/kernel/cpuset.c index 3e00526f52ec..96c0ba13b8cd 100644 --- a/kernel/cpuset.c +++ b/kernel/cpuset.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -584,10 +585,9 @@ static int generate_sched_domains(cpumask_t **domains, int i, j, k; /* indices for partition finding loops */ cpumask_t *doms; /* resulting partition; i.e. sched domains */ struct sched_domain_attr *dattr; /* attributes for custom domains */ - int ndoms; /* number of sched domains in result */ + int ndoms = 0; /* number of sched domains in result */ int nslot; /* next empty doms[] cpumask_t slot */ - ndoms = 0; doms = NULL; dattr = NULL; csa = NULL; @@ -674,10 +674,8 @@ restart: * Convert to and populate cpu masks. */ doms = kmalloc(ndoms * sizeof(cpumask_t), GFP_KERNEL); - if (!doms) { - ndoms = 0; + if (!doms) goto done; - } /* * The rest of the code, including the scheduler, can deal with @@ -732,6 +730,13 @@ restart: done: kfree(csa); + /* + * Fallback to the default domain if kmalloc() failed. + * See comments in partition_sched_domains(). + */ + if (doms == NULL) + ndoms = 1; + *domains = doms; *attributes = dattr; return ndoms; @@ -2011,12 +2016,23 @@ static int cpuset_track_online_cpus(struct notifier_block *unused_nb, * Call this routine anytime after node_states[N_HIGH_MEMORY] changes. * See also the previous routine cpuset_track_online_cpus(). */ -void cpuset_track_online_nodes(void) +static int cpuset_track_online_nodes(struct notifier_block *self, + unsigned long action, void *arg) { cgroup_lock(); - top_cpuset.mems_allowed = node_states[N_HIGH_MEMORY]; - scan_for_empty_cpusets(&top_cpuset); + switch (action) { + case MEM_ONLINE: + top_cpuset.mems_allowed = node_states[N_HIGH_MEMORY]; + break; + case MEM_OFFLINE: + top_cpuset.mems_allowed = node_states[N_HIGH_MEMORY]; + scan_for_empty_cpusets(&top_cpuset); + break; + default: + break; + } cgroup_unlock(); + return NOTIFY_OK; } #endif @@ -2032,6 +2048,7 @@ void __init cpuset_init_smp(void) top_cpuset.mems_allowed = node_states[N_HIGH_MEMORY]; hotcpu_notifier(cpuset_track_online_cpus, 0); + hotplug_memory_notifier(cpuset_track_online_nodes, 10); } /** diff --git a/kernel/exit.c b/kernel/exit.c index 80137a5d9467..2d8be7ebb0f7 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include /* for audit_free() */ #include @@ -141,6 +140,11 @@ static void __exit_signal(struct task_struct *tsk) if (sig) { flush_sigqueue(&sig->shared_pending); taskstats_tgid_free(sig); + /* + * Make sure ->signal can't go away under rq->lock, + * see account_group_exec_runtime(). + */ + task_rq_unlock_wait(tsk); __cleanup_signal(sig); } } @@ -1054,14 +1058,6 @@ NORET_TYPE void do_exit(long code) exit_itimers(tsk->signal); } acct_collect(code, group_dead); -#ifdef CONFIG_FUTEX - if (unlikely(tsk->robust_list)) - exit_robust_list(tsk); -#ifdef CONFIG_COMPAT - if (unlikely(tsk->compat_robust_list)) - compat_exit_robust_list(tsk); -#endif -#endif if (group_dead) tty_audit_exit(); if (unlikely(tsk->audit_context)) diff --git a/kernel/fork.c b/kernel/fork.c index f6083561dfe0..495da2e9a8b4 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -314,17 +315,20 @@ static int dup_mmap(struct mm_struct *mm, struct mm_struct *oldmm) file = tmp->vm_file; if (file) { struct inode *inode = file->f_path.dentry->d_inode; + struct address_space *mapping = file->f_mapping; + get_file(file); if (tmp->vm_flags & VM_DENYWRITE) atomic_dec(&inode->i_writecount); - - /* insert tmp into the share list, just after mpnt */ - spin_lock(&file->f_mapping->i_mmap_lock); + spin_lock(&mapping->i_mmap_lock); + if (tmp->vm_flags & VM_SHARED) + mapping->i_mmap_writable++; tmp->vm_truncate_count = mpnt->vm_truncate_count; - flush_dcache_mmap_lock(file->f_mapping); + flush_dcache_mmap_lock(mapping); + /* insert tmp into the share list, just after mpnt */ vma_prio_tree_add(tmp, mpnt); - flush_dcache_mmap_unlock(file->f_mapping); - spin_unlock(&file->f_mapping->i_mmap_lock); + flush_dcache_mmap_unlock(mapping); + spin_unlock(&mapping->i_mmap_lock); } /* @@ -519,6 +523,16 @@ void mm_release(struct task_struct *tsk, struct mm_struct *mm) { struct completion *vfork_done = tsk->vfork_done; + /* Get rid of any futexes when releasing the mm */ +#ifdef CONFIG_FUTEX + if (unlikely(tsk->robust_list)) + exit_robust_list(tsk); +#ifdef CONFIG_COMPAT + if (unlikely(tsk->compat_robust_list)) + compat_exit_robust_list(tsk); +#endif +#endif + /* Get rid of any cached register state */ deactivate_mm(tsk, mm); @@ -1387,6 +1401,7 @@ long do_fork(unsigned long clone_flags, init_completion(&vfork); } + audit_finish_fork(p); tracehook_report_clone(trace, regs, clone_flags, nr, p); /* diff --git a/kernel/freezer.c b/kernel/freezer.c index ba6248b323ef..2f4936cf7083 100644 --- a/kernel/freezer.c +++ b/kernel/freezer.c @@ -121,16 +121,7 @@ void cancel_freezing(struct task_struct *p) } } -/* - * Wake up a frozen process - * - * task_lock() is needed to prevent the race with refrigerator() which may - * occur if the freezing of tasks fails. Namely, without the lock, if the - * freezing of tasks failed, thaw_tasks() might have run before a task in - * refrigerator() could call frozen_process(), in which case the task would be - * frozen and no one would thaw it. - */ -int __thaw_process(struct task_struct *p) +static int __thaw_process(struct task_struct *p) { if (frozen(p)) { p->flags &= ~PF_FROZEN; @@ -140,6 +131,15 @@ int __thaw_process(struct task_struct *p) return 0; } +/* + * Wake up a frozen process + * + * task_lock() is needed to prevent the race with refrigerator() which may + * occur if the freezing of tasks fails. Namely, without the lock, if the + * freezing of tasks failed, thaw_tasks() might have run before a task in + * refrigerator() could call frozen_process(), in which case the task would be + * frozen and no one would thaw it. + */ int thaw_process(struct task_struct *p) { task_lock(p); diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c index 2b465dfde426..47e63349d1b2 100644 --- a/kernel/hrtimer.c +++ b/kernel/hrtimer.c @@ -664,14 +664,6 @@ static inline int hrtimer_enqueue_reprogram(struct hrtimer *timer, /* Timer is expired, act upon the callback mode */ switch(timer->cb_mode) { - case HRTIMER_CB_IRQSAFE_NO_RESTART: - debug_hrtimer_deactivate(timer); - /* - * We can call the callback from here. No restart - * happens, so no danger of recursion - */ - BUG_ON(timer->function(timer) != HRTIMER_NORESTART); - return 1; case HRTIMER_CB_IRQSAFE_PERCPU: case HRTIMER_CB_IRQSAFE_UNLOCKED: /* @@ -683,7 +675,6 @@ static inline int hrtimer_enqueue_reprogram(struct hrtimer *timer, */ debug_hrtimer_deactivate(timer); return 1; - case HRTIMER_CB_IRQSAFE: case HRTIMER_CB_SOFTIRQ: /* * Move everything else into the softirq pending list ! @@ -1209,6 +1200,7 @@ static void run_hrtimer_pending(struct hrtimer_cpu_base *cpu_base) enum hrtimer_restart (*fn)(struct hrtimer *); struct hrtimer *timer; int restart; + int emulate_hardirq_ctx = 0; timer = list_entry(cpu_base->cb_pending.next, struct hrtimer, cb_entry); @@ -1217,10 +1209,24 @@ static void run_hrtimer_pending(struct hrtimer_cpu_base *cpu_base) timer_stats_account_hrtimer(timer); fn = timer->function; + /* + * A timer might have been added to the cb_pending list + * when it was migrated during a cpu-offline operation. + * Emulate hardirq context for such timers. + */ + if (timer->cb_mode == HRTIMER_CB_IRQSAFE_PERCPU || + timer->cb_mode == HRTIMER_CB_IRQSAFE_UNLOCKED) + emulate_hardirq_ctx = 1; + __remove_hrtimer(timer, timer->base, HRTIMER_STATE_CALLBACK, 0); spin_unlock_irq(&cpu_base->lock); - restart = fn(timer); + if (unlikely(emulate_hardirq_ctx)) { + local_irq_disable(); + restart = fn(timer); + local_irq_enable(); + } else + restart = fn(timer); spin_lock_irq(&cpu_base->lock); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index c9767e641980..64c1c7253dae 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -25,6 +25,8 @@ static inline void unregister_handler_proc(unsigned int irq, struct irqaction *action) { } #endif +extern int irq_select_affinity_usr(unsigned int irq); + /* * Debugging printout: */ diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index c498a1b8c621..801addda3c43 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -82,24 +82,27 @@ int irq_can_set_affinity(unsigned int irq) int irq_set_affinity(unsigned int irq, cpumask_t cpumask) { struct irq_desc *desc = irq_to_desc(irq); + unsigned long flags; if (!desc->chip->set_affinity) return -EINVAL; + spin_lock_irqsave(&desc->lock, flags); + #ifdef CONFIG_GENERIC_PENDING_IRQ if (desc->status & IRQ_MOVE_PCNTXT || desc->status & IRQ_DISABLED) { - unsigned long flags; - - spin_lock_irqsave(&desc->lock, flags); desc->affinity = cpumask; desc->chip->set_affinity(irq, cpumask); - spin_unlock_irqrestore(&desc->lock, flags); - } else - set_pending_irq(irq, cpumask); + } else { + desc->status |= IRQ_MOVE_PENDING; + desc->pending_mask = cpumask; + } #else desc->affinity = cpumask; desc->chip->set_affinity(irq, cpumask); #endif + desc->status |= IRQ_AFFINITY_SET; + spin_unlock_irqrestore(&desc->lock, flags); return 0; } @@ -107,24 +110,59 @@ int irq_set_affinity(unsigned int irq, cpumask_t cpumask) /* * Generic version of the affinity autoselector. */ -int irq_select_affinity(unsigned int irq) +int do_irq_select_affinity(unsigned int irq, struct irq_desc *desc) { cpumask_t mask; - struct irq_desc *desc; if (!irq_can_set_affinity(irq)) return 0; cpus_and(mask, cpu_online_map, irq_default_affinity); - desc = irq_to_desc(irq); + /* + * Preserve an userspace affinity setup, but make sure that + * one of the targets is online. + */ + if (desc->status & (IRQ_AFFINITY_SET | IRQ_NO_BALANCING)) { + if (cpus_intersects(desc->affinity, cpu_online_map)) + mask = desc->affinity; + else + desc->status &= ~IRQ_AFFINITY_SET; + } + desc->affinity = mask; desc->chip->set_affinity(irq, mask); return 0; } +#else +static inline int do_irq_select_affinity(unsigned int irq, struct irq_desc *d) +{ + return irq_select_affinity(irq); +} #endif +/* + * Called when affinity is set via /proc/irq + */ +int irq_select_affinity_usr(unsigned int irq) +{ + struct irq_desc *desc = irq_to_desc(irq); + unsigned long flags; + int ret; + + spin_lock_irqsave(&desc->lock, flags); + ret = do_irq_select_affinity(irq, desc); + spin_unlock_irqrestore(&desc->lock, flags); + + return ret; +} + +#else +static inline int do_irq_select_affinity(int irq, struct irq_desc *desc) +{ + return 0; +} #endif /** @@ -327,7 +365,7 @@ int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, * IRQF_TRIGGER_* but the PIC does not support multiple * flow-types? */ - pr_warning("No set_type function for IRQ %d (%s)\n", irq, + pr_debug("No set_type function for IRQ %d (%s)\n", irq, chip ? (chip->name ? : "unknown") : "unknown"); return 0; } @@ -445,8 +483,12 @@ __setup_irq(unsigned int irq, struct irq_desc * desc, struct irqaction *new) /* Undo nested disables: */ desc->depth = 1; + /* Exclude IRQ from balancing if requested */ + if (new->flags & IRQF_NOBALANCING) + desc->status |= IRQ_NO_BALANCING; + /* Set default affinity mask once everything is setup */ - irq_select_affinity(irq); + do_irq_select_affinity(irq, desc); } else if ((new->flags & IRQF_TRIGGER_MASK) && (new->flags & IRQF_TRIGGER_MASK) @@ -459,10 +501,6 @@ __setup_irq(unsigned int irq, struct irq_desc * desc, struct irqaction *new) *p = new; - /* Exclude IRQ from balancing */ - if (new->flags & IRQF_NOBALANCING) - desc->status |= IRQ_NO_BALANCING; - /* Reset broken irq detection when installing new handler */ desc->irq_count = 0; desc->irqs_unhandled = 0; diff --git a/kernel/irq/migration.c b/kernel/irq/migration.c index 90b920d3f52b..9db681d95814 100644 --- a/kernel/irq/migration.c +++ b/kernel/irq/migration.c @@ -1,17 +1,6 @@ #include -void set_pending_irq(unsigned int irq, cpumask_t mask) -{ - struct irq_desc *desc = irq_to_desc(irq); - unsigned long flags; - - spin_lock_irqsave(&desc->lock, flags); - desc->status |= IRQ_MOVE_PENDING; - desc->pending_mask = mask; - spin_unlock_irqrestore(&desc->lock, flags); -} - void move_masked_irq(int irq) { struct irq_desc *desc = irq_to_desc(irq); diff --git a/kernel/irq/proc.c b/kernel/irq/proc.c index fac014a81b24..d257e7d6a8a4 100644 --- a/kernel/irq/proc.c +++ b/kernel/irq/proc.c @@ -62,7 +62,7 @@ static ssize_t irq_affinity_proc_write(struct file *file, if (!cpus_intersects(new_value, cpu_online_map)) /* Special case for empty set - allow the architecture code to set default SMP affinity. */ - return irq_select_affinity(irq) ? -EINVAL : count; + return irq_select_affinity_usr(irq) ? -EINVAL : count; irq_set_affinity(irq, new_value); @@ -220,7 +220,7 @@ void unregister_handler_proc(unsigned int irq, struct irqaction *action) } } -void register_default_affinity_proc(void) +static void register_default_affinity_proc(void) { #ifdef CONFIG_SMP proc_create("irq/default_smp_affinity", 0600, NULL, diff --git a/kernel/kallsyms.c b/kernel/kallsyms.c index 5072cf1685a2..7b8b0f21a5b1 100644 --- a/kernel/kallsyms.c +++ b/kernel/kallsyms.c @@ -304,17 +304,24 @@ int sprint_symbol(char *buffer, unsigned long address) char *modname; const char *name; unsigned long offset, size; - char namebuf[KSYM_NAME_LEN]; + int len; - name = kallsyms_lookup(address, &size, &offset, &modname, namebuf); + name = kallsyms_lookup(address, &size, &offset, &modname, buffer); if (!name) return sprintf(buffer, "0x%lx", address); + if (name != buffer) + strcpy(buffer, name); + len = strlen(buffer); + buffer += len; + if (modname) - return sprintf(buffer, "%s+%#lx/%#lx [%s]", name, offset, - size, modname); + len += sprintf(buffer, "+%#lx/%#lx [%s]", + offset, size, modname); else - return sprintf(buffer, "%s+%#lx/%#lx", name, offset, size); + len += sprintf(buffer, "+%#lx/%#lx", offset, size); + + return len; } /* Look up a kernel symbol and print it to the kernel messages. */ diff --git a/kernel/kprobes.c b/kernel/kprobes.c index 8b57a2597f21..9f8a3f25259a 100644 --- a/kernel/kprobes.c +++ b/kernel/kprobes.c @@ -72,7 +72,7 @@ static bool kprobe_enabled; DEFINE_MUTEX(kprobe_mutex); /* Protects kprobe_table */ static DEFINE_PER_CPU(struct kprobe *, kprobe_instance) = NULL; static struct { - spinlock_t lock ____cacheline_aligned; + spinlock_t lock ____cacheline_aligned_in_smp; } kretprobe_table_locks[KPROBE_TABLE_SIZE]; static spinlock_t *kretprobe_table_lock_ptr(unsigned long hash) @@ -613,30 +613,37 @@ static int __kprobes __register_kprobe(struct kprobe *p, return -EINVAL; p->addr = addr; - if (!kernel_text_address((unsigned long) p->addr) || - in_kprobes_functions((unsigned long) p->addr)) + preempt_disable(); + if (!__kernel_text_address((unsigned long) p->addr) || + in_kprobes_functions((unsigned long) p->addr)) { + preempt_enable(); return -EINVAL; + } p->mod_refcounted = 0; /* * Check if are we probing a module. */ - probed_mod = module_text_address((unsigned long) p->addr); + probed_mod = __module_text_address((unsigned long) p->addr); if (probed_mod) { - struct module *calling_mod = module_text_address(called_from); + struct module *calling_mod; + calling_mod = __module_text_address(called_from); /* * We must allow modules to probe themself and in this case * avoid incrementing the module refcount, so as to allow * unloading of self probing modules. */ if (calling_mod && calling_mod != probed_mod) { - if (unlikely(!try_module_get(probed_mod))) + if (unlikely(!try_module_get(probed_mod))) { + preempt_enable(); return -EINVAL; + } p->mod_refcounted = 1; } else probed_mod = NULL; } + preempt_enable(); p->nmissed = 0; INIT_LIST_HEAD(&p->list); @@ -718,6 +725,10 @@ static void __kprobes __unregister_kprobe_bottom(struct kprobe *p) struct kprobe *old_p; if (p->mod_refcounted) { + /* + * Since we've already incremented refcount, + * we don't need to disable preemption. + */ mod = module_text_address((unsigned long)p->addr); if (mod) module_put(mod); diff --git a/kernel/latencytop.c b/kernel/latencytop.c index 5e7b45c56923..449db466bdbc 100644 --- a/kernel/latencytop.c +++ b/kernel/latencytop.c @@ -191,7 +191,7 @@ static int lstats_show(struct seq_file *m, void *v) latency_record[i].time, latency_record[i].max); for (q = 0; q < LT_BACKTRACEDEPTH; q++) { - char sym[KSYM_NAME_LEN]; + char sym[KSYM_SYMBOL_LEN]; char *c; if (!latency_record[i].backtrace[q]) break; diff --git a/kernel/lockdep.c b/kernel/lockdep.c index dbda475b13bd..46a404173db2 100644 --- a/kernel/lockdep.c +++ b/kernel/lockdep.c @@ -2169,12 +2169,11 @@ void early_boot_irqs_on(void) /* * Hardirqs will be enabled: */ -void trace_hardirqs_on_caller(unsigned long a0) +void trace_hardirqs_on_caller(unsigned long ip) { struct task_struct *curr = current; - unsigned long ip; - time_hardirqs_on(CALLER_ADDR0, a0); + time_hardirqs_on(CALLER_ADDR0, ip); if (unlikely(!debug_locks || current->lockdep_recursion)) return; @@ -2188,7 +2187,6 @@ void trace_hardirqs_on_caller(unsigned long a0) } /* we'll do an OFF -> ON transition: */ curr->hardirqs_enabled = 1; - ip = (unsigned long) __builtin_return_address(0); if (DEBUG_LOCKS_WARN_ON(!irqs_disabled())) return; @@ -2224,11 +2222,11 @@ EXPORT_SYMBOL(trace_hardirqs_on); /* * Hardirqs were disabled: */ -void trace_hardirqs_off_caller(unsigned long a0) +void trace_hardirqs_off_caller(unsigned long ip) { struct task_struct *curr = current; - time_hardirqs_off(CALLER_ADDR0, a0); + time_hardirqs_off(CALLER_ADDR0, ip); if (unlikely(!debug_locks || current->lockdep_recursion)) return; @@ -2241,7 +2239,7 @@ void trace_hardirqs_off_caller(unsigned long a0) * We have done an ON -> OFF transition: */ curr->hardirqs_enabled = 0; - curr->hardirq_disable_ip = _RET_IP_; + curr->hardirq_disable_ip = ip; curr->hardirq_disable_event = ++curr->irq_events; debug_atomic_inc(&hardirqs_off_events); } else @@ -3278,10 +3276,10 @@ void __init lockdep_info(void) { printk("Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar\n"); - printk("... MAX_LOCKDEP_SUBCLASSES: %lu\n", MAX_LOCKDEP_SUBCLASSES); + printk("... MAX_LOCKDEP_SUBCLASSES: %lu\n", MAX_LOCKDEP_SUBCLASSES); printk("... MAX_LOCK_DEPTH: %lu\n", MAX_LOCK_DEPTH); printk("... MAX_LOCKDEP_KEYS: %lu\n", MAX_LOCKDEP_KEYS); - printk("... CLASSHASH_SIZE: %lu\n", CLASSHASH_SIZE); + printk("... CLASSHASH_SIZE: %lu\n", CLASSHASH_SIZE); printk("... MAX_LOCKDEP_ENTRIES: %lu\n", MAX_LOCKDEP_ENTRIES); printk("... MAX_LOCKDEP_CHAINS: %lu\n", MAX_LOCKDEP_CHAINS); printk("... CHAINHASH_SIZE: %lu\n", CHAINHASH_SIZE); @@ -3417,9 +3415,10 @@ retry: } printk(" ignoring it.\n"); unlock = 0; + } else { + if (count != 10) + printk(KERN_CONT " locked it.\n"); } - if (count != 10) - printk(" locked it.\n"); do_each_thread(g, p) { /* diff --git a/kernel/panic.c b/kernel/panic.c index 6513aac8e992..4d5088355bfe 100644 --- a/kernel/panic.c +++ b/kernel/panic.c @@ -167,6 +167,7 @@ static const struct tnt tnts[] = { * 'M' - System experienced a machine check exception. * 'B' - System has hit bad_page. * 'U' - Userspace-defined naughtiness. + * 'D' - Kernel has oopsed before * 'A' - ACPI table overridden. * 'W' - Taint on warning. * 'C' - modules from drivers/staging are loaded. diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c index 153dcb2639c3..4e5288a831de 100644 --- a/kernel/posix-cpu-timers.c +++ b/kernel/posix-cpu-timers.c @@ -311,7 +311,7 @@ static int cpu_clock_sample_group(const clockid_t which_clock, struct task_cputime cputime; thread_group_cputime(p, &cputime); - switch (which_clock) { + switch (CPUCLOCK_WHICH(which_clock)) { default: return -EINVAL; case CPUCLOCK_PROF: @@ -1308,9 +1308,10 @@ static inline int task_cputime_expired(const struct task_cputime *sample, */ static inline int fastpath_timer_check(struct task_struct *tsk) { - struct signal_struct *sig = tsk->signal; + struct signal_struct *sig; - if (unlikely(!sig)) + /* tsk == current, ensure it is safe to use ->signal/sighand */ + if (unlikely(tsk->exit_state)) return 0; if (!task_cputime_zero(&tsk->cputime_expires)) { @@ -1323,6 +1324,8 @@ static inline int fastpath_timer_check(struct task_struct *tsk) if (task_cputime_expired(&task_sample, &tsk->cputime_expires)) return 1; } + + sig = tsk->signal; if (!task_cputime_zero(&sig->cputime_expires)) { struct task_cputime group_sample; diff --git a/kernel/posix-timers.c b/kernel/posix-timers.c index 5e79c662294b..a140e44eebba 100644 --- a/kernel/posix-timers.c +++ b/kernel/posix-timers.c @@ -197,6 +197,11 @@ static int common_timer_create(struct k_itimer *new_timer) return 0; } +static int no_timer_create(struct k_itimer *new_timer) +{ + return -EOPNOTSUPP; +} + /* * Return nonzero if we know a priori this clockid_t value is bogus. */ @@ -248,6 +253,7 @@ static __init int init_posix_timers(void) .clock_getres = hrtimer_get_res, .clock_get = posix_get_monotonic_raw, .clock_set = do_posix_clock_nosettime, + .timer_create = no_timer_create, }; register_posix_clock(CLOCK_REALTIME, &clock_realtime); diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig index dcd165f92a88..23bd4daeb96b 100644 --- a/kernel/power/Kconfig +++ b/kernel/power/Kconfig @@ -96,7 +96,7 @@ config SUSPEND config PM_TEST_SUSPEND bool "Test suspend/resume and wakealarm during bootup" - depends on SUSPEND && PM_DEBUG && RTC_LIB=y + depends on SUSPEND && PM_DEBUG && RTC_CLASS=y ---help--- This option will let you suspend your machine during bootup, and make it wake up a few seconds later using an RTC wakeup alarm. diff --git a/kernel/power/main.c b/kernel/power/main.c index 19122cf6d827..b8f7ce9473e8 100644 --- a/kernel/power/main.c +++ b/kernel/power/main.c @@ -174,7 +174,7 @@ static void suspend_test_finish(const char *label) * has some performance issues. The stack dump of a WARN_ON * is more likely to get the right attention than a printk... */ - WARN_ON(msec > (TEST_SUSPEND_SECONDS * 1000)); + WARN(msec > (TEST_SUSPEND_SECONDS * 1000), "Component: %s\n", label); } #else diff --git a/kernel/power/swap.c b/kernel/power/swap.c index b7713b53d07a..6da14358537c 100644 --- a/kernel/power/swap.c +++ b/kernel/power/swap.c @@ -633,7 +633,7 @@ void swsusp_close(fmode_t mode) return; } - blkdev_put(resume_bdev, mode); /* move up */ + blkdev_put(resume_bdev, mode); } static int swsusp_header_init(void) diff --git a/kernel/printk.c b/kernel/printk.c index 6341af77eb65..f492f1583d77 100644 --- a/kernel/printk.c +++ b/kernel/printk.c @@ -232,45 +232,6 @@ static inline void boot_delay_msec(void) } #endif -/* - * Return the number of unread characters in the log buffer. - */ -static int log_buf_get_len(void) -{ - return logged_chars; -} - -/* - * Copy a range of characters from the log buffer. - */ -int log_buf_copy(char *dest, int idx, int len) -{ - int ret, max; - bool took_lock = false; - - if (!oops_in_progress) { - spin_lock_irq(&logbuf_lock); - took_lock = true; - } - - max = log_buf_get_len(); - if (idx < 0 || idx >= max) { - ret = -1; - } else { - if (len > max) - len = max; - ret = len; - idx += (log_end - max); - while (len-- > 0) - dest[len] = LOG_BUF(idx + len); - } - - if (took_lock) - spin_unlock_irq(&logbuf_lock); - - return ret; -} - /* * Commands to do_syslog: * diff --git a/kernel/profile.c b/kernel/profile.c index a9e422df6bf6..dc41827fbfee 100644 --- a/kernel/profile.c +++ b/kernel/profile.c @@ -102,7 +102,7 @@ int profile_setup(char *str) __setup("profile=", profile_setup); -int profile_init(void) +int __ref profile_init(void) { int buffer_bytes; if (!prof_on) @@ -351,7 +351,7 @@ out: put_cpu(); } -static int __devinit profile_cpu_callback(struct notifier_block *info, +static int __cpuinit profile_cpu_callback(struct notifier_block *info, unsigned long action, void *__cpu) { int node, cpu = (unsigned long)__cpu; @@ -544,7 +544,7 @@ static const struct file_operations proc_profile_operations = { }; #ifdef CONFIG_SMP -static void __init profile_nop(void *unused) +static inline void profile_nop(void *unused) { } @@ -596,7 +596,7 @@ out_cleanup: #define create_hash_tables() ({ 0; }) #endif -int create_proc_profile(void) +int __ref create_proc_profile(void) /* false positive from hotcpu_notifier */ { struct proc_dir_entry *entry; diff --git a/kernel/ptrace.c b/kernel/ptrace.c index 1e68e4c39e2c..4c8bcd7dd8e0 100644 --- a/kernel/ptrace.c +++ b/kernel/ptrace.c @@ -612,7 +612,7 @@ int generic_ptrace_pokedata(struct task_struct *tsk, long addr, long data) return (copied == sizeof(data)) ? 0 : -EIO; } -#if defined CONFIG_COMPAT && defined __ARCH_WANT_COMPAT_SYS_PTRACE +#if defined CONFIG_COMPAT #include int compat_ptrace_request(struct task_struct *child, compat_long_t request, @@ -709,4 +709,4 @@ asmlinkage long compat_sys_ptrace(compat_long_t request, compat_long_t pid, unlock_kernel(); return ret; } -#endif /* CONFIG_COMPAT && __ARCH_WANT_COMPAT_SYS_PTRACE */ +#endif /* CONFIG_COMPAT */ diff --git a/kernel/relay.c b/kernel/relay.c index 8d13a7855c08..09ac2008f77b 100644 --- a/kernel/relay.c +++ b/kernel/relay.c @@ -400,7 +400,7 @@ void relay_reset(struct rchan *chan) } mutex_lock(&relay_channels_mutex); - for_each_online_cpu(i) + for_each_possible_cpu(i) if (chan->buf[i]) __relay_reset(chan->buf[i], 0); mutex_unlock(&relay_channels_mutex); @@ -611,10 +611,9 @@ struct rchan *relay_open(const char *base_filename, return chan; free_bufs: - for_each_online_cpu(i) { - if (!chan->buf[i]) - break; - relay_close_buf(chan->buf[i]); + for_each_possible_cpu(i) { + if (chan->buf[i]) + relay_close_buf(chan->buf[i]); } kref_put(&chan->kref, relay_destroy_channel); @@ -1318,12 +1317,9 @@ static ssize_t relay_file_splice_read(struct file *in, if (ret < 0) break; else if (!ret) { - if (spliced) - break; - if (flags & SPLICE_F_NONBLOCK) { + if (flags & SPLICE_F_NONBLOCK) ret = -EAGAIN; - break; - } + break; } *ppos += ret; diff --git a/kernel/resource.c b/kernel/resource.c index 4089d12af6e0..4337063663ef 100644 --- a/kernel/resource.c +++ b/kernel/resource.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -522,7 +523,7 @@ static void __init __reserve_region_with_split(struct resource *root, { struct resource *parent = root; struct resource *conflict; - struct resource *res = kzalloc(sizeof(*res), GFP_KERNEL); + struct resource *res = kzalloc(sizeof(*res), GFP_ATOMIC); if (!res) return; @@ -571,7 +572,7 @@ static void __init __reserve_region_with_split(struct resource *root, } -void reserve_region_with_split(struct resource *root, +void __init reserve_region_with_split(struct resource *root, resource_size_t start, resource_size_t end, const char *name) { @@ -849,7 +850,8 @@ int iomem_map_sanity_check(resource_size_t addr, unsigned long size) continue; if (p->end < addr) continue; - if (p->start <= addr && (p->end >= addr + size - 1)) + if (PFN_DOWN(p->start) <= PFN_DOWN(addr) && + PFN_DOWN(p->end) >= PFN_DOWN(addr + size - 1)) continue; printk(KERN_WARNING "resource map sanity check conflict: " "0x%llx 0x%llx 0x%llx 0x%llx %s\n", diff --git a/kernel/sched.c b/kernel/sched.c index 6625c3c4b10d..e4bb1dd7b308 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -386,7 +386,6 @@ struct cfs_rq { u64 exec_clock; u64 min_vruntime; - u64 pair_start; struct rb_root tasks_timeline; struct rb_node *rb_leftmost; @@ -398,9 +397,9 @@ struct cfs_rq { * 'curr' points to currently running entity on this cfs_rq. * It is set to NULL otherwise (i.e when none are currently running). */ - struct sched_entity *curr, *next; + struct sched_entity *curr, *next, *last; - unsigned long nr_spread_over; + unsigned int nr_spread_over; #ifdef CONFIG_FAIR_GROUP_SCHED struct rq *rq; /* cpu runqueue to which this cfs_rq is attached */ @@ -970,6 +969,14 @@ static struct rq *task_rq_lock(struct task_struct *p, unsigned long *flags) } } +void task_rq_unlock_wait(struct task_struct *p) +{ + struct rq *rq = task_rq(p); + + smp_mb(); /* spin-unlock-wait is not a full memory barrier */ + spin_unlock_wait(&rq->lock); +} + static void __task_rq_unlock(struct rq *rq) __releases(rq->lock) { @@ -1446,9 +1453,12 @@ static int task_hot(struct task_struct *p, u64 now, struct sched_domain *sd); static unsigned long cpu_avg_load_per_task(int cpu) { struct rq *rq = cpu_rq(cpu); + unsigned long nr_running = ACCESS_ONCE(rq->nr_running); - if (rq->nr_running) - rq->avg_load_per_task = rq->load.weight / rq->nr_running; + if (nr_running) + rq->avg_load_per_task = rq->load.weight / nr_running; + else + rq->avg_load_per_task = 0; return rq->avg_load_per_task; } @@ -1806,7 +1816,9 @@ task_hot(struct task_struct *p, u64 now, struct sched_domain *sd) /* * Buddy candidates are cache hot: */ - if (sched_feat(CACHE_HOT_BUDDY) && (&p->se == cfs_rq_of(&p->se)->next)) + if (sched_feat(CACHE_HOT_BUDDY) && + (&p->se == cfs_rq_of(&p->se)->next || + &p->se == cfs_rq_of(&p->se)->last)) return 1; if (p->sched_class != &fair_sched_class) @@ -3344,7 +3356,7 @@ small_imbalance: } else this_load_per_task = cpu_avg_load_per_task(this_cpu); - if (max_load - this_load + 2*busiest_load_per_task >= + if (max_load - this_load + busiest_load_per_task >= busiest_load_per_task * imbn) { *imbalance = busiest_load_per_task; return busiest; @@ -5859,6 +5871,8 @@ void __cpuinit init_idle(struct task_struct *idle, int cpu) struct rq *rq = cpu_rq(cpu); unsigned long flags; + spin_lock_irqsave(&rq->lock, flags); + __sched_fork(idle); idle->se.exec_start = sched_clock(); @@ -5866,7 +5880,6 @@ void __cpuinit init_idle(struct task_struct *idle, int cpu) idle->cpus_allowed = cpumask_of_cpu(cpu); __set_task_cpu(idle, cpu); - spin_lock_irqsave(&rq->lock, flags); rq->curr = rq->idle = idle; #if defined(CONFIG_SMP) && defined(__ARCH_WANT_UNLOCKED_CTXSW) idle->oncpu = 1; @@ -6574,7 +6587,9 @@ migration_call(struct notifier_block *nfb, unsigned long action, void *hcpu) req = list_entry(rq->migration_queue.next, struct migration_req, list); list_del_init(&req->list); + spin_unlock_irq(&rq->lock); complete(&req->done); + spin_lock_irq(&rq->lock); } spin_unlock_irq(&rq->lock); break; @@ -6876,15 +6891,17 @@ cpu_attach_domain(struct sched_domain *sd, struct root_domain *rd, int cpu) struct sched_domain *tmp; /* Remove the sched domains which do not contribute to scheduling. */ - for (tmp = sd; tmp; tmp = tmp->parent) { + for (tmp = sd; tmp; ) { struct sched_domain *parent = tmp->parent; if (!parent) break; + if (sd_parent_degenerate(tmp, parent)) { tmp->parent = parent->parent; if (parent->parent) parent->parent->child = tmp; - } + } else + tmp = tmp->parent; } if (sd && sd_degenerate(sd)) { @@ -7673,6 +7690,7 @@ static int __build_sched_domains(const cpumask_t *cpu_map, error: free_sched_groups(cpu_map, tmpmask); SCHED_CPUMASK_FREE((void *)allmasks); + kfree(rd); return -ENOMEM; #endif } @@ -7774,13 +7792,14 @@ static int dattrs_equal(struct sched_domain_attr *cur, int idx_cur, * * The passed in 'doms_new' should be kmalloc'd. This routine takes * ownership of it and will kfree it when done with it. If the caller - * failed the kmalloc call, then it can pass in doms_new == NULL, - * and partition_sched_domains() will fallback to the single partition - * 'fallback_doms', it also forces the domains to be rebuilt. + * failed the kmalloc call, then it can pass in doms_new == NULL && + * ndoms_new == 1, and partition_sched_domains() will fallback to + * the single partition 'fallback_doms', it also forces the domains + * to be rebuilt. * - * If doms_new==NULL it will be replaced with cpu_online_map. - * ndoms_new==0 is a special case for destroying existing domains. - * It will not create the default domain. + * If doms_new == NULL it will be replaced with cpu_online_map. + * ndoms_new == 0 is a special case for destroying existing domains, + * and it will not create the default domain. * * Call with hotplug lock held */ diff --git a/kernel/sched_clock.c b/kernel/sched_clock.c index 81787248b60f..e8ab096ddfe3 100644 --- a/kernel/sched_clock.c +++ b/kernel/sched_clock.c @@ -118,13 +118,13 @@ static u64 __update_sched_clock(struct sched_clock_data *scd, u64 now) /* * scd->clock = clamp(scd->tick_gtod + delta, - * max(scd->tick_gtod, scd->clock), - * max(scd->clock, scd->tick_gtod + TICK_NSEC)); + * max(scd->tick_gtod, scd->clock), + * scd->tick_gtod + TICK_NSEC); */ clock = scd->tick_gtod + delta; min_clock = wrap_max(scd->tick_gtod, scd->clock); - max_clock = wrap_max(scd->clock, scd->tick_gtod + TICK_NSEC); + max_clock = scd->tick_gtod + TICK_NSEC; clock = wrap_max(clock, min_clock); clock = wrap_min(clock, max_clock); diff --git a/kernel/sched_debug.c b/kernel/sched_debug.c index ad958c1ec708..26ed8e3d1c15 100644 --- a/kernel/sched_debug.c +++ b/kernel/sched_debug.c @@ -144,7 +144,7 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) last = __pick_last_entity(cfs_rq); if (last) max_vruntime = last->vruntime; - min_vruntime = rq->cfs.min_vruntime; + min_vruntime = cfs_rq->min_vruntime; rq0_min_vruntime = per_cpu(runqueues, 0).cfs.min_vruntime; spin_unlock_irqrestore(&rq->lock, flags); SEQ_printf(m, " .%-30s: %Ld.%06ld\n", "MIN_vruntime", @@ -161,26 +161,8 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) SPLIT_NS(spread0)); SEQ_printf(m, " .%-30s: %ld\n", "nr_running", cfs_rq->nr_running); SEQ_printf(m, " .%-30s: %ld\n", "load", cfs_rq->load.weight); -#ifdef CONFIG_SCHEDSTATS -#define P(n) SEQ_printf(m, " .%-30s: %d\n", #n, rq->n); - - P(yld_exp_empty); - P(yld_act_empty); - P(yld_both_empty); - P(yld_count); - P(sched_switch); - P(sched_count); - P(sched_goidle); - - P(ttwu_count); - P(ttwu_local); - - P(bkl_count); - -#undef P -#endif - SEQ_printf(m, " .%-30s: %ld\n", "nr_spread_over", + SEQ_printf(m, " .%-30s: %d\n", "nr_spread_over", cfs_rq->nr_spread_over); #ifdef CONFIG_FAIR_GROUP_SCHED #ifdef CONFIG_SMP @@ -260,6 +242,25 @@ static void print_cpu(struct seq_file *m, int cpu) #undef P #undef PN +#ifdef CONFIG_SCHEDSTATS +#define P(n) SEQ_printf(m, " .%-30s: %d\n", #n, rq->n); + + P(yld_exp_empty); + P(yld_act_empty); + P(yld_both_empty); + P(yld_count); + + P(sched_switch); + P(sched_count); + P(sched_goidle); + + P(ttwu_count); + P(ttwu_local); + + P(bkl_count); + +#undef P +#endif print_cfs_stats(m, cpu); print_rt_stats(m, cpu); @@ -319,7 +320,7 @@ static int __init init_sched_debug_procfs(void) { struct proc_dir_entry *pe; - pe = proc_create("sched_debug", 0644, NULL, &sched_debug_fops); + pe = proc_create("sched_debug", 0444, NULL, &sched_debug_fops); if (!pe) return -ENOMEM; return 0; @@ -422,10 +423,11 @@ void proc_sched_show_task(struct task_struct *p, struct seq_file *m) #undef __P { + unsigned int this_cpu = raw_smp_processor_id(); u64 t0, t1; - t0 = sched_clock(); - t1 = sched_clock(); + t0 = cpu_clock(this_cpu); + t1 = cpu_clock(this_cpu); SEQ_printf(m, "%-35s:%21Ld\n", "clock-delta", (long long)(t1-t0)); } diff --git a/kernel/sched_fair.c b/kernel/sched_fair.c index 9573c33688b8..98345e45b059 100644 --- a/kernel/sched_fair.c +++ b/kernel/sched_fair.c @@ -143,6 +143,49 @@ static inline struct sched_entity *parent_entity(struct sched_entity *se) return se->parent; } +/* return depth at which a sched entity is present in the hierarchy */ +static inline int depth_se(struct sched_entity *se) +{ + int depth = 0; + + for_each_sched_entity(se) + depth++; + + return depth; +} + +static void +find_matching_se(struct sched_entity **se, struct sched_entity **pse) +{ + int se_depth, pse_depth; + + /* + * preemption test can be made between sibling entities who are in the + * same cfs_rq i.e who have a common parent. Walk up the hierarchy of + * both tasks until we find their ancestors who are siblings of common + * parent. + */ + + /* First walk up until both entities are at same depth */ + se_depth = depth_se(*se); + pse_depth = depth_se(*pse); + + while (se_depth > pse_depth) { + se_depth--; + *se = parent_entity(*se); + } + + while (pse_depth > se_depth) { + pse_depth--; + *pse = parent_entity(*pse); + } + + while (!is_same_group(*se, *pse)) { + *se = parent_entity(*se); + *pse = parent_entity(*pse); + } +} + #else /* CONFIG_FAIR_GROUP_SCHED */ static inline struct rq *rq_of(struct cfs_rq *cfs_rq) @@ -193,6 +236,11 @@ static inline struct sched_entity *parent_entity(struct sched_entity *se) return NULL; } +static inline void +find_matching_se(struct sched_entity **se, struct sched_entity **pse) +{ +} + #endif /* CONFIG_FAIR_GROUP_SCHED */ @@ -223,6 +271,27 @@ static inline s64 entity_key(struct cfs_rq *cfs_rq, struct sched_entity *se) return se->vruntime - cfs_rq->min_vruntime; } +static void update_min_vruntime(struct cfs_rq *cfs_rq) +{ + u64 vruntime = cfs_rq->min_vruntime; + + if (cfs_rq->curr) + vruntime = cfs_rq->curr->vruntime; + + if (cfs_rq->rb_leftmost) { + struct sched_entity *se = rb_entry(cfs_rq->rb_leftmost, + struct sched_entity, + run_node); + + if (vruntime == cfs_rq->min_vruntime) + vruntime = se->vruntime; + else + vruntime = min_vruntime(vruntime, se->vruntime); + } + + cfs_rq->min_vruntime = max_vruntime(cfs_rq->min_vruntime, vruntime); +} + /* * Enqueue an entity into the rb-tree: */ @@ -256,15 +325,8 @@ static void __enqueue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se) * Maintain a cache of leftmost tree entries (it is frequently * used): */ - if (leftmost) { + if (leftmost) cfs_rq->rb_leftmost = &se->run_node; - /* - * maintain cfs_rq->min_vruntime to be a monotonic increasing - * value tracking the leftmost vruntime in the tree. - */ - cfs_rq->min_vruntime = - max_vruntime(cfs_rq->min_vruntime, se->vruntime); - } rb_link_node(&se->run_node, parent, link); rb_insert_color(&se->run_node, &cfs_rq->tasks_timeline); @@ -274,37 +336,25 @@ static void __dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se) { if (cfs_rq->rb_leftmost == &se->run_node) { struct rb_node *next_node; - struct sched_entity *next; next_node = rb_next(&se->run_node); cfs_rq->rb_leftmost = next_node; - - if (next_node) { - next = rb_entry(next_node, - struct sched_entity, run_node); - cfs_rq->min_vruntime = - max_vruntime(cfs_rq->min_vruntime, - next->vruntime); - } } - if (cfs_rq->next == se) - cfs_rq->next = NULL; - rb_erase(&se->run_node, &cfs_rq->tasks_timeline); } -static inline struct rb_node *first_fair(struct cfs_rq *cfs_rq) -{ - return cfs_rq->rb_leftmost; -} - static struct sched_entity *__pick_next_entity(struct cfs_rq *cfs_rq) { - return rb_entry(first_fair(cfs_rq), struct sched_entity, run_node); + struct rb_node *left = cfs_rq->rb_leftmost; + + if (!left) + return NULL; + + return rb_entry(left, struct sched_entity, run_node); } -static inline struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) +static struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) { struct rb_node *last = rb_last(&cfs_rq->tasks_timeline); @@ -424,6 +474,7 @@ __update_curr(struct cfs_rq *cfs_rq, struct sched_entity *curr, schedstat_add(cfs_rq, exec_clock, delta_exec); delta_exec_weighted = calc_delta_fair(delta_exec, curr); curr->vruntime += delta_exec_weighted; + update_min_vruntime(cfs_rq); } static void update_curr(struct cfs_rq *cfs_rq) @@ -613,13 +664,7 @@ static void check_spread(struct cfs_rq *cfs_rq, struct sched_entity *se) static void place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) { - u64 vruntime; - - if (first_fair(cfs_rq)) { - vruntime = min_vruntime(cfs_rq->min_vruntime, - __pick_next_entity(cfs_rq)->vruntime); - } else - vruntime = cfs_rq->min_vruntime; + u64 vruntime = cfs_rq->min_vruntime; /* * The 'current' period is already promised to the current tasks, @@ -671,6 +716,15 @@ enqueue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int wakeup) __enqueue_entity(cfs_rq, se); } +static void clear_buddies(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ + if (cfs_rq->last == se) + cfs_rq->last = NULL; + + if (cfs_rq->next == se) + cfs_rq->next = NULL; +} + static void dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int sleep) { @@ -693,9 +747,12 @@ dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int sleep) #endif } + clear_buddies(cfs_rq, se); + if (se != cfs_rq->curr) __dequeue_entity(cfs_rq, se); account_entity_dequeue(cfs_rq, se); + update_min_vruntime(cfs_rq); } /* @@ -742,29 +799,18 @@ set_next_entity(struct cfs_rq *cfs_rq, struct sched_entity *se) se->prev_sum_exec_runtime = se->sum_exec_runtime; } -static struct sched_entity * -pick_next(struct cfs_rq *cfs_rq, struct sched_entity *se) -{ - struct rq *rq = rq_of(cfs_rq); - u64 pair_slice = rq->clock - cfs_rq->pair_start; - - if (!cfs_rq->next || pair_slice > sysctl_sched_min_granularity) { - cfs_rq->pair_start = rq->clock; - return se; - } - - return cfs_rq->next; -} +static int +wakeup_preempt_entity(struct sched_entity *curr, struct sched_entity *se); static struct sched_entity *pick_next_entity(struct cfs_rq *cfs_rq) { - struct sched_entity *se = NULL; + struct sched_entity *se = __pick_next_entity(cfs_rq); - if (first_fair(cfs_rq)) { - se = __pick_next_entity(cfs_rq); - se = pick_next(cfs_rq, se); - set_next_entity(cfs_rq, se); - } + if (cfs_rq->next && wakeup_preempt_entity(cfs_rq->next, se) < 1) + return cfs_rq->next; + + if (cfs_rq->last && wakeup_preempt_entity(cfs_rq->last, se) < 1) + return cfs_rq->last; return se; } @@ -936,6 +982,8 @@ static void yield_task_fair(struct rq *rq) if (unlikely(cfs_rq->nr_running == 1)) return; + clear_buddies(cfs_rq, se); + if (likely(!sysctl_sched_compat_yield) && curr->policy != SCHED_BATCH) { update_rq_clock(rq); /* @@ -1122,10 +1170,9 @@ wake_affine(struct sched_domain *this_sd, struct rq *this_rq, if (!(this_sd->flags & SD_WAKE_AFFINE) || !sched_feat(AFFINE_WAKEUPS)) return 0; - if (!sync && sched_feat(SYNC_WAKEUPS) && - curr->se.avg_overlap < sysctl_sched_migration_cost && - p->se.avg_overlap < sysctl_sched_migration_cost) - sync = 1; + if (sync && (curr->se.avg_overlap > sysctl_sched_migration_cost || + p->se.avg_overlap > sysctl_sched_migration_cost)) + sync = 0; /* * If sync wakeup then subtract the (maximum possible) @@ -1244,33 +1291,88 @@ static unsigned long wakeup_gran(struct sched_entity *se) * More easily preempt - nice tasks, while not making it harder for * + nice tasks. */ - if (sched_feat(ASYM_GRAN)) - gran = calc_delta_mine(gran, NICE_0_LOAD, &se->load); + if (!sched_feat(ASYM_GRAN) || se->load.weight > NICE_0_LOAD) + gran = calc_delta_fair(sysctl_sched_wakeup_granularity, se); return gran; } +/* + * Should 'se' preempt 'curr'. + * + * |s1 + * |s2 + * |s3 + * g + * |<--->|c + * + * w(c, s1) = -1 + * w(c, s2) = 0 + * w(c, s3) = 1 + * + */ +static int +wakeup_preempt_entity(struct sched_entity *curr, struct sched_entity *se) +{ + s64 gran, vdiff = curr->vruntime - se->vruntime; + + if (vdiff <= 0) + return -1; + + gran = wakeup_gran(curr); + if (vdiff > gran) + return 1; + + return 0; +} + +static void set_last_buddy(struct sched_entity *se) +{ + for_each_sched_entity(se) + cfs_rq_of(se)->last = se; +} + +static void set_next_buddy(struct sched_entity *se) +{ + for_each_sched_entity(se) + cfs_rq_of(se)->next = se; +} + /* * Preempt the current task with a newly woken task if needed: */ static void check_preempt_wakeup(struct rq *rq, struct task_struct *p, int sync) { struct task_struct *curr = rq->curr; - struct cfs_rq *cfs_rq = task_cfs_rq(curr); struct sched_entity *se = &curr->se, *pse = &p->se; - s64 delta_exec; if (unlikely(rt_prio(p->prio))) { + struct cfs_rq *cfs_rq = task_cfs_rq(curr); + update_rq_clock(rq); update_curr(cfs_rq); resched_task(curr); return; } + if (unlikely(p->sched_class != &fair_sched_class)) + return; + if (unlikely(se == pse)) return; - cfs_rq_of(pse)->next = pse; + /* + * Only set the backward buddy when the current task is still on the + * rq. This can happen when a wakeup gets interleaved with schedule on + * the ->pre_schedule() or idle_balance() point, either of which can + * drop the rq lock. + * + * Also, during early boot the idle thread is in the fair class, for + * obvious reasons its a bad idea to schedule back to the idle thread. + */ + if (sched_feat(LAST_BUDDY) && likely(se->on_rq && curr != rq->idle)) + set_last_buddy(se); + set_next_buddy(pse); /* * We can come here with TIF_NEED_RESCHED already set from new task @@ -1296,9 +1398,19 @@ static void check_preempt_wakeup(struct rq *rq, struct task_struct *p, int sync) return; } - delta_exec = se->sum_exec_runtime - se->prev_sum_exec_runtime; - if (delta_exec > wakeup_gran(pse)) - resched_task(curr); + find_matching_se(&se, &pse); + + while (se) { + BUG_ON(!pse); + + if (wakeup_preempt_entity(se, pse) == 1) { + resched_task(curr); + break; + } + + se = parent_entity(se); + pse = parent_entity(pse); + } } static struct task_struct *pick_next_task_fair(struct rq *rq) @@ -1312,6 +1424,7 @@ static struct task_struct *pick_next_task_fair(struct rq *rq) do { se = pick_next_entity(cfs_rq); + set_next_entity(cfs_rq, se); cfs_rq = group_cfs_rq(se); } while (cfs_rq); @@ -1594,9 +1707,6 @@ static const struct sched_class fair_sched_class = { .enqueue_task = enqueue_task_fair, .dequeue_task = dequeue_task_fair, .yield_task = yield_task_fair, -#ifdef CONFIG_SMP - .select_task_rq = select_task_rq_fair, -#endif /* CONFIG_SMP */ .check_preempt_curr = check_preempt_wakeup, @@ -1604,6 +1714,8 @@ static const struct sched_class fair_sched_class = { .put_prev_task = put_prev_task_fair, #ifdef CONFIG_SMP + .select_task_rq = select_task_rq_fair, + .load_balance = load_balance_fair, .move_one_task = move_one_task_fair, #endif diff --git a/kernel/sched_features.h b/kernel/sched_features.h index fda016218296..da5d93b5d2c6 100644 --- a/kernel/sched_features.h +++ b/kernel/sched_features.h @@ -12,3 +12,4 @@ SCHED_FEAT(LB_BIAS, 1) SCHED_FEAT(LB_WAKEUP_UPDATE, 1) SCHED_FEAT(ASYM_EFF_LOAD, 1) SCHED_FEAT(WAKEUP_OVERLAP, 0) +SCHED_FEAT(LAST_BUDDY, 1) diff --git a/kernel/sched_idletask.c b/kernel/sched_idletask.c index dec4ccabe2f5..8a21a2e28c13 100644 --- a/kernel/sched_idletask.c +++ b/kernel/sched_idletask.c @@ -105,9 +105,6 @@ static const struct sched_class idle_sched_class = { /* dequeue is not valid, we print a debug message there: */ .dequeue_task = dequeue_task_idle, -#ifdef CONFIG_SMP - .select_task_rq = select_task_rq_idle, -#endif /* CONFIG_SMP */ .check_preempt_curr = check_preempt_curr_idle, @@ -115,6 +112,8 @@ static const struct sched_class idle_sched_class = { .put_prev_task = put_prev_task_idle, #ifdef CONFIG_SMP + .select_task_rq = select_task_rq_idle, + .load_balance = load_balance_idle, .move_one_task = move_one_task_idle, #endif diff --git a/kernel/sched_rt.c b/kernel/sched_rt.c index b446dc87494f..d9ba9d5f99d6 100644 --- a/kernel/sched_rt.c +++ b/kernel/sched_rt.c @@ -1504,9 +1504,6 @@ static const struct sched_class rt_sched_class = { .enqueue_task = enqueue_task_rt, .dequeue_task = dequeue_task_rt, .yield_task = yield_task_rt, -#ifdef CONFIG_SMP - .select_task_rq = select_task_rq_rt, -#endif /* CONFIG_SMP */ .check_preempt_curr = check_preempt_curr_rt, @@ -1514,6 +1511,8 @@ static const struct sched_class rt_sched_class = { .put_prev_task = put_prev_task_rt, #ifdef CONFIG_SMP + .select_task_rq = select_task_rq_rt, + .load_balance = load_balance_rt, .move_one_task = move_one_task_rt, .set_cpus_allowed = set_cpus_allowed_rt, diff --git a/kernel/sched_stats.h b/kernel/sched_stats.h index ee71bec1da66..7dbf72a2b02c 100644 --- a/kernel/sched_stats.h +++ b/kernel/sched_stats.h @@ -298,9 +298,11 @@ static inline void account_group_user_time(struct task_struct *tsk, { struct signal_struct *sig; - sig = tsk->signal; - if (unlikely(!sig)) + /* tsk == current, ensure it is safe to use ->signal */ + if (unlikely(tsk->exit_state)) return; + + sig = tsk->signal; if (sig->cputime.totals) { struct task_cputime *times; @@ -325,9 +327,11 @@ static inline void account_group_system_time(struct task_struct *tsk, { struct signal_struct *sig; - sig = tsk->signal; - if (unlikely(!sig)) + /* tsk == current, ensure it is safe to use ->signal */ + if (unlikely(tsk->exit_state)) return; + + sig = tsk->signal; if (sig->cputime.totals) { struct task_cputime *times; @@ -353,8 +357,11 @@ static inline void account_group_exec_runtime(struct task_struct *tsk, struct signal_struct *sig; sig = tsk->signal; + /* see __exit_signal()->task_rq_unlock_wait() */ + barrier(); if (unlikely(!sig)) return; + if (sig->cputime.totals) { struct task_cputime *times; diff --git a/kernel/signal.c b/kernel/signal.c index 105217da5c82..4530fc654455 100644 --- a/kernel/signal.c +++ b/kernel/signal.c @@ -1144,7 +1144,8 @@ static int kill_something_info(int sig, struct siginfo *info, pid_t pid) struct task_struct * p; for_each_process(p) { - if (p->pid > 1 && !same_thread_group(p, current)) { + if (task_pid_vnr(p) > 1 && + !same_thread_group(p, current)) { int err = group_send_sig_info(sig, info, p); ++count; if (err != -EPERM) diff --git a/kernel/smp.c b/kernel/smp.c index f362a8553777..75c8dde58c55 100644 --- a/kernel/smp.c +++ b/kernel/smp.c @@ -51,10 +51,6 @@ static void csd_flag_wait(struct call_single_data *data) { /* Wait for response */ do { - /* - * We need to see the flags store in the IPI handler - */ - smp_mb(); if (!(data->flags & CSD_FLAG_WAIT)) break; cpu_relax(); @@ -76,6 +72,11 @@ static void generic_exec_single(int cpu, struct call_single_data *data) list_add_tail(&data->list, &dst->list); spin_unlock_irqrestore(&dst->lock, flags); + /* + * Make the list addition visible before sending the ipi. + */ + smp_mb(); + if (ipi) arch_send_call_function_single_ipi(cpu); @@ -157,7 +158,7 @@ void generic_smp_call_function_single_interrupt(void) * Need to see other stores to list head for checking whether * list is empty without holding q->lock */ - smp_mb(); + smp_read_barrier_depends(); while (!list_empty(&q->list)) { unsigned int data_flags; @@ -191,7 +192,7 @@ void generic_smp_call_function_single_interrupt(void) /* * See comment on outer loop */ - smp_mb(); + smp_read_barrier_depends(); } } @@ -370,6 +371,11 @@ int smp_call_function_mask(cpumask_t mask, void (*func)(void *), void *info, list_add_tail_rcu(&data->csd.list, &call_function_queue); spin_unlock_irqrestore(&call_function_lock, flags); + /* + * Make the list addition visible before sending the ipi. + */ + smp_mb(); + /* Send a message to all CPUs in the map */ arch_send_call_function_ipi(mask); diff --git a/kernel/softirq.c b/kernel/softirq.c index 7110daeb9a90..e7c69a720d69 100644 --- a/kernel/softirq.c +++ b/kernel/softirq.c @@ -269,10 +269,11 @@ void irq_enter(void) { int cpu = smp_processor_id(); - if (idle_cpu(cpu) && !in_interrupt()) + if (idle_cpu(cpu) && !in_interrupt()) { + __irq_enter(); tick_check_idle(cpu); - - __irq_enter(); + } else + __irq_enter(); } #ifdef __ARCH_IRQ_EXIT_IRQS_DISABLED diff --git a/kernel/softlockup.c b/kernel/softlockup.c index 3953e4aed733..dc0b3be6b7d5 100644 --- a/kernel/softlockup.c +++ b/kernel/softlockup.c @@ -188,7 +188,7 @@ static void check_hung_task(struct task_struct *t, unsigned long now) if ((long)(now - t->last_switch_timestamp) < sysctl_hung_task_timeout_secs) return; - if (sysctl_hung_task_warnings < 0) + if (!sysctl_hung_task_warnings) return; sysctl_hung_task_warnings--; diff --git a/kernel/stop_machine.c b/kernel/stop_machine.c index 9bc4c00872c9..24e8ceacc388 100644 --- a/kernel/stop_machine.c +++ b/kernel/stop_machine.c @@ -112,7 +112,7 @@ static int chill(void *unused) int __stop_machine(int (*fn)(void *), void *data, const cpumask_t *cpus) { struct work_struct *sm_work; - int i; + int i, ret; /* Set up initial state. */ mutex_lock(&lock); @@ -137,8 +137,9 @@ int __stop_machine(int (*fn)(void *), void *data, const cpumask_t *cpus) /* This will release the thread on our CPU. */ put_cpu(); flush_workqueue(stop_machine_wq); + ret = active.fnret; mutex_unlock(&lock); - return active.fnret; + return ret; } int stop_machine(int (*fn)(void *), void *data, const cpumask_t *cpus) diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index a77b27b11b04..e14a23281707 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -31,7 +31,7 @@ cond_syscall(sys_socketpair); cond_syscall(sys_bind); cond_syscall(sys_listen); cond_syscall(sys_accept); -cond_syscall(sys_paccept); +cond_syscall(sys_accept4); cond_syscall(sys_connect); cond_syscall(sys_getsockname); cond_syscall(sys_getpeername); diff --git a/kernel/sysctl.c b/kernel/sysctl.c index a13bd4dfaeb1..3d56fe7570da 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -176,6 +176,9 @@ extern struct ctl_table random_table[]; #ifdef CONFIG_INOTIFY_USER extern struct ctl_table inotify_table[]; #endif +#ifdef CONFIG_EPOLL +extern struct ctl_table epoll_table[]; +#endif #ifdef HAVE_ARCH_PICK_MMAP_LAYOUT int sysctl_legacy_va_layout; @@ -474,7 +477,7 @@ static struct ctl_table kern_table[] = { .mode = 0644, .proc_handler = &proc_dointvec, }, -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER { .ctl_name = CTL_UNNUMBERED, .procname = "ftrace_enabled", @@ -1325,6 +1328,13 @@ static struct ctl_table fs_table[] = { .child = inotify_table, }, #endif +#ifdef CONFIG_EPOLL + { + .procname = "epoll", + .mode = 0555, + .child = epoll_table, + }, +#endif #endif { .ctl_name = KERN_SETUID_DUMPABLE, diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 5bbb1044f847..342fc9ccab46 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -568,6 +568,9 @@ static void tick_nohz_switch_to_nohz(void) */ static void tick_nohz_kick_tick(int cpu) { +#if 0 + /* Switch back to 2.6.27 behaviour */ + struct tick_sched *ts = &per_cpu(tick_cpu_sched, cpu); ktime_t delta, now; @@ -584,6 +587,7 @@ static void tick_nohz_kick_tick(int cpu) return; tick_nohz_restart(ts, now); +#endif } #else diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index e7acfb482a68..fa05e88aa76f 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -518,6 +518,28 @@ void update_wall_time(void) /* correct the clock when NTP error is too big */ clocksource_adjust(offset); + /* + * Since in the loop above, we accumulate any amount of time + * in xtime_nsec over a second into xtime.tv_sec, its possible for + * xtime_nsec to be fairly small after the loop. Further, if we're + * slightly speeding the clocksource up in clocksource_adjust(), + * its possible the required corrective factor to xtime_nsec could + * cause it to underflow. + * + * Now, we cannot simply roll the accumulated second back, since + * the NTP subsystem has been notified via second_overflow. So + * instead we push xtime_nsec forward by the amount we underflowed, + * and add that amount into the error. + * + * We'll correct this error next time through this function, when + * xtime_nsec is not as small. + */ + if (unlikely((s64)clock->xtime_nsec < 0)) { + s64 neg = -(s64)clock->xtime_nsec; + clock->xtime_nsec = 0; + clock->error += neg << (NTP_SCALE_SHIFT - clock->shift); + } + /* store full nanoseconds into xtime after rounding it up and * add the remainder to the error difference. */ diff --git a/kernel/timer.c b/kernel/timer.c index 56becf373c58..dbd50fabe4c7 100644 --- a/kernel/timer.c +++ b/kernel/timer.c @@ -112,27 +112,8 @@ timer_set_base(struct timer_list *timer, struct tvec_base *new_base) tbase_get_deferrable(timer->base)); } -/** - * __round_jiffies - function to round jiffies to a full second - * @j: the time in (absolute) jiffies that should be rounded - * @cpu: the processor number on which the timeout will happen - * - * __round_jiffies() rounds an absolute time in the future (in jiffies) - * up or down to (approximately) full seconds. This is useful for timers - * for which the exact time they fire does not matter too much, as long as - * they fire approximately every X seconds. - * - * By rounding these timers to whole seconds, all such timers will fire - * at the same time, rather than at various times spread out. The goal - * of this is to have the CPU wake up less, which saves power. - * - * The exact rounding is skewed for each processor to avoid all - * processors firing at the exact same time, which could lead - * to lock contention or spurious cache line bouncing. - * - * The return value is the rounded version of the @j parameter. - */ -unsigned long __round_jiffies(unsigned long j, int cpu) +static unsigned long round_jiffies_common(unsigned long j, int cpu, + bool force_up) { int rem; unsigned long original = j; @@ -154,8 +135,9 @@ unsigned long __round_jiffies(unsigned long j, int cpu) * due to delays of the timer irq, long irq off times etc etc) then * we should round down to the whole second, not up. Use 1/4th second * as cutoff for this rounding as an extreme upper bound for this. + * But never round down if @force_up is set. */ - if (rem < HZ/4) /* round down */ + if (rem < HZ/4 && !force_up) /* round down */ j = j - rem; else /* round up */ j = j - rem + HZ; @@ -167,6 +149,31 @@ unsigned long __round_jiffies(unsigned long j, int cpu) return original; return j; } + +/** + * __round_jiffies - function to round jiffies to a full second + * @j: the time in (absolute) jiffies that should be rounded + * @cpu: the processor number on which the timeout will happen + * + * __round_jiffies() rounds an absolute time in the future (in jiffies) + * up or down to (approximately) full seconds. This is useful for timers + * for which the exact time they fire does not matter too much, as long as + * they fire approximately every X seconds. + * + * By rounding these timers to whole seconds, all such timers will fire + * at the same time, rather than at various times spread out. The goal + * of this is to have the CPU wake up less, which saves power. + * + * The exact rounding is skewed for each processor to avoid all + * processors firing at the exact same time, which could lead + * to lock contention or spurious cache line bouncing. + * + * The return value is the rounded version of the @j parameter. + */ +unsigned long __round_jiffies(unsigned long j, int cpu) +{ + return round_jiffies_common(j, cpu, false); +} EXPORT_SYMBOL_GPL(__round_jiffies); /** @@ -191,13 +198,10 @@ EXPORT_SYMBOL_GPL(__round_jiffies); */ unsigned long __round_jiffies_relative(unsigned long j, int cpu) { - /* - * In theory the following code can skip a jiffy in case jiffies - * increments right between the addition and the later subtraction. - * However since the entire point of this function is to use approximate - * timeouts, it's entirely ok to not handle that. - */ - return __round_jiffies(j + jiffies, cpu) - jiffies; + unsigned long j0 = jiffies; + + /* Use j0 because jiffies might change while we run */ + return round_jiffies_common(j + j0, cpu, false) - j0; } EXPORT_SYMBOL_GPL(__round_jiffies_relative); @@ -218,7 +222,7 @@ EXPORT_SYMBOL_GPL(__round_jiffies_relative); */ unsigned long round_jiffies(unsigned long j) { - return __round_jiffies(j, raw_smp_processor_id()); + return round_jiffies_common(j, raw_smp_processor_id(), false); } EXPORT_SYMBOL_GPL(round_jiffies); @@ -243,6 +247,71 @@ unsigned long round_jiffies_relative(unsigned long j) } EXPORT_SYMBOL_GPL(round_jiffies_relative); +/** + * __round_jiffies_up - function to round jiffies up to a full second + * @j: the time in (absolute) jiffies that should be rounded + * @cpu: the processor number on which the timeout will happen + * + * This is the same as __round_jiffies() except that it will never + * round down. This is useful for timeouts for which the exact time + * of firing does not matter too much, as long as they don't fire too + * early. + */ +unsigned long __round_jiffies_up(unsigned long j, int cpu) +{ + return round_jiffies_common(j, cpu, true); +} +EXPORT_SYMBOL_GPL(__round_jiffies_up); + +/** + * __round_jiffies_up_relative - function to round jiffies up to a full second + * @j: the time in (relative) jiffies that should be rounded + * @cpu: the processor number on which the timeout will happen + * + * This is the same as __round_jiffies_relative() except that it will never + * round down. This is useful for timeouts for which the exact time + * of firing does not matter too much, as long as they don't fire too + * early. + */ +unsigned long __round_jiffies_up_relative(unsigned long j, int cpu) +{ + unsigned long j0 = jiffies; + + /* Use j0 because jiffies might change while we run */ + return round_jiffies_common(j + j0, cpu, true) - j0; +} +EXPORT_SYMBOL_GPL(__round_jiffies_up_relative); + +/** + * round_jiffies_up - function to round jiffies up to a full second + * @j: the time in (absolute) jiffies that should be rounded + * + * This is the same as round_jiffies() except that it will never + * round down. This is useful for timeouts for which the exact time + * of firing does not matter too much, as long as they don't fire too + * early. + */ +unsigned long round_jiffies_up(unsigned long j) +{ + return round_jiffies_common(j, raw_smp_processor_id(), true); +} +EXPORT_SYMBOL_GPL(round_jiffies_up); + +/** + * round_jiffies_up_relative - function to round jiffies up to a full second + * @j: the time in (relative) jiffies that should be rounded + * + * This is the same as round_jiffies_relative() except that it will never + * round down. This is useful for timeouts for which the exact time + * of firing does not matter too much, as long as they don't fire too + * early. + */ +unsigned long round_jiffies_up_relative(unsigned long j) +{ + return __round_jiffies_up_relative(j, raw_smp_processor_id()); +} +EXPORT_SYMBOL_GPL(round_jiffies_up_relative); + static inline void set_running_timer(struct tvec_base *base, struct timer_list *timer) diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index 1cb3e1f616af..33dbefd471e8 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -1,13 +1,13 @@ # -# Architectures that offer an FTRACE implementation should select HAVE_FTRACE: +# Architectures that offer an FUNCTION_TRACER implementation should +# select HAVE_FUNCTION_TRACER: # config NOP_TRACER bool -config HAVE_FTRACE +config HAVE_FUNCTION_TRACER bool - select NOP_TRACER config HAVE_DYNAMIC_FTRACE bool @@ -25,12 +25,15 @@ config TRACING bool select DEBUG_FS select RING_BUFFER - select STACKTRACE + select STACKTRACE if STACKTRACE_SUPPORT select TRACEPOINTS + select NOP_TRACER -config FTRACE +menu "Tracers" + +config FUNCTION_TRACER bool "Kernel Function Tracer" - depends on HAVE_FTRACE + depends on HAVE_FUNCTION_TRACER depends on DEBUG_KERNEL select FRAME_POINTER select TRACING @@ -49,7 +52,6 @@ config IRQSOFF_TRACER default n depends on TRACE_IRQFLAGS_SUPPORT depends on GENERIC_TIME - depends on HAVE_FTRACE depends on DEBUG_KERNEL select TRACE_IRQFLAGS select TRACING @@ -73,7 +75,6 @@ config PREEMPT_TRACER default n depends on GENERIC_TIME depends on PREEMPT - depends on HAVE_FTRACE depends on DEBUG_KERNEL select TRACING select TRACER_MAX_TRACE @@ -101,7 +102,6 @@ config SYSPROF_TRACER config SCHED_TRACER bool "Scheduling Latency Tracer" - depends on HAVE_FTRACE depends on DEBUG_KERNEL select TRACING select CONTEXT_SWITCH_TRACER @@ -112,7 +112,6 @@ config SCHED_TRACER config CONTEXT_SWITCH_TRACER bool "Trace process context switches" - depends on HAVE_FTRACE depends on DEBUG_KERNEL select TRACING select MARKERS @@ -122,9 +121,9 @@ config CONTEXT_SWITCH_TRACER config BOOT_TRACER bool "Trace boot initcalls" - depends on HAVE_FTRACE depends on DEBUG_KERNEL select TRACING + select CONTEXT_SWITCH_TRACER help This tracer helps developers to optimize boot times: it records the timings of the initcalls and traces key events and the identity @@ -141,9 +140,9 @@ config BOOT_TRACER config STACK_TRACER bool "Trace max stack" - depends on HAVE_FTRACE + depends on HAVE_FUNCTION_TRACER depends on DEBUG_KERNEL - select FTRACE + select FUNCTION_TRACER select STACKTRACE help This special tracer records the maximum stack footprint of the @@ -160,7 +159,7 @@ config STACK_TRACER config DYNAMIC_FTRACE bool "enable/disable ftrace tracepoints dynamically" - depends on FTRACE + depends on FUNCTION_TRACER depends on HAVE_DYNAMIC_FTRACE depends on DEBUG_KERNEL default y @@ -170,7 +169,7 @@ config DYNAMIC_FTRACE with a No-Op instruction) as they are called. A table is created to dynamically enable them again. - This way a CONFIG_FTRACE kernel is slightly larger, but otherwise + This way a CONFIG_FUNCTION_TRACER kernel is slightly larger, but otherwise has native performance as long as no tracing is active. The changes to the code are done by a kernel thread that @@ -195,3 +194,5 @@ config FTRACE_STARTUP_TEST a series of tests are made to verify that the tracer is functioning properly. It will do tests on all the configured tracers of ftrace. + +endmenu diff --git a/kernel/trace/Makefile b/kernel/trace/Makefile index a85dfba88ba0..c8228b1a49e9 100644 --- a/kernel/trace/Makefile +++ b/kernel/trace/Makefile @@ -1,7 +1,7 @@ # Do not instrument the tracer itself: -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg,,$(ORIG_CFLAGS)) @@ -10,13 +10,13 @@ CFLAGS_trace_selftest_dynamic.o = -pg obj-y += trace_selftest_dynamic.o endif -obj-$(CONFIG_FTRACE) += libftrace.o +obj-$(CONFIG_FUNCTION_TRACER) += libftrace.o obj-$(CONFIG_RING_BUFFER) += ring_buffer.o obj-$(CONFIG_TRACING) += trace.o obj-$(CONFIG_CONTEXT_SWITCH_TRACER) += trace_sched_switch.o obj-$(CONFIG_SYSPROF_TRACER) += trace_sysprof.o -obj-$(CONFIG_FTRACE) += trace_functions.o +obj-$(CONFIG_FUNCTION_TRACER) += trace_functions.o obj-$(CONFIG_IRQSOFF_TRACER) += trace_irqsoff.o obj-$(CONFIG_PREEMPT_TRACER) += trace_irqsoff.o obj-$(CONFIG_SCHED_TRACER) += trace_sched_wakeup.o diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 4dda4f60a2a9..78db083390f0 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -25,13 +25,24 @@ #include #include #include -#include #include #include #include "trace.h" +#define FTRACE_WARN_ON(cond) \ + do { \ + if (WARN_ON(cond)) \ + ftrace_kill(); \ + } while (0) + +#define FTRACE_WARN_ON_ONCE(cond) \ + do { \ + if (WARN_ON_ONCE(cond)) \ + ftrace_kill(); \ + } while (0) + /* ftrace_enabled is a method to turn ftrace on or off */ int ftrace_enabled __read_mostly; static int last_ftrace_enabled; @@ -153,21 +164,8 @@ static int __unregister_ftrace_function(struct ftrace_ops *ops) } #ifdef CONFIG_DYNAMIC_FTRACE - #ifndef CONFIG_FTRACE_MCOUNT_RECORD -/* - * The hash lock is only needed when the recording of the mcount - * callers are dynamic. That is, by the caller themselves and - * not recorded via the compilation. - */ -static DEFINE_SPINLOCK(ftrace_hash_lock); -#define ftrace_hash_lock(flags) spin_lock_irqsave(&ftrace_hash_lock, flags) -#define ftrace_hash_unlock(flags) \ - spin_unlock_irqrestore(&ftrace_hash_lock, flags) -#else -/* This is protected via the ftrace_lock with MCOUNT_RECORD. */ -#define ftrace_hash_lock(flags) do { (void)(flags); } while (0) -#define ftrace_hash_unlock(flags) do { } while(0) +# error Dynamic ftrace depends on MCOUNT_RECORD #endif /* @@ -178,8 +176,6 @@ static DEFINE_SPINLOCK(ftrace_hash_lock); */ static unsigned long mcount_addr = MCOUNT_ADDR; -static struct task_struct *ftraced_task; - enum { FTRACE_ENABLE_CALLS = (1 << 0), FTRACE_DISABLE_CALLS = (1 << 1), @@ -189,14 +185,9 @@ enum { }; static int ftrace_filtered; -static int tracing_on; -static int frozen_record_count; - -static struct hlist_head ftrace_hash[FTRACE_HASHSIZE]; -static DEFINE_PER_CPU(int, ftrace_shutdown_disable_cpu); +static LIST_HEAD(ftrace_new_addrs); -static DEFINE_MUTEX(ftraced_lock); static DEFINE_MUTEX(ftrace_regex_lock); struct ftrace_page { @@ -214,16 +205,13 @@ struct ftrace_page { static struct ftrace_page *ftrace_pages_start; static struct ftrace_page *ftrace_pages; -static int ftraced_trigger; -static int ftraced_suspend; -static int ftraced_stop; - -static int ftrace_record_suspend; - static struct dyn_ftrace *ftrace_free_records; #ifdef CONFIG_KPROBES + +static int frozen_record_count; + static inline void freeze_record(struct dyn_ftrace *rec) { if (!(rec->flags & FTRACE_FL_FROZEN)) { @@ -250,72 +238,6 @@ static inline int record_frozen(struct dyn_ftrace *rec) # define record_frozen(rec) ({ 0; }) #endif /* CONFIG_KPROBES */ -int skip_trace(unsigned long ip) -{ - unsigned long fl; - struct dyn_ftrace *rec; - struct hlist_node *t; - struct hlist_head *head; - - if (frozen_record_count == 0) - return 0; - - head = &ftrace_hash[hash_long(ip, FTRACE_HASHBITS)]; - hlist_for_each_entry_rcu(rec, t, head, node) { - if (rec->ip == ip) { - if (record_frozen(rec)) { - if (rec->flags & FTRACE_FL_FAILED) - return 1; - - if (!(rec->flags & FTRACE_FL_CONVERTED)) - return 1; - - if (!tracing_on || !ftrace_enabled) - return 1; - - if (ftrace_filtered) { - fl = rec->flags & (FTRACE_FL_FILTER | - FTRACE_FL_NOTRACE); - if (!fl || (fl & FTRACE_FL_NOTRACE)) - return 1; - } - } - break; - } - } - - return 0; -} - -static inline int -ftrace_ip_in_hash(unsigned long ip, unsigned long key) -{ - struct dyn_ftrace *p; - struct hlist_node *t; - int found = 0; - - hlist_for_each_entry_rcu(p, t, &ftrace_hash[key], node) { - if (p->ip == ip) { - found = 1; - break; - } - } - - return found; -} - -static inline void -ftrace_add_hash(struct dyn_ftrace *node, unsigned long key) -{ - hlist_add_head_rcu(&node->node, &ftrace_hash[key]); -} - -/* called from kstop_machine */ -static inline void ftrace_del_hash(struct dyn_ftrace *node) -{ - hlist_del(&node->node); -} - static void ftrace_free_rec(struct dyn_ftrace *rec) { rec->ip = (unsigned long)ftrace_free_records; @@ -346,7 +268,6 @@ void ftrace_release(void *start, unsigned long size) } } spin_unlock(&ftrace_lock); - } static struct dyn_ftrace *ftrace_alloc_dyn_node(unsigned long ip) @@ -358,10 +279,8 @@ static struct dyn_ftrace *ftrace_alloc_dyn_node(unsigned long ip) rec = ftrace_free_records; if (unlikely(!(rec->flags & FTRACE_FL_FREE))) { - WARN_ON_ONCE(1); + FTRACE_WARN_ON_ONCE(1); ftrace_free_records = NULL; - ftrace_disabled = 1; - ftrace_enabled = 0; return NULL; } @@ -371,172 +290,125 @@ static struct dyn_ftrace *ftrace_alloc_dyn_node(unsigned long ip) } if (ftrace_pages->index == ENTRIES_PER_PAGE) { - if (!ftrace_pages->next) - return NULL; + if (!ftrace_pages->next) { + /* allocate another page */ + ftrace_pages->next = + (void *)get_zeroed_page(GFP_KERNEL); + if (!ftrace_pages->next) + return NULL; + } ftrace_pages = ftrace_pages->next; } return &ftrace_pages->records[ftrace_pages->index++]; } -static void +static struct dyn_ftrace * ftrace_record_ip(unsigned long ip) { - struct dyn_ftrace *node; - unsigned long flags; - unsigned long key; - int resched; - int cpu; + struct dyn_ftrace *rec; if (!ftrace_enabled || ftrace_disabled) - return; - - resched = need_resched(); - preempt_disable_notrace(); - - /* - * We simply need to protect against recursion. - * Use the the raw version of smp_processor_id and not - * __get_cpu_var which can call debug hooks that can - * cause a recursive crash here. - */ - cpu = raw_smp_processor_id(); - per_cpu(ftrace_shutdown_disable_cpu, cpu)++; - if (per_cpu(ftrace_shutdown_disable_cpu, cpu) != 1) - goto out; - - if (unlikely(ftrace_record_suspend)) - goto out; - - key = hash_long(ip, FTRACE_HASHBITS); - - WARN_ON_ONCE(key >= FTRACE_HASHSIZE); - - if (ftrace_ip_in_hash(ip, key)) - goto out; - - ftrace_hash_lock(flags); - - /* This ip may have hit the hash before the lock */ - if (ftrace_ip_in_hash(ip, key)) - goto out_unlock; - - node = ftrace_alloc_dyn_node(ip); - if (!node) - goto out_unlock; + return NULL; - node->ip = ip; - - ftrace_add_hash(node, key); + rec = ftrace_alloc_dyn_node(ip); + if (!rec) + return NULL; - ftraced_trigger = 1; + rec->ip = ip; - out_unlock: - ftrace_hash_unlock(flags); - out: - per_cpu(ftrace_shutdown_disable_cpu, cpu)--; + list_add(&rec->list, &ftrace_new_addrs); - /* prevent recursion with scheduler */ - if (resched) - preempt_enable_no_resched_notrace(); - else - preempt_enable_notrace(); + return rec; } #define FTRACE_ADDR ((long)(ftrace_caller)) static int __ftrace_replace_code(struct dyn_ftrace *rec, - unsigned char *old, unsigned char *new, int enable) + unsigned char *nop, int enable) { unsigned long ip, fl; + unsigned char *call, *old, *new; ip = rec->ip; - if (ftrace_filtered && enable) { + /* + * If this record is not to be traced and + * it is not enabled then do nothing. + * + * If this record is not to be traced and + * it is enabled then disabled it. + * + */ + if (rec->flags & FTRACE_FL_NOTRACE) { + if (rec->flags & FTRACE_FL_ENABLED) + rec->flags &= ~FTRACE_FL_ENABLED; + else + return 0; + + } else if (ftrace_filtered && enable) { /* - * If filtering is on: - * - * If this record is set to be filtered and - * is enabled then do nothing. - * - * If this record is set to be filtered and - * it is not enabled, enable it. - * - * If this record is not set to be filtered - * and it is not enabled do nothing. - * - * If this record is set not to trace then - * do nothing. - * - * If this record is set not to trace and - * it is enabled then disable it. - * - * If this record is not set to be filtered and - * it is enabled, disable it. + * Filtering is on: */ - fl = rec->flags & (FTRACE_FL_FILTER | FTRACE_FL_NOTRACE | - FTRACE_FL_ENABLED); + fl = rec->flags & (FTRACE_FL_FILTER | FTRACE_FL_ENABLED); - if ((fl == (FTRACE_FL_FILTER | FTRACE_FL_ENABLED)) || - (fl == (FTRACE_FL_FILTER | FTRACE_FL_NOTRACE)) || - !fl || (fl == FTRACE_FL_NOTRACE)) + /* Record is filtered and enabled, do nothing */ + if (fl == (FTRACE_FL_FILTER | FTRACE_FL_ENABLED)) return 0; - /* - * If it is enabled disable it, - * otherwise enable it! - */ - if (fl & FTRACE_FL_ENABLED) { - /* swap new and old */ - new = old; - old = ftrace_call_replace(ip, FTRACE_ADDR); + /* Record is not filtered and is not enabled do nothing */ + if (!fl) + return 0; + + /* Record is not filtered but enabled, disable it */ + if (fl == FTRACE_FL_ENABLED) rec->flags &= ~FTRACE_FL_ENABLED; - } else { - new = ftrace_call_replace(ip, FTRACE_ADDR); + else + /* Otherwise record is filtered but not enabled, enable it */ rec->flags |= FTRACE_FL_ENABLED; - } } else { + /* Disable or not filtered */ if (enable) { - /* - * If this record is set not to trace and is - * not enabled, do nothing. - */ - fl = rec->flags & (FTRACE_FL_NOTRACE | FTRACE_FL_ENABLED); - if (fl == FTRACE_FL_NOTRACE) - return 0; - - new = ftrace_call_replace(ip, FTRACE_ADDR); - } else - old = ftrace_call_replace(ip, FTRACE_ADDR); - - if (enable) { + /* if record is enabled, do nothing */ if (rec->flags & FTRACE_FL_ENABLED) return 0; + rec->flags |= FTRACE_FL_ENABLED; + } else { + + /* if record is not enabled do nothing */ if (!(rec->flags & FTRACE_FL_ENABLED)) return 0; + rec->flags &= ~FTRACE_FL_ENABLED; } } + call = ftrace_call_replace(ip, FTRACE_ADDR); + + if (rec->flags & FTRACE_FL_ENABLED) { + old = nop; + new = call; + } else { + old = call; + new = nop; + } + return ftrace_modify_code(ip, old, new); } static void ftrace_replace_code(int enable) { int i, failed; - unsigned char *new = NULL, *old = NULL; + unsigned char *nop = NULL; struct dyn_ftrace *rec; struct ftrace_page *pg; - if (enable) - old = ftrace_nop_replace(); - else - new = ftrace_nop_replace(); + nop = ftrace_nop_replace(); for (pg = ftrace_pages_start; pg; pg = pg->next) { for (i = 0; i < pg->index; i++) { @@ -554,12 +426,11 @@ static void ftrace_replace_code(int enable) unfreeze_record(rec); } - failed = __ftrace_replace_code(rec, old, new, enable); + failed = __ftrace_replace_code(rec, nop, enable); if (failed && (rec->flags & FTRACE_FL_CONVERTED)) { rec->flags |= FTRACE_FL_FAILED; if ((system_state == SYSTEM_BOOTING) || !core_kernel_text(rec->ip)) { - ftrace_del_hash(rec); ftrace_free_rec(rec); } } @@ -567,15 +438,6 @@ static void ftrace_replace_code(int enable) } } -static void ftrace_shutdown_replenish(void) -{ - if (ftrace_pages->next) - return; - - /* allocate another page */ - ftrace_pages->next = (void *)get_zeroed_page(GFP_KERNEL); -} - static void print_ip_ins(const char *fmt, unsigned char *p) { int i; @@ -591,23 +453,23 @@ ftrace_code_disable(struct dyn_ftrace *rec) { unsigned long ip; unsigned char *nop, *call; - int failed; + int ret; ip = rec->ip; nop = ftrace_nop_replace(); call = ftrace_call_replace(ip, mcount_addr); - failed = ftrace_modify_code(ip, call, nop); - if (failed) { - switch (failed) { - case 1: - WARN_ON_ONCE(1); + ret = ftrace_modify_code(ip, call, nop); + if (ret) { + switch (ret) { + case -EFAULT: + FTRACE_WARN_ON_ONCE(1); pr_info("ftrace faulted on modifying "); print_ip_sym(ip); break; - case 2: - WARN_ON_ONCE(1); + case -EINVAL: + FTRACE_WARN_ON_ONCE(1); pr_info("ftrace failed to modify "); print_ip_sym(ip); print_ip_ins(" expected: ", call); @@ -615,6 +477,15 @@ ftrace_code_disable(struct dyn_ftrace *rec) print_ip_ins(" replace: ", nop); printk(KERN_CONT "\n"); break; + case -EPERM: + FTRACE_WARN_ON_ONCE(1); + pr_info("ftrace faulted on writing "); + print_ip_sym(ip); + break; + default: + FTRACE_WARN_ON_ONCE(1); + pr_info("ftrace faulted on unknown error "); + print_ip_sym(ip); } rec->flags |= FTRACE_FL_FAILED; @@ -623,37 +494,18 @@ ftrace_code_disable(struct dyn_ftrace *rec) return 1; } -static int __ftrace_update_code(void *ignore); - static int __ftrace_modify_code(void *data) { - unsigned long addr; int *command = data; - if (*command & FTRACE_ENABLE_CALLS) { - /* - * Update any recorded ips now that we have the - * machine stopped - */ - __ftrace_update_code(NULL); + if (*command & FTRACE_ENABLE_CALLS) ftrace_replace_code(1); - tracing_on = 1; - } else if (*command & FTRACE_DISABLE_CALLS) { + else if (*command & FTRACE_DISABLE_CALLS) ftrace_replace_code(0); - tracing_on = 0; - } if (*command & FTRACE_UPDATE_TRACE_FUNC) ftrace_update_ftrace_func(ftrace_trace_function); - if (*command & FTRACE_ENABLE_MCOUNT) { - addr = (unsigned long)ftrace_record_ip; - ftrace_mcount_set(&addr); - } else if (*command & FTRACE_DISABLE_MCOUNT) { - addr = (unsigned long)ftrace_stub; - ftrace_mcount_set(&addr); - } - return 0; } @@ -662,26 +514,9 @@ static void ftrace_run_update_code(int command) stop_machine(__ftrace_modify_code, &command, NULL); } -void ftrace_disable_daemon(void) -{ - /* Stop the daemon from calling kstop_machine */ - mutex_lock(&ftraced_lock); - ftraced_stop = 1; - mutex_unlock(&ftraced_lock); - - ftrace_force_update(); -} - -void ftrace_enable_daemon(void) -{ - mutex_lock(&ftraced_lock); - ftraced_stop = 0; - mutex_unlock(&ftraced_lock); - - ftrace_force_update(); -} - static ftrace_func_t saved_ftrace_func; +static int ftrace_start; +static DEFINE_MUTEX(ftrace_start_lock); static void ftrace_startup(void) { @@ -690,10 +525,9 @@ static void ftrace_startup(void) if (unlikely(ftrace_disabled)) return; - mutex_lock(&ftraced_lock); - ftraced_suspend++; - if (ftraced_suspend == 1) - command |= FTRACE_ENABLE_CALLS; + mutex_lock(&ftrace_start_lock); + ftrace_start++; + command |= FTRACE_ENABLE_CALLS; if (saved_ftrace_func != ftrace_trace_function) { saved_ftrace_func = ftrace_trace_function; @@ -705,7 +539,7 @@ static void ftrace_startup(void) ftrace_run_update_code(command); out: - mutex_unlock(&ftraced_lock); + mutex_unlock(&ftrace_start_lock); } static void ftrace_shutdown(void) @@ -715,9 +549,9 @@ static void ftrace_shutdown(void) if (unlikely(ftrace_disabled)) return; - mutex_lock(&ftraced_lock); - ftraced_suspend--; - if (!ftraced_suspend) + mutex_lock(&ftrace_start_lock); + ftrace_start--; + if (!ftrace_start) command |= FTRACE_DISABLE_CALLS; if (saved_ftrace_func != ftrace_trace_function) { @@ -730,7 +564,7 @@ static void ftrace_shutdown(void) ftrace_run_update_code(command); out: - mutex_unlock(&ftraced_lock); + mutex_unlock(&ftrace_start_lock); } static void ftrace_startup_sysctl(void) @@ -740,15 +574,15 @@ static void ftrace_startup_sysctl(void) if (unlikely(ftrace_disabled)) return; - mutex_lock(&ftraced_lock); + mutex_lock(&ftrace_start_lock); /* Force update next time */ saved_ftrace_func = NULL; - /* ftraced_suspend is true if we want ftrace running */ - if (ftraced_suspend) + /* ftrace_start is true if we want ftrace running */ + if (ftrace_start) command |= FTRACE_ENABLE_CALLS; ftrace_run_update_code(command); - mutex_unlock(&ftraced_lock); + mutex_unlock(&ftrace_start_lock); } static void ftrace_shutdown_sysctl(void) @@ -758,112 +592,50 @@ static void ftrace_shutdown_sysctl(void) if (unlikely(ftrace_disabled)) return; - mutex_lock(&ftraced_lock); - /* ftraced_suspend is true if ftrace is running */ - if (ftraced_suspend) + mutex_lock(&ftrace_start_lock); + /* ftrace_start is true if ftrace is running */ + if (ftrace_start) command |= FTRACE_DISABLE_CALLS; ftrace_run_update_code(command); - mutex_unlock(&ftraced_lock); + mutex_unlock(&ftrace_start_lock); } static cycle_t ftrace_update_time; static unsigned long ftrace_update_cnt; unsigned long ftrace_update_tot_cnt; -static int __ftrace_update_code(void *ignore) +static int ftrace_update_code(void) { - int i, save_ftrace_enabled; + struct dyn_ftrace *p, *t; cycle_t start, stop; - struct dyn_ftrace *p; - struct hlist_node *t, *n; - struct hlist_head *head, temp_list; - - /* Don't be recording funcs now */ - ftrace_record_suspend++; - save_ftrace_enabled = ftrace_enabled; - ftrace_enabled = 0; start = ftrace_now(raw_smp_processor_id()); ftrace_update_cnt = 0; - /* No locks needed, the machine is stopped! */ - for (i = 0; i < FTRACE_HASHSIZE; i++) { - INIT_HLIST_HEAD(&temp_list); - head = &ftrace_hash[i]; - - /* all CPUS are stopped, we are safe to modify code */ - hlist_for_each_entry_safe(p, t, n, head, node) { - /* Skip over failed records which have not been - * freed. */ - if (p->flags & FTRACE_FL_FAILED) - continue; + list_for_each_entry_safe(p, t, &ftrace_new_addrs, list) { - /* Unconverted records are always at the head of the - * hash bucket. Once we encounter a converted record, - * simply skip over to the next bucket. Saves ftraced - * some processor cycles (ftrace does its bid for - * global warming :-p ). */ - if (p->flags & (FTRACE_FL_CONVERTED)) - break; + /* If something went wrong, bail without enabling anything */ + if (unlikely(ftrace_disabled)) + return -1; - /* Ignore updates to this record's mcount site. - * Reintroduce this record at the head of this - * bucket to attempt to "convert" it again if - * the kprobe on it is unregistered before the - * next run. */ - if (get_kprobe((void *)p->ip)) { - ftrace_del_hash(p); - INIT_HLIST_NODE(&p->node); - hlist_add_head(&p->node, &temp_list); - freeze_record(p); - continue; - } else { - unfreeze_record(p); - } + list_del_init(&p->list); - /* convert record (i.e, patch mcount-call with NOP) */ - if (ftrace_code_disable(p)) { - p->flags |= FTRACE_FL_CONVERTED; - ftrace_update_cnt++; - } else { - if ((system_state == SYSTEM_BOOTING) || - !core_kernel_text(p->ip)) { - ftrace_del_hash(p); - ftrace_free_rec(p); - } - } - } - - hlist_for_each_entry_safe(p, t, n, &temp_list, node) { - hlist_del(&p->node); - INIT_HLIST_NODE(&p->node); - hlist_add_head(&p->node, head); - } + /* convert record (i.e, patch mcount-call with NOP) */ + if (ftrace_code_disable(p)) { + p->flags |= FTRACE_FL_CONVERTED; + ftrace_update_cnt++; + } else + ftrace_free_rec(p); } stop = ftrace_now(raw_smp_processor_id()); ftrace_update_time = stop - start; ftrace_update_tot_cnt += ftrace_update_cnt; - ftraced_trigger = 0; - - ftrace_enabled = save_ftrace_enabled; - ftrace_record_suspend--; return 0; } -static int ftrace_update_code(void) -{ - if (unlikely(ftrace_disabled) || - !ftrace_enabled || !ftraced_trigger) - return 0; - - stop_machine(__ftrace_update_code, NULL, NULL); - - return 1; -} - static int __init ftrace_dyn_table_alloc(unsigned long num_to_init) { struct ftrace_page *pg; @@ -892,8 +664,8 @@ static int __init ftrace_dyn_table_alloc(unsigned long num_to_init) pg = ftrace_pages = ftrace_pages_start; cnt = num_to_init / ENTRIES_PER_PAGE; - pr_info("ftrace: allocating %ld hash entries in %d pages\n", - num_to_init, cnt); + pr_info("ftrace: allocating %ld entries in %d pages\n", + num_to_init, cnt + 1); for (i = 0; i < cnt; i++) { pg->next = (void *)get_zeroed_page(GFP_KERNEL); @@ -954,6 +726,9 @@ t_next(struct seq_file *m, void *v, loff_t *pos) ((iter->flags & FTRACE_ITER_FAILURES) && !(rec->flags & FTRACE_FL_FAILED)) || + ((iter->flags & FTRACE_ITER_FILTER) && + !(rec->flags & FTRACE_FL_FILTER)) || + ((iter->flags & FTRACE_ITER_NOTRACE) && !(rec->flags & FTRACE_FL_NOTRACE))) { rec = NULL; @@ -973,13 +748,11 @@ static void *t_start(struct seq_file *m, loff_t *pos) void *p = NULL; loff_t l = -1; - if (*pos != iter->pos) { - for (p = t_next(m, p, &l); p && l < *pos; p = t_next(m, p, &l)) - ; - } else { - l = *pos; - p = t_next(m, p, &l); - } + if (*pos > iter->pos) + *pos = iter->pos; + + l = *pos; + p = t_next(m, p, &l); return p; } @@ -990,15 +763,21 @@ static void t_stop(struct seq_file *m, void *p) static int t_show(struct seq_file *m, void *v) { + struct ftrace_iterator *iter = m->private; struct dyn_ftrace *rec = v; char str[KSYM_SYMBOL_LEN]; + int ret = 0; if (!rec) return 0; kallsyms_lookup(rec->ip, NULL, NULL, NULL, str); - seq_printf(m, "%s\n", str); + ret = seq_printf(m, "%s\n", str); + if (ret < 0) { + iter->pos--; + iter->idx--; + } return 0; } @@ -1024,7 +803,7 @@ ftrace_avail_open(struct inode *inode, struct file *file) return -ENOMEM; iter->pg = ftrace_pages_start; - iter->pos = -1; + iter->pos = 0; ret = seq_open(file, &show_ftrace_seq_ops); if (!ret) { @@ -1111,7 +890,7 @@ ftrace_regex_open(struct inode *inode, struct file *file, int enable) if (file->f_mode & FMODE_READ) { iter->pg = ftrace_pages_start; - iter->pos = -1; + iter->pos = 0; iter->flags = enable ? FTRACE_ITER_FILTER : FTRACE_ITER_NOTRACE; @@ -1401,10 +1180,10 @@ ftrace_regex_release(struct inode *inode, struct file *file, int enable) } mutex_lock(&ftrace_sysctl_lock); - mutex_lock(&ftraced_lock); - if (iter->filtered && ftraced_suspend && ftrace_enabled) + mutex_lock(&ftrace_start_lock); + if (ftrace_start && ftrace_enabled) ftrace_run_update_code(FTRACE_ENABLE_CALLS); - mutex_unlock(&ftraced_lock); + mutex_unlock(&ftrace_start_lock); mutex_unlock(&ftrace_sysctl_lock); kfree(iter); @@ -1424,55 +1203,6 @@ ftrace_notrace_release(struct inode *inode, struct file *file) return ftrace_regex_release(inode, file, 0); } -static ssize_t -ftraced_read(struct file *filp, char __user *ubuf, - size_t cnt, loff_t *ppos) -{ - /* don't worry about races */ - char *buf = ftraced_stop ? "disabled\n" : "enabled\n"; - int r = strlen(buf); - - return simple_read_from_buffer(ubuf, cnt, ppos, buf, r); -} - -static ssize_t -ftraced_write(struct file *filp, const char __user *ubuf, - size_t cnt, loff_t *ppos) -{ - char buf[64]; - long val; - int ret; - - if (cnt >= sizeof(buf)) - return -EINVAL; - - if (copy_from_user(&buf, ubuf, cnt)) - return -EFAULT; - - if (strncmp(buf, "enable", 6) == 0) - val = 1; - else if (strncmp(buf, "disable", 7) == 0) - val = 0; - else { - buf[cnt] = 0; - - ret = strict_strtoul(buf, 10, &val); - if (ret < 0) - return ret; - - val = !!val; - } - - if (val) - ftrace_enable_daemon(); - else - ftrace_disable_daemon(); - - filp->f_pos += cnt; - - return cnt; -} - static struct file_operations ftrace_avail_fops = { .open = ftrace_avail_open, .read = seq_read, @@ -1503,54 +1233,6 @@ static struct file_operations ftrace_notrace_fops = { .release = ftrace_notrace_release, }; -static struct file_operations ftraced_fops = { - .open = tracing_open_generic, - .read = ftraced_read, - .write = ftraced_write, -}; - -/** - * ftrace_force_update - force an update to all recording ftrace functions - */ -int ftrace_force_update(void) -{ - int ret = 0; - - if (unlikely(ftrace_disabled)) - return -ENODEV; - - mutex_lock(&ftrace_sysctl_lock); - mutex_lock(&ftraced_lock); - - /* - * If ftraced_trigger is not set, then there is nothing - * to update. - */ - if (ftraced_trigger && !ftrace_update_code()) - ret = -EBUSY; - - mutex_unlock(&ftraced_lock); - mutex_unlock(&ftrace_sysctl_lock); - - return ret; -} - -static void ftrace_force_shutdown(void) -{ - struct task_struct *task; - int command = FTRACE_DISABLE_CALLS | FTRACE_UPDATE_TRACE_FUNC; - - mutex_lock(&ftraced_lock); - task = ftraced_task; - ftraced_task = NULL; - ftraced_suspend = -1; - ftrace_run_update_code(command); - mutex_unlock(&ftraced_lock); - - if (task) - kthread_stop(task); -} - static __init int ftrace_init_debugfs(void) { struct dentry *d_tracer; @@ -1581,17 +1263,11 @@ static __init int ftrace_init_debugfs(void) pr_warning("Could not create debugfs " "'set_ftrace_notrace' entry\n"); - entry = debugfs_create_file("ftraced_enabled", 0644, d_tracer, - NULL, &ftraced_fops); - if (!entry) - pr_warning("Could not create debugfs " - "'ftraced_enabled' entry\n"); return 0; } fs_initcall(ftrace_init_debugfs); -#ifdef CONFIG_FTRACE_MCOUNT_RECORD static int ftrace_convert_nops(unsigned long *start, unsigned long *end) { @@ -1599,20 +1275,18 @@ static int ftrace_convert_nops(unsigned long *start, unsigned long addr; unsigned long flags; + mutex_lock(&ftrace_start_lock); p = start; while (p < end) { addr = ftrace_call_adjust(*p++); - /* should not be called from interrupt context */ - spin_lock(&ftrace_lock); ftrace_record_ip(addr); - spin_unlock(&ftrace_lock); - ftrace_shutdown_replenish(); } - /* p is ignored */ + /* disable interrupts to prevent kstop machine */ local_irq_save(flags); - __ftrace_update_code(p); + ftrace_update_code(); local_irq_restore(flags); + mutex_unlock(&ftrace_start_lock); return 0; } @@ -1658,130 +1332,34 @@ void __init ftrace_init(void) failed: ftrace_disabled = 1; } -#else /* CONFIG_FTRACE_MCOUNT_RECORD */ -static int ftraced(void *ignore) -{ - unsigned long usecs; - - while (!kthread_should_stop()) { - - set_current_state(TASK_INTERRUPTIBLE); - - /* check once a second */ - schedule_timeout(HZ); - if (unlikely(ftrace_disabled)) - continue; - - mutex_lock(&ftrace_sysctl_lock); - mutex_lock(&ftraced_lock); - if (!ftraced_suspend && !ftraced_stop && - ftrace_update_code()) { - usecs = nsecs_to_usecs(ftrace_update_time); - if (ftrace_update_tot_cnt > 100000) { - ftrace_update_tot_cnt = 0; - pr_info("hm, dftrace overflow: %lu change%s" - " (%lu total) in %lu usec%s\n", - ftrace_update_cnt, - ftrace_update_cnt != 1 ? "s" : "", - ftrace_update_tot_cnt, - usecs, usecs != 1 ? "s" : ""); - ftrace_disabled = 1; - WARN_ON_ONCE(1); - } - } - mutex_unlock(&ftraced_lock); - mutex_unlock(&ftrace_sysctl_lock); - - ftrace_shutdown_replenish(); - } - __set_current_state(TASK_RUNNING); - return 0; -} +#else -static int __init ftrace_dynamic_init(void) +static int __init ftrace_nodyn_init(void) { - struct task_struct *p; - unsigned long addr; - int ret; - - addr = (unsigned long)ftrace_record_ip; - - stop_machine(ftrace_dyn_arch_init, &addr, NULL); - - /* ftrace_dyn_arch_init places the return code in addr */ - if (addr) { - ret = (int)addr; - goto failed; - } - - ret = ftrace_dyn_table_alloc(NR_TO_INIT); - if (ret) - goto failed; - - p = kthread_run(ftraced, NULL, "ftraced"); - if (IS_ERR(p)) { - ret = -1; - goto failed; - } - - last_ftrace_enabled = ftrace_enabled = 1; - ftraced_task = p; - + ftrace_enabled = 1; return 0; - - failed: - ftrace_disabled = 1; - return ret; } +device_initcall(ftrace_nodyn_init); -core_initcall(ftrace_dynamic_init); -#endif /* CONFIG_FTRACE_MCOUNT_RECORD */ - -#else # define ftrace_startup() do { } while (0) # define ftrace_shutdown() do { } while (0) # define ftrace_startup_sysctl() do { } while (0) # define ftrace_shutdown_sysctl() do { } while (0) -# define ftrace_force_shutdown() do { } while (0) #endif /* CONFIG_DYNAMIC_FTRACE */ /** - * ftrace_kill_atomic - kill ftrace from critical sections + * ftrace_kill - kill ftrace * * This function should be used by panic code. It stops ftrace * but in a not so nice way. If you need to simply kill ftrace * from a non-atomic section, use ftrace_kill. */ -void ftrace_kill_atomic(void) -{ - ftrace_disabled = 1; - ftrace_enabled = 0; -#ifdef CONFIG_DYNAMIC_FTRACE - ftraced_suspend = -1; -#endif - clear_ftrace_function(); -} - -/** - * ftrace_kill - totally shutdown ftrace - * - * This is a safety measure. If something was detected that seems - * wrong, calling this function will keep ftrace from doing - * any more modifications, and updates. - * used when something went wrong. - */ void ftrace_kill(void) { - mutex_lock(&ftrace_sysctl_lock); ftrace_disabled = 1; ftrace_enabled = 0; - clear_ftrace_function(); - mutex_unlock(&ftrace_sysctl_lock); - - /* Try to totally disable ftrace */ - ftrace_force_shutdown(); } /** @@ -1870,3 +1448,4 @@ ftrace_enable_sysctl(struct ctl_table *table, int write, mutex_unlock(&ftrace_sysctl_lock); return ret; } + diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 94af1fe56bb4..668bbb5ef2bd 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -16,14 +16,49 @@ #include #include +#include "trace.h" + +/* Global flag to disable all recording to ring buffers */ +static int ring_buffers_off __read_mostly; + +/** + * tracing_on - enable all tracing buffers + * + * This function enables all tracing buffers that may have been + * disabled with tracing_off. + */ +void tracing_on(void) +{ + ring_buffers_off = 0; +} + +/** + * tracing_off - turn off all tracing buffers + * + * This function stops all tracing buffers from recording data. + * It does not disable any overhead the tracers themselves may + * be causing. This function simply causes all recording to + * the ring buffers to fail. + */ +void tracing_off(void) +{ + ring_buffers_off = 1; +} + /* Up this if you want to test the TIME_EXTENTS and normalization */ #define DEBUG_SHIFT 0 /* FIXME!!! */ u64 ring_buffer_time_stamp(int cpu) { + u64 time; + + preempt_disable_notrace(); /* shift to debug/test normalization and TIME_EXTENTS */ - return sched_clock() << DEBUG_SHIFT; + time = sched_clock() << DEBUG_SHIFT; + preempt_enable_notrace(); + + return time; } void ring_buffer_normalize_time_stamp(int cpu, u64 *ts) @@ -130,7 +165,7 @@ struct buffer_page { static inline void free_buffer_page(struct buffer_page *bpage) { if (bpage->page) - __free_page(bpage->page); + free_page((unsigned long)bpage->page); kfree(bpage); } @@ -503,6 +538,12 @@ int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size) LIST_HEAD(pages); int i, cpu; + /* + * Always succeed at resizing a non-existent buffer: + */ + if (!buffer) + return size; + size = DIV_ROUND_UP(size, BUF_PAGE_SIZE); size *= BUF_PAGE_SIZE; buffer_size = buffer->pages * BUF_PAGE_SIZE; @@ -576,6 +617,7 @@ int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size) list_del_init(&page->list); free_buffer_page(page); } + mutex_unlock(&buffer->mutex); return -ENOMEM; } @@ -966,7 +1008,9 @@ rb_add_time_stamp(struct ring_buffer_per_cpu *cpu_buffer, if (unlikely(*delta > (1ULL << 59) && !once++)) { printk(KERN_WARNING "Delta way too big! %llu" " ts=%llu write stamp = %llu\n", - *delta, *ts, cpu_buffer->write_stamp); + (unsigned long long)*delta, + (unsigned long long)*ts, + (unsigned long long)cpu_buffer->write_stamp); WARN_ON(1); } @@ -1020,8 +1064,23 @@ rb_reserve_next_event(struct ring_buffer_per_cpu *cpu_buffer, struct ring_buffer_event *event; u64 ts, delta; int commit = 0; + int nr_loops = 0; again: + /* + * We allow for interrupts to reenter here and do a trace. + * If one does, it will cause this original code to loop + * back here. Even with heavy interrupts happening, this + * should only happen a few times in a row. If this happens + * 1000 times in a row, there must be either an interrupt + * storm or we have something buggy. + * Bail! + */ + if (unlikely(++nr_loops > 1000)) { + RB_WARN_ON(cpu_buffer, 1); + return NULL; + } + ts = ring_buffer_time_stamp(cpu_buffer->cpu); /* @@ -1043,7 +1102,7 @@ rb_reserve_next_event(struct ring_buffer_per_cpu *cpu_buffer, /* Did the write stamp get updated already? */ if (unlikely(ts < cpu_buffer->write_stamp)) - goto again; + delta = 0; if (test_time_stamp(delta)) { @@ -1116,6 +1175,9 @@ ring_buffer_lock_reserve(struct ring_buffer *buffer, struct ring_buffer_event *event; int cpu, resched; + if (ring_buffers_off) + return NULL; + if (atomic_read(&buffer->record_disabled)) return NULL; @@ -1153,7 +1215,7 @@ ring_buffer_lock_reserve(struct ring_buffer *buffer, out: if (resched) - preempt_enable_notrace(); + preempt_enable_no_resched_notrace(); else preempt_enable_notrace(); return NULL; @@ -1232,6 +1294,9 @@ int ring_buffer_write(struct ring_buffer *buffer, int ret = -EBUSY; int cpu, resched; + if (ring_buffers_off) + return -EBUSY; + if (atomic_read(&buffer->record_disabled)) return -EBUSY; @@ -1530,10 +1595,23 @@ rb_get_reader_page(struct ring_buffer_per_cpu *cpu_buffer) { struct buffer_page *reader = NULL; unsigned long flags; + int nr_loops = 0; spin_lock_irqsave(&cpu_buffer->lock, flags); again: + /* + * This should normally only loop twice. But because the + * start of the reader inserts an empty page, it causes + * a case where we will loop three times. There should be no + * reason to loop four times (that I know of). + */ + if (unlikely(++nr_loops > 3)) { + RB_WARN_ON(cpu_buffer, 1); + reader = NULL; + goto out; + } + reader = cpu_buffer->reader_page; /* If there's more to read, return this page */ @@ -1663,6 +1741,7 @@ ring_buffer_peek(struct ring_buffer *buffer, int cpu, u64 *ts) struct ring_buffer_per_cpu *cpu_buffer; struct ring_buffer_event *event; struct buffer_page *reader; + int nr_loops = 0; if (!cpu_isset(cpu, buffer->cpumask)) return NULL; @@ -1670,6 +1749,19 @@ ring_buffer_peek(struct ring_buffer *buffer, int cpu, u64 *ts) cpu_buffer = buffer->buffers[cpu]; again: + /* + * We repeat when a timestamp is encountered. It is possible + * to get multiple timestamps from an interrupt entering just + * as one timestamp is about to be written. The max times + * that this can happen is the number of nested interrupts we + * can have. Nesting 10 deep of interrupts is clearly + * an anomaly. + */ + if (unlikely(++nr_loops > 10)) { + RB_WARN_ON(cpu_buffer, 1); + return NULL; + } + reader = rb_get_reader_page(cpu_buffer); if (!reader) return NULL; @@ -1720,6 +1812,7 @@ ring_buffer_iter_peek(struct ring_buffer_iter *iter, u64 *ts) struct ring_buffer *buffer; struct ring_buffer_per_cpu *cpu_buffer; struct ring_buffer_event *event; + int nr_loops = 0; if (ring_buffer_iter_empty(iter)) return NULL; @@ -1728,6 +1821,19 @@ ring_buffer_iter_peek(struct ring_buffer_iter *iter, u64 *ts) buffer = cpu_buffer->buffer; again: + /* + * We repeat when a timestamp is encountered. It is possible + * to get multiple timestamps from an interrupt entering just + * as one timestamp is about to be written. The max times + * that this can happen is the number of nested interrupts we + * can have. Nesting 10 deep of interrupts is clearly + * an anomaly. + */ + if (unlikely(++nr_loops > 10)) { + RB_WARN_ON(cpu_buffer, 1); + return NULL; + } + if (rb_per_cpu_empty(cpu_buffer)) return NULL; @@ -2012,3 +2118,69 @@ int ring_buffer_swap_cpu(struct ring_buffer *buffer_a, return 0; } +static ssize_t +rb_simple_read(struct file *filp, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + int *p = filp->private_data; + char buf[64]; + int r; + + /* !ring_buffers_off == tracing_on */ + r = sprintf(buf, "%d\n", !*p); + + return simple_read_from_buffer(ubuf, cnt, ppos, buf, r); +} + +static ssize_t +rb_simple_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + int *p = filp->private_data; + char buf[64]; + long val; + int ret; + + if (cnt >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(&buf, ubuf, cnt)) + return -EFAULT; + + buf[cnt] = 0; + + ret = strict_strtoul(buf, 10, &val); + if (ret < 0) + return ret; + + /* !ring_buffers_off == tracing_on */ + *p = !val; + + (*ppos)++; + + return cnt; +} + +static struct file_operations rb_simple_fops = { + .open = tracing_open_generic, + .read = rb_simple_read, + .write = rb_simple_write, +}; + + +static __init int rb_init_debugfs(void) +{ + struct dentry *d_tracer; + struct dentry *entry; + + d_tracer = tracing_init_dentry(); + + entry = debugfs_create_file("tracing_on", 0644, d_tracer, + &ring_buffers_off, &rb_simple_fops); + if (!entry) + pr_warning("Could not create debugfs 'tracing_on' entry\n"); + + return 0; +} + +fs_initcall(rb_init_debugfs); diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index d345d649d073..d86e3252f300 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -34,6 +34,7 @@ #include #include +#include #include "trace.h" @@ -655,7 +656,11 @@ tracing_generic_entry_update(struct trace_entry *entry, unsigned long flags, entry->preempt_count = pc & 0xff; entry->pid = (tsk) ? tsk->pid : 0; entry->flags = +#ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT (irqs_disabled_flags(flags) ? TRACE_FLAG_IRQS_OFF : 0) | +#else + TRACE_FLAG_IRQS_NOSUPPORT | +#endif ((pc & HARDIRQ_MASK) ? TRACE_FLAG_HARDIRQ : 0) | ((pc & SOFTIRQ_MASK) ? TRACE_FLAG_SOFTIRQ : 0) | (need_resched() ? TRACE_FLAG_NEED_RESCHED : 0); @@ -700,6 +705,7 @@ static void ftrace_trace_stack(struct trace_array *tr, unsigned long flags, int skip, int pc) { +#ifdef CONFIG_STACKTRACE struct ring_buffer_event *event; struct stack_entry *entry; struct stack_trace trace; @@ -725,6 +731,7 @@ static void ftrace_trace_stack(struct trace_array *tr, save_stack_trace(&trace); ring_buffer_unlock_commit(tr->buffer, event, irq_flags); +#endif } void __trace_stack(struct trace_array *tr, @@ -851,7 +858,7 @@ ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3) preempt_enable_notrace(); } -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER static void function_trace_call(unsigned long ip, unsigned long parent_ip) { @@ -865,9 +872,6 @@ function_trace_call(unsigned long ip, unsigned long parent_ip) if (unlikely(!ftrace_function_enabled)) return; - if (skip_trace(ip)) - return; - pc = preempt_count(); resched = need_resched(); preempt_disable_notrace(); @@ -1084,17 +1088,20 @@ static void s_stop(struct seq_file *m, void *p) mutex_unlock(&trace_types_lock); } -#define KRETPROBE_MSG "[unknown/kretprobe'd]" - #ifdef CONFIG_KRETPROBES -static inline int kretprobed(unsigned long addr) +static inline const char *kretprobed(const char *name) { - return addr == (unsigned long)kretprobe_trampoline; + static const char tramp_name[] = "kretprobe_trampoline"; + int size = sizeof(tramp_name); + + if (strncmp(tramp_name, name, size) == 0) + return "[unknown/kretprobe'd]"; + return name; } #else -static inline int kretprobed(unsigned long addr) +static inline const char *kretprobed(const char *name) { - return 0; + return name; } #endif /* CONFIG_KRETPROBES */ @@ -1103,10 +1110,13 @@ seq_print_sym_short(struct trace_seq *s, const char *fmt, unsigned long address) { #ifdef CONFIG_KALLSYMS char str[KSYM_SYMBOL_LEN]; + const char *name; kallsyms_lookup(address, NULL, NULL, NULL, str); - return trace_seq_printf(s, fmt, str); + name = kretprobed(str); + + return trace_seq_printf(s, fmt, name); #endif return 1; } @@ -1117,9 +1127,12 @@ seq_print_sym_offset(struct trace_seq *s, const char *fmt, { #ifdef CONFIG_KALLSYMS char str[KSYM_SYMBOL_LEN]; + const char *name; sprint_symbol(str, address); - return trace_seq_printf(s, fmt, str); + name = kretprobed(str); + + return trace_seq_printf(s, fmt, name); #endif return 1; } @@ -1246,7 +1259,8 @@ lat_print_generic(struct trace_seq *s, struct trace_entry *entry, int cpu) trace_seq_printf(s, "%8.8s-%-5d ", comm, entry->pid); trace_seq_printf(s, "%3d", cpu); trace_seq_printf(s, "%c%c", - (entry->flags & TRACE_FLAG_IRQS_OFF) ? 'd' : '.', + (entry->flags & TRACE_FLAG_IRQS_OFF) ? 'd' : + (entry->flags & TRACE_FLAG_IRQS_NOSUPPORT) ? 'X' : '.', ((entry->flags & TRACE_FLAG_NEED_RESCHED) ? 'N' : '.')); hardirq = entry->flags & TRACE_FLAG_HARDIRQ; @@ -1372,10 +1386,7 @@ print_lat_fmt(struct trace_iterator *iter, unsigned int trace_idx, int cpu) seq_print_ip_sym(s, field->ip, sym_flags); trace_seq_puts(s, " ("); - if (kretprobed(field->parent_ip)) - trace_seq_puts(s, KRETPROBE_MSG); - else - seq_print_ip_sym(s, field->parent_ip, sym_flags); + seq_print_ip_sym(s, field->parent_ip, sym_flags); trace_seq_puts(s, ")\n"); break; } @@ -1491,12 +1502,9 @@ static enum print_line_t print_trace_fmt(struct trace_iterator *iter) ret = trace_seq_printf(s, " <-"); if (!ret) return TRACE_TYPE_PARTIAL_LINE; - if (kretprobed(field->parent_ip)) - ret = trace_seq_puts(s, KRETPROBE_MSG); - else - ret = seq_print_ip_sym(s, - field->parent_ip, - sym_flags); + ret = seq_print_ip_sym(s, + field->parent_ip, + sym_flags); if (!ret) return TRACE_TYPE_PARTIAL_LINE; } @@ -1747,7 +1755,7 @@ static enum print_line_t print_bin_fmt(struct trace_iterator *iter) return TRACE_TYPE_HANDLED; SEQ_PUT_FIELD_RET(s, entry->pid); - SEQ_PUT_FIELD_RET(s, iter->cpu); + SEQ_PUT_FIELD_RET(s, entry->cpu); SEQ_PUT_FIELD_RET(s, iter->ts); switch (entry->type) { @@ -1928,6 +1936,7 @@ __tracing_open(struct inode *inode, struct file *file, int *ret) ring_buffer_read_finish(iter->buffer_iter[cpu]); } mutex_unlock(&trace_types_lock); + kfree(iter); return ERR_PTR(-ENOMEM); } @@ -2379,9 +2388,10 @@ tracing_set_trace_write(struct file *filp, const char __user *ubuf, int i; size_t ret; + ret = cnt; + if (cnt > max_tracer_type_len) cnt = max_tracer_type_len; - ret = cnt; if (copy_from_user(&buf, ubuf, cnt)) return -EFAULT; @@ -2414,8 +2424,8 @@ tracing_set_trace_write(struct file *filp, const char __user *ubuf, out: mutex_unlock(&trace_types_lock); - if (ret == cnt) - filp->f_pos += cnt; + if (ret > 0) + filp->f_pos += ret; return ret; } @@ -2667,7 +2677,7 @@ tracing_entries_write(struct file *filp, const char __user *ubuf, { unsigned long val; char buf[64]; - int ret; + int ret, cpu; struct trace_array *tr = filp->private_data; if (cnt >= sizeof(buf)) @@ -2695,6 +2705,14 @@ tracing_entries_write(struct file *filp, const char __user *ubuf, goto out; } + /* disable all cpu buffers */ + for_each_tracing_cpu(cpu) { + if (global_trace.data[cpu]) + atomic_inc(&global_trace.data[cpu]->disabled); + if (max_tr.data[cpu]) + atomic_inc(&max_tr.data[cpu]->disabled); + } + if (val != global_trace.entries) { ret = ring_buffer_resize(global_trace.buffer, val); if (ret < 0) { @@ -2726,6 +2744,13 @@ tracing_entries_write(struct file *filp, const char __user *ubuf, if (tracing_disabled) cnt = -ENOMEM; out: + for_each_tracing_cpu(cpu) { + if (global_trace.data[cpu]) + atomic_dec(&global_trace.data[cpu]->disabled); + if (max_tr.data[cpu]) + atomic_dec(&max_tr.data[cpu]->disabled); + } + max_tr.entries = global_trace.entries; mutex_unlock(&trace_types_lock); @@ -3097,7 +3122,7 @@ void ftrace_dump(void) dump_ran = 1; /* No turning back! */ - ftrace_kill_atomic(); + ftrace_kill(); for_each_tracing_cpu(cpu) { atomic_inc(&global_trace.data[cpu]->disabled); diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h index f1f99572cde7..8465ad052707 100644 --- a/kernel/trace/trace.h +++ b/kernel/trace/trace.h @@ -120,18 +120,20 @@ struct trace_boot { /* * trace_flag_type is an enumeration that holds different * states when a trace occurs. These are: - * IRQS_OFF - interrupts were disabled - * NEED_RESCED - reschedule is requested - * HARDIRQ - inside an interrupt handler - * SOFTIRQ - inside a softirq handler - * CONT - multiple entries hold the trace item + * IRQS_OFF - interrupts were disabled + * IRQS_NOSUPPORT - arch does not support irqs_disabled_flags + * NEED_RESCED - reschedule is requested + * HARDIRQ - inside an interrupt handler + * SOFTIRQ - inside a softirq handler + * CONT - multiple entries hold the trace item */ enum trace_flag_type { TRACE_FLAG_IRQS_OFF = 0x01, - TRACE_FLAG_NEED_RESCHED = 0x02, - TRACE_FLAG_HARDIRQ = 0x04, - TRACE_FLAG_SOFTIRQ = 0x08, - TRACE_FLAG_CONT = 0x10, + TRACE_FLAG_IRQS_NOSUPPORT = 0x02, + TRACE_FLAG_NEED_RESCHED = 0x04, + TRACE_FLAG_HARDIRQ = 0x08, + TRACE_FLAG_SOFTIRQ = 0x10, + TRACE_FLAG_CONT = 0x20, }; #define TRACE_BUF_SIZE 1024 @@ -335,7 +337,7 @@ void update_max_tr_single(struct trace_array *tr, extern cycle_t ftrace_now(int cpu); -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER void tracing_start_function_trace(void); void tracing_stop_function_trace(void); #else diff --git a/kernel/trace/trace_functions.c b/kernel/trace/trace_functions.c index e90eb0c2c56c..0f85a64003d3 100644 --- a/kernel/trace/trace_functions.c +++ b/kernel/trace/trace_functions.c @@ -64,7 +64,7 @@ static void function_trace_ctrl_update(struct trace_array *tr) static struct tracer function_trace __read_mostly = { - .name = "ftrace", + .name = "function", .init = function_trace_init, .reset = function_trace_reset, .ctrl_update = function_trace_ctrl_update, diff --git a/kernel/trace/trace_irqsoff.c b/kernel/trace/trace_irqsoff.c index a7db7f040ae0..9c74071c10e0 100644 --- a/kernel/trace/trace_irqsoff.c +++ b/kernel/trace/trace_irqsoff.c @@ -63,7 +63,7 @@ irq_trace(void) */ static __cacheline_aligned_in_smp unsigned long max_sequence; -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER /* * irqsoff uses its own tracer function to keep the overhead down: */ @@ -104,7 +104,7 @@ static struct ftrace_ops trace_ops __read_mostly = { .func = irqsoff_tracer_call, }; -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ /* * Should this new latency be reported/recorded? diff --git a/kernel/trace/trace_mmiotrace.c b/kernel/trace/trace_mmiotrace.c index f28484618ff0..e62cbf78eab6 100644 --- a/kernel/trace/trace_mmiotrace.c +++ b/kernel/trace/trace_mmiotrace.c @@ -18,12 +18,14 @@ struct header_iter { static struct trace_array *mmio_trace_array; static bool overrun_detected; +static unsigned long prev_overruns; static void mmio_reset_data(struct trace_array *tr) { int cpu; overrun_detected = false; + prev_overruns = 0; tr->time_start = ftrace_now(tr->cpu); for_each_online_cpu(cpu) @@ -128,16 +130,12 @@ static void mmio_close(struct trace_iterator *iter) static unsigned long count_overruns(struct trace_iterator *iter) { - int cpu; unsigned long cnt = 0; -/* FIXME: */ -#if 0 - for_each_online_cpu(cpu) { - cnt += iter->overrun[cpu]; - iter->overrun[cpu] = 0; - } -#endif - (void)cpu; + unsigned long over = ring_buffer_overruns(iter->tr->buffer); + + if (over > prev_overruns) + cnt = over - prev_overruns; + prev_overruns = over; return cnt; } diff --git a/kernel/trace/trace_sched_wakeup.c b/kernel/trace/trace_sched_wakeup.c index fe4a252c2363..3ae93f16b565 100644 --- a/kernel/trace/trace_sched_wakeup.c +++ b/kernel/trace/trace_sched_wakeup.c @@ -31,7 +31,7 @@ static raw_spinlock_t wakeup_lock = static void __wakeup_reset(struct trace_array *tr); -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER /* * irqsoff uses its own tracer function to keep the overhead down: */ @@ -96,7 +96,7 @@ static struct ftrace_ops trace_ops __read_mostly = { .func = wakeup_tracer_call, }; -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ /* * Should this new latency be reported/recorded? diff --git a/kernel/trace/trace_selftest.c b/kernel/trace/trace_selftest.c index 09cf230d7eca..90bc752a7580 100644 --- a/kernel/trace/trace_selftest.c +++ b/kernel/trace/trace_selftest.c @@ -70,7 +70,7 @@ static int trace_test_buffer(struct trace_array *tr, unsigned long *count) return ret; } -#ifdef CONFIG_FTRACE +#ifdef CONFIG_FUNCTION_TRACER #ifdef CONFIG_DYNAMIC_FTRACE @@ -99,13 +99,6 @@ int trace_selftest_startup_dynamic_tracing(struct tracer *trace, /* passed in by parameter to fool gcc from optimizing */ func(); - /* update the records */ - ret = ftrace_force_update(); - if (ret) { - printk(KERN_CONT ".. ftraced failed .. "); - return ret; - } - /* * Some archs *cough*PowerPC*cough* add charachters to the * start of the function names. We simply put a '*' to @@ -183,13 +176,6 @@ trace_selftest_startup_function(struct tracer *trace, struct trace_array *tr) /* make sure msleep has been recorded */ msleep(1); - /* force the recorded functions to be traced */ - ret = ftrace_force_update(); - if (ret) { - printk(KERN_CONT ".. ftraced failed .. "); - return ret; - } - /* start the tracing */ ftrace_enabled = 1; tracer_enabled = 1; @@ -226,7 +212,7 @@ trace_selftest_startup_function(struct tracer *trace, struct trace_array *tr) return ret; } -#endif /* CONFIG_FTRACE */ +#endif /* CONFIG_FUNCTION_TRACER */ #ifdef CONFIG_IRQSOFF_TRACER int diff --git a/kernel/trace/trace_stack.c b/kernel/trace/trace_stack.c index 74c5d9a3afae..3bdb44bde4b7 100644 --- a/kernel/trace/trace_stack.c +++ b/kernel/trace/trace_stack.c @@ -44,6 +44,10 @@ static inline void check_stack(void) if (this_size <= max_stack_size) return; + /* we do not handle interrupt stacks yet */ + if (!object_is_on_stack(&this_size)) + return; + raw_local_irq_save(flags); __raw_spin_lock(&max_stack_lock); @@ -180,11 +184,16 @@ static struct file_operations stack_max_size_fops = { static void * t_next(struct seq_file *m, void *v, loff_t *pos) { - long i = (long)m->private; + long i; (*pos)++; - i++; + if (v == SEQ_START_TOKEN) + i = 0; + else { + i = *(long *)v; + i++; + } if (i >= max_stack_trace.nr_entries || stack_dump_trace[i] == ULONG_MAX) @@ -197,12 +206,15 @@ t_next(struct seq_file *m, void *v, loff_t *pos) static void *t_start(struct seq_file *m, loff_t *pos) { - void *t = &m->private; + void *t = SEQ_START_TOKEN; loff_t l = 0; local_irq_disable(); __raw_spin_lock(&max_stack_lock); + if (*pos == 0) + return SEQ_START_TOKEN; + for (; t && l < *pos; t = t_next(m, t, &l)) ; @@ -231,10 +243,10 @@ static int trace_lookup_stack(struct seq_file *m, long i) static int t_show(struct seq_file *m, void *v) { - long i = *(long *)v; + long i; int size; - if (i < 0) { + if (v == SEQ_START_TOKEN) { seq_printf(m, " Depth Size Location" " (%d entries)\n" " ----- ---- --------\n", @@ -242,6 +254,8 @@ static int t_show(struct seq_file *m, void *v) return 0; } + i = *(long *)v; + if (i >= max_stack_trace.nr_entries || stack_dump_trace[i] == ULONG_MAX) return 0; @@ -271,10 +285,6 @@ static int stack_trace_open(struct inode *inode, struct file *file) int ret; ret = seq_open(file, &stack_trace_seq_ops); - if (!ret) { - struct seq_file *m = file->private_data; - m->private = (void *)-1; - } return ret; } diff --git a/kernel/tracepoint.c b/kernel/tracepoint.c index f2b7c28a4708..af8c85664882 100644 --- a/kernel/tracepoint.c +++ b/kernel/tracepoint.c @@ -131,6 +131,9 @@ tracepoint_entry_remove_probe(struct tracepoint_entry *entry, void *probe) old = entry->funcs; + if (!old) + return NULL; + debug_print_probes(entry); /* (N -> M), (N > 1, M >= 0) probes */ for (nr_probes = 0; old[nr_probes]; nr_probes++) { @@ -388,6 +391,11 @@ int tracepoint_probe_unregister(const char *name, void *probe) if (entry->rcu_pending) rcu_barrier_sched(); old = tracepoint_entry_remove_probe(entry, probe); + if (!old) { + printk(KERN_WARNING "Warning: Trying to unregister a probe" + "that doesn't exist\n"); + goto end; + } mutex_unlock(&tracepoints_mutex); tracepoint_update_probes(); /* may update entry */ mutex_lock(&tracepoints_mutex); diff --git a/kernel/workqueue.c b/kernel/workqueue.c index f928f2a87b9b..d4dc69ddebd7 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -970,6 +970,51 @@ undo: return ret; } +#ifdef CONFIG_SMP +struct work_for_cpu { + struct work_struct work; + long (*fn)(void *); + void *arg; + long ret; +}; + +static void do_work_for_cpu(struct work_struct *w) +{ + struct work_for_cpu *wfc = container_of(w, struct work_for_cpu, work); + + wfc->ret = wfc->fn(wfc->arg); +} + +/** + * work_on_cpu - run a function in user context on a particular cpu + * @cpu: the cpu to run on + * @fn: the function to run + * @arg: the function arg + * + * This will return -EINVAL in the cpu is not online, or the return value + * of @fn otherwise. + */ +long work_on_cpu(unsigned int cpu, long (*fn)(void *), void *arg) +{ + struct work_for_cpu wfc; + + INIT_WORK(&wfc.work, do_work_for_cpu); + wfc.fn = fn; + wfc.arg = arg; + get_online_cpus(); + if (unlikely(!cpu_online(cpu))) + wfc.ret = -EINVAL; + else { + schedule_work_on(cpu, &wfc.work); + flush_work(&wfc.work); + } + put_online_cpus(); + + return wfc.ret; +} +EXPORT_SYMBOL_GPL(work_on_cpu); +#endif /* CONFIG_SMP */ + void __init init_workqueues(void) { cpu_populated_map = cpu_online_map; diff --git a/lib/Makefile b/lib/Makefile index 16feaab057b2..7cb65d85aeb0 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -2,7 +2,7 @@ # Makefile for some libs needed in the kernel. # -ifdef CONFIG_FTRACE +ifdef CONFIG_FUNCTION_TRACER ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg,,$(ORIG_CFLAGS)) endif diff --git a/lib/bug.c b/lib/bug.c index bfeafd60ee9f..300e41afbf97 100644 --- a/lib/bug.c +++ b/lib/bug.c @@ -5,6 +5,8 @@ CONFIG_BUG - emit BUG traps. Nothing happens without this. CONFIG_GENERIC_BUG - enable this code. + CONFIG_GENERIC_BUG_RELATIVE_POINTERS - use 32-bit pointers relative to + the containing struct bug_entry for bug_addr and file. CONFIG_DEBUG_BUGVERBOSE - emit full file+line information for each BUG CONFIG_BUG and CONFIG_DEBUG_BUGVERBOSE are potentially user-settable @@ -43,6 +45,15 @@ extern const struct bug_entry __start___bug_table[], __stop___bug_table[]; +static inline unsigned long bug_addr(const struct bug_entry *bug) +{ +#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS + return bug->bug_addr; +#else + return (unsigned long)bug + bug->bug_addr_disp; +#endif +} + #ifdef CONFIG_MODULES static LIST_HEAD(module_bug_list); @@ -55,7 +66,7 @@ static const struct bug_entry *module_find_bug(unsigned long bugaddr) unsigned i; for (i = 0; i < mod->num_bugs; ++i, ++bug) - if (bugaddr == bug->bug_addr) + if (bugaddr == bug_addr(bug)) return bug; } return NULL; @@ -108,7 +119,7 @@ const struct bug_entry *find_bug(unsigned long bugaddr) const struct bug_entry *bug; for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) - if (bugaddr == bug->bug_addr) + if (bugaddr == bug_addr(bug)) return bug; return module_find_bug(bugaddr); @@ -133,7 +144,11 @@ enum bug_trap_type report_bug(unsigned long bugaddr, struct pt_regs *regs) if (bug) { #ifdef CONFIG_DEBUG_BUGVERBOSE +#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS file = bug->file; +#else + file = (const char *)bug + bug->file_disp; +#endif line = bug->line; #endif warning = (bug->flags & BUGFLAG_WARNING) != 0; diff --git a/lib/cpumask.c b/lib/cpumask.c index 5f97dc25ef9c..8d03f22c6ced 100644 --- a/lib/cpumask.c +++ b/lib/cpumask.c @@ -2,6 +2,7 @@ #include #include #include +#include int __first_cpu(const cpumask_t *srcp) { @@ -35,3 +36,81 @@ int __any_online_cpu(const cpumask_t *mask) return cpu; } EXPORT_SYMBOL(__any_online_cpu); + +/** + * cpumask_next_and - get the next cpu in *src1p & *src2p + * @n: the cpu prior to the place to search (ie. return will be > @n) + * @src1p: the first cpumask pointer + * @src2p: the second cpumask pointer + * + * Returns >= nr_cpu_ids if no further cpus set in both. + */ +int cpumask_next_and(int n, const struct cpumask *src1p, + const struct cpumask *src2p) +{ + while ((n = cpumask_next(n, src1p)) < nr_cpu_ids) + if (cpumask_test_cpu(n, src2p)) + break; + return n; +} +EXPORT_SYMBOL(cpumask_next_and); + +/** + * cpumask_any_but - return a "random" in a cpumask, but not this one. + * @mask: the cpumask to search + * @cpu: the cpu to ignore. + * + * Often used to find any cpu but smp_processor_id() in a mask. + * Returns >= nr_cpu_ids if no cpus set. + */ +int cpumask_any_but(const struct cpumask *mask, unsigned int cpu) +{ + unsigned int i; + + cpumask_check(cpu); + for_each_cpu(i, mask) + if (i != cpu) + break; + return i; +} + +/* These are not inline because of header tangles. */ +#ifdef CONFIG_CPUMASK_OFFSTACK +bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) +{ + if (likely(slab_is_available())) + *mask = kmalloc(cpumask_size(), flags); + else { +#ifdef CONFIG_DEBUG_PER_CPU_MAPS + printk(KERN_ERR + "=> alloc_cpumask_var: kmalloc not available!\n"); + dump_stack(); +#endif + *mask = NULL; + } +#ifdef CONFIG_DEBUG_PER_CPU_MAPS + if (!*mask) { + printk(KERN_ERR "=> alloc_cpumask_var: failed!\n"); + dump_stack(); + } +#endif + return *mask != NULL; +} +EXPORT_SYMBOL(alloc_cpumask_var); + +void __init alloc_bootmem_cpumask_var(cpumask_var_t *mask) +{ + *mask = alloc_bootmem(cpumask_size()); +} + +void free_cpumask_var(cpumask_var_t mask) +{ + kfree(mask); +} +EXPORT_SYMBOL(free_cpumask_var); + +void __init free_bootmem_cpumask_var(cpumask_var_t mask) +{ + free_bootmem((unsigned long)mask, cpumask_size()); +} +#endif diff --git a/lib/dynamic_printk.c b/lib/dynamic_printk.c index d640f87bdc9e..8e30295e8566 100644 --- a/lib/dynamic_printk.c +++ b/lib/dynamic_printk.c @@ -135,7 +135,7 @@ int unregister_dynamic_debug_module(char *mod_name) nr_entries--; out: up(&debug_list_mutex); - return 0; + return ret; } EXPORT_SYMBOL_GPL(unregister_dynamic_debug_module); @@ -289,7 +289,7 @@ static ssize_t pr_debug_write(struct file *file, const char __user *buf, dynamic_enabled = DYNAMIC_ENABLED_SOME; err = 0; printk(KERN_DEBUG - "debugging enabled for module %s", + "debugging enabled for module %s\n", elem->name); } else if (!value && (elem->enable == 1)) { elem->enable = 0; @@ -309,7 +309,7 @@ static ssize_t pr_debug_write(struct file *file, const char __user *buf, err = 0; printk(KERN_DEBUG "debugging disabled for module " - "%s", elem->name); + "%s\n", elem->name); } } } @@ -402,6 +402,8 @@ static int __init dynamic_printk_init(void) iter->logical_modname, iter->flag_names, iter->hash, iter->hash2); } + if (dynamic_enabled == DYNAMIC_ENABLED_ALL) + set_all(true); return 0; } module_init(dynamic_printk_init); @@ -411,7 +413,7 @@ static int __init dynamic_printk_setup(char *str) { if (str) return -ENOENT; - set_all(true); + dynamic_enabled = DYNAMIC_ENABLED_ALL; return 0; } /* Use early_param(), so we can get debug output as early as possible */ diff --git a/lib/idr.c b/lib/idr.c index e728c7fccc4d..1c4f9281f412 100644 --- a/lib/idr.c +++ b/lib/idr.c @@ -185,6 +185,7 @@ static int sub_alloc(struct idr *idp, int *starting_id, struct idr_layer **pa) new = get_from_free_list(idp); if (!new) return -1; + new->layer = l-1; rcu_assign_pointer(p->ary[m], new); p->count++; } @@ -210,6 +211,7 @@ build_up: if (unlikely(!p)) { if (!(p = get_from_free_list(idp))) return -1; + p->layer = 0; layers = 1; } /* @@ -218,8 +220,14 @@ build_up: */ while ((layers < (MAX_LEVEL - 1)) && (id >= (1 << (layers*IDR_BITS)))) { layers++; - if (!p->count) + if (!p->count) { + /* special case: if the tree is currently empty, + * then we grow the tree by moving the top node + * upwards. + */ + p->layer++; continue; + } if (!(new = get_from_free_list(idp))) { /* * The allocation failed. If we built part of @@ -237,6 +245,7 @@ build_up: } new->ary[0] = p; new->count = 1; + new->layer = layers-1; if (p->bitmap == IDR_FULL) __set_bit(0, &new->bitmap); p = new; @@ -493,17 +502,21 @@ void *idr_find(struct idr *idp, int id) int n; struct idr_layer *p; - n = idp->layers * IDR_BITS; p = rcu_dereference(idp->top); + if (!p) + return NULL; + n = (p->layer+1) * IDR_BITS; /* Mask off upper bits we don't use for the search. */ id &= MAX_ID_MASK; if (id >= (1 << n)) return NULL; + BUG_ON(n == 0); while (n > 0 && p) { n -= IDR_BITS; + BUG_ON(n != p->layer*IDR_BITS); p = rcu_dereference(p->ary[(id >> n) & IDR_MASK]); } return((void *)p); @@ -582,8 +595,11 @@ void *idr_replace(struct idr *idp, void *ptr, int id) int n; struct idr_layer *p, *old_p; - n = idp->layers * IDR_BITS; p = idp->top; + if (!p) + return ERR_PTR(-EINVAL); + + n = (p->layer+1) * IDR_BITS; id &= MAX_ID_MASK; diff --git a/lib/percpu_counter.c b/lib/percpu_counter.c index a8663890a88c..b255b939bc1b 100644 --- a/lib/percpu_counter.c +++ b/lib/percpu_counter.c @@ -62,10 +62,7 @@ s64 __percpu_counter_sum(struct percpu_counter *fbc) for_each_online_cpu(cpu) { s32 *pcount = per_cpu_ptr(fbc->counters, cpu); ret += *pcount; - *pcount = 0; } - fbc->count = ret; - spin_unlock(&fbc->lock); return ret; } @@ -104,13 +101,13 @@ void percpu_counter_destroy(struct percpu_counter *fbc) if (!fbc->counters) return; - free_percpu(fbc->counters); - fbc->counters = NULL; #ifdef CONFIG_HOTPLUG_CPU mutex_lock(&percpu_counters_lock); list_del(&fbc->list); mutex_unlock(&percpu_counters_lock); #endif + free_percpu(fbc->counters); + fbc->counters = NULL; } EXPORT_SYMBOL(percpu_counter_destroy); diff --git a/lib/scatterlist.c b/lib/scatterlist.c index 8d2688ff1352..b7b449dafbe5 100644 --- a/lib/scatterlist.c +++ b/lib/scatterlist.c @@ -395,7 +395,7 @@ void sg_miter_stop(struct sg_mapping_iter *miter) WARN_ON(!irqs_disabled()); kunmap_atomic(miter->addr, KM_BIO_SRC_IRQ); } else - kunmap(miter->addr); + kunmap(miter->page); miter->page = NULL; miter->addr = NULL; diff --git a/lib/swiotlb.c b/lib/swiotlb.c index f8eebd489149..5f6c629a924d 100644 --- a/lib/swiotlb.c +++ b/lib/swiotlb.c @@ -467,9 +467,13 @@ swiotlb_alloc_coherent(struct device *hwdev, size_t size, dma_addr_t dev_addr; void *ret; int order = get_order(size); + u64 dma_mask = DMA_32BIT_MASK; + + if (hwdev && hwdev->coherent_dma_mask) + dma_mask = hwdev->coherent_dma_mask; ret = (void *)__get_free_pages(flags, order); - if (ret && address_needs_mapping(hwdev, virt_to_bus(ret), size)) { + if (ret && !is_buffer_dma_capable(dma_mask, virt_to_bus(ret), size)) { /* * The allocated memory isn't reachable by the device. * Fall back on swiotlb_map_single(). @@ -493,12 +497,14 @@ swiotlb_alloc_coherent(struct device *hwdev, size_t size, dev_addr = virt_to_bus(ret); /* Confirm address can be DMA'd by device */ - if (address_needs_mapping(hwdev, dev_addr, size)) { + if (!is_buffer_dma_capable(dma_mask, dev_addr, size)) { printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", - (unsigned long long)*hwdev->dma_mask, + (unsigned long long)dma_mask, (unsigned long long)dev_addr); - panic("swiotlb_alloc_coherent: allocated memory is out of " - "range for device"); + + /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ + unmap_single(hwdev, ret, size, DMA_TO_DEVICE); + return NULL; } *dma_handle = dev_addr; return ret; diff --git a/mm/backing-dev.c b/mm/backing-dev.c index f2e574dbc300..801c08b046e6 100644 --- a/mm/backing-dev.c +++ b/mm/backing-dev.c @@ -176,6 +176,9 @@ int bdi_register(struct backing_dev_info *bdi, struct device *parent, int ret = 0; struct device *dev; + if (bdi->dev) /* The driver needs to use separate queues per device */ + goto exit; + va_start(args, fmt); dev = device_create_vargs(bdi_class, parent, MKDEV(0, 0), bdi, fmt, args); va_end(args); diff --git a/mm/filemap.c b/mm/filemap.c index ab8553658af3..f3e5f8944d17 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -2029,48 +2029,8 @@ int pagecache_write_begin(struct file *file, struct address_space *mapping, { const struct address_space_operations *aops = mapping->a_ops; - if (aops->write_begin) { - return aops->write_begin(file, mapping, pos, len, flags, + return aops->write_begin(file, mapping, pos, len, flags, pagep, fsdata); - } else { - int ret; - pgoff_t index = pos >> PAGE_CACHE_SHIFT; - unsigned offset = pos & (PAGE_CACHE_SIZE - 1); - struct inode *inode = mapping->host; - struct page *page; -again: - page = __grab_cache_page(mapping, index); - *pagep = page; - if (!page) - return -ENOMEM; - - if (flags & AOP_FLAG_UNINTERRUPTIBLE && !PageUptodate(page)) { - /* - * There is no way to resolve a short write situation - * for a !Uptodate page (except by double copying in - * the caller done by generic_perform_write_2copy). - * - * Instead, we have to bring it uptodate here. - */ - ret = aops->readpage(file, page); - page_cache_release(page); - if (ret) { - if (ret == AOP_TRUNCATED_PAGE) - goto again; - return ret; - } - goto again; - } - - ret = aops->prepare_write(file, page, offset, offset+len); - if (ret) { - unlock_page(page); - page_cache_release(page); - if (pos + len > inode->i_size) - vmtruncate(inode, inode->i_size); - } - return ret; - } } EXPORT_SYMBOL(pagecache_write_begin); @@ -2079,32 +2039,9 @@ int pagecache_write_end(struct file *file, struct address_space *mapping, struct page *page, void *fsdata) { const struct address_space_operations *aops = mapping->a_ops; - int ret; - - if (aops->write_end) { - mark_page_accessed(page); - ret = aops->write_end(file, mapping, pos, len, copied, - page, fsdata); - } else { - unsigned offset = pos & (PAGE_CACHE_SIZE - 1); - struct inode *inode = mapping->host; - - flush_dcache_page(page); - ret = aops->commit_write(file, page, offset, offset+len); - unlock_page(page); - mark_page_accessed(page); - page_cache_release(page); - - if (ret < 0) { - if (pos + len > inode->i_size) - vmtruncate(inode, inode->i_size); - } else if (ret > 0) - ret = min_t(size_t, copied, ret); - else - ret = copied; - } - return ret; + mark_page_accessed(page); + return aops->write_end(file, mapping, pos, len, copied, page, fsdata); } EXPORT_SYMBOL(pagecache_write_end); @@ -2226,174 +2163,6 @@ repeat: } EXPORT_SYMBOL(__grab_cache_page); -static ssize_t generic_perform_write_2copy(struct file *file, - struct iov_iter *i, loff_t pos) -{ - struct address_space *mapping = file->f_mapping; - const struct address_space_operations *a_ops = mapping->a_ops; - struct inode *inode = mapping->host; - long status = 0; - ssize_t written = 0; - - do { - struct page *src_page; - struct page *page; - pgoff_t index; /* Pagecache index for current page */ - unsigned long offset; /* Offset into pagecache page */ - unsigned long bytes; /* Bytes to write to page */ - size_t copied; /* Bytes copied from user */ - - offset = (pos & (PAGE_CACHE_SIZE - 1)); - index = pos >> PAGE_CACHE_SHIFT; - bytes = min_t(unsigned long, PAGE_CACHE_SIZE - offset, - iov_iter_count(i)); - - /* - * a non-NULL src_page indicates that we're doing the - * copy via get_user_pages and kmap. - */ - src_page = NULL; - - /* - * Bring in the user page that we will copy from _first_. - * Otherwise there's a nasty deadlock on copying from the - * same page as we're writing to, without it being marked - * up-to-date. - * - * Not only is this an optimisation, but it is also required - * to check that the address is actually valid, when atomic - * usercopies are used, below. - */ - if (unlikely(iov_iter_fault_in_readable(i, bytes))) { - status = -EFAULT; - break; - } - - page = __grab_cache_page(mapping, index); - if (!page) { - status = -ENOMEM; - break; - } - - /* - * non-uptodate pages cannot cope with short copies, and we - * cannot take a pagefault with the destination page locked. - * So pin the source page to copy it. - */ - if (!PageUptodate(page) && !segment_eq(get_fs(), KERNEL_DS)) { - unlock_page(page); - - src_page = alloc_page(GFP_KERNEL); - if (!src_page) { - page_cache_release(page); - status = -ENOMEM; - break; - } - - /* - * Cannot get_user_pages with a page locked for the - * same reason as we can't take a page fault with a - * page locked (as explained below). - */ - copied = iov_iter_copy_from_user(src_page, i, - offset, bytes); - if (unlikely(copied == 0)) { - status = -EFAULT; - page_cache_release(page); - page_cache_release(src_page); - break; - } - bytes = copied; - - lock_page(page); - /* - * Can't handle the page going uptodate here, because - * that means we would use non-atomic usercopies, which - * zero out the tail of the page, which can cause - * zeroes to become transiently visible. We could just - * use a non-zeroing copy, but the APIs aren't too - * consistent. - */ - if (unlikely(!page->mapping || PageUptodate(page))) { - unlock_page(page); - page_cache_release(page); - page_cache_release(src_page); - continue; - } - } - - status = a_ops->prepare_write(file, page, offset, offset+bytes); - if (unlikely(status)) - goto fs_write_aop_error; - - if (!src_page) { - /* - * Must not enter the pagefault handler here, because - * we hold the page lock, so we might recursively - * deadlock on the same lock, or get an ABBA deadlock - * against a different lock, or against the mmap_sem - * (which nests outside the page lock). So increment - * preempt count, and use _atomic usercopies. - * - * The page is uptodate so we are OK to encounter a - * short copy: if unmodified parts of the page are - * marked dirty and written out to disk, it doesn't - * really matter. - */ - pagefault_disable(); - copied = iov_iter_copy_from_user_atomic(page, i, - offset, bytes); - pagefault_enable(); - } else { - void *src, *dst; - src = kmap_atomic(src_page, KM_USER0); - dst = kmap_atomic(page, KM_USER1); - memcpy(dst + offset, src + offset, bytes); - kunmap_atomic(dst, KM_USER1); - kunmap_atomic(src, KM_USER0); - copied = bytes; - } - flush_dcache_page(page); - - status = a_ops->commit_write(file, page, offset, offset+bytes); - if (unlikely(status < 0)) - goto fs_write_aop_error; - if (unlikely(status > 0)) /* filesystem did partial write */ - copied = min_t(size_t, copied, status); - - unlock_page(page); - mark_page_accessed(page); - page_cache_release(page); - if (src_page) - page_cache_release(src_page); - - iov_iter_advance(i, copied); - pos += copied; - written += copied; - - balance_dirty_pages_ratelimited(mapping); - cond_resched(); - continue; - -fs_write_aop_error: - unlock_page(page); - page_cache_release(page); - if (src_page) - page_cache_release(src_page); - - /* - * prepare_write() may have instantiated a few blocks - * outside i_size. Trim these off again. Don't need - * i_size_read because we hold i_mutex. - */ - if (pos + bytes > inode->i_size) - vmtruncate(inode, inode->i_size); - break; - } while (iov_iter_count(i)); - - return written ? written : status; -} - static ssize_t generic_perform_write(struct file *file, struct iov_iter *i, loff_t pos) { @@ -2494,10 +2263,7 @@ generic_file_buffered_write(struct kiocb *iocb, const struct iovec *iov, struct iov_iter i; iov_iter_init(&i, iov, nr_segs, count, written); - if (a_ops->write_begin) - status = generic_perform_write(file, &i, pos); - else - status = generic_perform_write_2copy(file, &i, pos); + status = generic_perform_write(file, &i, pos); if (likely(status >= 0)) { written += status; diff --git a/mm/hugetlb.c b/mm/hugetlb.c index 421aee99b84a..6058b53dcb89 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@ -354,11 +354,26 @@ static int vma_has_reserves(struct vm_area_struct *vma) return 0; } +static void clear_gigantic_page(struct page *page, + unsigned long addr, unsigned long sz) +{ + int i; + struct page *p = page; + + might_sleep(); + for (i = 0; i < sz/PAGE_SIZE; i++, p = mem_map_next(p, page, i)) { + cond_resched(); + clear_user_highpage(p, addr + i * PAGE_SIZE); + } +} static void clear_huge_page(struct page *page, unsigned long addr, unsigned long sz) { int i; + if (unlikely(sz > MAX_ORDER_NR_PAGES)) + return clear_gigantic_page(page, addr, sz); + might_sleep(); for (i = 0; i < sz/PAGE_SIZE; i++) { cond_resched(); @@ -366,12 +381,32 @@ static void clear_huge_page(struct page *page, } } +static void copy_gigantic_page(struct page *dst, struct page *src, + unsigned long addr, struct vm_area_struct *vma) +{ + int i; + struct hstate *h = hstate_vma(vma); + struct page *dst_base = dst; + struct page *src_base = src; + might_sleep(); + for (i = 0; i < pages_per_huge_page(h); ) { + cond_resched(); + copy_user_highpage(dst, src, addr + i*PAGE_SIZE, vma); + + i++; + dst = mem_map_next(dst, dst_base, i); + src = mem_map_next(src, src_base, i); + } +} static void copy_huge_page(struct page *dst, struct page *src, unsigned long addr, struct vm_area_struct *vma) { int i; struct hstate *h = hstate_vma(vma); + if (unlikely(pages_per_huge_page(h) > MAX_ORDER_NR_PAGES)) + return copy_gigantic_page(dst, src, addr, vma); + might_sleep(); for (i = 0; i < pages_per_huge_page(h); i++) { cond_resched(); @@ -456,6 +491,8 @@ static void update_and_free_page(struct hstate *h, struct page *page) { int i; + VM_BUG_ON(h->order >= MAX_ORDER); + h->nr_huge_pages--; h->nr_huge_pages_node[page_to_nid(page)]--; for (i = 0; i < pages_per_huge_page(h); i++) { @@ -970,6 +1007,14 @@ found: return 1; } +static void prep_compound_huge_page(struct page *page, int order) +{ + if (unlikely(order > (MAX_ORDER - 1))) + prep_compound_gigantic_page(page, order); + else + prep_compound_page(page, order); +} + /* Put bootmem huge pages into the standard lists after mem_map is up */ static void __init gather_bootmem_prealloc(void) { @@ -980,7 +1025,7 @@ static void __init gather_bootmem_prealloc(void) struct hstate *h = m->hstate; __ClearPageReserved(page); WARN_ON(page_count(page) != 1); - prep_compound_page(page, h->order); + prep_compound_huge_page(page, h->order); prep_new_huge_page(h, page, page_to_nid(page)); } } @@ -1751,6 +1796,7 @@ void unmap_hugepage_range(struct vm_area_struct *vma, unsigned long start, static int unmap_ref_private(struct mm_struct *mm, struct vm_area_struct *vma, struct page *page, unsigned long address) { + struct hstate *h = hstate_vma(vma); struct vm_area_struct *iter_vma; struct address_space *mapping; struct prio_tree_iter iter; @@ -1760,7 +1806,7 @@ static int unmap_ref_private(struct mm_struct *mm, struct vm_area_struct *vma, * vm_pgoff is in PAGE_SIZE units, hence the different calculation * from page cache lookup which is in HPAGE_SIZE units. */ - address = address & huge_page_mask(hstate_vma(vma)); + address = address & huge_page_mask(h); pgoff = ((address - vma->vm_start) >> PAGE_SHIFT) + (vma->vm_pgoff >> PAGE_SHIFT); mapping = (struct address_space *)page_private(page); @@ -1779,7 +1825,7 @@ static int unmap_ref_private(struct mm_struct *mm, struct vm_area_struct *vma, */ if (!is_vma_resv_set(iter_vma, HPAGE_RESV_OWNER)) unmap_hugepage_range(iter_vma, - address, address + HPAGE_SIZE, + address, address + huge_page_size(h), page); } @@ -2130,7 +2176,7 @@ same_page: if (zeropage_ok) pages[i] = ZERO_PAGE(0); else - pages[i] = page + pfn_offset; + pages[i] = mem_map_offset(page, pfn_offset); get_page(pages[i]); } diff --git a/mm/internal.h b/mm/internal.h index e4e728bdf324..13333bc2eb68 100644 --- a/mm/internal.h +++ b/mm/internal.h @@ -17,6 +17,7 @@ void free_pgtables(struct mmu_gather *tlb, struct vm_area_struct *start_vma, unsigned long floor, unsigned long ceiling); extern void prep_compound_page(struct page *page, unsigned long order); +extern void prep_compound_gigantic_page(struct page *page, unsigned long order); static inline void set_page_count(struct page *page, int v) { @@ -175,6 +176,34 @@ static inline void free_page_mlock(struct page *page) { } #endif /* CONFIG_UNEVICTABLE_LRU */ +/* + * Return the mem_map entry representing the 'offset' subpage within + * the maximally aligned gigantic page 'base'. Handle any discontiguity + * in the mem_map at MAX_ORDER_NR_PAGES boundaries. + */ +static inline struct page *mem_map_offset(struct page *base, int offset) +{ + if (unlikely(offset >= MAX_ORDER_NR_PAGES)) + return pfn_to_page(page_to_pfn(base) + offset); + return base + offset; +} + +/* + * Iterator over all subpages withing the maximally aligned gigantic + * page 'base'. Handle any discontiguity in the mem_map. + */ +static inline struct page *mem_map_next(struct page *iter, + struct page *base, int offset) +{ + if (unlikely((offset & (MAX_ORDER_NR_PAGES - 1)) == 0)) { + unsigned long pfn = page_to_pfn(base) + offset; + if (!pfn_valid(pfn)) + return NULL; + return pfn_to_page(pfn); + } + return iter + 1; +} + /* * FLATMEM and DISCONTIGMEM configurations use alloc_bootmem_node, * so all functions starting at paging_init should be marked __init diff --git a/mm/memory.c b/mm/memory.c index 164951c47305..f01b7eed6e16 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -669,6 +669,16 @@ int copy_page_range(struct mm_struct *dst_mm, struct mm_struct *src_mm, if (is_vm_hugetlb_page(vma)) return copy_hugetlb_page_range(dst_mm, src_mm, vma); + if (unlikely(is_pfn_mapping(vma))) { + /* + * We do not free on error cases below as remove_vma + * gets called on error from higher level routine + */ + ret = track_pfn_vma_copy(vma); + if (ret) + return ret; + } + /* * We need to invalidate the secondary MMU mappings only when * there could be a permission downgrade on the ptes of the @@ -915,6 +925,9 @@ unsigned long unmap_vmas(struct mmu_gather **tlbp, if (vma->vm_flags & VM_ACCOUNT) *nr_accounted += (end - start) >> PAGE_SHIFT; + if (unlikely(is_pfn_mapping(vma))) + untrack_pfn_vma(vma, 0, 0); + while (start != end) { if (!tlb_start_valid) { tlb_start = start; @@ -1430,6 +1443,7 @@ out: int vm_insert_pfn(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) { + int ret; /* * Technically, architectures with pte_special can avoid all these * restrictions (same for remap_pfn_range). However we would like @@ -1444,7 +1458,15 @@ int vm_insert_pfn(struct vm_area_struct *vma, unsigned long addr, if (addr < vma->vm_start || addr >= vma->vm_end) return -EFAULT; - return insert_pfn(vma, addr, pfn, vma->vm_page_prot); + if (track_pfn_vma_new(vma, vma->vm_page_prot, pfn, PAGE_SIZE)) + return -EINVAL; + + ret = insert_pfn(vma, addr, pfn, vma->vm_page_prot); + + if (ret) + untrack_pfn_vma(vma, pfn, PAGE_SIZE); + + return ret; } EXPORT_SYMBOL(vm_insert_pfn); @@ -1575,14 +1597,17 @@ int remap_pfn_range(struct vm_area_struct *vma, unsigned long addr, * behaviour that some programs depend on. We mark the "original" * un-COW'ed pages by matching them up with "vma->vm_pgoff". */ - if (is_cow_mapping(vma->vm_flags)) { - if (addr != vma->vm_start || end != vma->vm_end) - return -EINVAL; + if (addr == vma->vm_start && end == vma->vm_end) vma->vm_pgoff = pfn; - } + else if (is_cow_mapping(vma->vm_flags)) + return -EINVAL; vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP; + err = track_pfn_vma_new(vma, prot, pfn, PAGE_ALIGN(size)); + if (err) + return -EINVAL; + BUG_ON(addr >= end); pfn -= addr >> PAGE_SHIFT; pgd = pgd_offset(mm, addr); @@ -1594,6 +1619,10 @@ int remap_pfn_range(struct vm_area_struct *vma, unsigned long addr, if (err) break; } while (pgd++, addr = next, addr != end); + + if (err) + untrack_pfn_vma(vma, pfn, PAGE_ALIGN(size)); + return err; } EXPORT_SYMBOL(remap_pfn_range); @@ -2865,9 +2894,9 @@ int in_gate_area_no_task(unsigned long addr) #endif /* __HAVE_ARCH_GATE_AREA */ #ifdef CONFIG_HAVE_IOREMAP_PROT -static resource_size_t follow_phys(struct vm_area_struct *vma, - unsigned long address, unsigned int flags, - unsigned long *prot) +int follow_phys(struct vm_area_struct *vma, + unsigned long address, unsigned int flags, + unsigned long *prot, resource_size_t *phys) { pgd_t *pgd; pud_t *pud; @@ -2876,24 +2905,26 @@ static resource_size_t follow_phys(struct vm_area_struct *vma, spinlock_t *ptl; resource_size_t phys_addr = 0; struct mm_struct *mm = vma->vm_mm; + int ret = -EINVAL; - VM_BUG_ON(!(vma->vm_flags & (VM_IO | VM_PFNMAP))); + if (!(vma->vm_flags & (VM_IO | VM_PFNMAP))) + goto out; pgd = pgd_offset(mm, address); if (pgd_none(*pgd) || unlikely(pgd_bad(*pgd))) - goto no_page_table; + goto out; pud = pud_offset(pgd, address); if (pud_none(*pud) || unlikely(pud_bad(*pud))) - goto no_page_table; + goto out; pmd = pmd_offset(pud, address); if (pmd_none(*pmd) || unlikely(pmd_bad(*pmd))) - goto no_page_table; + goto out; /* We cannot handle huge page PFN maps. Luckily they don't exist. */ if (pmd_huge(*pmd)) - goto no_page_table; + goto out; ptep = pte_offset_map_lock(mm, pmd, address, &ptl); if (!ptep) @@ -2908,13 +2939,13 @@ static resource_size_t follow_phys(struct vm_area_struct *vma, phys_addr <<= PAGE_SHIFT; /* Shift here to avoid overflow on PAE */ *prot = pgprot_val(pte_pgprot(pte)); + *phys = phys_addr; + ret = 0; unlock: pte_unmap_unlock(ptep, ptl); out: - return phys_addr; -no_page_table: - return 0; + return ret; } int generic_access_phys(struct vm_area_struct *vma, unsigned long addr, @@ -2925,12 +2956,7 @@ int generic_access_phys(struct vm_area_struct *vma, unsigned long addr, void *maddr; int offset = addr & (PAGE_SIZE-1); - if (!(vma->vm_flags & (VM_IO | VM_PFNMAP))) - return -EINVAL; - - phys_addr = follow_phys(vma, addr, write, &prot); - - if (!phys_addr) + if (follow_phys(vma, addr, write, &prot, &phys_addr)) return -EINVAL; maddr = ioremap_prot(phys_addr, PAGE_SIZE, prot); diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c index 6837a1014372..b17371185468 100644 --- a/mm/memory_hotplug.c +++ b/mm/memory_hotplug.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -190,7 +189,7 @@ static void grow_pgdat_span(struct pglist_data *pgdat, unsigned long start_pfn, pgdat->node_start_pfn; } -static int __add_zone(struct zone *zone, unsigned long phys_start_pfn) +static int __meminit __add_zone(struct zone *zone, unsigned long phys_start_pfn) { struct pglist_data *pgdat = zone->zone_pgdat; int nr_pages = PAGES_PER_SECTION; @@ -217,7 +216,7 @@ static int __add_zone(struct zone *zone, unsigned long phys_start_pfn) return 0; } -static int __add_section(struct zone *zone, unsigned long phys_start_pfn) +static int __meminit __add_section(struct zone *zone, unsigned long phys_start_pfn) { int nr_pages = PAGES_PER_SECTION; int ret; @@ -274,7 +273,7 @@ static int __remove_section(struct zone *zone, struct mem_section *ms) * call this function after deciding the zone to which to * add the new pages. */ -int __add_pages(struct zone *zone, unsigned long phys_start_pfn, +int __ref __add_pages(struct zone *zone, unsigned long phys_start_pfn, unsigned long nr_pages) { unsigned long i; @@ -471,7 +470,8 @@ static void rollback_node_hotadd(int nid, pg_data_t *pgdat) } -int add_memory(int nid, u64 start, u64 size) +/* we are OK calling __meminit stuff here - we have CONFIG_MEMORY_HOTPLUG */ +int __ref add_memory(int nid, u64 start, u64 size) { pg_data_t *pgdat = NULL; int new_pgdat = 0; @@ -498,8 +498,6 @@ int add_memory(int nid, u64 start, u64 size) /* we online node here. we can't roll back from here. */ node_set_online(nid); - cpuset_track_online_nodes(); - if (new_pgdat) { ret = register_one_node(nid); /* diff --git a/mm/mempolicy.c b/mm/mempolicy.c index 36f42573a335..e9493b1c1117 100644 --- a/mm/mempolicy.c +++ b/mm/mempolicy.c @@ -489,12 +489,6 @@ check_range(struct mm_struct *mm, unsigned long start, unsigned long end, int err; struct vm_area_struct *first, *vma, *prev; - if (flags & (MPOL_MF_MOVE | MPOL_MF_MOVE_ALL)) { - - err = migrate_prep(); - if (err) - return ERR_PTR(err); - } first = find_vma(mm, start); if (!first) @@ -809,9 +803,13 @@ int do_migrate_pages(struct mm_struct *mm, const nodemask_t *from_nodes, const nodemask_t *to_nodes, int flags) { int busy = 0; - int err = 0; + int err; nodemask_t tmp; + err = migrate_prep(); + if (err) + return err; + down_read(&mm->mmap_sem); err = migrate_vmas(mm, from_nodes, to_nodes, flags); @@ -974,6 +972,12 @@ static long do_mbind(unsigned long start, unsigned long len, start, start + len, mode, mode_flags, nmask ? nodes_addr(*nmask)[0] : -1); + if (flags & (MPOL_MF_MOVE | MPOL_MF_MOVE_ALL)) { + + err = migrate_prep(); + if (err) + return err; + } down_write(&mm->mmap_sem); vma = check_range(mm, start, end, nmask, flags | MPOL_MF_INVERT, &pagelist); diff --git a/mm/migrate.c b/mm/migrate.c index 6602941bfab0..037b0967c1e3 100644 --- a/mm/migrate.c +++ b/mm/migrate.c @@ -522,15 +522,12 @@ static int writeout(struct address_space *mapping, struct page *page) remove_migration_ptes(page, page); rc = mapping->a_ops->writepage(page, &wbc); - if (rc < 0) - /* I/O Error writing */ - return -EIO; if (rc != AOP_WRITEPAGE_ACTIVATE) /* unlocked. Relock */ lock_page(page); - return -EAGAIN; + return (rc < 0) ? -EIO : -EAGAIN; } /* @@ -841,12 +838,12 @@ static int do_move_page_to_node_array(struct mm_struct *mm, struct page_to_node *pp; LIST_HEAD(pagelist); + migrate_prep(); down_read(&mm->mmap_sem); /* * Build a list of pages to migrate */ - migrate_prep(); for (pp = pm; pp->node != MAX_NUMNODES; pp++) { struct vm_area_struct *vma; struct page *page; @@ -990,25 +987,18 @@ out: /* * Determine the nodes of an array of pages and store it in an array of status. */ -static int do_pages_stat(struct mm_struct *mm, unsigned long nr_pages, - const void __user * __user *pages, - int __user *status) +static void do_pages_stat_array(struct mm_struct *mm, unsigned long nr_pages, + const void __user **pages, int *status) { unsigned long i; - int err; down_read(&mm->mmap_sem); for (i = 0; i < nr_pages; i++) { - const void __user *p; - unsigned long addr; + unsigned long addr = (unsigned long)(*pages); struct vm_area_struct *vma; struct page *page; - - err = -EFAULT; - if (get_user(p, pages+i)) - goto out; - addr = (unsigned long) p; + int err = -EFAULT; vma = find_vma(mm, addr); if (!vma) @@ -1027,12 +1017,52 @@ static int do_pages_stat(struct mm_struct *mm, unsigned long nr_pages, err = page_to_nid(page); set_status: - put_user(err, status+i); + *status = err; + + pages++; + status++; + } + + up_read(&mm->mmap_sem); +} + +/* + * Determine the nodes of a user array of pages and store it in + * a user array of status. + */ +static int do_pages_stat(struct mm_struct *mm, unsigned long nr_pages, + const void __user * __user *pages, + int __user *status) +{ +#define DO_PAGES_STAT_CHUNK_NR 16 + const void __user *chunk_pages[DO_PAGES_STAT_CHUNK_NR]; + int chunk_status[DO_PAGES_STAT_CHUNK_NR]; + unsigned long i, chunk_nr = DO_PAGES_STAT_CHUNK_NR; + int err; + + for (i = 0; i < nr_pages; i += chunk_nr) { + if (chunk_nr + i > nr_pages) + chunk_nr = nr_pages - i; + + err = copy_from_user(chunk_pages, &pages[i], + chunk_nr * sizeof(*chunk_pages)); + if (err) { + err = -EFAULT; + goto out; + } + + do_pages_stat_array(mm, chunk_nr, chunk_pages, chunk_status); + + err = copy_to_user(&status[i], chunk_status, + chunk_nr * sizeof(*chunk_status)); + if (err) { + err = -EFAULT; + goto out; + } } err = 0; out: - up_read(&mm->mmap_sem); return err; } diff --git a/mm/mlock.c b/mm/mlock.c index 008ea70b7afa..1ada366570cb 100644 --- a/mm/mlock.c +++ b/mm/mlock.c @@ -66,14 +66,10 @@ void __clear_page_mlock(struct page *page) putback_lru_page(page); } else { /* - * Page not on the LRU yet. Flush all pagevecs and retry. + * We lost the race. the page already moved to evictable list. */ - lru_add_drain_all(); - if (!isolate_lru_page(page)) - putback_lru_page(page); - else if (PageUnevictable(page)) + if (PageUnevictable(page)) count_vm_event(UNEVICTABLE_PGSTRANDED); - } } @@ -166,7 +162,7 @@ static long __mlock_vma_pages_range(struct vm_area_struct *vma, unsigned long addr = start; struct page *pages[16]; /* 16 gives a reasonable batch */ int nr_pages = (end - start) / PAGE_SIZE; - int ret; + int ret = 0; int gup_flags = 0; VM_BUG_ON(start & ~PAGE_MASK); @@ -187,8 +183,6 @@ static long __mlock_vma_pages_range(struct vm_area_struct *vma, if (vma->vm_flags & VM_WRITE) gup_flags |= GUP_FLAGS_WRITE; - lru_add_drain_all(); /* push cached pages to LRU */ - while (nr_pages > 0) { int i; @@ -251,8 +245,6 @@ static long __mlock_vma_pages_range(struct vm_area_struct *vma, ret = 0; } - lru_add_drain_all(); /* to update stats */ - return ret; /* count entire vma as locked_vm */ } @@ -546,6 +538,8 @@ asmlinkage long sys_mlock(unsigned long start, size_t len) if (!can_do_mlock()) return -EPERM; + lru_add_drain_all(); /* flush pagevec */ + down_write(¤t->mm->mmap_sem); len = PAGE_ALIGN(len + (start & ~PAGE_MASK)); start &= PAGE_MASK; @@ -612,6 +606,8 @@ asmlinkage long sys_mlockall(int flags) if (!can_do_mlock()) goto out; + lru_add_drain_all(); /* flush pagevec */ + down_write(¤t->mm->mmap_sem); lock_limit = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur; diff --git a/mm/mmap.c b/mm/mmap.c index 74f4d158022e..d4855a682ab6 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -175,7 +175,8 @@ int __vm_enough_memory(struct mm_struct *mm, long pages, int cap_sys_admin) /* Don't let a single process grow too big: leave 3% of the size of this process for other processes */ - allowed -= mm->total_vm / 32; + if (mm) + allowed -= mm->total_vm / 32; /* * cast `allowed' as a signed long because vm_committed_space @@ -1703,7 +1704,7 @@ find_extend_vma(struct mm_struct *mm, unsigned long addr) vma = find_vma_prev(mm, addr, &prev); if (vma && (vma->vm_start <= addr)) return vma; - if (expand_stack(prev, addr)) + if (!prev || expand_stack(prev, addr)) return NULL; if (prev->vm_flags & VM_LOCKED) { if (mlock_vma_pages_range(prev, addr, prev->vm_end) < 0) diff --git a/mm/nommu.c b/mm/nommu.c index 2696b24f2bb3..7695dc850785 100644 --- a/mm/nommu.c +++ b/mm/nommu.c @@ -1454,7 +1454,8 @@ int __vm_enough_memory(struct mm_struct *mm, long pages, int cap_sys_admin) /* Don't let a single process grow too big: leave 3% of the size of this process for other processes */ - allowed -= current->mm->total_vm / 32; + if (mm) + allowed -= mm->total_vm / 32; /* * cast `allowed' as a signed long because vm_committed_space diff --git a/mm/oom_kill.c b/mm/oom_kill.c index 64e5b4bcd964..a0a01902f551 100644 --- a/mm/oom_kill.c +++ b/mm/oom_kill.c @@ -38,7 +38,6 @@ static DEFINE_SPINLOCK(zone_scan_mutex); * badness - calculate a numeric value for how bad this task has been * @p: task struct of which task we should calculate * @uptime: current uptime in seconds - * @mem: target memory controller * * The formula used is relatively simple and documented inline in the * function. The main rationale is that we want to select a good task @@ -295,6 +294,8 @@ static void dump_tasks(const struct mem_cgroup *mem) continue; if (mem && !task_in_mem_cgroup(p, mem)) continue; + if (!thread_group_leader(p)) + continue; task_lock(p); printk(KERN_INFO "[%5d] %5d %5d %8lu %8lu %3d %3d %s\n", diff --git a/mm/page_alloc.c b/mm/page_alloc.c index d0a240fbb8bf..d8ac01474563 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -260,6 +260,23 @@ static void free_compound_page(struct page *page) } void prep_compound_page(struct page *page, unsigned long order) +{ + int i; + int nr_pages = 1 << order; + + set_compound_page_dtor(page, free_compound_page); + set_compound_order(page, order); + __SetPageHead(page); + for (i = 1; i < nr_pages; i++) { + struct page *p = page + i; + + __SetPageTail(p); + p->first_page = page; + } +} + +#ifdef CONFIG_HUGETLBFS +void prep_compound_gigantic_page(struct page *page, unsigned long order) { int i; int nr_pages = 1 << order; @@ -268,19 +285,17 @@ void prep_compound_page(struct page *page, unsigned long order) set_compound_page_dtor(page, free_compound_page); set_compound_order(page, order); __SetPageHead(page); - for (i = 1; i < nr_pages; i++, p++) { - if (unlikely((i & (MAX_ORDER_NR_PAGES - 1)) == 0)) - p = pfn_to_page(page_to_pfn(page) + i); + for (i = 1; i < nr_pages; i++, p = mem_map_next(p, page, i)) { __SetPageTail(p); p->first_page = page; } } +#endif static void destroy_compound_page(struct page *page, unsigned long order) { int i; int nr_pages = 1 << order; - struct page *p = page + 1; if (unlikely(compound_order(page) != order)) bad_page(page); @@ -288,9 +303,8 @@ static void destroy_compound_page(struct page *page, unsigned long order) if (unlikely(!PageHead(page))) bad_page(page); __ClearPageHead(page); - for (i = 1; i < nr_pages; i++, p++) { - if (unlikely((i & (MAX_ORDER_NR_PAGES - 1)) == 0)) - p = pfn_to_page(page_to_pfn(page) + i); + for (i = 1; i < nr_pages; i++) { + struct page *p = page + i; if (unlikely(!PageTail(p) | (p->first_page != page))) @@ -1547,6 +1561,10 @@ nofail_alloc: /* We now go into synchronous reclaim */ cpuset_memory_pressure_bump(); + /* + * The task's cpuset might have expanded its set of allowable nodes + */ + cpuset_update_task_memory_state(); p->flags |= PF_MEMALLOC; reclaim_state.reclaimed_slab = 0; p->reclaim_state = &reclaim_state; diff --git a/mm/page_cgroup.c b/mm/page_cgroup.c index f59d797dc5a9..ab27ff750519 100644 --- a/mm/page_cgroup.c +++ b/mm/page_cgroup.c @@ -21,7 +21,7 @@ static unsigned long total_usage; #if !defined(CONFIG_SPARSEMEM) -void __init pgdat_page_cgroup_init(struct pglist_data *pgdat) +void __meminit pgdat_page_cgroup_init(struct pglist_data *pgdat) { pgdat->node_page_cgroup = NULL; } @@ -49,6 +49,9 @@ static int __init alloc_node_page_cgroup(int nid) start_pfn = NODE_DATA(nid)->node_start_pfn; nr_pages = NODE_DATA(nid)->node_spanned_pages; + if (!nr_pages) + return 0; + table_size = sizeof(struct page_cgroup) * nr_pages; base = __alloc_bootmem_node_nopanic(NODE_DATA(nid), @@ -97,7 +100,8 @@ struct page_cgroup *lookup_page_cgroup(struct page *page) return section->page_cgroup + pfn; } -int __meminit init_section_page_cgroup(unsigned long pfn) +/* __alloc_bootmem...() is protected by !slab_available() */ +int __init_refok init_section_page_cgroup(unsigned long pfn) { struct mem_section *section; struct page_cgroup *base, *pc; @@ -106,19 +110,29 @@ int __meminit init_section_page_cgroup(unsigned long pfn) section = __pfn_to_section(pfn); - if (section->page_cgroup) - return 0; - - nid = page_to_nid(pfn_to_page(pfn)); - - table_size = sizeof(struct page_cgroup) * PAGES_PER_SECTION; - if (slab_is_available()) { - base = kmalloc_node(table_size, GFP_KERNEL, nid); - if (!base) - base = vmalloc_node(table_size, nid); - } else { - base = __alloc_bootmem_node_nopanic(NODE_DATA(nid), table_size, + if (!section->page_cgroup) { + nid = page_to_nid(pfn_to_page(pfn)); + table_size = sizeof(struct page_cgroup) * PAGES_PER_SECTION; + if (slab_is_available()) { + base = kmalloc_node(table_size, GFP_KERNEL, nid); + if (!base) + base = vmalloc_node(table_size, nid); + } else { + base = __alloc_bootmem_node_nopanic(NODE_DATA(nid), + table_size, PAGE_SIZE, __pa(MAX_DMA_ADDRESS)); + } + } else { + /* + * We don't have to allocate page_cgroup again, but + * address of memmap may be changed. So, we have to initialize + * again. + */ + base = section->page_cgroup + pfn; + table_size = 0; + /* check address of memmap is changed or not. */ + if (base->page == pfn_to_page(pfn)) + return 0; } if (!base) { @@ -158,14 +172,14 @@ void __free_page_cgroup(unsigned long pfn) } } -int online_page_cgroup(unsigned long start_pfn, +int __meminit online_page_cgroup(unsigned long start_pfn, unsigned long nr_pages, int nid) { unsigned long start, end, pfn; int fail = 0; - start = start_pfn & (PAGES_PER_SECTION - 1); + start = start_pfn & ~(PAGES_PER_SECTION - 1); end = ALIGN(start_pfn + nr_pages, PAGES_PER_SECTION); for (pfn = start; !fail && pfn < end; pfn += PAGES_PER_SECTION) { @@ -183,12 +197,12 @@ int online_page_cgroup(unsigned long start_pfn, return -ENOMEM; } -int offline_page_cgroup(unsigned long start_pfn, +int __meminit offline_page_cgroup(unsigned long start_pfn, unsigned long nr_pages, int nid) { unsigned long start, end, pfn; - start = start_pfn & (PAGES_PER_SECTION - 1); + start = start_pfn & ~(PAGES_PER_SECTION - 1); end = ALIGN(start_pfn + nr_pages, PAGES_PER_SECTION); for (pfn = start; pfn < end; pfn += PAGES_PER_SECTION) @@ -197,7 +211,7 @@ int offline_page_cgroup(unsigned long start_pfn, } -static int page_cgroup_callback(struct notifier_block *self, +static int __meminit page_cgroup_callback(struct notifier_block *self, unsigned long action, void *arg) { struct memory_notify *mn = arg; @@ -207,18 +221,23 @@ static int page_cgroup_callback(struct notifier_block *self, ret = online_page_cgroup(mn->start_pfn, mn->nr_pages, mn->status_change_nid); break; - case MEM_CANCEL_ONLINE: case MEM_OFFLINE: offline_page_cgroup(mn->start_pfn, mn->nr_pages, mn->status_change_nid); break; + case MEM_CANCEL_ONLINE: case MEM_GOING_OFFLINE: break; case MEM_ONLINE: case MEM_CANCEL_OFFLINE: break; } - ret = notifier_from_errno(ret); + + if (ret) + ret = notifier_from_errno(ret); + else + ret = NOTIFY_OK; + return ret; } @@ -248,7 +267,7 @@ void __init page_cgroup_init(void) " want\n"); } -void __init pgdat_page_cgroup_init(struct pglist_data *pgdat) +void __meminit pgdat_page_cgroup_init(struct pglist_data *pgdat) { return; } diff --git a/mm/page_isolation.c b/mm/page_isolation.c index b70a7fec1ff6..5e0ffd967452 100644 --- a/mm/page_isolation.c +++ b/mm/page_isolation.c @@ -130,10 +130,11 @@ int test_pages_isolated(unsigned long start_pfn, unsigned long end_pfn) if (page && get_pageblock_migratetype(page) != MIGRATE_ISOLATE) break; } - if (pfn < end_pfn) + page = __first_valid_page(start_pfn, end_pfn - start_pfn); + if ((pfn < end_pfn) || !page) return -EBUSY; /* Check all pages are free or Marked as ISOLATED */ - zone = page_zone(pfn_to_page(pfn)); + zone = page_zone(page); spin_lock_irqsave(&zone->lock, flags); ret = __test_page_isolated_in_pageblock(start_pfn, end_pfn); spin_unlock_irqrestore(&zone->lock, flags); diff --git a/mm/shmem.c b/mm/shmem.c index d38d7e61fcd0..0ed075215e5f 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -161,8 +161,8 @@ static inline struct shmem_sb_info *SHMEM_SB(struct super_block *sb) */ static inline int shmem_acct_size(unsigned long flags, loff_t size) { - return (flags & VM_ACCOUNT)? - security_vm_enough_memory(VM_ACCT(size)): 0; + return (flags & VM_ACCOUNT) ? + security_vm_enough_memory_kern(VM_ACCT(size)) : 0; } static inline void shmem_unacct_size(unsigned long flags, loff_t size) @@ -179,8 +179,8 @@ static inline void shmem_unacct_size(unsigned long flags, loff_t size) */ static inline int shmem_acct_block(unsigned long flags) { - return (flags & VM_ACCOUNT)? - 0: security_vm_enough_memory(VM_ACCT(PAGE_CACHE_SIZE)); + return (flags & VM_ACCOUNT) ? + 0 : security_vm_enough_memory_kern(VM_ACCT(PAGE_CACHE_SIZE)); } static inline void shmem_unacct_blocks(unsigned long flags, long pages) diff --git a/mm/slob.c b/mm/slob.c index cb675d126791..bf7e8fc3aed8 100644 --- a/mm/slob.c +++ b/mm/slob.c @@ -535,7 +535,7 @@ struct kmem_cache *kmem_cache_create(const char *name, size_t size, struct kmem_cache *c; c = slob_alloc(sizeof(struct kmem_cache), - flags, ARCH_KMALLOC_MINALIGN, -1); + GFP_KERNEL, ARCH_KMALLOC_MINALIGN, -1); if (c) { c->name = name; diff --git a/mm/slub.c b/mm/slub.c index 7ad489af9561..a2cd47d89e0a 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -2931,8 +2931,10 @@ static int slab_memory_callback(struct notifier_block *self, case MEM_CANCEL_OFFLINE: break; } - - ret = notifier_from_errno(ret); + if (ret) + ret = notifier_from_errno(ret); + else + ret = NOTIFY_OK; return ret; } @@ -3595,7 +3597,7 @@ static int list_locations(struct kmem_cache *s, char *buf, for (i = 0; i < t.count; i++) { struct location *l = &t.loc[i]; - if (len > PAGE_SIZE - 100) + if (len > PAGE_SIZE - KSYM_SYMBOL_LEN - 100) break; len += sprintf(buf + len, "%7ld ", l->count); diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c index a91b5f8fcaf6..a13ea6401ae7 100644 --- a/mm/sparse-vmemmap.c +++ b/mm/sparse-vmemmap.c @@ -64,7 +64,7 @@ void __meminit vmemmap_verify(pte_t *pte, int node, unsigned long pfn = pte_pfn(*pte); int actual_node = early_pfn_to_nid(pfn); - if (actual_node != node) + if (node_distance(actual_node, node) > LOCAL_DISTANCE) printk(KERN_WARNING "[%lx-%lx] potential offnode " "page_structs\n", start, end - 1); } diff --git a/mm/sparse.c b/mm/sparse.c index 39db301b920d..083f5b63e7a8 100644 --- a/mm/sparse.c +++ b/mm/sparse.c @@ -570,7 +570,7 @@ static void free_section_usemap(struct page *memmap, unsigned long *usemap) * set. If this is <=0, then that means that the passed-in * map was not consumed and must be freed. */ -int sparse_add_one_section(struct zone *zone, unsigned long start_pfn, +int __meminit sparse_add_one_section(struct zone *zone, unsigned long start_pfn, int nr_pages) { unsigned long section_nr = pfn_to_section_nr(start_pfn); diff --git a/mm/swap.c b/mm/swap.c index 2152e48a7b8f..b135ec90cdeb 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -299,7 +299,6 @@ void lru_add_drain(void) put_cpu(); } -#if defined(CONFIG_NUMA) || defined(CONFIG_UNEVICTABLE_LRU) static void lru_add_drain_per_cpu(struct work_struct *dummy) { lru_add_drain(); @@ -313,18 +312,6 @@ int lru_add_drain_all(void) return schedule_on_each_cpu(lru_add_drain_per_cpu); } -#else - -/* - * Returns 0 for success - */ -int lru_add_drain_all(void) -{ - lru_add_drain(); - return 0; -} -#endif - /* * Batched page_cache_release(). Decrement the reference count on all the * passed pages. If it fell to zero then remove the page from the LRU and @@ -445,6 +432,7 @@ void ____pagevec_lru_add(struct pagevec *pvec, enum lru_list lru) for (i = 0; i < pagevec_count(pvec); i++) { struct page *page = pvec->pages[i]; struct zone *pagezone = page_zone(page); + int file; if (pagezone != zone) { if (zone) @@ -456,8 +444,12 @@ void ____pagevec_lru_add(struct pagevec *pvec, enum lru_list lru) VM_BUG_ON(PageUnevictable(page)); VM_BUG_ON(PageLRU(page)); SetPageLRU(page); - if (is_active_lru(lru)) + file = is_file_lru(lru); + zone->recent_scanned[file]++; + if (is_active_lru(lru)) { SetPageActive(page); + zone->recent_rotated[file]++; + } add_page_to_lru_list(zone, page, lru); } if (zone) diff --git a/mm/swapfile.c b/mm/swapfile.c index 90cb67a5417c..54a9f87e5162 100644 --- a/mm/swapfile.c +++ b/mm/swapfile.c @@ -1462,6 +1462,15 @@ static int __init procswaps_init(void) __initcall(procswaps_init); #endif /* CONFIG_PROC_FS */ +#ifdef MAX_SWAPFILES_CHECK +static int __init max_swapfiles_check(void) +{ + MAX_SWAPFILES_CHECK(); + return 0; +} +late_initcall(max_swapfiles_check); +#endif + /* * Written 01/25/92 by Simmule Turner, heavily changed by Linus. * diff --git a/mm/vmalloc.c b/mm/vmalloc.c index 036536945dd9..1ddb77ba3995 100644 --- a/mm/vmalloc.c +++ b/mm/vmalloc.c @@ -77,7 +77,6 @@ static void vunmap_page_range(unsigned long addr, unsigned long end) BUG_ON(addr >= end); pgd = pgd_offset_k(addr); - flush_cache_vunmap(addr, end); do { next = pgd_addr_end(addr, end); if (pgd_none_or_clear_bad(pgd)) @@ -178,7 +177,7 @@ static int vmap_page_range(unsigned long addr, unsigned long end, static inline int is_vmalloc_or_module_addr(const void *x) { /* - * x86-64 and sparc64 put modules in a special place, + * ARM, x86-64 and sparc64 put modules in a special place, * and fall back on vmalloc() if that fails. Others * just put it in the vmalloc space. */ @@ -324,14 +323,14 @@ static struct vmap_area *alloc_vmap_area(unsigned long size, BUG_ON(size & ~PAGE_MASK); - addr = ALIGN(vstart, align); - va = kmalloc_node(sizeof(struct vmap_area), gfp_mask & GFP_RECLAIM_MASK, node); if (unlikely(!va)) return ERR_PTR(-ENOMEM); retry: + addr = ALIGN(vstart, align); + spin_lock(&vmap_area_lock); /* XXX: could have a last_hole cache */ n = vmap_area_root.rb_node; @@ -362,7 +361,7 @@ retry: goto found; } - while (addr + size >= first->va_start && addr + size <= vend) { + while (addr + size > first->va_start && addr + size <= vend) { addr = ALIGN(first->va_end + PAGE_SIZE, align); n = rb_next(&first->rb_node); @@ -521,6 +520,17 @@ static void __purge_vmap_area_lazy(unsigned long *start, unsigned long *end, spin_unlock(&purge_lock); } +/* + * Kick off a purge of the outstanding lazy areas. Don't bother if somebody + * is already purging. + */ +static void try_purge_vmap_area_lazy(void) +{ + unsigned long start = ULONG_MAX, end = 0; + + __purge_vmap_area_lazy(&start, &end, 0, 0); +} + /* * Kick off a purge of the outstanding lazy areas. */ @@ -528,18 +538,28 @@ static void purge_vmap_area_lazy(void) { unsigned long start = ULONG_MAX, end = 0; - __purge_vmap_area_lazy(&start, &end, 0, 0); + __purge_vmap_area_lazy(&start, &end, 1, 0); } /* - * Free and unmap a vmap area + * Free and unmap a vmap area, caller ensuring flush_cache_vunmap had been + * called for the correct range previously. */ -static void free_unmap_vmap_area(struct vmap_area *va) +static void free_unmap_vmap_area_noflush(struct vmap_area *va) { va->flags |= VM_LAZY_FREE; atomic_add((va->va_end - va->va_start) >> PAGE_SHIFT, &vmap_lazy_nr); if (unlikely(atomic_read(&vmap_lazy_nr) > lazy_max_pages())) - purge_vmap_area_lazy(); + try_purge_vmap_area_lazy(); +} + +/* + * Free and unmap a vmap area + */ +static void free_unmap_vmap_area(struct vmap_area *va) +{ + flush_cache_vunmap(va->va_start, va->va_end); + free_unmap_vmap_area_noflush(va); } static struct vmap_area *find_vmap_area(unsigned long addr) @@ -592,6 +612,8 @@ static void free_unmap_vmap_area_addr(unsigned long addr) #define VMAP_BLOCK_SIZE (VMAP_BBMAP_BITS * PAGE_SIZE) +static bool vmap_initialized __read_mostly = false; + struct vmap_block_queue { spinlock_t lock; struct list_head free; @@ -721,7 +743,7 @@ static void free_vmap_block(struct vmap_block *vb) spin_unlock(&vmap_block_tree_lock); BUG_ON(tmp != vb); - free_unmap_vmap_area(vb->va); + free_unmap_vmap_area_noflush(vb->va); call_rcu(&vb->rcu_head, rcu_free_vb); } @@ -783,6 +805,9 @@ static void vb_free(const void *addr, unsigned long size) BUG_ON(size & ~PAGE_MASK); BUG_ON(size > PAGE_SIZE*VMAP_MAX_ALLOC); + + flush_cache_vunmap((unsigned long)addr, (unsigned long)addr + size); + order = get_order(size); offset = (unsigned long)addr & (VMAP_BLOCK_SIZE - 1); @@ -828,6 +853,9 @@ void vm_unmap_aliases(void) int cpu; int flush = 0; + if (unlikely(!vmap_initialized)) + return; + for_each_possible_cpu(cpu) { struct vmap_block_queue *vbq = &per_cpu(vmap_block_queue, cpu); struct vmap_block *vb; @@ -897,7 +925,8 @@ EXPORT_SYMBOL(vm_unmap_ram); * @count: number of pages * @node: prefer to allocate data structures on this node * @prot: memory protection to use. PAGE_KERNEL for regular RAM - * @returns: a pointer to the address that has been mapped, or NULL on failure + * + * Returns: a pointer to the address that has been mapped, or %NULL on failure */ void *vm_map_ram(struct page **pages, unsigned int count, int node, pgprot_t prot) { @@ -941,6 +970,8 @@ void __init vmalloc_init(void) INIT_LIST_HEAD(&vbq->dirty); vbq->nr_dirty = 0; } + + vmap_initialized = true; } void unmap_kernel_range(unsigned long addr, unsigned long size) @@ -1686,7 +1717,7 @@ static int s_show(struct seq_file *m, void *p) v->addr, v->addr + v->size, v->size); if (v->caller) { - char buff[2 * KSYM_NAME_LEN]; + char buff[KSYM_SYMBOL_LEN]; seq_putc(m, ' '); sprint_symbol(buff, (unsigned long)v->caller); diff --git a/mm/vmscan.c b/mm/vmscan.c index 3b5860294bb6..62e7f62fb559 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -623,6 +623,8 @@ static unsigned long shrink_page_list(struct list_head *page_list, * Try to allocate it some swap space here. */ if (PageAnon(page) && !PageSwapCache(page)) { + if (!(sc->gfp_mask & __GFP_IO)) + goto keep_locked; switch (try_to_munlock(page)) { case SWAP_FAIL: /* shouldn't happen */ case SWAP_AGAIN: @@ -634,6 +636,7 @@ static unsigned long shrink_page_list(struct list_head *page_list, } if (!add_to_swap(page, GFP_ATOMIC)) goto activate_locked; + may_enter_fs = 1; } #endif /* CONFIG_SWAP */ @@ -1245,6 +1248,7 @@ static void shrink_active_list(unsigned long nr_pages, struct zone *zone, list_add(&page->lru, &l_inactive); } + spin_lock_irq(&zone->lru_lock); /* * Count referenced pages from currently used mappings as * rotated, even though they are moved to the inactive list. @@ -1260,7 +1264,6 @@ static void shrink_active_list(unsigned long nr_pages, struct zone *zone, pgmoved = 0; lru = LRU_BASE + file * LRU_FILE; - spin_lock_irq(&zone->lru_lock); while (!list_empty(&l_inactive)) { page = lru_to_page(&l_inactive); prefetchw_prev_lru_page(page, &l_inactive, flags); @@ -1386,9 +1389,9 @@ static void get_scan_ratio(struct zone *zone, struct scan_control *sc, file_prio = 200 - sc->swappiness; /* - * anon recent_rotated[0] - * %anon = 100 * ----------- / ----------------- * IO cost - * anon + file rotate_sum + * The amount of pressure on anon vs file pages is inversely + * proportional to the fraction of recently scanned pages on + * each list that were recently referenced and in active use. */ ap = (anon_prio + 1) * (zone->recent_scanned[0] + 1); ap /= zone->recent_rotated[0] + 1; @@ -2368,39 +2371,6 @@ int page_evictable(struct page *page, struct vm_area_struct *vma) return 1; } -static void show_page_path(struct page *page) -{ - char buf[256]; - if (page_is_file_cache(page)) { - struct address_space *mapping = page->mapping; - struct dentry *dentry; - pgoff_t pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT); - - spin_lock(&mapping->i_mmap_lock); - dentry = d_find_alias(mapping->host); - printk(KERN_INFO "rescued: %s %lu\n", - dentry_path(dentry, buf, 256), pgoff); - spin_unlock(&mapping->i_mmap_lock); - } else { -#if defined(CONFIG_MM_OWNER) && defined(CONFIG_MMU) - struct anon_vma *anon_vma; - struct vm_area_struct *vma; - - anon_vma = page_lock_anon_vma(page); - if (!anon_vma) - return; - - list_for_each_entry(vma, &anon_vma->head, anon_vma_node) { - printk(KERN_INFO "rescued: anon %s\n", - vma->vm_mm->owner->comm); - break; - } - page_unlock_anon_vma(anon_vma); -#endif - } -} - - /** * check_move_unevictable_page - check page for evictability and move to appropriate zone lru list * @page: page to check evictability and move to appropriate lru list @@ -2421,8 +2391,6 @@ retry: if (page_evictable(page, NULL)) { enum lru_list l = LRU_INACTIVE_ANON + page_is_file_cache(page); - show_page_path(page); - __dec_zone_state(zone, NR_UNEVICTABLE); list_move(&page->lru, &zone->lru[l].list); __inc_zone_state(zone, NR_INACTIVE_ANON + l); diff --git a/net/8021q/vlan_core.c b/net/8021q/vlan_core.c index 916061f681b6..68ced4bf158c 100644 --- a/net/8021q/vlan_core.c +++ b/net/8021q/vlan_core.c @@ -3,11 +3,20 @@ #include #include "vlan.h" +struct vlan_hwaccel_cb { + struct net_device *dev; +}; + +static inline struct vlan_hwaccel_cb *vlan_hwaccel_cb(struct sk_buff *skb) +{ + return (struct vlan_hwaccel_cb *)skb->cb; +} + /* VLAN rx hw acceleration helper. This acts like netif_{rx,receive_skb}(). */ int __vlan_hwaccel_rx(struct sk_buff *skb, struct vlan_group *grp, u16 vlan_tci, int polling) { - struct net_device_stats *stats; + struct vlan_hwaccel_cb *cb = vlan_hwaccel_cb(skb); if (skb_bond_should_drop(skb)) { dev_kfree_skb_any(skb); @@ -15,23 +24,35 @@ int __vlan_hwaccel_rx(struct sk_buff *skb, struct vlan_group *grp, } skb->vlan_tci = vlan_tci; + cb->dev = vlan_group_get_device(grp, vlan_tci & VLAN_VID_MASK); + + return (polling ? netif_receive_skb(skb) : netif_rx(skb)); +} +EXPORT_SYMBOL(__vlan_hwaccel_rx); + +int vlan_hwaccel_do_receive(struct sk_buff *skb) +{ + struct vlan_hwaccel_cb *cb = vlan_hwaccel_cb(skb); + struct net_device *dev = cb->dev; + struct net_device_stats *stats; + netif_nit_deliver(skb); - skb->dev = vlan_group_get_device(grp, vlan_tci & VLAN_VID_MASK); - if (skb->dev == NULL) { - dev_kfree_skb_any(skb); - /* Not NET_RX_DROP, this is not being dropped - * due to congestion. */ - return NET_RX_SUCCESS; + if (dev == NULL) { + kfree_skb(skb); + return -1; } - skb->dev->last_rx = jiffies; + + skb->dev = dev; + skb->priority = vlan_get_ingress_priority(dev, skb->vlan_tci); skb->vlan_tci = 0; - stats = &skb->dev->stats; + dev->last_rx = jiffies; + + stats = &dev->stats; stats->rx_packets++; stats->rx_bytes += skb->len; - skb->priority = vlan_get_ingress_priority(skb->dev, vlan_tci); switch (skb->pkt_type) { case PACKET_BROADCAST: break; @@ -43,13 +64,12 @@ int __vlan_hwaccel_rx(struct sk_buff *skb, struct vlan_group *grp, * This allows the VLAN to have a different MAC than the * underlying device, and still route correctly. */ if (!compare_ether_addr(eth_hdr(skb)->h_dest, - skb->dev->dev_addr)) + dev->dev_addr)) skb->pkt_type = PACKET_HOST; break; }; - return (polling ? netif_receive_skb(skb) : netif_rx(skb)); + return 0; } -EXPORT_SYMBOL(__vlan_hwaccel_rx); struct net_device *vlan_dev_real_dev(const struct net_device *dev) { diff --git a/net/8021q/vlanproc.c b/net/8021q/vlanproc.c index 0feefa4e1a4b..3628e0a81b40 100644 --- a/net/8021q/vlanproc.c +++ b/net/8021q/vlanproc.c @@ -314,7 +314,7 @@ static int vlandev_seq_show(struct seq_file *seq, void *offset) dev_info->ingress_priority_map[6], dev_info->ingress_priority_map[7]); - seq_printf(seq, "EGRESSS priority Mappings: "); + seq_printf(seq, " EGRESS priority mappings: "); for (i = 0; i < 16; i++) { const struct vlan_priority_tci_mapping *mp = dev_info->egress_priority_map[i]; diff --git a/net/9p/Kconfig b/net/9p/Kconfig index c42c0c400bf9..0663f99e977a 100644 --- a/net/9p/Kconfig +++ b/net/9p/Kconfig @@ -13,22 +13,24 @@ menuconfig NET_9P If unsure, say N. +if NET_9P + config NET_9P_VIRTIO - depends on NET_9P && EXPERIMENTAL && VIRTIO + depends on EXPERIMENTAL && VIRTIO tristate "9P Virtio Transport (Experimental)" help This builds support for a transports between guest partitions and a host partition. config NET_9P_RDMA - depends on NET_9P && INFINIBAND && EXPERIMENTAL + depends on INET && INFINIBAND && EXPERIMENTAL tristate "9P RDMA Transport (Experimental)" help - This builds support for a RDMA transport. + This builds support for an RDMA transport. config NET_9P_DEBUG bool "Debug information" - depends on NET_9P help Say Y if you want the 9P subsystem to log debug information. +endif diff --git a/net/9p/client.c b/net/9p/client.c index 67717f69412e..4b529454616d 100644 --- a/net/9p/client.c +++ b/net/9p/client.c @@ -189,6 +189,9 @@ static struct p9_req_t *p9_tag_alloc(struct p9_client *c, u16 tag) printk(KERN_ERR "Couldn't grow tag array\n"); kfree(req->tc); kfree(req->rc); + kfree(req->wq); + req->tc = req->rc = NULL; + req->wq = NULL; return ERR_PTR(-ENOMEM); } req->tc->sdata = (char *) req->tc + sizeof(struct p9_fcall); @@ -311,12 +314,6 @@ static void p9_free_req(struct p9_client *c, struct p9_req_t *r) r->status = REQ_STATUS_IDLE; if (tag != P9_NOTAG && p9_idpool_check(tag, c->tagpool)) p9_idpool_put(tag, c->tagpool); - - /* if this was a flush request we have to free response fcall */ - if (r->rc->id == P9_RFLUSH) { - kfree(r->tc); - kfree(r->rc); - } } /** @@ -611,19 +608,21 @@ reterr: static struct p9_fid *p9_fid_create(struct p9_client *clnt) { - int err; + int ret; struct p9_fid *fid; + unsigned long flags; P9_DPRINTK(P9_DEBUG_FID, "clnt %p\n", clnt); fid = kmalloc(sizeof(struct p9_fid), GFP_KERNEL); if (!fid) return ERR_PTR(-ENOMEM); - fid->fid = p9_idpool_get(clnt->fidpool); + ret = p9_idpool_get(clnt->fidpool); if (fid->fid < 0) { - err = -ENOSPC; + ret = -ENOSPC; goto error; } + fid->fid = ret; memset(&fid->qid, 0, sizeof(struct p9_qid)); fid->mode = -1; @@ -632,27 +631,28 @@ static struct p9_fid *p9_fid_create(struct p9_client *clnt) fid->clnt = clnt; fid->aux = NULL; - spin_lock(&clnt->lock); + spin_lock_irqsave(&clnt->lock, flags); list_add(&fid->flist, &clnt->fidlist); - spin_unlock(&clnt->lock); + spin_unlock_irqrestore(&clnt->lock, flags); return fid; error: kfree(fid); - return ERR_PTR(err); + return ERR_PTR(ret); } static void p9_fid_destroy(struct p9_fid *fid) { struct p9_client *clnt; + unsigned long flags; P9_DPRINTK(P9_DEBUG_FID, "fid %d\n", fid->fid); clnt = fid->clnt; p9_idpool_put(fid->fid, clnt->fidpool); - spin_lock(&clnt->lock); + spin_lock_irqsave(&clnt->lock, flags); list_del(&fid->flist); - spin_unlock(&clnt->lock); + spin_unlock_irqrestore(&clnt->lock, flags); kfree(fid); } @@ -818,7 +818,9 @@ struct p9_fid *p9_client_attach(struct p9_client *clnt, struct p9_fid *afid, } P9_DPRINTK(P9_DEBUG_9P, "<<< RATTACH qid %x.%llx.%x\n", - qid.type, qid.path, qid.version); + qid.type, + (unsigned long long)qid.path, + qid.version); memmove(&fid->qid, &qid, sizeof(struct p9_qid)); @@ -865,7 +867,9 @@ p9_client_auth(struct p9_client *clnt, char *uname, u32 n_uname, char *aname) } P9_DPRINTK(P9_DEBUG_9P, "<<< RAUTH qid %x.%llx.%x\n", - qid.type, qid.path, qid.version); + qid.type, + (unsigned long long)qid.path, + qid.version); memmove(&afid->qid, &qid, sizeof(struct p9_qid)); p9_free_req(clnt, req); @@ -930,7 +934,8 @@ struct p9_fid *p9_client_walk(struct p9_fid *oldfid, int nwname, char **wnames, for (count = 0; count < nwqids; count++) P9_DPRINTK(P9_DEBUG_9P, "<<< [%d] %x.%llx.%x\n", - count, wqids[count].type, wqids[count].path, + count, wqids[count].type, + (unsigned long long)wqids[count].path, wqids[count].version); if (nwname) @@ -980,7 +985,9 @@ int p9_client_open(struct p9_fid *fid, int mode) } P9_DPRINTK(P9_DEBUG_9P, "<<< ROPEN qid %x.%llx.%x iounit %x\n", - qid.type, qid.path, qid.version, iounit); + qid.type, + (unsigned long long)qid.path, + qid.version, iounit); fid->mode = mode; fid->iounit = iounit; @@ -1023,7 +1030,9 @@ int p9_client_fcreate(struct p9_fid *fid, char *name, u32 perm, int mode, } P9_DPRINTK(P9_DEBUG_9P, "<<< RCREATE qid %x.%llx.%x iounit %x\n", - qid.type, qid.path, qid.version, iounit); + qid.type, + (unsigned long long)qid.path, + qid.version, iounit); fid->mode = mode; fid->iounit = iounit; @@ -1230,9 +1239,9 @@ struct p9_wstat *p9_client_stat(struct p9_fid *fid) "<<< name=%s uid=%s gid=%s muid=%s extension=(%s)\n" "<<< uid=%d gid=%d n_muid=%d\n", ret->size, ret->type, ret->dev, ret->qid.type, - ret->qid.path, ret->qid.version, ret->mode, - ret->atime, ret->mtime, ret->length, ret->name, - ret->uid, ret->gid, ret->muid, ret->extension, + (unsigned long long)ret->qid.path, ret->qid.version, ret->mode, + ret->atime, ret->mtime, (unsigned long long)ret->length, + ret->name, ret->uid, ret->gid, ret->muid, ret->extension, ret->n_uid, ret->n_gid, ret->n_muid); free_and_error: @@ -1255,9 +1264,9 @@ int p9_client_wstat(struct p9_fid *fid, struct p9_wstat *wst) " name=%s uid=%s gid=%s muid=%s extension=(%s)\n" " uid=%d gid=%d n_muid=%d\n", wst->size, wst->type, wst->dev, wst->qid.type, - wst->qid.path, wst->qid.version, wst->mode, - wst->atime, wst->mtime, wst->length, wst->name, - wst->uid, wst->gid, wst->muid, wst->extension, + (unsigned long long)wst->qid.path, wst->qid.version, wst->mode, + wst->atime, wst->mtime, (unsigned long long)wst->length, + wst->name, wst->uid, wst->gid, wst->muid, wst->extension, wst->n_uid, wst->n_gid, wst->n_muid); err = 0; clnt = fid->clnt; diff --git a/net/9p/trans_rdma.c b/net/9p/trans_rdma.c index 8d6cc4777aae..2f1fe5fc1228 100644 --- a/net/9p/trans_rdma.c +++ b/net/9p/trans_rdma.c @@ -45,7 +45,6 @@ #include #include #include -#include #define P9_PORT 5640 #define P9_RDMA_SQ_DEPTH 32 @@ -589,6 +588,9 @@ rdma_create_trans(struct p9_client *client, const char *addr, char *args) if (IS_ERR(rdma->cm_id)) goto error; + /* Associate the client with the transport */ + client->trans = rdma; + /* Resolve the server's address */ rdma->addr.sin_family = AF_INET; rdma->addr.sin_addr.s_addr = in_aton(addr); @@ -669,7 +671,6 @@ rdma_create_trans(struct p9_client *client, const char *addr, char *args) if (err || (rdma->state != P9_RDMA_CONNECTED)) goto error; - client->trans = rdma; client->status = Connected; return 0; diff --git a/net/atm/svc.c b/net/atm/svc.c index de1e4f2f3a43..8fb54dc870b3 100644 --- a/net/atm/svc.c +++ b/net/atm/svc.c @@ -293,7 +293,10 @@ static int svc_listen(struct socket *sock,int backlog) error = -EINVAL; goto out; } - vcc_insert_socket(sk); + if (test_bit(ATM_VF_LISTEN, &vcc->flags)) { + error = -EADDRINUSE; + goto out; + } set_bit(ATM_VF_WAITING, &vcc->flags); prepare_to_wait(sk->sk_sleep, &wait, TASK_UNINTERRUPTIBLE); sigd_enq(vcc,as_listen,NULL,NULL,&vcc->local); @@ -307,6 +310,7 @@ static int svc_listen(struct socket *sock,int backlog) goto out; } set_bit(ATM_VF_LISTEN,&vcc->flags); + vcc_insert_socket(sk); sk->sk_max_ack_backlog = backlog > 0 ? backlog : ATM_BACKLOG_DEFAULT; error = -sk->sk_err; out: diff --git a/net/bridge/br_netfilter.c b/net/bridge/br_netfilter.c index fa5cda4e552a..45f61c348e36 100644 --- a/net/bridge/br_netfilter.c +++ b/net/bridge/br_netfilter.c @@ -101,6 +101,18 @@ static inline __be16 pppoe_proto(const struct sk_buff *skb) pppoe_proto(skb) == htons(PPP_IPV6) && \ brnf_filter_pppoe_tagged) +static void fake_update_pmtu(struct dst_entry *dst, u32 mtu) +{ +} + +static struct dst_ops fake_dst_ops = { + .family = AF_INET, + .protocol = __constant_htons(ETH_P_IP), + .update_pmtu = fake_update_pmtu, + .entry_size = sizeof(struct rtable), + .entries = ATOMIC_INIT(0), +}; + /* * Initialize bogus route table used to keep netfilter happy. * Currently, we fill in the PMTU entry because netfilter @@ -117,6 +129,7 @@ void br_netfilter_rtable_init(struct net_bridge *br) rt->u.dst.path = &rt->u.dst; rt->u.dst.metrics[RTAX_MTU - 1] = 1500; rt->u.dst.flags = DST_NOXFRM; + rt->u.dst.ops = &fake_dst_ops; } static inline struct rtable *bridge_parent_rtable(const struct net_device *dev) diff --git a/net/can/af_can.c b/net/can/af_can.c index 7d4d2b3c137e..3dadb338addd 100644 --- a/net/can/af_can.c +++ b/net/can/af_can.c @@ -319,23 +319,52 @@ static struct dev_rcv_lists *find_dev_rcv_lists(struct net_device *dev) return n ? d : NULL; } +/** + * find_rcv_list - determine optimal filterlist inside device filter struct + * @can_id: pointer to CAN identifier of a given can_filter + * @mask: pointer to CAN mask of a given can_filter + * @d: pointer to the device filter struct + * + * Description: + * Returns the optimal filterlist to reduce the filter handling in the + * receive path. This function is called by service functions that need + * to register or unregister a can_filter in the filter lists. + * + * A filter matches in general, when + * + * & mask == can_id & mask + * + * so every bit set in the mask (even CAN_EFF_FLAG, CAN_RTR_FLAG) describe + * relevant bits for the filter. + * + * The filter can be inverted (CAN_INV_FILTER bit set in can_id) or it can + * filter for error frames (CAN_ERR_FLAG bit set in mask). For error frames + * there is a special filterlist and a special rx path filter handling. + * + * Return: + * Pointer to optimal filterlist for the given can_id/mask pair. + * Constistency checked mask. + * Reduced can_id to have a preprocessed filter compare value. + */ static struct hlist_head *find_rcv_list(canid_t *can_id, canid_t *mask, struct dev_rcv_lists *d) { canid_t inv = *can_id & CAN_INV_FILTER; /* save flag before masking */ - /* filter error frames */ + /* filter for error frames in extra filterlist */ if (*mask & CAN_ERR_FLAG) { - /* clear CAN_ERR_FLAG in list entry */ + /* clear CAN_ERR_FLAG in filter entry */ *mask &= CAN_ERR_MASK; return &d->rx[RX_ERR]; } - /* ensure valid values in can_mask */ - if (*mask & CAN_EFF_FLAG) - *mask &= (CAN_EFF_MASK | CAN_EFF_FLAG | CAN_RTR_FLAG); - else - *mask &= (CAN_SFF_MASK | CAN_RTR_FLAG); + /* with cleared CAN_ERR_FLAG we have a simple mask/value filterpair */ + +#define CAN_EFF_RTR_FLAGS (CAN_EFF_FLAG | CAN_RTR_FLAG) + + /* ensure valid values in can_mask for 'SFF only' frame filtering */ + if ((*mask & CAN_EFF_FLAG) && !(*can_id & CAN_EFF_FLAG)) + *mask &= (CAN_SFF_MASK | CAN_EFF_RTR_FLAGS); /* reduce condition testing at receive time */ *can_id &= *mask; @@ -348,15 +377,19 @@ static struct hlist_head *find_rcv_list(canid_t *can_id, canid_t *mask, if (!(*mask)) return &d->rx[RX_ALL]; - /* use extra filterset for the subscription of exactly *ONE* can_id */ - if (*can_id & CAN_EFF_FLAG) { - if (*mask == (CAN_EFF_MASK | CAN_EFF_FLAG)) { - /* RFC: a use-case for hash-tables in the future? */ - return &d->rx[RX_EFF]; + /* extra filterlists for the subscription of a single non-RTR can_id */ + if (((*mask & CAN_EFF_RTR_FLAGS) == CAN_EFF_RTR_FLAGS) + && !(*can_id & CAN_RTR_FLAG)) { + + if (*can_id & CAN_EFF_FLAG) { + if (*mask == (CAN_EFF_MASK | CAN_EFF_RTR_FLAGS)) { + /* RFC: a future use-case for hash-tables? */ + return &d->rx[RX_EFF]; + } + } else { + if (*mask == (CAN_SFF_MASK | CAN_EFF_RTR_FLAGS)) + return &d->rx_sff[*can_id]; } - } else { - if (*mask == CAN_SFF_MASK) - return &d->rx_sff[*can_id]; } /* default: filter via can_id/can_mask */ @@ -589,7 +622,10 @@ static int can_rcv_filter(struct dev_rcv_lists *d, struct sk_buff *skb) } } - /* check CAN_ID specific entries */ + /* check filterlists for single non-RTR can_ids */ + if (can_id & CAN_RTR_FLAG) + return matches; + if (can_id & CAN_EFF_FLAG) { hlist_for_each_entry_rcu(r, n, &d->rx[RX_EFF], list) { if (r->can_id == can_id) { diff --git a/net/can/bcm.c b/net/can/bcm.c index d0dd382001e2..da0d426c0ce4 100644 --- a/net/can/bcm.c +++ b/net/can/bcm.c @@ -64,10 +64,11 @@ #define BCM_CAN_DLC_MASK 0x0F /* clean private flags in can_dlc by masking */ /* get best masking value for can_rx_register() for a given single can_id */ -#define REGMASK(id) ((id & CAN_RTR_FLAG) | ((id & CAN_EFF_FLAG) ? \ - (CAN_EFF_MASK | CAN_EFF_FLAG) : CAN_SFF_MASK)) +#define REGMASK(id) ((id & CAN_EFF_FLAG) ? \ + (CAN_EFF_MASK | CAN_EFF_FLAG | CAN_RTR_FLAG) : \ + (CAN_SFF_MASK | CAN_EFF_FLAG | CAN_RTR_FLAG)) -#define CAN_BCM_VERSION "20080415" +#define CAN_BCM_VERSION CAN_VERSION static __initdata const char banner[] = KERN_INFO "can: broadcast manager protocol (rev " CAN_BCM_VERSION ")\n"; diff --git a/net/compat.c b/net/compat.c index 67fb6a3834a3..a3a2ba0fac08 100644 --- a/net/compat.c +++ b/net/compat.c @@ -226,14 +226,14 @@ int put_cmsg_compat(struct msghdr *kmsg, int level, int type, int len, void *dat return 0; /* XXX: return error? check spec. */ } - if (level == SOL_SOCKET && type == SO_TIMESTAMP) { + if (level == SOL_SOCKET && type == SCM_TIMESTAMP) { struct timeval *tv = (struct timeval *)data; ctv.tv_sec = tv->tv_sec; ctv.tv_usec = tv->tv_usec; data = &ctv; len = sizeof(ctv); } - if (level == SOL_SOCKET && type == SO_TIMESTAMPNS) { + if (level == SOL_SOCKET && type == SCM_TIMESTAMPNS) { struct timespec *ts = (struct timespec *)data; cts.tv_sec = ts->tv_sec; cts.tv_nsec = ts->tv_nsec; @@ -725,7 +725,7 @@ EXPORT_SYMBOL(compat_mc_getsockopt); static unsigned char nas[19]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), AL(3),AL(3),AL(4),AL(4),AL(4),AL(6), AL(6),AL(2),AL(5),AL(5),AL(3),AL(3), - AL(6)}; + AL(4)}; #undef AL asmlinkage long compat_sys_sendmsg(int fd, struct compat_msghdr __user *msg, unsigned flags) @@ -738,52 +738,13 @@ asmlinkage long compat_sys_recvmsg(int fd, struct compat_msghdr __user *msg, uns return sys_recvmsg(fd, (struct msghdr __user *)msg, flags | MSG_CMSG_COMPAT); } -asmlinkage long compat_sys_paccept(int fd, struct sockaddr __user *upeer_sockaddr, - int __user *upeer_addrlen, - const compat_sigset_t __user *sigmask, - compat_size_t sigsetsize, int flags) -{ - compat_sigset_t ss32; - sigset_t ksigmask, sigsaved; - int ret; - - if (sigmask) { - if (sigsetsize != sizeof(compat_sigset_t)) - return -EINVAL; - if (copy_from_user(&ss32, sigmask, sizeof(ss32))) - return -EFAULT; - sigset_from_compat(&ksigmask, &ss32); - - sigdelsetmask(&ksigmask, sigmask(SIGKILL)|sigmask(SIGSTOP)); - sigprocmask(SIG_SETMASK, &ksigmask, &sigsaved); - } - - ret = do_accept(fd, upeer_sockaddr, upeer_addrlen, flags); - - if (ret == -ERESTARTNOHAND) { - /* - * Don't restore the signal mask yet. Let do_signal() deliver - * the signal on the way back to userspace, before the signal - * mask is restored. - */ - if (sigmask) { - memcpy(¤t->saved_sigmask, &sigsaved, - sizeof(sigsaved)); - set_restore_sigmask(); - } - } else if (sigmask) - sigprocmask(SIG_SETMASK, &sigsaved, NULL); - - return ret; -} - asmlinkage long compat_sys_socketcall(int call, u32 __user *args) { int ret; u32 a[6]; u32 a0, a1; - if (call < SYS_SOCKET || call > SYS_PACCEPT) + if (call < SYS_SOCKET || call > SYS_ACCEPT4) return -EINVAL; if (copy_from_user(a, args, nas[call])) return -EFAULT; @@ -804,7 +765,7 @@ asmlinkage long compat_sys_socketcall(int call, u32 __user *args) ret = sys_listen(a0, a1); break; case SYS_ACCEPT: - ret = do_accept(a0, compat_ptr(a1), compat_ptr(a[2]), 0); + ret = sys_accept4(a0, compat_ptr(a1), compat_ptr(a[2]), 0); break; case SYS_GETSOCKNAME: ret = sys_getsockname(a0, compat_ptr(a1), compat_ptr(a[2])); @@ -844,9 +805,8 @@ asmlinkage long compat_sys_socketcall(int call, u32 __user *args) case SYS_RECVMSG: ret = compat_sys_recvmsg(a0, compat_ptr(a1), a[2]); break; - case SYS_PACCEPT: - ret = compat_sys_paccept(a0, compat_ptr(a1), compat_ptr(a[2]), - compat_ptr(a[3]), a[4], a[5]); + case SYS_ACCEPT4: + ret = sys_accept4(a0, compat_ptr(a1), compat_ptr(a[2]), a[3]); break; default: ret = -EINVAL; diff --git a/net/core/dev.c b/net/core/dev.c index d9038e328cc1..9174c77d3112 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -2218,6 +2218,9 @@ int netif_receive_skb(struct sk_buff *skb) int ret = NET_RX_DROP; __be16 type; + if (skb->vlan_tci && vlan_hwaccel_do_receive(skb)) + return NET_RX_SUCCESS; + /* if we've gotten here through NAPI, check netpoll */ if (netpoll_receive_skb(skb)) return NET_RX_DROP; diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index f1d07b5c1e17..1895a4ca9c4f 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c @@ -325,6 +325,38 @@ void unregister_pernet_subsys(struct pernet_operations *module) } EXPORT_SYMBOL_GPL(unregister_pernet_subsys); +int register_pernet_gen_subsys(int *id, struct pernet_operations *ops) +{ + int rv; + + mutex_lock(&net_mutex); +again: + rv = ida_get_new_above(&net_generic_ids, 1, id); + if (rv < 0) { + if (rv == -EAGAIN) { + ida_pre_get(&net_generic_ids, GFP_KERNEL); + goto again; + } + goto out; + } + rv = register_pernet_operations(first_device, ops); + if (rv < 0) + ida_remove(&net_generic_ids, *id); + mutex_unlock(&net_mutex); +out: + return rv; +} +EXPORT_SYMBOL_GPL(register_pernet_gen_subsys); + +void unregister_pernet_gen_subsys(int id, struct pernet_operations *ops) +{ + mutex_lock(&net_mutex); + unregister_pernet_operations(ops); + ida_remove(&net_generic_ids, id); + mutex_unlock(&net_mutex); +} +EXPORT_SYMBOL_GPL(unregister_pernet_gen_subsys); + /** * register_pernet_device - register a network namespace device * @ops: pernet operations structure for the subsystem diff --git a/net/core/netpoll.c b/net/core/netpoll.c index 6c7af390be0a..dadac6281f20 100644 --- a/net/core/netpoll.c +++ b/net/core/netpoll.c @@ -133,9 +133,11 @@ static int poll_one_napi(struct netpoll_info *npinfo, npinfo->rx_flags |= NETPOLL_RX_DROP; atomic_inc(&trapped); + set_bit(NAPI_STATE_NPSVC, &napi->state); work = napi->poll(napi, budget); + clear_bit(NAPI_STATE_NPSVC, &napi->state); atomic_dec(&trapped); npinfo->rx_flags &= ~NETPOLL_RX_DROP; diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 99f656d35b4f..8997e912aaaf 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -1973,28 +1973,21 @@ static void pktgen_setup_inject(struct pktgen_dev *pkt_dev) /* make sure that we don't pick a non-existing transmit queue */ ntxq = pkt_dev->odev->real_num_tx_queues; - if (ntxq <= num_online_cpus() && (pkt_dev->flags & F_QUEUE_MAP_CPU)) { - printk(KERN_WARNING "pktgen: WARNING: QUEUE_MAP_CPU " - "disabled because CPU count (%d) exceeds number ", - num_online_cpus()); - printk(KERN_WARNING "pktgen: WARNING: of tx queues " - "(%d) on %s \n", ntxq, pkt_dev->odev->name); - pkt_dev->flags &= ~F_QUEUE_MAP_CPU; - } + if (ntxq <= pkt_dev->queue_map_min) { printk(KERN_WARNING "pktgen: WARNING: Requested " - "queue_map_min (%d) exceeds number of tx\n", - pkt_dev->queue_map_min); - printk(KERN_WARNING "pktgen: WARNING: queues (%d) on " - "%s, resetting\n", ntxq, pkt_dev->odev->name); + "queue_map_min (zero-based) (%d) exceeds valid range " + "[0 - %d] for (%d) queues on %s, resetting\n", + pkt_dev->queue_map_min, (ntxq ?: 1)- 1, ntxq, + pkt_dev->odev->name); pkt_dev->queue_map_min = ntxq - 1; } - if (ntxq <= pkt_dev->queue_map_max) { + if (pkt_dev->queue_map_max >= ntxq) { printk(KERN_WARNING "pktgen: WARNING: Requested " - "queue_map_max (%d) exceeds number of tx\n", - pkt_dev->queue_map_max); - printk(KERN_WARNING "pktgen: WARNING: queues (%d) on " - "%s, resetting\n", ntxq, pkt_dev->odev->name); + "queue_map_max (zero-based) (%d) exceeds valid range " + "[0 - %d] for (%d) queues on %s, resetting\n", + pkt_dev->queue_map_max, (ntxq ?: 1)- 1, ntxq, + pkt_dev->odev->name); pkt_dev->queue_map_max = ntxq - 1; } @@ -2203,6 +2196,7 @@ static void set_cur_queue_map(struct pktgen_dev *pkt_dev) } pkt_dev->cur_queue_map = t; } + pkt_dev->cur_queue_map = pkt_dev->cur_queue_map % pkt_dev->odev->real_num_tx_queues; } /* Increment/randomize headers according to flags and current values diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 31f29d2989fd..4dfb6b4d4559 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -878,7 +878,9 @@ static int do_setlink(struct net_device *dev, struct ifinfomsg *ifm, if (ifm->ifi_change) flags = (flags & ifm->ifi_change) | (dev->flags & ~ifm->ifi_change); - dev_change_flags(dev, flags); + err = dev_change_flags(dev, flags); + if (err < 0) + goto errout; } if (tb[IFLA_TXQLEN]) diff --git a/net/core/scm.c b/net/core/scm.c index 10f5c65f6a47..b12303dd39d9 100644 --- a/net/core/scm.c +++ b/net/core/scm.c @@ -106,9 +106,25 @@ void __scm_destroy(struct scm_cookie *scm) if (fpl) { scm->fp = NULL; - for (i=fpl->count-1; i>=0; i--) - fput(fpl->fp[i]); - kfree(fpl); + if (current->scm_work_list) { + list_add_tail(&fpl->list, current->scm_work_list); + } else { + LIST_HEAD(work_list); + + current->scm_work_list = &work_list; + + list_add(&fpl->list, &work_list); + while (!list_empty(&work_list)) { + fpl = list_first_entry(&work_list, struct scm_fp_list, list); + + list_del(&fpl->list); + for (i=fpl->count-1; i>=0; i--) + fput(fpl->fp[i]); + kfree(fpl); + } + + current->scm_work_list = NULL; + } } } diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 4e22e3a35359..65f7757465bd 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -149,7 +149,7 @@ void skb_under_panic(struct sk_buff *skb, int sz, void *here) void skb_truesize_bug(struct sk_buff *skb) { - printk(KERN_ERR "SKB BUG: Invalid truesize (%u) " + WARN(net_ratelimit(), KERN_ERR "SKB BUG: Invalid truesize (%u) " "len=%u, sizeof(sk_buff)=%Zd\n", skb->truesize, skb->len, sizeof(struct sk_buff)); } @@ -449,6 +449,18 @@ void kfree_skb(struct sk_buff *skb) __kfree_skb(skb); } +/** + * skb_recycle_check - check if skb can be reused for receive + * @skb: buffer + * @skb_size: minimum receive buffer size + * + * Checks that the skb passed in is not shared or cloned, and + * that it is linear and its head portion at least as large as + * skb_size so that it can be recycled as a receive buffer. + * If these conditions are met, this function does any necessary + * reference count dropping and cleans up the skbuff as if it + * just came from __alloc_skb(). + */ int skb_recycle_check(struct sk_buff *skb, int skb_size) { struct skb_shared_info *shinfo; @@ -474,8 +486,8 @@ int skb_recycle_check(struct sk_buff *skb, int skb_size) shinfo->frag_list = NULL; memset(skb, 0, offsetof(struct sk_buff, tail)); - skb_reset_tail_pointer(skb); skb->data = skb->head + NET_SKB_PAD; + skb_reset_tail_pointer(skb); return 1; } diff --git a/net/core/sock.c b/net/core/sock.c index 5e2a3132a8c9..edf7220889a4 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -136,7 +136,6 @@ static struct lock_class_key af_family_keys[AF_MAX]; static struct lock_class_key af_family_slock_keys[AF_MAX]; -#ifdef CONFIG_DEBUG_LOCK_ALLOC /* * Make lock validator output more readable. (we pre-construct these * strings build-time, so that runtime initialization of socket @@ -187,7 +186,6 @@ static const char *af_family_clock_key_strings[AF_MAX+1] = { "clock-AF_RXRPC" , "clock-AF_ISDN" , "clock-AF_PHONET" , "clock-AF_MAX" }; -#endif /* * sk_callback_lock locking rules are per-address-family, @@ -2037,9 +2035,6 @@ static inline void release_proto_idx(struct proto *prot) int proto_register(struct proto *prot, int alloc_slab) { - char *request_sock_slab_name = NULL; - char *timewait_sock_slab_name; - if (alloc_slab) { prot->slab = kmem_cache_create(prot->name, prot->obj_size, 0, SLAB_HWCACHE_ALIGN, NULL); @@ -2053,12 +2048,12 @@ int proto_register(struct proto *prot, int alloc_slab) if (prot->rsk_prot != NULL) { static const char mask[] = "request_sock_%s"; - request_sock_slab_name = kmalloc(strlen(prot->name) + sizeof(mask) - 1, GFP_KERNEL); - if (request_sock_slab_name == NULL) + prot->rsk_prot->slab_name = kmalloc(strlen(prot->name) + sizeof(mask) - 1, GFP_KERNEL); + if (prot->rsk_prot->slab_name == NULL) goto out_free_sock_slab; - sprintf(request_sock_slab_name, mask, prot->name); - prot->rsk_prot->slab = kmem_cache_create(request_sock_slab_name, + sprintf(prot->rsk_prot->slab_name, mask, prot->name); + prot->rsk_prot->slab = kmem_cache_create(prot->rsk_prot->slab_name, prot->rsk_prot->obj_size, 0, SLAB_HWCACHE_ALIGN, NULL); @@ -2072,14 +2067,14 @@ int proto_register(struct proto *prot, int alloc_slab) if (prot->twsk_prot != NULL) { static const char mask[] = "tw_sock_%s"; - timewait_sock_slab_name = kmalloc(strlen(prot->name) + sizeof(mask) - 1, GFP_KERNEL); + prot->twsk_prot->twsk_slab_name = kmalloc(strlen(prot->name) + sizeof(mask) - 1, GFP_KERNEL); - if (timewait_sock_slab_name == NULL) + if (prot->twsk_prot->twsk_slab_name == NULL) goto out_free_request_sock_slab; - sprintf(timewait_sock_slab_name, mask, prot->name); + sprintf(prot->twsk_prot->twsk_slab_name, mask, prot->name); prot->twsk_prot->twsk_slab = - kmem_cache_create(timewait_sock_slab_name, + kmem_cache_create(prot->twsk_prot->twsk_slab_name, prot->twsk_prot->twsk_obj_size, 0, SLAB_HWCACHE_ALIGN, NULL); @@ -2095,14 +2090,14 @@ int proto_register(struct proto *prot, int alloc_slab) return 0; out_free_timewait_sock_slab_name: - kfree(timewait_sock_slab_name); + kfree(prot->twsk_prot->twsk_slab_name); out_free_request_sock_slab: if (prot->rsk_prot && prot->rsk_prot->slab) { kmem_cache_destroy(prot->rsk_prot->slab); prot->rsk_prot->slab = NULL; } out_free_request_sock_slab_name: - kfree(request_sock_slab_name); + kfree(prot->rsk_prot->slab_name); out_free_sock_slab: kmem_cache_destroy(prot->slab); prot->slab = NULL; @@ -2125,18 +2120,14 @@ void proto_unregister(struct proto *prot) } if (prot->rsk_prot != NULL && prot->rsk_prot->slab != NULL) { - const char *name = kmem_cache_name(prot->rsk_prot->slab); - kmem_cache_destroy(prot->rsk_prot->slab); - kfree(name); + kfree(prot->rsk_prot->slab_name); prot->rsk_prot->slab = NULL; } if (prot->twsk_prot != NULL && prot->twsk_prot->twsk_slab != NULL) { - const char *name = kmem_cache_name(prot->twsk_prot->twsk_slab); - kmem_cache_destroy(prot->twsk_prot->twsk_slab); - kfree(name); + kfree(prot->twsk_prot->twsk_slab_name); prot->twsk_prot->twsk_slab = NULL; } } diff --git a/net/dsa/slave.c b/net/dsa/slave.c index 37616884b8a9..1af5a79309e9 100644 --- a/net/dsa/slave.c +++ b/net/dsa/slave.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "dsa_priv.h" @@ -49,11 +50,57 @@ void dsa_slave_mii_bus_init(struct dsa_switch *ds) /* slave device handling ****************************************************/ static int dsa_slave_open(struct net_device *dev) { + struct dsa_slave_priv *p = netdev_priv(dev); + struct net_device *master = p->parent->master_netdev; + int err; + + if (!(master->flags & IFF_UP)) + return -ENETDOWN; + + if (compare_ether_addr(dev->dev_addr, master->dev_addr)) { + err = dev_unicast_add(master, dev->dev_addr, ETH_ALEN); + if (err < 0) + goto out; + } + + if (dev->flags & IFF_ALLMULTI) { + err = dev_set_allmulti(master, 1); + if (err < 0) + goto del_unicast; + } + if (dev->flags & IFF_PROMISC) { + err = dev_set_promiscuity(master, 1); + if (err < 0) + goto clear_allmulti; + } + return 0; + +clear_allmulti: + if (dev->flags & IFF_ALLMULTI) + dev_set_allmulti(master, -1); +del_unicast: + if (compare_ether_addr(dev->dev_addr, master->dev_addr)) + dev_unicast_delete(master, dev->dev_addr, ETH_ALEN); +out: + return err; } static int dsa_slave_close(struct net_device *dev) { + struct dsa_slave_priv *p = netdev_priv(dev); + struct net_device *master = p->parent->master_netdev; + + dev_mc_unsync(master, dev); + dev_unicast_unsync(master, dev); + if (dev->flags & IFF_ALLMULTI) + dev_set_allmulti(master, -1); + if (dev->flags & IFF_PROMISC) + dev_set_promiscuity(master, -1); + + if (compare_ether_addr(dev->dev_addr, master->dev_addr)) + dev_unicast_delete(master, dev->dev_addr, ETH_ALEN); + return 0; } @@ -77,9 +124,30 @@ static void dsa_slave_set_rx_mode(struct net_device *dev) dev_unicast_sync(master, dev); } -static int dsa_slave_set_mac_address(struct net_device *dev, void *addr) +static int dsa_slave_set_mac_address(struct net_device *dev, void *a) { - memcpy(dev->dev_addr, addr + 2, 6); + struct dsa_slave_priv *p = netdev_priv(dev); + struct net_device *master = p->parent->master_netdev; + struct sockaddr *addr = a; + int err; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + if (!(dev->flags & IFF_UP)) + goto out; + + if (compare_ether_addr(addr->sa_data, master->dev_addr)) { + err = dev_unicast_add(master, addr->sa_data, ETH_ALEN); + if (err < 0) + return err; + } + + if (compare_ether_addr(dev->dev_addr, master->dev_addr)) + dev_unicast_delete(master, dev->dev_addr, ETH_ALEN); + +out: + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); return 0; } diff --git a/net/dsa/tag_dsa.c b/net/dsa/tag_dsa.c index bdc0510b53b7..31866543332e 100644 --- a/net/dsa/tag_dsa.c +++ b/net/dsa/tag_dsa.c @@ -159,6 +159,7 @@ static int dsa_rcv(struct sk_buff *skb, struct net_device *dev, skb->dev = ds->ports[source_port]; skb_push(skb, ETH_HLEN); + skb->pkt_type = PACKET_HOST; skb->protocol = eth_type_trans(skb, skb->dev); skb->dev->last_rx = jiffies; diff --git a/net/dsa/tag_edsa.c b/net/dsa/tag_edsa.c index f985ea993843..9f4ce55eae59 100644 --- a/net/dsa/tag_edsa.c +++ b/net/dsa/tag_edsa.c @@ -178,6 +178,7 @@ static int edsa_rcv(struct sk_buff *skb, struct net_device *dev, skb->dev = ds->ports[source_port]; skb_push(skb, ETH_HLEN); + skb->pkt_type = PACKET_HOST; skb->protocol = eth_type_trans(skb, skb->dev); skb->dev->last_rx = jiffies; diff --git a/net/dsa/tag_trailer.c b/net/dsa/tag_trailer.c index d3117764b2c2..efd26697e716 100644 --- a/net/dsa/tag_trailer.c +++ b/net/dsa/tag_trailer.c @@ -95,6 +95,7 @@ static int trailer_rcv(struct sk_buff *skb, struct net_device *dev, skb->dev = ds->ports[source_port]; skb_push(skb, ETH_HLEN); + skb->pkt_type = PACKET_HOST; skb->protocol = eth_type_trans(skb, skb->dev); skb->dev->last_rx = jiffies; diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 1fbff5fa4241..1aa2dc9e380e 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -1117,6 +1117,7 @@ int inet_sk_rebuild_header(struct sock *sk) }, }, .proto = sk->sk_protocol, + .flags = inet_sk_flowi_flags(sk), .uli_u = { .ports = { .sport = inet->sport, diff --git a/net/ipv4/cipso_ipv4.c b/net/ipv4/cipso_ipv4.c index 490e035c6d90..2e78f6bd9775 100644 --- a/net/ipv4/cipso_ipv4.c +++ b/net/ipv4/cipso_ipv4.c @@ -2063,9 +2063,10 @@ int cipso_v4_skbuff_setattr(struct sk_buff *skb, u32 opt_len; int len_delta; - buf_len = cipso_v4_genopt(buf, buf_len, doi_def, secattr); - if (buf_len < 0) - return buf_len; + ret_val = cipso_v4_genopt(buf, buf_len, doi_def, secattr); + if (ret_val < 0) + return ret_val; + buf_len = ret_val; opt_len = (buf_len + 3) & ~3; /* we overwrite any existing options to ensure that we have enough diff --git a/net/ipv4/ip_input.c b/net/ipv4/ip_input.c index 861978a4f1a8..cfb38ac9d698 100644 --- a/net/ipv4/ip_input.c +++ b/net/ipv4/ip_input.c @@ -209,9 +209,17 @@ static int ip_local_deliver_finish(struct sk_buff *skb) hash = protocol & (MAX_INET_PROTOS - 1); ipprot = rcu_dereference(inet_protos[hash]); - if (ipprot != NULL && (net == &init_net || ipprot->netns_ok)) { + if (ipprot != NULL) { int ret; + if (!net_eq(net, &init_net) && !ipprot->netns_ok) { + if (net_ratelimit()) + printk("%s: proto %d isn't netns-ready\n", + __func__, protocol); + kfree_skb(skb); + goto out; + } + if (!ipprot->no_policy) { if (!xfrm4_policy_check(NULL, XFRM_POLICY_IN, skb)) { kfree_skb(skb); diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index b42e082cc170..25924b1eb2ef 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -1945,13 +1945,14 @@ int __init ip_mr_init(void) goto proc_cache_fail; #endif return 0; -reg_notif_fail: - kmem_cache_destroy(mrt_cachep); #ifdef CONFIG_PROC_FS -proc_vif_fail: - unregister_netdevice_notifier(&ip_mr_notifier); proc_cache_fail: proc_net_remove(&init_net, "ip_mr_vif"); +proc_vif_fail: + unregister_netdevice_notifier(&ip_mr_notifier); #endif +reg_notif_fail: + del_timer(&ipmr_expire_timer); + kmem_cache_destroy(mrt_cachep); return err; } diff --git a/net/ipv4/netfilter/nf_nat_rule.c b/net/ipv4/netfilter/nf_nat_rule.c index bea54a685109..8d489e746b21 100644 --- a/net/ipv4/netfilter/nf_nat_rule.c +++ b/net/ipv4/netfilter/nf_nat_rule.c @@ -61,7 +61,7 @@ static struct static struct xt_table nat_table = { .name = "nat", .valid_hooks = NAT_VALID_HOOKS, - .lock = __RW_LOCK_UNLOCKED(__nat_table.lock), + .lock = __RW_LOCK_UNLOCKED(nat_table.lock), .me = THIS_MODULE, .af = AF_INET, }; diff --git a/net/ipv4/proc.c b/net/ipv4/proc.c index 8f5a403f6f6b..a631a1f110ca 100644 --- a/net/ipv4/proc.c +++ b/net/ipv4/proc.c @@ -237,43 +237,45 @@ static const struct snmp_mib snmp4_net_list[] = { SNMP_MIB_SENTINEL }; +static void icmpmsg_put_line(struct seq_file *seq, unsigned long *vals, + unsigned short *type, int count) +{ + int j; + + if (count) { + seq_printf(seq, "\nIcmpMsg:"); + for (j = 0; j < count; ++j) + seq_printf(seq, " %sType%u", + type[j] & 0x100 ? "Out" : "In", + type[j] & 0xff); + seq_printf(seq, "\nIcmpMsg:"); + for (j = 0; j < count; ++j) + seq_printf(seq, " %lu", vals[j]); + } +} + static void icmpmsg_put(struct seq_file *seq) { #define PERLINE 16 - int j, i, count; - static int out[PERLINE]; + int i, count; + unsigned short type[PERLINE]; + unsigned long vals[PERLINE], val; struct net *net = seq->private; count = 0; for (i = 0; i < ICMPMSG_MIB_MAX; i++) { - - if (snmp_fold_field((void **) net->mib.icmpmsg_statistics, i)) - out[count++] = i; - if (count < PERLINE) - continue; - - seq_printf(seq, "\nIcmpMsg:"); - for (j = 0; j < PERLINE; ++j) - seq_printf(seq, " %sType%u", i & 0x100 ? "Out" : "In", - i & 0xff); - seq_printf(seq, "\nIcmpMsg: "); - for (j = 0; j < PERLINE; ++j) - seq_printf(seq, " %lu", - snmp_fold_field((void **) net->mib.icmpmsg_statistics, - out[j])); - seq_putc(seq, '\n'); - } - if (count) { - seq_printf(seq, "\nIcmpMsg:"); - for (j = 0; j < count; ++j) - seq_printf(seq, " %sType%u", out[j] & 0x100 ? "Out" : - "In", out[j] & 0xff); - seq_printf(seq, "\nIcmpMsg:"); - for (j = 0; j < count; ++j) - seq_printf(seq, " %lu", snmp_fold_field((void **) - net->mib.icmpmsg_statistics, out[j])); + val = snmp_fold_field((void **) net->mib.icmpmsg_statistics, i); + if (val) { + type[count] = i; + vals[count++] = val; + } + if (count == PERLINE) { + icmpmsg_put_line(seq, vals, type, count); + count = 0; + } } + icmpmsg_put_line(seq, vals, type, count); #undef PERLINE } diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index eccb7165a80c..c5aca0bb116a 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -1374,8 +1374,7 @@ int tcp_recvmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, sk->sk_state == TCP_CLOSE || (sk->sk_shutdown & RCV_SHUTDOWN) || !timeo || - signal_pending(current) || - (flags & MSG_PEEK)) + signal_pending(current)) break; } else { if (sock_flag(sk, SOCK_DONE)) diff --git a/net/ipv4/tcp_htcp.c b/net/ipv4/tcp_htcp.c index af99776146ff..937549b8a921 100644 --- a/net/ipv4/tcp_htcp.c +++ b/net/ipv4/tcp_htcp.c @@ -69,9 +69,12 @@ static u32 htcp_cwnd_undo(struct sock *sk) const struct tcp_sock *tp = tcp_sk(sk); struct htcp *ca = inet_csk_ca(sk); - ca->last_cong = ca->undo_last_cong; - ca->maxRTT = ca->undo_maxRTT; - ca->old_maxB = ca->undo_old_maxB; + if (ca->undo_last_cong) { + ca->last_cong = ca->undo_last_cong; + ca->maxRTT = ca->undo_maxRTT; + ca->old_maxB = ca->undo_old_maxB; + ca->undo_last_cong = 0; + } return max(tp->snd_cwnd, (tp->snd_ssthresh << 7) / ca->beta); } @@ -268,7 +271,10 @@ static void htcp_state(struct sock *sk, u8 new_state) case TCP_CA_Open: { struct htcp *ca = inet_csk_ca(sk); - ca->last_cong = jiffies; + if (ca->undo_last_cong) { + ca->last_cong = jiffies; + ca->undo_last_cong = 0; + } } break; case TCP_CA_CWR: diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index e4c5ac9fe89b..fe3b4bdfd251 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -1028,10 +1028,6 @@ unsigned int tcp_sync_mss(struct sock *sk, u32 pmtu) /* Compute the current effective MSS, taking SACKs and IP options, * and even PMTU discovery events into account. - * - * LARGESEND note: !tcp_urg_mode is overkill, only frames up to snd_up - * cannot be large. However, taking into account rare use of URG, this - * is not a big flaw. */ unsigned int tcp_current_mss(struct sock *sk, int large_allowed) { @@ -1046,7 +1042,7 @@ unsigned int tcp_current_mss(struct sock *sk, int large_allowed) mss_now = tp->mss_cache; - if (large_allowed && sk_can_gso(sk) && !tcp_urg_mode(tp)) + if (large_allowed && sk_can_gso(sk)) doing_tso = 1; if (dst) { @@ -1516,6 +1512,10 @@ static int tcp_mtu_probe(struct sock *sk) * send_head. This happens as incoming acks open up the remote * window for us. * + * LARGESEND note: !tcp_urg_mode is overkill, only frames between + * snd_up-64k-mss .. snd_up cannot be large. However, taking into + * account rare use of URG, this is not a big flaw. + * * Returns 1, if no segments are in flight and we have queued segments, but * cannot send anything now because of SWS or another problem. */ @@ -1567,7 +1567,7 @@ static int tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle) } limit = mss_now; - if (tso_segs > 1) + if (tso_segs > 1 && !tcp_urg_mode(tp)) limit = tcp_mss_split_point(sk, skb, mss_now, cwnd_quota); @@ -1616,6 +1616,7 @@ void __tcp_push_pending_frames(struct sock *sk, unsigned int cur_mss, */ void tcp_push_one(struct sock *sk, unsigned int mss_now) { + struct tcp_sock *tp = tcp_sk(sk); struct sk_buff *skb = tcp_send_head(sk); unsigned int tso_segs, cwnd_quota; @@ -1630,7 +1631,7 @@ void tcp_push_one(struct sock *sk, unsigned int mss_now) BUG_ON(!tso_segs); limit = mss_now; - if (tso_segs > 1) + if (tso_segs > 1 && !tcp_urg_mode(tp)) limit = tcp_mss_split_point(sk, skb, mss_now, cwnd_quota); @@ -2279,6 +2280,11 @@ struct sk_buff *tcp_make_synack(struct sock *sk, struct dst_entry *dst, } memset(&opts, 0, sizeof(opts)); +#ifdef CONFIG_SYN_COOKIES + if (unlikely(req->cookie_ts)) + TCP_SKB_CB(skb)->when = cookie_init_timestamp(req); + else +#endif TCP_SKB_CB(skb)->when = tcp_time_stamp; tcp_header_size = tcp_synack_options(sk, req, mss, skb, &opts, &md5) + @@ -2304,11 +2310,6 @@ struct sk_buff *tcp_make_synack(struct sock *sk, struct dst_entry *dst, /* RFC1323: The window in SYN & SYN/ACK segments is never scaled. */ th->window = htons(min(req->rcv_wnd, 65535U)); -#ifdef CONFIG_SYN_COOKIES - if (unlikely(req->cookie_ts)) - TCP_SKB_CB(skb)->when = cookie_init_timestamp(req); - else -#endif tcp_options_write((__be32 *)(th + 1), tp, &opts, &md5_hash_location); th->doff = (tcp_header_size >> 2); TCP_INC_STATS(sock_net(sk), TCP_MIB_OUTSEGS); diff --git a/net/ipv4/tcp_vegas.c b/net/ipv4/tcp_vegas.c index 14504dada116..a453aac91bd3 100644 --- a/net/ipv4/tcp_vegas.c +++ b/net/ipv4/tcp_vegas.c @@ -40,18 +40,14 @@ #include "tcp_vegas.h" -/* Default values of the Vegas variables, in fixed-point representation - * with V_PARAM_SHIFT bits to the right of the binary point. - */ -#define V_PARAM_SHIFT 1 -static int alpha = 2<beg_snd_nxt)) { /* Do the Vegas once-per-RTT cwnd adjustment. */ - u32 old_wnd, old_snd_cwnd; - - - /* Here old_wnd is essentially the window of data that was - * sent during the previous RTT, and has all - * been acknowledged in the course of the RTT that ended - * with the ACK we just received. Likewise, old_snd_cwnd - * is the cwnd during the previous RTT. - */ - old_wnd = (vegas->beg_snd_nxt - vegas->beg_snd_una) / - tp->mss_cache; - old_snd_cwnd = vegas->beg_snd_cwnd; /* Save the extent of the current window so we can use this * at the end of the next RTT. */ - vegas->beg_snd_una = vegas->beg_snd_nxt; vegas->beg_snd_nxt = tp->snd_nxt; - vegas->beg_snd_cwnd = tp->snd_cwnd; /* We do the Vegas calculations only if we got enough RTT * samples that we can be reasonably sure that we got @@ -252,22 +212,14 @@ static void tcp_vegas_cong_avoid(struct sock *sk, u32 ack, u32 in_flight) * * This is: * (actual rate in segments) * baseRTT - * We keep it as a fixed point number with - * V_PARAM_SHIFT bits to the right of the binary point. */ - target_cwnd = ((u64)old_wnd * vegas->baseRTT); - target_cwnd <<= V_PARAM_SHIFT; - do_div(target_cwnd, rtt); + target_cwnd = tp->snd_cwnd * vegas->baseRTT / rtt; /* Calculate the difference between the window we had, * and the window we would like to have. This quantity * is the "Diff" from the Arizona Vegas papers. - * - * Again, this is a fixed point number with - * V_PARAM_SHIFT bits to the right of the binary - * point. */ - diff = (old_wnd << V_PARAM_SHIFT) - target_cwnd; + diff = tp->snd_cwnd * (rtt-vegas->baseRTT) / vegas->baseRTT; if (diff > gamma && tp->snd_ssthresh > 2 ) { /* Going too fast. Time to slow down @@ -282,16 +234,13 @@ static void tcp_vegas_cong_avoid(struct sock *sk, u32 ack, u32 in_flight) * truncation robs us of full link * utilization. */ - tp->snd_cwnd = min(tp->snd_cwnd, - ((u32)target_cwnd >> - V_PARAM_SHIFT)+1); + tp->snd_cwnd = min(tp->snd_cwnd, (u32)target_cwnd+1); } else if (tp->snd_cwnd <= tp->snd_ssthresh) { /* Slow start. */ tcp_slow_start(tp); } else { /* Congestion avoidance. */ - u32 next_snd_cwnd; /* Figure out where we would like cwnd * to be. @@ -300,32 +249,25 @@ static void tcp_vegas_cong_avoid(struct sock *sk, u32 ack, u32 in_flight) /* The old window was too fast, so * we slow down. */ - next_snd_cwnd = old_snd_cwnd - 1; + tp->snd_cwnd--; } else if (diff < alpha) { /* We don't have enough extra packets * in the network, so speed up. */ - next_snd_cwnd = old_snd_cwnd + 1; + tp->snd_cwnd++; } else { /* Sending just as fast as we * should be. */ - next_snd_cwnd = old_snd_cwnd; } - - /* Adjust cwnd upward or downward, toward the - * desired value. - */ - if (next_snd_cwnd > tp->snd_cwnd) - tp->snd_cwnd++; - else if (next_snd_cwnd < tp->snd_cwnd) - tp->snd_cwnd--; } if (tp->snd_cwnd < 2) tp->snd_cwnd = 2; else if (tp->snd_cwnd > tp->snd_cwnd_clamp) tp->snd_cwnd = tp->snd_cwnd_clamp; + + tp->snd_ssthresh = tcp_current_ssthresh(sk); } /* Wipe the slate clean for the next RTT. */ diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c index 2095abc3caba..98c1fd09be88 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -284,7 +284,7 @@ struct sock *udp4_lib_lookup(struct net *net, __be32 saddr, __be16 sport, } EXPORT_SYMBOL_GPL(udp4_lib_lookup); -static inline struct sock *udp_v4_mcast_next(struct sock *sk, +static inline struct sock *udp_v4_mcast_next(struct net *net, struct sock *sk, __be16 loc_port, __be32 loc_addr, __be16 rmt_port, __be32 rmt_addr, int dif) @@ -296,7 +296,8 @@ static inline struct sock *udp_v4_mcast_next(struct sock *sk, sk_for_each_from(s, node) { struct inet_sock *inet = inet_sk(s); - if (s->sk_hash != hnum || + if (!net_eq(sock_net(s), net) || + s->sk_hash != hnum || (inet->daddr && inet->daddr != rmt_addr) || (inet->dport != rmt_port && inet->dport) || (inet->rcv_saddr && inet->rcv_saddr != loc_addr) || @@ -632,6 +633,7 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, .saddr = saddr, .tos = tos } }, .proto = sk->sk_protocol, + .flags = inet_sk_flowi_flags(sk), .uli_u = { .ports = { .sport = inet->sport, .dport = dport } } }; @@ -1079,15 +1081,16 @@ static int __udp4_lib_mcast_deliver(struct net *net, struct sk_buff *skb, read_lock(&udp_hash_lock); sk = sk_head(&udptable[udp_hashfn(net, ntohs(uh->dest))]); dif = skb->dev->ifindex; - sk = udp_v4_mcast_next(sk, uh->dest, daddr, uh->source, saddr, dif); + sk = udp_v4_mcast_next(net, sk, uh->dest, daddr, uh->source, saddr, dif); if (sk) { struct sock *sknext = NULL; do { struct sk_buff *skb1 = skb; - sknext = udp_v4_mcast_next(sk_next(sk), uh->dest, daddr, - uh->source, saddr, dif); + sknext = udp_v4_mcast_next(net, sk_next(sk), uh->dest, + daddr, uh->source, saddr, + dif); if (sknext) skb1 = skb_clone(skb, GFP_ATOMIC); diff --git a/net/ipv4/xfrm4_state.c b/net/ipv4/xfrm4_state.c index 07735ed280d7..55dc6beab9aa 100644 --- a/net/ipv4/xfrm4_state.c +++ b/net/ipv4/xfrm4_state.c @@ -33,6 +33,7 @@ __xfrm4_init_tempsel(struct xfrm_state *x, struct flowi *fl, x->sel.dport_mask = htons(0xffff); x->sel.sport = xfrm_flowi_sport(fl); x->sel.sport_mask = htons(0xffff); + x->sel.family = AF_INET; x->sel.prefixlen_d = 32; x->sel.prefixlen_s = 32; x->sel.proto = fl->proto; diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index eea9542728ca..d9da5eb9dcb2 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -2483,8 +2483,10 @@ static int addrconf_notify(struct notifier_block *this, unsigned long event, if (!idev && dev->mtu >= IPV6_MIN_MTU) idev = ipv6_add_dev(dev); - if (idev) + if (idev) { idev->if_flags |= IF_READY; + run_pending = 1; + } } else { if (!addrconf_qdisc_ok(dev)) { /* device is still not ready. */ diff --git a/net/ipv6/datagram.c b/net/ipv6/datagram.c index 410046a8cc91..e44deb8d4df2 100644 --- a/net/ipv6/datagram.c +++ b/net/ipv6/datagram.c @@ -661,6 +661,11 @@ int datagram_send_ctl(struct net *net, switch (rthdr->type) { #if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) case IPV6_SRCRT_TYPE_2: + if (rthdr->hdrlen != 2 || + rthdr->segments_left != 1) { + err = -EINVAL; + goto exit_f; + } break; #endif default: diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index 182f8a177e7f..0524769632e7 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -224,7 +224,7 @@ static struct file_operations ip6mr_vif_fops = { .open = ip6mr_vif_open, .read = seq_read, .llseek = seq_lseek, - .release = seq_release, + .release = seq_release_private, }; static void *ipmr_mfc_seq_start(struct seq_file *seq, loff_t *pos) @@ -338,7 +338,7 @@ static struct file_operations ip6mr_mfc_fops = { .open = ipmr_mfc_open, .read = seq_read, .llseek = seq_lseek, - .release = seq_release, + .release = seq_release_private, }; #endif @@ -981,14 +981,15 @@ int __init ip6_mr_init(void) goto proc_cache_fail; #endif return 0; -reg_notif_fail: - kmem_cache_destroy(mrt_cachep); #ifdef CONFIG_PROC_FS -proc_vif_fail: - unregister_netdevice_notifier(&ip6_mr_notifier); proc_cache_fail: proc_net_remove(&init_net, "ip6_mr_vif"); +proc_vif_fail: + unregister_netdevice_notifier(&ip6_mr_notifier); #endif +reg_notif_fail: + del_timer(&ipmr_expire_timer); + kmem_cache_destroy(mrt_cachep); return err; } diff --git a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c index 4e5eac301f91..2aa294be0c79 100644 --- a/net/ipv6/ipv6_sockglue.c +++ b/net/ipv6/ipv6_sockglue.c @@ -366,11 +366,16 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, } /* routing header option needs extra check */ + retv = -EINVAL; if (optname == IPV6_RTHDR && opt && opt->srcrt) { struct ipv6_rt_hdr *rthdr = opt->srcrt; switch (rthdr->type) { #if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) case IPV6_SRCRT_TYPE_2: + if (rthdr->hdrlen != 2 || + rthdr->segments_left != 1) + goto sticky_done; + break; #endif default: diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 172438320eec..d0f54d18e19b 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -912,8 +912,13 @@ static void ndisc_recv_na(struct sk_buff *skb) is invalid, but ndisc specs say nothing about it. It could be misconfiguration, or an smart proxy agent tries to help us :-) + + We should not print the error if NA has been + received from loopback - it is just our own + unsolicited advertisement. */ - ND_PRINTK1(KERN_WARNING + if (skb->pkt_type != PACKET_LOOPBACK) + ND_PRINTK1(KERN_WARNING "ICMPv6 NA: someone advertises our address on %s!\n", ifp->idev->dev->name); in6_ifa_put(ifp); diff --git a/net/ipv6/proc.c b/net/ipv6/proc.c index 07f0b76e7427..97c17fdd6f75 100644 --- a/net/ipv6/proc.c +++ b/net/ipv6/proc.c @@ -132,7 +132,7 @@ static struct snmp_mib snmp6_udplite6_list[] = { static void snmp6_seq_show_icmpv6msg(struct seq_file *seq, void **mib) { - static char name[32]; + char name[32]; int i; /* print by name -- deprecated items */ @@ -144,7 +144,7 @@ static void snmp6_seq_show_icmpv6msg(struct seq_file *seq, void **mib) p = icmp6type2name[icmptype]; if (!p) /* don't print un-named types here */ continue; - (void) snprintf(name, sizeof(name)-1, "Icmp6%s%s", + snprintf(name, sizeof(name), "Icmp6%s%s", i & 0x100 ? "Out" : "In", p); seq_printf(seq, "%-32s\t%lu\n", name, snmp_fold_field(mib, i)); @@ -157,7 +157,7 @@ static void snmp6_seq_show_icmpv6msg(struct seq_file *seq, void **mib) val = snmp_fold_field(mib, i); if (!val) continue; - (void) snprintf(name, sizeof(name)-1, "Icmp6%sType%u", + snprintf(name, sizeof(name), "Icmp6%sType%u", i & 0x100 ? "Out" : "In", i & 0xff); seq_printf(seq, "%-32s\t%lu\n", name, val); } diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index e51da8c092fa..8b48512ebf6a 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -138,6 +138,7 @@ int udpv6_recvmsg(struct kiocb *iocb, struct sock *sk, int peeked; int err; int is_udplite = IS_UDPLITE(sk); + int is_udp4; if (addr_len) *addr_len=sizeof(struct sockaddr_in6); @@ -158,6 +159,8 @@ try_again: else if (copied < ulen) msg->msg_flags |= MSG_TRUNC; + is_udp4 = (skb->protocol == htons(ETH_P_IP)); + /* * If checksum is needed at all, try to do it while copying the * data. If the data is truncated, or if we only want a partial @@ -180,9 +183,14 @@ try_again: if (err) goto out_free; - if (!peeked) - UDP6_INC_STATS_USER(sock_net(sk), - UDP_MIB_INDATAGRAMS, is_udplite); + if (!peeked) { + if (is_udp4) + UDP_INC_STATS_USER(sock_net(sk), + UDP_MIB_INDATAGRAMS, is_udplite); + else + UDP6_INC_STATS_USER(sock_net(sk), + UDP_MIB_INDATAGRAMS, is_udplite); + } sock_recv_timestamp(msg, sk, skb); @@ -196,7 +204,7 @@ try_again: sin6->sin6_flowinfo = 0; sin6->sin6_scope_id = 0; - if (skb->protocol == htons(ETH_P_IP)) + if (is_udp4) ipv6_addr_set(&sin6->sin6_addr, 0, 0, htonl(0xffff), ip_hdr(skb)->saddr); else { @@ -207,7 +215,7 @@ try_again: } } - if (skb->protocol == htons(ETH_P_IP)) { + if (is_udp4) { if (inet->cmsg_flags) ip_cmsg_recv(msg, skb); } else { @@ -228,8 +236,14 @@ out: csum_copy_err: lock_sock(sk); - if (!skb_kill_datagram(sk, skb, flags)) - UDP6_INC_STATS_USER(sock_net(sk), UDP_MIB_INERRORS, is_udplite); + if (!skb_kill_datagram(sk, skb, flags)) { + if (is_udp4) + UDP_INC_STATS_USER(sock_net(sk), + UDP_MIB_INERRORS, is_udplite); + else + UDP6_INC_STATS_USER(sock_net(sk), + UDP_MIB_INERRORS, is_udplite); + } release_sock(sk); if (flags & MSG_DONTWAIT) @@ -328,7 +342,7 @@ drop: return -1; } -static struct sock *udp_v6_mcast_next(struct sock *sk, +static struct sock *udp_v6_mcast_next(struct net *net, struct sock *sk, __be16 loc_port, struct in6_addr *loc_addr, __be16 rmt_port, struct in6_addr *rmt_addr, int dif) @@ -340,7 +354,7 @@ static struct sock *udp_v6_mcast_next(struct sock *sk, sk_for_each_from(s, node) { struct inet_sock *inet = inet_sk(s); - if (sock_net(s) != sock_net(sk)) + if (!net_eq(sock_net(s), net)) continue; if (s->sk_hash == num && s->sk_family == PF_INET6) { @@ -383,14 +397,14 @@ static int __udp6_lib_mcast_deliver(struct net *net, struct sk_buff *skb, read_lock(&udp_hash_lock); sk = sk_head(&udptable[udp_hashfn(net, ntohs(uh->dest))]); dif = inet6_iif(skb); - sk = udp_v6_mcast_next(sk, uh->dest, daddr, uh->source, saddr, dif); + sk = udp_v6_mcast_next(net, sk, uh->dest, daddr, uh->source, saddr, dif); if (!sk) { kfree_skb(skb); goto out; } sk2 = sk; - while ((sk2 = udp_v6_mcast_next(sk_next(sk2), uh->dest, daddr, + while ((sk2 = udp_v6_mcast_next(net, sk_next(sk2), uh->dest, daddr, uh->source, saddr, dif))) { struct sk_buff *buff = skb_clone(skb, GFP_ATOMIC); if (buff) { diff --git a/net/ipv6/xfrm6_state.c b/net/ipv6/xfrm6_state.c index 89884a4f23aa..60c78cfc2737 100644 --- a/net/ipv6/xfrm6_state.c +++ b/net/ipv6/xfrm6_state.c @@ -34,6 +34,7 @@ __xfrm6_init_tempsel(struct xfrm_state *x, struct flowi *fl, x->sel.dport_mask = htons(0xffff); x->sel.sport = xfrm_flowi_sport(fl); x->sel.sport_mask = htons(0xffff); + x->sel.family = AF_INET6; x->sel.prefixlen_d = 128; x->sel.prefixlen_s = 128; x->sel.proto = fl->proto; diff --git a/net/key/af_key.c b/net/key/af_key.c index e55e0441e4d9..5b22e011653b 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -2075,7 +2075,6 @@ static int pfkey_xfrm_policy2msg(struct sk_buff *skb, struct xfrm_policy *xp, in req_size += socklen * 2; } else { size -= 2*socklen; - socklen = 0; } rq = (void*)skb_put(skb, req_size); pol->sadb_x_policy_len += req_size/8; @@ -3189,6 +3188,7 @@ static struct xfrm_policy *pfkey_compile_policy(struct sock *sk, int opt, return xp; out: + xp->walk.dead = 1; xfrm_policy_destroy(xp); return NULL; } diff --git a/net/mac80211/debugfs_sta.c b/net/mac80211/debugfs_sta.c index 189d0bafa91a..b85c4f27b361 100644 --- a/net/mac80211/debugfs_sta.c +++ b/net/mac80211/debugfs_sta.c @@ -199,7 +199,7 @@ static ssize_t sta_agg_status_write(struct file *file, /* toggle Rx aggregation command */ tid_num = tid_num - 100; if (tid_static_rx[tid_num] == 1) { - strcpy(state, "off "); + strcpy(state, "off"); ieee80211_sta_stop_rx_ba_session(sta->sdata, da, tid_num, 0, WLAN_REASON_QSTA_REQUIRE_SETUP); sta->ampdu_mlme.tid_state_rx[tid_num] |= diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 87665d7bb4f9..409bb7716236 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -2560,25 +2560,3 @@ void ieee80211_mlme_notify_scan_completed(struct ieee80211_local *local) ieee80211_restart_sta_timer(sdata); rcu_read_unlock(); } - -/* driver notification call */ -void ieee80211_notify_mac(struct ieee80211_hw *hw, - enum ieee80211_notification_types notif_type) -{ - struct ieee80211_local *local = hw_to_local(hw); - struct ieee80211_sub_if_data *sdata; - - switch (notif_type) { - case IEEE80211_NOTIFY_RE_ASSOC: - rcu_read_lock(); - list_for_each_entry_rcu(sdata, &local->interfaces, list) { - if (sdata->vif.type != NL80211_IFTYPE_STATION) - continue; - - ieee80211_sta_req_auth(sdata, &sdata->u.sta); - } - rcu_read_unlock(); - break; - } -} -EXPORT_SYMBOL(ieee80211_notify_mac); diff --git a/net/mac80211/rc80211_minstrel_debugfs.c b/net/mac80211/rc80211_minstrel_debugfs.c index 0b024cd6b809..98f480708050 100644 --- a/net/mac80211/rc80211_minstrel_debugfs.c +++ b/net/mac80211/rc80211_minstrel_debugfs.c @@ -94,8 +94,8 @@ minstrel_stats_open(struct inode *inode, struct file *file) prob / 10, prob % 10, mr->last_success, mr->last_attempts, - mr->succ_hist, - mr->att_hist); + (unsigned long long)mr->succ_hist, + (unsigned long long)mr->att_hist); } p += sprintf(p, "\nTotal packet count:: ideal %d " "lookaround %d\n\n", @@ -106,7 +106,7 @@ minstrel_stats_open(struct inode *inode, struct file *file) return 0; } -static int +static ssize_t minstrel_stats_read(struct file *file, char __user *buf, size_t len, loff_t *o) { struct minstrel_stats_info *ms; diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c index 7fef8ea1f5ec..d254446b85b5 100644 --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c @@ -99,7 +99,7 @@ struct sta_info *sta_info_get(struct ieee80211_local *local, const u8 *addr) sta = rcu_dereference(local->sta_hash[STA_HASH(addr)]); while (sta) { - if (compare_ether_addr(sta->sta.addr, addr) == 0) + if (memcmp(sta->sta.addr, addr, ETH_ALEN) == 0) break; sta = rcu_dereference(sta->hnext); } diff --git a/net/mac80211/wext.c b/net/mac80211/wext.c index 742f811ca416..ab4ddba874be 100644 --- a/net/mac80211/wext.c +++ b/net/mac80211/wext.c @@ -271,6 +271,7 @@ static int ieee80211_ioctl_siwmode(struct net_device *dev, __u32 *mode, char *extra) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; int type; if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) @@ -281,6 +282,13 @@ static int ieee80211_ioctl_siwmode(struct net_device *dev, type = NL80211_IFTYPE_STATION; break; case IW_MODE_ADHOC: + /* Setting ad-hoc mode on non ibss channel is not + * supported. + */ + if (local->oper_channel && + (local->oper_channel->flags & IEEE80211_CHAN_NO_IBSS)) + return -EOPNOTSUPP; + type = NL80211_IFTYPE_ADHOC; break; case IW_MODE_REPEAT: diff --git a/net/netfilter/ipvs/ip_vs_xmit.c b/net/netfilter/ipvs/ip_vs_xmit.c index 02ddc2b3ce2e..e90d52f199bc 100644 --- a/net/netfilter/ipvs/ip_vs_xmit.c +++ b/net/netfilter/ipvs/ip_vs_xmit.c @@ -713,7 +713,8 @@ ip_vs_tunnel_xmit_v6(struct sk_buff *skb, struct ip_vs_conn *cp, iph = ipv6_hdr(skb); iph->version = 6; iph->nexthdr = IPPROTO_IPV6; - iph->payload_len = old_iph->payload_len + sizeof(old_iph); + iph->payload_len = old_iph->payload_len; + be16_add_cpu(&iph->payload_len, sizeof(*old_iph)); iph->priority = old_iph->priority; memset(&iph->flow_lbl, 0, sizeof(iph->flow_lbl)); iph->daddr = rt->rt6i_dst.addr; diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index 622d7c671cb7..233fdd2d7d21 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -305,9 +305,7 @@ void nf_conntrack_hash_insert(struct nf_conn *ct) hash = hash_conntrack(&ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); repl_hash = hash_conntrack(&ct->tuplehash[IP_CT_DIR_REPLY].tuple); - spin_lock_bh(&nf_conntrack_lock); __nf_conntrack_hash_insert(ct, hash, repl_hash); - spin_unlock_bh(&nf_conntrack_lock); } EXPORT_SYMBOL_GPL(nf_conntrack_hash_insert); diff --git a/net/netfilter/nf_conntrack_helper.c b/net/netfilter/nf_conntrack_helper.c index 9c06b9f86ad4..c39b6a994133 100644 --- a/net/netfilter/nf_conntrack_helper.c +++ b/net/netfilter/nf_conntrack_helper.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -167,10 +168,12 @@ void nf_conntrack_helper_unregister(struct nf_conntrack_helper *me) */ synchronize_rcu(); + rtnl_lock(); spin_lock_bh(&nf_conntrack_lock); for_each_net(net) __nf_conntrack_helper_unregister(me, net); spin_unlock_bh(&nf_conntrack_lock); + rtnl_unlock(); } EXPORT_SYMBOL_GPL(nf_conntrack_helper_unregister); diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index a040d46f85d6..5f4a6516b3b6 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -1090,7 +1090,7 @@ ctnetlink_create_conntrack(struct nlattr *cda[], struct nf_conn_help *help; struct nf_conntrack_helper *helper; - ct = nf_conntrack_alloc(&init_net, otuple, rtuple, GFP_KERNEL); + ct = nf_conntrack_alloc(&init_net, otuple, rtuple, GFP_ATOMIC); if (ct == NULL || IS_ERR(ct)) return -ENOMEM; @@ -1138,7 +1138,7 @@ ctnetlink_create_conntrack(struct nlattr *cda[], } } - nf_ct_acct_ext_add(ct, GFP_KERNEL); + nf_ct_acct_ext_add(ct, GFP_ATOMIC); #if defined(CONFIG_NF_CONNTRACK_MARK) if (cda[CTA_MARK]) @@ -1212,13 +1212,14 @@ ctnetlink_new_conntrack(struct sock *ctnl, struct sk_buff *skb, atomic_inc(&master_ct->ct_general.use); } - spin_unlock_bh(&nf_conntrack_lock); err = -ENOENT; if (nlh->nlmsg_flags & NLM_F_CREATE) err = ctnetlink_create_conntrack(cda, &otuple, &rtuple, master_ct); + spin_unlock_bh(&nf_conntrack_lock); + if (err < 0 && master_ct) nf_ct_put(master_ct); diff --git a/net/netfilter/nf_conntrack_proto.c b/net/netfilter/nf_conntrack_proto.c index a59a307e685d..592d73344d46 100644 --- a/net/netfilter/nf_conntrack_proto.c +++ b/net/netfilter/nf_conntrack_proto.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -221,8 +222,10 @@ void nf_conntrack_l3proto_unregister(struct nf_conntrack_l3proto *proto) synchronize_rcu(); /* Remove all contrack entries for this protocol */ + rtnl_lock(); for_each_net(net) nf_ct_iterate_cleanup(net, kill_l3proto, proto); + rtnl_unlock(); } EXPORT_SYMBOL_GPL(nf_conntrack_l3proto_unregister); @@ -333,8 +336,10 @@ void nf_conntrack_l4proto_unregister(struct nf_conntrack_l4proto *l4proto) synchronize_rcu(); /* Remove all contrack entries for this protocol */ + rtnl_lock(); for_each_net(net) nf_ct_iterate_cleanup(net, kill_l4proto, l4proto); + rtnl_unlock(); } EXPORT_SYMBOL_GPL(nf_conntrack_l4proto_unregister); diff --git a/net/netfilter/nf_conntrack_proto_gre.c b/net/netfilter/nf_conntrack_proto_gre.c index a2cdbcbf64c4..4ab62ad85dd4 100644 --- a/net/netfilter/nf_conntrack_proto_gre.c +++ b/net/netfilter/nf_conntrack_proto_gre.c @@ -335,7 +335,7 @@ static int __init nf_ct_proto_gre_init(void) rv = nf_conntrack_l4proto_register(&nf_conntrack_l4proto_gre4); if (rv < 0) return rv; - rv = register_pernet_gen_device(&proto_gre_net_id, &proto_gre_net_ops); + rv = register_pernet_gen_subsys(&proto_gre_net_id, &proto_gre_net_ops); if (rv < 0) nf_conntrack_l4proto_unregister(&nf_conntrack_l4proto_gre4); return rv; @@ -344,7 +344,7 @@ static int __init nf_ct_proto_gre_init(void) static void nf_ct_proto_gre_fini(void) { nf_conntrack_l4proto_unregister(&nf_conntrack_l4proto_gre4); - unregister_pernet_gen_device(proto_gre_net_id, &proto_gre_net_ops); + unregister_pernet_gen_subsys(proto_gre_net_id, &proto_gre_net_ops); } module_init(nf_ct_proto_gre_init); diff --git a/net/netfilter/xt_socket.c b/net/netfilter/xt_socket.c index 02a8fed21082..1acc089be7e9 100644 --- a/net/netfilter/xt_socket.c +++ b/net/netfilter/xt_socket.c @@ -141,7 +141,7 @@ socket_mt(const struct sk_buff *skb, const struct xt_match_param *par) sk = nf_tproxy_get_sock_v4(dev_net(skb->dev), protocol, saddr, daddr, sport, dport, par->in, false); if (sk != NULL) { - bool wildcard = (inet_sk(sk)->rcv_saddr == 0); + bool wildcard = (sk->sk_state != TCP_TIME_WAIT && inet_sk(sk)->rcv_saddr == 0); nf_tproxy_put_sock(sk); if (wildcard) diff --git a/net/netlabel/netlabel_addrlist.c b/net/netlabel/netlabel_addrlist.c index b0925a303353..249f6b92f153 100644 --- a/net/netlabel/netlabel_addrlist.c +++ b/net/netlabel/netlabel_addrlist.c @@ -315,6 +315,7 @@ struct netlbl_af6list *netlbl_af6list_remove(const struct in6_addr *addr, * Audit Helper Functions */ +#ifdef CONFIG_AUDIT /** * netlbl_af4list_audit_addr - Audit an IPv4 address * @audit_buf: audit buffer @@ -386,3 +387,4 @@ void netlbl_af6list_audit_addr(struct audit_buffer *audit_buf, } } #endif /* IPv6 */ +#endif /* CONFIG_AUDIT */ diff --git a/net/netlabel/netlabel_addrlist.h b/net/netlabel/netlabel_addrlist.h index 0242bead405f..07ae7fd82be1 100644 --- a/net/netlabel/netlabel_addrlist.h +++ b/net/netlabel/netlabel_addrlist.h @@ -120,9 +120,19 @@ struct netlbl_af4list *netlbl_af4list_search(__be32 addr, struct netlbl_af4list *netlbl_af4list_search_exact(__be32 addr, __be32 mask, struct list_head *head); + +#ifdef CONFIG_AUDIT void netlbl_af4list_audit_addr(struct audit_buffer *audit_buf, int src, const char *dev, __be32 addr, __be32 mask); +#else +static inline void netlbl_af4list_audit_addr(struct audit_buffer *audit_buf, + int src, const char *dev, + __be32 addr, __be32 mask) +{ + return; +} +#endif #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) @@ -179,11 +189,23 @@ struct netlbl_af6list *netlbl_af6list_search(const struct in6_addr *addr, struct netlbl_af6list *netlbl_af6list_search_exact(const struct in6_addr *addr, const struct in6_addr *mask, struct list_head *head); + +#ifdef CONFIG_AUDIT void netlbl_af6list_audit_addr(struct audit_buffer *audit_buf, int src, const char *dev, const struct in6_addr *addr, const struct in6_addr *mask); +#else +static inline void netlbl_af6list_audit_addr(struct audit_buffer *audit_buf, + int src, + const char *dev, + const struct in6_addr *addr, + const struct in6_addr *mask) +{ + return; +} +#endif #endif /* IPV6 */ #endif diff --git a/net/netlabel/netlabel_mgmt.c b/net/netlabel/netlabel_mgmt.c index ee769ecaa13c..0a0ef17b2a40 100644 --- a/net/netlabel/netlabel_mgmt.c +++ b/net/netlabel/netlabel_mgmt.c @@ -265,7 +265,7 @@ add_failure: static int netlbl_mgmt_listentry(struct sk_buff *skb, struct netlbl_dom_map *entry) { - int ret_val; + int ret_val = 0; struct nlattr *nla_a; struct nlattr *nla_b; struct netlbl_af4list *iter4; diff --git a/net/netlabel/netlabel_unlabeled.c b/net/netlabel/netlabel_unlabeled.c index e8a5c32b0f10..8c0308032178 100644 --- a/net/netlabel/netlabel_unlabeled.c +++ b/net/netlabel/netlabel_unlabeled.c @@ -562,7 +562,6 @@ static int netlbl_unlhsh_remove_addr4(struct net *net, const struct in_addr *mask, struct netlbl_audit *audit_info) { - int ret_val = 0; struct netlbl_af4list *list_entry; struct netlbl_unlhsh_addr4 *entry; struct audit_buffer *audit_buf; @@ -574,9 +573,10 @@ static int netlbl_unlhsh_remove_addr4(struct net *net, list_entry = netlbl_af4list_remove(addr->s_addr, mask->s_addr, &iface->addr4_list); spin_unlock(&netlbl_unlhsh_lock); - if (list_entry == NULL) - ret_val = -ENOENT; - entry = netlbl_unlhsh_addr4_entry(list_entry); + if (list_entry != NULL) + entry = netlbl_unlhsh_addr4_entry(list_entry); + else + entry = NULL; audit_buf = netlbl_audit_start_common(AUDIT_MAC_UNLBL_STCDEL, audit_info); @@ -587,19 +587,21 @@ static int netlbl_unlhsh_remove_addr4(struct net *net, addr->s_addr, mask->s_addr); if (dev != NULL) dev_put(dev); - if (entry && security_secid_to_secctx(entry->secid, - &secctx, - &secctx_len) == 0) { + if (entry != NULL && + security_secid_to_secctx(entry->secid, + &secctx, &secctx_len) == 0) { audit_log_format(audit_buf, " sec_obj=%s", secctx); security_release_secctx(secctx, secctx_len); } - audit_log_format(audit_buf, " res=%u", ret_val == 0 ? 1 : 0); + audit_log_format(audit_buf, " res=%u", entry != NULL ? 1 : 0); audit_log_end(audit_buf); } - if (ret_val == 0) - call_rcu(&entry->rcu, netlbl_unlhsh_free_addr4); - return ret_val; + if (entry == NULL) + return -ENOENT; + + call_rcu(&entry->rcu, netlbl_unlhsh_free_addr4); + return 0; } #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) @@ -623,7 +625,6 @@ static int netlbl_unlhsh_remove_addr6(struct net *net, const struct in6_addr *mask, struct netlbl_audit *audit_info) { - int ret_val = 0; struct netlbl_af6list *list_entry; struct netlbl_unlhsh_addr6 *entry; struct audit_buffer *audit_buf; @@ -634,9 +635,10 @@ static int netlbl_unlhsh_remove_addr6(struct net *net, spin_lock(&netlbl_unlhsh_lock); list_entry = netlbl_af6list_remove(addr, mask, &iface->addr6_list); spin_unlock(&netlbl_unlhsh_lock); - if (list_entry == NULL) - ret_val = -ENOENT; - entry = netlbl_unlhsh_addr6_entry(list_entry); + if (list_entry != NULL) + entry = netlbl_unlhsh_addr6_entry(list_entry); + else + entry = NULL; audit_buf = netlbl_audit_start_common(AUDIT_MAC_UNLBL_STCDEL, audit_info); @@ -647,19 +649,21 @@ static int netlbl_unlhsh_remove_addr6(struct net *net, addr, mask); if (dev != NULL) dev_put(dev); - if (entry && security_secid_to_secctx(entry->secid, - &secctx, - &secctx_len) == 0) { + if (entry != NULL && + security_secid_to_secctx(entry->secid, + &secctx, &secctx_len) == 0) { audit_log_format(audit_buf, " sec_obj=%s", secctx); security_release_secctx(secctx, secctx_len); } - audit_log_format(audit_buf, " res=%u", ret_val == 0 ? 1 : 0); + audit_log_format(audit_buf, " res=%u", entry != NULL ? 1 : 0); audit_log_end(audit_buf); } - if (ret_val == 0) - call_rcu(&entry->rcu, netlbl_unlhsh_free_addr6); - return ret_val; + if (entry == NULL) + return -ENOENT; + + call_rcu(&entry->rcu, netlbl_unlhsh_free_addr6); + return 0; } #endif /* IPv6 */ diff --git a/net/phonet/af_phonet.c b/net/phonet/af_phonet.c index b9d97effebe3..9d211f12582b 100644 --- a/net/phonet/af_phonet.c +++ b/net/phonet/af_phonet.c @@ -33,9 +33,30 @@ #include #include -static struct net_proto_family phonet_proto_family; -static struct phonet_protocol *phonet_proto_get(int protocol); -static inline void phonet_proto_put(struct phonet_protocol *pp); +/* Transport protocol registration */ +static struct phonet_protocol *proto_tab[PHONET_NPROTO] __read_mostly; +static DEFINE_SPINLOCK(proto_tab_lock); + +static struct phonet_protocol *phonet_proto_get(int protocol) +{ + struct phonet_protocol *pp; + + if (protocol >= PHONET_NPROTO) + return NULL; + + spin_lock(&proto_tab_lock); + pp = proto_tab[protocol]; + if (pp && !try_module_get(pp->prot->owner)) + pp = NULL; + spin_unlock(&proto_tab_lock); + + return pp; +} + +static inline void phonet_proto_put(struct phonet_protocol *pp) +{ + module_put(pp->prot->owner); +} /* protocol family functions */ @@ -144,8 +165,8 @@ static int pn_send(struct sk_buff *skb, struct net_device *dev, struct phonethdr *ph; int err; - if (skb->len + 2 > 0xffff) { - /* Phonet length field would overflow */ + if (skb->len + 2 > 0xffff /* Phonet length field limit */ || + skb->len + sizeof(struct phonethdr) > dev->mtu) { err = -EMSGSIZE; goto drop; } @@ -261,6 +282,8 @@ static inline int can_respond(struct sk_buff *skb) return 0; /* we are not the destination */ if (ph->pn_res == PN_PREFIX && !pskb_may_pull(skb, 5)) return 0; + if (ph->pn_res == PN_COMMGR) /* indications */ + return 0; ph = pn_hdr(skb); /* re-acquires the pointer */ pm = pn_msg(skb); @@ -309,7 +332,8 @@ static int send_reset_indications(struct sk_buff *rskb) return pn_raw_send(data, sizeof(data), rskb->dev, pn_object(oph->pn_sdev, 0x00), - pn_object(oph->pn_rdev, oph->pn_robj), 0x10); + pn_object(oph->pn_rdev, oph->pn_robj), + PN_COMMGR); } @@ -372,10 +396,6 @@ static struct packet_type phonet_packet_type = { .func = phonet_rcv, }; -/* Transport protocol registration */ -static struct phonet_protocol *proto_tab[PHONET_NPROTO] __read_mostly; -static DEFINE_SPINLOCK(proto_tab_lock); - int __init_or_module phonet_proto_register(int protocol, struct phonet_protocol *pp) { @@ -409,27 +429,6 @@ void phonet_proto_unregister(int protocol, struct phonet_protocol *pp) } EXPORT_SYMBOL(phonet_proto_unregister); -static struct phonet_protocol *phonet_proto_get(int protocol) -{ - struct phonet_protocol *pp; - - if (protocol >= PHONET_NPROTO) - return NULL; - - spin_lock(&proto_tab_lock); - pp = proto_tab[protocol]; - if (pp && !try_module_get(pp->prot->owner)) - pp = NULL; - spin_unlock(&proto_tab_lock); - - return pp; -} - -static inline void phonet_proto_put(struct phonet_protocol *pp) -{ - module_put(pp->prot->owner); -} - /* Module registration */ static int __init phonet_init(void) { diff --git a/net/phonet/pep-gprs.c b/net/phonet/pep-gprs.c index 9978afbd9f2a..803eeef0aa85 100644 --- a/net/phonet/pep-gprs.c +++ b/net/phonet/pep-gprs.c @@ -155,12 +155,13 @@ static void gprs_data_ready(struct sock *sk, int len) static void gprs_write_space(struct sock *sk) { struct gprs_dev *dev = sk->sk_user_data; + struct net_device *net = dev->net; unsigned credits = pep_writeable(sk); spin_lock_bh(&dev->tx_lock); dev->tx_max = credits; - if (credits > skb_queue_len(&dev->tx_queue)) - netif_wake_queue(dev->net); + if (credits > skb_queue_len(&dev->tx_queue) && netif_running(net)) + netif_wake_queue(net); spin_unlock_bh(&dev->tx_lock); } @@ -168,6 +169,23 @@ static void gprs_write_space(struct sock *sk) * Network device callbacks */ +static int gprs_open(struct net_device *dev) +{ + struct gprs_dev *gp = netdev_priv(dev); + + gprs_write_space(gp->sk); + return 0; +} + +static int gprs_close(struct net_device *dev) +{ + struct gprs_dev *gp = netdev_priv(dev); + + netif_stop_queue(dev); + flush_work(&gp->tx_work); + return 0; +} + static int gprs_xmit(struct sk_buff *skb, struct net_device *net) { struct gprs_dev *dev = netdev_priv(net); @@ -254,6 +272,8 @@ static void gprs_setup(struct net_device *net) net->tx_queue_len = 10; net->destructor = free_netdev; + net->open = gprs_open; + net->stop = gprs_close; net->hard_start_xmit = gprs_xmit; /* mandatory */ net->change_mtu = gprs_set_mtu; net->get_stats = gprs_get_stats; @@ -318,7 +338,6 @@ int gprs_attach(struct sock *sk) dev->sk = sk; printk(KERN_DEBUG"%s: attached\n", net->name); - gprs_write_space(sk); /* kick off TX */ return net->ifindex; out_rel: @@ -341,7 +360,5 @@ void gprs_detach(struct sock *sk) printk(KERN_DEBUG"%s: detached\n", net->name); unregister_netdev(net); - flush_scheduled_work(); sock_put(sk); - skb_queue_purge(&dev->tx_queue); } diff --git a/net/phonet/pn_dev.c b/net/phonet/pn_dev.c index 53be9fc82aaa..f93ff8ef47d0 100644 --- a/net/phonet/pn_dev.c +++ b/net/phonet/pn_dev.c @@ -115,7 +115,7 @@ int phonet_address_del(struct net_device *dev, u8 addr) pnd = __phonet_get(dev); if (!pnd || !test_and_clear_bit(addr >> 2, pnd->addrs)) err = -EADDRNOTAVAIL; - if (bitmap_empty(pnd->addrs, 64)) + else if (bitmap_empty(pnd->addrs, 64)) __phonet_device_free(pnd); spin_unlock_bh(&pndevs.lock); return err; diff --git a/net/phonet/pn_netlink.c b/net/phonet/pn_netlink.c index b1770d66bc8d..242fe8f8c322 100644 --- a/net/phonet/pn_netlink.c +++ b/net/phonet/pn_netlink.c @@ -123,6 +123,7 @@ nla_put_failure: static int getaddr_dumpit(struct sk_buff *skb, struct netlink_callback *cb) { + struct net *net = sock_net(skb->sk); struct phonet_device *pnd; int dev_idx = 0, dev_start_idx = cb->args[0]; int addr_idx = 0, addr_start_idx = cb->args[1]; @@ -131,6 +132,8 @@ static int getaddr_dumpit(struct sk_buff *skb, struct netlink_callback *cb) list_for_each_entry(pnd, &pndevs.list, list) { u8 addr; + if (!net_eq(dev_net(pnd->netdev), net)) + continue; if (dev_idx > dev_start_idx) addr_start_idx = 0; if (dev_idx++ < dev_start_idx) diff --git a/net/rfkill/rfkill-input.c b/net/rfkill/rfkill-input.c index 21124ec0a73d..bfdade72e066 100644 --- a/net/rfkill/rfkill-input.c +++ b/net/rfkill/rfkill-input.c @@ -256,6 +256,11 @@ static struct input_handler rfkill_handler = { static int __init rfkill_handler_init(void) { + unsigned long last_run = jiffies - msecs_to_jiffies(500); + rfkill_wlan.last = last_run; + rfkill_bt.last = last_run; + rfkill_uwb.last = last_run; + rfkill_wimax.last = last_run; return input_register_handler(&rfkill_handler); } diff --git a/net/rfkill/rfkill.c b/net/rfkill/rfkill.c index f949a482b007..25ba3bd57e66 100644 --- a/net/rfkill/rfkill.c +++ b/net/rfkill/rfkill.c @@ -603,7 +603,7 @@ static int rfkill_check_duplicity(const struct rfkill *rfkill) } /* 0: first switch of its kind */ - return test_bit(rfkill->type, seen); + return (test_bit(rfkill->type, seen)) ? 1 : 0; } static int rfkill_add_switch(struct rfkill *rfkill) diff --git a/net/rose/af_rose.c b/net/rose/af_rose.c index a7f1ce11bc22..0c1cc7612800 100644 --- a/net/rose/af_rose.c +++ b/net/rose/af_rose.c @@ -1072,6 +1072,10 @@ static int rose_sendmsg(struct kiocb *iocb, struct socket *sock, unsigned char *asmptr; int n, size, qbit = 0; + /* ROSE empty frame has no meaning : don't send */ + if (len == 0) + return 0; + if (msg->msg_flags & ~(MSG_DONTWAIT|MSG_EOR|MSG_CMSG_COMPAT)) return -EINVAL; @@ -1265,6 +1269,12 @@ static int rose_recvmsg(struct kiocb *iocb, struct socket *sock, skb_reset_transport_header(skb); copied = skb->len; + /* ROSE empty frame has no meaning : ignore it */ + if (copied == 0) { + skb_free_datagram(sk, skb); + return copied; + } + if (copied > size) { copied = size; msg->msg_flags |= MSG_TRUNC; diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index b16ad2972c6b..6ab4a2f92ca0 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -417,6 +417,8 @@ static int qdisc_dump_stab(struct sk_buff *skb, struct qdisc_size_table *stab) struct nlattr *nest; nest = nla_nest_start(skb, TCA_STAB); + if (nest == NULL) + goto nla_put_failure; NLA_PUT(skb, TCA_STAB_BASE, sizeof(stab->szopts), &stab->szopts); nla_nest_end(skb, nest); diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c index 93cd30ce6501..cdcd16fcfeda 100644 --- a/net/sched/sch_generic.c +++ b/net/sched/sch_generic.c @@ -270,6 +270,8 @@ static void dev_watchdog_down(struct net_device *dev) void netif_carrier_on(struct net_device *dev) { if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &dev->state)) { + if (dev->reg_state == NETREG_UNINITIALIZED) + return; linkwatch_fire_event(dev); if (netif_running(dev)) __netdev_watchdog_up(dev); @@ -285,8 +287,11 @@ EXPORT_SYMBOL(netif_carrier_on); */ void netif_carrier_off(struct net_device *dev) { - if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->state)) + if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->state)) { + if (dev->reg_state == NETREG_UNINITIALIZED) + return; linkwatch_fire_event(dev); + } } EXPORT_SYMBOL(netif_carrier_off); diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c index a11959908d9a..98402f0efa47 100644 --- a/net/sched/sch_netem.c +++ b/net/sched/sch_netem.c @@ -46,9 +46,6 @@ layering other disciplines. It does not need to do bandwidth control either since that can be handled by using token bucket or other rate control. - - The simulator is limited by the Linux timer resolution - and will create packet bursts on the HZ boundary (1ms). */ struct netem_sched_data { diff --git a/net/socket.c b/net/socket.c index 2b7a4b5c9b72..92764d836891 100644 --- a/net/socket.c +++ b/net/socket.c @@ -990,7 +990,6 @@ static int sock_close(struct inode *inode, struct file *filp) printk(KERN_DEBUG "sock_close: NULL inode\n"); return 0; } - sock_fasync(-1, filp, 0); sock_release(SOCKET_I(inode)); return 0; } @@ -1427,8 +1426,8 @@ asmlinkage long sys_listen(int fd, int backlog) * clean when we restucture accept also. */ -long do_accept(int fd, struct sockaddr __user *upeer_sockaddr, - int __user *upeer_addrlen, int flags) +asmlinkage long sys_accept4(int fd, struct sockaddr __user *upeer_sockaddr, + int __user *upeer_addrlen, int flags) { struct socket *sock, *newsock; struct file *newfile; @@ -1511,66 +1510,10 @@ out_fd: goto out_put; } -#if 0 -#ifdef HAVE_SET_RESTORE_SIGMASK -asmlinkage long sys_paccept(int fd, struct sockaddr __user *upeer_sockaddr, - int __user *upeer_addrlen, - const sigset_t __user *sigmask, - size_t sigsetsize, int flags) -{ - sigset_t ksigmask, sigsaved; - int ret; - - if (sigmask) { - /* XXX: Don't preclude handling different sized sigset_t's. */ - if (sigsetsize != sizeof(sigset_t)) - return -EINVAL; - if (copy_from_user(&ksigmask, sigmask, sizeof(ksigmask))) - return -EFAULT; - - sigdelsetmask(&ksigmask, sigmask(SIGKILL)|sigmask(SIGSTOP)); - sigprocmask(SIG_SETMASK, &ksigmask, &sigsaved); - } - - ret = do_accept(fd, upeer_sockaddr, upeer_addrlen, flags); - - if (ret < 0 && signal_pending(current)) { - /* - * Don't restore the signal mask yet. Let do_signal() deliver - * the signal on the way back to userspace, before the signal - * mask is restored. - */ - if (sigmask) { - memcpy(¤t->saved_sigmask, &sigsaved, - sizeof(sigsaved)); - set_restore_sigmask(); - } - } else if (sigmask) - sigprocmask(SIG_SETMASK, &sigsaved, NULL); - - return ret; -} -#else -asmlinkage long sys_paccept(int fd, struct sockaddr __user *upeer_sockaddr, - int __user *upeer_addrlen, - const sigset_t __user *sigmask, - size_t sigsetsize, int flags) -{ - /* The platform does not support restoring the signal mask in the - * return path. So we do not allow using paccept() with a signal - * mask. */ - if (sigmask) - return -EINVAL; - - return do_accept(fd, upeer_sockaddr, upeer_addrlen, flags); -} -#endif -#endif - asmlinkage long sys_accept(int fd, struct sockaddr __user *upeer_sockaddr, int __user *upeer_addrlen) { - return do_accept(fd, upeer_sockaddr, upeer_addrlen, 0); + return sys_accept4(fd, upeer_sockaddr, upeer_addrlen, 0); } /* @@ -2097,7 +2040,7 @@ static const unsigned char nargs[19]={ AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), AL(3),AL(3),AL(4),AL(4),AL(4),AL(6), AL(6),AL(2),AL(5),AL(5),AL(3),AL(3), - AL(6) + AL(4) }; #undef AL @@ -2116,7 +2059,7 @@ asmlinkage long sys_socketcall(int call, unsigned long __user *args) unsigned long a0, a1; int err; - if (call < 1 || call > SYS_PACCEPT) + if (call < 1 || call > SYS_ACCEPT4) return -EINVAL; /* copy_from_user should be SMP safe. */ @@ -2144,9 +2087,8 @@ asmlinkage long sys_socketcall(int call, unsigned long __user *args) err = sys_listen(a0, a1); break; case SYS_ACCEPT: - err = - do_accept(a0, (struct sockaddr __user *)a1, - (int __user *)a[2], 0); + err = sys_accept4(a0, (struct sockaddr __user *)a1, + (int __user *)a[2], 0); break; case SYS_GETSOCKNAME: err = @@ -2193,12 +2135,9 @@ asmlinkage long sys_socketcall(int call, unsigned long __user *args) case SYS_RECVMSG: err = sys_recvmsg(a0, (struct msghdr __user *)a1, a[2]); break; - case SYS_PACCEPT: - err = - sys_paccept(a0, (struct sockaddr __user *)a1, - (int __user *)a[2], - (const sigset_t __user *) a[3], - a[4], a[5]); + case SYS_ACCEPT4: + err = sys_accept4(a0, (struct sockaddr __user *)a1, + (int __user *)a[2], a[3]); break; default: err = -EINVAL; diff --git a/net/sunrpc/auth.c b/net/sunrpc/auth.c index 436bf1b4b76c..cb216b2df666 100644 --- a/net/sunrpc/auth.c +++ b/net/sunrpc/auth.c @@ -228,19 +228,21 @@ static int rpcauth_prune_expired(struct list_head *free, int nr_to_scan) { spinlock_t *cache_lock; - struct rpc_cred *cred; + struct rpc_cred *cred, *next; unsigned long expired = jiffies - RPC_AUTH_EXPIRY_MORATORIUM; - while (!list_empty(&cred_unused)) { - cred = list_entry(cred_unused.next, struct rpc_cred, cr_lru); + list_for_each_entry_safe(cred, next, &cred_unused, cr_lru) { + + /* Enforce a 60 second garbage collection moratorium */ + if (time_in_range(cred->cr_expire, expired, jiffies) && + test_bit(RPCAUTH_CRED_HASHED, &cred->cr_flags) != 0) + continue; + list_del_init(&cred->cr_lru); number_cred_unused--; if (atomic_read(&cred->cr_count) != 0) continue; - /* Enforce a 5 second garbage collection moratorium */ - if (time_in_range(cred->cr_expire, expired, jiffies) && - test_bit(RPCAUTH_CRED_UPTODATE, &cred->cr_flags) != 0) - continue; + cache_lock = &cred->cr_auth->au_credcache->lock; spin_lock(cache_lock); if (atomic_read(&cred->cr_count) == 0) { @@ -453,7 +455,7 @@ need_lock: } if (test_bit(RPCAUTH_CRED_UPTODATE, &cred->cr_flags) == 0) rpcauth_unhash_cred(cred); - else if (test_bit(RPCAUTH_CRED_HASHED, &cred->cr_flags) != 0) { + if (test_bit(RPCAUTH_CRED_HASHED, &cred->cr_flags) != 0) { cred->cr_expire = jiffies; list_add_tail(&cred->cr_lru, &cred_unused); number_cred_unused++; diff --git a/net/sunrpc/auth_generic.c b/net/sunrpc/auth_generic.c index 744b79fdcb19..4028502f0528 100644 --- a/net/sunrpc/auth_generic.c +++ b/net/sunrpc/auth_generic.c @@ -133,13 +133,29 @@ static int generic_match(struct auth_cred *acred, struct rpc_cred *cred, int flags) { struct generic_cred *gcred = container_of(cred, struct generic_cred, gc_base); + int i; if (gcred->acred.uid != acred->uid || gcred->acred.gid != acred->gid || - gcred->acred.group_info != acred->group_info || gcred->acred.machine_cred != acred->machine_cred) - return 0; + goto out_nomatch; + + /* Optimisation in the case where pointers are identical... */ + if (gcred->acred.group_info == acred->group_info) + goto out_match; + + /* Slow path... */ + if (gcred->acred.group_info->ngroups != acred->group_info->ngroups) + goto out_nomatch; + for (i = 0; i < gcred->acred.group_info->ngroups; i++) { + if (GROUP_AT(gcred->acred.group_info, i) != + GROUP_AT(acred->group_info, i)) + goto out_nomatch; + } +out_match: return 1; +out_nomatch: + return 0; } void __init rpc_init_generic_auth(void) diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index 95293f549e9c..a1951dcc5776 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c @@ -1183,7 +1183,11 @@ int svc_addsock(struct svc_serv *serv, else if (so->state > SS_UNCONNECTED) err = -EISCONN; else { - svsk = svc_setup_socket(serv, so, &err, SVC_SOCK_DEFAULTS); + if (!try_module_get(THIS_MODULE)) + err = -ENOENT; + else + svsk = svc_setup_socket(serv, so, &err, + SVC_SOCK_DEFAULTS); if (svsk) { struct sockaddr_storage addr; struct sockaddr *sin = (struct sockaddr *)&addr; @@ -1196,7 +1200,8 @@ int svc_addsock(struct svc_serv *serv, spin_unlock_bh(&serv->sv_lock); svc_xprt_received(&svsk->sk_xprt); err = 0; - } + } else + module_put(THIS_MODULE); } if (err) { sockfd_put(so); diff --git a/net/sunrpc/xprtsock.c b/net/sunrpc/xprtsock.c index 9a288d5eea64..0a50361e3d83 100644 --- a/net/sunrpc/xprtsock.c +++ b/net/sunrpc/xprtsock.c @@ -249,6 +249,7 @@ struct sock_xprt { void (*old_data_ready)(struct sock *, int); void (*old_state_change)(struct sock *); void (*old_write_space)(struct sock *); + void (*old_error_report)(struct sock *); }; /* @@ -698,8 +699,9 @@ static int xs_tcp_send_request(struct rpc_task *task) case -EAGAIN: xs_nospace(task); break; - case -ECONNREFUSED: case -ECONNRESET: + xs_tcp_shutdown(xprt); + case -ECONNREFUSED: case -ENOTCONN: case -EPIPE: status = -ENOTCONN; @@ -742,6 +744,22 @@ out_release: xprt_release_xprt(xprt, task); } +static void xs_save_old_callbacks(struct sock_xprt *transport, struct sock *sk) +{ + transport->old_data_ready = sk->sk_data_ready; + transport->old_state_change = sk->sk_state_change; + transport->old_write_space = sk->sk_write_space; + transport->old_error_report = sk->sk_error_report; +} + +static void xs_restore_old_callbacks(struct sock_xprt *transport, struct sock *sk) +{ + sk->sk_data_ready = transport->old_data_ready; + sk->sk_state_change = transport->old_state_change; + sk->sk_write_space = transport->old_write_space; + sk->sk_error_report = transport->old_error_report; +} + /** * xs_close - close a socket * @xprt: transport @@ -765,9 +783,8 @@ static void xs_close(struct rpc_xprt *xprt) transport->sock = NULL; sk->sk_user_data = NULL; - sk->sk_data_ready = transport->old_data_ready; - sk->sk_state_change = transport->old_state_change; - sk->sk_write_space = transport->old_write_space; + + xs_restore_old_callbacks(transport, sk); write_unlock_bh(&sk->sk_callback_lock); sk->sk_no_check = 0; @@ -1179,6 +1196,28 @@ static void xs_tcp_state_change(struct sock *sk) read_unlock(&sk->sk_callback_lock); } +/** + * xs_tcp_error_report - callback mainly for catching RST events + * @sk: socket + */ +static void xs_tcp_error_report(struct sock *sk) +{ + struct rpc_xprt *xprt; + + read_lock(&sk->sk_callback_lock); + if (sk->sk_err != ECONNRESET || sk->sk_state != TCP_ESTABLISHED) + goto out; + if (!(xprt = xprt_from_sock(sk))) + goto out; + dprintk("RPC: %s client %p...\n" + "RPC: error %d\n", + __func__, xprt, sk->sk_err); + + xprt_force_disconnect(xprt); +out: + read_unlock(&sk->sk_callback_lock); +} + /** * xs_udp_write_space - callback invoked when socket buffer space * becomes available @@ -1454,10 +1493,9 @@ static void xs_udp_finish_connecting(struct rpc_xprt *xprt, struct socket *sock) write_lock_bh(&sk->sk_callback_lock); + xs_save_old_callbacks(transport, sk); + sk->sk_user_data = xprt; - transport->old_data_ready = sk->sk_data_ready; - transport->old_state_change = sk->sk_state_change; - transport->old_write_space = sk->sk_write_space; sk->sk_data_ready = xs_udp_data_ready; sk->sk_write_space = xs_udp_write_space; sk->sk_no_check = UDP_CSUM_NORCV; @@ -1589,13 +1627,13 @@ static int xs_tcp_finish_connecting(struct rpc_xprt *xprt, struct socket *sock) write_lock_bh(&sk->sk_callback_lock); + xs_save_old_callbacks(transport, sk); + sk->sk_user_data = xprt; - transport->old_data_ready = sk->sk_data_ready; - transport->old_state_change = sk->sk_state_change; - transport->old_write_space = sk->sk_write_space; sk->sk_data_ready = xs_tcp_data_ready; sk->sk_state_change = xs_tcp_state_change; sk->sk_write_space = xs_tcp_write_space; + sk->sk_error_report = xs_tcp_error_report; sk->sk_allocation = GFP_ATOMIC; /* socket options */ diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index dc504d308ec0..66d5ac4773ab 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -1302,14 +1302,23 @@ static void unix_destruct_fds(struct sk_buff *skb) sock_wfree(skb); } -static void unix_attach_fds(struct scm_cookie *scm, struct sk_buff *skb) +static int unix_attach_fds(struct scm_cookie *scm, struct sk_buff *skb) { int i; + + /* + * Need to duplicate file references for the sake of garbage + * collection. Otherwise a socket in the fps might become a + * candidate for GC while the skb is not yet queued. + */ + UNIXCB(skb).fp = scm_fp_dup(scm->fp); + if (!UNIXCB(skb).fp) + return -ENOMEM; + for (i=scm->fp->count-1; i>=0; i--) unix_inflight(scm->fp->fp[i]); - UNIXCB(skb).fp = scm->fp; skb->destructor = unix_destruct_fds; - scm->fp = NULL; + return 0; } /* @@ -1334,6 +1343,7 @@ static int unix_dgram_sendmsg(struct kiocb *kiocb, struct socket *sock, if (NULL == siocb->scm) siocb->scm = &tmp_scm; + wait_for_unix_gc(); err = scm_send(sock, msg, siocb->scm); if (err < 0) return err; @@ -1368,8 +1378,11 @@ static int unix_dgram_sendmsg(struct kiocb *kiocb, struct socket *sock, goto out; memcpy(UNIXCREDS(skb), &siocb->scm->creds, sizeof(struct ucred)); - if (siocb->scm->fp) - unix_attach_fds(siocb->scm, skb); + if (siocb->scm->fp) { + err = unix_attach_fds(siocb->scm, skb); + if (err) + goto out_free; + } unix_get_secdata(siocb->scm, skb); skb_reset_transport_header(skb); @@ -1481,6 +1494,7 @@ static int unix_stream_sendmsg(struct kiocb *kiocb, struct socket *sock, if (NULL == siocb->scm) siocb->scm = &tmp_scm; + wait_for_unix_gc(); err = scm_send(sock, msg, siocb->scm); if (err < 0) return err; @@ -1538,8 +1552,13 @@ static int unix_stream_sendmsg(struct kiocb *kiocb, struct socket *sock, size = min_t(int, size, skb_tailroom(skb)); memcpy(UNIXCREDS(skb), &siocb->scm->creds, sizeof(struct ucred)); - if (siocb->scm->fp) - unix_attach_fds(siocb->scm, skb); + if (siocb->scm->fp) { + err = unix_attach_fds(siocb->scm, skb); + if (err) { + kfree_skb(skb); + goto out_err; + } + } if ((err = memcpy_fromiovec(skb_put(skb,size), msg->msg_iov, size)) != 0) { kfree_skb(skb); @@ -2213,7 +2232,7 @@ static int unix_net_init(struct net *net) #endif error = 0; out: - return 0; + return error; } static void unix_net_exit(struct net *net) diff --git a/net/unix/garbage.c b/net/unix/garbage.c index 2a27b84f740b..abb3ab34cb1e 100644 --- a/net/unix/garbage.c +++ b/net/unix/garbage.c @@ -80,6 +80,7 @@ #include #include #include +#include #include #include @@ -91,6 +92,7 @@ static LIST_HEAD(gc_inflight_list); static LIST_HEAD(gc_candidates); static DEFINE_SPINLOCK(unix_gc_lock); +static DECLARE_WAIT_QUEUE_HEAD(unix_gc_wait); unsigned int unix_tot_inflight; @@ -186,8 +188,17 @@ static void scan_inflight(struct sock *x, void (*func)(struct unix_sock *), */ struct sock *sk = unix_get_socket(*fp++); if (sk) { - hit = true; - func(unix_sk(sk)); + struct unix_sock *u = unix_sk(sk); + + /* + * Ignore non-candidates, they could + * have been added to the queues after + * starting the garbage collection + */ + if (u->gc_candidate) { + hit = true; + func(u); + } } } if (hit && hitlist != NULL) { @@ -249,24 +260,29 @@ static void inc_inflight_move_tail(struct unix_sock *u) { atomic_long_inc(&u->inflight); /* - * If this is still a candidate, move it to the end of the - * list, so that it's checked even if it was already passed - * over + * If this still might be part of a cycle, move it to the end + * of the list, so that it's checked even if it was already + * passed over */ - if (u->gc_candidate) + if (u->gc_maybe_cycle) list_move_tail(&u->link, &gc_candidates); } -/* The external entry point: unix_gc() */ +static bool gc_in_progress = false; -void unix_gc(void) +void wait_for_unix_gc(void) { - static bool gc_in_progress = false; + wait_event(unix_gc_wait, gc_in_progress == false); +} +/* The external entry point: unix_gc() */ +void unix_gc(void) +{ struct unix_sock *u; struct unix_sock *next; struct sk_buff_head hitlist; struct list_head cursor; + LIST_HEAD(not_cycle_list); spin_lock(&unix_gc_lock); @@ -282,10 +298,14 @@ void unix_gc(void) * * Holding unix_gc_lock will protect these candidates from * being detached, and hence from gaining an external - * reference. This also means, that since there are no - * possible receivers, the receive queues of these sockets are - * static during the GC, even though the dequeue is done - * before the detach without atomicity guarantees. + * reference. Since there are no possible receivers, all + * buffers currently on the candidates' queues stay there + * during the garbage collection. + * + * We also know that no new candidate can be added onto the + * receive queues. Other, non candidate sockets _can_ be + * added to queue, so we must make sure only to touch + * candidates. */ list_for_each_entry_safe(u, next, &gc_inflight_list, link) { long total_refs; @@ -299,6 +319,7 @@ void unix_gc(void) if (total_refs == inflight_refs) { list_move_tail(&u->link, &gc_candidates); u->gc_candidate = 1; + u->gc_maybe_cycle = 1; } } @@ -325,13 +346,23 @@ void unix_gc(void) list_move(&cursor, &u->link); if (atomic_long_read(&u->inflight) > 0) { - list_move_tail(&u->link, &gc_inflight_list); - u->gc_candidate = 0; + list_move_tail(&u->link, ¬_cycle_list); + u->gc_maybe_cycle = 0; scan_children(&u->sk, inc_inflight_move_tail, NULL); } } list_del(&cursor); + /* + * not_cycle_list contains those sockets which do not make up a + * cycle. Restore these to the inflight list. + */ + while (!list_empty(¬_cycle_list)) { + u = list_entry(not_cycle_list.next, struct unix_sock, link); + u->gc_candidate = 0; + list_move_tail(&u->link, &gc_inflight_list); + } + /* * Now gc_candidates contains only garbage. Restore original * inflight counters for these as well, and remove the skbuffs @@ -351,6 +382,7 @@ void unix_gc(void) /* All candidates should have been detached by now. */ BUG_ON(!list_empty(&gc_candidates)); gc_in_progress = false; + wake_up(&unix_gc_wait); out: spin_unlock(&unix_gc_lock); diff --git a/net/wireless/reg.c b/net/wireless/reg.c index 626dbb688499..eb3b1a9f9b12 100644 --- a/net/wireless/reg.c +++ b/net/wireless/reg.c @@ -343,9 +343,9 @@ static int ignore_request(struct wiphy *wiphy, enum reg_set_by set_by, return 0; return -EALREADY; } - if (WARN_ON(!is_alpha2_set(alpha2) || !is_an_alpha2(alpha2)), + if (WARN(!is_alpha2_set(alpha2) || !is_an_alpha2(alpha2), "Invalid Country IE regulatory hint passed " - "to the wireless core\n") + "to the wireless core\n")) return -EINVAL; /* We ignore Country IE hints for now, as we haven't yet * added the dot11MultiDomainCapabilityEnabled flag diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index 832b47c1de80..fb216c9adf86 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -315,9 +315,9 @@ static void xfrm_policy_kill(struct xfrm_policy *policy) return; } - spin_lock(&xfrm_policy_gc_lock); + spin_lock_bh(&xfrm_policy_gc_lock); hlist_add_head(&policy->bydst, &xfrm_policy_gc_list); - spin_unlock(&xfrm_policy_gc_lock); + spin_unlock_bh(&xfrm_policy_gc_lock); schedule_work(&xfrm_policy_gc_work); } @@ -817,6 +817,7 @@ int xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info) continue; hlist_del(&pol->bydst); hlist_del(&pol->byidx); + list_del(&pol->walk.all); write_unlock_bh(&xfrm_policy_lock); xfrm_audit_policy_delete(pol, 1, audit_info->loginuid, @@ -1251,6 +1252,8 @@ xfrm_tmpl_resolve_one(struct xfrm_policy *policy, struct flowi *fl, -EINVAL : -EAGAIN); xfrm_state_put(x); } + else if (error == -ESRCH) + error = -EAGAIN; if (!tmpl->optional) goto fail; diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index 4a8a1abb59ee..a278a6f3b991 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -1816,7 +1816,7 @@ static int copy_to_user_kmaddress(struct xfrm_kmaddress *k, struct sk_buff *skb) uk.family = k->family; uk.reserved = k->reserved; memcpy(&uk.local, &k->local, sizeof(uk.local)); - memcpy(&uk.remote, &k->local, sizeof(uk.remote)); + memcpy(&uk.remote, &k->remote, sizeof(uk.remote)); return nla_put(skb, XFRMA_KMADDRESS, sizeof(uk), &uk); } diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 5ed4cbf1e0e1..468fbc9016c7 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -198,10 +198,16 @@ cmd_modversions = \ fi; endif +ifdef CONFIG_64BIT +arch_bits = 64 +else +arch_bits = 32 +endif + ifdef CONFIG_FTRACE_MCOUNT_RECORD cmd_record_mcount = perl $(srctree)/scripts/recordmcount.pl \ - "$(ARCH)" "$(OBJDUMP)" "$(OBJCOPY)" "$(CC)" "$(LD)" "$(NM)" "$(RM)" \ - "$(MV)" "$(@)"; + "$(ARCH)" "$(arch_bits)" "$(OBJDUMP)" "$(OBJCOPY)" "$(CC)" "$(LD)" \ + "$(NM)" "$(RM)" "$(MV)" "$(@)"; endif define rule_cc_o_c diff --git a/scripts/Makefile.modpost b/scripts/Makefile.modpost index 9ee9783aea57..f4053dc7b5d6 100644 --- a/scripts/Makefile.modpost +++ b/scripts/Makefile.modpost @@ -82,7 +82,7 @@ modpost = scripts/mod/modpost \ $(if $(CONFIG_MODULE_SRCVERSION_ALL),-a,) \ $(if $(KBUILD_EXTMOD),-i,-o) $(kernelsymfile) \ $(if $(KBUILD_EXTMOD),-I $(modulesymfile)) \ - $(if $(KBUILD_EXTRA_SYMBOLS), $(patsubst %, -e %,$(EXTRA_SYMBOLS))) \ + $(if $(KBUILD_EXTRA_SYMBOLS), $(patsubst %, -e %,$(KBUILD_EXTRA_SYMBOLS))) \ $(if $(KBUILD_EXTMOD),-o $(modulesymfile)) \ $(if $(CONFIG_DEBUG_SECTION_MISMATCH),,-S) \ $(if $(CONFIG_MARKERS),-K $(kernelmarkersfile)) \ diff --git a/scripts/bootgraph.pl b/scripts/bootgraph.pl index 5e7316e5aa39..d2c61efc216f 100644 --- a/scripts/bootgraph.pl +++ b/scripts/bootgraph.pl @@ -37,7 +37,10 @@ # dmesg | perl scripts/bootgraph.pl > output.svg # -my %start, %end; +use strict; + +my %start; +my %end; my $done = 0; my $maxtime = 0; my $firsttime = 100; @@ -105,18 +108,20 @@ my $threshold = ($maxtime - $firsttime) / 60.0; my $stylecounter = 0; my %rows; my $rowscount = 1; -while (($key,$value) = each %start) { +my @initcalls = sort { $start{$a} <=> $start{$b} } keys(%start); +my $key; +foreach $key (@initcalls) { my $duration = $end{$key} - $start{$key}; if ($duration >= $threshold) { - my $s, $s2, $e, $y; - $pid = $pids{$key}; + my ($s, $s2, $e, $w, $y, $y2, $style); + my $pid = $pids{$key}; if (!defined($rows{$pid})) { $rows{$pid} = $rowscount; $rowscount = $rowscount + 1; } - $s = ($value - $firsttime) * $mult; + $s = ($start{$key} - $firsttime) * $mult; $s2 = $s + 6; $e = ($end{$key} - $firsttime) * $mult; $w = $e - $s; @@ -140,9 +145,9 @@ while (($key,$value) = each %start) { my $time = $firsttime; my $step = ($maxtime - $firsttime) / 15; while ($time < $maxtime) { - my $s2 = ($time - $firsttime) * $mult; + my $s3 = ($time - $firsttime) * $mult; my $tm = int($time * 100) / 100.0; - print "$tm\n"; + print "$tm\n"; $time = $time + $step; } diff --git a/scripts/checksyscalls.sh b/scripts/checksyscalls.sh index 41564b142c04..60d00d1c4eee 100755 --- a/scripts/checksyscalls.sh +++ b/scripts/checksyscalls.sh @@ -113,10 +113,10 @@ EOF } syscall_list() { -sed -n -e '/^\#define/ { s/[^_]*__NR_\([^[:space:]]*\).*/\ +sed -n -e '/^\#define/ s/[^_]*__NR_\([^[:space:]]*\).*/\ \#if !defined \(__NR_\1\) \&\& !defined \(__IGNORE_\1\)\ \#warning syscall \1 not implemented\ -\#endif/p }' $1 +\#endif/p' $1 } (ignore_list && syscall_list ${srctree}/arch/x86/include/asm/unistd_32.h) | \ diff --git a/scripts/headers_check.pl b/scripts/headers_check.pl index 15d53a6b1a1f..488a3b1f760f 100644 --- a/scripts/headers_check.pl +++ b/scripts/headers_check.pl @@ -1,4 +1,4 @@ -#!/usr/bin/perl +#!/usr/bin/perl -w # # headers_check.pl execute a number of trivial consistency checks # @@ -17,7 +17,6 @@ # 2) TODO: check for leaked CONFIG_ symbols use strict; -use warnings; my ($dir, $arch, @files) = @ARGV; @@ -27,14 +26,15 @@ my $lineno = 0; my $filename; foreach my $file (@files) { + local *FH; $filename = $file; - open(my $fh, '<', "$filename") or die "$filename: $!\n"; + open(FH, "<$filename") or die "$filename: $!\n"; $lineno = 0; - while ($line = <$fh>) { + while ($line = ) { $lineno++; check_include(); } - close $fh; + close FH; } exit $ret; diff --git a/scripts/headers_install.pl b/scripts/headers_install.pl index 68591cd08731..7d2b4146e02f 100644 --- a/scripts/headers_install.pl +++ b/scripts/headers_install.pl @@ -1,4 +1,4 @@ -#!/usr/bin/perl +#!/usr/bin/perl -w # # headers_install prepare the listed header files for use in # user space and copy the files to their destination. @@ -17,28 +17,29 @@ # 3) Drop all sections defined out by __KERNEL__ (using unifdef) use strict; -use warnings; my ($readdir, $installdir, $arch, @files) = @ARGV; my $unifdef = "scripts/unifdef -U__KERNEL__"; foreach my $file (@files) { + local *INFILE; + local *OUTFILE; my $tmpfile = "$installdir/$file.tmp"; - open(my $infile, '<', "$readdir/$file") + open(INFILE, "<$readdir/$file") or die "$readdir/$file: $!\n"; - open(my $outfile, '>', "$tmpfile") or die "$tmpfile: $!\n"; - while (my $line = <$infile>) { + open(OUTFILE, ">$tmpfile") or die "$tmpfile: $!\n"; + while (my $line = ) { $line =~ s/([\s(])__user\s/$1/g; $line =~ s/([\s(])__force\s/$1/g; $line =~ s/([\s(])__iomem\s/$1/g; $line =~ s/\s__attribute_const__\s/ /g; $line =~ s/\s__attribute_const__$//g; $line =~ s/^#include //; - printf $outfile "%s", $line; + printf OUTFILE "%s", $line; } - close $outfile; - close $infile; + close OUTFILE; + close INFILE; system $unifdef . " $tmpfile > $installdir/$file"; unlink $tmpfile; } diff --git a/scripts/kernel-doc b/scripts/kernel-doc index 44ee94d2ab76..d27aad78e1d8 100755 --- a/scripts/kernel-doc +++ b/scripts/kernel-doc @@ -378,6 +378,10 @@ sub dump_section { # print STDERR "parameter def '$1' = '$contents'\n"; $name = $1; $parameterdescs{$name} = $contents; + } elsif ($name eq "@\.\.\.") { +# print STDERR "parameter def '...' = '$contents'\n"; + $name = "..."; + $parameterdescs{$name} = $contents; } else { # print STDERR "other section '$name' = '$contents'\n"; if (defined($sections{$name}) && ($sections{$name} ne "")) { @@ -1588,12 +1592,12 @@ sub push_parameter($$$) { if ($type eq "" && $param =~ /\.\.\.$/) { - $type=""; - $parameterdescs{$param} = "variable arguments"; + if (!defined $parameterdescs{$param} || $parameterdescs{$param} eq "") { + $parameterdescs{$param} = "variable arguments"; + } } elsif ($type eq "" && ($param eq "" or $param eq "void")) { - $type=""; $param="void"; $parameterdescs{void} = "no arguments"; } @@ -1648,7 +1652,7 @@ sub dump_function($$) { $prototype =~ s/^noinline +//; $prototype =~ s/__devinit +//; $prototype =~ s/__init +//; - $prototype =~ s/^#define\s+//; #ak added + $prototype =~ s/^#\s*define\s+//; #ak added $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//; # Yes, this truly is vile. We are looking for: @@ -1764,13 +1768,13 @@ sub process_state3_function($$) { $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line - if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#define/)) { + if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#\s*define/)) { # do nothing } elsif ($x =~ /([^\{]*)/) { $prototype .= $1; } - if (($x =~ /\{/) || ($x =~ /\#define/) || ($x =~ /;/)) { + if (($x =~ /\{/) || ($x =~ /\#\s*define/) || ($x =~ /;/)) { $prototype =~ s@/\*.*?\*/@@gos; # strip comments. $prototype =~ s@[\r\n]+@ @gos; # strip newlines/cr's. $prototype =~ s@^\s+@@gos; # strip leading spaces diff --git a/scripts/mod/sumversion.c b/scripts/mod/sumversion.c index d9cc6901d680..aadc5223dcdb 100644 --- a/scripts/mod/sumversion.c +++ b/scripts/mod/sumversion.c @@ -290,6 +290,15 @@ static int parse_file(const char *fname, struct md4_ctx *md) release_file(file, len); return 1; } +/* Check whether the file is a static library or not */ +static int is_static_library(const char *objfile) +{ + int len = strlen(objfile); + if (objfile[len - 2] == '.' && objfile[len - 1] == 'a') + return 1; + else + return 0; +} /* We have dir/file.o. Open dir/.file.o.cmd, look for deps_ line to * figure out source file. */ @@ -420,7 +429,8 @@ void get_src_version(const char *modname, char sum[], unsigned sumlen) while ((fname = strsep(&sources, " ")) != NULL) { if (!*fname) continue; - if (!parse_source_files(fname, &md)) + if (!(is_static_library(fname)) && + !parse_source_files(fname, &md)) goto release; } diff --git a/scripts/package/builddeb b/scripts/package/builddeb index ba6bf5d5abf9..1264b8e2829d 100644 --- a/scripts/package/builddeb +++ b/scripts/package/builddeb @@ -15,15 +15,18 @@ set -e version=$KERNELRELEASE revision=`cat .version` tmpdir="$objtree/debian/tmp" +fwdir="$objtree/debian/fwtmp" packagename=linux-$version +fwpackagename=linux-firmware-image if [ "$ARCH" == "um" ] ; then packagename=user-mode-linux-$version fi # Setup the directory structure -rm -rf "$tmpdir" +rm -rf "$tmpdir" "$fwdir" mkdir -p "$tmpdir/DEBIAN" "$tmpdir/lib" "$tmpdir/boot" +mkdir -p "$fwdir/DEBIAN" "$fwdir/lib" if [ "$ARCH" == "um" ] ; then mkdir -p "$tmpdir/usr/lib/uml/modules/$version" "$tmpdir/usr/share/doc/$packagename" "$tmpdir/usr/bin" fi @@ -107,6 +110,7 @@ Standards-Version: 3.6.1 Package: $packagename Provides: kernel-image-$version, linux-image-$version +Suggests: $fwpackagename Architecture: any Description: Linux kernel, version $version This package contains the Linux kernel, modules and corresponding other @@ -118,8 +122,24 @@ fi chown -R root:root "$tmpdir" chmod -R go-w "$tmpdir" +# Do we have firmware? Move it out of the way and build it into a package. +if [ -e "$tmpdir/lib/firmware" ]; then + mv "$tmpdir/lib/firmware" "$fwdir/lib/" + + cat <> debian/control + +Package: $fwpackagename +Architecture: all +Description: Linux kernel firmware, version $version + This package contains firmware from the Linux kernel, version $version +EOF + + dpkg-gencontrol -isp -p$fwpackagename -P"$fwdir" + dpkg --build "$fwdir" .. +fi + # Perform the final magic -dpkg-gencontrol -isp +dpkg-gencontrol -isp -p$packagename dpkg --build "$tmpdir" .. exit 0 diff --git a/scripts/package/mkspec b/scripts/package/mkspec index ffd61fe0c1ad..2500886fb90a 100755 --- a/scripts/package/mkspec +++ b/scripts/package/mkspec @@ -57,15 +57,17 @@ fi echo "%build" if ! $PREBUILT; then -echo "make clean && make %{_smp_mflags}" +echo "make clean && make %{?_smp_mflags}" echo "" fi echo "%install" echo "%ifarch ia64" echo 'mkdir -p $RPM_BUILD_ROOT/boot/efi $RPM_BUILD_ROOT/lib/modules' +echo 'mkdir -p $RPM_BUILD_ROOT/lib/firmware' echo "%else" echo 'mkdir -p $RPM_BUILD_ROOT/boot $RPM_BUILD_ROOT/lib/modules' +echo 'mkdir -p $RPM_BUILD_ROOT/lib/firmware' echo "%endif" echo 'INSTALL_MOD_PATH=$RPM_BUILD_ROOT make %{_smp_mflags} modules_install' @@ -92,5 +94,6 @@ echo "%files" echo '%defattr (-, root, root)' echo "%dir /lib/modules" echo "/lib/modules/$KERNELRELEASE" +echo "/lib/firmware" echo "/boot/*" echo "" diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl index f56d760bd589..6b9fe3eb8360 100755 --- a/scripts/recordmcount.pl +++ b/scripts/recordmcount.pl @@ -106,7 +106,13 @@ if ($#ARGV < 6) { exit(1); } -my ($arch, $objdump, $objcopy, $cc, $ld, $nm, $rm, $mv, $inputfile) = @ARGV; +my ($arch, $bits, $objdump, $objcopy, $cc, + $ld, $nm, $rm, $mv, $inputfile) = @ARGV; + +# Acceptable sections to record. +my %text_sections = ( + ".text" => 1, +); $objdump = "objdump" if ((length $objdump) == 0); $objcopy = "objcopy" if ((length $objcopy) == 0); @@ -129,8 +135,16 @@ my $function_regex; # Find the name of a function # (return offset and func name) my $mcount_regex; # Find the call site to mcount (return offset) +if ($arch eq "x86") { + if ($bits == 64) { + $arch = "x86_64"; + } else { + $arch = "i386"; + } +} + if ($arch eq "x86_64") { - $section_regex = "Disassembly of section"; + $section_regex = "Disassembly of section\\s+(\\S+):"; $function_regex = "^([0-9a-fA-F]+)\\s+<(.*?)>:"; $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\smcount([+-]0x[0-9a-zA-Z]+)?\$"; $type = ".quad"; @@ -142,7 +156,7 @@ if ($arch eq "x86_64") { $cc .= " -m64"; } elsif ($arch eq "i386") { - $section_regex = "Disassembly of section"; + $section_regex = "Disassembly of section\\s+(\\S+):"; $function_regex = "^([0-9a-fA-F]+)\\s+<(.*?)>:"; $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\smcount\$"; $type = ".long"; @@ -289,7 +303,13 @@ my $text; while () { # is it a section? if (/$section_regex/) { - $read_function = 1; + + # Only record text sections that we know are safe + if (defined($text_sections{$1})) { + $read_function = 1; + } else { + $read_function = 0; + } # print out any recorded offsets update_funcs() if ($text_found); diff --git a/scripts/setlocalversion b/scripts/setlocalversion index 83b75126c9f7..72d233528ade 100755 --- a/scripts/setlocalversion +++ b/scripts/setlocalversion @@ -9,11 +9,13 @@ usage() { cd "${1:-.}" || usage # Check for git and a git repo. -if head=`git rev-parse --verify HEAD 2>/dev/null`; then +if head=`git rev-parse --verify --short HEAD 2>/dev/null`; then # Do we have an untagged version? if git name-rev --tags HEAD | grep -E '^HEAD[[:space:]]+(.*~[0-9]*|undefined)$' > /dev/null; then if tag=`git describe 2>/dev/null`; then echo $tag | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}' + else + printf '%s%s' -g $head fi fi @@ -55,7 +57,7 @@ if rev=`svn info 2>/dev/null | grep '^Revision'`; then # Are there uncommitted changes? if [ $changes != 0 ]; then - printf -- '-svn%s%s%s' "$rev" -dirty "$changes" + printf -- '-svn%s%s' "$rev" -dirty else printf -- '-svn%s' "$rev" fi diff --git a/security/commoncap.c b/security/commoncap.c index 399bfdb9e2da..3976613db829 100644 --- a/security/commoncap.c +++ b/security/commoncap.c @@ -279,10 +279,10 @@ static int get_file_caps(struct linux_binprm *bprm) struct vfs_cap_data vcaps; struct inode *inode; - if (bprm->file->f_vfsmnt->mnt_flags & MNT_NOSUID) { - bprm_clear_caps(bprm); + bprm_clear_caps(bprm); + + if (bprm->file->f_vfsmnt->mnt_flags & MNT_NOSUID) return 0; - } dentry = dget(bprm->file->f_dentry); inode = dentry->d_inode; diff --git a/security/keys/internal.h b/security/keys/internal.h index b39f5c2e2c4b..239098f0fd76 100644 --- a/security/keys/internal.h +++ b/security/keys/internal.h @@ -107,6 +107,7 @@ extern key_ref_t search_process_keyrings(struct key_type *type, extern struct key *find_keyring_by_name(const char *name, bool skip_perm_check); +extern int install_user_keyrings(struct task_struct *tsk); extern int install_thread_keyring(struct task_struct *tsk); extern int install_process_keyring(struct task_struct *tsk); diff --git a/security/keys/process_keys.c b/security/keys/process_keys.c index 5be6d018759a..45b240af6dbe 100644 --- a/security/keys/process_keys.c +++ b/security/keys/process_keys.c @@ -40,7 +40,7 @@ struct key_user root_key_user = { /* * install user and user session keyrings for a particular UID */ -static int install_user_keyrings(struct task_struct *tsk) +int install_user_keyrings(struct task_struct *tsk) { struct user_struct *user = tsk->user; struct key *uid_keyring, *session_keyring; diff --git a/security/keys/request_key.c b/security/keys/request_key.c index ba32ca6469bd..abea08f87fe2 100644 --- a/security/keys/request_key.c +++ b/security/keys/request_key.c @@ -74,6 +74,10 @@ static int call_sbin_request_key(struct key_construction *cons, kenter("{%d},{%d},%s", key->serial, authkey->serial, op); + ret = install_user_keyrings(tsk); + if (ret < 0) + goto error_alloc; + /* allocate a new session keyring */ sprintf(desc, "_req.%u", key->serial); diff --git a/security/security.c b/security/security.c index 255b08559b2b..c0acfa7177e5 100644 --- a/security/security.c +++ b/security/security.c @@ -198,14 +198,23 @@ int security_settime(struct timespec *ts, struct timezone *tz) int security_vm_enough_memory(long pages) { + WARN_ON(current->mm == NULL); return security_ops->vm_enough_memory(current->mm, pages); } int security_vm_enough_memory_mm(struct mm_struct *mm, long pages) { + WARN_ON(mm == NULL); return security_ops->vm_enough_memory(mm, pages); } +int security_vm_enough_memory_kern(long pages) +{ + /* If current->mm is a kernel thread then we will pass NULL, + for this specific case that is fine */ + return security_ops->vm_enough_memory(current->mm, pages); +} + int security_bprm_alloc(struct linux_binprm *bprm) { return security_ops->bprm_alloc_security(bprm); diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 3e3fde7c1d2b..f85597a4d733 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -2126,14 +2126,16 @@ static inline void flush_unauthorized_files(struct files_struct *files) tty = get_current_tty(); if (tty) { file_list_lock(); - file = list_entry(tty->tty_files.next, typeof(*file), f_u.fu_list); - if (file) { + if (!list_empty(&tty->tty_files)) { + struct inode *inode; + /* Revalidate access to controlling tty. Use inode_has_perm on the tty inode directly rather than using file_has_perm, as this particular open file may belong to another process and we are only interested in the inode-based check here. */ - struct inode *inode = file->f_path.dentry->d_inode; + file = list_first_entry(&tty->tty_files, struct file, f_u.fu_list); + inode = file->f_path.dentry->d_inode; if (inode_has_perm(current, inode, FILE__READ | FILE__WRITE, NULL)) { drop_tty = 1; diff --git a/sound/aoa/soundbus/core.c b/sound/aoa/soundbus/core.c index f84f3e505788..fa8ab2815a98 100644 --- a/sound/aoa/soundbus/core.c +++ b/sound/aoa/soundbus/core.c @@ -176,7 +176,7 @@ int soundbus_add_one(struct soundbus_dev *dev) return -EINVAL; } - snprintf(dev->ofdev.dev.bus_id, BUS_ID_SIZE, "soundbus:%x", ++devcount); + dev_set_name(&dev->ofdev.dev, "soundbus:%x", ++devcount); dev->ofdev.dev.bus = &soundbus_bus_type; return of_device_register(&dev->ofdev); } diff --git a/sound/core/control.c b/sound/core/control.c index 6d71f9a7ccbb..636b3b52ef8b 100644 --- a/sound/core/control.c +++ b/sound/core/control.c @@ -113,7 +113,6 @@ static int snd_ctl_release(struct inode *inode, struct file *file) unsigned int idx; ctl = file->private_data; - fasync_helper(-1, file, 0, &ctl->fasync); file->private_data = NULL; card = ctl->card; write_lock_irqsave(&card->ctl_files_rwlock, flags); @@ -225,8 +224,13 @@ struct snd_kcontrol *snd_ctl_new1(const struct snd_kcontrol_new *ncontrol, kctl.id.iface = ncontrol->iface; kctl.id.device = ncontrol->device; kctl.id.subdevice = ncontrol->subdevice; - if (ncontrol->name) + if (ncontrol->name) { strlcpy(kctl.id.name, ncontrol->name, sizeof(kctl.id.name)); + if (strcmp(ncontrol->name, kctl.id.name) != 0) + snd_printk(KERN_WARNING + "Control name '%s' truncated to '%s'\n", + ncontrol->name, kctl.id.name); + } kctl.id.index = ncontrol->index; kctl.count = ncontrol->count ? ncontrol->count : 1; access = ncontrol->access == 0 ? SNDRV_CTL_ELEM_ACCESS_READWRITE : diff --git a/sound/core/init.c b/sound/core/init.c index ef2352c2e451..b47ff8b44be8 100644 --- a/sound/core/init.c +++ b/sound/core/init.c @@ -264,8 +264,11 @@ static int snd_disconnect_release(struct inode *inode, struct file *file) } spin_unlock(&shutdown_lock); - if (likely(df)) + if (likely(df)) { + if ((file->f_flags & FASYNC) && df->disconnected_f_op->fasync) + df->disconnected_f_op->fasync(-1, file, 0); return df->disconnected_f_op->release(inode, file); + } panic("%s(%p, %p) failed!", __func__, inode, file); } diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index aef18682c035..a789efc9df39 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -2169,7 +2169,6 @@ static int snd_pcm_release(struct inode *inode, struct file *file) if (snd_BUG_ON(!substream)) return -ENXIO; pcm = substream->pcm; - fasync_helper(-1, file, 0, &substream->runtime->fasync); mutex_lock(&pcm->open_mutex); snd_pcm_release_substream(substream); kfree(pcm_file); diff --git a/sound/core/rawmidi.c b/sound/core/rawmidi.c index c4995c9f5730..39672f68ce5d 100644 --- a/sound/core/rawmidi.c +++ b/sound/core/rawmidi.c @@ -148,6 +148,8 @@ static int snd_rawmidi_runtime_free(struct snd_rawmidi_substream *substream) static inline void snd_rawmidi_output_trigger(struct snd_rawmidi_substream *substream,int up) { + if (!substream->opened) + return; if (up) { tasklet_hi_schedule(&substream->runtime->tasklet); } else { @@ -158,6 +160,8 @@ static inline void snd_rawmidi_output_trigger(struct snd_rawmidi_substream *subs static void snd_rawmidi_input_trigger(struct snd_rawmidi_substream *substream, int up) { + if (!substream->opened) + return; substream->ops->trigger(substream, up); if (!up && substream->runtime->event) tasklet_kill(&substream->runtime->tasklet); @@ -857,6 +861,8 @@ int snd_rawmidi_receive(struct snd_rawmidi_substream *substream, int result = 0, count1; struct snd_rawmidi_runtime *runtime = substream->runtime; + if (!substream->opened) + return -EBADFD; if (runtime->buffer == NULL) { snd_printd("snd_rawmidi_receive: input is not active!!!\n"); return -EINVAL; @@ -1126,6 +1132,8 @@ int snd_rawmidi_transmit_ack(struct snd_rawmidi_substream *substream, int count) int snd_rawmidi_transmit(struct snd_rawmidi_substream *substream, unsigned char *buffer, int count) { + if (!substream->opened) + return -EBADFD; count = snd_rawmidi_transmit_peek(substream, buffer, count); if (count < 0) return count; diff --git a/sound/core/timer.c b/sound/core/timer.c index e582face89d2..c584408c9f17 100644 --- a/sound/core/timer.c +++ b/sound/core/timer.c @@ -1263,7 +1263,6 @@ static int snd_timer_user_release(struct inode *inode, struct file *file) if (file->private_data) { tu = file->private_data; file->private_data = NULL; - fasync_helper(-1, file, 0, &tu->fasync); if (tu->timeri) snd_timer_close(tu->timeri); kfree(tu->queue); diff --git a/sound/drivers/ml403-ac97cr.c b/sound/drivers/ml403-ac97cr.c index ecdbeb6d3603..7783843ca9ae 100644 --- a/sound/drivers/ml403-ac97cr.c +++ b/sound/drivers/ml403-ac97cr.c @@ -1153,7 +1153,7 @@ snd_ml403_ac97cr_create(struct snd_card *card, struct platform_device *pfdev, /* get irq */ irq = platform_get_irq(pfdev, 0); if (request_irq(irq, snd_ml403_ac97cr_irq, IRQF_DISABLED, - pfdev->dev.bus_id, (void *)ml403_ac97cr)) { + dev_name(&pfdev->dev), (void *)ml403_ac97cr)) { snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": " "unable to grab IRQ %d\n", irq); @@ -1166,7 +1166,7 @@ snd_ml403_ac97cr_create(struct snd_card *card, struct platform_device *pfdev, ml403_ac97cr->irq); irq = platform_get_irq(pfdev, 1); if (request_irq(irq, snd_ml403_ac97cr_irq, IRQF_DISABLED, - pfdev->dev.bus_id, (void *)ml403_ac97cr)) { + dev_name(&pfdev->dev), (void *)ml403_ac97cr)) { snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": " "unable to grab IRQ %d\n", irq); diff --git a/sound/drivers/pcsp/pcsp_input.c b/sound/drivers/pcsp/pcsp_input.c index cd9b83e7f7d1..0444cdeb4bec 100644 --- a/sound/drivers/pcsp/pcsp_input.c +++ b/sound/drivers/pcsp/pcsp_input.c @@ -24,13 +24,13 @@ static void pcspkr_do_sound(unsigned int count) spin_lock_irqsave(&i8253_lock, flags); if (count) { - /* enable counter 2 */ - outb_p(inb_p(0x61) | 3, 0x61); /* set command for counter 2, 2 byte write */ outb_p(0xB6, 0x43); /* select desired HZ */ outb_p(count & 0xff, 0x42); outb((count >> 8) & 0xff, 0x42); + /* enable counter 2 */ + outb_p(inb_p(0x61) | 3, 0x61); } else { /* disable counter 2 */ outb(inb_p(0x61) & 0xFC, 0x61); diff --git a/sound/isa/Kconfig b/sound/isa/Kconfig index 660beb41f767..ce0aa044e274 100644 --- a/sound/isa/Kconfig +++ b/sound/isa/Kconfig @@ -211,7 +211,7 @@ config SND_GUSCLASSIC config SND_GUSEXTREME tristate "Gravis UltraSound Extreme" - select SND_HWDEP + select SND_OPL3_LIB select SND_MPU401_UART select SND_PCM help diff --git a/sound/isa/ad1848/ad1848.c b/sound/isa/ad1848/ad1848.c index b68d20edc20f..223a6c038819 100644 --- a/sound/isa/ad1848/ad1848.c +++ b/sound/isa/ad1848/ad1848.c @@ -70,15 +70,15 @@ static int __devinit snd_ad1848_match(struct device *dev, unsigned int n) return 0; if (port[n] == SNDRV_AUTO_PORT) { - snd_printk(KERN_ERR "%s: please specify port\n", dev->bus_id); + dev_err(dev, "please specify port\n"); return 0; } if (irq[n] == SNDRV_AUTO_IRQ) { - snd_printk(KERN_ERR "%s: please specify irq\n", dev->bus_id); + dev_err(dev, "please specify irq\n"); return 0; } if (dma1[n] == SNDRV_AUTO_DMA) { - snd_printk(KERN_ERR "%s: please specify dma1\n", dev->bus_id); + dev_err(dev, "please specify dma1\n"); return 0; } return 1; diff --git a/sound/isa/adlib.c b/sound/isa/adlib.c index efa8c80d05b6..374b7177e111 100644 --- a/sound/isa/adlib.c +++ b/sound/isa/adlib.c @@ -36,7 +36,7 @@ static int __devinit snd_adlib_match(struct device *dev, unsigned int n) return 0; if (port[n] == SNDRV_AUTO_PORT) { - snd_printk(KERN_ERR "%s: please specify port\n", dev->bus_id); + dev_err(dev, "please specify port\n"); return 0; } return 1; @@ -55,13 +55,13 @@ static int __devinit snd_adlib_probe(struct device *dev, unsigned int n) card = snd_card_new(index[n], id[n], THIS_MODULE, 0); if (!card) { - snd_printk(KERN_ERR "%s: could not create card\n", dev->bus_id); + dev_err(dev, "could not create card\n"); return -EINVAL; } card->private_data = request_region(port[n], 4, CRD_NAME); if (!card->private_data) { - snd_printk(KERN_ERR "%s: could not grab ports\n", dev->bus_id); + dev_err(dev, "could not grab ports\n"); error = -EBUSY; goto out; } @@ -73,13 +73,13 @@ static int __devinit snd_adlib_probe(struct device *dev, unsigned int n) error = snd_opl3_create(card, port[n], port[n] + 2, OPL3_HW_AUTO, 1, &opl3); if (error < 0) { - snd_printk(KERN_ERR "%s: could not create OPL\n", dev->bus_id); + dev_err(dev, "could not create OPL\n"); goto out; } error = snd_opl3_hwdep_new(opl3, 0, 0, NULL); if (error < 0) { - snd_printk(KERN_ERR "%s: could not create FM\n", dev->bus_id); + dev_err(dev, "could not create FM\n"); goto out; } @@ -87,7 +87,7 @@ static int __devinit snd_adlib_probe(struct device *dev, unsigned int n) error = snd_card_register(card); if (error < 0) { - snd_printk(KERN_ERR "%s: could not register card\n", dev->bus_id); + dev_err(dev, "could not register card\n"); goto out; } diff --git a/sound/isa/cs423x/cs4231.c b/sound/isa/cs423x/cs4231.c index ddd289120aa8..f019d449e2d6 100644 --- a/sound/isa/cs423x/cs4231.c +++ b/sound/isa/cs423x/cs4231.c @@ -74,15 +74,15 @@ static int __devinit snd_cs4231_match(struct device *dev, unsigned int n) return 0; if (port[n] == SNDRV_AUTO_PORT) { - snd_printk(KERN_ERR "%s: please specify port\n", dev->bus_id); + dev_err(dev, "please specify port\n"); return 0; } if (irq[n] == SNDRV_AUTO_IRQ) { - snd_printk(KERN_ERR "%s: please specify irq\n", dev->bus_id); + dev_err(dev, "please specify irq\n"); return 0; } if (dma1[n] == SNDRV_AUTO_DMA) { - snd_printk(KERN_ERR "%s: please specify dma1\n", dev->bus_id); + dev_err(dev, "please specify dma1\n"); return 0; } return 1; @@ -133,7 +133,7 @@ static int __devinit snd_cs4231_probe(struct device *dev, unsigned int n) mpu_port[n], 0, mpu_irq[n], mpu_irq[n] >= 0 ? IRQF_DISABLED : 0, NULL) < 0) - printk(KERN_WARNING "%s: MPU401 not detected\n", dev->bus_id); + dev_warn(dev, "MPU401 not detected\n"); } snd_card_set_dev(card, dev); diff --git a/sound/isa/cs423x/cs4236.c b/sound/isa/cs423x/cs4236.c index 91f9c15d3e30..019c9401663e 100644 --- a/sound/isa/cs423x/cs4236.c +++ b/sound/isa/cs423x/cs4236.c @@ -488,19 +488,19 @@ static int __devinit snd_cs423x_isa_match(struct device *pdev, return 0; if (port[dev] == SNDRV_AUTO_PORT) { - snd_printk(KERN_ERR "%s: please specify port\n", pdev->bus_id); + dev_err(pdev, "please specify port\n"); return 0; } if (cport[dev] == SNDRV_AUTO_PORT) { - snd_printk(KERN_ERR "%s: please specify cport\n", pdev->bus_id); + dev_err(pdev, "please specify cport\n"); return 0; } if (irq[dev] == SNDRV_AUTO_IRQ) { - snd_printk(KERN_ERR "%s: please specify irq\n", pdev->bus_id); + dev_err(pdev, "please specify irq\n"); return 0; } if (dma1[dev] == SNDRV_AUTO_DMA) { - snd_printk(KERN_ERR "%s: please specify dma1\n", pdev->bus_id); + dev_err(pdev, "please specify dma1\n"); return 0; } return 1; diff --git a/sound/isa/es1688/es1688.c b/sound/isa/es1688/es1688.c index f88639ea64b2..b46377139cf8 100644 --- a/sound/isa/es1688/es1688.c +++ b/sound/isa/es1688/es1688.c @@ -88,16 +88,14 @@ static int __devinit snd_es1688_legacy_create(struct snd_card *card, if (irq[n] == SNDRV_AUTO_IRQ) { irq[n] = snd_legacy_find_free_irq(possible_irqs); if (irq[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free IRQ\n", - dev->bus_id); + dev_err(dev, "unable to find a free IRQ\n"); return -EBUSY; } } if (dma8[n] == SNDRV_AUTO_DMA) { dma8[n] = snd_legacy_find_free_dma(possible_dmas); if (dma8[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free DMA\n", - dev->bus_id); + dev_err(dev, "unable to find a free DMA\n"); return -EBUSY; } } @@ -147,8 +145,7 @@ static int __devinit snd_es1688_probe(struct device *dev, unsigned int n) if (snd_opl3_create(card, chip->port, chip->port + 2, OPL3_HW_OPL3, 0, &opl3) < 0) - printk(KERN_WARNING "%s: opl3 not detected at 0x%lx\n", - dev->bus_id, chip->port); + dev_warn(dev, "opl3 not detected at 0x%lx\n", chip->port); else { error = snd_opl3_hwdep_new(opl3, 0, 1, NULL); if (error < 0) diff --git a/sound/isa/gus/gusclassic.c b/sound/isa/gus/gusclassic.c index 8f914b37bf89..426532a4d730 100644 --- a/sound/isa/gus/gusclassic.c +++ b/sound/isa/gus/gusclassic.c @@ -90,24 +90,21 @@ static int __devinit snd_gusclassic_create(struct snd_card *card, if (irq[n] == SNDRV_AUTO_IRQ) { irq[n] = snd_legacy_find_free_irq(possible_irqs); if (irq[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free IRQ\n", - dev->bus_id); + dev_err(dev, "unable to find a free IRQ\n"); return -EBUSY; } } if (dma1[n] == SNDRV_AUTO_DMA) { dma1[n] = snd_legacy_find_free_dma(possible_dmas); if (dma1[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free DMA1\n", - dev->bus_id); + dev_err(dev, "unable to find a free DMA1\n"); return -EBUSY; } } if (dma2[n] == SNDRV_AUTO_DMA) { dma2[n] = snd_legacy_find_free_dma(possible_dmas); if (dma2[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free DMA2\n", - dev->bus_id); + dev_err(dev, "unable to find a free DMA2\n"); return -EBUSY; } } @@ -174,8 +171,8 @@ static int __devinit snd_gusclassic_probe(struct device *dev, unsigned int n) error = -ENODEV; if (gus->max_flag || gus->ess_flag) { - snd_printk(KERN_ERR "%s: GUS Classic or ACE soundcard was " - "not detected at 0x%lx\n", dev->bus_id, gus->gf1.port); + dev_err(dev, "GUS Classic or ACE soundcard was " + "not detected at 0x%lx\n", gus->gf1.port); goto out; } diff --git a/sound/isa/gus/gusextreme.c b/sound/isa/gus/gusextreme.c index da13185eb0a0..7ad4c3b41a84 100644 --- a/sound/isa/gus/gusextreme.c +++ b/sound/isa/gus/gusextreme.c @@ -106,16 +106,14 @@ static int __devinit snd_gusextreme_es1688_create(struct snd_card *card, if (irq[n] == SNDRV_AUTO_IRQ) { irq[n] = snd_legacy_find_free_irq(possible_irqs); if (irq[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free IRQ " - "for ES1688\n", dev->bus_id); + dev_err(dev, "unable to find a free IRQ for ES1688\n"); return -EBUSY; } } if (dma8[n] == SNDRV_AUTO_DMA) { dma8[n] = snd_legacy_find_free_dma(possible_dmas); if (dma8[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free DMA " - "for ES1688\n", dev->bus_id); + dev_err(dev, "unable to find a free DMA for ES1688\n"); return -EBUSY; } } @@ -143,16 +141,14 @@ static int __devinit snd_gusextreme_gus_card_create(struct snd_card *card, if (gf1_irq[n] == SNDRV_AUTO_IRQ) { gf1_irq[n] = snd_legacy_find_free_irq(possible_irqs); if (gf1_irq[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free IRQ " - "for GF1\n", dev->bus_id); + dev_err(dev, "unable to find a free IRQ for GF1\n"); return -EBUSY; } } if (dma1[n] == SNDRV_AUTO_DMA) { dma1[n] = snd_legacy_find_free_dma(possible_dmas); if (dma1[n] < 0) { - snd_printk(KERN_ERR "%s: unable to find a free DMA " - "for GF1\n", dev->bus_id); + dev_err(dev, "unable to find a free DMA for GF1\n"); return -EBUSY; } } @@ -278,8 +274,8 @@ static int __devinit snd_gusextreme_probe(struct device *dev, unsigned int n) error = -ENODEV; if (!gus->ess_flag) { - snd_printk(KERN_ERR "%s: GUS Extreme soundcard was not " - "detected at 0x%lx\n", dev->bus_id, gus->gf1.port); + dev_err(dev, "GUS Extreme soundcard was not " + "detected at 0x%lx\n", gus->gf1.port); goto out; } gus->codec_flag = 1; @@ -310,8 +306,7 @@ static int __devinit snd_gusextreme_probe(struct device *dev, unsigned int n) if (snd_opl3_create(card, es1688->port, es1688->port + 2, OPL3_HW_OPL3, 0, &opl3) < 0) - printk(KERN_ERR "%s: opl3 not detected at 0x%lx\n", - dev->bus_id, es1688->port); + dev_warn(dev, "opl3 not detected at 0x%lx\n", es1688->port); else { error = snd_opl3_hwdep_new(opl3, 0, 2, NULL); if (error < 0) diff --git a/sound/isa/sb/sb8.c b/sound/isa/sb/sb8.c index 336a34277907..667eccc676a4 100644 --- a/sound/isa/sb/sb8.c +++ b/sound/isa/sb/sb8.c @@ -85,11 +85,11 @@ static int __devinit snd_sb8_match(struct device *pdev, unsigned int dev) if (!enable[dev]) return 0; if (irq[dev] == SNDRV_AUTO_IRQ) { - snd_printk(KERN_ERR "%s: please specify irq\n", pdev->bus_id); + dev_err(pdev, "please specify irq\n"); return 0; } if (dma8[dev] == SNDRV_AUTO_DMA) { - snd_printk(KERN_ERR "%s: please specify dma8\n", pdev->bus_id); + dev_err(pdev, "please specify dma8\n"); return 0; } return 1; diff --git a/sound/oss/dmasound/dmasound.h b/sound/oss/dmasound/dmasound.h index 1cb13fe56ec4..1308d8d34186 100644 --- a/sound/oss/dmasound/dmasound.h +++ b/sound/oss/dmasound/dmasound.h @@ -235,7 +235,7 @@ struct sound_queue { */ int active; wait_queue_head_t action_queue, open_queue, sync_queue; - fmode_t open_mode; + int non_blocking; int busy, syncing, xruns, died; }; diff --git a/sound/oss/dmasound/dmasound_core.c b/sound/oss/dmasound/dmasound_core.c index b8239f3168fb..793b7f478433 100644 --- a/sound/oss/dmasound/dmasound_core.c +++ b/sound/oss/dmasound/dmasound_core.c @@ -603,7 +603,7 @@ static ssize_t sq_write(struct file *file, const char __user *src, size_t uLeft, while (uLeft) { while (write_sq.count >= write_sq.max_active) { sq_play(); - if (write_sq.open_mode & O_NONBLOCK) + if (write_sq.non_blocking) return uWritten > 0 ? uWritten : -EAGAIN; SLEEP(write_sq.action_queue); if (signal_pending(current)) @@ -718,7 +718,7 @@ static int sq_open2(struct sound_queue *sq, struct file *file, fmode_t mode, return rc; } - sq->open_mode = file->f_mode; + sq->non_blocking = file->f_flags & O_NONBLOCK; } return rc; } diff --git a/sound/oss/kahlua.c b/sound/oss/kahlua.c index eb9bc365530d..c180598f1710 100644 --- a/sound/oss/kahlua.c +++ b/sound/oss/kahlua.c @@ -1,7 +1,7 @@ /* * Initialisation code for Cyrix/NatSemi VSA1 softaudio * - * (C) Copyright 2003 Red Hat Inc + * (C) Copyright 2003 Red Hat Inc * * XpressAudio(tm) is used on the Cyrix MediaGX (now NatSemi Geode) systems. * The older version (VSA1) provides fairly good soundblaster emulation diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c index 6704acbca8c0..bd510eceff1f 100644 --- a/sound/pci/ac97/ac97_codec.c +++ b/sound/pci/ac97/ac97_codec.c @@ -1927,9 +1927,9 @@ static int snd_ac97_dev_register(struct snd_device *device) ac97->dev.bus = &ac97_bus_type; ac97->dev.parent = ac97->bus->card->dev; ac97->dev.release = ac97_device_release; - snprintf(ac97->dev.bus_id, BUS_ID_SIZE, "%d-%d:%s", - ac97->bus->card->number, ac97->num, - snd_ac97_get_short_name(ac97)); + dev_set_name(&ac97->dev, "%d-%d:%s", + ac97->bus->card->number, ac97->num, + snd_ac97_get_short_name(ac97)); if ((err = device_register(&ac97->dev)) < 0) { snd_printk(KERN_ERR "Can't register ac97 bus\n"); ac97->dev.bus = NULL; diff --git a/sound/pci/ad1889.c b/sound/pci/ad1889.c index 92f3a976ef2e..a7f38e63303f 100644 --- a/sound/pci/ad1889.c +++ b/sound/pci/ad1889.c @@ -932,7 +932,7 @@ snd_ad1889_create(struct snd_card *card, goto free_and_ret; chip->bar = pci_resource_start(pci, 0); - chip->iobase = ioremap_nocache(chip->bar, pci_resource_len(pci, 0)); + chip->iobase = pci_ioremap_bar(pci, 0); if (chip->iobase == NULL) { printk(KERN_ERR PFX "unable to reserve region.\n"); err = -EBUSY; diff --git a/sound/pci/atiixp.c b/sound/pci/atiixp.c index 085a52b8c807..226fe8237d31 100644 --- a/sound/pci/atiixp.c +++ b/sound/pci/atiixp.c @@ -1609,7 +1609,7 @@ static int __devinit snd_atiixp_create(struct snd_card *card, return err; } chip->addr = pci_resource_start(pci, 0); - chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0)); + chip->remap_addr = pci_ioremap_bar(pci, 0); if (chip->remap_addr == NULL) { snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); snd_atiixp_free(chip); diff --git a/sound/pci/atiixp_modem.c b/sound/pci/atiixp_modem.c index 2f106306c7fe..0e6e5cc1c501 100644 --- a/sound/pci/atiixp_modem.c +++ b/sound/pci/atiixp_modem.c @@ -1252,7 +1252,7 @@ static int __devinit snd_atiixp_create(struct snd_card *card, return err; } chip->addr = pci_resource_start(pci, 0); - chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0)); + chip->remap_addr = pci_ioremap_bar(pci, 0); if (chip->remap_addr == NULL) { snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); snd_atiixp_free(chip); diff --git a/sound/pci/au88x0/au88x0.c b/sound/pci/au88x0/au88x0.c index 68368e490074..a36d4d1fd419 100644 --- a/sound/pci/au88x0/au88x0.c +++ b/sound/pci/au88x0/au88x0.c @@ -180,8 +180,7 @@ snd_vortex_create(struct snd_card *card, struct pci_dev *pci, vortex_t ** rchip) if ((err = pci_request_regions(pci, CARD_NAME_SHORT)) != 0) goto regions_out; - chip->mmio = ioremap_nocache(pci_resource_start(pci, 0), - pci_resource_len(pci, 0)); + chip->mmio = pci_ioremap_bar(pci, 0); if (!chip->mmio) { printk(KERN_ERR "MMIO area remap failed.\n"); err = -ENOMEM; diff --git a/sound/pci/bt87x.c b/sound/pci/bt87x.c index 3aa8d973540a..1aa1c0402540 100644 --- a/sound/pci/bt87x.c +++ b/sound/pci/bt87x.c @@ -749,8 +749,7 @@ static int __devinit snd_bt87x_create(struct snd_card *card, pci_disable_device(pci); return err; } - chip->mmio = ioremap_nocache(pci_resource_start(pci, 0), - pci_resource_len(pci, 0)); + chip->mmio = pci_ioremap_bar(pci, 0); if (!chip->mmio) { snd_printk(KERN_ERR "cannot remap io memory\n"); err = -ENOMEM; diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c index ef9308f7c45b..192e7842e181 100644 --- a/sound/pci/cs4281.c +++ b/sound/pci/cs4281.c @@ -1382,8 +1382,8 @@ static int __devinit snd_cs4281_create(struct snd_card *card, chip->ba0_addr = pci_resource_start(pci, 0); chip->ba1_addr = pci_resource_start(pci, 1); - chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0)); - chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1)); + chip->ba0 = pci_ioremap_bar(pci, 0); + chip->ba1 = pci_ioremap_bar(pci, 1); if (!chip->ba0 || !chip->ba1) { snd_cs4281_free(chip); return -ENOMEM; diff --git a/sound/pci/cs5530.c b/sound/pci/cs5530.c index 7ff8b68e997e..6dea5b5cc774 100644 --- a/sound/pci/cs5530.c +++ b/sound/pci/cs5530.c @@ -2,7 +2,7 @@ * cs5530.c - Initialisation code for Cyrix/NatSemi VSA1 softaudio * * (C) Copyright 2007 Ash Willis - * (C) Copyright 2003 Red Hat Inc + * (C) Copyright 2003 Red Hat Inc * * This driver was ported (shamelessly ripped ;) from oss/kahlua.c but I did * mess with it a bit. The chip seems to have to have trouble with full duplex @@ -132,7 +132,7 @@ static int __devinit snd_cs5530_create(struct snd_card *card, } chip->pci_base = pci_resource_start(pci, 0); - mem = ioremap_nocache(chip->pci_base, pci_resource_len(pci, 0)); + mem = pci_ioremap_bar(pci, 0); if (mem == NULL) { kfree(chip); pci_disable_device(pci); diff --git a/sound/pci/emu10k1/emu10k1_main.c b/sound/pci/emu10k1/emu10k1_main.c index 2f283ea6ad9a..de5ee8f097f6 100644 --- a/sound/pci/emu10k1/emu10k1_main.c +++ b/sound/pci/emu10k1/emu10k1_main.c @@ -1464,6 +1464,7 @@ static struct snd_emu_chip_details emu_chip_details[] = { .ca0151_chip = 1, .spk71 = 1, .spdif_bug = 1, + .invert_shared_spdif = 1, /* digital/analog switch swapped */ .ac97_chip = 1} , {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102, .driver = "Audigy2", .name = "Audigy 2 ZS [SB0350]", @@ -1473,6 +1474,7 @@ static struct snd_emu_chip_details emu_chip_details[] = { .ca0151_chip = 1, .spk71 = 1, .spdif_bug = 1, + .invert_shared_spdif = 1, /* digital/analog switch swapped */ .ac97_chip = 1} , {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102, .driver = "Audigy2", .name = "Audigy 2 ZS [2001]", @@ -1482,6 +1484,7 @@ static struct snd_emu_chip_details emu_chip_details[] = { .ca0151_chip = 1, .spk71 = 1, .spdif_bug = 1, + .invert_shared_spdif = 1, /* digital/analog switch swapped */ .ac97_chip = 1} , /* Audigy 2 */ /* Tested by James@superbug.co.uk 3rd July 2005 */ diff --git a/sound/pci/hda/hda_beep.c b/sound/pci/hda/hda_beep.c index 9b77b3e0fa98..3ecd7e797dee 100644 --- a/sound/pci/hda/hda_beep.c +++ b/sound/pci/hda/hda_beep.c @@ -37,6 +37,9 @@ static void snd_hda_generate_beep(struct work_struct *work) container_of(work, struct hda_beep, beep_work); struct hda_codec *codec = beep->codec; + if (!beep->enabled) + return; + /* generate tone */ snd_hda_codec_write_cache(codec, beep->nid, 0, AC_VERB_SET_BEEP_CONTROL, beep->tone); @@ -85,6 +88,10 @@ int snd_hda_attach_beep_device(struct hda_codec *codec, int nid) snprintf(beep->phys, sizeof(beep->phys), "card%d/codec#%d/beep0", codec->bus->card->number, codec->addr); input_dev = input_allocate_device(); + if (!input_dev) { + kfree(beep); + return -ENOMEM; + } /* setup digital beep device */ input_dev->name = "HDA Digital PCBeep"; @@ -115,6 +122,7 @@ int snd_hda_attach_beep_device(struct hda_codec *codec, int nid) beep->nid = nid; beep->dev = input_dev; beep->codec = codec; + beep->enabled = 1; codec->beep = beep; INIT_WORK(&beep->beep_work, &snd_hda_generate_beep); diff --git a/sound/pci/hda/hda_beep.h b/sound/pci/hda/hda_beep.h index de4036e6e710..b9679f081cae 100644 --- a/sound/pci/hda/hda_beep.h +++ b/sound/pci/hda/hda_beep.h @@ -31,6 +31,7 @@ struct hda_beep { char phys[32]; int tone; int nid; + int enabled; struct work_struct beep_work; /* scheduled task for beep event */ }; diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index 6447754ae56e..eb9164176dab 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c @@ -64,6 +64,7 @@ static struct hda_vendor_id hda_vendor_ids[] = { { 0x14f1, "Conexant" }, { 0x17e8, "Chrontel" }, { 0x1854, "LG" }, + { 0x1aec, "Wolfson Microelectronics" }, { 0x434d, "C-Media" }, { 0x8384, "SigmaTel" }, {} /* terminator */ @@ -1435,12 +1436,12 @@ static void set_dig_out(struct hda_codec *codec, hda_nid_t nid, { hda_nid_t *d; - snd_hda_codec_write(codec, nid, 0, verb, val); + snd_hda_codec_write_cache(codec, nid, 0, verb, val); d = codec->slave_dig_outs; if (!d) return; for (; *d; d++) - snd_hda_codec_write(codec, *d, 0, verb, val); + snd_hda_codec_write_cache(codec, *d, 0, verb, val); } static inline void set_dig_out_convert(struct hda_codec *codec, hda_nid_t nid, diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 9f316c1b2790..35722ec920cb 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #include "hda_codec.h" @@ -397,6 +398,9 @@ struct azx { /* for pending irqs */ struct work_struct irq_pending_work; + + /* reboot notifier (for mysterious hangup problem at power-down) */ + struct notifier_block reboot_notifier; }; /* driver types */ @@ -1978,6 +1982,28 @@ static int azx_resume(struct pci_dev *pci) #endif /* CONFIG_PM */ +/* + * reboot notifier for hang-up problem at power-down + */ +static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) +{ + struct azx *chip = container_of(nb, struct azx, reboot_notifier); + azx_stop_chip(chip); + return NOTIFY_OK; +} + +static void azx_notifier_register(struct azx *chip) +{ + chip->reboot_notifier.notifier_call = azx_halt; + register_reboot_notifier(&chip->reboot_notifier); +} + +static void azx_notifier_unregister(struct azx *chip) +{ + if (chip->reboot_notifier.notifier_call) + unregister_reboot_notifier(&chip->reboot_notifier); +} + /* * destructor */ @@ -1985,6 +2011,8 @@ static int azx_free(struct azx *chip) { int i; + azx_notifier_unregister(chip); + if (chip->initialized) { azx_clear_irq_pending(chip); for (i = 0; i < chip->num_streams; i++) @@ -2158,7 +2186,7 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, } chip->addr = pci_resource_start(pci, 0); - chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); + chip->remap_addr = pci_ioremap_bar(pci, 0); if (chip->remap_addr == NULL) { snd_printk(KERN_ERR SFX "ioremap error\n"); err = -ENXIO; @@ -2348,6 +2376,7 @@ static int __devinit azx_probe(struct pci_dev *pci, pci_set_drvdata(pci, card); chip->running = 1; power_down_all_codecs(chip); + azx_notifier_register(chip); dev++; return err; diff --git a/sound/pci/hda/hda_proc.c b/sound/pci/hda/hda_proc.c index 743d77922bce..c39af986bff1 100644 --- a/sound/pci/hda/hda_proc.c +++ b/sound/pci/hda/hda_proc.c @@ -483,6 +483,8 @@ static void print_gpio(struct snd_info_buffer *buffer, (gpio & AC_GPIO_UNSOLICITED) ? 1 : 0, (gpio & AC_GPIO_WAKE) ? 1 : 0); max = gpio & AC_GPIO_IO_COUNT; + if (!max || max > 8) + return; enable = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_GPIO_MASK, 0); direction = snd_hda_codec_read(codec, nid, 0, diff --git a/sound/pci/hda/patch_analog.c b/sound/pci/hda/patch_analog.c index 2b00c4afdf97..686c77491dea 100644 --- a/sound/pci/hda/patch_analog.c +++ b/sound/pci/hda/patch_analog.c @@ -3860,6 +3860,9 @@ static const char *ad1884a_models[AD1884A_MODELS] = { static struct snd_pci_quirk ad1884a_cfg_tbl[] = { SND_PCI_QUIRK(0x103c, 0x3030, "HP", AD1884A_MOBILE), + SND_PCI_QUIRK(0x103c, 0x3056, "HP", AD1884A_MOBILE), + SND_PCI_QUIRK(0x103c, 0x30e7, "HP EliteBook 8530p", AD1884A_LAPTOP), + SND_PCI_QUIRK(0x103c, 0x3614, "HP 6730s", AD1884A_LAPTOP), SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X300", AD1884A_THINKPAD), {} }; diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index ef4955c73c88..a378c0145125 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -307,6 +307,13 @@ struct alc_spec { /* for PLL fix */ hda_nid_t pll_nid; unsigned int pll_coef_idx, pll_coef_bit; + +#ifdef SND_HDA_NEEDS_RESUME +#define ALC_MAX_PINS 16 + unsigned int num_pins; + hda_nid_t pin_nids[ALC_MAX_PINS]; + unsigned int pin_cfgs[ALC_MAX_PINS]; +#endif }; /* @@ -822,6 +829,7 @@ static void alc_sku_automute(struct hda_codec *codec) spec->jack_present ? 0 : PIN_OUT); } +#if 0 /* it's broken in some acses -- temporarily disabled */ static void alc_mic_automute(struct hda_codec *codec) { struct alc_spec *spec = codec->spec; @@ -842,6 +850,9 @@ static void alc_mic_automute(struct hda_codec *codec) snd_hda_codec_amp_stereo(codec, 0x0b, HDA_INPUT, capsrc_idx_fmic, HDA_AMP_MUTE, present ? HDA_AMP_MUTE : 0); } +#else +#define alc_mic_automute(codec) /* NOP */ +#endif /* disabled */ /* unsolicited event for HP jack sensing */ static void alc_sku_unsol_event(struct hda_codec *codec, unsigned int res) @@ -1051,12 +1062,14 @@ do_sku: AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | ALC880_HP_EVENT); +#if 0 /* it's broken in some acses -- temporarily disabled */ if (spec->autocfg.input_pins[AUTO_PIN_MIC] && spec->autocfg.input_pins[AUTO_PIN_FRONT_MIC]) snd_hda_codec_write(codec, spec->autocfg.input_pins[AUTO_PIN_MIC], 0, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | ALC880_MIC_EVENT); +#endif /* disabled */ spec->unsol_event = alc_sku_unsol_event; } @@ -2778,6 +2791,64 @@ static void alc_free(struct hda_codec *codec) codec->spec = NULL; /* to be sure */ } +#ifdef SND_HDA_NEEDS_RESUME +static void store_pin_configs(struct hda_codec *codec) +{ + struct alc_spec *spec = codec->spec; + hda_nid_t nid, end_nid; + + end_nid = codec->start_nid + codec->num_nodes; + for (nid = codec->start_nid; nid < end_nid; nid++) { + unsigned int wid_caps = get_wcaps(codec, nid); + unsigned int wid_type = + (wid_caps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT; + if (wid_type != AC_WID_PIN) + continue; + if (spec->num_pins >= ARRAY_SIZE(spec->pin_nids)) + break; + spec->pin_nids[spec->num_pins] = nid; + spec->pin_cfgs[spec->num_pins] = + snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_CONFIG_DEFAULT, 0); + spec->num_pins++; + } +} + +static void resume_pin_configs(struct hda_codec *codec) +{ + struct alc_spec *spec = codec->spec; + int i; + + for (i = 0; i < spec->num_pins; i++) { + hda_nid_t pin_nid = spec->pin_nids[i]; + unsigned int pin_config = spec->pin_cfgs[i]; + snd_hda_codec_write(codec, pin_nid, 0, + AC_VERB_SET_CONFIG_DEFAULT_BYTES_0, + pin_config & 0x000000ff); + snd_hda_codec_write(codec, pin_nid, 0, + AC_VERB_SET_CONFIG_DEFAULT_BYTES_1, + (pin_config & 0x0000ff00) >> 8); + snd_hda_codec_write(codec, pin_nid, 0, + AC_VERB_SET_CONFIG_DEFAULT_BYTES_2, + (pin_config & 0x00ff0000) >> 16); + snd_hda_codec_write(codec, pin_nid, 0, + AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, + pin_config >> 24); + } +} + +static int alc_resume(struct hda_codec *codec) +{ + resume_pin_configs(codec); + codec->patch_ops.init(codec); + snd_hda_codec_resume_amp(codec); + snd_hda_codec_resume_cache(codec); + return 0; +} +#else +#define store_pin_configs(codec) +#endif + /* */ static struct hda_codec_ops alc_patch_ops = { @@ -2786,6 +2857,9 @@ static struct hda_codec_ops alc_patch_ops = { .init = alc_init, .free = alc_free, .unsol_event = alc_unsol_event, +#ifdef SND_HDA_NEEDS_RESUME + .resume = alc_resume, +#endif #ifdef CONFIG_SND_HDA_POWER_SAVE .check_power_status = alc_check_power_status, #endif @@ -3832,6 +3906,7 @@ static int alc880_parse_auto_config(struct hda_codec *codec) spec->num_mux_defs = 1; spec->input_mux = &spec->private_imux; + store_pin_configs(codec); return 1; } @@ -5250,6 +5325,7 @@ static int alc260_parse_auto_config(struct hda_codec *codec) } spec->num_mixers++; + store_pin_configs(codec); return 1; } @@ -8338,6 +8414,7 @@ static const char *alc883_models[ALC883_MODEL_LAST] = { static struct snd_pci_quirk alc883_cfg_tbl[] = { SND_PCI_QUIRK(0x1019, 0x6668, "ECS", ALC883_3ST_6ch_DIG), SND_PCI_QUIRK(0x1025, 0x006c, "Acer Aspire 9810", ALC883_ACER_ASPIRE), + SND_PCI_QUIRK(0x1025, 0x0090, "Acer Aspire", ALC883_ACER_ASPIRE), SND_PCI_QUIRK(0x1025, 0x0110, "Acer Aspire", ALC883_ACER_ASPIRE), SND_PCI_QUIRK(0x1025, 0x0112, "Acer Aspire 9303", ALC883_ACER_ASPIRE), SND_PCI_QUIRK(0x1025, 0x0121, "Acer Aspire 5920G", ALC883_ACER_ASPIRE), @@ -8392,6 +8469,7 @@ static struct snd_pci_quirk alc883_cfg_tbl[] = { SND_PCI_QUIRK(0x17aa, 0x3bfd, "Lenovo NB0763", ALC883_LENOVO_NB0763), SND_PCI_QUIRK(0x17aa, 0x101d, "Lenovo Sky", ALC888_LENOVO_SKY), SND_PCI_QUIRK(0x17c0, 0x4071, "MEDION MD2", ALC883_MEDION_MD2), + SND_PCI_QUIRK(0x17c0, 0x4085, "MEDION MD96630", ALC888_LENOVO_MS7195_DIG), SND_PCI_QUIRK(0x17f2, 0x5000, "Albatron KI690-AM2", ALC883_6ST_DIG), SND_PCI_QUIRK(0x1991, 0x5625, "Haier W66", ALC883_HAIER_W66), SND_PCI_QUIRK(0x8086, 0x0001, "DG33BUC", ALC883_3ST_6ch_INTEL), @@ -10313,6 +10391,7 @@ static int alc262_parse_auto_config(struct hda_codec *codec) if (err < 0) return err; + store_pin_configs(codec); return 1; } @@ -11447,6 +11526,7 @@ static int alc268_parse_auto_config(struct hda_codec *codec) if (err < 0) return err; + store_pin_configs(codec); return 1; } @@ -12166,8 +12246,26 @@ static int alc269_auto_create_multi_out_ctls(struct alc_spec *spec, return 0; } -#define alc269_auto_create_analog_input_ctls \ - alc880_auto_create_analog_input_ctls +static int alc269_auto_create_analog_input_ctls(struct alc_spec *spec, + const struct auto_pin_cfg *cfg) +{ + int err; + + err = alc880_auto_create_analog_input_ctls(spec, cfg); + if (err < 0) + return err; + /* digital-mic input pin is excluded in alc880_auto_create..() + * because it's under 0x18 + */ + if (cfg->input_pins[AUTO_PIN_MIC] == 0x12 || + cfg->input_pins[AUTO_PIN_FRONT_MIC] == 0x12) { + struct hda_input_mux *imux = &spec->private_imux; + imux->items[imux->num_items].label = "Int Mic"; + imux->items[imux->num_items].index = 0x05; + imux->num_items++; + } + return 0; +} #ifdef CONFIG_SND_HDA_POWER_SAVE #define alc269_loopbacks alc880_loopbacks @@ -12230,6 +12328,7 @@ static int alc269_parse_auto_config(struct hda_codec *codec) spec->mixers[spec->num_mixers] = alc269_capture_mixer; spec->num_mixers++; + store_pin_configs(codec); return 1; } @@ -13316,6 +13415,7 @@ static int alc861_parse_auto_config(struct hda_codec *codec) spec->mixers[spec->num_mixers] = alc861_capture_mixer; spec->num_mixers++; + store_pin_configs(codec); return 1; } @@ -14427,6 +14527,7 @@ static int alc861vd_parse_auto_config(struct hda_codec *codec) if (err < 0) return err; + store_pin_configs(codec); return 1; } @@ -16258,6 +16359,8 @@ static int alc662_parse_auto_config(struct hda_codec *codec) spec->mixers[spec->num_mixers] = alc662_capture_mixer; spec->num_mixers++; + + store_pin_configs(codec); return 1; } diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 788fdc6f3264..596ceabd6504 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -36,9 +36,11 @@ #include "hda_beep.h" #define NUM_CONTROL_ALLOC 32 + +#define STAC_VREF_EVENT 0x00 +#define STAC_INSERT_EVENT 0x10 #define STAC_PWR_EVENT 0x20 #define STAC_HP_EVENT 0x30 -#define STAC_VREF_EVENT 0x40 enum { STAC_REF, @@ -67,8 +69,12 @@ enum { }; enum { + STAC_92HD73XX_NO_JD, /* no jack-detection */ STAC_92HD73XX_REF, - STAC_DELL_M6, + STAC_DELL_M6_AMIC, + STAC_DELL_M6_DMIC, + STAC_DELL_M6_BOTH, + STAC_DELL_EQ, STAC_92HD73XX_MODELS }; @@ -81,6 +87,7 @@ enum { STAC_92HD71BXX_REF, STAC_DELL_M4_1, STAC_DELL_M4_2, + STAC_DELL_M4_3, STAC_HP_M4, STAC_92HD71BXX_MODELS }; @@ -121,6 +128,7 @@ enum { }; enum { + STAC_D965_REF_NO_JD, /* no jack-detection */ STAC_D965_REF, STAC_D965_3ST, STAC_D965_5ST, @@ -134,6 +142,7 @@ struct sigmatel_spec { unsigned int num_mixers; int board_config; + unsigned int eapd_switch: 1; unsigned int surr_switch: 1; unsigned int line_switch: 1; unsigned int mic_switch: 1; @@ -211,7 +220,7 @@ struct sigmatel_spec { /* i/o switches */ unsigned int io_switch[2]; unsigned int clfe_swap; - unsigned int hp_switch; + unsigned int hp_switch; /* NID of HP as line-out */ unsigned int aloopback; struct hda_pcm pcm_rec[2]; /* PCM information */ @@ -566,10 +575,8 @@ static int stac92xx_smux_enum_put(struct snd_kcontrol *kcontrol, nid = codec->slave_dig_outs[smux_idx - 1]; if (spec->cur_smux[smux_idx] == smux->num_items - 1) val = AMP_OUT_MUTE; - if (smux_idx == 0) - nid = spec->multiout.dig_out_nid; else - nid = codec->slave_dig_outs[smux_idx - 1]; + val = AMP_OUT_UNMUTE; /* un/mute SPDIF out */ snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE, val); @@ -775,9 +782,7 @@ static struct hda_verb dell_eq_core_init[] = { }; static struct hda_verb dell_m6_core_init[] = { - /* set master volume to max value without distortion - * and direct control */ - { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xec}, + { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff}, /* setup audio connections */ { 0x0d, AC_VERB_SET_CONNECT_SEL, 0x00}, { 0x0a, AC_VERB_SET_CONNECT_SEL, 0x01}, @@ -1601,12 +1606,19 @@ static unsigned int dell_m6_pin_configs[13] = { static unsigned int *stac92hd73xx_brd_tbl[STAC_92HD73XX_MODELS] = { [STAC_92HD73XX_REF] = ref92hd73xx_pin_configs, - [STAC_DELL_M6] = dell_m6_pin_configs, + [STAC_DELL_M6_AMIC] = dell_m6_pin_configs, + [STAC_DELL_M6_DMIC] = dell_m6_pin_configs, + [STAC_DELL_M6_BOTH] = dell_m6_pin_configs, + [STAC_DELL_EQ] = dell_m6_pin_configs, }; static const char *stac92hd73xx_models[STAC_92HD73XX_MODELS] = { + [STAC_92HD73XX_NO_JD] = "no-jd", [STAC_92HD73XX_REF] = "ref", - [STAC_DELL_M6] = "dell-m6", + [STAC_DELL_M6_AMIC] = "dell-m6-amic", + [STAC_DELL_M6_DMIC] = "dell-m6-dmic", + [STAC_DELL_M6_BOTH] = "dell-m6", + [STAC_DELL_EQ] = "dell-eq", }; static struct snd_pci_quirk stac92hd73xx_cfg_tbl[] = { @@ -1614,19 +1626,25 @@ static struct snd_pci_quirk stac92hd73xx_cfg_tbl[] = { SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_92HD73XX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0254, - "unknown Dell", STAC_DELL_M6), + "Dell Studio 1535", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0255, - "unknown Dell", STAC_DELL_M6), + "unknown Dell", STAC_DELL_M6_DMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0256, - "unknown Dell", STAC_DELL_M6), + "unknown Dell", STAC_DELL_M6_BOTH), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0257, - "unknown Dell", STAC_DELL_M6), + "unknown Dell", STAC_DELL_M6_BOTH), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x025e, - "unknown Dell", STAC_DELL_M6), + "unknown Dell", STAC_DELL_M6_AMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x025f, - "unknown Dell", STAC_DELL_M6), + "unknown Dell", STAC_DELL_M6_AMIC), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0271, - "unknown Dell", STAC_DELL_M6), + "unknown Dell", STAC_DELL_M6_DMIC), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0272, + "unknown Dell", STAC_DELL_M6_DMIC), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x029f, + "Dell Studio 1537", STAC_DELL_M6_DMIC), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02a0, + "Dell Studio 17", STAC_DELL_M6_DMIC), {} /* terminator */ }; @@ -1669,10 +1687,17 @@ static unsigned int dell_m4_2_pin_configs[11] = { 0x40f000f0, 0x044413b0, 0x044413b0, }; +static unsigned int dell_m4_3_pin_configs[11] = { + 0x0421101f, 0x04a11221, 0x90a70330, 0x90170110, + 0x40f000f0, 0x40f000f0, 0x40f000f0, 0x90a000f0, + 0x40f000f0, 0x044413b0, 0x044413b0, +}; + static unsigned int *stac92hd71bxx_brd_tbl[STAC_92HD71BXX_MODELS] = { [STAC_92HD71BXX_REF] = ref92hd71bxx_pin_configs, [STAC_DELL_M4_1] = dell_m4_1_pin_configs, [STAC_DELL_M4_2] = dell_m4_2_pin_configs, + [STAC_DELL_M4_3] = dell_m4_3_pin_configs, [STAC_HP_M4] = NULL, }; @@ -1680,6 +1705,7 @@ static const char *stac92hd71bxx_models[STAC_92HD71BXX_MODELS] = { [STAC_92HD71BXX_REF] = "ref", [STAC_DELL_M4_1] = "dell-m4-1", [STAC_DELL_M4_2] = "dell-m4-2", + [STAC_DELL_M4_3] = "dell-m4-3", [STAC_HP_M4] = "hp-m4", }; @@ -1687,6 +1713,10 @@ static struct snd_pci_quirk stac92hd71bxx_cfg_tbl[] = { /* SigmaTel reference board */ SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_92HD71BXX_REF), + SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30f2, + "HP dv5", STAC_HP_M4), + SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x30f4, + "HP dv7", STAC_HP_M4), SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x361a, "unknown HP", STAC_HP_M4), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0233, @@ -1711,6 +1741,8 @@ static struct snd_pci_quirk stac92hd71bxx_cfg_tbl[] = { "unknown Dell", STAC_DELL_M4_2), SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0264, "unknown Dell", STAC_DELL_M4_2), + SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02aa, + "unknown Dell", STAC_DELL_M4_3), {} /* terminator */ }; @@ -2000,6 +2032,7 @@ static unsigned int dell_3st_pin_configs[14] = { }; static unsigned int *stac927x_brd_tbl[STAC_927X_MODELS] = { + [STAC_D965_REF_NO_JD] = ref927x_pin_configs, [STAC_D965_REF] = ref927x_pin_configs, [STAC_D965_3ST] = d965_3st_pin_configs, [STAC_D965_5ST] = d965_5st_pin_configs, @@ -2008,6 +2041,7 @@ static unsigned int *stac927x_brd_tbl[STAC_927X_MODELS] = { }; static const char *stac927x_models[STAC_927X_MODELS] = { + [STAC_D965_REF_NO_JD] = "ref-no-jd", [STAC_D965_REF] = "ref", [STAC_D965_3ST] = "3stack", [STAC_D965_5ST] = "5stack", @@ -2444,7 +2478,7 @@ static int stac92xx_hp_switch_get(struct snd_kcontrol *kcontrol, struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; - ucontrol->value.integer.value[0] = spec->hp_switch; + ucontrol->value.integer.value[0] = !!spec->hp_switch; return 0; } @@ -2453,8 +2487,9 @@ static int stac92xx_hp_switch_put(struct snd_kcontrol *kcontrol, { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); struct sigmatel_spec *spec = codec->spec; - - spec->hp_switch = ucontrol->value.integer.value[0]; + int nid = kcontrol->private_value; + + spec->hp_switch = ucontrol->value.integer.value[0] ? nid : 0; /* check to be sure that the ports are upto date with * switch changes @@ -2587,8 +2622,10 @@ static struct snd_kcontrol_new stac92xx_control_templates[] = { }; /* add dynamic controls */ -static int stac92xx_add_control_idx(struct sigmatel_spec *spec, int type, - int idx, const char *name, unsigned long val) +static int stac92xx_add_control_temp(struct sigmatel_spec *spec, + struct snd_kcontrol_new *ktemp, + int idx, const char *name, + unsigned long val) { struct snd_kcontrol_new *knew; @@ -2607,20 +2644,29 @@ static int stac92xx_add_control_idx(struct sigmatel_spec *spec, int type, } knew = &spec->kctl_alloc[spec->num_kctl_used]; - *knew = stac92xx_control_templates[type]; + *knew = *ktemp; knew->index = idx; knew->name = kstrdup(name, GFP_KERNEL); - if (! knew->name) + if (!knew->name) return -ENOMEM; knew->private_value = val; spec->num_kctl_used++; return 0; } +static inline int stac92xx_add_control_idx(struct sigmatel_spec *spec, + int type, int idx, const char *name, + unsigned long val) +{ + return stac92xx_add_control_temp(spec, + &stac92xx_control_templates[type], + idx, name, val); +} + /* add dynamic controls */ -static int stac92xx_add_control(struct sigmatel_spec *spec, int type, - const char *name, unsigned long val) +static inline int stac92xx_add_control(struct sigmatel_spec *spec, int type, + const char *name, unsigned long val) { return stac92xx_add_control_idx(spec, type, 0, name, val); } @@ -2857,13 +2903,14 @@ static int stac92xx_auto_create_multi_out_ctls(struct hda_codec *codec, } if ((spec->multiout.num_dacs - cfg->line_outs) > 0 && - cfg->hp_outs && !spec->multiout.hp_nid) + cfg->hp_outs == 1 && !spec->multiout.hp_nid) spec->multiout.hp_nid = nid; - if (cfg->hp_outs > 1) { + if (cfg->hp_outs > 1 && cfg->line_out_type == AUTO_PIN_LINE_OUT) { err = stac92xx_add_control(spec, STAC_CTL_WIDGET_HP_SWITCH, - "Headphone as Line Out Switch", 0); + "Headphone as Line Out Switch", + cfg->hp_pins[cfg->hp_outs - 1]); if (err < 0) return err; } @@ -3061,6 +3108,43 @@ static int stac92xx_auto_create_beep_ctls(struct hda_codec *codec, return 0; } +#ifdef CONFIG_SND_HDA_INPUT_BEEP +#define stac92xx_dig_beep_switch_info snd_ctl_boolean_mono_info + +static int stac92xx_dig_beep_switch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + ucontrol->value.integer.value[0] = codec->beep->enabled; + return 0; +} + +static int stac92xx_dig_beep_switch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + int enabled = !!ucontrol->value.integer.value[0]; + if (codec->beep->enabled != enabled) { + codec->beep->enabled = enabled; + return 1; + } + return 0; +} + +static struct snd_kcontrol_new stac92xx_dig_beep_ctrl = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .info = stac92xx_dig_beep_switch_info, + .get = stac92xx_dig_beep_switch_get, + .put = stac92xx_dig_beep_switch_put, +}; + +static int stac92xx_beep_switch_ctl(struct hda_codec *codec) +{ + return stac92xx_add_control_temp(codec->spec, &stac92xx_dig_beep_ctrl, + 0, "PC Beep Playback Switch", 0); +} +#endif + static int stac92xx_auto_create_mux_input_ctls(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; @@ -3367,6 +3451,7 @@ static int stac92xx_parse_auto_config(struct hda_codec *codec, hda_nid_t dig_out #ifdef CONFIG_SND_HDA_INPUT_BEEP if (spec->digbeep_nid > 0) { hda_nid_t nid = spec->digbeep_nid; + unsigned int caps; err = stac92xx_auto_create_beep_ctls(codec, nid); if (err < 0) @@ -3374,6 +3459,14 @@ static int stac92xx_parse_auto_config(struct hda_codec *codec, hda_nid_t dig_out err = snd_hda_attach_beep_device(codec, nid); if (err < 0) return err; + /* if no beep switch is available, make its own one */ + caps = query_amp_caps(codec, nid, HDA_OUTPUT); + if (codec->beep && + !((caps & AC_AMPCAP_MUTE) >> AC_AMPCAP_MUTE_SHIFT)) { + err = stac92xx_beep_switch_ctl(codec); + if (err < 0) + return err; + } } #endif @@ -3531,6 +3624,12 @@ static int stac9200_parse_auto_config(struct hda_codec *codec) if ((err = stac9200_auto_create_lfe_ctls(codec, &spec->autocfg)) < 0) return err; + if (spec->num_muxes > 0) { + err = stac92xx_auto_create_mux_input_ctls(codec); + if (err < 0) + return err; + } + if (spec->autocfg.dig_out_pin) spec->multiout.dig_out_nid = 0x05; if (spec->autocfg.dig_in_pin) @@ -3613,10 +3712,14 @@ static void stac92xx_power_down(struct hda_codec *codec) AC_VERB_SET_POWER_STATE, AC_PWRST_D3); } +static void stac_toggle_power_map(struct hda_codec *codec, hda_nid_t nid, + int enable); + static int stac92xx_init(struct hda_codec *codec) { struct sigmatel_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->autocfg; + unsigned int gpio; int i; snd_hda_sequence_write(codec, spec->init); @@ -3627,6 +3730,16 @@ static int stac92xx_init(struct hda_codec *codec) snd_hda_codec_write_cache(codec, spec->adc_nids[i], 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D3); + + /* set up GPIO */ + gpio = spec->gpio_data; + /* turn on EAPD statically when spec->eapd_switch isn't set. + * otherwise, unsol event will turn it on/off dynamically + */ + if (!spec->eapd_switch) + gpio |= spec->eapd_mask; + stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, gpio); + /* set up pins */ if (spec->hp_detect) { /* Enable unsolicited responses on the HP widget */ @@ -3648,53 +3761,61 @@ static int stac92xx_init(struct hda_codec *codec) for (i = 0; i < AUTO_PIN_LAST; i++) { hda_nid_t nid = cfg->input_pins[i]; if (nid) { - unsigned int pinctl = snd_hda_codec_read(codec, nid, - 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); - /* if PINCTL already set then skip */ - if (pinctl & AC_PINCAP_IN) - continue; - pinctl = AC_PINCTL_IN_EN; - if (i == AUTO_PIN_MIC || i == AUTO_PIN_FRONT_MIC) - pinctl |= stac92xx_get_vref(codec, nid); + unsigned int pinctl; + if (i == AUTO_PIN_MIC || i == AUTO_PIN_FRONT_MIC) { + /* for mic pins, force to initialize */ + pinctl = stac92xx_get_vref(codec, nid); + } else { + pinctl = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_PIN_WIDGET_CONTROL, 0); + /* if PINCTL already set then skip */ + if (pinctl & AC_PINCTL_IN_EN) + continue; + } + pinctl |= AC_PINCTL_IN_EN; stac92xx_auto_set_pinctl(codec, nid, pinctl); } } for (i = 0; i < spec->num_dmics; i++) stac92xx_auto_set_pinctl(codec, spec->dmic_nids[i], AC_PINCTL_IN_EN); + if (cfg->dig_out_pin) + stac92xx_auto_set_pinctl(codec, cfg->dig_out_pin, + AC_PINCTL_OUT_EN); + if (cfg->dig_in_pin) + stac92xx_auto_set_pinctl(codec, cfg->dig_in_pin, + AC_PINCTL_IN_EN); for (i = 0; i < spec->num_pwrs; i++) { - int event = is_nid_hp_pin(cfg, spec->pwr_nids[i]) - ? STAC_HP_EVENT : STAC_PWR_EVENT; - int pinctl = snd_hda_codec_read(codec, spec->pwr_nids[i], - 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); - int def_conf = snd_hda_codec_read(codec, spec->pwr_nids[i], - 0, AC_VERB_GET_CONFIG_DEFAULT, 0); - def_conf = get_defcfg_connect(def_conf); + hda_nid_t nid = spec->pwr_nids[i]; + int pinctl, def_conf; + int event = STAC_PWR_EVENT; + + if (is_nid_hp_pin(cfg, nid) && spec->hp_detect) + continue; /* already has an unsol event */ + + pinctl = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_PIN_WIDGET_CONTROL, 0); /* outputs are only ports capable of power management * any attempts on powering down a input port cause the * referenced VREF to act quirky. */ if (pinctl & AC_PINCTL_IN_EN) continue; + def_conf = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_CONFIG_DEFAULT, 0); + def_conf = get_defcfg_connect(def_conf); /* skip any ports that don't have jacks since presence * detection is useless */ - if (def_conf && def_conf != AC_JACK_PORT_FIXED) + if (def_conf != AC_JACK_PORT_COMPLEX) { + if (def_conf != AC_JACK_PORT_NONE) + stac_toggle_power_map(codec, nid, 1); continue; + } enable_pin_detect(codec, spec->pwr_nids[i], event | i); codec->patch_ops.unsol_event(codec, (event | i) << 26); } if (spec->dac_list) stac92xx_power_down(codec); - if (cfg->dig_out_pin) - stac92xx_auto_set_pinctl(codec, cfg->dig_out_pin, - AC_PINCTL_OUT_EN); - if (cfg->dig_in_pin) - stac92xx_auto_set_pinctl(codec, cfg->dig_in_pin, - AC_PINCTL_IN_EN); - - stac_gpio_set(codec, spec->gpio_mask, - spec->gpio_dir, spec->gpio_data); - return 0; } @@ -3777,11 +3898,30 @@ static int get_hp_pin_presence(struct hda_codec *codec, hda_nid_t nid) return 0; } +/* return non-zero if the hp-pin of the given array index isn't + * a jack-detection target + */ +static int no_hp_sensing(struct sigmatel_spec *spec, int i) +{ + struct auto_pin_cfg *cfg = &spec->autocfg; + + /* ignore sensing of shared line and mic jacks */ + if (spec->line_switch && + cfg->hp_pins[i] == cfg->input_pins[AUTO_PIN_LINE]) + return 1; + if (spec->mic_switch && + cfg->hp_pins[i] == cfg->input_pins[AUTO_PIN_MIC]) + return 1; + /* ignore if the pin is set as line-out */ + if (cfg->hp_pins[i] == spec->hp_switch) + return 1; + return 0; +} + static void stac92xx_hp_detect(struct hda_codec *codec, unsigned int res) { struct sigmatel_spec *spec = codec->spec; struct auto_pin_cfg *cfg = &spec->autocfg; - int nid = cfg->hp_pins[cfg->hp_outs - 1]; int i, presence; presence = 0; @@ -3792,52 +3932,66 @@ static void stac92xx_hp_detect(struct hda_codec *codec, unsigned int res) for (i = 0; i < cfg->hp_outs; i++) { if (presence) break; - if (spec->hp_switch && cfg->hp_pins[i] == nid) - break; + if (no_hp_sensing(spec, i)) + continue; presence = get_hp_pin_presence(codec, cfg->hp_pins[i]); } if (presence) { - /* disable lineouts, enable hp */ + /* disable lineouts */ if (spec->hp_switch) - stac92xx_reset_pinctl(codec, nid, AC_PINCTL_OUT_EN); + stac92xx_reset_pinctl(codec, spec->hp_switch, + AC_PINCTL_OUT_EN); for (i = 0; i < cfg->line_outs; i++) stac92xx_reset_pinctl(codec, cfg->line_out_pins[i], AC_PINCTL_OUT_EN); for (i = 0; i < cfg->speaker_outs; i++) stac92xx_reset_pinctl(codec, cfg->speaker_pins[i], AC_PINCTL_OUT_EN); - if (spec->eapd_mask) + if (spec->eapd_mask && spec->eapd_switch) stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data & ~spec->eapd_mask); } else { - /* enable lineouts, disable hp */ + /* enable lineouts */ if (spec->hp_switch) - stac92xx_set_pinctl(codec, nid, AC_PINCTL_OUT_EN); + stac92xx_set_pinctl(codec, spec->hp_switch, + AC_PINCTL_OUT_EN); for (i = 0; i < cfg->line_outs; i++) stac92xx_set_pinctl(codec, cfg->line_out_pins[i], AC_PINCTL_OUT_EN); for (i = 0; i < cfg->speaker_outs; i++) stac92xx_set_pinctl(codec, cfg->speaker_pins[i], AC_PINCTL_OUT_EN); - if (spec->eapd_mask) + if (spec->eapd_mask && spec->eapd_switch) stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data | spec->eapd_mask); } - if (!spec->hp_switch && cfg->hp_outs > 1 && presence) - stac92xx_set_pinctl(codec, nid, AC_PINCTL_OUT_EN); + /* toggle hp outs */ + for (i = 0; i < cfg->hp_outs; i++) { + unsigned int val = AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN; + if (no_hp_sensing(spec, i)) + continue; + if (presence) + stac92xx_set_pinctl(codec, cfg->hp_pins[i], val); + else + stac92xx_reset_pinctl(codec, cfg->hp_pins[i], val); + } } -static void stac92xx_pin_sense(struct hda_codec *codec, int idx) +static void stac_toggle_power_map(struct hda_codec *codec, hda_nid_t nid, + int enable) { struct sigmatel_spec *spec = codec->spec; - hda_nid_t nid = spec->pwr_nids[idx]; - int presence, val; - val = snd_hda_codec_read(codec, codec->afg, 0, 0x0fec, 0x0) - & 0x000000ff; - presence = get_hp_pin_presence(codec, nid); + unsigned int idx, val; + + for (idx = 0; idx < spec->num_pwrs; idx++) { + if (spec->pwr_nids[idx] == nid) + break; + } + if (idx >= spec->num_pwrs) + return; /* several codecs have two power down bits */ if (spec->pwr_mapping) @@ -3845,14 +3999,20 @@ static void stac92xx_pin_sense(struct hda_codec *codec, int idx) else idx = 1 << idx; - if (presence) + val = snd_hda_codec_read(codec, codec->afg, 0, 0x0fec, 0x0) & 0xff; + if (enable) val &= ~idx; else val |= idx; /* power down unused output ports */ snd_hda_codec_write(codec, codec->afg, 0, 0x7ec, val); -}; +} + +static void stac92xx_pin_sense(struct hda_codec *codec, hda_nid_t nid) +{ + stac_toggle_power_map(codec, nid, get_hp_pin_presence(codec, nid)); +} static void stac92xx_unsol_event(struct hda_codec *codec, unsigned int res) { @@ -4101,14 +4261,17 @@ again: switch (spec->multiout.num_dacs) { case 0x3: /* 6 Channel */ + spec->multiout.hp_nid = 0x17; spec->mixer = stac92hd73xx_6ch_mixer; spec->init = stac92hd73xx_6ch_core_init; break; case 0x4: /* 8 Channel */ + spec->multiout.hp_nid = 0x18; spec->mixer = stac92hd73xx_8ch_mixer; spec->init = stac92hd73xx_8ch_core_init; break; case 0x5: /* 10 Channel */ + spec->multiout.hp_nid = 0x19; spec->mixer = stac92hd73xx_10ch_mixer; spec->init = stac92hd73xx_10ch_core_init; }; @@ -4133,31 +4296,33 @@ again: sizeof(stac92hd73xx_dmux)); switch (spec->board_config) { - case STAC_DELL_M6: + case STAC_DELL_EQ: spec->init = dell_eq_core_init; + /* fallthru */ + case STAC_DELL_M6_AMIC: + case STAC_DELL_M6_DMIC: + case STAC_DELL_M6_BOTH: spec->num_smuxes = 0; spec->mixer = &stac92hd73xx_6ch_mixer[DELL_M6_MIXER]; spec->amp_nids = &stac92hd73xx_amp_nids[DELL_M6_AMP]; + spec->eapd_switch = 0; spec->num_amps = 1; - switch (codec->subsystem_id) { - case 0x1028025e: /* Analog Mics */ - case 0x1028025f: + spec->multiout.hp_nid = 0; /* dual HPs */ + + if (!spec->init) + spec->init = dell_m6_core_init; + switch (spec->board_config) { + case STAC_DELL_M6_AMIC: /* Analog Mics */ stac92xx_set_config_reg(codec, 0x0b, 0x90A70170); spec->num_dmics = 0; spec->private_dimux.num_items = 1; break; - case 0x10280271: /* Digital Mics */ - case 0x10280272: - spec->init = dell_m6_core_init; - /* fall-through */ - case 0x10280254: - case 0x10280255: + case STAC_DELL_M6_DMIC: /* Digital Mics */ stac92xx_set_config_reg(codec, 0x13, 0x90A60160); spec->num_dmics = 1; spec->private_dimux.num_items = 2; break; - case 0x10280256: /* Both */ - case 0x10280057: + case STAC_DELL_M6_BOTH: /* Both */ stac92xx_set_config_reg(codec, 0x0b, 0x90A70170); stac92xx_set_config_reg(codec, 0x13, 0x90A60160); spec->num_dmics = 1; @@ -4168,6 +4333,7 @@ again: default: spec->num_dmics = STAC92HD73XX_NUM_DMICS; spec->num_smuxes = ARRAY_SIZE(stac92hd73xx_smux_nids); + spec->eapd_switch = 1; } if (spec->board_config > STAC_92HD73XX_REF) { /* GPIO0 High = Enable EAPD */ @@ -4196,6 +4362,9 @@ again: return err; } + if (spec->board_config == STAC_92HD73XX_NO_JD) + spec->hp_detect = 0; + codec->patch_ops = stac92xx_patch_ops; return 0; @@ -4313,7 +4482,13 @@ static int stac92hd71xx_resume(struct hda_codec *codec) static int stac92hd71xx_suspend(struct hda_codec *codec, pm_message_t state) { + struct sigmatel_spec *spec = codec->spec; + stac92hd71xx_set_power_state(codec, AC_PWRST_D3); + if (spec->eapd_mask) + stac_gpio_set(codec, spec->gpio_mask, + spec->gpio_dir, spec->gpio_data & + ~spec->eapd_mask); return 0; }; @@ -4376,6 +4551,13 @@ again: stac92xx_set_config_regs(codec); } + if (spec->board_config > STAC_92HD71BXX_REF) { + /* GPIO0 = EAPD */ + spec->gpio_mask = 0x01; + spec->gpio_dir = 0x01; + spec->gpio_data = 0x01; + } + switch (codec->vendor_id) { case 0x111d76b6: /* 4 Port without Analog Mixer */ case 0x111d76b7: @@ -4386,10 +4568,10 @@ again: codec->slave_dig_outs = stac92hd71bxx_slave_dig_outs; break; case 0x111d7608: /* 5 Port with Analog Mixer */ - switch (codec->subsystem_id) { - case 0x103c361a: + switch (spec->board_config) { + case STAC_HP_M4: /* Enable VREF power saving on GPIO1 detect */ - snd_hda_codec_write(codec, codec->afg, 0, + snd_hda_codec_write_cache(codec, codec->afg, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 0x02); snd_hda_codec_write_cache(codec, codec->afg, 0, AC_VERB_SET_UNSOLICITED_ENABLE, @@ -4435,13 +4617,6 @@ again: spec->aloopback_mask = 0x50; spec->aloopback_shift = 0; - if (spec->board_config > STAC_92HD71BXX_REF) { - /* GPIO0 = EAPD */ - spec->gpio_mask = 0x01; - spec->gpio_dir = 0x01; - spec->gpio_data = 0x01; - } - spec->powerdown_adcs = 1; spec->digbeep_nid = 0x26; spec->mux_nids = stac92hd71bxx_mux_nids; @@ -4456,14 +4631,21 @@ again: switch (spec->board_config) { case STAC_HP_M4: - spec->num_dmics = 0; - spec->num_smuxes = 0; - spec->num_dmuxes = 0; - /* enable internal microphone */ stac92xx_set_config_reg(codec, 0x0e, 0x01813040); stac92xx_auto_set_pinctl(codec, 0x0e, AC_PINCTL_IN_EN | AC_PINCTL_VREF_80); + /* fallthru */ + case STAC_DELL_M4_2: + spec->num_dmics = 0; + spec->num_smuxes = 0; + spec->num_dmuxes = 0; + break; + case STAC_DELL_M4_1: + case STAC_DELL_M4_3: + spec->num_dmics = 1; + spec->num_smuxes = 0; + spec->num_dmuxes = 0; break; default: spec->num_dmics = STAC92HD71BXX_NUM_DMICS; @@ -4700,6 +4882,7 @@ static int patch_stac927x(struct hda_codec *codec) spec->num_pwrs = 0; spec->aloopback_mask = 0x40; spec->aloopback_shift = 0; + spec->eapd_switch = 1; err = stac92xx_parse_auto_config(codec, 0x1e, 0x20); if (!err) { @@ -4730,6 +4913,10 @@ static int patch_stac927x(struct hda_codec *codec) */ codec->bus->needs_damn_long_delay = 1; + /* no jack detecion for ref-no-jd model */ + if (spec->board_config == STAC_D965_REF_NO_JD) + spec->hp_detect = 0; + return 0; } @@ -4780,6 +4967,7 @@ static int patch_stac9205(struct hda_codec *codec) spec->aloopback_mask = 0x40; spec->aloopback_shift = 0; + spec->eapd_switch = 1; spec->multiout.dac_nids = spec->dac_nids; switch (spec->board_config){ @@ -4789,7 +4977,7 @@ static int patch_stac9205(struct hda_codec *codec) stac92xx_set_config_reg(codec, 0x20, 0x1c410030); /* Enable unsol response for GPIO4/Dock HP connection */ - snd_hda_codec_write(codec, codec->afg, 0, + snd_hda_codec_write_cache(codec, codec->afg, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 0x10); snd_hda_codec_write_cache(codec, codec->afg, 0, AC_VERB_SET_UNSOLICITED_ENABLE, diff --git a/sound/pci/ice1712/ice1712.c b/sound/pci/ice1712/ice1712.c index 5b442383fcda..58d7cda03de5 100644 --- a/sound/pci/ice1712/ice1712.c +++ b/sound/pci/ice1712/ice1712.c @@ -2688,12 +2688,13 @@ static int __devinit snd_ice1712_probe(struct pci_dev *pci, return err; } - if (ice_has_con_ac97(ice)) + if (ice_has_con_ac97(ice)) { err = snd_ice1712_pcm(ice, pcm_dev++, NULL); if (err < 0) { snd_card_free(card); return err; } + } err = snd_ice1712_ac97_mixer(ice); if (err < 0) { @@ -2715,12 +2716,13 @@ static int __devinit snd_ice1712_probe(struct pci_dev *pci, } } - if (ice_has_con_ac97(ice)) + if (ice_has_con_ac97(ice)) { err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL); if (err < 0) { snd_card_free(card); return err; } + } if (!c->no_mpu401) { err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712, diff --git a/sound/pci/intel8x0.c b/sound/pci/intel8x0.c index c88d1eace1c4..19d3391e229f 100644 --- a/sound/pci/intel8x0.c +++ b/sound/pci/intel8x0.c @@ -2702,6 +2702,7 @@ static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = { SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), + SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), { } /* terminator */ }; diff --git a/sound/pci/mixart/mixart.c b/sound/pci/mixart/mixart.c index 2d0dce649a64..ae7601f353a7 100644 --- a/sound/pci/mixart/mixart.c +++ b/sound/pci/mixart/mixart.c @@ -1314,8 +1314,7 @@ static int __devinit snd_mixart_probe(struct pci_dev *pci, } for (i = 0; i < 2; i++) { mgr->mem[i].phys = pci_resource_start(pci, i); - mgr->mem[i].virt = ioremap_nocache(mgr->mem[i].phys, - pci_resource_len(pci, i)); + mgr->mem[i].virt = pci_ioremap_bar(pci, i); if (!mgr->mem[i].virt) { printk(KERN_ERR "unable to remap resource 0x%lx\n", mgr->mem[i].phys); diff --git a/sound/pci/pcxhr/pcxhr.c b/sound/pci/pcxhr/pcxhr.c index 0e06c6c9fcc0..73de6e989b3d 100644 --- a/sound/pci/pcxhr/pcxhr.c +++ b/sound/pci/pcxhr/pcxhr.c @@ -1229,8 +1229,11 @@ static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id return -ENOMEM; } - if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) + if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) { + kfree(mgr); + pci_disable_device(pci); return -ENODEV; + } card_name = pcxhr_board_params[pci_id->driver_data].board_name; mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips; mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips; diff --git a/sound/pci/rme9652/hdsp.c b/sound/pci/rme9652/hdsp.c index d723543beadd..736246f98acc 100644 --- a/sound/pci/rme9652/hdsp.c +++ b/sound/pci/rme9652/hdsp.c @@ -4548,11 +4548,20 @@ static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigne { struct hdsp *hdsp = (struct hdsp *)hw->private_data; void __user *argp = (void __user *)arg; + int err; switch (cmd) { case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; + err = hdsp_check_for_iobox(hdsp); + if (err < 0) + return err; + + err = hdsp_check_for_firmware(hdsp, 1); + if (err < 0) + return err; + if (!(hdsp->state & HDSP_FirmwareLoaded)) { snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); return -EINVAL; @@ -4572,10 +4581,14 @@ static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigne unsigned long flags; int i; - if (!(hdsp->state & HDSP_FirmwareLoaded)) { - snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n"); - return -EINVAL; - } + err = hdsp_check_for_iobox(hdsp); + if (err < 0) + return err; + + err = hdsp_check_for_firmware(hdsp, 1); + if (err < 0) + return err; + spin_lock_irqsave(&hdsp->lock, flags); info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); @@ -5045,6 +5058,10 @@ static int __devinit snd_hdsp_create(struct snd_card *card, /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */ ssleep(2); + err = hdsp_check_for_iobox(hdsp); + if (err < 0) + return err; + if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { #ifdef HDSP_FW_LOADER if ((err = hdsp_request_fw_loader(hdsp)) < 0) @@ -5057,7 +5074,7 @@ static int __devinit snd_hdsp_create(struct snd_card *card, /* init is complete, we return */ return 0; #endif - /* no iobox connected, we defer initialization */ + /* we defer initialization */ snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n"); if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) return err; diff --git a/sound/soc/blackfin/bf5xx-i2s.c b/sound/soc/blackfin/bf5xx-i2s.c index 827587f08180..e020c160ee44 100644 --- a/sound/soc/blackfin/bf5xx-i2s.c +++ b/sound/soc/blackfin/bf5xx-i2s.c @@ -70,12 +70,24 @@ static struct sport_param sport_params[2] = { } }; -static u16 sport_req[][7] = { - { P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0}, - { P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0}, -}; +/* + * Setting the TFS pin selector for SPORT 0 based on whether the selected + * port id F or G. If the port is F then no conflict should exist for the + * TFS. When Port G is selected and EMAC then there is a conflict between + * the PHY interrupt line and TFS. Current settings prevent the conflict + * by ignoring the TFS pin when Port G is selected. This allows both + * ssm2602 using Port G and EMAC concurrently. + */ +#ifdef CONFIG_BF527_SPORT0_PORTF +#define LOCAL_SPORT0_TFS (P_SPORT0_TFS) +#else +#define LOCAL_SPORT0_TFS (0) +#endif + +static u16 sport_req[][7] = { {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, LOCAL_SPORT0_TFS, 0}, + {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, P_SPORT1_DRPRI, + P_SPORT1_RSCLK, P_SPORT1_TFS, 0} }; static int bf5xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) @@ -98,23 +110,21 @@ static int bf5xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, ret = -EINVAL; break; default: + printk(KERN_ERR "%s: Unknown DAI format type\n", __func__); ret = -EINVAL; break; } switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBS_CFS: - ret = -EINVAL; - break; - case SND_SOC_DAIFMT_CBM_CFS: - ret = -EINVAL; - break; case SND_SOC_DAIFMT_CBM_CFM: break; + case SND_SOC_DAIFMT_CBS_CFS: + case SND_SOC_DAIFMT_CBM_CFS: case SND_SOC_DAIFMT_CBS_CFM: ret = -EINVAL; break; default: + printk(KERN_ERR "%s: Unknown DAI master type\n", __func__); ret = -EINVAL; break; } diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c index aba402b3c999..945b32ed9884 100644 --- a/sound/soc/codecs/wm9713.c +++ b/sound/soc/codecs/wm9713.c @@ -140,7 +140,7 @@ SOC_SINGLE("Capture ADC Boost (+20dB) Switch", AC97_VIDEO, 6, 1, 0), SOC_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0), SOC_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0), -SOC_SINGLE("ALC Decay Time ", AC97_CODEC_CLASS_REV, 4, 15, 0), +SOC_SINGLE("ALC Decay Time", AC97_CODEC_CLASS_REV, 4, 15, 0), SOC_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0), SOC_ENUM("ALC Function", wm9713_enum[6]), SOC_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 0), diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index bba9546ba5f5..8d73edc56102 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -20,7 +20,8 @@ config SND_SOC_MPC8610_HPCD config SND_SOC_MPC5200_I2S tristate "Freescale MPC5200 PSC in I2S mode driver" + depends on SND_SOC && PPC_MPC52xx && PPC_BESTCOMM select SND_SOC_OF_SIMPLE - depends on SND_SOC && PPC_MPC52xx + select PPC_BESTCOMM_GEN_BD help Say Y here to support the MPC5200 PSCs in I2S mode. diff --git a/sound/soc/fsl/mpc5200_psc_i2s.c b/sound/soc/fsl/mpc5200_psc_i2s.c index 86923299bc10..94a02eaa4825 100644 --- a/sound/soc/fsl/mpc5200_psc_i2s.c +++ b/sound/soc/fsl/mpc5200_psc_i2s.c @@ -277,7 +277,7 @@ static int psc_i2s_trigger(struct snd_pcm_substream *substream, int cmd) struct mpc52xx_psc __iomem *regs = psc_i2s->psc_regs; u16 imr; u8 psc_cmd; - long flags; + unsigned long flags; if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) s = &psc_i2s->capture; @@ -699,9 +699,11 @@ static ssize_t psc_i2s_stat_store(struct device *dev, return count; } -DEVICE_ATTR(status, 0644, psc_i2s_status_show, NULL); -DEVICE_ATTR(playback_underrun, 0644, psc_i2s_stat_show, psc_i2s_stat_store); -DEVICE_ATTR(capture_overrun, 0644, psc_i2s_stat_show, psc_i2s_stat_store); +static DEVICE_ATTR(status, 0644, psc_i2s_status_show, NULL); +static DEVICE_ATTR(playback_underrun, 0644, psc_i2s_stat_show, + psc_i2s_stat_store); +static DEVICE_ATTR(capture_overrun, 0644, psc_i2s_stat_show, + psc_i2s_stat_store); /* --------------------------------------------------------------------- * OF platform bus binding code: @@ -819,8 +821,8 @@ static int __devinit psc_i2s_of_probe(struct of_device *op, /* Register the SYSFS files */ rc = device_create_file(psc_i2s->dev, &dev_attr_status); - rc = device_create_file(psc_i2s->dev, &dev_attr_capture_overrun); - rc = device_create_file(psc_i2s->dev, &dev_attr_playback_underrun); + rc |= device_create_file(psc_i2s->dev, &dev_attr_capture_overrun); + rc |= device_create_file(psc_i2s->dev, &dev_attr_playback_underrun); if (rc) dev_info(psc_i2s->dev, "error creating sysfs files\n"); diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c index e9084fdd2082..acd68efb2b75 100644 --- a/sound/soc/omap/omap-pcm.c +++ b/sound/soc/omap/omap-pcm.c @@ -233,7 +233,7 @@ static int omap_pcm_open(struct snd_pcm_substream *substream) if (ret < 0) goto out; - prtd = kzalloc(sizeof(prtd), GFP_KERNEL); + prtd = kzalloc(sizeof(*prtd), GFP_KERNEL); if (prtd == NULL) { ret = -ENOMEM; goto out; diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 462e635dfc74..16c7453f4946 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -95,8 +95,8 @@ static int soc_ac97_dev_register(struct snd_soc_codec *codec) codec->ac97->dev.parent = NULL; codec->ac97->dev.release = soc_ac97_device_release; - snprintf(codec->ac97->dev.bus_id, BUS_ID_SIZE, "%d-%d:%s", - codec->card->number, 0, codec->name); + dev_set_name(&codec->ac97->dev, "%d-%d:%s", + codec->card->number, 0, codec->name); err = device_register(&codec->ac97->dev); if (err < 0) { snd_printk(KERN_ERR "Can't register ac97 bus\n"); @@ -1462,7 +1462,7 @@ int snd_soc_info_volsw(struct snd_kcontrol *kcontrol, struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; int max = mc->max; - unsigned int shift = mc->min; + unsigned int shift = mc->shift; unsigned int rshift = mc->rshift; if (max == 1) diff --git a/sound/sound_core.c b/sound/sound_core.c index faef87a9bc3f..10ba4218161b 100644 --- a/sound/sound_core.c +++ b/sound/sound_core.c @@ -57,7 +57,7 @@ module_exit(cleanup_soundcore); /* * OSS sound core handling. Breaks out sound functions to submodules * - * Author: Alan Cox + * Author: Alan Cox * * Fixes: * @@ -457,7 +457,7 @@ EXPORT_SYMBOL(unregister_sound_mixer); void unregister_sound_midi(int unit) { - return sound_remove_unit(&chains[2], unit); + sound_remove_unit(&chains[2], unit); } EXPORT_SYMBOL(unregister_sound_midi); @@ -474,7 +474,7 @@ EXPORT_SYMBOL(unregister_sound_midi); void unregister_sound_dsp(int unit) { - return sound_remove_unit(&chains[3], unit); + sound_remove_unit(&chains[3], unit); } @@ -507,7 +507,7 @@ static struct sound_unit *__look_for_unit(int chain, int unit) return NULL; } -int soundcore_open(struct inode *inode, struct file *file) +static int soundcore_open(struct inode *inode, struct file *file) { int chain; int unit = iminor(inode); diff --git a/sound/sparc/dbri.c b/sound/sparc/dbri.c index c257ad8bdfbc..23ed6f04a718 100644 --- a/sound/sparc/dbri.c +++ b/sound/sparc/dbri.c @@ -2534,6 +2534,8 @@ static int __devinit snd_dbri_create(struct snd_card *card, dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma), &dbri->dma_dvma, GFP_ATOMIC); + if (!dbri->dma) + return -ENOMEM; memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n", diff --git a/sound/usb/usbquirks.h b/sound/usb/usbquirks.h index 69689e79bf79..92115755d98e 100644 --- a/sound/usb/usbquirks.h +++ b/sound/usb/usbquirks.h @@ -1480,6 +1480,36 @@ YAMAHA_DEVICE(0x7010, "UB99"), } } }, +{ + /* Advanced modes of the Edirol UA-25EX. + * For the standard mode, UA-25EX has ID 0582:00e7, which + * offers only 16-bit PCM at 44.1 kHz and no MIDI. + */ + USB_DEVICE_VENDOR_SPEC(0x0582, 0x00e6), + .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) { + .vendor_name = "EDIROL", + .product_name = "UA-25EX", + .ifnum = QUIRK_ANY_INTERFACE, + .type = QUIRK_COMPOSITE, + .data = (const struct snd_usb_audio_quirk[]) { + { + .ifnum = 0, + .type = QUIRK_AUDIO_EDIROL_UAXX + }, + { + .ifnum = 1, + .type = QUIRK_AUDIO_EDIROL_UAXX + }, + { + .ifnum = 2, + .type = QUIRK_AUDIO_EDIROL_UAXX + }, + { + .ifnum = -1 + } + } + } +}, /* Guillemot devices */ { diff --git a/virt/kvm/irq_comm.c b/virt/kvm/irq_comm.c index d0169f5e6047..55ad76ee2d09 100644 --- a/virt/kvm/irq_comm.c +++ b/virt/kvm/irq_comm.c @@ -25,15 +25,23 @@ #include "ioapic.h" /* This should be called with the kvm->lock mutex held */ -void kvm_set_irq(struct kvm *kvm, int irq, int level) +void kvm_set_irq(struct kvm *kvm, int irq_source_id, int irq, int level) { + unsigned long *irq_state = (unsigned long *)&kvm->arch.irq_states[irq]; + + /* Logical OR for level trig interrupt */ + if (level) + set_bit(irq_source_id, irq_state); + else + clear_bit(irq_source_id, irq_state); + /* Not possible to detect if the guest uses the PIC or the * IOAPIC. So set the bit in both. The guest will ignore * writes to the unused one. */ - kvm_ioapic_set_irq(kvm->arch.vioapic, irq, level); + kvm_ioapic_set_irq(kvm->arch.vioapic, irq, !!(*irq_state)); #ifdef CONFIG_X86 - kvm_pic_set_irq(pic_irqchip(kvm), irq, level); + kvm_pic_set_irq(pic_irqchip(kvm), irq, !!(*irq_state)); #endif } @@ -58,3 +66,31 @@ void kvm_unregister_irq_ack_notifier(struct kvm *kvm, { hlist_del(&kian->link); } + +/* The caller must hold kvm->lock mutex */ +int kvm_request_irq_source_id(struct kvm *kvm) +{ + unsigned long *bitmap = &kvm->arch.irq_sources_bitmap; + int irq_source_id = find_first_zero_bit(bitmap, + sizeof(kvm->arch.irq_sources_bitmap)); + if (irq_source_id >= sizeof(kvm->arch.irq_sources_bitmap)) { + printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n"); + irq_source_id = -EFAULT; + } else + set_bit(irq_source_id, bitmap); + return irq_source_id; +} + +void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id) +{ + int i; + + if (irq_source_id <= 0 || + irq_source_id >= sizeof(kvm->arch.irq_sources_bitmap)) { + printk(KERN_ERR "kvm: IRQ source ID out of range!\n"); + return; + } + for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) + clear_bit(irq_source_id, &kvm->arch.irq_states[i]); + clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap); +} diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index cf0ab8ed3845..a87f45edfae8 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -105,14 +105,12 @@ static void kvm_assigned_dev_interrupt_work_handler(struct work_struct *work) */ mutex_lock(&assigned_dev->kvm->lock); kvm_set_irq(assigned_dev->kvm, + assigned_dev->irq_source_id, assigned_dev->guest_irq, 1); mutex_unlock(&assigned_dev->kvm->lock); kvm_put_kvm(assigned_dev->kvm); } -/* FIXME: Implement the OR logic needed to make shared interrupts on - * this line behave properly - */ static irqreturn_t kvm_assigned_dev_intr(int irq, void *dev_id) { struct kvm_assigned_dev_kernel *assigned_dev = @@ -134,7 +132,7 @@ static void kvm_assigned_dev_ack_irq(struct kvm_irq_ack_notifier *kian) dev = container_of(kian, struct kvm_assigned_dev_kernel, ack_notifier); - kvm_set_irq(dev->kvm, dev->guest_irq, 0); + kvm_set_irq(dev->kvm, dev->irq_source_id, dev->guest_irq, 0); enable_irq(dev->host_irq); } @@ -146,6 +144,7 @@ static void kvm_free_assigned_device(struct kvm *kvm, free_irq(assigned_dev->host_irq, (void *)assigned_dev); kvm_unregister_irq_ack_notifier(kvm, &assigned_dev->ack_notifier); + kvm_free_irq_source_id(kvm, assigned_dev->irq_source_id); if (cancel_work_sync(&assigned_dev->interrupt_work)) /* We had pending work. That means we will have to take @@ -215,6 +214,11 @@ static int kvm_vm_ioctl_assign_irq(struct kvm *kvm, match->ack_notifier.gsi = assigned_irq->guest_irq; match->ack_notifier.irq_acked = kvm_assigned_dev_ack_irq; kvm_register_irq_ack_notifier(kvm, &match->ack_notifier); + r = kvm_request_irq_source_id(kvm); + if (r < 0) + goto out_release; + else + match->irq_source_id = r; /* Even though this is PCI, we don't want to use shared * interrupts. Sharing host devices with guest-assigned devices